2 * CAN bus driver for Bosch M_CAN controller
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 * Dong Aisheng <b29396@freescale.com>
7 * Bosch M_CAN user manual can be obtained from:
8 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
9 * mcan_users_manual_v302.pdf
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/netdevice.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
27 #include <linux/can/dev.h>
30 #define M_CAN_NAPI_WEIGHT 64
32 /* message ram configuration data length */
33 #define MRAM_CFG_LEN 8
35 /* registers definition */
85 /* m_can lec values */
108 /* Test Register (TEST) */
109 #define TEST_LBCK BIT(4)
111 /* CC Control Register(CCCR) */
112 #define CCCR_TEST BIT(7)
113 #define CCCR_MON BIT(5)
114 #define CCCR_CCE BIT(1)
115 #define CCCR_INIT BIT(0)
117 /* Bit Timing & Prescaler Register (BTP) */
118 #define BTR_BRP_MASK 0x3ff
119 #define BTR_BRP_SHIFT 16
120 #define BTR_TSEG1_SHIFT 8
121 #define BTR_TSEG1_MASK (0x3f << BTR_TSEG1_SHIFT)
122 #define BTR_TSEG2_SHIFT 4
123 #define BTR_TSEG2_MASK (0xf << BTR_TSEG2_SHIFT)
124 #define BTR_SJW_SHIFT 0
125 #define BTR_SJW_MASK 0xf
127 /* Error Counter Register(ECR) */
128 #define ECR_RP BIT(15)
129 #define ECR_REC_SHIFT 8
130 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT)
131 #define ECR_TEC_SHIFT 0
132 #define ECR_TEC_MASK 0xff
134 /* Protocol Status Register(PSR) */
135 #define PSR_BO BIT(7)
136 #define PSR_EW BIT(6)
137 #define PSR_EP BIT(5)
138 #define PSR_LEC_MASK 0x7
140 /* Interrupt Register(IR) */
141 #define IR_ALL_INT 0xffffffff
142 #define IR_STE BIT(31)
143 #define IR_FOE BIT(30)
144 #define IR_ACKE BIT(29)
145 #define IR_BE BIT(28)
146 #define IR_CRCE BIT(27)
147 #define IR_WDI BIT(26)
148 #define IR_BO BIT(25)
149 #define IR_EW BIT(24)
150 #define IR_EP BIT(23)
151 #define IR_ELO BIT(22)
152 #define IR_BEU BIT(21)
153 #define IR_BEC BIT(20)
154 #define IR_DRX BIT(19)
155 #define IR_TOO BIT(18)
156 #define IR_MRAF BIT(17)
157 #define IR_TSW BIT(16)
158 #define IR_TEFL BIT(15)
159 #define IR_TEFF BIT(14)
160 #define IR_TEFW BIT(13)
161 #define IR_TEFN BIT(12)
162 #define IR_TFE BIT(11)
163 #define IR_TCF BIT(10)
165 #define IR_HPM BIT(8)
166 #define IR_RF1L BIT(7)
167 #define IR_RF1F BIT(6)
168 #define IR_RF1W BIT(5)
169 #define IR_RF1N BIT(4)
170 #define IR_RF0L BIT(3)
171 #define IR_RF0F BIT(2)
172 #define IR_RF0W BIT(1)
173 #define IR_RF0N BIT(0)
174 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
175 #define IR_ERR_LEC (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
176 #define IR_ERR_BUS (IR_ERR_LEC | IR_WDI | IR_ELO | IR_BEU | \
177 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
179 #define IR_ERR_ALL (IR_ERR_STATE | IR_ERR_BUS)
181 /* Interrupt Line Select (ILS) */
182 #define ILS_ALL_INT0 0x0
183 #define ILS_ALL_INT1 0xFFFFFFFF
185 /* Interrupt Line Enable (ILE) */
186 #define ILE_EINT0 BIT(0)
187 #define ILE_EINT1 BIT(1)
189 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
190 #define RXFC_FWM_OFF 24
191 #define RXFC_FWM_MASK 0x7f
192 #define RXFC_FWM_1 (1 << RXFC_FWM_OFF)
193 #define RXFC_FS_OFF 16
194 #define RXFC_FS_MASK 0x7f
196 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
197 #define RXFS_RFL BIT(25)
198 #define RXFS_FF BIT(24)
199 #define RXFS_FPI_OFF 16
200 #define RXFS_FPI_MASK 0x3f0000
201 #define RXFS_FGI_OFF 8
202 #define RXFS_FGI_MASK 0x3f00
203 #define RXFS_FFL_MASK 0x7f
205 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
206 #define M_CAN_RXESC_8BYTES 0x0
208 /* Tx Buffer Configuration(TXBC) */
209 #define TXBC_NDTB_OFF 16
210 #define TXBC_NDTB_MASK 0x3f
212 /* Tx Buffer Element Size Configuration(TXESC) */
213 #define TXESC_TBDS_8BYTES 0x0
215 /* Tx Event FIFO Con.guration (TXEFC) */
216 #define TXEFC_EFS_OFF 16
217 #define TXEFC_EFS_MASK 0x3f
219 /* Message RAM Configuration (in bytes) */
220 #define SIDF_ELEMENT_SIZE 4
221 #define XIDF_ELEMENT_SIZE 8
222 #define RXF0_ELEMENT_SIZE 16
223 #define RXF1_ELEMENT_SIZE 16
224 #define RXB_ELEMENT_SIZE 16
225 #define TXE_ELEMENT_SIZE 8
226 #define TXB_ELEMENT_SIZE 16
228 /* Message RAM Elements */
229 #define M_CAN_FIFO_ID 0x0
230 #define M_CAN_FIFO_DLC 0x4
231 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2))
233 /* Rx Buffer Element */
234 #define RX_BUF_ESI BIT(31)
235 #define RX_BUF_XTD BIT(30)
236 #define RX_BUF_RTR BIT(29)
238 /* Tx Buffer Element */
239 #define TX_BUF_XTD BIT(30)
240 #define TX_BUF_RTR BIT(29)
242 /* address offset and element number for each FIFO/Buffer in the Message RAM */
248 /* m_can private data structure */
250 struct can_priv can; /* must be the first member */
251 struct napi_struct napi;
252 struct net_device *dev;
253 struct device *device;
259 /* message ram configuration */
260 void __iomem *mram_base;
261 struct mram_cfg mcfg[MRAM_CFG_NUM];
264 static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg)
266 return readl(priv->base + reg);
269 static inline void m_can_write(const struct m_can_priv *priv,
270 enum m_can_reg reg, u32 val)
272 writel(val, priv->base + reg);
275 static inline u32 m_can_fifo_read(const struct m_can_priv *priv,
276 u32 fgi, unsigned int offset)
278 return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off +
279 fgi * RXF0_ELEMENT_SIZE + offset);
282 static inline void m_can_fifo_write(const struct m_can_priv *priv,
283 u32 fpi, unsigned int offset, u32 val)
285 return writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off +
286 fpi * TXB_ELEMENT_SIZE + offset);
289 static inline void m_can_config_endisable(const struct m_can_priv *priv,
292 u32 cccr = m_can_read(priv, M_CAN_CCCR);
297 /* enable m_can configuration */
298 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT);
299 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
300 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
302 m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
305 /* there's a delay for module initialization */
307 val = CCCR_INIT | CCCR_CCE;
309 while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
311 netdev_warn(priv->dev, "Failed to init module\n");
319 static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv)
321 m_can_write(priv, M_CAN_ILE, ILE_EINT0 | ILE_EINT1);
324 static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv)
326 m_can_write(priv, M_CAN_ILE, 0x0);
329 static void m_can_read_fifo(const struct net_device *dev, struct can_frame *cf,
332 struct m_can_priv *priv = netdev_priv(dev);
335 /* calculate the fifo get index for where to read data */
336 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_OFF;
337 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID);
339 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
341 cf->can_id = (id >> 18) & CAN_SFF_MASK;
343 if (id & RX_BUF_RTR) {
344 cf->can_id |= CAN_RTR_FLAG;
346 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
347 cf->can_dlc = get_can_dlc((id >> 16) & 0x0F);
348 *(u32 *)(cf->data + 0) = m_can_fifo_read(priv, fgi,
350 *(u32 *)(cf->data + 4) = m_can_fifo_read(priv, fgi,
354 /* acknowledge rx fifo 0 */
355 m_can_write(priv, M_CAN_RXF0A, fgi);
358 static int m_can_do_rx_poll(struct net_device *dev, int quota)
360 struct m_can_priv *priv = netdev_priv(dev);
361 struct net_device_stats *stats = &dev->stats;
363 struct can_frame *frame;
367 rxfs = m_can_read(priv, M_CAN_RXF0S);
368 if (!(rxfs & RXFS_FFL_MASK)) {
369 netdev_dbg(dev, "no messages in fifo0\n");
373 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
375 netdev_warn(dev, "Rx FIFO 0 Message Lost\n");
377 skb = alloc_can_skb(dev, &frame);
383 m_can_read_fifo(dev, frame, rxfs);
386 stats->rx_bytes += frame->can_dlc;
388 netif_receive_skb(skb);
392 rxfs = m_can_read(priv, M_CAN_RXF0S);
396 can_led_event(dev, CAN_LED_EVENT_RX);
401 static int m_can_handle_lost_msg(struct net_device *dev)
403 struct net_device_stats *stats = &dev->stats;
405 struct can_frame *frame;
407 netdev_err(dev, "msg lost in rxf0\n");
410 stats->rx_over_errors++;
412 skb = alloc_can_err_skb(dev, &frame);
416 frame->can_id |= CAN_ERR_CRTL;
417 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
419 netif_receive_skb(skb);
424 static int m_can_handle_lec_err(struct net_device *dev,
425 enum m_can_lec_type lec_type)
427 struct m_can_priv *priv = netdev_priv(dev);
428 struct net_device_stats *stats = &dev->stats;
429 struct can_frame *cf;
432 priv->can.can_stats.bus_error++;
435 /* propagate the error condition to the CAN stack */
436 skb = alloc_can_err_skb(dev, &cf);
440 /* check for 'last error code' which tells us the
441 * type of the last error to occur on the CAN bus
443 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
444 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
447 case LEC_STUFF_ERROR:
448 netdev_dbg(dev, "stuff error\n");
449 cf->data[2] |= CAN_ERR_PROT_STUFF;
452 netdev_dbg(dev, "form error\n");
453 cf->data[2] |= CAN_ERR_PROT_FORM;
456 netdev_dbg(dev, "ack error\n");
457 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
458 CAN_ERR_PROT_LOC_ACK_DEL);
461 netdev_dbg(dev, "bit1 error\n");
462 cf->data[2] |= CAN_ERR_PROT_BIT1;
465 netdev_dbg(dev, "bit0 error\n");
466 cf->data[2] |= CAN_ERR_PROT_BIT0;
469 netdev_dbg(dev, "CRC error\n");
470 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
471 CAN_ERR_PROT_LOC_CRC_DEL);
478 stats->rx_bytes += cf->can_dlc;
479 netif_receive_skb(skb);
484 static int __m_can_get_berr_counter(const struct net_device *dev,
485 struct can_berr_counter *bec)
487 struct m_can_priv *priv = netdev_priv(dev);
490 ecr = m_can_read(priv, M_CAN_ECR);
491 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
492 bec->txerr = ecr & ECR_TEC_MASK;
497 static int m_can_get_berr_counter(const struct net_device *dev,
498 struct can_berr_counter *bec)
500 struct m_can_priv *priv = netdev_priv(dev);
503 err = clk_prepare_enable(priv->hclk);
507 err = clk_prepare_enable(priv->cclk);
509 clk_disable_unprepare(priv->hclk);
513 __m_can_get_berr_counter(dev, bec);
515 clk_disable_unprepare(priv->cclk);
516 clk_disable_unprepare(priv->hclk);
521 static int m_can_handle_state_change(struct net_device *dev,
522 enum can_state new_state)
524 struct m_can_priv *priv = netdev_priv(dev);
525 struct net_device_stats *stats = &dev->stats;
526 struct can_frame *cf;
528 struct can_berr_counter bec;
532 case CAN_STATE_ERROR_ACTIVE:
533 /* error warning state */
534 priv->can.can_stats.error_warning++;
535 priv->can.state = CAN_STATE_ERROR_WARNING;
537 case CAN_STATE_ERROR_PASSIVE:
538 /* error passive state */
539 priv->can.can_stats.error_passive++;
540 priv->can.state = CAN_STATE_ERROR_PASSIVE;
542 case CAN_STATE_BUS_OFF:
544 priv->can.state = CAN_STATE_BUS_OFF;
545 m_can_disable_all_interrupts(priv);
552 /* propagate the error condition to the CAN stack */
553 skb = alloc_can_err_skb(dev, &cf);
557 __m_can_get_berr_counter(dev, &bec);
560 case CAN_STATE_ERROR_ACTIVE:
561 /* error warning state */
562 cf->can_id |= CAN_ERR_CRTL;
563 cf->data[1] = (bec.txerr > bec.rxerr) ?
564 CAN_ERR_CRTL_TX_WARNING :
565 CAN_ERR_CRTL_RX_WARNING;
566 cf->data[6] = bec.txerr;
567 cf->data[7] = bec.rxerr;
569 case CAN_STATE_ERROR_PASSIVE:
570 /* error passive state */
571 cf->can_id |= CAN_ERR_CRTL;
572 ecr = m_can_read(priv, M_CAN_ECR);
574 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
576 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
577 cf->data[6] = bec.txerr;
578 cf->data[7] = bec.rxerr;
580 case CAN_STATE_BUS_OFF:
582 cf->can_id |= CAN_ERR_BUSOFF;
589 stats->rx_bytes += cf->can_dlc;
590 netif_receive_skb(skb);
595 static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
597 struct m_can_priv *priv = netdev_priv(dev);
600 if ((psr & PSR_EW) &&
601 (priv->can.state != CAN_STATE_ERROR_WARNING)) {
602 netdev_dbg(dev, "entered error warning state\n");
603 work_done += m_can_handle_state_change(dev,
604 CAN_STATE_ERROR_WARNING);
607 if ((psr & PSR_EP) &&
608 (priv->can.state != CAN_STATE_ERROR_PASSIVE)) {
609 netdev_dbg(dev, "entered error warning state\n");
610 work_done += m_can_handle_state_change(dev,
611 CAN_STATE_ERROR_PASSIVE);
614 if ((psr & PSR_BO) &&
615 (priv->can.state != CAN_STATE_BUS_OFF)) {
616 netdev_dbg(dev, "entered error warning state\n");
617 work_done += m_can_handle_state_change(dev,
624 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
626 if (irqstatus & IR_WDI)
627 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
628 if (irqstatus & IR_BEU)
629 netdev_err(dev, "Error Logging Overflow\n");
630 if (irqstatus & IR_BEU)
631 netdev_err(dev, "Bit Error Uncorrected\n");
632 if (irqstatus & IR_BEC)
633 netdev_err(dev, "Bit Error Corrected\n");
634 if (irqstatus & IR_TOO)
635 netdev_err(dev, "Timeout reached\n");
636 if (irqstatus & IR_MRAF)
637 netdev_err(dev, "Message RAM access failure occurred\n");
640 static inline bool is_lec_err(u32 psr)
644 return psr && (psr != LEC_UNUSED);
647 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
650 struct m_can_priv *priv = netdev_priv(dev);
653 if (irqstatus & IR_RF0L)
654 work_done += m_can_handle_lost_msg(dev);
656 /* handle lec errors on the bus */
657 if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
659 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED);
661 /* other unproccessed error interrupts */
662 m_can_handle_other_err(dev, irqstatus);
667 static int m_can_poll(struct napi_struct *napi, int quota)
669 struct net_device *dev = napi->dev;
670 struct m_can_priv *priv = netdev_priv(dev);
674 irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR);
678 psr = m_can_read(priv, M_CAN_PSR);
679 if (irqstatus & IR_ERR_STATE)
680 work_done += m_can_handle_state_errors(dev, psr);
682 if (irqstatus & IR_ERR_BUS)
683 work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
685 if (irqstatus & IR_RF0N)
686 work_done += m_can_do_rx_poll(dev, (quota - work_done));
688 if (work_done < quota) {
690 m_can_enable_all_interrupts(priv);
697 static irqreturn_t m_can_isr(int irq, void *dev_id)
699 struct net_device *dev = (struct net_device *)dev_id;
700 struct m_can_priv *priv = netdev_priv(dev);
701 struct net_device_stats *stats = &dev->stats;
704 ir = m_can_read(priv, M_CAN_IR);
710 m_can_write(priv, M_CAN_IR, ir);
712 /* schedule NAPI in case of
715 * - bus error IRQ and bus error reporting
717 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL)) {
718 priv->irqstatus = ir;
719 m_can_disable_all_interrupts(priv);
720 napi_schedule(&priv->napi);
723 /* transmission complete interrupt */
725 stats->tx_bytes += can_get_echo_skb(dev, 0);
727 can_led_event(dev, CAN_LED_EVENT_TX);
728 netif_wake_queue(dev);
734 static const struct can_bittiming_const m_can_bittiming_const = {
735 .name = KBUILD_MODNAME,
736 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
738 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
746 static int m_can_set_bittiming(struct net_device *dev)
748 struct m_can_priv *priv = netdev_priv(dev);
749 const struct can_bittiming *bt = &priv->can.bittiming;
750 u16 brp, sjw, tseg1, tseg2;
755 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
756 tseg2 = bt->phase_seg2 - 1;
757 reg_btp = (brp << BTR_BRP_SHIFT) | (sjw << BTR_SJW_SHIFT) |
758 (tseg1 << BTR_TSEG1_SHIFT) | (tseg2 << BTR_TSEG2_SHIFT);
759 m_can_write(priv, M_CAN_BTP, reg_btp);
760 netdev_dbg(dev, "setting BTP 0x%x\n", reg_btp);
765 /* Configure M_CAN chip:
766 * - set rx buffer/fifo element size
767 * - configure rx fifo
768 * - accept non-matching frame into fifo 0
769 * - configure tx buffer
773 static void m_can_chip_config(struct net_device *dev)
775 struct m_can_priv *priv = netdev_priv(dev);
778 m_can_config_endisable(priv, true);
780 /* RX Buffer/FIFO Element Size 8 bytes data field */
781 m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_8BYTES);
783 /* Accept Non-matching Frames Into FIFO 0 */
784 m_can_write(priv, M_CAN_GFC, 0x0);
786 /* only support one Tx Buffer currently */
787 m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_OFF) |
788 priv->mcfg[MRAM_TXB].off);
790 /* only support 8 bytes firstly */
791 m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_8BYTES);
793 m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_OFF) |
794 priv->mcfg[MRAM_TXE].off);
796 /* rx fifo configuration, blocking mode, fifo size 1 */
797 m_can_write(priv, M_CAN_RXF0C,
798 (priv->mcfg[MRAM_RXF0].num << RXFC_FS_OFF) |
799 RXFC_FWM_1 | priv->mcfg[MRAM_RXF0].off);
801 m_can_write(priv, M_CAN_RXF1C,
802 (priv->mcfg[MRAM_RXF1].num << RXFC_FS_OFF) |
803 RXFC_FWM_1 | priv->mcfg[MRAM_RXF1].off);
805 cccr = m_can_read(priv, M_CAN_CCCR);
806 cccr &= ~(CCCR_TEST | CCCR_MON);
807 test = m_can_read(priv, M_CAN_TEST);
810 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
813 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
818 m_can_write(priv, M_CAN_CCCR, cccr);
819 m_can_write(priv, M_CAN_TEST, test);
821 /* enable interrupts */
822 m_can_write(priv, M_CAN_IR, IR_ALL_INT);
823 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
824 m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC);
826 m_can_write(priv, M_CAN_IE, IR_ALL_INT);
828 /* route all interrupts to INT0 */
829 m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0);
831 /* set bittiming params */
832 m_can_set_bittiming(dev);
834 m_can_config_endisable(priv, false);
837 static void m_can_start(struct net_device *dev)
839 struct m_can_priv *priv = netdev_priv(dev);
841 /* basic m_can configuration */
842 m_can_chip_config(dev);
844 priv->can.state = CAN_STATE_ERROR_ACTIVE;
846 m_can_enable_all_interrupts(priv);
849 static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
854 netif_wake_queue(dev);
863 static void free_m_can_dev(struct net_device *dev)
868 static struct net_device *alloc_m_can_dev(void)
870 struct net_device *dev;
871 struct m_can_priv *priv;
873 dev = alloc_candev(sizeof(*priv), 1);
877 priv = netdev_priv(dev);
878 netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT);
881 priv->can.bittiming_const = &m_can_bittiming_const;
882 priv->can.do_set_mode = m_can_set_mode;
883 priv->can.do_get_berr_counter = m_can_get_berr_counter;
884 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
885 CAN_CTRLMODE_LISTENONLY |
886 CAN_CTRLMODE_BERR_REPORTING;
891 static int m_can_open(struct net_device *dev)
893 struct m_can_priv *priv = netdev_priv(dev);
896 err = clk_prepare_enable(priv->hclk);
900 err = clk_prepare_enable(priv->cclk);
902 goto exit_disable_hclk;
904 /* open the can device */
905 err = open_candev(dev);
907 netdev_err(dev, "failed to open can device\n");
908 goto exit_disable_cclk;
911 /* register interrupt handler */
912 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
915 netdev_err(dev, "failed to request interrupt\n");
919 /* start the m_can controller */
922 can_led_event(dev, CAN_LED_EVENT_OPEN);
923 napi_enable(&priv->napi);
924 netif_start_queue(dev);
931 clk_disable_unprepare(priv->cclk);
933 clk_disable_unprepare(priv->hclk);
937 static void m_can_stop(struct net_device *dev)
939 struct m_can_priv *priv = netdev_priv(dev);
941 /* disable all interrupts */
942 m_can_disable_all_interrupts(priv);
944 clk_disable_unprepare(priv->hclk);
945 clk_disable_unprepare(priv->cclk);
947 /* set the state as STOPPED */
948 priv->can.state = CAN_STATE_STOPPED;
951 static int m_can_close(struct net_device *dev)
953 struct m_can_priv *priv = netdev_priv(dev);
955 netif_stop_queue(dev);
956 napi_disable(&priv->napi);
958 free_irq(dev->irq, dev);
960 can_led_event(dev, CAN_LED_EVENT_STOP);
965 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
966 struct net_device *dev)
968 struct m_can_priv *priv = netdev_priv(dev);
969 struct can_frame *cf = (struct can_frame *)skb->data;
972 if (can_dropped_invalid_skb(dev, skb))
975 netif_stop_queue(dev);
977 if (cf->can_id & CAN_EFF_FLAG) {
978 id = cf->can_id & CAN_EFF_MASK;
981 id = ((cf->can_id & CAN_SFF_MASK) << 18);
984 if (cf->can_id & CAN_RTR_FLAG)
987 /* message ram configuration */
988 m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
989 m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, cf->can_dlc << 16);
990 m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(0), *(u32 *)(cf->data + 0));
991 m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(1), *(u32 *)(cf->data + 4));
992 can_put_echo_skb(skb, dev, 0);
994 /* enable first TX buffer to start transfer */
995 m_can_write(priv, M_CAN_TXBTIE, 0x1);
996 m_can_write(priv, M_CAN_TXBAR, 0x1);
1001 static const struct net_device_ops m_can_netdev_ops = {
1002 .ndo_open = m_can_open,
1003 .ndo_stop = m_can_close,
1004 .ndo_start_xmit = m_can_start_xmit,
1005 .ndo_change_mtu = can_change_mtu,
1008 static int register_m_can_dev(struct net_device *dev)
1010 dev->flags |= IFF_ECHO; /* we support local echo */
1011 dev->netdev_ops = &m_can_netdev_ops;
1013 return register_candev(dev);
1016 static int m_can_of_parse_mram(struct platform_device *pdev,
1017 struct m_can_priv *priv)
1019 struct device_node *np = pdev->dev.of_node;
1020 struct resource *res;
1022 u32 out_val[MRAM_CFG_LEN];
1023 int i, start, end, ret;
1025 /* message ram could be shared */
1026 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
1030 addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1034 /* get message ram configuration */
1035 ret = of_property_read_u32_array(np, "bosch,mram-cfg",
1036 out_val, sizeof(out_val) / 4);
1038 dev_err(&pdev->dev, "can not get message ram configuration\n");
1042 priv->mram_base = addr;
1043 priv->mcfg[MRAM_SIDF].off = out_val[0];
1044 priv->mcfg[MRAM_SIDF].num = out_val[1];
1045 priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off +
1046 priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
1047 priv->mcfg[MRAM_XIDF].num = out_val[2];
1048 priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
1049 priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
1050 priv->mcfg[MRAM_RXF0].num = out_val[3] & RXFC_FS_MASK;
1051 priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
1052 priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
1053 priv->mcfg[MRAM_RXF1].num = out_val[4] & RXFC_FS_MASK;
1054 priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
1055 priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
1056 priv->mcfg[MRAM_RXB].num = out_val[5];
1057 priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off +
1058 priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
1059 priv->mcfg[MRAM_TXE].num = out_val[6];
1060 priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
1061 priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
1062 priv->mcfg[MRAM_TXB].num = out_val[7] & TXBC_NDTB_MASK;
1064 dev_dbg(&pdev->dev, "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
1066 priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num,
1067 priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num,
1068 priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num,
1069 priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num,
1070 priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num,
1071 priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num,
1072 priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num);
1074 /* initialize the entire Message RAM in use to avoid possible
1075 * ECC/parity checksum errors when reading an uninitialized buffer
1077 start = priv->mcfg[MRAM_SIDF].off;
1078 end = priv->mcfg[MRAM_TXB].off +
1079 priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
1080 for (i = start; i < end; i += 4)
1081 writel(0x0, priv->mram_base + i);
1086 static int m_can_plat_probe(struct platform_device *pdev)
1088 struct net_device *dev;
1089 struct m_can_priv *priv;
1090 struct resource *res;
1092 struct clk *hclk, *cclk;
1095 hclk = devm_clk_get(&pdev->dev, "hclk");
1096 cclk = devm_clk_get(&pdev->dev, "cclk");
1097 if (IS_ERR(hclk) || IS_ERR(cclk)) {
1098 dev_err(&pdev->dev, "no clock find\n");
1102 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
1103 addr = devm_ioremap_resource(&pdev->dev, res);
1104 irq = platform_get_irq_byname(pdev, "int0");
1105 if (IS_ERR(addr) || irq < 0)
1108 /* allocate the m_can device */
1109 dev = alloc_m_can_dev();
1113 priv = netdev_priv(dev);
1116 priv->device = &pdev->dev;
1119 priv->can.clock.freq = clk_get_rate(cclk);
1121 ret = m_can_of_parse_mram(pdev, priv);
1123 goto failed_free_dev;
1125 platform_set_drvdata(pdev, dev);
1126 SET_NETDEV_DEV(dev, &pdev->dev);
1128 ret = register_m_can_dev(dev);
1130 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
1131 KBUILD_MODNAME, ret);
1132 goto failed_free_dev;
1135 devm_can_led_init(dev);
1137 dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
1138 KBUILD_MODNAME, priv->base, dev->irq);
1143 free_m_can_dev(dev);
1147 static __maybe_unused int m_can_suspend(struct device *dev)
1149 struct net_device *ndev = dev_get_drvdata(dev);
1150 struct m_can_priv *priv = netdev_priv(ndev);
1152 if (netif_running(ndev)) {
1153 netif_stop_queue(ndev);
1154 netif_device_detach(ndev);
1157 /* TODO: enter low power */
1159 priv->can.state = CAN_STATE_SLEEPING;
1164 static __maybe_unused int m_can_resume(struct device *dev)
1166 struct net_device *ndev = dev_get_drvdata(dev);
1167 struct m_can_priv *priv = netdev_priv(ndev);
1169 /* TODO: exit low power */
1171 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1173 if (netif_running(ndev)) {
1174 netif_device_attach(ndev);
1175 netif_start_queue(ndev);
1181 static void unregister_m_can_dev(struct net_device *dev)
1183 unregister_candev(dev);
1186 static int m_can_plat_remove(struct platform_device *pdev)
1188 struct net_device *dev = platform_get_drvdata(pdev);
1190 unregister_m_can_dev(dev);
1191 platform_set_drvdata(pdev, NULL);
1193 free_m_can_dev(dev);
1198 static const struct dev_pm_ops m_can_pmops = {
1199 SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
1202 static const struct of_device_id m_can_of_table[] = {
1203 { .compatible = "bosch,m_can", .data = NULL },
1206 MODULE_DEVICE_TABLE(of, m_can_of_table);
1208 static struct platform_driver m_can_plat_driver = {
1210 .name = KBUILD_MODNAME,
1211 .of_match_table = m_can_of_table,
1214 .probe = m_can_plat_probe,
1215 .remove = m_can_plat_remove,
1218 module_platform_driver(m_can_plat_driver);
1220 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
1221 MODULE_LICENSE("GPL v2");
1222 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");