drivers/net/chelsio/suni1x10gexp_regs.h

   1 /*****************************************************************************
   2  *                                                                           *
   3  * File: suni1x10gexp_regs.h                                                 *
   4  * $Revision: 1.4 $                                                          *
   5  * $Date: 2005/03/23 07:15:59 $                                              *
   6  * Description:                                                              *
   7  *  PMC/SIERRA (pm3393) MAC-PHY functionality.                               *
   8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
   9  *                                                                           *
  10  * This program is free software; you can redistribute it and/or modify      *
  11  * it under the terms of the GNU General Public License, version 2, as       *
  12  * published by the Free Software Foundation.                                *
  13  *                                                                           *
  14  * You should have received a copy of the GNU General Public License along   *
  15  * with this program; if not, write to the Free Software Foundation, Inc.,   *
  16  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
  17  *                                                                           *
  18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
  19  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
  20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
  21  *                                                                           *
  22  * http://www.chelsio.com                                                    *
  23  *                                                                           *
  24  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
  25  * All rights reserved.                                                      *
  26  *                                                                           *
  27  * Maintainers: maintainers@chelsio.com                                      *
  28  *                                                                           *
  29  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
  30  *          Tina Yang               <tainay@chelsio.com>                     *
  31  *          Felix Marti             <felix@chelsio.com>                      *
  32  *          Scott Bardone           <sbardone@chelsio.com>                   *
  33  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
  34  *          Frank DiMambro          <frank@chelsio.com>                      *
  35  *                                                                           *
  36  * History:                                                                  *
  37  *                                                                           *
  38  ****************************************************************************/
  39
  40 #ifndef _SUNI1x10GEXP_REGS_H
  41 #define _SUNI1x10GEXP_REGS_H
  42
  43 /******************************************************************************/
  44 /** S/UNI-1x10GE-XP REGISTER ADDRESS MAP                                     **/
  45 /******************************************************************************/
  46 /* Refer to the Register Bit Masks bellow for the naming of each register and */
  47 /* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit        */
  48 /******************************************************************************/
  49
  50 #define SUNI1x10GEXP_REG_DEVICE_STATUS                                   0x0004
  51 #define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS                         0x000D
  52 #define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE                         0x000E
  53 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE                    0x0102
  54 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS                    0x0104
  55 #define SUNI1x10GEXP_REG_RXXG_CONFIG_1                                   0x2040
  56 #define SUNI1x10GEXP_REG_RXXG_CONFIG_3                                   0x2042
  57 #define SUNI1x10GEXP_REG_RXXG_INTERRUPT                                  0x2043
  58 #define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH                           0x2045
  59 #define SUNI1x10GEXP_REG_RXXG_SA_15_0                                    0x2046
  60 #define SUNI1x10GEXP_REG_RXXG_SA_31_16                                   0x2047
  61 #define SUNI1x10GEXP_REG_RXXG_SA_47_32                                   0x2048
  62 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW                     0x204D
  63 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID                     0x204E
  64 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH                    0x204F
  65 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW                         0x206A
  66 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW                      0x206B
  67 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH                     0x206C
  68 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH                        0x206D
  69 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0                   0x206E
  70 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2                   0x2070
  71 #define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE                            0x2088
  72 #define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS                            0x2089
  73 #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE                       0x208B
  74 #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS                       0x208C
  75 #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE                          0x20C7
  76 #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS                          0x20C8
  77 #define SUNI1x10GEXP_REG_MSTAT_CONTROL                                   0x2100
  78 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0                        0x2101
  79 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1                        0x2102
  80 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2                        0x2103
  81 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3                        0x2104
  82 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0                          0x2105
  83 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1                          0x2106
  84 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2                          0x2107
  85 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3                          0x2108
  86 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW                             0x2110
  87 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW                             0x2114
  88 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW                             0x2120
  89 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW                             0x2124
  90 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW                             0x2128
  91 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW                             0x2130
  92 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW                            0x2138
  93 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW                            0x213C
  94 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW                            0x2140
  95 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW                            0x2144
  96 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW                            0x214C
  97 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW                            0x2150
  98 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW                            0x2154
  99 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW                            0x2158
 100 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW                            0x2194
 101 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW                            0x219C
 102 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW                            0x21A0
 103 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW                            0x21A8
 104 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW                            0x21B0
 105 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW                            0x21B8
 106 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW                            0x21BC
 107 #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE                       0x2209
 108 #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT                    0x220A
 109 #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK                           0x2282
 110 #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT                                0x2283
 111 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS                        0x2300
 112 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE                        0x2301
 113 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK                          0x2302
 114 #define SUNI1x10GEXP_REG_TXXG_CONFIG_1                                   0x3040
 115 #define SUNI1x10GEXP_REG_TXXG_CONFIG_3                                   0x3042
 116 #define SUNI1x10GEXP_REG_TXXG_INTERRUPT                                  0x3043
 117 #define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE                             0x3045
 118 #define SUNI1x10GEXP_REG_TXXG_SA_15_0                                    0x3047
 119 #define SUNI1x10GEXP_REG_TXXG_SA_31_16                                   0x3048
 120 #define SUNI1x10GEXP_REG_TXXG_SA_47_32                                   0x3049
 121 #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS                           0x3084
 122 #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE                           0x3085
 123 #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE                          0x30C6
 124 #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS                          0x30C7
 125 #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE                 0x320C
 126 #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION             0x320D
 127 #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK                           0x3282
 128 #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT                                0x3283
 129
 130 /******************************************************************************/
 131 /*                 -- End register offset definitions --                      */
 132 /******************************************************************************/
 133
 134 /******************************************************************************/
 135 /** SUNI-1x10GE-XP REGISTER BIT MASKS                                        **/
 136 /******************************************************************************/
 137
 138 /*----------------------------------------------------------------------------
 139  * Register 0x0004: S/UNI-1x10GE-XP Device Status
 140  *    Bit 9 TOP_SXRA_EXPIRED
 141  *    Bit 8 TOP_MDIO_BUSY
 142  *    Bit 7 TOP_DTRB
 143  *    Bit 6 TOP_EXPIRED
 144  *    Bit 5 TOP_PAUSED
 145  *    Bit 4 TOP_PL4_ID_DOOL
 146  *    Bit 3 TOP_PL4_IS_DOOL
 147  *    Bit 2 TOP_PL4_ID_ROOL
 148  *    Bit 1 TOP_PL4_IS_ROOL
 149  *    Bit 0 TOP_PL4_OUT_ROOL
 150  *----------------------------------------------------------------------------*/
 151 #define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED  0x0200
 152 #define SUNI1x10GEXP_BITMSK_TOP_EXPIRED       0x0040
 153 #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL   0x0010
 154 #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL   0x0008
 155 #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL   0x0004
 156 #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL   0x0002
 157 #define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL  0x0001
 158
 159 /*----------------------------------------------------------------------------
 160  * Register 0x000E:PM3393 Global interrupt enable
 161  *    Bit 15 TOP_INTE
 162  *----------------------------------------------------------------------------*/
 163 #define SUNI1x10GEXP_BITMSK_TOP_INTE  0x8000
 164
 165 /*----------------------------------------------------------------------------
 166  * Register 0x2040: RXXG Configuration 1
 167  *    Bit 15  RXXG_RXEN
 168  *    Bit 14  RXXG_ROCF
 169  *    Bit 13  RXXG_PAD_STRIP
 170  *    Bit 10  RXXG_PUREP
 171  *    Bit 9   RXXG_LONGP
 172  *    Bit 8   RXXG_PARF
 173  *    Bit 7   RXXG_FLCHK
 174  *    Bit 5   RXXG_PASS_CTRL
 175  *    Bit 3   RXXG_CRC_STRIP
 176  *    Bit 2-0 RXXG_MIFG
 177  *----------------------------------------------------------------------------*/
 178 #define SUNI1x10GEXP_BITMSK_RXXG_RXEN       0x8000
 179 #define SUNI1x10GEXP_BITMSK_RXXG_PUREP      0x0400
 180 #define SUNI1x10GEXP_BITMSK_RXXG_FLCHK      0x0080
 181 #define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP  0x0008
 182
 183 /*----------------------------------------------------------------------------
 184  * Register 0x2070: RXXG Address Filter Control 2
 185  *    Bit 1 RXXG_PMODE
 186  *    Bit 0 RXXG_MHASH_EN
 187  *----------------------------------------------------------------------------*/
 188 #define SUNI1x10GEXP_BITMSK_RXXG_PMODE     0x0002
 189 #define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN  0x0001
 190
 191 /*----------------------------------------------------------------------------
 192  * Register 0x2100: MSTAT Control
 193  *    Bit 2 MSTAT_WRITE
 194  *    Bit 1 MSTAT_CLEAR
 195  *    Bit 0 MSTAT_SNAP
 196  *----------------------------------------------------------------------------*/
 197 #define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR  0x0002
 198 #define SUNI1x10GEXP_BITMSK_MSTAT_SNAP   0x0001
 199
 200 /*----------------------------------------------------------------------------
 201  * Register 0x3040: TXXG Configuration Register 1
 202  *    Bit 15   TXXG_TXEN0
 203  *    Bit 13   TXXG_HOSTPAUSE
 204  *    Bit 12-7 TXXG_IPGT
 205  *    Bit 5    TXXG_32BIT_ALIGN
 206  *    Bit 4    TXXG_CRCEN
 207  *    Bit 3    TXXG_FCTX
 208  *    Bit 2    TXXG_FCRX
 209  *    Bit 1    TXXG_PADEN
 210  *    Bit 0    TXXG_SPRE
 211  *----------------------------------------------------------------------------*/
 212 #define SUNI1x10GEXP_BITMSK_TXXG_TXEN0        0x8000
 213 #define SUNI1x10GEXP_BITOFF_TXXG_IPGT         7
 214 #define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN  0x0020
 215 #define SUNI1x10GEXP_BITMSK_TXXG_CRCEN        0x0010
 216 #define SUNI1x10GEXP_BITMSK_TXXG_FCTX         0x0008
 217 #define SUNI1x10GEXP_BITMSK_TXXG_FCRX         0x0004
 218 #define SUNI1x10GEXP_BITMSK_TXXG_PADEN        0x0002
 219
 220 #endif /* _SUNI1x10GEXP_REGS_H */
 221