2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/version.h>
52 #include <linux/spinlock.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/clk.h>
55 #include <linux/platform_device.h>
56 #include <linux/semaphore.h>
57 #include <linux/phy.h>
58 #include <linux/bitops.h>
60 #include <linux/uaccess.h>
61 #include <linux/davinci_emac.h>
66 #include "davinci_cpdma.h"
68 static int debug_level;
69 module_param(debug_level, int, 0);
70 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
72 /* Netif debug messages possible */
73 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
81 NETIF_MSG_TX_QUEUED | \
84 NETIF_MSG_RX_STATUS | \
90 #define EMAC_MAJOR_VERSION 6
91 #define EMAC_MINOR_VERSION 1
92 #define EMAC_MODULE_VERSION "6.1"
93 MODULE_VERSION(EMAC_MODULE_VERSION);
94 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
96 /* Configuration items */
97 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
98 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
99 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
100 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
101 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
102 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
103 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
104 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
105 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
106 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
107 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
108 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
110 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
111 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
113 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
114 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
115 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
116 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
117 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
118 #define EMAC_DEF_RX_NUM_DESC (128)
119 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
120 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
121 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
123 /* Buffer descriptor parameters */
124 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
125 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
127 /* EMAC register related defines */
128 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
129 #define EMAC_NUM_MULTICAST_BITS (64)
130 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
131 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
132 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
133 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
134 #define EMAC_INT_MASK_CLEAR (0xFF)
136 /* RX MBP register bit positions */
137 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
138 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
139 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
140 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
141 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
142 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
143 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
144 #define EMAC_RXMBP_PROMCH_SHIFT (16)
145 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
146 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
147 #define EMAC_RXMBP_BROADCH_SHIFT (8)
148 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
149 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
150 #define EMAC_RXMBP_MULTICH_SHIFT (0)
151 #define EMAC_RXMBP_MULTICH_MASK (0x7)
152 #define EMAC_RXMBP_CHMASK (0x7)
154 /* EMAC register definitions/bit maps used */
155 # define EMAC_MBP_RXPROMISC (0x00200000)
156 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
157 # define EMAC_MBP_RXBCAST (0x00002000)
158 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
159 # define EMAC_MBP_RXMCAST (0x00000020)
160 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
162 /* EMAC mac_control register */
163 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
164 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
165 #define EMAC_MACCONTROL_GMIIEN BIT(5)
166 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
167 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
168 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
170 /* GIGABIT MODE related bits */
171 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
172 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
174 /* EMAC mac_status register */
175 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
176 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
177 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
178 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
179 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
180 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
181 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
182 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
184 /* EMAC RX register masks */
185 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
186 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
188 /* MAC_IN_VECTOR (0x180) register bit fields */
189 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
190 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
191 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
192 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
194 /** NOTE:: For DM646x the IN_VECTOR has changed */
195 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
196 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
197 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
198 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
200 /* CPPI bit positions */
201 #define EMAC_CPPI_SOP_BIT BIT(31)
202 #define EMAC_CPPI_EOP_BIT BIT(30)
203 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
204 #define EMAC_CPPI_EOQ_BIT BIT(28)
205 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
206 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
207 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
208 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
209 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
211 /* Max hardware defines */
212 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
213 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
215 /* EMAC Peripheral Device Register Memory Layout structure */
216 #define EMAC_MACINVECTOR 0x90
218 #define EMAC_DM646X_MACEOIVECTOR 0x94
220 #define EMAC_MACINTSTATRAW 0xB0
221 #define EMAC_MACINTSTATMASKED 0xB4
222 #define EMAC_MACINTMASKSET 0xB8
223 #define EMAC_MACINTMASKCLEAR 0xBC
225 #define EMAC_RXMBPENABLE 0x100
226 #define EMAC_RXUNICASTSET 0x104
227 #define EMAC_RXUNICASTCLEAR 0x108
228 #define EMAC_RXMAXLEN 0x10C
229 #define EMAC_RXBUFFEROFFSET 0x110
230 #define EMAC_RXFILTERLOWTHRESH 0x114
232 #define EMAC_MACCONTROL 0x160
233 #define EMAC_MACSTATUS 0x164
234 #define EMAC_EMCONTROL 0x168
235 #define EMAC_FIFOCONTROL 0x16C
236 #define EMAC_MACCONFIG 0x170
237 #define EMAC_SOFTRESET 0x174
238 #define EMAC_MACSRCADDRLO 0x1D0
239 #define EMAC_MACSRCADDRHI 0x1D4
240 #define EMAC_MACHASH1 0x1D8
241 #define EMAC_MACHASH2 0x1DC
242 #define EMAC_MACADDRLO 0x500
243 #define EMAC_MACADDRHI 0x504
244 #define EMAC_MACINDEX 0x508
246 /* EMAC statistics registers */
247 #define EMAC_RXGOODFRAMES 0x200
248 #define EMAC_RXBCASTFRAMES 0x204
249 #define EMAC_RXMCASTFRAMES 0x208
250 #define EMAC_RXPAUSEFRAMES 0x20C
251 #define EMAC_RXCRCERRORS 0x210
252 #define EMAC_RXALIGNCODEERRORS 0x214
253 #define EMAC_RXOVERSIZED 0x218
254 #define EMAC_RXJABBER 0x21C
255 #define EMAC_RXUNDERSIZED 0x220
256 #define EMAC_RXFRAGMENTS 0x224
257 #define EMAC_RXFILTERED 0x228
258 #define EMAC_RXQOSFILTERED 0x22C
259 #define EMAC_RXOCTETS 0x230
260 #define EMAC_TXGOODFRAMES 0x234
261 #define EMAC_TXBCASTFRAMES 0x238
262 #define EMAC_TXMCASTFRAMES 0x23C
263 #define EMAC_TXPAUSEFRAMES 0x240
264 #define EMAC_TXDEFERRED 0x244
265 #define EMAC_TXCOLLISION 0x248
266 #define EMAC_TXSINGLECOLL 0x24C
267 #define EMAC_TXMULTICOLL 0x250
268 #define EMAC_TXEXCESSIVECOLL 0x254
269 #define EMAC_TXLATECOLL 0x258
270 #define EMAC_TXUNDERRUN 0x25C
271 #define EMAC_TXCARRIERSENSE 0x260
272 #define EMAC_TXOCTETS 0x264
273 #define EMAC_NETOCTETS 0x280
274 #define EMAC_RXSOFOVERRUNS 0x284
275 #define EMAC_RXMOFOVERRUNS 0x288
276 #define EMAC_RXDMAOVERRUNS 0x28C
278 /* EMAC DM644x control registers */
279 #define EMAC_CTRL_EWCTL (0x4)
280 #define EMAC_CTRL_EWINTTCNT (0x8)
282 /* EMAC DM644x control module masks */
283 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
284 #define EMAC_DM644X_INTMIN_INTVL 0x1
285 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
287 /* EMAC DM646X control module registers */
288 #define EMAC_DM646X_CMINTCTRL 0x0C
289 #define EMAC_DM646X_CMRXINTEN 0x14
290 #define EMAC_DM646X_CMTXINTEN 0x18
291 #define EMAC_DM646X_CMRXINTMAX 0x70
292 #define EMAC_DM646X_CMTXINTMAX 0x74
294 /* EMAC DM646X control module masks */
295 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
296 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
297 #define EMAC_DM646X_CMINTMAX_CNT 63
298 #define EMAC_DM646X_CMINTMIN_CNT 2
299 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
300 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
303 /* EMAC EOI codes for C0 */
304 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
305 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
307 /* EMAC Stats Clear Mask */
308 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
310 /* emac_priv: EMAC private data structure
312 * EMAC adapter private data structure
316 struct net_device *ndev;
317 struct platform_device *pdev;
318 struct napi_struct napi;
320 void __iomem *remap_addr;
322 void __iomem *emac_base;
323 void __iomem *ctrl_base;
324 struct cpdma_ctlr *dma;
325 struct cpdma_chan *txchan;
326 struct cpdma_chan *rxchan;
327 u32 link; /* 1=link on, 0=link off */
328 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
329 u32 duplex; /* Link duplex: 0=Half, 1=Full */
338 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
341 struct phy_device *phydev;
343 /*platform specific members*/
344 void (*int_enable) (void);
345 void (*int_disable) (void);
348 /* clock frequency for EMAC */
349 static struct clk *emac_clk;
350 static unsigned long emac_bus_frequency;
352 /* EMAC TX Host Error description strings */
353 static char *emac_txhost_errcodes[16] = {
354 "No error", "SOP error", "Ownership bit not set in SOP buffer",
355 "Zero Next Buffer Descriptor Pointer Without EOP",
356 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
357 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
358 "Reserved", "Reserved", "Reserved", "Reserved"
361 /* EMAC RX Host Error description strings */
362 static char *emac_rxhost_errcodes[16] = {
363 "No error", "Reserved", "Ownership bit not set in input buffer",
364 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
365 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
366 "Reserved", "Reserved", "Reserved", "Reserved"
370 #define emac_read(reg) ioread32(priv->emac_base + (reg))
371 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
373 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
374 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
377 * emac_dump_regs: Dump important EMAC registers to debug terminal
378 * @priv: The DaVinci EMAC private adapter structure
380 * Executes ethtool set cmd & sets phy mode
383 static void emac_dump_regs(struct emac_priv *priv)
385 struct device *emac_dev = &priv->ndev->dev;
387 /* Print important registers in EMAC */
388 dev_info(emac_dev, "EMAC Basic registers\n");
389 if (priv->version == EMAC_VERSION_1) {
390 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
391 emac_ctrl_read(EMAC_CTRL_EWCTL),
392 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
394 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
395 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
396 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
397 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
398 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
399 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
400 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
401 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
402 dev_info(emac_dev, "EMAC Statistics\n");
403 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
404 emac_read(EMAC_RXGOODFRAMES));
405 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
406 emac_read(EMAC_RXBCASTFRAMES));
407 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
408 emac_read(EMAC_RXMCASTFRAMES));
409 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
410 emac_read(EMAC_RXPAUSEFRAMES));
411 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
412 emac_read(EMAC_RXCRCERRORS));
413 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
414 emac_read(EMAC_RXALIGNCODEERRORS));
415 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
416 emac_read(EMAC_RXOVERSIZED));
417 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
418 emac_read(EMAC_RXJABBER));
419 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
420 emac_read(EMAC_RXUNDERSIZED));
421 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
422 emac_read(EMAC_RXFRAGMENTS));
423 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
424 emac_read(EMAC_RXFILTERED));
425 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
426 emac_read(EMAC_RXQOSFILTERED));
427 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
428 emac_read(EMAC_RXOCTETS));
429 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
430 emac_read(EMAC_TXGOODFRAMES));
431 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
432 emac_read(EMAC_TXBCASTFRAMES));
433 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
434 emac_read(EMAC_TXMCASTFRAMES));
435 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
436 emac_read(EMAC_TXPAUSEFRAMES));
437 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
438 emac_read(EMAC_TXDEFERRED));
439 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
440 emac_read(EMAC_TXCOLLISION));
441 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
442 emac_read(EMAC_TXSINGLECOLL));
443 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
444 emac_read(EMAC_TXMULTICOLL));
445 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
446 emac_read(EMAC_TXEXCESSIVECOLL));
447 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
448 emac_read(EMAC_TXLATECOLL));
449 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
450 emac_read(EMAC_TXUNDERRUN));
451 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
452 emac_read(EMAC_TXCARRIERSENSE));
453 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
454 emac_read(EMAC_TXOCTETS));
455 dev_info(emac_dev, "EMAC: net_octets:%d\n",
456 emac_read(EMAC_NETOCTETS));
457 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
458 emac_read(EMAC_RXSOFOVERRUNS));
459 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
460 emac_read(EMAC_RXMOFOVERRUNS));
461 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
462 emac_read(EMAC_RXDMAOVERRUNS));
464 cpdma_ctlr_dump(priv->dma);
468 * emac_get_drvinfo: Get EMAC driver information
469 * @ndev: The DaVinci EMAC network adapter
470 * @info: ethtool info structure containing name and version
472 * Returns EMAC driver information (name and version)
475 static void emac_get_drvinfo(struct net_device *ndev,
476 struct ethtool_drvinfo *info)
478 strcpy(info->driver, emac_version_string);
479 strcpy(info->version, EMAC_MODULE_VERSION);
483 * emac_get_settings: Get EMAC settings
484 * @ndev: The DaVinci EMAC network adapter
485 * @ecmd: ethtool command
487 * Executes ethool get command
490 static int emac_get_settings(struct net_device *ndev,
491 struct ethtool_cmd *ecmd)
493 struct emac_priv *priv = netdev_priv(ndev);
495 return phy_ethtool_gset(priv->phydev, ecmd);
502 * emac_set_settings: Set EMAC settings
503 * @ndev: The DaVinci EMAC network adapter
504 * @ecmd: ethtool command
506 * Executes ethool set command
509 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
511 struct emac_priv *priv = netdev_priv(ndev);
513 return phy_ethtool_sset(priv->phydev, ecmd);
520 * emac_get_coalesce : Get interrupt coalesce settings for this device
521 * @ndev : The DaVinci EMAC network adapter
522 * @coal : ethtool coalesce settings structure
524 * Fetch the current interrupt coalesce settings
527 static int emac_get_coalesce(struct net_device *ndev,
528 struct ethtool_coalesce *coal)
530 struct emac_priv *priv = netdev_priv(ndev);
532 coal->rx_coalesce_usecs = priv->coal_intvl;
538 * emac_set_coalesce : Set interrupt coalesce settings for this device
539 * @ndev : The DaVinci EMAC network adapter
540 * @coal : ethtool coalesce settings structure
542 * Set interrupt coalesce parameters
545 static int emac_set_coalesce(struct net_device *ndev,
546 struct ethtool_coalesce *coal)
548 struct emac_priv *priv = netdev_priv(ndev);
549 u32 int_ctrl, num_interrupts = 0;
550 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
552 if (!coal->rx_coalesce_usecs)
555 coal_intvl = coal->rx_coalesce_usecs;
557 switch (priv->version) {
559 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
560 prescale = priv->bus_freq_mhz * 4;
562 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
563 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
565 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
567 * Interrupt pacer works with 4us Pulse, we can
568 * throttle further by dilating the 4us pulse.
570 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
572 if (addnl_dvdr > 1) {
573 prescale *= addnl_dvdr;
574 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
576 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
580 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
584 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
586 int_ctrl |= EMAC_DM646X_INTPACEEN;
587 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
588 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
589 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
591 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
592 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
596 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
597 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
598 prescale = coal_intvl * priv->bus_freq_mhz;
599 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
600 prescale = EMAC_DM644X_EWINTCNT_MASK;
601 coal_intvl = prescale / priv->bus_freq_mhz;
603 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
608 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
609 priv->coal_intvl = coal_intvl;
617 * ethtool_ops: DaVinci EMAC Ethtool structure
619 * Ethtool support for EMAC adapter
622 static const struct ethtool_ops ethtool_ops = {
623 .get_drvinfo = emac_get_drvinfo,
624 .get_settings = emac_get_settings,
625 .set_settings = emac_set_settings,
626 .get_link = ethtool_op_get_link,
627 .get_coalesce = emac_get_coalesce,
628 .set_coalesce = emac_set_coalesce,
632 * emac_update_phystatus: Update Phy status
633 * @priv: The DaVinci EMAC private adapter structure
635 * Updates phy status and takes action for network queue if required
636 * based upon link status
639 static void emac_update_phystatus(struct emac_priv *priv)
644 struct net_device *ndev = priv->ndev;
646 mac_control = emac_read(EMAC_MACCONTROL);
647 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
648 DUPLEX_FULL : DUPLEX_HALF;
650 new_duplex = priv->phydev->duplex;
652 new_duplex = DUPLEX_FULL;
654 /* We get called only if link has changed (speed/duplex/status) */
655 if ((priv->link) && (new_duplex != cur_duplex)) {
656 priv->duplex = new_duplex;
657 if (DUPLEX_FULL == priv->duplex)
658 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
660 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
663 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
664 mac_control = emac_read(EMAC_MACCONTROL);
665 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
666 EMAC_DM646X_MACCONTORL_GIGFORCE);
668 /* Clear the GIG bit and GIGFORCE bit */
669 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
670 EMAC_DM646X_MACCONTORL_GIG);
672 if (priv->rmii_en && (priv->speed == SPEED_100))
673 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
675 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
678 /* Update mac_control if changed */
679 emac_write(EMAC_MACCONTROL, mac_control);
683 if (!netif_carrier_ok(ndev))
684 netif_carrier_on(ndev);
685 /* reactivate the transmit queue if it is stopped */
686 if (netif_running(ndev) && netif_queue_stopped(ndev))
687 netif_wake_queue(ndev);
690 if (netif_carrier_ok(ndev))
691 netif_carrier_off(ndev);
692 if (!netif_queue_stopped(ndev))
693 netif_stop_queue(ndev);
698 * hash_get: Calculate hash value from mac address
699 * @addr: mac address to delete from hash table
701 * Calculates hash value from mac address
704 static u32 hash_get(u8 *addr)
711 for (cnt = 0; cnt < 2; cnt++) {
713 hash ^= (tmpval >> 2) ^ (tmpval << 4);
715 hash ^= (tmpval >> 4) ^ (tmpval << 2);
717 hash ^= (tmpval >> 6) ^ (tmpval);
724 * hash_add: Hash function to add mac addr from hash table
725 * @priv: The DaVinci EMAC private adapter structure
726 * mac_addr: mac address to delete from hash table
728 * Adds mac address to the internal hash table
731 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
733 struct device *emac_dev = &priv->ndev->dev;
736 u32 hash_value = hash_get(mac_addr);
738 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
739 if (netif_msg_drv(priv)) {
740 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
741 "Hash %08x, should not be greater than %08x",
742 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
747 /* set the hash bit only if not previously set */
748 if (priv->multicast_hash_cnt[hash_value] == 0) {
749 rc = 1; /* hash value changed */
750 if (hash_value < 32) {
751 hash_bit = BIT(hash_value);
752 priv->mac_hash1 |= hash_bit;
754 hash_bit = BIT((hash_value - 32));
755 priv->mac_hash2 |= hash_bit;
759 /* incr counter for num of mcast addr's mapped to "this" hash bit */
760 ++priv->multicast_hash_cnt[hash_value];
766 * hash_del: Hash function to delete mac addr from hash table
767 * @priv: The DaVinci EMAC private adapter structure
768 * mac_addr: mac address to delete from hash table
770 * Removes mac address from the internal hash table
773 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
778 hash_value = hash_get(mac_addr);
779 if (priv->multicast_hash_cnt[hash_value] > 0) {
780 /* dec cntr for num of mcast addr's mapped to this hash bit */
781 --priv->multicast_hash_cnt[hash_value];
784 /* if counter still > 0, at least one multicast address refers
785 * to this hash bit. so return 0 */
786 if (priv->multicast_hash_cnt[hash_value] > 0)
789 if (hash_value < 32) {
790 hash_bit = BIT(hash_value);
791 priv->mac_hash1 &= ~hash_bit;
793 hash_bit = BIT((hash_value - 32));
794 priv->mac_hash2 &= ~hash_bit;
797 /* return 1 to indicate change in mac_hash registers reqd */
801 /* EMAC multicast operation */
802 #define EMAC_MULTICAST_ADD 0
803 #define EMAC_MULTICAST_DEL 1
804 #define EMAC_ALL_MULTI_SET 2
805 #define EMAC_ALL_MULTI_CLR 3
808 * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
809 * @priv: The DaVinci EMAC private adapter structure
810 * @action: multicast operation to perform
811 * mac_addr: mac address to set
813 * Set multicast addresses in EMAC adapter - internal function
816 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
818 struct device *emac_dev = &priv->ndev->dev;
822 case EMAC_MULTICAST_ADD:
823 update = hash_add(priv, mac_addr);
825 case EMAC_MULTICAST_DEL:
826 update = hash_del(priv, mac_addr);
828 case EMAC_ALL_MULTI_SET:
830 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
831 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
833 case EMAC_ALL_MULTI_CLR:
837 memset(&(priv->multicast_hash_cnt[0]), 0,
838 sizeof(priv->multicast_hash_cnt[0]) *
839 EMAC_NUM_MULTICAST_BITS);
842 if (netif_msg_drv(priv))
843 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
844 ": bad operation %d", action);
848 /* write to the hardware only if the register status chances */
850 emac_write(EMAC_MACHASH1, priv->mac_hash1);
851 emac_write(EMAC_MACHASH2, priv->mac_hash2);
856 * emac_dev_mcast_set: Set multicast address in the EMAC adapter
857 * @ndev: The DaVinci EMAC network adapter
859 * Set multicast addresses in EMAC adapter
862 static void emac_dev_mcast_set(struct net_device *ndev)
865 struct emac_priv *priv = netdev_priv(ndev);
867 mbp_enable = emac_read(EMAC_RXMBPENABLE);
868 if (ndev->flags & IFF_PROMISC) {
869 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
870 mbp_enable |= (EMAC_MBP_RXPROMISC);
872 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
873 if ((ndev->flags & IFF_ALLMULTI) ||
874 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
875 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
876 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
878 if (!netdev_mc_empty(ndev)) {
879 struct netdev_hw_addr *ha;
881 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
882 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
883 /* program multicast address list into EMAC hardware */
884 netdev_for_each_mc_addr(ha, ndev) {
885 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
889 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
890 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
893 /* Set mbp config register */
894 emac_write(EMAC_RXMBPENABLE, mbp_enable);
897 /*************************************************************************
898 * EMAC Hardware manipulation
899 *************************************************************************/
902 * emac_int_disable: Disable EMAC module interrupt (from adapter)
903 * @priv: The DaVinci EMAC private adapter structure
905 * Disable EMAC interrupt on the adapter
908 static void emac_int_disable(struct emac_priv *priv)
910 if (priv->version == EMAC_VERSION_2) {
913 local_irq_save(flags);
915 /* Program C0_Int_En to zero to turn off
916 * interrupts to the CPU */
917 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
918 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
919 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
920 if (priv->int_disable)
923 local_irq_restore(flags);
926 /* Set DM644x control registers for interrupt control */
927 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
932 * emac_int_enable: Enable EMAC module interrupt (from adapter)
933 * @priv: The DaVinci EMAC private adapter structure
935 * Enable EMAC interrupt on the adapter
938 static void emac_int_enable(struct emac_priv *priv)
940 if (priv->version == EMAC_VERSION_2) {
941 if (priv->int_enable)
944 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
945 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
947 /* In addition to turning on interrupt Enable, we need
948 * ack by writing appropriate values to the EOI
951 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
953 /* ack rxen only then a new pulse will be generated */
954 emac_write(EMAC_DM646X_MACEOIVECTOR,
955 EMAC_DM646X_MAC_EOI_C0_RXEN);
957 /* ack txen- only then a new pulse will be generated */
958 emac_write(EMAC_DM646X_MACEOIVECTOR,
959 EMAC_DM646X_MAC_EOI_C0_TXEN);
962 /* Set DM644x control registers for interrupt control */
963 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
968 * emac_irq: EMAC interrupt handler
969 * @irq: interrupt number
970 * @dev_id: EMAC network adapter data structure ptr
972 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
973 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
975 * Returns interrupt handled condition
977 static irqreturn_t emac_irq(int irq, void *dev_id)
979 struct net_device *ndev = (struct net_device *)dev_id;
980 struct emac_priv *priv = netdev_priv(ndev);
983 if (likely(netif_running(priv->ndev))) {
984 emac_int_disable(priv);
985 napi_schedule(&priv->napi);
987 /* we are closing down, so dont process anything */
992 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
994 struct sk_buff *skb = dev_alloc_skb(priv->rx_buf_size);
997 skb->dev = priv->ndev;
998 skb_reserve(skb, NET_IP_ALIGN);
1002 static void emac_rx_handler(void *token, int len, int status)
1004 struct sk_buff *skb = token;
1005 struct net_device *ndev = skb->dev;
1006 struct emac_priv *priv = netdev_priv(ndev);
1007 struct device *emac_dev = &ndev->dev;
1010 /* free and bail if we are shutting down */
1011 if (unlikely(!netif_running(ndev))) {
1012 dev_kfree_skb_any(skb);
1016 /* recycle on receive error */
1018 ndev->stats.rx_errors++;
1022 /* feed received packet up the stack */
1024 skb->protocol = eth_type_trans(skb, ndev);
1025 netif_receive_skb(skb);
1026 ndev->stats.rx_bytes += len;
1027 ndev->stats.rx_packets++;
1029 /* alloc a new packet for receive */
1030 skb = emac_rx_alloc(priv);
1032 if (netif_msg_rx_err(priv) && net_ratelimit())
1033 dev_err(emac_dev, "failed rx buffer alloc\n");
1038 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1039 skb_tailroom(skb), GFP_KERNEL);
1041 WARN_ON(ret == -ENOMEM);
1042 if (unlikely(ret < 0))
1043 dev_kfree_skb_any(skb);
1046 static void emac_tx_handler(void *token, int len, int status)
1048 struct sk_buff *skb = token;
1049 struct net_device *ndev = skb->dev;
1051 if (unlikely(netif_queue_stopped(ndev)))
1052 netif_start_queue(ndev);
1053 ndev->stats.tx_packets++;
1054 ndev->stats.tx_bytes += len;
1055 dev_kfree_skb_any(skb);
1059 * emac_dev_xmit: EMAC Transmit function
1061 * @ndev: The DaVinci EMAC network adapter
1063 * Called by the system to transmit a packet - we queue the packet in
1064 * EMAC hardware transmit queue
1066 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1068 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1070 struct device *emac_dev = &ndev->dev;
1072 struct emac_priv *priv = netdev_priv(ndev);
1074 /* If no link, return */
1075 if (unlikely(!priv->link)) {
1076 if (netif_msg_tx_err(priv) && net_ratelimit())
1077 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1081 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1082 if (unlikely(ret_code < 0)) {
1083 if (netif_msg_tx_err(priv) && net_ratelimit())
1084 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1088 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1090 if (unlikely(ret_code != 0)) {
1091 if (netif_msg_tx_err(priv) && net_ratelimit())
1092 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1096 return NETDEV_TX_OK;
1099 ndev->stats.tx_dropped++;
1100 netif_stop_queue(ndev);
1101 return NETDEV_TX_BUSY;
1105 * emac_dev_tx_timeout: EMAC Transmit timeout function
1106 * @ndev: The DaVinci EMAC network adapter
1108 * Called when system detects that a skb timeout period has expired
1109 * potentially due to a fault in the adapter in not being able to send
1110 * it out on the wire. We teardown the TX channel assuming a hardware
1111 * error and re-initialize the TX channel for hardware operation
1114 static void emac_dev_tx_timeout(struct net_device *ndev)
1116 struct emac_priv *priv = netdev_priv(ndev);
1117 struct device *emac_dev = &ndev->dev;
1119 if (netif_msg_tx_err(priv))
1120 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1122 emac_dump_regs(priv);
1124 ndev->stats.tx_errors++;
1125 emac_int_disable(priv);
1126 cpdma_chan_stop(priv->txchan);
1127 cpdma_chan_start(priv->txchan);
1128 emac_int_enable(priv);
1132 * emac_set_type0addr: Set EMAC Type0 mac address
1133 * @priv: The DaVinci EMAC private adapter structure
1134 * @ch: RX channel number
1135 * @mac_addr: MAC address to set in device
1137 * Called internally to set Type0 mac address of the adapter (Device)
1139 * Returns success (0) or appropriate error code (none as of now)
1141 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1144 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1145 emac_write(EMAC_MACSRCADDRLO, val);
1147 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1148 (mac_addr[1] << 8) | (mac_addr[0]));
1149 emac_write(EMAC_MACSRCADDRHI, val);
1150 val = emac_read(EMAC_RXUNICASTSET);
1152 emac_write(EMAC_RXUNICASTSET, val);
1153 val = emac_read(EMAC_RXUNICASTCLEAR);
1155 emac_write(EMAC_RXUNICASTCLEAR, val);
1159 * emac_set_type1addr: Set EMAC Type1 mac address
1160 * @priv: The DaVinci EMAC private adapter structure
1161 * @ch: RX channel number
1162 * @mac_addr: MAC address to set in device
1164 * Called internally to set Type1 mac address of the adapter (Device)
1166 * Returns success (0) or appropriate error code (none as of now)
1168 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1171 emac_write(EMAC_MACINDEX, ch);
1172 val = ((mac_addr[5] << 8) | mac_addr[4]);
1173 emac_write(EMAC_MACADDRLO, val);
1174 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1175 (mac_addr[1] << 8) | (mac_addr[0]));
1176 emac_write(EMAC_MACADDRHI, val);
1177 emac_set_type0addr(priv, ch, mac_addr);
1181 * emac_set_type2addr: Set EMAC Type2 mac address
1182 * @priv: The DaVinci EMAC private adapter structure
1183 * @ch: RX channel number
1184 * @mac_addr: MAC address to set in device
1185 * @index: index into RX address entries
1186 * @match: match parameter for RX address matching logic
1188 * Called internally to set Type2 mac address of the adapter (Device)
1190 * Returns success (0) or appropriate error code (none as of now)
1192 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1193 char *mac_addr, int index, int match)
1196 emac_write(EMAC_MACINDEX, index);
1197 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1198 (mac_addr[1] << 8) | (mac_addr[0]));
1199 emac_write(EMAC_MACADDRHI, val);
1200 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1201 (match << 19) | BIT(20));
1202 emac_write(EMAC_MACADDRLO, val);
1203 emac_set_type0addr(priv, ch, mac_addr);
1207 * emac_setmac: Set mac address in the adapter (internal function)
1208 * @priv: The DaVinci EMAC private adapter structure
1209 * @ch: RX channel number
1210 * @mac_addr: MAC address to set in device
1212 * Called internally to set the mac address of the adapter (Device)
1214 * Returns success (0) or appropriate error code (none as of now)
1216 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1218 struct device *emac_dev = &priv->ndev->dev;
1220 if (priv->rx_addr_type == 0) {
1221 emac_set_type0addr(priv, ch, mac_addr);
1222 } else if (priv->rx_addr_type == 1) {
1224 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1225 emac_set_type1addr(priv, ch, mac_addr);
1226 } else if (priv->rx_addr_type == 2) {
1227 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1228 emac_set_type0addr(priv, ch, mac_addr);
1230 if (netif_msg_drv(priv))
1231 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1236 * emac_dev_setmac_addr: Set mac address in the adapter
1237 * @ndev: The DaVinci EMAC network adapter
1238 * @addr: MAC address to set in device
1240 * Called by the system to set the mac address of the adapter (Device)
1242 * Returns success (0) or appropriate error code (none as of now)
1244 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1246 struct emac_priv *priv = netdev_priv(ndev);
1247 struct device *emac_dev = &priv->ndev->dev;
1248 struct sockaddr *sa = addr;
1250 if (!is_valid_ether_addr(sa->sa_data))
1253 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1254 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1255 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1257 /* MAC address is configured only after the interface is enabled. */
1258 if (netif_running(ndev)) {
1259 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1260 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1263 if (netif_msg_drv(priv))
1264 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1271 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
1272 * @priv: The DaVinci EMAC private adapter structure
1274 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1275 * for packet reception and enables device interrupts and then NAPI
1277 * Returns success (0) or appropriate error code (none right now)
1279 static int emac_hw_enable(struct emac_priv *priv)
1281 u32 val, mbp_enable, mac_control;
1284 emac_write(EMAC_SOFTRESET, 1);
1285 while (emac_read(EMAC_SOFTRESET))
1288 /* Disable interrupt & Set pacing for more interrupts initially */
1289 emac_int_disable(priv);
1291 /* Full duplex enable bit set when auto negotiation happens */
1293 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1294 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1295 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1296 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1297 emac_write(EMAC_MACCONTROL, mac_control);
1300 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1301 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1302 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1303 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1304 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1305 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1306 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1307 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1308 EMAC_RXMBP_PROMCH_SHIFT) |
1309 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1310 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1311 EMAC_RXMBP_BROADCH_SHIFT) |
1312 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1313 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1314 EMAC_RXMBP_MULTICH_SHIFT));
1315 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1316 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1317 EMAC_RX_MAX_LEN_MASK));
1318 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1319 EMAC_RX_BUFFER_OFFSET_MASK));
1320 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1321 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1322 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1324 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1326 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1329 val = emac_read(EMAC_MACCONTROL);
1330 val |= (EMAC_MACCONTROL_GMIIEN);
1331 emac_write(EMAC_MACCONTROL, val);
1333 /* Enable NAPI and interrupts */
1334 napi_enable(&priv->napi);
1335 emac_int_enable(priv);
1341 * emac_poll: EMAC NAPI Poll function
1342 * @ndev: The DaVinci EMAC network adapter
1343 * @budget: Number of receive packets to process (as told by NAPI layer)
1345 * NAPI Poll function implemented to process packets as per budget. We check
1346 * the type of interrupt on the device and accordingly call the TX or RX
1347 * packet processing functions. We follow the budget for RX processing and
1348 * also put a cap on number of TX pkts processed through config param. The
1349 * NAPI schedule function is called if more packets pending.
1351 * Returns number of packets received (in most cases; else TX pkts - rarely)
1353 static int emac_poll(struct napi_struct *napi, int budget)
1356 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1357 struct net_device *ndev = priv->ndev;
1358 struct device *emac_dev = &ndev->dev;
1360 u32 num_tx_pkts = 0, num_rx_pkts = 0;
1362 /* Check interrupt vectors and call packet processing */
1363 status = emac_read(EMAC_MACINVECTOR);
1365 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1367 if (priv->version == EMAC_VERSION_2)
1368 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1370 if (status & mask) {
1371 num_tx_pkts = cpdma_chan_process(priv->txchan,
1372 EMAC_DEF_TX_MAX_SERVICE);
1373 } /* TX processing */
1375 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1377 if (priv->version == EMAC_VERSION_2)
1378 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1380 if (status & mask) {
1381 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1382 } /* RX processing */
1384 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1385 if (priv->version == EMAC_VERSION_2)
1386 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1388 if (unlikely(status & mask)) {
1390 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1391 netif_stop_queue(ndev);
1392 napi_disable(&priv->napi);
1394 status = emac_read(EMAC_MACSTATUS);
1395 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1396 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1398 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1399 EMAC_MACSTATUS_TXERRCH_SHIFT);
1400 if (net_ratelimit()) {
1401 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1402 &emac_txhost_errcodes[cause][0], ch);
1405 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1406 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1408 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1409 EMAC_MACSTATUS_RXERRCH_SHIFT);
1410 if (netif_msg_hw(priv) && net_ratelimit())
1411 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1412 &emac_rxhost_errcodes[cause][0], ch);
1414 } else if (num_rx_pkts < budget) {
1415 napi_complete(napi);
1416 emac_int_enable(priv);
1422 #ifdef CONFIG_NET_POLL_CONTROLLER
1424 * emac_poll_controller: EMAC Poll controller function
1425 * @ndev: The DaVinci EMAC network adapter
1427 * Polled functionality used by netconsole and others in non interrupt mode
1430 void emac_poll_controller(struct net_device *ndev)
1432 struct emac_priv *priv = netdev_priv(ndev);
1434 emac_int_disable(priv);
1435 emac_irq(ndev->irq, ndev);
1436 emac_int_enable(priv);
1440 static void emac_adjust_link(struct net_device *ndev)
1442 struct emac_priv *priv = netdev_priv(ndev);
1443 struct phy_device *phydev = priv->phydev;
1444 unsigned long flags;
1447 spin_lock_irqsave(&priv->lock, flags);
1450 /* check the mode of operation - full/half duplex */
1451 if (phydev->duplex != priv->duplex) {
1453 priv->duplex = phydev->duplex;
1455 if (phydev->speed != priv->speed) {
1457 priv->speed = phydev->speed;
1464 } else if (priv->link) {
1471 emac_update_phystatus(priv);
1472 phy_print_status(priv->phydev);
1475 spin_unlock_irqrestore(&priv->lock, flags);
1478 /*************************************************************************
1479 * Linux Driver Model
1480 *************************************************************************/
1483 * emac_devioctl: EMAC adapter ioctl
1484 * @ndev: The DaVinci EMAC network adapter
1485 * @ifrq: request parameter
1486 * @cmd: command parameter
1488 * EMAC driver ioctl function
1490 * Returns success(0) or appropriate error code
1492 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1494 dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n");
1496 if (!(netif_running(ndev)))
1499 /* TODO: Add phy read and write and private statistics get feature */
1504 static int match_first_device(struct device *dev, void *data)
1510 * emac_dev_open: EMAC device open
1511 * @ndev: The DaVinci EMAC network adapter
1513 * Called when system wants to start the interface. We init TX/RX channels
1514 * and enable the hardware for packet reception/transmission and start the
1517 * Returns 0 for a successful open, or appropriate error code
1519 static int emac_dev_open(struct net_device *ndev)
1521 struct device *emac_dev = &ndev->dev;
1523 struct resource *res;
1527 struct emac_priv *priv = netdev_priv(ndev);
1529 netif_carrier_off(ndev);
1530 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1531 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1533 /* Configuration items */
1534 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1536 priv->mac_hash1 = 0;
1537 priv->mac_hash2 = 0;
1538 emac_write(EMAC_MACHASH1, 0);
1539 emac_write(EMAC_MACHASH2, 0);
1541 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1542 struct sk_buff *skb = emac_rx_alloc(priv);
1547 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1548 skb_tailroom(skb), GFP_KERNEL);
1549 if (WARN_ON(ret < 0))
1555 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1556 for (i = res->start; i <= res->end; i++) {
1557 if (request_irq(i, emac_irq, IRQF_DISABLED,
1564 /* Start/Enable EMAC hardware */
1565 emac_hw_enable(priv);
1567 /* Enable Interrupt pacing if configured */
1568 if (priv->coal_intvl != 0) {
1569 struct ethtool_coalesce coal;
1571 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1572 emac_set_coalesce(ndev, &coal);
1575 cpdma_ctlr_start(priv->dma);
1577 priv->phydev = NULL;
1578 /* use the first phy on the bus if pdata did not give us a phy id */
1579 if (!priv->phy_id) {
1582 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1583 match_first_device);
1585 priv->phy_id = dev_name(phy);
1588 if (priv->phy_id && *priv->phy_id) {
1589 priv->phydev = phy_connect(ndev, priv->phy_id,
1590 &emac_adjust_link, 0,
1591 PHY_INTERFACE_MODE_MII);
1593 if (IS_ERR(priv->phydev)) {
1594 dev_err(emac_dev, "could not connect to phy %s\n",
1596 priv->phydev = NULL;
1597 return PTR_ERR(priv->phydev);
1604 dev_info(emac_dev, "attached PHY driver [%s] "
1605 "(mii_bus:phy_addr=%s, id=%x)\n",
1606 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
1607 priv->phydev->phy_id);
1609 /* No PHY , fix the link, speed and duplex settings */
1610 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1612 priv->speed = SPEED_100;
1613 priv->duplex = DUPLEX_FULL;
1614 emac_update_phystatus(priv);
1617 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
1618 emac_dump_regs(priv);
1620 if (netif_msg_drv(priv))
1621 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1624 phy_start(priv->phydev);
1630 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
1632 for (q = k; k >= 0; k--) {
1633 for (m = i; m >= res->start; m--)
1635 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
1642 * emac_dev_stop: EMAC device stop
1643 * @ndev: The DaVinci EMAC network adapter
1645 * Called when system wants to stop or down the interface. We stop the network
1646 * queue, disable interrupts and cleanup TX/RX channels.
1648 * We return the statistics in net_device_stats structure pulled from emac
1650 static int emac_dev_stop(struct net_device *ndev)
1652 struct resource *res;
1655 struct emac_priv *priv = netdev_priv(ndev);
1656 struct device *emac_dev = &ndev->dev;
1658 /* inform the upper layers. */
1659 netif_stop_queue(ndev);
1660 napi_disable(&priv->napi);
1662 netif_carrier_off(ndev);
1663 emac_int_disable(priv);
1664 cpdma_ctlr_stop(priv->dma);
1665 emac_write(EMAC_SOFTRESET, 1);
1668 phy_disconnect(priv->phydev);
1671 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1672 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1673 free_irq(irq_num, priv->ndev);
1677 if (netif_msg_drv(priv))
1678 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1684 * emac_dev_getnetstats: EMAC get statistics function
1685 * @ndev: The DaVinci EMAC network adapter
1687 * Called when system wants to get statistics from the device.
1689 * We return the statistics in net_device_stats structure pulled from emac
1691 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1693 struct emac_priv *priv = netdev_priv(ndev);
1695 u32 stats_clear_mask;
1697 /* update emac hardware stats and reset the registers*/
1699 mac_control = emac_read(EMAC_MACCONTROL);
1701 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1702 stats_clear_mask = EMAC_STATS_CLR_MASK;
1704 stats_clear_mask = 0;
1706 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1707 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1709 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1710 emac_read(EMAC_TXSINGLECOLL) +
1711 emac_read(EMAC_TXMULTICOLL));
1712 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1713 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1714 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1716 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1717 emac_read(EMAC_RXJABBER) +
1718 emac_read(EMAC_RXUNDERSIZED));
1719 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1720 emac_write(EMAC_RXJABBER, stats_clear_mask);
1721 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1723 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1724 emac_read(EMAC_RXMOFOVERRUNS));
1725 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1726 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1728 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1729 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1731 ndev->stats.tx_carrier_errors +=
1732 emac_read(EMAC_TXCARRIERSENSE);
1733 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1735 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1736 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1738 return &ndev->stats;
1741 static const struct net_device_ops emac_netdev_ops = {
1742 .ndo_open = emac_dev_open,
1743 .ndo_stop = emac_dev_stop,
1744 .ndo_start_xmit = emac_dev_xmit,
1745 .ndo_set_multicast_list = emac_dev_mcast_set,
1746 .ndo_set_mac_address = emac_dev_setmac_addr,
1747 .ndo_do_ioctl = emac_devioctl,
1748 .ndo_tx_timeout = emac_dev_tx_timeout,
1749 .ndo_get_stats = emac_dev_getnetstats,
1750 #ifdef CONFIG_NET_POLL_CONTROLLER
1751 .ndo_poll_controller = emac_poll_controller,
1756 * davinci_emac_probe: EMAC device probe
1757 * @pdev: The DaVinci EMAC device that we are removing
1759 * Called when probing for emac devicesr. We get details of instances and
1760 * resource information from platform init and register a network device
1761 * and allocate resources necessary for driver to perform
1763 static int __devinit davinci_emac_probe(struct platform_device *pdev)
1766 struct resource *res;
1767 struct net_device *ndev;
1768 struct emac_priv *priv;
1769 unsigned long size, hw_ram_addr;
1770 struct emac_platform_data *pdata;
1771 struct device *emac_dev;
1772 struct cpdma_params dma_params;
1774 /* obtain emac clock from kernel */
1775 emac_clk = clk_get(&pdev->dev, NULL);
1776 if (IS_ERR(emac_clk)) {
1777 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1780 emac_bus_frequency = clk_get_rate(emac_clk);
1781 /* TODO: Probe PHY here if possible */
1783 ndev = alloc_etherdev(sizeof(struct emac_priv));
1785 dev_err(&pdev->dev, "error allocating net_device\n");
1790 platform_set_drvdata(pdev, ndev);
1791 priv = netdev_priv(ndev);
1794 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1796 spin_lock_init(&priv->lock);
1798 pdata = pdev->dev.platform_data;
1800 dev_err(&pdev->dev, "no platform data\n");
1805 /* MAC addr and PHY mask , RMII enable info from platform_data */
1806 memcpy(priv->mac_addr, pdata->mac_addr, 6);
1807 priv->phy_id = pdata->phy_id;
1808 priv->rmii_en = pdata->rmii_en;
1809 priv->version = pdata->version;
1810 priv->int_enable = pdata->interrupt_enable;
1811 priv->int_disable = pdata->interrupt_disable;
1813 priv->coal_intvl = 0;
1814 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1816 emac_dev = &ndev->dev;
1817 /* Get EMAC platform data */
1818 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1820 dev_err(&pdev->dev,"error getting res\n");
1825 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1826 size = res->end - res->start + 1;
1827 if (!request_mem_region(res->start, size, ndev->name)) {
1828 dev_err(&pdev->dev, "failed request_mem_region() for regs\n");
1833 priv->remap_addr = ioremap(res->start, size);
1834 if (!priv->remap_addr) {
1835 dev_err(&pdev->dev, "unable to map IO\n");
1837 release_mem_region(res->start, size);
1840 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1841 ndev->base_addr = (unsigned long)priv->remap_addr;
1843 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1845 hw_ram_addr = pdata->hw_ram_addr;
1847 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1849 memset(&dma_params, 0, sizeof(dma_params));
1850 dma_params.dev = emac_dev;
1851 dma_params.dmaregs = priv->emac_base;
1852 dma_params.rxthresh = priv->emac_base + 0x120;
1853 dma_params.rxfree = priv->emac_base + 0x140;
1854 dma_params.txhdp = priv->emac_base + 0x600;
1855 dma_params.rxhdp = priv->emac_base + 0x620;
1856 dma_params.txcp = priv->emac_base + 0x640;
1857 dma_params.rxcp = priv->emac_base + 0x660;
1858 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1859 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1860 dma_params.desc_hw_addr = hw_ram_addr;
1861 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1862 dma_params.desc_align = 16;
1864 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1865 (u32 __force)res->start + pdata->ctrl_ram_offset;
1867 priv->dma = cpdma_ctlr_create(&dma_params);
1869 dev_err(&pdev->dev, "error initializing DMA\n");
1874 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
1876 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
1878 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
1883 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1885 dev_err(&pdev->dev, "error getting irq res\n");
1889 ndev->irq = res->start;
1891 if (!is_valid_ether_addr(priv->mac_addr)) {
1892 /* Use random MAC if none passed */
1893 random_ether_addr(priv->mac_addr);
1894 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1898 ndev->netdev_ops = &emac_netdev_ops;
1899 SET_ETHTOOL_OPS(ndev, ðtool_ops);
1900 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1902 clk_enable(emac_clk);
1904 /* register the network device */
1905 SET_NETDEV_DEV(ndev, &pdev->dev);
1906 rc = register_netdev(ndev);
1908 dev_err(&pdev->dev, "error in register_netdev\n");
1910 goto netdev_reg_err;
1914 if (netif_msg_probe(priv)) {
1915 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
1916 "(regs: %p, irq: %d)\n",
1917 (void *)priv->emac_base_phys, ndev->irq);
1922 clk_disable(emac_clk);
1925 cpdma_chan_destroy(priv->txchan);
1927 cpdma_chan_destroy(priv->rxchan);
1928 cpdma_ctlr_destroy(priv->dma);
1930 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1931 release_mem_region(res->start, res->end - res->start + 1);
1932 iounmap(priv->remap_addr);
1942 * davinci_emac_remove: EMAC device remove
1943 * @pdev: The DaVinci EMAC device that we are removing
1945 * Called when removing the device driver. We disable clock usage and release
1946 * the resources taken up by the driver and unregister network device
1948 static int __devexit davinci_emac_remove(struct platform_device *pdev)
1950 struct resource *res;
1951 struct net_device *ndev = platform_get_drvdata(pdev);
1952 struct emac_priv *priv = netdev_priv(ndev);
1954 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
1956 platform_set_drvdata(pdev, NULL);
1957 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1960 cpdma_chan_destroy(priv->txchan);
1962 cpdma_chan_destroy(priv->rxchan);
1963 cpdma_ctlr_destroy(priv->dma);
1965 release_mem_region(res->start, res->end - res->start + 1);
1967 unregister_netdev(ndev);
1968 iounmap(priv->remap_addr);
1971 clk_disable(emac_clk);
1977 static int davinci_emac_suspend(struct device *dev)
1979 struct platform_device *pdev = to_platform_device(dev);
1980 struct net_device *ndev = platform_get_drvdata(pdev);
1982 if (netif_running(ndev))
1983 emac_dev_stop(ndev);
1985 clk_disable(emac_clk);
1990 static int davinci_emac_resume(struct device *dev)
1992 struct platform_device *pdev = to_platform_device(dev);
1993 struct net_device *ndev = platform_get_drvdata(pdev);
1995 clk_enable(emac_clk);
1997 if (netif_running(ndev))
1998 emac_dev_open(ndev);
2003 static const struct dev_pm_ops davinci_emac_pm_ops = {
2004 .suspend = davinci_emac_suspend,
2005 .resume = davinci_emac_resume,
2009 * davinci_emac_driver: EMAC platform driver structure
2011 static struct platform_driver davinci_emac_driver = {
2013 .name = "davinci_emac",
2014 .owner = THIS_MODULE,
2015 .pm = &davinci_emac_pm_ops,
2017 .probe = davinci_emac_probe,
2018 .remove = __devexit_p(davinci_emac_remove),
2022 * davinci_emac_init: EMAC driver module init
2024 * Called when initializing the driver. We register the driver with
2027 static int __init davinci_emac_init(void)
2029 return platform_driver_register(&davinci_emac_driver);
2031 late_initcall(davinci_emac_init);
2034 * davinci_emac_exit: EMAC driver module exit
2036 * Called when exiting the driver completely. We unregister the driver with
2037 * the platform and exit
2039 static void __exit davinci_emac_exit(void)
2041 platform_driver_unregister(&davinci_emac_driver);
2043 module_exit(davinci_emac_exit);
2045 MODULE_LICENSE("GPL");
2046 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2047 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2048 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");