2 * Broadcom Starfighter 2 DSA switch driver
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
18 #include <linux/phy.h>
19 #include <linux/phy_fixed.h>
20 #include <linux/mii.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
25 #include <linux/ethtool.h>
26 #include <linux/if_bridge.h>
27 #include <linux/brcmphy.h>
30 #include "bcm_sf2_regs.h"
32 /* String, offset, and register size in bytes if different from 4 bytes */
33 static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
34 { "TxOctets", 0x000, 8 },
35 { "TxDropPkts", 0x020 },
36 { "TxQPKTQ0", 0x030 },
37 { "TxBroadcastPkts", 0x040 },
38 { "TxMulticastPkts", 0x050 },
39 { "TxUnicastPKts", 0x060 },
40 { "TxCollisions", 0x070 },
41 { "TxSingleCollision", 0x080 },
42 { "TxMultipleCollision", 0x090 },
43 { "TxDeferredCollision", 0x0a0 },
44 { "TxLateCollision", 0x0b0 },
45 { "TxExcessiveCollision", 0x0c0 },
46 { "TxFrameInDisc", 0x0d0 },
47 { "TxPausePkts", 0x0e0 },
48 { "TxQPKTQ1", 0x0f0 },
49 { "TxQPKTQ2", 0x100 },
50 { "TxQPKTQ3", 0x110 },
51 { "TxQPKTQ4", 0x120 },
52 { "TxQPKTQ5", 0x130 },
53 { "RxOctets", 0x140, 8 },
54 { "RxUndersizePkts", 0x160 },
55 { "RxPausePkts", 0x170 },
56 { "RxPkts64Octets", 0x180 },
57 { "RxPkts65to127Octets", 0x190 },
58 { "RxPkts128to255Octets", 0x1a0 },
59 { "RxPkts256to511Octets", 0x1b0 },
60 { "RxPkts512to1023Octets", 0x1c0 },
61 { "RxPkts1024toMaxPktsOctets", 0x1d0 },
62 { "RxOversizePkts", 0x1e0 },
63 { "RxJabbers", 0x1f0 },
64 { "RxAlignmentErrors", 0x200 },
65 { "RxFCSErrors", 0x210 },
66 { "RxGoodOctets", 0x220, 8 },
67 { "RxDropPkts", 0x240 },
68 { "RxUnicastPkts", 0x250 },
69 { "RxMulticastPkts", 0x260 },
70 { "RxBroadcastPkts", 0x270 },
71 { "RxSAChanges", 0x280 },
72 { "RxFragments", 0x290 },
73 { "RxJumboPkt", 0x2a0 },
74 { "RxSymblErr", 0x2b0 },
75 { "InRangeErrCount", 0x2c0 },
76 { "OutRangeErrCount", 0x2d0 },
77 { "EEELpiEvent", 0x2e0 },
78 { "EEELpiDuration", 0x2f0 },
79 { "RxDiscard", 0x300, 8 },
80 { "TxQPKTQ6", 0x320 },
81 { "TxQPKTQ7", 0x330 },
82 { "TxPkts64Octets", 0x340 },
83 { "TxPkts65to127Octets", 0x350 },
84 { "TxPkts128to255Octets", 0x360 },
85 { "TxPkts256to511Ocets", 0x370 },
86 { "TxPkts512to1023Ocets", 0x380 },
87 { "TxPkts1024toMaxPktOcets", 0x390 },
90 #define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
92 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
93 int port, uint8_t *data)
97 for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
98 memcpy(data + i * ETH_GSTRING_LEN,
99 bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
102 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
103 int port, uint64_t *data)
105 struct bcm_sf2_priv *priv = ds_to_priv(ds);
106 const struct bcm_sf2_hw_stats *s;
111 mutex_lock(&priv->stats_mutex);
113 /* Now fetch the per-port counters */
114 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
117 /* Do a latched 64-bit read if needed */
118 offset = s->reg + CORE_P_MIB_OFFSET(port);
119 if (s->sizeof_stat == 8)
120 val = core_readq(priv, offset);
122 val = core_readl(priv, offset);
127 mutex_unlock(&priv->stats_mutex);
130 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
132 return BCM_SF2_STATS_SIZE;
135 static char *bcm_sf2_sw_probe(struct device *host_dev, int sw_addr)
137 return "Broadcom Starfighter 2";
140 static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
142 struct bcm_sf2_priv *priv = ds_to_priv(ds);
146 /* Enable the IMP Port to be in the same VLAN as the other ports
147 * on a per-port basis such that we only have Port i and IMP in
150 for (i = 0; i < priv->hw_params.num_ports; i++) {
151 if (!((1 << i) & ds->phys_port_mask))
154 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
155 reg |= (1 << cpu_port);
156 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
160 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
162 struct bcm_sf2_priv *priv = ds_to_priv(ds);
165 /* Enable the port memories */
166 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
167 reg &= ~P_TXQ_PSM_VDD(port);
168 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
170 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
171 reg = core_readl(priv, CORE_IMP_CTL);
172 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
173 reg &= ~(RX_DIS | TX_DIS);
174 core_writel(priv, reg, CORE_IMP_CTL);
176 /* Enable forwarding */
177 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
179 /* Enable IMP port in dumb mode */
180 reg = core_readl(priv, CORE_SWITCH_CTRL);
181 reg |= MII_DUMB_FWDG_EN;
182 core_writel(priv, reg, CORE_SWITCH_CTRL);
184 /* Resolve which bit controls the Broadcom tag */
187 val = BRCM_HDR_EN_P8;
190 val = BRCM_HDR_EN_P7;
193 val = BRCM_HDR_EN_P5;
200 /* Enable Broadcom tags for IMP port */
201 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
203 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
205 /* Enable reception Broadcom tag for CPU TX (switch RX) to
206 * allow us to tag outgoing frames
208 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
210 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
212 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
213 * allow delivering frames to the per-port net_devices
215 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
217 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
219 /* Force link status for IMP port */
220 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
221 reg |= (MII_SW_OR | LINK_STS);
222 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
225 static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
227 struct bcm_sf2_priv *priv = ds_to_priv(ds);
230 reg = core_readl(priv, CORE_EEE_EN_CTRL);
235 core_writel(priv, reg, CORE_EEE_EN_CTRL);
238 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
240 struct bcm_sf2_priv *priv = ds_to_priv(ds);
243 reg = reg_readl(priv, REG_SPHY_CNTRL);
246 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
247 reg_writel(priv, reg, REG_SPHY_CNTRL);
249 reg = reg_readl(priv, REG_SPHY_CNTRL);
252 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
253 reg_writel(priv, reg, REG_SPHY_CNTRL);
257 reg_writel(priv, reg, REG_SPHY_CNTRL);
259 /* Use PHY-driven LED signaling */
261 reg = reg_readl(priv, REG_LED_CNTRL(0));
262 reg |= SPDLNK_SRC_SEL;
263 reg_writel(priv, reg, REG_LED_CNTRL(0));
267 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
268 struct phy_device *phy)
270 struct bcm_sf2_priv *priv = ds_to_priv(ds);
271 s8 cpu_port = ds->dst[ds->index].cpu_port;
274 /* Clear the memory power down */
275 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
276 reg &= ~P_TXQ_PSM_VDD(port);
277 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
279 /* Clear the Rx and Tx disable bits and set to no spanning tree */
280 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
282 /* Re-enable the GPHY and re-apply workarounds */
283 if (port == 0 && priv->hw_params.num_gphy == 1) {
284 bcm_sf2_gphy_enable_set(ds, true);
286 /* if phy_stop() has been called before, phy
287 * will be in halted state, and phy_start()
290 * the resume path does not configure back
291 * autoneg settings, and since we hard reset
292 * the phy manually here, we need to reset the
293 * state machine also.
295 phy->state = PHY_READY;
300 /* Enable port 7 interrupts to get notified */
302 intrl2_1_mask_clear(priv, P_IRQ_MASK(P7_IRQ_OFF));
304 /* Set this port, and only this one to be in the default VLAN,
305 * if member of a bridge, restore its membership prior to
306 * bringing down this port.
308 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
309 reg &= ~PORT_VLAN_CTRL_MASK;
311 reg |= priv->port_sts[port].vlan_ctl_mask;
312 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
314 bcm_sf2_imp_vlan_setup(ds, cpu_port);
316 /* If EEE was enabled, restore it */
317 if (priv->port_sts[port].eee.eee_enabled)
318 bcm_sf2_eee_enable_set(ds, port, true);
323 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
324 struct phy_device *phy)
326 struct bcm_sf2_priv *priv = ds_to_priv(ds);
329 if (priv->wol_ports_mask & (1 << port))
333 intrl2_1_mask_set(priv, P_IRQ_MASK(P7_IRQ_OFF));
334 intrl2_1_writel(priv, P_IRQ_MASK(P7_IRQ_OFF), INTRL2_CPU_CLEAR);
337 if (port == 0 && priv->hw_params.num_gphy == 1)
338 bcm_sf2_gphy_enable_set(ds, false);
340 if (dsa_is_cpu_port(ds, port))
343 off = CORE_G_PCTL_PORT(port);
345 reg = core_readl(priv, off);
346 reg |= RX_DIS | TX_DIS;
347 core_writel(priv, reg, off);
349 /* Power down the port memory */
350 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
351 reg |= P_TXQ_PSM_VDD(port);
352 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
355 /* Returns 0 if EEE was not enabled, or 1 otherwise
357 static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
358 struct phy_device *phy)
360 struct bcm_sf2_priv *priv = ds_to_priv(ds);
361 struct ethtool_eee *p = &priv->port_sts[port].eee;
364 p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
366 ret = phy_init_eee(phy, 0);
370 bcm_sf2_eee_enable_set(ds, port, true);
375 static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
376 struct ethtool_eee *e)
378 struct bcm_sf2_priv *priv = ds_to_priv(ds);
379 struct ethtool_eee *p = &priv->port_sts[port].eee;
382 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
383 e->eee_enabled = p->eee_enabled;
384 e->eee_active = !!(reg & (1 << port));
389 static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
390 struct phy_device *phydev,
391 struct ethtool_eee *e)
393 struct bcm_sf2_priv *priv = ds_to_priv(ds);
394 struct ethtool_eee *p = &priv->port_sts[port].eee;
396 p->eee_enabled = e->eee_enabled;
398 if (!p->eee_enabled) {
399 bcm_sf2_eee_enable_set(ds, port, false);
401 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
409 /* Fast-ageing of ARL entries for a given port, equivalent to an ARL
410 * flush for that port.
412 static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port)
414 struct bcm_sf2_priv *priv = ds_to_priv(ds);
415 unsigned int timeout = 1000;
418 core_writel(priv, port, CORE_FAST_AGE_PORT);
420 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
421 reg |= EN_AGE_PORT | FAST_AGE_STR_DONE;
422 core_writel(priv, reg, CORE_FAST_AGE_CTRL);
425 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
426 if (!(reg & FAST_AGE_STR_DONE))
438 static int bcm_sf2_sw_br_join(struct dsa_switch *ds, int port,
441 struct bcm_sf2_priv *priv = ds_to_priv(ds);
445 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
447 for (i = 0; i < priv->hw_params.num_ports; i++) {
448 if (!((1 << i) & br_port_mask))
451 /* Add this local port to the remote port VLAN control
452 * membership and update the remote port bitmask
454 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
456 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
457 priv->port_sts[i].vlan_ctl_mask = reg;
462 /* Configure the local port VLAN control membership to include
463 * remote ports and update the local port bitmask
465 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
466 priv->port_sts[port].vlan_ctl_mask = p_ctl;
471 static int bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port,
474 struct bcm_sf2_priv *priv = ds_to_priv(ds);
478 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
480 for (i = 0; i < priv->hw_params.num_ports; i++) {
481 /* Don't touch the remaining ports */
482 if (!((1 << i) & br_port_mask))
485 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
487 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
488 priv->port_sts[port].vlan_ctl_mask = reg;
490 /* Prevent self removal to preserve isolation */
495 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
496 priv->port_sts[port].vlan_ctl_mask = p_ctl;
501 static int bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port,
504 struct bcm_sf2_priv *priv = ds_to_priv(ds);
505 u8 hw_state, cur_hw_state;
509 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
510 cur_hw_state = reg >> G_MISTP_STATE_SHIFT;
513 case BR_STATE_DISABLED:
514 hw_state = G_MISTP_DIS_STATE;
516 case BR_STATE_LISTENING:
517 hw_state = G_MISTP_LISTEN_STATE;
519 case BR_STATE_LEARNING:
520 hw_state = G_MISTP_LEARN_STATE;
522 case BR_STATE_FORWARDING:
523 hw_state = G_MISTP_FWD_STATE;
525 case BR_STATE_BLOCKING:
526 hw_state = G_MISTP_BLOCK_STATE;
529 pr_err("%s: invalid STP state: %d\n", __func__, state);
533 /* Fast-age ARL entries if we are moving a port from Learning or
534 * Forwarding state to Disabled, Blocking or Listening state
536 if (cur_hw_state != hw_state) {
537 if (cur_hw_state & 4 && !(hw_state & 4)) {
538 ret = bcm_sf2_sw_fast_age_port(ds, port);
540 pr_err("%s: fast-ageing failed\n", __func__);
546 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
547 reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
549 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
554 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
556 struct bcm_sf2_priv *priv = dev_id;
558 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
560 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
565 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
567 struct bcm_sf2_priv *priv = dev_id;
569 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
571 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
573 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
574 priv->port_sts[7].link = 1;
575 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
576 priv->port_sts[7].link = 0;
581 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
583 unsigned int timeout = 1000;
586 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
587 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
588 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
591 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
592 if (!(reg & SOFTWARE_RESET))
595 usleep_range(1000, 2000);
596 } while (timeout-- > 0);
604 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
606 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
607 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
608 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
609 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
610 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
611 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
614 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
616 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
617 struct bcm_sf2_priv *priv = ds_to_priv(ds);
618 struct device_node *dn;
625 spin_lock_init(&priv->indir_lock);
626 mutex_init(&priv->stats_mutex);
628 /* All the interesting properties are at the parent device_node
631 dn = ds->pd->of_node->parent;
633 priv->irq0 = irq_of_parse_and_map(dn, 0);
634 priv->irq1 = irq_of_parse_and_map(dn, 1);
637 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
638 *base = of_iomap(dn, i);
640 pr_err("unable to find register: %s\n", reg_names[i]);
647 ret = bcm_sf2_sw_rst(priv);
649 pr_err("unable to software reset switch: %d\n", ret);
653 /* Disable all interrupts and request them */
654 bcm_sf2_intr_disable(priv);
656 ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
659 pr_err("failed to request switch_0 IRQ\n");
663 ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
666 pr_err("failed to request switch_1 IRQ\n");
670 /* Reset the MIB counters */
671 reg = core_readl(priv, CORE_GMNCFGCFG);
673 core_writel(priv, reg, CORE_GMNCFGCFG);
675 core_writel(priv, reg, CORE_GMNCFGCFG);
677 /* Get the maximum number of ports for this switch */
678 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
679 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
680 priv->hw_params.num_ports = DSA_MAX_PORTS;
682 /* Assume a single GPHY setup if we can't read that property */
683 if (of_property_read_u32(dn, "brcm,num-gphy",
684 &priv->hw_params.num_gphy))
685 priv->hw_params.num_gphy = 1;
687 /* Enable all valid ports and disable those unused */
688 for (port = 0; port < priv->hw_params.num_ports; port++) {
689 /* IMP port receives special treatment */
690 if ((1 << port) & ds->phys_port_mask)
691 bcm_sf2_port_setup(ds, port, NULL);
692 else if (dsa_is_cpu_port(ds, port))
693 bcm_sf2_imp_setup(ds, port);
695 bcm_sf2_port_disable(ds, port, NULL);
698 /* Include the pseudo-PHY address and the broadcast PHY address to
699 * divert reads towards our workaround. This is only required for
700 * 7445D0, since 7445E0 disconnects the internal switch pseudo-PHY such
701 * that we can use the regular SWITCH_MDIO master controller instead.
703 * By default, DSA initializes ds->phys_mii_mask to ds->phys_port_mask
704 * to have a 1:1 mapping between Port address and PHY address in order
705 * to utilize the slave_mii_bus instance to read from Port PHYs. This is
706 * not what we want here, so we initialize phys_mii_mask 0 to always
707 * utilize the "master" MDIO bus backed by the "mdio-unimac" driver.
709 if (of_machine_is_compatible("brcm,bcm7445d0"))
710 ds->phys_mii_mask |= ((1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0));
712 ds->phys_mii_mask = 0;
714 rev = reg_readl(priv, REG_SWITCH_REVISION);
715 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
717 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
719 rev = reg_readl(priv, REG_PHY_REVISION);
720 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
722 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
723 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
724 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
725 priv->core, priv->irq0, priv->irq1);
730 free_irq(priv->irq0, priv);
733 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
741 static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
746 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
748 struct bcm_sf2_priv *priv = ds_to_priv(ds);
750 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
751 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
752 * the REG_PHY_REVISION register layout is.
755 return priv->hw_params.gphy_rev;
758 static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
761 struct bcm_sf2_priv *priv = ds_to_priv(ds);
765 reg = reg_readl(priv, REG_SWITCH_CNTRL);
766 reg |= MDIO_MASTER_SEL;
767 reg_writel(priv, reg, REG_SWITCH_CNTRL);
769 /* Page << 8 | offset */
772 core_writel(priv, addr, reg);
774 /* Page << 8 | offset */
775 reg = 0x80 << 8 | regnum << 1;
779 ret = core_readl(priv, reg);
781 core_writel(priv, val, reg);
783 reg = reg_readl(priv, REG_SWITCH_CNTRL);
784 reg &= ~MDIO_MASTER_SEL;
785 reg_writel(priv, reg, REG_SWITCH_CNTRL);
790 static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
792 /* Intercept reads from the MDIO broadcast address or Broadcom
797 case BRCM_PSEUDO_PHY_ADDR:
798 return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
804 static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
807 /* Intercept writes to the MDIO broadcast address or Broadcom
812 case BRCM_PSEUDO_PHY_ADDR:
813 bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
820 static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
821 struct phy_device *phydev)
823 struct bcm_sf2_priv *priv = ds_to_priv(ds);
824 u32 id_mode_dis = 0, port_mode;
825 const char *str = NULL;
828 switch (phydev->interface) {
829 case PHY_INTERFACE_MODE_RGMII:
830 str = "RGMII (no delay)";
832 case PHY_INTERFACE_MODE_RGMII_TXID:
834 str = "RGMII (TX delay)";
835 port_mode = EXT_GPHY;
837 case PHY_INTERFACE_MODE_MII:
839 port_mode = EXT_EPHY;
841 case PHY_INTERFACE_MODE_REVMII:
843 port_mode = EXT_REVMII;
846 /* All other PHYs: internal and MoCA */
850 /* If the link is down, just disable the interface to conserve power */
852 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
853 reg &= ~RGMII_MODE_EN;
854 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
858 /* Clear id_mode_dis bit, and the existing port mode, but
859 * make sure we enable the RGMII block for data to pass
861 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
863 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
864 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
866 reg |= port_mode | RGMII_MODE_EN;
871 if (phydev->asym_pause)
876 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
878 pr_info("Port %d configured for %s\n", port, str);
881 /* Force link settings detected from the PHY */
883 switch (phydev->speed) {
885 reg |= SPDSTS_1000 << SPEED_SHIFT;
888 reg |= SPDSTS_100 << SPEED_SHIFT;
894 if (phydev->duplex == DUPLEX_FULL)
897 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
900 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
901 struct fixed_phy_status *status)
903 struct bcm_sf2_priv *priv = ds_to_priv(ds);
907 duplex = core_readl(priv, CORE_DUPSTS);
908 pause = core_readl(priv, CORE_PAUSESTS);
912 /* Port 7 is special as we do not get link status from CORE_LNKSTS,
913 * which means that we need to force the link at the port override
914 * level to get the data to flow. We do use what the interrupt handler
915 * did determine before.
917 * For the other ports, we just force the link status, since this is
918 * a fixed PHY device.
921 status->link = priv->port_sts[port].link;
922 /* For MoCA interfaces, also force a link down notification
923 * since some version of the user-space daemon (mocad) use
924 * cmd->autoneg to force the link, which messes up the PHY
925 * state machine and make it go in PHY_FORCING state instead.
928 netif_carrier_off(ds->ports[port]);
932 status->duplex = !!(duplex & (1 << port));
935 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
941 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
943 if ((pause & (1 << port)) &&
944 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
945 status->asym_pause = 1;
949 if (pause & (1 << port))
953 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
955 struct bcm_sf2_priv *priv = ds_to_priv(ds);
958 bcm_sf2_intr_disable(priv);
960 /* Disable all ports physically present including the IMP
961 * port, the other ones have already been disabled during
964 for (port = 0; port < DSA_MAX_PORTS; port++) {
965 if ((1 << port) & ds->phys_port_mask ||
966 dsa_is_cpu_port(ds, port))
967 bcm_sf2_port_disable(ds, port, NULL);
973 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
975 struct bcm_sf2_priv *priv = ds_to_priv(ds);
979 ret = bcm_sf2_sw_rst(priv);
981 pr_err("%s: failed to software reset switch\n", __func__);
985 if (priv->hw_params.num_gphy == 1)
986 bcm_sf2_gphy_enable_set(ds, true);
988 for (port = 0; port < DSA_MAX_PORTS; port++) {
989 if ((1 << port) & ds->phys_port_mask)
990 bcm_sf2_port_setup(ds, port, NULL);
991 else if (dsa_is_cpu_port(ds, port))
992 bcm_sf2_imp_setup(ds, port);
998 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
999 struct ethtool_wolinfo *wol)
1001 struct net_device *p = ds->dst[ds->index].master_netdev;
1002 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1003 struct ethtool_wolinfo pwol;
1005 /* Get the parent device WoL settings */
1006 p->ethtool_ops->get_wol(p, &pwol);
1008 /* Advertise the parent device supported settings */
1009 wol->supported = pwol.supported;
1010 memset(&wol->sopass, 0, sizeof(wol->sopass));
1012 if (pwol.wolopts & WAKE_MAGICSECURE)
1013 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1015 if (priv->wol_ports_mask & (1 << port))
1016 wol->wolopts = pwol.wolopts;
1021 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1022 struct ethtool_wolinfo *wol)
1024 struct net_device *p = ds->dst[ds->index].master_netdev;
1025 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1026 s8 cpu_port = ds->dst[ds->index].cpu_port;
1027 struct ethtool_wolinfo pwol;
1029 p->ethtool_ops->get_wol(p, &pwol);
1030 if (wol->wolopts & ~pwol.supported)
1034 priv->wol_ports_mask |= (1 << port);
1036 priv->wol_ports_mask &= ~(1 << port);
1038 /* If we have at least one port enabled, make sure the CPU port
1039 * is also enabled. If the CPU port is the last one enabled, we disable
1040 * it since this configuration does not make sense.
1042 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1043 priv->wol_ports_mask |= (1 << cpu_port);
1045 priv->wol_ports_mask &= ~(1 << cpu_port);
1047 return p->ethtool_ops->set_wol(p, wol);
1050 static struct dsa_switch_driver bcm_sf2_switch_driver = {
1051 .tag_protocol = DSA_TAG_PROTO_BRCM,
1052 .priv_size = sizeof(struct bcm_sf2_priv),
1053 .probe = bcm_sf2_sw_probe,
1054 .setup = bcm_sf2_sw_setup,
1055 .set_addr = bcm_sf2_sw_set_addr,
1056 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1057 .phy_read = bcm_sf2_sw_phy_read,
1058 .phy_write = bcm_sf2_sw_phy_write,
1059 .get_strings = bcm_sf2_sw_get_strings,
1060 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1061 .get_sset_count = bcm_sf2_sw_get_sset_count,
1062 .adjust_link = bcm_sf2_sw_adjust_link,
1063 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
1064 .suspend = bcm_sf2_sw_suspend,
1065 .resume = bcm_sf2_sw_resume,
1066 .get_wol = bcm_sf2_sw_get_wol,
1067 .set_wol = bcm_sf2_sw_set_wol,
1068 .port_enable = bcm_sf2_port_setup,
1069 .port_disable = bcm_sf2_port_disable,
1070 .get_eee = bcm_sf2_sw_get_eee,
1071 .set_eee = bcm_sf2_sw_set_eee,
1072 .port_join_bridge = bcm_sf2_sw_br_join,
1073 .port_leave_bridge = bcm_sf2_sw_br_leave,
1074 .port_stp_update = bcm_sf2_sw_br_set_stp_state,
1077 static int __init bcm_sf2_init(void)
1079 register_switch_driver(&bcm_sf2_switch_driver);
1083 module_init(bcm_sf2_init);
1085 static void __exit bcm_sf2_exit(void)
1087 unregister_switch_driver(&bcm_sf2_switch_driver);
1089 module_exit(bcm_sf2_exit);
1091 MODULE_AUTHOR("Broadcom Corporation");
1092 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1093 MODULE_LICENSE("GPL");
1094 MODULE_ALIAS("platform:brcm-sf2");