2 * net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
4 * Copyright (c) 2014 Guenter Roeck
6 * Derived from mv88e6123_61_65.c
7 * Copyright (c) 2008-2009 Marvell Semiconductor
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/delay.h>
16 #include <linux/jiffies.h>
17 #include <linux/list.h>
18 #include <linux/module.h>
19 #include <linux/netdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/phy.h>
23 #include "mv88e6xxx.h"
25 static char *mv88e6352_probe(struct device *host_dev, int sw_addr)
27 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
33 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
35 if ((ret & 0xfff0) == 0x1760)
36 return "Marvell 88E6176";
38 return "Marvell 88E6352 (A0)";
40 return "Marvell 88E6352 (A1)";
41 if ((ret & 0xfff0) == 0x3520)
42 return "Marvell 88E6352";
48 static int mv88e6352_setup_global(struct dsa_switch *ds)
50 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
54 /* Discard packets with excessive collisions,
55 * mask all interrupt sources, enable PPU (bit 14, undocumented).
57 REG_WRITE(REG_GLOBAL, 0x04, 0x6000);
59 /* Set the default address aging time to 5 minutes, and
60 * enable address learn messages to be sent to all message
63 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
65 /* Configure the priority mapping registers. */
66 ret = mv88e6xxx_config_prio(ds);
70 /* Configure the upstream port, and configure the upstream
71 * port as the port to which ingress and egress monitor frames
74 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));
76 /* Disable remote management for now, and set the switch's
79 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
81 /* Send all frames with destination addresses matching
82 * 01:80:c2:00:00:2x to the CPU port.
84 REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);
86 /* Send all frames with destination addresses matching
87 * 01:80:c2:00:00:0x to the CPU port.
89 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
91 /* Disable the loopback filter, disable flow control
92 * messages, disable flood broadcast override, disable
93 * removing of provider tags, disable ATU age violation
94 * interrupts, disable tag flow control, force flow
95 * control priority to the highest, and send all special
96 * multicast frames to the CPU at the highest priority.
98 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
100 /* Program the DSA routing table. */
101 for (i = 0; i < 32; i++) {
104 if (i != ds->index && i < ds->dst->pd->nr_chips)
105 nexthop = ds->pd->rtable[i] & 0x1f;
107 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
110 /* Clear all trunk masks. */
111 for (i = 0; i < 8; i++)
112 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7f);
114 /* Clear all trunk mappings. */
115 for (i = 0; i < 16; i++)
116 REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
118 /* Disable ingress rate limiting by resetting all ingress
119 * rate limit registers to their initial state.
121 for (i = 0; i < ps->num_ports; i++)
122 REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));
124 /* Initialise cross-chip port VLAN table to reset defaults. */
125 REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);
127 /* Clear the priority override table. */
128 for (i = 0; i < 16; i++)
129 REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));
131 /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */
136 static int mv88e6352_setup_port(struct dsa_switch *ds, int p)
138 int addr = REG_PORT(p);
141 /* MAC Forcing register: don't force link, speed, duplex
142 * or flow control state to any particular values on physical
143 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
146 if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
147 REG_WRITE(addr, 0x01, 0x003e);
149 REG_WRITE(addr, 0x01, 0x0003);
151 /* Do not limit the period of time that this port can be
152 * paused for by the remote end or the period of time that
153 * this port can pause the remote end.
155 REG_WRITE(addr, 0x02, 0x0000);
157 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
158 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
159 * tunneling, determine priority by looking at 802.1p and IP
160 * priority fields (IP prio has precedence), and set STP state
163 * If this is the CPU link, use DSA or EDSA tagging depending
164 * on which tagging mode was configured.
166 * If this is a link to another switch, use DSA tagging mode.
168 * If this is the upstream port for this switch, enable
169 * forwarding of unknown unicasts and multicasts.
172 if (dsa_is_cpu_port(ds, p)) {
173 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
178 if (ds->dsa_port_mask & (1 << p))
180 if (p == dsa_upstream_port(ds))
182 REG_WRITE(addr, 0x04, val);
184 /* Port Control 2: don't force a good FCS, set the maximum
185 * frame size to 10240 bytes, don't let the switch add or
186 * strip 802.1q tags, don't discard tagged or untagged frames
187 * on this port, do a destination address lookup on all
188 * received packets as usual, disable ARP mirroring and don't
189 * send a copy of all transmitted/received frames on this port
192 REG_WRITE(addr, 0x08, 0x2080);
194 /* Egress rate control: disable egress rate control. */
195 REG_WRITE(addr, 0x09, 0x0001);
197 /* Egress rate control 2: disable egress rate control. */
198 REG_WRITE(addr, 0x0a, 0x0000);
200 /* Port Association Vector: when learning source addresses
201 * of packets, add the address to the address database using
202 * a port bitmap that has only the bit for this port set and
203 * the other bits clear.
205 REG_WRITE(addr, 0x0b, 1 << p);
207 /* Port ATU control: disable limiting the number of address
208 * database entries that this port is allowed to use.
210 REG_WRITE(addr, 0x0c, 0x0000);
212 /* Priority Override: disable DA, SA and VTU priority override. */
213 REG_WRITE(addr, 0x0d, 0x0000);
215 /* Port Ethertype: use the Ethertype DSA Ethertype value. */
216 REG_WRITE(addr, 0x0f, ETH_P_EDSA);
218 /* Tag Remap: use an identity 802.1p prio -> switch prio
221 REG_WRITE(addr, 0x18, 0x3210);
223 /* Tag Remap 2: use an identity 802.1p prio -> switch prio
226 REG_WRITE(addr, 0x19, 0x7654);
228 return mv88e6xxx_setup_port_common(ds, p);
231 #ifdef CONFIG_NET_DSA_HWMON
233 static int mv88e6352_get_temp(struct dsa_switch *ds, int *temp)
239 ret = mv88e6xxx_phy_page_read(ds, 0, 6, 27);
243 *temp = (ret & 0xff) - 25;
248 static int mv88e6352_get_temp_limit(struct dsa_switch *ds, int *temp)
254 ret = mv88e6xxx_phy_page_read(ds, 0, 6, 26);
258 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
263 static int mv88e6352_set_temp_limit(struct dsa_switch *ds, int temp)
267 ret = mv88e6xxx_phy_page_read(ds, 0, 6, 26);
270 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
271 return mv88e6xxx_phy_page_write(ds, 0, 6, 26,
272 (ret & 0xe0ff) | (temp << 8));
275 static int mv88e6352_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
281 ret = mv88e6xxx_phy_page_read(ds, 0, 6, 26);
285 *alarm = !!(ret & 0x40);
289 #endif /* CONFIG_NET_DSA_HWMON */
291 static int mv88e6352_setup(struct dsa_switch *ds)
293 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
297 ret = mv88e6xxx_setup_common(ds);
303 mutex_init(&ps->eeprom_mutex);
305 ret = mv88e6xxx_switch_reset(ds, true);
309 /* @@@ initialise vtu and atu */
311 ret = mv88e6352_setup_global(ds);
315 for (i = 0; i < ps->num_ports; i++) {
316 ret = mv88e6352_setup_port(ds, i);
324 static int mv88e6352_port_to_phy_addr(int port)
326 if (port >= 0 && port <= 4)
332 mv88e6352_phy_read(struct dsa_switch *ds, int port, int regnum)
334 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
335 int addr = mv88e6352_port_to_phy_addr(port);
341 mutex_lock(&ps->phy_mutex);
342 ret = mv88e6xxx_phy_read_indirect(ds, addr, regnum);
343 mutex_unlock(&ps->phy_mutex);
349 mv88e6352_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
351 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
352 int addr = mv88e6352_port_to_phy_addr(port);
358 mutex_lock(&ps->phy_mutex);
359 ret = mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
360 mutex_unlock(&ps->phy_mutex);
365 static struct mv88e6xxx_hw_stat mv88e6352_hw_stats[] = {
366 { "in_good_octets", 8, 0x00, },
367 { "in_bad_octets", 4, 0x02, },
368 { "in_unicast", 4, 0x04, },
369 { "in_broadcasts", 4, 0x06, },
370 { "in_multicasts", 4, 0x07, },
371 { "in_pause", 4, 0x16, },
372 { "in_undersize", 4, 0x18, },
373 { "in_fragments", 4, 0x19, },
374 { "in_oversize", 4, 0x1a, },
375 { "in_jabber", 4, 0x1b, },
376 { "in_rx_error", 4, 0x1c, },
377 { "in_fcs_error", 4, 0x1d, },
378 { "out_octets", 8, 0x0e, },
379 { "out_unicast", 4, 0x10, },
380 { "out_broadcasts", 4, 0x13, },
381 { "out_multicasts", 4, 0x12, },
382 { "out_pause", 4, 0x15, },
383 { "excessive", 4, 0x11, },
384 { "collisions", 4, 0x1e, },
385 { "deferred", 4, 0x05, },
386 { "single", 4, 0x14, },
387 { "multiple", 4, 0x17, },
388 { "out_fcs_error", 4, 0x03, },
389 { "late", 4, 0x1f, },
390 { "hist_64bytes", 4, 0x08, },
391 { "hist_65_127bytes", 4, 0x09, },
392 { "hist_128_255bytes", 4, 0x0a, },
393 { "hist_256_511bytes", 4, 0x0b, },
394 { "hist_512_1023bytes", 4, 0x0c, },
395 { "hist_1024_max_bytes", 4, 0x0d, },
396 { "sw_in_discards", 4, 0x110, },
397 { "sw_in_filtered", 2, 0x112, },
398 { "sw_out_filtered", 2, 0x113, },
401 static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr)
403 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
406 mutex_lock(&ps->eeprom_mutex);
408 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14,
409 0xc000 | (addr & 0xff));
413 ret = mv88e6xxx_eeprom_busy_wait(ds);
417 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x15);
419 mutex_unlock(&ps->eeprom_mutex);
423 static int mv88e6352_get_eeprom(struct dsa_switch *ds,
424 struct ethtool_eeprom *eeprom, u8 *data)
430 offset = eeprom->offset;
434 eeprom->magic = 0xc3ec4951;
436 ret = mv88e6xxx_eeprom_load_wait(ds);
443 word = mv88e6352_read_eeprom_word(ds, offset >> 1);
447 *data++ = (word >> 8) & 0xff;
457 word = mv88e6352_read_eeprom_word(ds, offset >> 1);
461 *data++ = word & 0xff;
462 *data++ = (word >> 8) & 0xff;
472 word = mv88e6352_read_eeprom_word(ds, offset >> 1);
476 *data++ = word & 0xff;
486 static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds)
490 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x14);
500 static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr,
503 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
506 mutex_lock(&ps->eeprom_mutex);
508 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x15, data);
512 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14,
513 0xb000 | (addr & 0xff));
517 ret = mv88e6xxx_eeprom_busy_wait(ds);
519 mutex_unlock(&ps->eeprom_mutex);
523 static int mv88e6352_set_eeprom(struct dsa_switch *ds,
524 struct ethtool_eeprom *eeprom, u8 *data)
530 if (eeprom->magic != 0xc3ec4951)
533 ret = mv88e6352_eeprom_is_readonly(ds);
537 offset = eeprom->offset;
541 ret = mv88e6xxx_eeprom_load_wait(ds);
548 word = mv88e6352_read_eeprom_word(ds, offset >> 1);
552 word = (*data++ << 8) | (word & 0xff);
554 ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
567 word |= *data++ << 8;
569 ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
581 word = mv88e6352_read_eeprom_word(ds, offset >> 1);
585 word = (word & 0xff00) | *data++;
587 ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
600 mv88e6352_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
602 mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6352_hw_stats),
603 mv88e6352_hw_stats, port, data);
607 mv88e6352_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
609 mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6352_hw_stats),
610 mv88e6352_hw_stats, port, data);
613 static int mv88e6352_get_sset_count(struct dsa_switch *ds)
615 return ARRAY_SIZE(mv88e6352_hw_stats);
618 struct dsa_switch_driver mv88e6352_switch_driver = {
619 .tag_protocol = DSA_TAG_PROTO_EDSA,
620 .priv_size = sizeof(struct mv88e6xxx_priv_state),
621 .probe = mv88e6352_probe,
622 .setup = mv88e6352_setup,
623 .set_addr = mv88e6xxx_set_addr_indirect,
624 .phy_read = mv88e6352_phy_read,
625 .phy_write = mv88e6352_phy_write,
626 .poll_link = mv88e6xxx_poll_link,
627 .get_strings = mv88e6352_get_strings,
628 .get_ethtool_stats = mv88e6352_get_ethtool_stats,
629 .get_sset_count = mv88e6352_get_sset_count,
630 .set_eee = mv88e6xxx_set_eee,
631 .get_eee = mv88e6xxx_get_eee,
632 #ifdef CONFIG_NET_DSA_HWMON
633 .get_temp = mv88e6352_get_temp,
634 .get_temp_limit = mv88e6352_get_temp_limit,
635 .set_temp_limit = mv88e6352_set_temp_limit,
636 .get_temp_alarm = mv88e6352_get_temp_alarm,
638 .get_eeprom = mv88e6352_get_eeprom,
639 .set_eeprom = mv88e6352_set_eeprom,
640 .get_regs_len = mv88e6xxx_get_regs_len,
641 .get_regs = mv88e6xxx_get_regs,
642 .port_join_bridge = mv88e6xxx_join_bridge,
643 .port_leave_bridge = mv88e6xxx_leave_bridge,
644 .port_stp_update = mv88e6xxx_port_stp_update,
645 .fdb_add = mv88e6xxx_port_fdb_add,
646 .fdb_del = mv88e6xxx_port_fdb_del,
647 .fdb_getnext = mv88e6xxx_port_fdb_getnext,
650 MODULE_ALIAS("platform:mv88e6352");