2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/delay.h>
12 #include <linux/etherdevice.h>
13 #include <linux/if_bridge.h>
14 #include <linux/jiffies.h>
15 #include <linux/list.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/phy.h>
20 #include "mv88e6xxx.h"
22 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
23 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
24 * will be directly accessible on some {device address,register address}
25 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
26 * will only respond to SMI transactions to that specific address, and
27 * an indirect addressing mechanism needs to be used to access its
30 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
35 for (i = 0; i < 16; i++) {
36 ret = mdiobus_read(bus, sw_addr, 0);
40 if ((ret & 0x8000) == 0)
47 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
52 return mdiobus_read(bus, addr, reg);
54 /* Wait for the bus to become free. */
55 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
59 /* Transmit the read command. */
60 ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg);
64 /* Wait for the read command to complete. */
65 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
70 ret = mdiobus_read(bus, sw_addr, 1);
77 /* Must be called with SMI mutex held */
78 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
80 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
86 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
90 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
96 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
98 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
101 mutex_lock(&ps->smi_mutex);
102 ret = _mv88e6xxx_reg_read(ds, addr, reg);
103 mutex_unlock(&ps->smi_mutex);
108 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
114 return mdiobus_write(bus, addr, reg, val);
116 /* Wait for the bus to become free. */
117 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
121 /* Transmit the data to write. */
122 ret = mdiobus_write(bus, sw_addr, 1, val);
126 /* Transmit the write command. */
127 ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg);
131 /* Wait for the write command to complete. */
132 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
139 /* Must be called with SMI mutex held */
140 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
143 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
148 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
151 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
154 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
156 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
159 mutex_lock(&ps->smi_mutex);
160 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
161 mutex_unlock(&ps->smi_mutex);
166 int mv88e6xxx_config_prio(struct dsa_switch *ds)
168 /* Configure the IP ToS mapping registers. */
169 REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
170 REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
171 REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
172 REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
173 REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
174 REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
175 REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
176 REG_WRITE(REG_GLOBAL, 0x17, 0xffff);
178 /* Configure the IEEE 802.1p priority mapping register. */
179 REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);
184 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
186 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
187 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
188 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
193 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
198 for (i = 0; i < 6; i++) {
201 /* Write the MAC address byte. */
202 REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 | (i << 8) | addr[i]);
204 /* Wait for the write to complete. */
205 for (j = 0; j < 16; j++) {
206 ret = REG_READ(REG_GLOBAL2, 0x0d);
207 if ((ret & 0x8000) == 0)
217 int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
220 return mv88e6xxx_reg_read(ds, addr, regnum);
224 int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
227 return mv88e6xxx_reg_write(ds, addr, regnum, val);
231 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
232 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
235 unsigned long timeout;
237 ret = REG_READ(REG_GLOBAL, 0x04);
238 REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);
240 timeout = jiffies + 1 * HZ;
241 while (time_before(jiffies, timeout)) {
242 ret = REG_READ(REG_GLOBAL, 0x00);
243 usleep_range(1000, 2000);
244 if ((ret & 0xc000) != 0xc000)
251 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
254 unsigned long timeout;
256 ret = REG_READ(REG_GLOBAL, 0x04);
257 REG_WRITE(REG_GLOBAL, 0x04, ret | 0x4000);
259 timeout = jiffies + 1 * HZ;
260 while (time_before(jiffies, timeout)) {
261 ret = REG_READ(REG_GLOBAL, 0x00);
262 usleep_range(1000, 2000);
263 if ((ret & 0xc000) == 0xc000)
270 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
272 struct mv88e6xxx_priv_state *ps;
274 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
275 if (mutex_trylock(&ps->ppu_mutex)) {
276 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
278 if (mv88e6xxx_ppu_enable(ds) == 0)
279 ps->ppu_disabled = 0;
280 mutex_unlock(&ps->ppu_mutex);
284 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
286 struct mv88e6xxx_priv_state *ps = (void *)_ps;
288 schedule_work(&ps->ppu_work);
291 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
293 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
296 mutex_lock(&ps->ppu_mutex);
298 /* If the PHY polling unit is enabled, disable it so that
299 * we can access the PHY registers. If it was already
300 * disabled, cancel the timer that is going to re-enable
303 if (!ps->ppu_disabled) {
304 ret = mv88e6xxx_ppu_disable(ds);
306 mutex_unlock(&ps->ppu_mutex);
309 ps->ppu_disabled = 1;
311 del_timer(&ps->ppu_timer);
318 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
320 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
322 /* Schedule a timer to re-enable the PHY polling unit. */
323 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
324 mutex_unlock(&ps->ppu_mutex);
327 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
329 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
331 mutex_init(&ps->ppu_mutex);
332 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
333 init_timer(&ps->ppu_timer);
334 ps->ppu_timer.data = (unsigned long)ps;
335 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
338 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
342 ret = mv88e6xxx_ppu_access_get(ds);
344 ret = mv88e6xxx_reg_read(ds, addr, regnum);
345 mv88e6xxx_ppu_access_put(ds);
351 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
356 ret = mv88e6xxx_ppu_access_get(ds);
358 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
359 mv88e6xxx_ppu_access_put(ds);
366 void mv88e6xxx_poll_link(struct dsa_switch *ds)
370 for (i = 0; i < DSA_MAX_PORTS; i++) {
371 struct net_device *dev;
372 int uninitialized_var(port_status);
383 if (dev->flags & IFF_UP) {
384 port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
388 link = !!(port_status & 0x0800);
392 if (netif_carrier_ok(dev)) {
393 netdev_info(dev, "link down\n");
394 netif_carrier_off(dev);
399 switch (port_status & 0x0300) {
413 duplex = (port_status & 0x0400) ? 1 : 0;
414 fc = (port_status & 0x8000) ? 1 : 0;
416 if (!netif_carrier_ok(dev)) {
418 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
420 duplex ? "full" : "half",
422 netif_carrier_on(dev);
427 static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
432 for (i = 0; i < 10; i++) {
433 ret = REG_READ(REG_GLOBAL, 0x1d);
434 if ((ret & 0x8000) == 0)
441 static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
445 /* Snapshot the hardware statistics counters for this port. */
446 REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 | port);
448 /* Wait for the snapshotting to complete. */
449 ret = mv88e6xxx_stats_wait(ds);
456 static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
463 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 | stat);
467 ret = mv88e6xxx_stats_wait(ds);
471 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
477 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
484 void mv88e6xxx_get_strings(struct dsa_switch *ds,
485 int nr_stats, struct mv88e6xxx_hw_stat *stats,
486 int port, uint8_t *data)
490 for (i = 0; i < nr_stats; i++) {
491 memcpy(data + i * ETH_GSTRING_LEN,
492 stats[i].string, ETH_GSTRING_LEN);
496 void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
497 int nr_stats, struct mv88e6xxx_hw_stat *stats,
498 int port, uint64_t *data)
500 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
504 mutex_lock(&ps->stats_mutex);
506 ret = mv88e6xxx_stats_snapshot(ds, port);
508 mutex_unlock(&ps->stats_mutex);
512 /* Read each of the counters. */
513 for (i = 0; i < nr_stats; i++) {
514 struct mv88e6xxx_hw_stat *s = stats + i;
518 if (s->reg >= 0x100) {
521 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
526 if (s->sizeof_stat == 4) {
527 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
533 data[i] = (((u64)high) << 16) | low;
536 mv88e6xxx_stats_read(ds, s->reg, &low);
537 if (s->sizeof_stat == 8)
538 mv88e6xxx_stats_read(ds, s->reg + 1, &high);
540 data[i] = (((u64)high) << 32) | low;
543 mutex_unlock(&ps->stats_mutex);
546 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
548 return 32 * sizeof(u16);
551 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
552 struct ethtool_regs *regs, void *_p)
559 memset(p, 0xff, 32 * sizeof(u16));
561 for (i = 0; i < 32; i++) {
564 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
570 #ifdef CONFIG_NET_DSA_HWMON
572 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
574 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
580 mutex_lock(&ps->phy_mutex);
582 ret = mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
586 /* Enable temperature sensor */
587 ret = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
591 ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
595 /* Wait for temperature to stabilize */
596 usleep_range(10000, 12000);
598 val = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
604 /* Disable temperature sensor */
605 ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
609 *temp = ((val & 0x1f) - 5) * 5;
612 mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
613 mutex_unlock(&ps->phy_mutex);
616 #endif /* CONFIG_NET_DSA_HWMON */
618 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
620 unsigned long timeout = jiffies + HZ / 10;
622 while (time_before(jiffies, timeout)) {
625 ret = REG_READ(reg, offset);
629 usleep_range(1000, 2000);
634 int mv88e6xxx_phy_wait(struct dsa_switch *ds)
636 return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x18, 0x8000);
639 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
641 return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x0800);
644 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
646 return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x8000);
649 /* Must be called with SMI lock held */
650 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
652 unsigned long timeout = jiffies + HZ / 10;
654 while (time_before(jiffies, timeout)) {
657 ret = _mv88e6xxx_reg_read(ds, reg, offset);
663 usleep_range(1000, 2000);
668 /* Must be called with SMI lock held */
669 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
671 return _mv88e6xxx_wait(ds, REG_GLOBAL, 0x0b, ATU_BUSY);
674 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum)
678 REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 | (addr << 5) | regnum);
680 ret = mv88e6xxx_phy_wait(ds);
684 return REG_READ(REG_GLOBAL2, 0x19);
687 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
690 REG_WRITE(REG_GLOBAL2, 0x19, val);
691 REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 | (addr << 5) | regnum);
693 return mv88e6xxx_phy_wait(ds);
696 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
700 reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
704 e->eee_enabled = !!(reg & 0x0200);
705 e->tx_lpi_enabled = !!(reg & 0x0100);
707 reg = REG_READ(REG_PORT(port), 0);
708 e->eee_active = !!(reg & 0x0040);
713 static int mv88e6xxx_eee_enable_set(struct dsa_switch *ds, int port,
714 bool eee_enabled, bool tx_lpi_enabled)
718 reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
722 nreg = reg & ~0x0300;
729 return mv88e6xxx_phy_write_indirect(ds, port, 16, nreg);
734 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
735 struct phy_device *phydev, struct ethtool_eee *e)
739 ret = mv88e6xxx_eee_enable_set(ds, port, e->eee_enabled,
747 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
751 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid);
755 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x0b, cmd);
759 return _mv88e6xxx_atu_wait(ds);
762 static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
766 ret = _mv88e6xxx_atu_wait(ds);
770 return _mv88e6xxx_atu_cmd(ds, fid, ATU_CMD_FLUSH_NONSTATIC_FID);
773 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
775 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
779 mutex_lock(&ps->smi_mutex);
781 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), 0x04);
785 oldstate = reg & PSTATE_MASK;
786 if (oldstate != state) {
787 /* Flush forwarding database if we're moving a port
788 * from Learning or Forwarding state to Disabled or
789 * Blocking or Listening state.
791 if (oldstate >= PSTATE_LEARNING && state <= PSTATE_BLOCKING) {
792 ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
796 reg = (reg & ~PSTATE_MASK) | state;
797 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x04, reg);
801 mutex_unlock(&ps->smi_mutex);
805 /* Must be called with smi lock held */
806 static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
808 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
809 u8 fid = ps->fid[port];
812 if (dsa_is_cpu_port(ds, port))
813 reg |= ds->phys_port_mask;
815 reg |= (ps->bridge_mask[fid] |
816 (1 << dsa_upstream_port(ds))) & ~(1 << port);
818 return _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x06, reg);
821 /* Must be called with smi lock held */
822 static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
824 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
829 mask = ds->phys_port_mask;
832 mask &= ~(1 << port);
833 if (ps->fid[port] != fid)
836 ret = _mv88e6xxx_update_port_config(ds, port);
841 return _mv88e6xxx_flush_fid(ds, fid);
844 /* Bridge handling functions */
846 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
848 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
853 /* If the bridge group is not empty, join that group.
854 * Otherwise create a new group.
857 nmask = br_port_mask & ~(1 << port);
859 fid = ps->fid[__ffs(nmask)];
861 nmask = ps->bridge_mask[fid] | (1 << port);
862 if (nmask != br_port_mask) {
863 netdev_err(ds->ports[port],
864 "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
865 fid, br_port_mask, nmask);
869 mutex_lock(&ps->smi_mutex);
871 ps->bridge_mask[fid] = br_port_mask;
873 if (fid != ps->fid[port]) {
874 ps->fid_mask |= 1 << ps->fid[port];
876 ret = _mv88e6xxx_update_bridge_config(ds, fid);
879 mutex_unlock(&ps->smi_mutex);
884 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
886 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
892 if (ps->bridge_mask[fid] != br_port_mask) {
893 netdev_err(ds->ports[port],
894 "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
895 fid, br_port_mask, ps->bridge_mask[fid]);
899 /* If the port was the last port of a bridge, we are done.
900 * Otherwise assign a new fid to the port, and fix up
901 * the bridge configuration.
903 if (br_port_mask == (1 << port))
906 mutex_lock(&ps->smi_mutex);
908 newfid = __ffs(ps->fid_mask);
909 ps->fid[port] = newfid;
910 ps->fid_mask &= (1 << newfid);
911 ps->bridge_mask[fid] &= ~(1 << port);
912 ps->bridge_mask[newfid] = 1 << port;
914 ret = _mv88e6xxx_update_bridge_config(ds, fid);
916 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
918 mutex_unlock(&ps->smi_mutex);
923 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
925 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
929 case BR_STATE_DISABLED:
930 stp_state = PSTATE_DISABLED;
932 case BR_STATE_BLOCKING:
933 case BR_STATE_LISTENING:
934 stp_state = PSTATE_BLOCKING;
936 case BR_STATE_LEARNING:
937 stp_state = PSTATE_LEARNING;
939 case BR_STATE_FORWARDING:
941 stp_state = PSTATE_FORWARDING;
945 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
947 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
948 * so we can not update the port state directly but need to schedule it.
950 ps->port_state[port] = stp_state;
951 set_bit(port, &ps->port_state_update_mask);
952 schedule_work(&ps->bridge_work);
957 static int __mv88e6xxx_write_addr(struct dsa_switch *ds,
958 const unsigned char *addr)
962 for (i = 0; i < 3; i++) {
963 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x0d + i,
964 (addr[i * 2] << 8) | addr[i * 2 + 1]);
972 static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr)
976 for (i = 0; i < 3; i++) {
977 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x0d + i);
980 addr[i * 2] = ret >> 8;
981 addr[i * 2 + 1] = ret & 0xff;
987 static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port,
988 const unsigned char *addr, int state)
990 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
991 u8 fid = ps->fid[port];
994 ret = _mv88e6xxx_atu_wait(ds);
998 ret = __mv88e6xxx_write_addr(ds, addr);
1002 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x0c,
1003 (0x10 << port) | state);
1007 ret = _mv88e6xxx_atu_cmd(ds, fid, ATU_CMD_LOAD_FID);
1012 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1013 const unsigned char *addr, u16 vid)
1015 int state = is_multicast_ether_addr(addr) ?
1016 FDB_STATE_MC_STATIC : FDB_STATE_STATIC;
1017 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1020 mutex_lock(&ps->smi_mutex);
1021 ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state);
1022 mutex_unlock(&ps->smi_mutex);
1027 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1028 const unsigned char *addr, u16 vid)
1030 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1033 mutex_lock(&ps->smi_mutex);
1034 ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, FDB_STATE_UNUSED);
1035 mutex_unlock(&ps->smi_mutex);
1040 static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port,
1041 unsigned char *addr, bool *is_static)
1043 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1044 u8 fid = ps->fid[port];
1047 ret = _mv88e6xxx_atu_wait(ds);
1051 ret = __mv88e6xxx_write_addr(ds, addr);
1056 ret = _mv88e6xxx_atu_cmd(ds, fid, ATU_CMD_GETNEXT_FID);
1060 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x0c);
1063 state = ret & FDB_STATE_MASK;
1064 if (state == FDB_STATE_UNUSED)
1066 } while (!(((ret >> 4) & 0xff) & (1 << port)));
1068 ret = __mv88e6xxx_read_addr(ds, addr);
1072 *is_static = state == (is_multicast_ether_addr(addr) ?
1073 FDB_STATE_MC_STATIC : FDB_STATE_STATIC);
1078 /* get next entry for port */
1079 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
1080 unsigned char *addr, bool *is_static)
1082 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1085 mutex_lock(&ps->smi_mutex);
1086 ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static);
1087 mutex_unlock(&ps->smi_mutex);
1092 static void mv88e6xxx_bridge_work(struct work_struct *work)
1094 struct mv88e6xxx_priv_state *ps;
1095 struct dsa_switch *ds;
1098 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1099 ds = ((struct dsa_switch *)ps) - 1;
1101 while (ps->port_state_update_mask) {
1102 port = __ffs(ps->port_state_update_mask);
1103 clear_bit(port, &ps->port_state_update_mask);
1104 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1108 int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port)
1110 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1113 mutex_lock(&ps->smi_mutex);
1115 /* Port Control 1: disable trunking, disable sending
1116 * learning messages to this port.
1118 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x05, 0x0000);
1122 /* Port based VLAN map: give each port its own address
1123 * database, allow the CPU port to talk to each of the 'real'
1124 * ports, and allow each of the 'real' ports to only talk to
1125 * the upstream port.
1127 fid = __ffs(ps->fid_mask);
1128 ps->fid[port] = fid;
1129 ps->fid_mask &= ~(1 << fid);
1131 if (!dsa_is_cpu_port(ds, port))
1132 ps->bridge_mask[fid] = 1 << port;
1134 ret = _mv88e6xxx_update_port_config(ds, port);
1138 /* Default VLAN ID and priority: don't set a default VLAN
1139 * ID, and set the default packet priority to zero.
1141 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x07, 0x0000);
1143 mutex_unlock(&ps->smi_mutex);
1147 int mv88e6xxx_setup_common(struct dsa_switch *ds)
1149 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1151 mutex_init(&ps->smi_mutex);
1152 mutex_init(&ps->stats_mutex);
1153 mutex_init(&ps->phy_mutex);
1155 ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
1157 ps->fid_mask = (1 << DSA_MAX_PORTS) - 1;
1159 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
1164 static int __init mv88e6xxx_init(void)
1166 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1167 register_switch_driver(&mv88e6131_switch_driver);
1169 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1170 register_switch_driver(&mv88e6123_61_65_switch_driver);
1172 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
1173 register_switch_driver(&mv88e6352_switch_driver);
1175 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1176 register_switch_driver(&mv88e6171_switch_driver);
1180 module_init(mv88e6xxx_init);
1182 static void __exit mv88e6xxx_cleanup(void)
1184 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1185 unregister_switch_driver(&mv88e6171_switch_driver);
1187 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1188 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
1190 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1191 unregister_switch_driver(&mv88e6131_switch_driver);
1194 module_exit(mv88e6xxx_cleanup);
1196 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
1197 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
1198 MODULE_LICENSE("GPL");