2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/debugfs.h>
12 #include <linux/delay.h>
13 #include <linux/etherdevice.h>
14 #include <linux/if_bridge.h>
15 #include <linux/jiffies.h>
16 #include <linux/list.h>
17 #include <linux/module.h>
18 #include <linux/netdevice.h>
19 #include <linux/phy.h>
20 #include <linux/seq_file.h>
22 #include "mv88e6xxx.h"
24 /* MDIO bus access can be nested in the case of PHYs connected to the
25 * internal MDIO bus of the switch, which is accessed via MDIO bus of
26 * the Ethernet interface. Avoid lockdep false positives by using
27 * mutex_lock_nested().
29 static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
33 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
34 ret = bus->read(bus, addr, regnum);
35 mutex_unlock(&bus->mdio_lock);
40 static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum,
45 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
46 ret = bus->write(bus, addr, regnum, val);
47 mutex_unlock(&bus->mdio_lock);
52 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
53 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
54 * will be directly accessible on some {device address,register address}
55 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
56 * will only respond to SMI transactions to that specific address, and
57 * an indirect addressing mechanism needs to be used to access its
60 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
65 for (i = 0; i < 16; i++) {
66 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD);
70 if ((ret & SMI_CMD_BUSY) == 0)
77 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
82 return mv88e6xxx_mdiobus_read(bus, addr, reg);
84 /* Wait for the bus to become free. */
85 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
89 /* Transmit the read command. */
90 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
91 SMI_CMD_OP_22_READ | (addr << 5) | reg);
95 /* Wait for the read command to complete. */
96 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
101 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA);
108 /* Must be called with SMI mutex held */
109 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
111 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
117 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
121 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
127 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
129 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
132 mutex_lock(&ps->smi_mutex);
133 ret = _mv88e6xxx_reg_read(ds, addr, reg);
134 mutex_unlock(&ps->smi_mutex);
139 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
145 return mv88e6xxx_mdiobus_write(bus, addr, reg, val);
147 /* Wait for the bus to become free. */
148 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
152 /* Transmit the data to write. */
153 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val);
157 /* Transmit the write command. */
158 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
159 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
163 /* Wait for the write command to complete. */
164 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
171 /* Must be called with SMI mutex held */
172 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
175 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
180 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
183 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
186 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
188 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
191 mutex_lock(&ps->smi_mutex);
192 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
193 mutex_unlock(&ps->smi_mutex);
198 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
200 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
201 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
202 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
207 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
212 for (i = 0; i < 6; i++) {
215 /* Write the MAC address byte. */
216 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
217 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
219 /* Wait for the write to complete. */
220 for (j = 0; j < 16; j++) {
221 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
222 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
232 /* Must be called with SMI mutex held */
233 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
236 return _mv88e6xxx_reg_read(ds, addr, regnum);
240 /* Must be called with SMI mutex held */
241 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
245 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
249 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
250 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
253 unsigned long timeout;
255 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
256 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
257 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
259 timeout = jiffies + 1 * HZ;
260 while (time_before(jiffies, timeout)) {
261 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
262 usleep_range(1000, 2000);
263 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
264 GLOBAL_STATUS_PPU_POLLING)
271 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
274 unsigned long timeout;
276 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
277 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
279 timeout = jiffies + 1 * HZ;
280 while (time_before(jiffies, timeout)) {
281 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
282 usleep_range(1000, 2000);
283 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
284 GLOBAL_STATUS_PPU_POLLING)
291 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
293 struct mv88e6xxx_priv_state *ps;
295 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
296 if (mutex_trylock(&ps->ppu_mutex)) {
297 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
299 if (mv88e6xxx_ppu_enable(ds) == 0)
300 ps->ppu_disabled = 0;
301 mutex_unlock(&ps->ppu_mutex);
305 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
307 struct mv88e6xxx_priv_state *ps = (void *)_ps;
309 schedule_work(&ps->ppu_work);
312 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
314 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
317 mutex_lock(&ps->ppu_mutex);
319 /* If the PHY polling unit is enabled, disable it so that
320 * we can access the PHY registers. If it was already
321 * disabled, cancel the timer that is going to re-enable
324 if (!ps->ppu_disabled) {
325 ret = mv88e6xxx_ppu_disable(ds);
327 mutex_unlock(&ps->ppu_mutex);
330 ps->ppu_disabled = 1;
332 del_timer(&ps->ppu_timer);
339 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
341 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
343 /* Schedule a timer to re-enable the PHY polling unit. */
344 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
345 mutex_unlock(&ps->ppu_mutex);
348 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
350 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
352 mutex_init(&ps->ppu_mutex);
353 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
354 init_timer(&ps->ppu_timer);
355 ps->ppu_timer.data = (unsigned long)ps;
356 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
359 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
363 ret = mv88e6xxx_ppu_access_get(ds);
365 ret = mv88e6xxx_reg_read(ds, addr, regnum);
366 mv88e6xxx_ppu_access_put(ds);
372 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
377 ret = mv88e6xxx_ppu_access_get(ds);
379 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
380 mv88e6xxx_ppu_access_put(ds);
387 void mv88e6xxx_poll_link(struct dsa_switch *ds)
391 for (i = 0; i < DSA_MAX_PORTS; i++) {
392 struct net_device *dev;
393 int uninitialized_var(port_status);
404 if (dev->flags & IFF_UP) {
405 port_status = mv88e6xxx_reg_read(ds, REG_PORT(i),
410 link = !!(port_status & PORT_STATUS_LINK);
414 if (netif_carrier_ok(dev)) {
415 netdev_info(dev, "link down\n");
416 netif_carrier_off(dev);
421 switch (port_status & PORT_STATUS_SPEED_MASK) {
422 case PORT_STATUS_SPEED_10:
425 case PORT_STATUS_SPEED_100:
428 case PORT_STATUS_SPEED_1000:
435 duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0;
436 fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0;
438 if (!netif_carrier_ok(dev)) {
440 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
442 duplex ? "full" : "half",
444 netif_carrier_on(dev);
449 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
451 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
454 case PORT_SWITCH_ID_6031:
455 case PORT_SWITCH_ID_6061:
456 case PORT_SWITCH_ID_6035:
457 case PORT_SWITCH_ID_6065:
463 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
465 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
468 case PORT_SWITCH_ID_6092:
469 case PORT_SWITCH_ID_6095:
475 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
477 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
480 case PORT_SWITCH_ID_6046:
481 case PORT_SWITCH_ID_6085:
482 case PORT_SWITCH_ID_6096:
483 case PORT_SWITCH_ID_6097:
489 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
491 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
494 case PORT_SWITCH_ID_6123:
495 case PORT_SWITCH_ID_6161:
496 case PORT_SWITCH_ID_6165:
502 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
504 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
507 case PORT_SWITCH_ID_6121:
508 case PORT_SWITCH_ID_6122:
509 case PORT_SWITCH_ID_6152:
510 case PORT_SWITCH_ID_6155:
511 case PORT_SWITCH_ID_6182:
512 case PORT_SWITCH_ID_6185:
513 case PORT_SWITCH_ID_6108:
514 case PORT_SWITCH_ID_6131:
520 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
522 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
525 case PORT_SWITCH_ID_6320:
526 case PORT_SWITCH_ID_6321:
532 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
534 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
537 case PORT_SWITCH_ID_6171:
538 case PORT_SWITCH_ID_6175:
539 case PORT_SWITCH_ID_6350:
540 case PORT_SWITCH_ID_6351:
546 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
548 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
551 case PORT_SWITCH_ID_6172:
552 case PORT_SWITCH_ID_6176:
553 case PORT_SWITCH_ID_6240:
554 case PORT_SWITCH_ID_6352:
560 /* Must be called with SMI mutex held */
561 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
566 for (i = 0; i < 10; i++) {
567 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
568 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
575 /* Must be called with SMI mutex held */
576 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
580 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
581 port = (port + 1) << 5;
583 /* Snapshot the hardware statistics counters for this port. */
584 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
585 GLOBAL_STATS_OP_CAPTURE_PORT |
586 GLOBAL_STATS_OP_HIST_RX_TX | port);
590 /* Wait for the snapshotting to complete. */
591 ret = _mv88e6xxx_stats_wait(ds);
598 /* Must be called with SMI mutex held */
599 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
606 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
607 GLOBAL_STATS_OP_READ_CAPTURED |
608 GLOBAL_STATS_OP_HIST_RX_TX | stat);
612 ret = _mv88e6xxx_stats_wait(ds);
616 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
622 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
629 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
630 { "in_good_octets", 8, 0x00, },
631 { "in_bad_octets", 4, 0x02, },
632 { "in_unicast", 4, 0x04, },
633 { "in_broadcasts", 4, 0x06, },
634 { "in_multicasts", 4, 0x07, },
635 { "in_pause", 4, 0x16, },
636 { "in_undersize", 4, 0x18, },
637 { "in_fragments", 4, 0x19, },
638 { "in_oversize", 4, 0x1a, },
639 { "in_jabber", 4, 0x1b, },
640 { "in_rx_error", 4, 0x1c, },
641 { "in_fcs_error", 4, 0x1d, },
642 { "out_octets", 8, 0x0e, },
643 { "out_unicast", 4, 0x10, },
644 { "out_broadcasts", 4, 0x13, },
645 { "out_multicasts", 4, 0x12, },
646 { "out_pause", 4, 0x15, },
647 { "excessive", 4, 0x11, },
648 { "collisions", 4, 0x1e, },
649 { "deferred", 4, 0x05, },
650 { "single", 4, 0x14, },
651 { "multiple", 4, 0x17, },
652 { "out_fcs_error", 4, 0x03, },
653 { "late", 4, 0x1f, },
654 { "hist_64bytes", 4, 0x08, },
655 { "hist_65_127bytes", 4, 0x09, },
656 { "hist_128_255bytes", 4, 0x0a, },
657 { "hist_256_511bytes", 4, 0x0b, },
658 { "hist_512_1023bytes", 4, 0x0c, },
659 { "hist_1024_max_bytes", 4, 0x0d, },
660 /* Not all devices have the following counters */
661 { "sw_in_discards", 4, 0x110, },
662 { "sw_in_filtered", 2, 0x112, },
663 { "sw_out_filtered", 2, 0x113, },
667 static bool have_sw_in_discards(struct dsa_switch *ds)
669 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
672 case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
673 case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
674 case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
675 case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
676 case PORT_SWITCH_ID_6352:
683 static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
685 struct mv88e6xxx_hw_stat *stats,
686 int port, uint8_t *data)
690 for (i = 0; i < nr_stats; i++) {
691 memcpy(data + i * ETH_GSTRING_LEN,
692 stats[i].string, ETH_GSTRING_LEN);
696 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
698 struct mv88e6xxx_hw_stat *stats,
701 struct mv88e6xxx_hw_stat *s = stats + stat;
707 if (s->reg >= 0x100) {
708 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
714 if (s->sizeof_stat == 4) {
715 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
722 _mv88e6xxx_stats_read(ds, s->reg, &low);
723 if (s->sizeof_stat == 8)
724 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
726 value = (((u64)high) << 16) | low;
730 static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
732 struct mv88e6xxx_hw_stat *stats,
733 int port, uint64_t *data)
735 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
739 mutex_lock(&ps->smi_mutex);
741 ret = _mv88e6xxx_stats_snapshot(ds, port);
743 mutex_unlock(&ps->smi_mutex);
747 /* Read each of the counters. */
748 for (i = 0; i < nr_stats; i++)
749 data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port);
751 mutex_unlock(&ps->smi_mutex);
754 /* All the statistics in the table */
756 mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
758 if (have_sw_in_discards(ds))
759 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
760 mv88e6xxx_hw_stats, port, data);
762 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
763 mv88e6xxx_hw_stats, port, data);
766 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
768 if (have_sw_in_discards(ds))
769 return ARRAY_SIZE(mv88e6xxx_hw_stats);
770 return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
774 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
775 int port, uint64_t *data)
777 if (have_sw_in_discards(ds))
778 _mv88e6xxx_get_ethtool_stats(
779 ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
780 mv88e6xxx_hw_stats, port, data);
782 _mv88e6xxx_get_ethtool_stats(
783 ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
784 mv88e6xxx_hw_stats, port, data);
787 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
789 return 32 * sizeof(u16);
792 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
793 struct ethtool_regs *regs, void *_p)
800 memset(p, 0xff, 32 * sizeof(u16));
802 for (i = 0; i < 32; i++) {
805 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
811 /* Must be called with SMI lock held */
812 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
815 unsigned long timeout = jiffies + HZ / 10;
817 while (time_before(jiffies, timeout)) {
820 ret = _mv88e6xxx_reg_read(ds, reg, offset);
826 usleep_range(1000, 2000);
831 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
833 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
836 mutex_lock(&ps->smi_mutex);
837 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
838 mutex_unlock(&ps->smi_mutex);
843 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
845 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
846 GLOBAL2_SMI_OP_BUSY);
849 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
851 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
852 GLOBAL2_EEPROM_OP_LOAD);
855 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
857 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
858 GLOBAL2_EEPROM_OP_BUSY);
861 /* Must be called with SMI lock held */
862 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
864 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
868 /* Must be called with SMI lock held */
869 static int _mv88e6xxx_scratch_wait(struct dsa_switch *ds)
871 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
872 GLOBAL2_SCRATCH_BUSY);
875 /* Must be called with SMI mutex held */
876 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
881 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
882 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
887 ret = _mv88e6xxx_phy_wait(ds);
891 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
894 /* Must be called with SMI mutex held */
895 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
900 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
904 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
905 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
908 return _mv88e6xxx_phy_wait(ds);
911 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
913 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
916 mutex_lock(&ps->smi_mutex);
918 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
922 e->eee_enabled = !!(reg & 0x0200);
923 e->tx_lpi_enabled = !!(reg & 0x0100);
925 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
929 e->eee_active = !!(reg & PORT_STATUS_EEE);
933 mutex_unlock(&ps->smi_mutex);
937 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
938 struct phy_device *phydev, struct ethtool_eee *e)
940 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
944 mutex_lock(&ps->smi_mutex);
946 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
953 if (e->tx_lpi_enabled)
956 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
958 mutex_unlock(&ps->smi_mutex);
963 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
967 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
971 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
975 return _mv88e6xxx_atu_wait(ds);
978 static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
982 ret = _mv88e6xxx_atu_wait(ds);
986 return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB);
989 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
991 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
995 mutex_lock(&ps->smi_mutex);
997 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1003 oldstate = reg & PORT_CONTROL_STATE_MASK;
1004 if (oldstate != state) {
1005 /* Flush forwarding database if we're moving a port
1006 * from Learning or Forwarding state to Disabled or
1007 * Blocking or Listening state.
1009 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1010 state <= PORT_CONTROL_STATE_BLOCKING) {
1011 ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
1015 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1016 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1021 mutex_unlock(&ps->smi_mutex);
1025 /* Must be called with smi lock held */
1026 static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
1028 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1029 u8 fid = ps->fid[port];
1030 u16 reg = fid << 12;
1032 if (dsa_is_cpu_port(ds, port))
1033 reg |= ds->phys_port_mask;
1035 reg |= (ps->bridge_mask[fid] |
1036 (1 << dsa_upstream_port(ds))) & ~(1 << port);
1038 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1041 /* Must be called with smi lock held */
1042 static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
1044 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1049 mask = ds->phys_port_mask;
1052 mask &= ~(1 << port);
1053 if (ps->fid[port] != fid)
1056 ret = _mv88e6xxx_update_port_config(ds, port);
1061 return _mv88e6xxx_flush_fid(ds, fid);
1064 /* Bridge handling functions */
1066 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1068 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1073 /* If the bridge group is not empty, join that group.
1074 * Otherwise create a new group.
1076 fid = ps->fid[port];
1077 nmask = br_port_mask & ~(1 << port);
1079 fid = ps->fid[__ffs(nmask)];
1081 nmask = ps->bridge_mask[fid] | (1 << port);
1082 if (nmask != br_port_mask) {
1083 netdev_err(ds->ports[port],
1084 "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1085 fid, br_port_mask, nmask);
1089 mutex_lock(&ps->smi_mutex);
1091 ps->bridge_mask[fid] = br_port_mask;
1093 if (fid != ps->fid[port]) {
1094 clear_bit(ps->fid[port], ps->fid_bitmap);
1095 ps->fid[port] = fid;
1096 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1099 mutex_unlock(&ps->smi_mutex);
1104 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1106 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1110 fid = ps->fid[port];
1112 if (ps->bridge_mask[fid] != br_port_mask) {
1113 netdev_err(ds->ports[port],
1114 "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1115 fid, br_port_mask, ps->bridge_mask[fid]);
1119 /* If the port was the last port of a bridge, we are done.
1120 * Otherwise assign a new fid to the port, and fix up
1121 * the bridge configuration.
1123 if (br_port_mask == (1 << port))
1126 mutex_lock(&ps->smi_mutex);
1128 newfid = find_next_zero_bit(ps->fid_bitmap, VLAN_N_VID, 1);
1129 if (unlikely(newfid > ps->num_ports)) {
1130 netdev_err(ds->ports[port], "all first %d FIDs are used\n",
1136 ps->fid[port] = newfid;
1137 set_bit(newfid, ps->fid_bitmap);
1138 ps->bridge_mask[fid] &= ~(1 << port);
1139 ps->bridge_mask[newfid] = 1 << port;
1141 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1143 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
1146 mutex_unlock(&ps->smi_mutex);
1151 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1153 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1157 case BR_STATE_DISABLED:
1158 stp_state = PORT_CONTROL_STATE_DISABLED;
1160 case BR_STATE_BLOCKING:
1161 case BR_STATE_LISTENING:
1162 stp_state = PORT_CONTROL_STATE_BLOCKING;
1164 case BR_STATE_LEARNING:
1165 stp_state = PORT_CONTROL_STATE_LEARNING;
1167 case BR_STATE_FORWARDING:
1169 stp_state = PORT_CONTROL_STATE_FORWARDING;
1173 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1175 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1176 * so we can not update the port state directly but need to schedule it.
1178 ps->port_state[port] = stp_state;
1179 set_bit(port, &ps->port_state_update_mask);
1180 schedule_work(&ps->bridge_work);
1185 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1187 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1188 GLOBAL_VTU_OP_BUSY);
1191 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1195 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1199 return _mv88e6xxx_vtu_wait(ds);
1202 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1206 ret = _mv88e6xxx_vtu_wait(ds);
1210 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1213 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1214 const unsigned char *addr)
1218 for (i = 0; i < 3; i++) {
1219 ret = _mv88e6xxx_reg_write(
1220 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1221 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1229 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
1233 for (i = 0; i < 3; i++) {
1234 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1235 GLOBAL_ATU_MAC_01 + i);
1238 addr[i * 2] = ret >> 8;
1239 addr[i * 2 + 1] = ret & 0xff;
1245 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1246 struct mv88e6xxx_atu_entry *entry)
1251 ret = _mv88e6xxx_atu_wait(ds);
1255 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
1259 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1260 unsigned int mask, shift;
1263 reg |= GLOBAL_ATU_DATA_TRUNK;
1264 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1265 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1267 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1268 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1271 reg |= (entry->portv_trunkid << shift) & mask;
1274 reg |= entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1276 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, reg);
1280 return _mv88e6xxx_atu_cmd(ds, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
1283 static int _mv88e6xxx_port_vid_to_fid(struct dsa_switch *ds, int port, u16 vid)
1285 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1288 return ps->fid[port];
1293 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1294 const unsigned char *addr, u16 vid,
1297 struct mv88e6xxx_atu_entry entry = { 0 };
1300 ret = _mv88e6xxx_port_vid_to_fid(ds, port, vid);
1305 entry.state = state;
1306 ether_addr_copy(entry.mac, addr);
1307 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1308 entry.trunk = false;
1309 entry.portv_trunkid = BIT(port);
1312 return _mv88e6xxx_atu_load(ds, &entry);
1315 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1316 const unsigned char *addr, u16 vid)
1318 int state = is_multicast_ether_addr(addr) ?
1319 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1320 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1321 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1324 mutex_lock(&ps->smi_mutex);
1325 ret = _mv88e6xxx_port_fdb_load(ds, port, addr, vid, state);
1326 mutex_unlock(&ps->smi_mutex);
1331 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1332 const unsigned char *addr, u16 vid)
1334 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1337 mutex_lock(&ps->smi_mutex);
1338 ret = _mv88e6xxx_port_fdb_load(ds, port, addr, vid,
1339 GLOBAL_ATU_DATA_STATE_UNUSED);
1340 mutex_unlock(&ps->smi_mutex);
1345 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1346 const unsigned char *addr,
1347 struct mv88e6xxx_atu_entry *entry)
1349 struct mv88e6xxx_atu_entry next = { 0 };
1354 ret = _mv88e6xxx_atu_wait(ds);
1358 ret = _mv88e6xxx_atu_mac_write(ds, addr);
1362 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1366 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
1370 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1374 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1375 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1376 unsigned int mask, shift;
1378 if (ret & GLOBAL_ATU_DATA_TRUNK) {
1380 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1381 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1384 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1385 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1388 next.portv_trunkid = (ret & mask) >> shift;
1395 /* get next entry for port */
1396 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
1397 unsigned char *addr, u16 *vid, bool *is_static)
1399 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1400 struct mv88e6xxx_atu_entry next;
1404 mutex_lock(&ps->smi_mutex);
1406 ret = _mv88e6xxx_port_vid_to_fid(ds, port, *vid);
1412 if (is_broadcast_ether_addr(addr)) {
1417 ret = _mv88e6xxx_atu_getnext(ds, fid, addr, &next);
1421 ether_addr_copy(addr, next.mac);
1423 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1425 } while (next.trunk || (next.portv_trunkid & BIT(port)) == 0);
1427 *is_static = next.state == (is_multicast_ether_addr(addr) ?
1428 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1429 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1431 mutex_unlock(&ps->smi_mutex);
1436 static void mv88e6xxx_bridge_work(struct work_struct *work)
1438 struct mv88e6xxx_priv_state *ps;
1439 struct dsa_switch *ds;
1442 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1443 ds = ((struct dsa_switch *)ps) - 1;
1445 while (ps->port_state_update_mask) {
1446 port = __ffs(ps->port_state_update_mask);
1447 clear_bit(port, &ps->port_state_update_mask);
1448 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1452 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
1454 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1458 mutex_lock(&ps->smi_mutex);
1460 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1461 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1462 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1463 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
1464 /* MAC Forcing register: don't force link, speed,
1465 * duplex or flow control state to any particular
1466 * values on physical ports, but force the CPU port
1467 * and all DSA ports to their maximum bandwidth and
1470 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
1471 if (dsa_is_cpu_port(ds, port) ||
1472 ds->dsa_port_mask & (1 << port)) {
1473 reg |= PORT_PCS_CTRL_FORCE_LINK |
1474 PORT_PCS_CTRL_LINK_UP |
1475 PORT_PCS_CTRL_DUPLEX_FULL |
1476 PORT_PCS_CTRL_FORCE_DUPLEX;
1477 if (mv88e6xxx_6065_family(ds))
1478 reg |= PORT_PCS_CTRL_100;
1480 reg |= PORT_PCS_CTRL_1000;
1482 reg |= PORT_PCS_CTRL_UNFORCED;
1485 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1486 PORT_PCS_CTRL, reg);
1491 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1492 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1493 * tunneling, determine priority by looking at 802.1p and IP
1494 * priority fields (IP prio has precedence), and set STP state
1497 * If this is the CPU link, use DSA or EDSA tagging depending
1498 * on which tagging mode was configured.
1500 * If this is a link to another switch, use DSA tagging mode.
1502 * If this is the upstream port for this switch, enable
1503 * forwarding of unknown unicasts and multicasts.
1506 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1507 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1508 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1509 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
1510 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
1511 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
1512 PORT_CONTROL_STATE_FORWARDING;
1513 if (dsa_is_cpu_port(ds, port)) {
1514 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1515 reg |= PORT_CONTROL_DSA_TAG;
1516 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1517 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1518 mv88e6xxx_6320_family(ds)) {
1519 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1520 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
1522 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1525 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1526 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1527 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1528 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
1529 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1530 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
1533 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1534 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1535 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1536 mv88e6xxx_6320_family(ds)) {
1537 if (ds->dsa_port_mask & (1 << port))
1538 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1539 if (port == dsa_upstream_port(ds))
1540 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
1541 PORT_CONTROL_FORWARD_UNKNOWN_MC;
1544 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1550 /* Port Control 2: don't force a good FCS, set the maximum
1551 * frame size to 10240 bytes, don't let the switch add or
1552 * strip 802.1q tags, don't discard tagged or untagged frames
1553 * on this port, do a destination address lookup on all
1554 * received packets as usual, disable ARP mirroring and don't
1555 * send a copy of all transmitted/received frames on this port
1559 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1560 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1561 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
1562 reg = PORT_CONTROL_2_MAP_DA;
1564 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1565 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
1566 reg |= PORT_CONTROL_2_JUMBO_10240;
1568 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
1569 /* Set the upstream port this port should use */
1570 reg |= dsa_upstream_port(ds);
1571 /* enable forwarding of unknown multicast addresses to
1574 if (port == dsa_upstream_port(ds))
1575 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
1579 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1580 PORT_CONTROL_2, reg);
1585 /* Port Association Vector: when learning source addresses
1586 * of packets, add the address to the address database using
1587 * a port bitmap that has only the bit for this port set and
1588 * the other bits clear.
1590 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
1595 /* Egress rate control 2: disable egress rate control. */
1596 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
1601 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1602 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1603 mv88e6xxx_6320_family(ds)) {
1604 /* Do not limit the period of time that this port can
1605 * be paused for by the remote end or the period of
1606 * time that this port can pause the remote end.
1608 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1609 PORT_PAUSE_CTRL, 0x0000);
1613 /* Port ATU control: disable limiting the number of
1614 * address database entries that this port is allowed
1617 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1618 PORT_ATU_CONTROL, 0x0000);
1619 /* Priority Override: disable DA, SA and VTU priority
1622 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1623 PORT_PRI_OVERRIDE, 0x0000);
1627 /* Port Ethertype: use the Ethertype DSA Ethertype
1630 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1631 PORT_ETH_TYPE, ETH_P_EDSA);
1634 /* Tag Remap: use an identity 802.1p prio -> switch
1637 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1638 PORT_TAG_REGMAP_0123, 0x3210);
1642 /* Tag Remap 2: use an identity 802.1p prio -> switch
1645 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1646 PORT_TAG_REGMAP_4567, 0x7654);
1651 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1652 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1653 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1654 mv88e6xxx_6320_family(ds)) {
1655 /* Rate Control: disable ingress rate limiting. */
1656 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1657 PORT_RATE_CONTROL, 0x0001);
1662 /* Port Control 1: disable trunking, disable sending
1663 * learning messages to this port.
1665 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
1669 /* Port based VLAN map: give each port its own address
1670 * database, allow the CPU port to talk to each of the 'real'
1671 * ports, and allow each of the 'real' ports to only talk to
1672 * the upstream port.
1675 ps->fid[port] = fid;
1676 set_bit(fid, ps->fid_bitmap);
1678 if (!dsa_is_cpu_port(ds, port))
1679 ps->bridge_mask[fid] = 1 << port;
1681 ret = _mv88e6xxx_update_port_config(ds, port);
1685 /* Default VLAN ID and priority: don't set a default VLAN
1686 * ID, and set the default packet priority to zero.
1688 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1691 mutex_unlock(&ps->smi_mutex);
1695 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
1697 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1701 for (i = 0; i < ps->num_ports; i++) {
1702 ret = mv88e6xxx_setup_port(ds, i);
1709 static int mv88e6xxx_regs_show(struct seq_file *s, void *p)
1711 struct dsa_switch *ds = s->private;
1713 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1716 seq_puts(s, " GLOBAL GLOBAL2 ");
1717 for (port = 0 ; port < ps->num_ports; port++)
1718 seq_printf(s, " %2d ", port);
1721 for (reg = 0; reg < 32; reg++) {
1722 seq_printf(s, "%2x: ", reg);
1723 seq_printf(s, " %4x %4x ",
1724 mv88e6xxx_reg_read(ds, REG_GLOBAL, reg),
1725 mv88e6xxx_reg_read(ds, REG_GLOBAL2, reg));
1727 for (port = 0 ; port < ps->num_ports; port++)
1728 seq_printf(s, "%4x ",
1729 mv88e6xxx_reg_read(ds, REG_PORT(port), reg));
1736 static int mv88e6xxx_regs_open(struct inode *inode, struct file *file)
1738 return single_open(file, mv88e6xxx_regs_show, inode->i_private);
1741 static const struct file_operations mv88e6xxx_regs_fops = {
1742 .open = mv88e6xxx_regs_open,
1744 .llseek = no_llseek,
1745 .release = single_release,
1746 .owner = THIS_MODULE,
1749 static void mv88e6xxx_atu_show_header(struct seq_file *s)
1751 seq_puts(s, "DB T/P Vec State Addr\n");
1754 static void mv88e6xxx_atu_show_entry(struct seq_file *s, int dbnum,
1755 unsigned char *addr, int data)
1757 bool trunk = !!(data & GLOBAL_ATU_DATA_TRUNK);
1758 int portvec = ((data & GLOBAL_ATU_DATA_PORT_VECTOR_MASK) >>
1759 GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT);
1760 int state = data & GLOBAL_ATU_DATA_STATE_MASK;
1762 seq_printf(s, "%03x %5s %10pb %x %pM\n",
1763 dbnum, (trunk ? "Trunk" : "Port"), &portvec, state, addr);
1766 static int mv88e6xxx_atu_show_db(struct seq_file *s, struct dsa_switch *ds,
1769 unsigned char bcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
1770 unsigned char addr[6];
1771 int ret, data, state;
1773 ret = _mv88e6xxx_atu_mac_write(ds, bcast);
1778 ret = _mv88e6xxx_atu_cmd(ds, dbnum, GLOBAL_ATU_OP_GET_NEXT_DB);
1781 data = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1785 state = data & GLOBAL_ATU_DATA_STATE_MASK;
1786 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
1788 ret = _mv88e6xxx_atu_mac_read(ds, addr);
1791 mv88e6xxx_atu_show_entry(s, dbnum, addr, data);
1792 } while (state != GLOBAL_ATU_DATA_STATE_UNUSED);
1797 static int mv88e6xxx_atu_show(struct seq_file *s, void *p)
1799 struct dsa_switch *ds = s->private;
1800 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1803 mv88e6xxx_atu_show_header(s);
1805 for (dbnum = 0; dbnum < 255; dbnum++) {
1806 mutex_lock(&ps->smi_mutex);
1807 mv88e6xxx_atu_show_db(s, ds, dbnum);
1808 mutex_unlock(&ps->smi_mutex);
1814 static int mv88e6xxx_atu_open(struct inode *inode, struct file *file)
1816 return single_open(file, mv88e6xxx_atu_show, inode->i_private);
1819 static const struct file_operations mv88e6xxx_atu_fops = {
1820 .open = mv88e6xxx_atu_open,
1822 .llseek = no_llseek,
1823 .release = single_release,
1824 .owner = THIS_MODULE,
1827 static void mv88e6xxx_stats_show_header(struct seq_file *s,
1828 struct mv88e6xxx_priv_state *ps)
1832 seq_puts(s, " Statistic ");
1833 for (port = 0 ; port < ps->num_ports; port++)
1834 seq_printf(s, "Port %2d ", port);
1838 static int mv88e6xxx_stats_show(struct seq_file *s, void *p)
1840 struct dsa_switch *ds = s->private;
1841 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1842 struct mv88e6xxx_hw_stat *stats = mv88e6xxx_hw_stats;
1843 int port, stat, max_stats;
1846 if (have_sw_in_discards(ds))
1847 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats);
1849 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
1851 mv88e6xxx_stats_show_header(s, ps);
1853 mutex_lock(&ps->smi_mutex);
1855 for (stat = 0; stat < max_stats; stat++) {
1856 seq_printf(s, "%19s: ", stats[stat].string);
1857 for (port = 0 ; port < ps->num_ports; port++) {
1858 _mv88e6xxx_stats_snapshot(ds, port);
1859 value = _mv88e6xxx_get_ethtool_stat(ds, stat, stats,
1861 seq_printf(s, "%8llu ", value);
1865 mutex_unlock(&ps->smi_mutex);
1870 static int mv88e6xxx_stats_open(struct inode *inode, struct file *file)
1872 return single_open(file, mv88e6xxx_stats_show, inode->i_private);
1875 static const struct file_operations mv88e6xxx_stats_fops = {
1876 .open = mv88e6xxx_stats_open,
1878 .llseek = no_llseek,
1879 .release = single_release,
1880 .owner = THIS_MODULE,
1883 static int mv88e6xxx_device_map_show(struct seq_file *s, void *p)
1885 struct dsa_switch *ds = s->private;
1886 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1889 seq_puts(s, "Target Port\n");
1891 mutex_lock(&ps->smi_mutex);
1892 for (target = 0; target < 32; target++) {
1893 ret = _mv88e6xxx_reg_write(
1894 ds, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
1895 target << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT);
1898 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
1899 GLOBAL2_DEVICE_MAPPING);
1900 seq_printf(s, " %2d %2d\n", target,
1901 ret & GLOBAL2_DEVICE_MAPPING_PORT_MASK);
1904 mutex_unlock(&ps->smi_mutex);
1909 static int mv88e6xxx_device_map_open(struct inode *inode, struct file *file)
1911 return single_open(file, mv88e6xxx_device_map_show, inode->i_private);
1914 static const struct file_operations mv88e6xxx_device_map_fops = {
1915 .open = mv88e6xxx_device_map_open,
1917 .llseek = no_llseek,
1918 .release = single_release,
1919 .owner = THIS_MODULE,
1922 static int mv88e6xxx_scratch_show(struct seq_file *s, void *p)
1924 struct dsa_switch *ds = s->private;
1925 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1928 seq_puts(s, "Register Value\n");
1930 mutex_lock(&ps->smi_mutex);
1931 for (reg = 0; reg < 0x80; reg++) {
1932 ret = _mv88e6xxx_reg_write(
1933 ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
1934 reg << GLOBAL2_SCRATCH_REGISTER_SHIFT);
1938 ret = _mv88e6xxx_scratch_wait(ds);
1942 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
1943 GLOBAL2_SCRATCH_MISC);
1944 seq_printf(s, " %2x %2x\n", reg,
1945 ret & GLOBAL2_SCRATCH_VALUE_MASK);
1948 mutex_unlock(&ps->smi_mutex);
1953 static int mv88e6xxx_scratch_open(struct inode *inode, struct file *file)
1955 return single_open(file, mv88e6xxx_scratch_show, inode->i_private);
1958 static const struct file_operations mv88e6xxx_scratch_fops = {
1959 .open = mv88e6xxx_scratch_open,
1961 .llseek = no_llseek,
1962 .release = single_release,
1963 .owner = THIS_MODULE,
1966 int mv88e6xxx_setup_common(struct dsa_switch *ds)
1968 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1971 mutex_init(&ps->smi_mutex);
1973 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
1975 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
1977 name = kasprintf(GFP_KERNEL, "dsa%d", ds->index);
1978 ps->dbgfs = debugfs_create_dir(name, NULL);
1981 debugfs_create_file("regs", S_IRUGO, ps->dbgfs, ds,
1982 &mv88e6xxx_regs_fops);
1984 debugfs_create_file("atu", S_IRUGO, ps->dbgfs, ds,
1985 &mv88e6xxx_atu_fops);
1987 debugfs_create_file("stats", S_IRUGO, ps->dbgfs, ds,
1988 &mv88e6xxx_stats_fops);
1990 debugfs_create_file("device_map", S_IRUGO, ps->dbgfs, ds,
1991 &mv88e6xxx_device_map_fops);
1993 debugfs_create_file("scratch", S_IRUGO, ps->dbgfs, ds,
1994 &mv88e6xxx_scratch_fops);
1998 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2000 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2004 /* Set the default address aging time to 5 minutes, and
2005 * enable address learn messages to be sent to all message
2008 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2009 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2011 /* Configure the IP ToS mapping registers. */
2012 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2013 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2014 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2015 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2016 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2017 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2018 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2019 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2021 /* Configure the IEEE 802.1p priority mapping register. */
2022 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2024 /* Send all frames with destination addresses matching
2025 * 01:80:c2:00:00:0x to the CPU port.
2027 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2029 /* Ignore removed tag data on doubly tagged packets, disable
2030 * flow control messages, force flow control priority to the
2031 * highest, and send all special multicast frames to the CPU
2032 * port at the highest priority.
2034 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2035 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2036 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2038 /* Program the DSA routing table. */
2039 for (i = 0; i < 32; i++) {
2042 if (ds->pd->rtable &&
2043 i != ds->index && i < ds->dst->pd->nr_chips)
2044 nexthop = ds->pd->rtable[i] & 0x1f;
2046 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2047 GLOBAL2_DEVICE_MAPPING_UPDATE |
2048 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2052 /* Clear all trunk masks. */
2053 for (i = 0; i < 8; i++)
2054 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2055 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2056 ((1 << ps->num_ports) - 1));
2058 /* Clear all trunk mappings. */
2059 for (i = 0; i < 16; i++)
2060 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2061 GLOBAL2_TRUNK_MAPPING_UPDATE |
2062 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2064 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2065 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2066 mv88e6xxx_6320_family(ds)) {
2067 /* Send all frames with destination addresses matching
2068 * 01:80:c2:00:00:2x to the CPU port.
2070 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2072 /* Initialise cross-chip port VLAN table to reset
2075 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2077 /* Clear the priority override table. */
2078 for (i = 0; i < 16; i++)
2079 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2083 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2084 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2085 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2086 mv88e6xxx_6320_family(ds)) {
2087 /* Disable ingress rate limiting by resetting all
2088 * ingress rate limit registers to their initial
2091 for (i = 0; i < ps->num_ports; i++)
2092 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2096 /* Clear the statistics counters for all ports */
2097 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2099 /* Wait for the flush to complete. */
2100 mutex_lock(&ps->smi_mutex);
2101 ret = _mv88e6xxx_stats_wait(ds);
2105 /* Clear all the VTU and STU entries */
2106 ret = _mv88e6xxx_vtu_stu_flush(ds);
2108 mutex_unlock(&ps->smi_mutex);
2113 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2115 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2116 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2117 unsigned long timeout;
2121 /* Set all ports to the disabled state. */
2122 for (i = 0; i < ps->num_ports; i++) {
2123 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2124 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2127 /* Wait for transmit queues to drain. */
2128 usleep_range(2000, 4000);
2130 /* Reset the switch. Keep the PPU active if requested. The PPU
2131 * needs to be active to support indirect phy register access
2132 * through global registers 0x18 and 0x19.
2135 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2137 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2139 /* Wait up to one second for reset to complete. */
2140 timeout = jiffies + 1 * HZ;
2141 while (time_before(jiffies, timeout)) {
2142 ret = REG_READ(REG_GLOBAL, 0x00);
2143 if ((ret & is_reset) == is_reset)
2145 usleep_range(1000, 2000);
2147 if (time_after(jiffies, timeout))
2153 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2155 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2158 mutex_lock(&ps->smi_mutex);
2159 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2162 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2164 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2165 mutex_unlock(&ps->smi_mutex);
2169 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2172 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2175 mutex_lock(&ps->smi_mutex);
2176 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2180 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2182 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2183 mutex_unlock(&ps->smi_mutex);
2187 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2189 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2191 if (port >= 0 && port < ps->num_ports)
2197 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2199 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2200 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2206 mutex_lock(&ps->smi_mutex);
2207 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2208 mutex_unlock(&ps->smi_mutex);
2213 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2215 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2216 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2222 mutex_lock(&ps->smi_mutex);
2223 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2224 mutex_unlock(&ps->smi_mutex);
2229 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2231 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2232 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2238 mutex_lock(&ps->smi_mutex);
2239 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2240 mutex_unlock(&ps->smi_mutex);
2245 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2248 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2249 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2255 mutex_lock(&ps->smi_mutex);
2256 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2257 mutex_unlock(&ps->smi_mutex);
2261 #ifdef CONFIG_NET_DSA_HWMON
2263 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2265 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2271 mutex_lock(&ps->smi_mutex);
2273 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2277 /* Enable temperature sensor */
2278 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2282 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2286 /* Wait for temperature to stabilize */
2287 usleep_range(10000, 12000);
2289 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2295 /* Disable temperature sensor */
2296 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2300 *temp = ((val & 0x1f) - 5) * 5;
2303 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2304 mutex_unlock(&ps->smi_mutex);
2308 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2310 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2315 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2319 *temp = (ret & 0xff) - 25;
2324 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2326 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2327 return mv88e63xx_get_temp(ds, temp);
2329 return mv88e61xx_get_temp(ds, temp);
2332 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2334 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2337 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2342 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2346 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2351 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2353 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2356 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2359 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2362 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2363 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2364 (ret & 0xe0ff) | (temp << 8));
2367 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2369 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2372 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2377 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2381 *alarm = !!(ret & 0x40);
2385 #endif /* CONFIG_NET_DSA_HWMON */
2387 static int __init mv88e6xxx_init(void)
2389 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2390 register_switch_driver(&mv88e6131_switch_driver);
2392 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2393 register_switch_driver(&mv88e6123_61_65_switch_driver);
2395 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2396 register_switch_driver(&mv88e6352_switch_driver);
2398 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2399 register_switch_driver(&mv88e6171_switch_driver);
2403 module_init(mv88e6xxx_init);
2405 static void __exit mv88e6xxx_cleanup(void)
2407 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2408 unregister_switch_driver(&mv88e6171_switch_driver);
2410 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2411 unregister_switch_driver(&mv88e6352_switch_driver);
2413 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2414 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2416 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2417 unregister_switch_driver(&mv88e6131_switch_driver);
2420 module_exit(mv88e6xxx_cleanup);
2422 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2423 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2424 MODULE_LICENSE("GPL");