2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/delay.h>
12 #include <linux/etherdevice.h>
13 #include <linux/if_bridge.h>
14 #include <linux/jiffies.h>
15 #include <linux/list.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/phy.h>
20 #include "mv88e6xxx.h"
22 /* MDIO bus access can be nested in the case of PHYs connected to the
23 * internal MDIO bus of the switch, which is accessed via MDIO bus of
24 * the Ethernet interface. Avoid lockdep false positives by using
25 * mutex_lock_nested().
27 static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
31 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
32 ret = bus->read(bus, addr, regnum);
33 mutex_unlock(&bus->mdio_lock);
38 static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum,
43 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
44 ret = bus->write(bus, addr, regnum, val);
45 mutex_unlock(&bus->mdio_lock);
50 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
51 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
52 * will be directly accessible on some {device address,register address}
53 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
54 * will only respond to SMI transactions to that specific address, and
55 * an indirect addressing mechanism needs to be used to access its
58 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
63 for (i = 0; i < 16; i++) {
64 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD);
68 if ((ret & SMI_CMD_BUSY) == 0)
75 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
80 return mv88e6xxx_mdiobus_read(bus, addr, reg);
82 /* Wait for the bus to become free. */
83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
87 /* Transmit the read command. */
88 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
89 SMI_CMD_OP_22_READ | (addr << 5) | reg);
93 /* Wait for the read command to complete. */
94 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
99 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA);
106 /* Must be called with SMI mutex held */
107 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
109 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
115 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
119 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
125 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
127 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
130 mutex_lock(&ps->smi_mutex);
131 ret = _mv88e6xxx_reg_read(ds, addr, reg);
132 mutex_unlock(&ps->smi_mutex);
137 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
143 return mv88e6xxx_mdiobus_write(bus, addr, reg, val);
145 /* Wait for the bus to become free. */
146 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
150 /* Transmit the data to write. */
151 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val);
155 /* Transmit the write command. */
156 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
157 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
161 /* Wait for the write command to complete. */
162 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
169 /* Must be called with SMI mutex held */
170 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
173 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
178 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
181 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
184 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
186 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
189 mutex_lock(&ps->smi_mutex);
190 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
191 mutex_unlock(&ps->smi_mutex);
196 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
198 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
199 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
200 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
205 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
210 for (i = 0; i < 6; i++) {
213 /* Write the MAC address byte. */
214 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
215 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
217 /* Wait for the write to complete. */
218 for (j = 0; j < 16; j++) {
219 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
220 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
230 /* Must be called with SMI mutex held */
231 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
234 return _mv88e6xxx_reg_read(ds, addr, regnum);
238 /* Must be called with SMI mutex held */
239 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
243 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
247 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
248 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
251 unsigned long timeout;
253 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
254 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
255 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
257 timeout = jiffies + 1 * HZ;
258 while (time_before(jiffies, timeout)) {
259 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
260 usleep_range(1000, 2000);
261 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
262 GLOBAL_STATUS_PPU_POLLING)
269 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
272 unsigned long timeout;
274 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
275 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
277 timeout = jiffies + 1 * HZ;
278 while (time_before(jiffies, timeout)) {
279 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
280 usleep_range(1000, 2000);
281 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
282 GLOBAL_STATUS_PPU_POLLING)
289 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
291 struct mv88e6xxx_priv_state *ps;
293 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
294 if (mutex_trylock(&ps->ppu_mutex)) {
295 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
297 if (mv88e6xxx_ppu_enable(ds) == 0)
298 ps->ppu_disabled = 0;
299 mutex_unlock(&ps->ppu_mutex);
303 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
305 struct mv88e6xxx_priv_state *ps = (void *)_ps;
307 schedule_work(&ps->ppu_work);
310 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
312 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
315 mutex_lock(&ps->ppu_mutex);
317 /* If the PHY polling unit is enabled, disable it so that
318 * we can access the PHY registers. If it was already
319 * disabled, cancel the timer that is going to re-enable
322 if (!ps->ppu_disabled) {
323 ret = mv88e6xxx_ppu_disable(ds);
325 mutex_unlock(&ps->ppu_mutex);
328 ps->ppu_disabled = 1;
330 del_timer(&ps->ppu_timer);
337 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
339 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
341 /* Schedule a timer to re-enable the PHY polling unit. */
342 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
343 mutex_unlock(&ps->ppu_mutex);
346 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
348 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
350 mutex_init(&ps->ppu_mutex);
351 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
352 init_timer(&ps->ppu_timer);
353 ps->ppu_timer.data = (unsigned long)ps;
354 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
357 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
361 ret = mv88e6xxx_ppu_access_get(ds);
363 ret = mv88e6xxx_reg_read(ds, addr, regnum);
364 mv88e6xxx_ppu_access_put(ds);
370 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
375 ret = mv88e6xxx_ppu_access_get(ds);
377 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
378 mv88e6xxx_ppu_access_put(ds);
385 void mv88e6xxx_poll_link(struct dsa_switch *ds)
389 for (i = 0; i < DSA_MAX_PORTS; i++) {
390 struct net_device *dev;
391 int uninitialized_var(port_status);
402 if (dev->flags & IFF_UP) {
403 port_status = mv88e6xxx_reg_read(ds, REG_PORT(i),
408 link = !!(port_status & PORT_STATUS_LINK);
412 if (netif_carrier_ok(dev)) {
413 netdev_info(dev, "link down\n");
414 netif_carrier_off(dev);
419 switch (port_status & PORT_STATUS_SPEED_MASK) {
420 case PORT_STATUS_SPEED_10:
423 case PORT_STATUS_SPEED_100:
426 case PORT_STATUS_SPEED_1000:
433 duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0;
434 fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0;
436 if (!netif_carrier_ok(dev)) {
438 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
440 duplex ? "full" : "half",
442 netif_carrier_on(dev);
447 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
449 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
452 case PORT_SWITCH_ID_6031:
453 case PORT_SWITCH_ID_6061:
454 case PORT_SWITCH_ID_6035:
455 case PORT_SWITCH_ID_6065:
461 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
463 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
466 case PORT_SWITCH_ID_6092:
467 case PORT_SWITCH_ID_6095:
473 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
475 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
478 case PORT_SWITCH_ID_6046:
479 case PORT_SWITCH_ID_6085:
480 case PORT_SWITCH_ID_6096:
481 case PORT_SWITCH_ID_6097:
487 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
489 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
492 case PORT_SWITCH_ID_6123:
493 case PORT_SWITCH_ID_6161:
494 case PORT_SWITCH_ID_6165:
500 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
502 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
505 case PORT_SWITCH_ID_6121:
506 case PORT_SWITCH_ID_6122:
507 case PORT_SWITCH_ID_6152:
508 case PORT_SWITCH_ID_6155:
509 case PORT_SWITCH_ID_6182:
510 case PORT_SWITCH_ID_6185:
511 case PORT_SWITCH_ID_6108:
512 case PORT_SWITCH_ID_6131:
518 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
520 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
523 case PORT_SWITCH_ID_6171:
524 case PORT_SWITCH_ID_6175:
525 case PORT_SWITCH_ID_6350:
526 case PORT_SWITCH_ID_6351:
532 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
534 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
537 case PORT_SWITCH_ID_6172:
538 case PORT_SWITCH_ID_6176:
539 case PORT_SWITCH_ID_6240:
540 case PORT_SWITCH_ID_6352:
546 /* Must be called with SMI mutex held */
547 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
552 for (i = 0; i < 10; i++) {
553 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
554 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
561 /* Must be called with SMI mutex held */
562 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
566 if (mv88e6xxx_6352_family(ds))
567 port = (port + 1) << 5;
569 /* Snapshot the hardware statistics counters for this port. */
570 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
571 GLOBAL_STATS_OP_CAPTURE_PORT |
572 GLOBAL_STATS_OP_HIST_RX_TX | port);
576 /* Wait for the snapshotting to complete. */
577 ret = _mv88e6xxx_stats_wait(ds);
584 /* Must be called with SMI mutex held */
585 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
592 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
593 GLOBAL_STATS_OP_READ_CAPTURED |
594 GLOBAL_STATS_OP_HIST_RX_TX | stat);
598 ret = _mv88e6xxx_stats_wait(ds);
602 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
608 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
615 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
616 { "in_good_octets", 8, 0x00, },
617 { "in_bad_octets", 4, 0x02, },
618 { "in_unicast", 4, 0x04, },
619 { "in_broadcasts", 4, 0x06, },
620 { "in_multicasts", 4, 0x07, },
621 { "in_pause", 4, 0x16, },
622 { "in_undersize", 4, 0x18, },
623 { "in_fragments", 4, 0x19, },
624 { "in_oversize", 4, 0x1a, },
625 { "in_jabber", 4, 0x1b, },
626 { "in_rx_error", 4, 0x1c, },
627 { "in_fcs_error", 4, 0x1d, },
628 { "out_octets", 8, 0x0e, },
629 { "out_unicast", 4, 0x10, },
630 { "out_broadcasts", 4, 0x13, },
631 { "out_multicasts", 4, 0x12, },
632 { "out_pause", 4, 0x15, },
633 { "excessive", 4, 0x11, },
634 { "collisions", 4, 0x1e, },
635 { "deferred", 4, 0x05, },
636 { "single", 4, 0x14, },
637 { "multiple", 4, 0x17, },
638 { "out_fcs_error", 4, 0x03, },
639 { "late", 4, 0x1f, },
640 { "hist_64bytes", 4, 0x08, },
641 { "hist_65_127bytes", 4, 0x09, },
642 { "hist_128_255bytes", 4, 0x0a, },
643 { "hist_256_511bytes", 4, 0x0b, },
644 { "hist_512_1023bytes", 4, 0x0c, },
645 { "hist_1024_max_bytes", 4, 0x0d, },
646 /* Not all devices have the following counters */
647 { "sw_in_discards", 4, 0x110, },
648 { "sw_in_filtered", 2, 0x112, },
649 { "sw_out_filtered", 2, 0x113, },
653 static bool have_sw_in_discards(struct dsa_switch *ds)
655 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
658 case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
659 case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
660 case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
661 case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
662 case PORT_SWITCH_ID_6352:
669 static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
671 struct mv88e6xxx_hw_stat *stats,
672 int port, uint8_t *data)
676 for (i = 0; i < nr_stats; i++) {
677 memcpy(data + i * ETH_GSTRING_LEN,
678 stats[i].string, ETH_GSTRING_LEN);
682 static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
684 struct mv88e6xxx_hw_stat *stats,
685 int port, uint64_t *data)
687 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
691 mutex_lock(&ps->smi_mutex);
693 ret = _mv88e6xxx_stats_snapshot(ds, port);
695 mutex_unlock(&ps->smi_mutex);
699 /* Read each of the counters. */
700 for (i = 0; i < nr_stats; i++) {
701 struct mv88e6xxx_hw_stat *s = stats + i;
705 if (s->reg >= 0x100) {
706 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
711 if (s->sizeof_stat == 4) {
712 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
718 data[i] = (((u64)high) << 16) | low;
721 _mv88e6xxx_stats_read(ds, s->reg, &low);
722 if (s->sizeof_stat == 8)
723 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
725 data[i] = (((u64)high) << 32) | low;
728 mutex_unlock(&ps->smi_mutex);
731 /* All the statistics in the table */
733 mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
735 if (have_sw_in_discards(ds))
736 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
737 mv88e6xxx_hw_stats, port, data);
739 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
740 mv88e6xxx_hw_stats, port, data);
743 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
745 if (have_sw_in_discards(ds))
746 return ARRAY_SIZE(mv88e6xxx_hw_stats);
747 return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
751 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
752 int port, uint64_t *data)
754 if (have_sw_in_discards(ds))
755 _mv88e6xxx_get_ethtool_stats(
756 ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
757 mv88e6xxx_hw_stats, port, data);
759 _mv88e6xxx_get_ethtool_stats(
760 ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
761 mv88e6xxx_hw_stats, port, data);
764 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
766 return 32 * sizeof(u16);
769 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
770 struct ethtool_regs *regs, void *_p)
777 memset(p, 0xff, 32 * sizeof(u16));
779 for (i = 0; i < 32; i++) {
782 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
788 #ifdef CONFIG_NET_DSA_HWMON
790 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
792 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
798 mutex_lock(&ps->smi_mutex);
800 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
804 /* Enable temperature sensor */
805 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
809 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
813 /* Wait for temperature to stabilize */
814 usleep_range(10000, 12000);
816 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
822 /* Disable temperature sensor */
823 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
827 *temp = ((val & 0x1f) - 5) * 5;
830 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
831 mutex_unlock(&ps->smi_mutex);
834 #endif /* CONFIG_NET_DSA_HWMON */
836 /* Must be called with SMI lock held */
837 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
840 unsigned long timeout = jiffies + HZ / 10;
842 while (time_before(jiffies, timeout)) {
845 ret = _mv88e6xxx_reg_read(ds, reg, offset);
851 usleep_range(1000, 2000);
856 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
858 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
861 mutex_lock(&ps->smi_mutex);
862 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
863 mutex_unlock(&ps->smi_mutex);
868 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
870 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
871 GLOBAL2_SMI_OP_BUSY);
874 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
876 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
877 GLOBAL2_EEPROM_OP_LOAD);
880 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
882 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
883 GLOBAL2_EEPROM_OP_BUSY);
886 /* Must be called with SMI lock held */
887 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
889 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
893 /* Must be called with SMI mutex held */
894 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
899 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
900 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
905 ret = _mv88e6xxx_phy_wait(ds);
909 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
912 /* Must be called with SMI mutex held */
913 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
918 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
922 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
923 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
926 return _mv88e6xxx_phy_wait(ds);
929 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
931 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
934 mutex_lock(&ps->smi_mutex);
936 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
940 e->eee_enabled = !!(reg & 0x0200);
941 e->tx_lpi_enabled = !!(reg & 0x0100);
943 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
947 e->eee_active = !!(reg & PORT_STATUS_EEE);
951 mutex_unlock(&ps->smi_mutex);
955 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
956 struct phy_device *phydev, struct ethtool_eee *e)
958 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
962 mutex_lock(&ps->smi_mutex);
964 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
971 if (e->tx_lpi_enabled)
974 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
976 mutex_unlock(&ps->smi_mutex);
981 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
985 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid);
989 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
993 return _mv88e6xxx_atu_wait(ds);
996 static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
1000 ret = _mv88e6xxx_atu_wait(ds);
1004 return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB);
1007 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1009 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1013 mutex_lock(&ps->smi_mutex);
1015 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1021 oldstate = reg & PORT_CONTROL_STATE_MASK;
1022 if (oldstate != state) {
1023 /* Flush forwarding database if we're moving a port
1024 * from Learning or Forwarding state to Disabled or
1025 * Blocking or Listening state.
1027 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1028 state <= PORT_CONTROL_STATE_BLOCKING) {
1029 ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
1033 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1034 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1039 mutex_unlock(&ps->smi_mutex);
1043 /* Must be called with smi lock held */
1044 static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
1046 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1047 u8 fid = ps->fid[port];
1048 u16 reg = fid << 12;
1050 if (dsa_is_cpu_port(ds, port))
1051 reg |= ds->phys_port_mask;
1053 reg |= (ps->bridge_mask[fid] |
1054 (1 << dsa_upstream_port(ds))) & ~(1 << port);
1056 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1059 /* Must be called with smi lock held */
1060 static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
1062 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1067 mask = ds->phys_port_mask;
1070 mask &= ~(1 << port);
1071 if (ps->fid[port] != fid)
1074 ret = _mv88e6xxx_update_port_config(ds, port);
1079 return _mv88e6xxx_flush_fid(ds, fid);
1082 /* Bridge handling functions */
1084 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1086 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1091 /* If the bridge group is not empty, join that group.
1092 * Otherwise create a new group.
1094 fid = ps->fid[port];
1095 nmask = br_port_mask & ~(1 << port);
1097 fid = ps->fid[__ffs(nmask)];
1099 nmask = ps->bridge_mask[fid] | (1 << port);
1100 if (nmask != br_port_mask) {
1101 netdev_err(ds->ports[port],
1102 "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1103 fid, br_port_mask, nmask);
1107 mutex_lock(&ps->smi_mutex);
1109 ps->bridge_mask[fid] = br_port_mask;
1111 if (fid != ps->fid[port]) {
1112 ps->fid_mask |= 1 << ps->fid[port];
1113 ps->fid[port] = fid;
1114 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1117 mutex_unlock(&ps->smi_mutex);
1122 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1124 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1128 fid = ps->fid[port];
1130 if (ps->bridge_mask[fid] != br_port_mask) {
1131 netdev_err(ds->ports[port],
1132 "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1133 fid, br_port_mask, ps->bridge_mask[fid]);
1137 /* If the port was the last port of a bridge, we are done.
1138 * Otherwise assign a new fid to the port, and fix up
1139 * the bridge configuration.
1141 if (br_port_mask == (1 << port))
1144 mutex_lock(&ps->smi_mutex);
1146 newfid = __ffs(ps->fid_mask);
1147 ps->fid[port] = newfid;
1148 ps->fid_mask &= (1 << newfid);
1149 ps->bridge_mask[fid] &= ~(1 << port);
1150 ps->bridge_mask[newfid] = 1 << port;
1152 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1154 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
1156 mutex_unlock(&ps->smi_mutex);
1161 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1163 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1167 case BR_STATE_DISABLED:
1168 stp_state = PORT_CONTROL_STATE_DISABLED;
1170 case BR_STATE_BLOCKING:
1171 case BR_STATE_LISTENING:
1172 stp_state = PORT_CONTROL_STATE_BLOCKING;
1174 case BR_STATE_LEARNING:
1175 stp_state = PORT_CONTROL_STATE_LEARNING;
1177 case BR_STATE_FORWARDING:
1179 stp_state = PORT_CONTROL_STATE_FORWARDING;
1183 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1185 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1186 * so we can not update the port state directly but need to schedule it.
1188 ps->port_state[port] = stp_state;
1189 set_bit(port, &ps->port_state_update_mask);
1190 schedule_work(&ps->bridge_work);
1195 static int __mv88e6xxx_write_addr(struct dsa_switch *ds,
1196 const unsigned char *addr)
1200 for (i = 0; i < 3; i++) {
1201 ret = _mv88e6xxx_reg_write(
1202 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1203 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1211 static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr)
1215 for (i = 0; i < 3; i++) {
1216 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1217 GLOBAL_ATU_MAC_01 + i);
1220 addr[i * 2] = ret >> 8;
1221 addr[i * 2 + 1] = ret & 0xff;
1227 static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port,
1228 const unsigned char *addr, int state)
1230 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1231 u8 fid = ps->fid[port];
1234 ret = _mv88e6xxx_atu_wait(ds);
1238 ret = __mv88e6xxx_write_addr(ds, addr);
1242 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA,
1243 (0x10 << port) | state);
1247 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_LOAD_DB);
1252 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1253 const unsigned char *addr, u16 vid)
1255 int state = is_multicast_ether_addr(addr) ?
1256 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1257 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1258 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1261 mutex_lock(&ps->smi_mutex);
1262 ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state);
1263 mutex_unlock(&ps->smi_mutex);
1268 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1269 const unsigned char *addr, u16 vid)
1271 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1274 mutex_lock(&ps->smi_mutex);
1275 ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr,
1276 GLOBAL_ATU_DATA_STATE_UNUSED);
1277 mutex_unlock(&ps->smi_mutex);
1282 static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port,
1283 unsigned char *addr, bool *is_static)
1285 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1286 u8 fid = ps->fid[port];
1289 ret = _mv88e6xxx_atu_wait(ds);
1293 ret = __mv88e6xxx_write_addr(ds, addr);
1298 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1302 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1305 state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1306 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
1308 } while (!(((ret >> 4) & 0xff) & (1 << port)));
1310 ret = __mv88e6xxx_read_addr(ds, addr);
1314 *is_static = state == (is_multicast_ether_addr(addr) ?
1315 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1316 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1321 /* get next entry for port */
1322 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
1323 unsigned char *addr, bool *is_static)
1325 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1328 mutex_lock(&ps->smi_mutex);
1329 ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static);
1330 mutex_unlock(&ps->smi_mutex);
1335 static void mv88e6xxx_bridge_work(struct work_struct *work)
1337 struct mv88e6xxx_priv_state *ps;
1338 struct dsa_switch *ds;
1341 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1342 ds = ((struct dsa_switch *)ps) - 1;
1344 while (ps->port_state_update_mask) {
1345 port = __ffs(ps->port_state_update_mask);
1346 clear_bit(port, &ps->port_state_update_mask);
1347 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1351 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
1353 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1357 mutex_lock(&ps->smi_mutex);
1359 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1360 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1361 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1362 mv88e6xxx_6065_family(ds)) {
1363 /* MAC Forcing register: don't force link, speed,
1364 * duplex or flow control state to any particular
1365 * values on physical ports, but force the CPU port
1366 * and all DSA ports to their maximum bandwidth and
1369 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
1370 if (dsa_is_cpu_port(ds, port) ||
1371 ds->dsa_port_mask & (1 << port)) {
1372 reg |= PORT_PCS_CTRL_FORCE_LINK |
1373 PORT_PCS_CTRL_LINK_UP |
1374 PORT_PCS_CTRL_DUPLEX_FULL |
1375 PORT_PCS_CTRL_FORCE_DUPLEX;
1376 if (mv88e6xxx_6065_family(ds))
1377 reg |= PORT_PCS_CTRL_100;
1379 reg |= PORT_PCS_CTRL_1000;
1381 reg |= PORT_PCS_CTRL_UNFORCED;
1384 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1385 PORT_PCS_CTRL, reg);
1390 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1391 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1392 * tunneling, determine priority by looking at 802.1p and IP
1393 * priority fields (IP prio has precedence), and set STP state
1396 * If this is the CPU link, use DSA or EDSA tagging depending
1397 * on which tagging mode was configured.
1399 * If this is a link to another switch, use DSA tagging mode.
1401 * If this is the upstream port for this switch, enable
1402 * forwarding of unknown unicasts and multicasts.
1405 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1406 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1407 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1408 mv88e6xxx_6185_family(ds))
1409 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
1410 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
1411 PORT_CONTROL_STATE_FORWARDING;
1412 if (dsa_is_cpu_port(ds, port)) {
1413 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1414 reg |= PORT_CONTROL_DSA_TAG;
1415 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1416 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) {
1417 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1418 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
1420 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1423 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1424 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1425 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1426 mv88e6xxx_6185_family(ds)) {
1427 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1428 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
1431 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1432 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1433 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds)) {
1434 if (ds->dsa_port_mask & (1 << port))
1435 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1436 if (port == dsa_upstream_port(ds))
1437 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
1438 PORT_CONTROL_FORWARD_UNKNOWN_MC;
1441 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1447 /* Port Control 2: don't force a good FCS, set the maximum
1448 * frame size to 10240 bytes, don't let the switch add or
1449 * strip 802.1q tags, don't discard tagged or untagged frames
1450 * on this port, do a destination address lookup on all
1451 * received packets as usual, disable ARP mirroring and don't
1452 * send a copy of all transmitted/received frames on this port
1456 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1457 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1458 mv88e6xxx_6095_family(ds))
1459 reg = PORT_CONTROL_2_MAP_DA;
1461 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1462 mv88e6xxx_6165_family(ds))
1463 reg |= PORT_CONTROL_2_JUMBO_10240;
1465 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
1466 /* Set the upstream port this port should use */
1467 reg |= dsa_upstream_port(ds);
1468 /* enable forwarding of unknown multicast addresses to
1471 if (port == dsa_upstream_port(ds))
1472 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
1476 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1477 PORT_CONTROL_2, reg);
1482 /* Port Association Vector: when learning source addresses
1483 * of packets, add the address to the address database using
1484 * a port bitmap that has only the bit for this port set and
1485 * the other bits clear.
1487 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
1492 /* Egress rate control 2: disable egress rate control. */
1493 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
1498 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1499 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) {
1500 /* Do not limit the period of time that this port can
1501 * be paused for by the remote end or the period of
1502 * time that this port can pause the remote end.
1504 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1505 PORT_PAUSE_CTRL, 0x0000);
1509 /* Port ATU control: disable limiting the number of
1510 * address database entries that this port is allowed
1513 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1514 PORT_ATU_CONTROL, 0x0000);
1515 /* Priority Override: disable DA, SA and VTU priority
1518 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1519 PORT_PRI_OVERRIDE, 0x0000);
1523 /* Port Ethertype: use the Ethertype DSA Ethertype
1526 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1527 PORT_ETH_TYPE, ETH_P_EDSA);
1530 /* Tag Remap: use an identity 802.1p prio -> switch
1533 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1534 PORT_TAG_REGMAP_0123, 0x3210);
1538 /* Tag Remap 2: use an identity 802.1p prio -> switch
1541 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1542 PORT_TAG_REGMAP_4567, 0x7654);
1547 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1548 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1549 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) {
1550 /* Rate Control: disable ingress rate limiting. */
1551 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1552 PORT_RATE_CONTROL, 0x0001);
1557 /* Port Control 1: disable trunking, disable sending
1558 * learning messages to this port.
1560 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
1564 /* Port based VLAN map: give each port its own address
1565 * database, allow the CPU port to talk to each of the 'real'
1566 * ports, and allow each of the 'real' ports to only talk to
1567 * the upstream port.
1569 fid = __ffs(ps->fid_mask);
1570 ps->fid[port] = fid;
1571 ps->fid_mask &= ~(1 << fid);
1573 if (!dsa_is_cpu_port(ds, port))
1574 ps->bridge_mask[fid] = 1 << port;
1576 ret = _mv88e6xxx_update_port_config(ds, port);
1580 /* Default VLAN ID and priority: don't set a default VLAN
1581 * ID, and set the default packet priority to zero.
1583 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1586 mutex_unlock(&ps->smi_mutex);
1590 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
1592 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1596 for (i = 0; i < ps->num_ports; i++) {
1597 ret = mv88e6xxx_setup_port(ds, i);
1604 int mv88e6xxx_setup_common(struct dsa_switch *ds)
1606 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1608 mutex_init(&ps->smi_mutex);
1610 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
1612 ps->fid_mask = (1 << DSA_MAX_PORTS) - 1;
1614 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
1619 int mv88e6xxx_setup_global(struct dsa_switch *ds)
1621 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1624 /* Set the default address aging time to 5 minutes, and
1625 * enable address learn messages to be sent to all message
1628 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
1629 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
1631 /* Configure the IP ToS mapping registers. */
1632 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
1633 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
1634 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
1635 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
1636 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
1637 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
1638 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
1639 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
1641 /* Configure the IEEE 802.1p priority mapping register. */
1642 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
1644 /* Send all frames with destination addresses matching
1645 * 01:80:c2:00:00:0x to the CPU port.
1647 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
1649 /* Ignore removed tag data on doubly tagged packets, disable
1650 * flow control messages, force flow control priority to the
1651 * highest, and send all special multicast frames to the CPU
1652 * port at the highest priority.
1654 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
1655 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
1656 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
1658 /* Program the DSA routing table. */
1659 for (i = 0; i < 32; i++) {
1662 if (ds->pd->rtable &&
1663 i != ds->index && i < ds->dst->pd->nr_chips)
1664 nexthop = ds->pd->rtable[i] & 0x1f;
1666 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
1667 GLOBAL2_DEVICE_MAPPING_UPDATE |
1668 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
1672 /* Clear all trunk masks. */
1673 for (i = 0; i < 8; i++)
1674 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
1675 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
1676 ((1 << ps->num_ports) - 1));
1678 /* Clear all trunk mappings. */
1679 for (i = 0; i < 16; i++)
1680 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
1681 GLOBAL2_TRUNK_MAPPING_UPDATE |
1682 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
1684 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1685 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) {
1686 /* Send all frames with destination addresses matching
1687 * 01:80:c2:00:00:2x to the CPU port.
1689 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
1691 /* Initialise cross-chip port VLAN table to reset
1694 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
1696 /* Clear the priority override table. */
1697 for (i = 0; i < 16; i++)
1698 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
1702 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1703 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1704 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) {
1705 /* Disable ingress rate limiting by resetting all
1706 * ingress rate limit registers to their initial
1709 for (i = 0; i < ps->num_ports; i++)
1710 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
1717 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
1719 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1720 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
1721 unsigned long timeout;
1725 /* Set all ports to the disabled state. */
1726 for (i = 0; i < ps->num_ports; i++) {
1727 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
1728 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
1731 /* Wait for transmit queues to drain. */
1732 usleep_range(2000, 4000);
1734 /* Reset the switch. Keep the PPU active if requested. The PPU
1735 * needs to be active to support indirect phy register access
1736 * through global registers 0x18 and 0x19.
1739 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
1741 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
1743 /* Wait up to one second for reset to complete. */
1744 timeout = jiffies + 1 * HZ;
1745 while (time_before(jiffies, timeout)) {
1746 ret = REG_READ(REG_GLOBAL, 0x00);
1747 if ((ret & is_reset) == is_reset)
1749 usleep_range(1000, 2000);
1751 if (time_after(jiffies, timeout))
1757 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
1759 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1762 mutex_lock(&ps->smi_mutex);
1763 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
1766 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
1768 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
1769 mutex_unlock(&ps->smi_mutex);
1773 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
1776 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1779 mutex_lock(&ps->smi_mutex);
1780 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
1784 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
1786 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
1787 mutex_unlock(&ps->smi_mutex);
1791 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
1793 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1795 if (port >= 0 && port < ps->num_ports)
1801 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
1803 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1804 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
1810 mutex_lock(&ps->smi_mutex);
1811 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
1812 mutex_unlock(&ps->smi_mutex);
1817 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
1819 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1820 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
1826 mutex_lock(&ps->smi_mutex);
1827 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
1828 mutex_unlock(&ps->smi_mutex);
1833 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
1835 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1836 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
1842 mutex_lock(&ps->smi_mutex);
1843 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
1844 mutex_unlock(&ps->smi_mutex);
1849 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
1852 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1853 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
1859 mutex_lock(&ps->smi_mutex);
1860 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
1861 mutex_unlock(&ps->smi_mutex);
1865 static int __init mv88e6xxx_init(void)
1867 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1868 register_switch_driver(&mv88e6131_switch_driver);
1870 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1871 register_switch_driver(&mv88e6123_61_65_switch_driver);
1873 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
1874 register_switch_driver(&mv88e6352_switch_driver);
1876 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1877 register_switch_driver(&mv88e6171_switch_driver);
1881 module_init(mv88e6xxx_init);
1883 static void __exit mv88e6xxx_cleanup(void)
1885 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1886 unregister_switch_driver(&mv88e6171_switch_driver);
1888 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
1889 unregister_switch_driver(&mv88e6352_switch_driver);
1891 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1892 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
1894 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1895 unregister_switch_driver(&mv88e6131_switch_driver);
1898 module_exit(mv88e6xxx_cleanup);
1900 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
1901 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
1902 MODULE_LICENSE("GPL");