2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/debugfs.h>
12 #include <linux/delay.h>
13 #include <linux/etherdevice.h>
14 #include <linux/if_bridge.h>
15 #include <linux/jiffies.h>
16 #include <linux/list.h>
17 #include <linux/module.h>
18 #include <linux/netdevice.h>
19 #include <linux/phy.h>
20 #include <linux/seq_file.h>
22 #include "mv88e6xxx.h"
24 /* MDIO bus access can be nested in the case of PHYs connected to the
25 * internal MDIO bus of the switch, which is accessed via MDIO bus of
26 * the Ethernet interface. Avoid lockdep false positives by using
27 * mutex_lock_nested().
29 static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
33 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
34 ret = bus->read(bus, addr, regnum);
35 mutex_unlock(&bus->mdio_lock);
40 static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum,
45 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
46 ret = bus->write(bus, addr, regnum, val);
47 mutex_unlock(&bus->mdio_lock);
52 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
53 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
54 * will be directly accessible on some {device address,register address}
55 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
56 * will only respond to SMI transactions to that specific address, and
57 * an indirect addressing mechanism needs to be used to access its
60 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
65 for (i = 0; i < 16; i++) {
66 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD);
70 if ((ret & SMI_CMD_BUSY) == 0)
77 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
82 return mv88e6xxx_mdiobus_read(bus, addr, reg);
84 /* Wait for the bus to become free. */
85 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
89 /* Transmit the read command. */
90 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
91 SMI_CMD_OP_22_READ | (addr << 5) | reg);
95 /* Wait for the read command to complete. */
96 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
101 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA);
108 /* Must be called with SMI mutex held */
109 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
111 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
117 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
121 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
127 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
129 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
132 mutex_lock(&ps->smi_mutex);
133 ret = _mv88e6xxx_reg_read(ds, addr, reg);
134 mutex_unlock(&ps->smi_mutex);
139 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
145 return mv88e6xxx_mdiobus_write(bus, addr, reg, val);
147 /* Wait for the bus to become free. */
148 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
152 /* Transmit the data to write. */
153 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val);
157 /* Transmit the write command. */
158 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
159 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
163 /* Wait for the write command to complete. */
164 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
171 /* Must be called with SMI mutex held */
172 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
175 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
180 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
183 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
186 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
188 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
191 mutex_lock(&ps->smi_mutex);
192 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
193 mutex_unlock(&ps->smi_mutex);
198 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
200 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
201 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
202 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
207 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
212 for (i = 0; i < 6; i++) {
215 /* Write the MAC address byte. */
216 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
217 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
219 /* Wait for the write to complete. */
220 for (j = 0; j < 16; j++) {
221 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
222 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
232 /* Must be called with SMI mutex held */
233 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
236 return _mv88e6xxx_reg_read(ds, addr, regnum);
240 /* Must be called with SMI mutex held */
241 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
245 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
249 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
250 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
253 unsigned long timeout;
255 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
256 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
257 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
259 timeout = jiffies + 1 * HZ;
260 while (time_before(jiffies, timeout)) {
261 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
262 usleep_range(1000, 2000);
263 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
264 GLOBAL_STATUS_PPU_POLLING)
271 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
274 unsigned long timeout;
276 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
277 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
279 timeout = jiffies + 1 * HZ;
280 while (time_before(jiffies, timeout)) {
281 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
282 usleep_range(1000, 2000);
283 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
284 GLOBAL_STATUS_PPU_POLLING)
291 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
293 struct mv88e6xxx_priv_state *ps;
295 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
296 if (mutex_trylock(&ps->ppu_mutex)) {
297 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
299 if (mv88e6xxx_ppu_enable(ds) == 0)
300 ps->ppu_disabled = 0;
301 mutex_unlock(&ps->ppu_mutex);
305 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
307 struct mv88e6xxx_priv_state *ps = (void *)_ps;
309 schedule_work(&ps->ppu_work);
312 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
314 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
317 mutex_lock(&ps->ppu_mutex);
319 /* If the PHY polling unit is enabled, disable it so that
320 * we can access the PHY registers. If it was already
321 * disabled, cancel the timer that is going to re-enable
324 if (!ps->ppu_disabled) {
325 ret = mv88e6xxx_ppu_disable(ds);
327 mutex_unlock(&ps->ppu_mutex);
330 ps->ppu_disabled = 1;
332 del_timer(&ps->ppu_timer);
339 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
341 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
343 /* Schedule a timer to re-enable the PHY polling unit. */
344 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
345 mutex_unlock(&ps->ppu_mutex);
348 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
350 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
352 mutex_init(&ps->ppu_mutex);
353 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
354 init_timer(&ps->ppu_timer);
355 ps->ppu_timer.data = (unsigned long)ps;
356 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
359 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
363 ret = mv88e6xxx_ppu_access_get(ds);
365 ret = mv88e6xxx_reg_read(ds, addr, regnum);
366 mv88e6xxx_ppu_access_put(ds);
372 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
377 ret = mv88e6xxx_ppu_access_get(ds);
379 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
380 mv88e6xxx_ppu_access_put(ds);
387 void mv88e6xxx_poll_link(struct dsa_switch *ds)
391 for (i = 0; i < DSA_MAX_PORTS; i++) {
392 struct net_device *dev;
393 int uninitialized_var(port_status);
404 if (dev->flags & IFF_UP) {
405 port_status = mv88e6xxx_reg_read(ds, REG_PORT(i),
410 link = !!(port_status & PORT_STATUS_LINK);
414 if (netif_carrier_ok(dev)) {
415 netdev_info(dev, "link down\n");
416 netif_carrier_off(dev);
421 switch (port_status & PORT_STATUS_SPEED_MASK) {
422 case PORT_STATUS_SPEED_10:
425 case PORT_STATUS_SPEED_100:
428 case PORT_STATUS_SPEED_1000:
435 duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0;
436 fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0;
438 if (!netif_carrier_ok(dev)) {
440 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
442 duplex ? "full" : "half",
444 netif_carrier_on(dev);
449 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
451 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
454 case PORT_SWITCH_ID_6031:
455 case PORT_SWITCH_ID_6061:
456 case PORT_SWITCH_ID_6035:
457 case PORT_SWITCH_ID_6065:
463 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
465 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
468 case PORT_SWITCH_ID_6092:
469 case PORT_SWITCH_ID_6095:
475 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
477 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
480 case PORT_SWITCH_ID_6046:
481 case PORT_SWITCH_ID_6085:
482 case PORT_SWITCH_ID_6096:
483 case PORT_SWITCH_ID_6097:
489 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
491 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
494 case PORT_SWITCH_ID_6123:
495 case PORT_SWITCH_ID_6161:
496 case PORT_SWITCH_ID_6165:
502 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
504 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
507 case PORT_SWITCH_ID_6121:
508 case PORT_SWITCH_ID_6122:
509 case PORT_SWITCH_ID_6152:
510 case PORT_SWITCH_ID_6155:
511 case PORT_SWITCH_ID_6182:
512 case PORT_SWITCH_ID_6185:
513 case PORT_SWITCH_ID_6108:
514 case PORT_SWITCH_ID_6131:
520 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
522 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
525 case PORT_SWITCH_ID_6171:
526 case PORT_SWITCH_ID_6175:
527 case PORT_SWITCH_ID_6350:
528 case PORT_SWITCH_ID_6351:
534 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
536 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
539 case PORT_SWITCH_ID_6172:
540 case PORT_SWITCH_ID_6176:
541 case PORT_SWITCH_ID_6240:
542 case PORT_SWITCH_ID_6352:
548 /* Must be called with SMI mutex held */
549 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
554 for (i = 0; i < 10; i++) {
555 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
556 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
563 /* Must be called with SMI mutex held */
564 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
568 if (mv88e6xxx_6352_family(ds))
569 port = (port + 1) << 5;
571 /* Snapshot the hardware statistics counters for this port. */
572 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
573 GLOBAL_STATS_OP_CAPTURE_PORT |
574 GLOBAL_STATS_OP_HIST_RX_TX | port);
578 /* Wait for the snapshotting to complete. */
579 ret = _mv88e6xxx_stats_wait(ds);
586 /* Must be called with SMI mutex held */
587 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
594 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
595 GLOBAL_STATS_OP_READ_CAPTURED |
596 GLOBAL_STATS_OP_HIST_RX_TX | stat);
600 ret = _mv88e6xxx_stats_wait(ds);
604 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
610 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
617 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
618 { "in_good_octets", 8, 0x00, },
619 { "in_bad_octets", 4, 0x02, },
620 { "in_unicast", 4, 0x04, },
621 { "in_broadcasts", 4, 0x06, },
622 { "in_multicasts", 4, 0x07, },
623 { "in_pause", 4, 0x16, },
624 { "in_undersize", 4, 0x18, },
625 { "in_fragments", 4, 0x19, },
626 { "in_oversize", 4, 0x1a, },
627 { "in_jabber", 4, 0x1b, },
628 { "in_rx_error", 4, 0x1c, },
629 { "in_fcs_error", 4, 0x1d, },
630 { "out_octets", 8, 0x0e, },
631 { "out_unicast", 4, 0x10, },
632 { "out_broadcasts", 4, 0x13, },
633 { "out_multicasts", 4, 0x12, },
634 { "out_pause", 4, 0x15, },
635 { "excessive", 4, 0x11, },
636 { "collisions", 4, 0x1e, },
637 { "deferred", 4, 0x05, },
638 { "single", 4, 0x14, },
639 { "multiple", 4, 0x17, },
640 { "out_fcs_error", 4, 0x03, },
641 { "late", 4, 0x1f, },
642 { "hist_64bytes", 4, 0x08, },
643 { "hist_65_127bytes", 4, 0x09, },
644 { "hist_128_255bytes", 4, 0x0a, },
645 { "hist_256_511bytes", 4, 0x0b, },
646 { "hist_512_1023bytes", 4, 0x0c, },
647 { "hist_1024_max_bytes", 4, 0x0d, },
648 /* Not all devices have the following counters */
649 { "sw_in_discards", 4, 0x110, },
650 { "sw_in_filtered", 2, 0x112, },
651 { "sw_out_filtered", 2, 0x113, },
655 static bool have_sw_in_discards(struct dsa_switch *ds)
657 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
660 case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
661 case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
662 case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
663 case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
664 case PORT_SWITCH_ID_6352:
671 static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
673 struct mv88e6xxx_hw_stat *stats,
674 int port, uint8_t *data)
678 for (i = 0; i < nr_stats; i++) {
679 memcpy(data + i * ETH_GSTRING_LEN,
680 stats[i].string, ETH_GSTRING_LEN);
684 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
686 struct mv88e6xxx_hw_stat *stats,
689 struct mv88e6xxx_hw_stat *s = stats + stat;
695 if (s->reg >= 0x100) {
696 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
702 if (s->sizeof_stat == 4) {
703 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
710 _mv88e6xxx_stats_read(ds, s->reg, &low);
711 if (s->sizeof_stat == 8)
712 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
714 value = (((u64)high) << 16) | low;
718 static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
720 struct mv88e6xxx_hw_stat *stats,
721 int port, uint64_t *data)
723 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
727 mutex_lock(&ps->smi_mutex);
729 ret = _mv88e6xxx_stats_snapshot(ds, port);
731 mutex_unlock(&ps->smi_mutex);
735 /* Read each of the counters. */
736 for (i = 0; i < nr_stats; i++)
737 data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port);
739 mutex_unlock(&ps->smi_mutex);
742 /* All the statistics in the table */
744 mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
746 if (have_sw_in_discards(ds))
747 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
748 mv88e6xxx_hw_stats, port, data);
750 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
751 mv88e6xxx_hw_stats, port, data);
754 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
756 if (have_sw_in_discards(ds))
757 return ARRAY_SIZE(mv88e6xxx_hw_stats);
758 return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
762 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
763 int port, uint64_t *data)
765 if (have_sw_in_discards(ds))
766 _mv88e6xxx_get_ethtool_stats(
767 ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
768 mv88e6xxx_hw_stats, port, data);
770 _mv88e6xxx_get_ethtool_stats(
771 ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
772 mv88e6xxx_hw_stats, port, data);
775 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
777 return 32 * sizeof(u16);
780 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
781 struct ethtool_regs *regs, void *_p)
788 memset(p, 0xff, 32 * sizeof(u16));
790 for (i = 0; i < 32; i++) {
793 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
799 #ifdef CONFIG_NET_DSA_HWMON
801 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
803 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
809 mutex_lock(&ps->smi_mutex);
811 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
815 /* Enable temperature sensor */
816 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
820 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
824 /* Wait for temperature to stabilize */
825 usleep_range(10000, 12000);
827 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
833 /* Disable temperature sensor */
834 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
838 *temp = ((val & 0x1f) - 5) * 5;
841 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
842 mutex_unlock(&ps->smi_mutex);
845 #endif /* CONFIG_NET_DSA_HWMON */
847 /* Must be called with SMI lock held */
848 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
851 unsigned long timeout = jiffies + HZ / 10;
853 while (time_before(jiffies, timeout)) {
856 ret = _mv88e6xxx_reg_read(ds, reg, offset);
862 usleep_range(1000, 2000);
867 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
869 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
872 mutex_lock(&ps->smi_mutex);
873 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
874 mutex_unlock(&ps->smi_mutex);
879 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
881 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
882 GLOBAL2_SMI_OP_BUSY);
885 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
887 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
888 GLOBAL2_EEPROM_OP_LOAD);
891 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
893 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
894 GLOBAL2_EEPROM_OP_BUSY);
897 /* Must be called with SMI lock held */
898 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
900 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
904 /* Must be called with SMI lock held */
905 static int _mv88e6xxx_scratch_wait(struct dsa_switch *ds)
907 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
908 GLOBAL2_SCRATCH_BUSY);
911 /* Must be called with SMI mutex held */
912 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
917 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
918 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
923 ret = _mv88e6xxx_phy_wait(ds);
927 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
930 /* Must be called with SMI mutex held */
931 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
936 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
940 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
941 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
944 return _mv88e6xxx_phy_wait(ds);
947 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
949 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
952 mutex_lock(&ps->smi_mutex);
954 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
958 e->eee_enabled = !!(reg & 0x0200);
959 e->tx_lpi_enabled = !!(reg & 0x0100);
961 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
965 e->eee_active = !!(reg & PORT_STATUS_EEE);
969 mutex_unlock(&ps->smi_mutex);
973 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
974 struct phy_device *phydev, struct ethtool_eee *e)
976 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
980 mutex_lock(&ps->smi_mutex);
982 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
989 if (e->tx_lpi_enabled)
992 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
994 mutex_unlock(&ps->smi_mutex);
999 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
1003 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid);
1007 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1011 return _mv88e6xxx_atu_wait(ds);
1014 static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
1018 ret = _mv88e6xxx_atu_wait(ds);
1022 return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB);
1025 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1027 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1031 mutex_lock(&ps->smi_mutex);
1033 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1039 oldstate = reg & PORT_CONTROL_STATE_MASK;
1040 if (oldstate != state) {
1041 /* Flush forwarding database if we're moving a port
1042 * from Learning or Forwarding state to Disabled or
1043 * Blocking or Listening state.
1045 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1046 state <= PORT_CONTROL_STATE_BLOCKING) {
1047 ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
1051 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1052 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1057 mutex_unlock(&ps->smi_mutex);
1061 /* Must be called with smi lock held */
1062 static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
1064 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1065 u8 fid = ps->fid[port];
1066 u16 reg = fid << 12;
1068 if (dsa_is_cpu_port(ds, port))
1069 reg |= ds->phys_port_mask;
1071 reg |= (ps->bridge_mask[fid] |
1072 (1 << dsa_upstream_port(ds))) & ~(1 << port);
1074 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1077 /* Must be called with smi lock held */
1078 static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
1080 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1085 mask = ds->phys_port_mask;
1088 mask &= ~(1 << port);
1089 if (ps->fid[port] != fid)
1092 ret = _mv88e6xxx_update_port_config(ds, port);
1097 return _mv88e6xxx_flush_fid(ds, fid);
1100 /* Bridge handling functions */
1102 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1104 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1109 /* If the bridge group is not empty, join that group.
1110 * Otherwise create a new group.
1112 fid = ps->fid[port];
1113 nmask = br_port_mask & ~(1 << port);
1115 fid = ps->fid[__ffs(nmask)];
1117 nmask = ps->bridge_mask[fid] | (1 << port);
1118 if (nmask != br_port_mask) {
1119 netdev_err(ds->ports[port],
1120 "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1121 fid, br_port_mask, nmask);
1125 mutex_lock(&ps->smi_mutex);
1127 ps->bridge_mask[fid] = br_port_mask;
1129 if (fid != ps->fid[port]) {
1130 ps->fid_mask |= 1 << ps->fid[port];
1131 ps->fid[port] = fid;
1132 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1135 mutex_unlock(&ps->smi_mutex);
1140 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1142 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1146 fid = ps->fid[port];
1148 if (ps->bridge_mask[fid] != br_port_mask) {
1149 netdev_err(ds->ports[port],
1150 "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1151 fid, br_port_mask, ps->bridge_mask[fid]);
1155 /* If the port was the last port of a bridge, we are done.
1156 * Otherwise assign a new fid to the port, and fix up
1157 * the bridge configuration.
1159 if (br_port_mask == (1 << port))
1162 mutex_lock(&ps->smi_mutex);
1164 newfid = __ffs(ps->fid_mask);
1165 ps->fid[port] = newfid;
1166 ps->fid_mask &= ~(1 << newfid);
1167 ps->bridge_mask[fid] &= ~(1 << port);
1168 ps->bridge_mask[newfid] = 1 << port;
1170 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1172 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
1174 mutex_unlock(&ps->smi_mutex);
1179 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1181 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1185 case BR_STATE_DISABLED:
1186 stp_state = PORT_CONTROL_STATE_DISABLED;
1188 case BR_STATE_BLOCKING:
1189 case BR_STATE_LISTENING:
1190 stp_state = PORT_CONTROL_STATE_BLOCKING;
1192 case BR_STATE_LEARNING:
1193 stp_state = PORT_CONTROL_STATE_LEARNING;
1195 case BR_STATE_FORWARDING:
1197 stp_state = PORT_CONTROL_STATE_FORWARDING;
1201 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1203 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1204 * so we can not update the port state directly but need to schedule it.
1206 ps->port_state[port] = stp_state;
1207 set_bit(port, &ps->port_state_update_mask);
1208 schedule_work(&ps->bridge_work);
1213 static int __mv88e6xxx_write_addr(struct dsa_switch *ds,
1214 const unsigned char *addr)
1218 for (i = 0; i < 3; i++) {
1219 ret = _mv88e6xxx_reg_write(
1220 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1221 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1229 static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr)
1233 for (i = 0; i < 3; i++) {
1234 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1235 GLOBAL_ATU_MAC_01 + i);
1238 addr[i * 2] = ret >> 8;
1239 addr[i * 2 + 1] = ret & 0xff;
1245 static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port,
1246 const unsigned char *addr, int state)
1248 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1249 u8 fid = ps->fid[port];
1252 ret = _mv88e6xxx_atu_wait(ds);
1256 ret = __mv88e6xxx_write_addr(ds, addr);
1260 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA,
1261 (0x10 << port) | state);
1265 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_LOAD_DB);
1270 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1271 const unsigned char *addr, u16 vid)
1273 int state = is_multicast_ether_addr(addr) ?
1274 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1275 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1276 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1279 mutex_lock(&ps->smi_mutex);
1280 ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state);
1281 mutex_unlock(&ps->smi_mutex);
1286 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1287 const unsigned char *addr, u16 vid)
1289 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1292 mutex_lock(&ps->smi_mutex);
1293 ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr,
1294 GLOBAL_ATU_DATA_STATE_UNUSED);
1295 mutex_unlock(&ps->smi_mutex);
1300 static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port,
1301 unsigned char *addr, bool *is_static)
1303 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1304 u8 fid = ps->fid[port];
1307 ret = _mv88e6xxx_atu_wait(ds);
1311 ret = __mv88e6xxx_write_addr(ds, addr);
1316 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1320 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1323 state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1324 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
1326 } while (!(((ret >> 4) & 0xff) & (1 << port)));
1328 ret = __mv88e6xxx_read_addr(ds, addr);
1332 *is_static = state == (is_multicast_ether_addr(addr) ?
1333 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1334 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1339 /* get next entry for port */
1340 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
1341 unsigned char *addr, bool *is_static)
1343 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1346 mutex_lock(&ps->smi_mutex);
1347 ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static);
1348 mutex_unlock(&ps->smi_mutex);
1353 static void mv88e6xxx_bridge_work(struct work_struct *work)
1355 struct mv88e6xxx_priv_state *ps;
1356 struct dsa_switch *ds;
1359 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1360 ds = ((struct dsa_switch *)ps) - 1;
1362 while (ps->port_state_update_mask) {
1363 port = __ffs(ps->port_state_update_mask);
1364 clear_bit(port, &ps->port_state_update_mask);
1365 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1369 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
1371 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1375 mutex_lock(&ps->smi_mutex);
1377 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1378 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1379 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1380 mv88e6xxx_6065_family(ds)) {
1381 /* MAC Forcing register: don't force link, speed,
1382 * duplex or flow control state to any particular
1383 * values on physical ports, but force the CPU port
1384 * and all DSA ports to their maximum bandwidth and
1387 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
1388 if (dsa_is_cpu_port(ds, port) ||
1389 ds->dsa_port_mask & (1 << port)) {
1390 reg |= PORT_PCS_CTRL_FORCE_LINK |
1391 PORT_PCS_CTRL_LINK_UP |
1392 PORT_PCS_CTRL_DUPLEX_FULL |
1393 PORT_PCS_CTRL_FORCE_DUPLEX;
1394 if (mv88e6xxx_6065_family(ds))
1395 reg |= PORT_PCS_CTRL_100;
1397 reg |= PORT_PCS_CTRL_1000;
1399 reg |= PORT_PCS_CTRL_UNFORCED;
1402 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1403 PORT_PCS_CTRL, reg);
1408 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1409 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1410 * tunneling, determine priority by looking at 802.1p and IP
1411 * priority fields (IP prio has precedence), and set STP state
1414 * If this is the CPU link, use DSA or EDSA tagging depending
1415 * on which tagging mode was configured.
1417 * If this is a link to another switch, use DSA tagging mode.
1419 * If this is the upstream port for this switch, enable
1420 * forwarding of unknown unicasts and multicasts.
1423 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1424 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1425 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1426 mv88e6xxx_6185_family(ds))
1427 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
1428 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
1429 PORT_CONTROL_STATE_FORWARDING;
1430 if (dsa_is_cpu_port(ds, port)) {
1431 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1432 reg |= PORT_CONTROL_DSA_TAG;
1433 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1434 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) {
1435 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1436 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
1438 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1441 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1442 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1443 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1444 mv88e6xxx_6185_family(ds)) {
1445 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1446 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
1449 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1450 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1451 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds)) {
1452 if (ds->dsa_port_mask & (1 << port))
1453 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1454 if (port == dsa_upstream_port(ds))
1455 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
1456 PORT_CONTROL_FORWARD_UNKNOWN_MC;
1459 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1465 /* Port Control 2: don't force a good FCS, set the maximum
1466 * frame size to 10240 bytes, don't let the switch add or
1467 * strip 802.1q tags, don't discard tagged or untagged frames
1468 * on this port, do a destination address lookup on all
1469 * received packets as usual, disable ARP mirroring and don't
1470 * send a copy of all transmitted/received frames on this port
1474 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1475 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1476 mv88e6xxx_6095_family(ds))
1477 reg = PORT_CONTROL_2_MAP_DA;
1479 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1480 mv88e6xxx_6165_family(ds))
1481 reg |= PORT_CONTROL_2_JUMBO_10240;
1483 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
1484 /* Set the upstream port this port should use */
1485 reg |= dsa_upstream_port(ds);
1486 /* enable forwarding of unknown multicast addresses to
1489 if (port == dsa_upstream_port(ds))
1490 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
1494 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1495 PORT_CONTROL_2, reg);
1500 /* Port Association Vector: when learning source addresses
1501 * of packets, add the address to the address database using
1502 * a port bitmap that has only the bit for this port set and
1503 * the other bits clear.
1505 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
1510 /* Egress rate control 2: disable egress rate control. */
1511 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
1516 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1517 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) {
1518 /* Do not limit the period of time that this port can
1519 * be paused for by the remote end or the period of
1520 * time that this port can pause the remote end.
1522 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1523 PORT_PAUSE_CTRL, 0x0000);
1527 /* Port ATU control: disable limiting the number of
1528 * address database entries that this port is allowed
1531 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1532 PORT_ATU_CONTROL, 0x0000);
1533 /* Priority Override: disable DA, SA and VTU priority
1536 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1537 PORT_PRI_OVERRIDE, 0x0000);
1541 /* Port Ethertype: use the Ethertype DSA Ethertype
1544 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1545 PORT_ETH_TYPE, ETH_P_EDSA);
1548 /* Tag Remap: use an identity 802.1p prio -> switch
1551 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1552 PORT_TAG_REGMAP_0123, 0x3210);
1556 /* Tag Remap 2: use an identity 802.1p prio -> switch
1559 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1560 PORT_TAG_REGMAP_4567, 0x7654);
1565 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1566 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1567 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) {
1568 /* Rate Control: disable ingress rate limiting. */
1569 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1570 PORT_RATE_CONTROL, 0x0001);
1575 /* Port Control 1: disable trunking, disable sending
1576 * learning messages to this port.
1578 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
1582 /* Port based VLAN map: give each port its own address
1583 * database, allow the CPU port to talk to each of the 'real'
1584 * ports, and allow each of the 'real' ports to only talk to
1585 * the upstream port.
1587 fid = __ffs(ps->fid_mask);
1588 ps->fid[port] = fid;
1589 ps->fid_mask &= ~(1 << fid);
1591 if (!dsa_is_cpu_port(ds, port))
1592 ps->bridge_mask[fid] = 1 << port;
1594 ret = _mv88e6xxx_update_port_config(ds, port);
1598 /* Default VLAN ID and priority: don't set a default VLAN
1599 * ID, and set the default packet priority to zero.
1601 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1604 mutex_unlock(&ps->smi_mutex);
1608 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
1610 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1614 for (i = 0; i < ps->num_ports; i++) {
1615 ret = mv88e6xxx_setup_port(ds, i);
1622 static int mv88e6xxx_regs_show(struct seq_file *s, void *p)
1624 struct dsa_switch *ds = s->private;
1626 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1629 seq_puts(s, " GLOBAL GLOBAL2 ");
1630 for (port = 0 ; port < ps->num_ports; port++)
1631 seq_printf(s, " %2d ", port);
1634 for (reg = 0; reg < 32; reg++) {
1635 seq_printf(s, "%2x: ", reg);
1636 seq_printf(s, " %4x %4x ",
1637 mv88e6xxx_reg_read(ds, REG_GLOBAL, reg),
1638 mv88e6xxx_reg_read(ds, REG_GLOBAL2, reg));
1640 for (port = 0 ; port < ps->num_ports; port++)
1641 seq_printf(s, "%4x ",
1642 mv88e6xxx_reg_read(ds, REG_PORT(port), reg));
1649 static int mv88e6xxx_regs_open(struct inode *inode, struct file *file)
1651 return single_open(file, mv88e6xxx_regs_show, inode->i_private);
1654 static const struct file_operations mv88e6xxx_regs_fops = {
1655 .open = mv88e6xxx_regs_open,
1657 .llseek = no_llseek,
1658 .release = single_release,
1659 .owner = THIS_MODULE,
1662 static void mv88e6xxx_atu_show_header(struct seq_file *s)
1664 seq_puts(s, "DB T/P Vec State Addr\n");
1667 static void mv88e6xxx_atu_show_entry(struct seq_file *s, int dbnum,
1668 unsigned char *addr, int data)
1670 bool trunk = !!(data & GLOBAL_ATU_DATA_TRUNK);
1671 int portvec = ((data & GLOBAL_ATU_DATA_PORT_VECTOR_MASK) >>
1672 GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT);
1673 int state = data & GLOBAL_ATU_DATA_STATE_MASK;
1675 seq_printf(s, "%03x %5s %10pb %x %pM\n",
1676 dbnum, (trunk ? "Trunk" : "Port"), &portvec, state, addr);
1679 static int mv88e6xxx_atu_show_db(struct seq_file *s, struct dsa_switch *ds,
1682 unsigned char bcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
1683 unsigned char addr[6];
1684 int ret, data, state;
1686 ret = __mv88e6xxx_write_addr(ds, bcast);
1691 ret = _mv88e6xxx_atu_cmd(ds, dbnum, GLOBAL_ATU_OP_GET_NEXT_DB);
1694 data = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1698 state = data & GLOBAL_ATU_DATA_STATE_MASK;
1699 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
1701 ret = __mv88e6xxx_read_addr(ds, addr);
1704 mv88e6xxx_atu_show_entry(s, dbnum, addr, data);
1705 } while (state != GLOBAL_ATU_DATA_STATE_UNUSED);
1710 static int mv88e6xxx_atu_show(struct seq_file *s, void *p)
1712 struct dsa_switch *ds = s->private;
1713 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1716 mv88e6xxx_atu_show_header(s);
1718 for (dbnum = 0; dbnum < 255; dbnum++) {
1719 mutex_lock(&ps->smi_mutex);
1720 mv88e6xxx_atu_show_db(s, ds, dbnum);
1721 mutex_unlock(&ps->smi_mutex);
1727 static int mv88e6xxx_atu_open(struct inode *inode, struct file *file)
1729 return single_open(file, mv88e6xxx_atu_show, inode->i_private);
1732 static const struct file_operations mv88e6xxx_atu_fops = {
1733 .open = mv88e6xxx_atu_open,
1735 .llseek = no_llseek,
1736 .release = single_release,
1737 .owner = THIS_MODULE,
1740 static void mv88e6xxx_stats_show_header(struct seq_file *s,
1741 struct mv88e6xxx_priv_state *ps)
1745 seq_puts(s, " Statistic ");
1746 for (port = 0 ; port < ps->num_ports; port++)
1747 seq_printf(s, "Port %2d ", port);
1751 static int mv88e6xxx_stats_show(struct seq_file *s, void *p)
1753 struct dsa_switch *ds = s->private;
1754 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1755 struct mv88e6xxx_hw_stat *stats = mv88e6xxx_hw_stats;
1756 int port, stat, max_stats;
1759 if (have_sw_in_discards(ds))
1760 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats);
1762 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
1764 mv88e6xxx_stats_show_header(s, ps);
1766 mutex_lock(&ps->smi_mutex);
1768 for (stat = 0; stat < max_stats; stat++) {
1769 seq_printf(s, "%19s: ", stats[stat].string);
1770 for (port = 0 ; port < ps->num_ports; port++) {
1771 _mv88e6xxx_stats_snapshot(ds, port);
1772 value = _mv88e6xxx_get_ethtool_stat(ds, stat, stats,
1774 seq_printf(s, "%8llu ", value);
1778 mutex_unlock(&ps->smi_mutex);
1783 static int mv88e6xxx_stats_open(struct inode *inode, struct file *file)
1785 return single_open(file, mv88e6xxx_stats_show, inode->i_private);
1788 static const struct file_operations mv88e6xxx_stats_fops = {
1789 .open = mv88e6xxx_stats_open,
1791 .llseek = no_llseek,
1792 .release = single_release,
1793 .owner = THIS_MODULE,
1796 static int mv88e6xxx_device_map_show(struct seq_file *s, void *p)
1798 struct dsa_switch *ds = s->private;
1799 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1802 seq_puts(s, "Target Port\n");
1804 mutex_lock(&ps->smi_mutex);
1805 for (target = 0; target < 32; target++) {
1806 ret = _mv88e6xxx_reg_write(
1807 ds, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
1808 target << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT);
1811 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
1812 GLOBAL2_DEVICE_MAPPING);
1813 seq_printf(s, " %2d %2d\n", target,
1814 ret & GLOBAL2_DEVICE_MAPPING_PORT_MASK);
1817 mutex_unlock(&ps->smi_mutex);
1822 static int mv88e6xxx_device_map_open(struct inode *inode, struct file *file)
1824 return single_open(file, mv88e6xxx_device_map_show, inode->i_private);
1827 static const struct file_operations mv88e6xxx_device_map_fops = {
1828 .open = mv88e6xxx_device_map_open,
1830 .llseek = no_llseek,
1831 .release = single_release,
1832 .owner = THIS_MODULE,
1835 static int mv88e6xxx_scratch_show(struct seq_file *s, void *p)
1837 struct dsa_switch *ds = s->private;
1838 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1841 seq_puts(s, "Register Value\n");
1843 mutex_lock(&ps->smi_mutex);
1844 for (reg = 0; reg < 0x80; reg++) {
1845 ret = _mv88e6xxx_reg_write(
1846 ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
1847 reg << GLOBAL2_SCRATCH_REGISTER_SHIFT);
1851 ret = _mv88e6xxx_scratch_wait(ds);
1855 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
1856 GLOBAL2_SCRATCH_MISC);
1857 seq_printf(s, " %2x %2x\n", reg,
1858 ret & GLOBAL2_SCRATCH_VALUE_MASK);
1861 mutex_unlock(&ps->smi_mutex);
1866 static int mv88e6xxx_scratch_open(struct inode *inode, struct file *file)
1868 return single_open(file, mv88e6xxx_scratch_show, inode->i_private);
1871 static const struct file_operations mv88e6xxx_scratch_fops = {
1872 .open = mv88e6xxx_scratch_open,
1874 .llseek = no_llseek,
1875 .release = single_release,
1876 .owner = THIS_MODULE,
1879 int mv88e6xxx_setup_common(struct dsa_switch *ds)
1881 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1884 mutex_init(&ps->smi_mutex);
1886 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
1888 ps->fid_mask = (1 << DSA_MAX_PORTS) - 1;
1890 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
1892 name = kasprintf(GFP_KERNEL, "dsa%d", ds->index);
1893 ps->dbgfs = debugfs_create_dir(name, NULL);
1896 debugfs_create_file("regs", S_IRUGO, ps->dbgfs, ds,
1897 &mv88e6xxx_regs_fops);
1899 debugfs_create_file("atu", S_IRUGO, ps->dbgfs, ds,
1900 &mv88e6xxx_atu_fops);
1902 debugfs_create_file("stats", S_IRUGO, ps->dbgfs, ds,
1903 &mv88e6xxx_stats_fops);
1905 debugfs_create_file("device_map", S_IRUGO, ps->dbgfs, ds,
1906 &mv88e6xxx_device_map_fops);
1908 debugfs_create_file("scratch", S_IRUGO, ps->dbgfs, ds,
1909 &mv88e6xxx_scratch_fops);
1913 int mv88e6xxx_setup_global(struct dsa_switch *ds)
1915 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1918 /* Set the default address aging time to 5 minutes, and
1919 * enable address learn messages to be sent to all message
1922 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
1923 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
1925 /* Configure the IP ToS mapping registers. */
1926 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
1927 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
1928 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
1929 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
1930 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
1931 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
1932 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
1933 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
1935 /* Configure the IEEE 802.1p priority mapping register. */
1936 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
1938 /* Send all frames with destination addresses matching
1939 * 01:80:c2:00:00:0x to the CPU port.
1941 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
1943 /* Ignore removed tag data on doubly tagged packets, disable
1944 * flow control messages, force flow control priority to the
1945 * highest, and send all special multicast frames to the CPU
1946 * port at the highest priority.
1948 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
1949 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
1950 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
1952 /* Program the DSA routing table. */
1953 for (i = 0; i < 32; i++) {
1956 if (ds->pd->rtable &&
1957 i != ds->index && i < ds->dst->pd->nr_chips)
1958 nexthop = ds->pd->rtable[i] & 0x1f;
1960 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
1961 GLOBAL2_DEVICE_MAPPING_UPDATE |
1962 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
1966 /* Clear all trunk masks. */
1967 for (i = 0; i < 8; i++)
1968 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
1969 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
1970 ((1 << ps->num_ports) - 1));
1972 /* Clear all trunk mappings. */
1973 for (i = 0; i < 16; i++)
1974 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
1975 GLOBAL2_TRUNK_MAPPING_UPDATE |
1976 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
1978 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1979 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) {
1980 /* Send all frames with destination addresses matching
1981 * 01:80:c2:00:00:2x to the CPU port.
1983 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
1985 /* Initialise cross-chip port VLAN table to reset
1988 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
1990 /* Clear the priority override table. */
1991 for (i = 0; i < 16; i++)
1992 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
1996 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1997 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1998 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) {
1999 /* Disable ingress rate limiting by resetting all
2000 * ingress rate limit registers to their initial
2003 for (i = 0; i < ps->num_ports; i++)
2004 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2008 /* Clear the statistics counters for all ports */
2009 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2011 /* Wait for the flush to complete. */
2012 _mv88e6xxx_stats_wait(ds);
2017 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2019 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2020 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2021 unsigned long timeout;
2025 /* Set all ports to the disabled state. */
2026 for (i = 0; i < ps->num_ports; i++) {
2027 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2028 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2031 /* Wait for transmit queues to drain. */
2032 usleep_range(2000, 4000);
2034 /* Reset the switch. Keep the PPU active if requested. The PPU
2035 * needs to be active to support indirect phy register access
2036 * through global registers 0x18 and 0x19.
2039 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2041 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2043 /* Wait up to one second for reset to complete. */
2044 timeout = jiffies + 1 * HZ;
2045 while (time_before(jiffies, timeout)) {
2046 ret = REG_READ(REG_GLOBAL, 0x00);
2047 if ((ret & is_reset) == is_reset)
2049 usleep_range(1000, 2000);
2051 if (time_after(jiffies, timeout))
2057 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2059 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2062 mutex_lock(&ps->smi_mutex);
2063 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2066 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2068 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2069 mutex_unlock(&ps->smi_mutex);
2073 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2076 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2079 mutex_lock(&ps->smi_mutex);
2080 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2084 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2086 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2087 mutex_unlock(&ps->smi_mutex);
2091 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2093 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2095 if (port >= 0 && port < ps->num_ports)
2101 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2103 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2104 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2110 mutex_lock(&ps->smi_mutex);
2111 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2112 mutex_unlock(&ps->smi_mutex);
2117 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2119 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2120 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2126 mutex_lock(&ps->smi_mutex);
2127 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2128 mutex_unlock(&ps->smi_mutex);
2133 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2135 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2136 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2142 mutex_lock(&ps->smi_mutex);
2143 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2144 mutex_unlock(&ps->smi_mutex);
2149 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2152 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2153 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2159 mutex_lock(&ps->smi_mutex);
2160 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2161 mutex_unlock(&ps->smi_mutex);
2165 static int __init mv88e6xxx_init(void)
2167 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2168 register_switch_driver(&mv88e6131_switch_driver);
2170 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2171 register_switch_driver(&mv88e6123_61_65_switch_driver);
2173 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2174 register_switch_driver(&mv88e6352_switch_driver);
2176 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2177 register_switch_driver(&mv88e6171_switch_driver);
2181 module_init(mv88e6xxx_init);
2183 static void __exit mv88e6xxx_cleanup(void)
2185 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2186 unregister_switch_driver(&mv88e6171_switch_driver);
2188 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2189 unregister_switch_driver(&mv88e6352_switch_driver);
2191 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2192 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2194 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2195 unregister_switch_driver(&mv88e6131_switch_driver);
2198 module_exit(mv88e6xxx_cleanup);
2200 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2201 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2202 MODULE_LICENSE("GPL");