2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/debugfs.h>
12 #include <linux/delay.h>
13 #include <linux/etherdevice.h>
14 #include <linux/if_bridge.h>
15 #include <linux/jiffies.h>
16 #include <linux/list.h>
17 #include <linux/module.h>
18 #include <linux/netdevice.h>
19 #include <linux/phy.h>
20 #include <linux/seq_file.h>
22 #include "mv88e6xxx.h"
24 /* MDIO bus access can be nested in the case of PHYs connected to the
25 * internal MDIO bus of the switch, which is accessed via MDIO bus of
26 * the Ethernet interface. Avoid lockdep false positives by using
27 * mutex_lock_nested().
29 static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
33 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
34 ret = bus->read(bus, addr, regnum);
35 mutex_unlock(&bus->mdio_lock);
40 static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum,
45 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
46 ret = bus->write(bus, addr, regnum, val);
47 mutex_unlock(&bus->mdio_lock);
52 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
53 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
54 * will be directly accessible on some {device address,register address}
55 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
56 * will only respond to SMI transactions to that specific address, and
57 * an indirect addressing mechanism needs to be used to access its
60 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
65 for (i = 0; i < 16; i++) {
66 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD);
70 if ((ret & SMI_CMD_BUSY) == 0)
77 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
82 return mv88e6xxx_mdiobus_read(bus, addr, reg);
84 /* Wait for the bus to become free. */
85 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
89 /* Transmit the read command. */
90 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
91 SMI_CMD_OP_22_READ | (addr << 5) | reg);
95 /* Wait for the read command to complete. */
96 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
101 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA);
108 /* Must be called with SMI mutex held */
109 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
111 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
117 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
121 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
127 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
129 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
132 mutex_lock(&ps->smi_mutex);
133 ret = _mv88e6xxx_reg_read(ds, addr, reg);
134 mutex_unlock(&ps->smi_mutex);
139 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
145 return mv88e6xxx_mdiobus_write(bus, addr, reg, val);
147 /* Wait for the bus to become free. */
148 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
152 /* Transmit the data to write. */
153 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val);
157 /* Transmit the write command. */
158 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
159 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
163 /* Wait for the write command to complete. */
164 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
171 /* Must be called with SMI mutex held */
172 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
175 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
180 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
183 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
186 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
188 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
191 mutex_lock(&ps->smi_mutex);
192 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
193 mutex_unlock(&ps->smi_mutex);
198 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
200 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
201 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
202 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
207 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
212 for (i = 0; i < 6; i++) {
215 /* Write the MAC address byte. */
216 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
217 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
219 /* Wait for the write to complete. */
220 for (j = 0; j < 16; j++) {
221 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
222 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
232 /* Must be called with SMI mutex held */
233 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
236 return _mv88e6xxx_reg_read(ds, addr, regnum);
240 /* Must be called with SMI mutex held */
241 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
245 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
249 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
250 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
253 unsigned long timeout;
255 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
256 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
257 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
259 timeout = jiffies + 1 * HZ;
260 while (time_before(jiffies, timeout)) {
261 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
262 usleep_range(1000, 2000);
263 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
264 GLOBAL_STATUS_PPU_POLLING)
271 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
274 unsigned long timeout;
276 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
277 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
279 timeout = jiffies + 1 * HZ;
280 while (time_before(jiffies, timeout)) {
281 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
282 usleep_range(1000, 2000);
283 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
284 GLOBAL_STATUS_PPU_POLLING)
291 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
293 struct mv88e6xxx_priv_state *ps;
295 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
296 if (mutex_trylock(&ps->ppu_mutex)) {
297 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
299 if (mv88e6xxx_ppu_enable(ds) == 0)
300 ps->ppu_disabled = 0;
301 mutex_unlock(&ps->ppu_mutex);
305 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
307 struct mv88e6xxx_priv_state *ps = (void *)_ps;
309 schedule_work(&ps->ppu_work);
312 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
314 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
317 mutex_lock(&ps->ppu_mutex);
319 /* If the PHY polling unit is enabled, disable it so that
320 * we can access the PHY registers. If it was already
321 * disabled, cancel the timer that is going to re-enable
324 if (!ps->ppu_disabled) {
325 ret = mv88e6xxx_ppu_disable(ds);
327 mutex_unlock(&ps->ppu_mutex);
330 ps->ppu_disabled = 1;
332 del_timer(&ps->ppu_timer);
339 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
341 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
343 /* Schedule a timer to re-enable the PHY polling unit. */
344 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
345 mutex_unlock(&ps->ppu_mutex);
348 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
350 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
352 mutex_init(&ps->ppu_mutex);
353 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
354 init_timer(&ps->ppu_timer);
355 ps->ppu_timer.data = (unsigned long)ps;
356 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
359 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
363 ret = mv88e6xxx_ppu_access_get(ds);
365 ret = mv88e6xxx_reg_read(ds, addr, regnum);
366 mv88e6xxx_ppu_access_put(ds);
372 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
377 ret = mv88e6xxx_ppu_access_get(ds);
379 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
380 mv88e6xxx_ppu_access_put(ds);
387 void mv88e6xxx_poll_link(struct dsa_switch *ds)
391 for (i = 0; i < DSA_MAX_PORTS; i++) {
392 struct net_device *dev;
393 int uninitialized_var(port_status);
404 if (dev->flags & IFF_UP) {
405 port_status = mv88e6xxx_reg_read(ds, REG_PORT(i),
410 link = !!(port_status & PORT_STATUS_LINK);
414 if (netif_carrier_ok(dev)) {
415 netdev_info(dev, "link down\n");
416 netif_carrier_off(dev);
421 switch (port_status & PORT_STATUS_SPEED_MASK) {
422 case PORT_STATUS_SPEED_10:
425 case PORT_STATUS_SPEED_100:
428 case PORT_STATUS_SPEED_1000:
435 duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0;
436 fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0;
438 if (!netif_carrier_ok(dev)) {
440 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
442 duplex ? "full" : "half",
444 netif_carrier_on(dev);
449 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
451 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
454 case PORT_SWITCH_ID_6031:
455 case PORT_SWITCH_ID_6061:
456 case PORT_SWITCH_ID_6035:
457 case PORT_SWITCH_ID_6065:
463 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
465 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
468 case PORT_SWITCH_ID_6092:
469 case PORT_SWITCH_ID_6095:
475 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
477 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
480 case PORT_SWITCH_ID_6046:
481 case PORT_SWITCH_ID_6085:
482 case PORT_SWITCH_ID_6096:
483 case PORT_SWITCH_ID_6097:
489 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
491 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
494 case PORT_SWITCH_ID_6123:
495 case PORT_SWITCH_ID_6161:
496 case PORT_SWITCH_ID_6165:
502 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
504 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
507 case PORT_SWITCH_ID_6121:
508 case PORT_SWITCH_ID_6122:
509 case PORT_SWITCH_ID_6152:
510 case PORT_SWITCH_ID_6155:
511 case PORT_SWITCH_ID_6182:
512 case PORT_SWITCH_ID_6185:
513 case PORT_SWITCH_ID_6108:
514 case PORT_SWITCH_ID_6131:
520 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
522 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
525 case PORT_SWITCH_ID_6320:
526 case PORT_SWITCH_ID_6321:
532 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
534 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
537 case PORT_SWITCH_ID_6171:
538 case PORT_SWITCH_ID_6175:
539 case PORT_SWITCH_ID_6350:
540 case PORT_SWITCH_ID_6351:
546 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
548 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
551 case PORT_SWITCH_ID_6172:
552 case PORT_SWITCH_ID_6176:
553 case PORT_SWITCH_ID_6240:
554 case PORT_SWITCH_ID_6352:
560 /* Must be called with SMI mutex held */
561 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
566 for (i = 0; i < 10; i++) {
567 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
568 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
575 /* Must be called with SMI mutex held */
576 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
580 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
581 port = (port + 1) << 5;
583 /* Snapshot the hardware statistics counters for this port. */
584 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
585 GLOBAL_STATS_OP_CAPTURE_PORT |
586 GLOBAL_STATS_OP_HIST_RX_TX | port);
590 /* Wait for the snapshotting to complete. */
591 ret = _mv88e6xxx_stats_wait(ds);
598 /* Must be called with SMI mutex held */
599 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
606 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
607 GLOBAL_STATS_OP_READ_CAPTURED |
608 GLOBAL_STATS_OP_HIST_RX_TX | stat);
612 ret = _mv88e6xxx_stats_wait(ds);
616 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
622 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
629 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
630 { "in_good_octets", 8, 0x00, },
631 { "in_bad_octets", 4, 0x02, },
632 { "in_unicast", 4, 0x04, },
633 { "in_broadcasts", 4, 0x06, },
634 { "in_multicasts", 4, 0x07, },
635 { "in_pause", 4, 0x16, },
636 { "in_undersize", 4, 0x18, },
637 { "in_fragments", 4, 0x19, },
638 { "in_oversize", 4, 0x1a, },
639 { "in_jabber", 4, 0x1b, },
640 { "in_rx_error", 4, 0x1c, },
641 { "in_fcs_error", 4, 0x1d, },
642 { "out_octets", 8, 0x0e, },
643 { "out_unicast", 4, 0x10, },
644 { "out_broadcasts", 4, 0x13, },
645 { "out_multicasts", 4, 0x12, },
646 { "out_pause", 4, 0x15, },
647 { "excessive", 4, 0x11, },
648 { "collisions", 4, 0x1e, },
649 { "deferred", 4, 0x05, },
650 { "single", 4, 0x14, },
651 { "multiple", 4, 0x17, },
652 { "out_fcs_error", 4, 0x03, },
653 { "late", 4, 0x1f, },
654 { "hist_64bytes", 4, 0x08, },
655 { "hist_65_127bytes", 4, 0x09, },
656 { "hist_128_255bytes", 4, 0x0a, },
657 { "hist_256_511bytes", 4, 0x0b, },
658 { "hist_512_1023bytes", 4, 0x0c, },
659 { "hist_1024_max_bytes", 4, 0x0d, },
660 /* Not all devices have the following counters */
661 { "sw_in_discards", 4, 0x110, },
662 { "sw_in_filtered", 2, 0x112, },
663 { "sw_out_filtered", 2, 0x113, },
667 static bool have_sw_in_discards(struct dsa_switch *ds)
669 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
672 case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
673 case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
674 case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
675 case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
676 case PORT_SWITCH_ID_6352:
683 static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
685 struct mv88e6xxx_hw_stat *stats,
686 int port, uint8_t *data)
690 for (i = 0; i < nr_stats; i++) {
691 memcpy(data + i * ETH_GSTRING_LEN,
692 stats[i].string, ETH_GSTRING_LEN);
696 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
698 struct mv88e6xxx_hw_stat *stats,
701 struct mv88e6xxx_hw_stat *s = stats + stat;
707 if (s->reg >= 0x100) {
708 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
714 if (s->sizeof_stat == 4) {
715 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
722 _mv88e6xxx_stats_read(ds, s->reg, &low);
723 if (s->sizeof_stat == 8)
724 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
726 value = (((u64)high) << 16) | low;
730 static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
732 struct mv88e6xxx_hw_stat *stats,
733 int port, uint64_t *data)
735 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
739 mutex_lock(&ps->smi_mutex);
741 ret = _mv88e6xxx_stats_snapshot(ds, port);
743 mutex_unlock(&ps->smi_mutex);
747 /* Read each of the counters. */
748 for (i = 0; i < nr_stats; i++)
749 data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port);
751 mutex_unlock(&ps->smi_mutex);
754 /* All the statistics in the table */
756 mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
758 if (have_sw_in_discards(ds))
759 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
760 mv88e6xxx_hw_stats, port, data);
762 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
763 mv88e6xxx_hw_stats, port, data);
766 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
768 if (have_sw_in_discards(ds))
769 return ARRAY_SIZE(mv88e6xxx_hw_stats);
770 return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
774 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
775 int port, uint64_t *data)
777 if (have_sw_in_discards(ds))
778 _mv88e6xxx_get_ethtool_stats(
779 ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
780 mv88e6xxx_hw_stats, port, data);
782 _mv88e6xxx_get_ethtool_stats(
783 ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
784 mv88e6xxx_hw_stats, port, data);
787 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
789 return 32 * sizeof(u16);
792 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
793 struct ethtool_regs *regs, void *_p)
800 memset(p, 0xff, 32 * sizeof(u16));
802 for (i = 0; i < 32; i++) {
805 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
811 /* Must be called with SMI lock held */
812 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
815 unsigned long timeout = jiffies + HZ / 10;
817 while (time_before(jiffies, timeout)) {
820 ret = _mv88e6xxx_reg_read(ds, reg, offset);
826 usleep_range(1000, 2000);
831 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
833 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
836 mutex_lock(&ps->smi_mutex);
837 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
838 mutex_unlock(&ps->smi_mutex);
843 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
845 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
846 GLOBAL2_SMI_OP_BUSY);
849 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
851 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
852 GLOBAL2_EEPROM_OP_LOAD);
855 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
857 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
858 GLOBAL2_EEPROM_OP_BUSY);
861 /* Must be called with SMI lock held */
862 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
864 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
868 /* Must be called with SMI lock held */
869 static int _mv88e6xxx_scratch_wait(struct dsa_switch *ds)
871 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
872 GLOBAL2_SCRATCH_BUSY);
875 /* Must be called with SMI mutex held */
876 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
881 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
882 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
887 ret = _mv88e6xxx_phy_wait(ds);
891 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
894 /* Must be called with SMI mutex held */
895 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
900 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
904 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
905 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
908 return _mv88e6xxx_phy_wait(ds);
911 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
913 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
916 mutex_lock(&ps->smi_mutex);
918 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
922 e->eee_enabled = !!(reg & 0x0200);
923 e->tx_lpi_enabled = !!(reg & 0x0100);
925 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
929 e->eee_active = !!(reg & PORT_STATUS_EEE);
933 mutex_unlock(&ps->smi_mutex);
937 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
938 struct phy_device *phydev, struct ethtool_eee *e)
940 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
944 mutex_lock(&ps->smi_mutex);
946 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
953 if (e->tx_lpi_enabled)
956 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
958 mutex_unlock(&ps->smi_mutex);
963 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
967 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid);
971 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
975 return _mv88e6xxx_atu_wait(ds);
978 static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
982 ret = _mv88e6xxx_atu_wait(ds);
986 return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB);
989 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
991 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
995 mutex_lock(&ps->smi_mutex);
997 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1003 oldstate = reg & PORT_CONTROL_STATE_MASK;
1004 if (oldstate != state) {
1005 /* Flush forwarding database if we're moving a port
1006 * from Learning or Forwarding state to Disabled or
1007 * Blocking or Listening state.
1009 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1010 state <= PORT_CONTROL_STATE_BLOCKING) {
1011 ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
1015 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1016 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1021 mutex_unlock(&ps->smi_mutex);
1025 /* Must be called with smi lock held */
1026 static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
1028 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1029 u8 fid = ps->fid[port];
1030 u16 reg = fid << 12;
1032 if (dsa_is_cpu_port(ds, port))
1033 reg |= ds->phys_port_mask;
1035 reg |= (ps->bridge_mask[fid] |
1036 (1 << dsa_upstream_port(ds))) & ~(1 << port);
1038 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1041 /* Must be called with smi lock held */
1042 static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
1044 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1049 mask = ds->phys_port_mask;
1052 mask &= ~(1 << port);
1053 if (ps->fid[port] != fid)
1056 ret = _mv88e6xxx_update_port_config(ds, port);
1061 return _mv88e6xxx_flush_fid(ds, fid);
1064 /* Bridge handling functions */
1066 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1068 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1073 /* If the bridge group is not empty, join that group.
1074 * Otherwise create a new group.
1076 fid = ps->fid[port];
1077 nmask = br_port_mask & ~(1 << port);
1079 fid = ps->fid[__ffs(nmask)];
1081 nmask = ps->bridge_mask[fid] | (1 << port);
1082 if (nmask != br_port_mask) {
1083 netdev_err(ds->ports[port],
1084 "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1085 fid, br_port_mask, nmask);
1089 mutex_lock(&ps->smi_mutex);
1091 ps->bridge_mask[fid] = br_port_mask;
1093 if (fid != ps->fid[port]) {
1094 ps->fid_mask |= 1 << ps->fid[port];
1095 ps->fid[port] = fid;
1096 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1099 mutex_unlock(&ps->smi_mutex);
1104 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1106 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1110 fid = ps->fid[port];
1112 if (ps->bridge_mask[fid] != br_port_mask) {
1113 netdev_err(ds->ports[port],
1114 "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1115 fid, br_port_mask, ps->bridge_mask[fid]);
1119 /* If the port was the last port of a bridge, we are done.
1120 * Otherwise assign a new fid to the port, and fix up
1121 * the bridge configuration.
1123 if (br_port_mask == (1 << port))
1126 mutex_lock(&ps->smi_mutex);
1128 newfid = __ffs(ps->fid_mask);
1129 ps->fid[port] = newfid;
1130 ps->fid_mask &= ~(1 << newfid);
1131 ps->bridge_mask[fid] &= ~(1 << port);
1132 ps->bridge_mask[newfid] = 1 << port;
1134 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1136 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
1138 mutex_unlock(&ps->smi_mutex);
1143 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1145 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1149 case BR_STATE_DISABLED:
1150 stp_state = PORT_CONTROL_STATE_DISABLED;
1152 case BR_STATE_BLOCKING:
1153 case BR_STATE_LISTENING:
1154 stp_state = PORT_CONTROL_STATE_BLOCKING;
1156 case BR_STATE_LEARNING:
1157 stp_state = PORT_CONTROL_STATE_LEARNING;
1159 case BR_STATE_FORWARDING:
1161 stp_state = PORT_CONTROL_STATE_FORWARDING;
1165 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1167 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1168 * so we can not update the port state directly but need to schedule it.
1170 ps->port_state[port] = stp_state;
1171 set_bit(port, &ps->port_state_update_mask);
1172 schedule_work(&ps->bridge_work);
1177 static int __mv88e6xxx_write_addr(struct dsa_switch *ds,
1178 const unsigned char *addr)
1182 for (i = 0; i < 3; i++) {
1183 ret = _mv88e6xxx_reg_write(
1184 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1185 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1193 static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr)
1197 for (i = 0; i < 3; i++) {
1198 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1199 GLOBAL_ATU_MAC_01 + i);
1202 addr[i * 2] = ret >> 8;
1203 addr[i * 2 + 1] = ret & 0xff;
1209 static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port,
1210 const unsigned char *addr, int state)
1212 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1213 u8 fid = ps->fid[port];
1216 ret = _mv88e6xxx_atu_wait(ds);
1220 ret = __mv88e6xxx_write_addr(ds, addr);
1224 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA,
1225 (0x10 << port) | state);
1229 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_LOAD_DB);
1234 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1235 const unsigned char *addr, u16 vid)
1237 int state = is_multicast_ether_addr(addr) ?
1238 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1239 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1240 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1243 mutex_lock(&ps->smi_mutex);
1244 ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state);
1245 mutex_unlock(&ps->smi_mutex);
1250 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1251 const unsigned char *addr, u16 vid)
1253 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1256 mutex_lock(&ps->smi_mutex);
1257 ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr,
1258 GLOBAL_ATU_DATA_STATE_UNUSED);
1259 mutex_unlock(&ps->smi_mutex);
1264 static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port,
1265 unsigned char *addr, bool *is_static)
1267 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1268 u8 fid = ps->fid[port];
1271 ret = _mv88e6xxx_atu_wait(ds);
1275 ret = __mv88e6xxx_write_addr(ds, addr);
1280 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1284 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1287 state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1288 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
1290 } while (!(((ret >> 4) & 0xff) & (1 << port)));
1292 ret = __mv88e6xxx_read_addr(ds, addr);
1296 *is_static = state == (is_multicast_ether_addr(addr) ?
1297 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1298 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1303 /* get next entry for port */
1304 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
1305 unsigned char *addr, bool *is_static)
1307 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1310 mutex_lock(&ps->smi_mutex);
1311 ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static);
1312 mutex_unlock(&ps->smi_mutex);
1317 static void mv88e6xxx_bridge_work(struct work_struct *work)
1319 struct mv88e6xxx_priv_state *ps;
1320 struct dsa_switch *ds;
1323 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1324 ds = ((struct dsa_switch *)ps) - 1;
1326 while (ps->port_state_update_mask) {
1327 port = __ffs(ps->port_state_update_mask);
1328 clear_bit(port, &ps->port_state_update_mask);
1329 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1333 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
1335 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1339 mutex_lock(&ps->smi_mutex);
1341 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1342 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1343 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1344 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
1345 /* MAC Forcing register: don't force link, speed,
1346 * duplex or flow control state to any particular
1347 * values on physical ports, but force the CPU port
1348 * and all DSA ports to their maximum bandwidth and
1351 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
1352 if (dsa_is_cpu_port(ds, port) ||
1353 ds->dsa_port_mask & (1 << port)) {
1354 reg |= PORT_PCS_CTRL_FORCE_LINK |
1355 PORT_PCS_CTRL_LINK_UP |
1356 PORT_PCS_CTRL_DUPLEX_FULL |
1357 PORT_PCS_CTRL_FORCE_DUPLEX;
1358 if (mv88e6xxx_6065_family(ds))
1359 reg |= PORT_PCS_CTRL_100;
1361 reg |= PORT_PCS_CTRL_1000;
1363 reg |= PORT_PCS_CTRL_UNFORCED;
1366 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1367 PORT_PCS_CTRL, reg);
1372 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1373 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1374 * tunneling, determine priority by looking at 802.1p and IP
1375 * priority fields (IP prio has precedence), and set STP state
1378 * If this is the CPU link, use DSA or EDSA tagging depending
1379 * on which tagging mode was configured.
1381 * If this is a link to another switch, use DSA tagging mode.
1383 * If this is the upstream port for this switch, enable
1384 * forwarding of unknown unicasts and multicasts.
1387 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1388 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1389 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1390 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
1391 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
1392 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
1393 PORT_CONTROL_STATE_FORWARDING;
1394 if (dsa_is_cpu_port(ds, port)) {
1395 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1396 reg |= PORT_CONTROL_DSA_TAG;
1397 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1398 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1399 mv88e6xxx_6320_family(ds)) {
1400 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1401 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
1403 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1406 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1407 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1408 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1409 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
1410 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1411 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
1414 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1415 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1416 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1417 mv88e6xxx_6320_family(ds)) {
1418 if (ds->dsa_port_mask & (1 << port))
1419 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1420 if (port == dsa_upstream_port(ds))
1421 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
1422 PORT_CONTROL_FORWARD_UNKNOWN_MC;
1425 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1431 /* Port Control 2: don't force a good FCS, set the maximum
1432 * frame size to 10240 bytes, don't let the switch add or
1433 * strip 802.1q tags, don't discard tagged or untagged frames
1434 * on this port, do a destination address lookup on all
1435 * received packets as usual, disable ARP mirroring and don't
1436 * send a copy of all transmitted/received frames on this port
1440 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1441 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1442 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
1443 reg = PORT_CONTROL_2_MAP_DA;
1445 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1446 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
1447 reg |= PORT_CONTROL_2_JUMBO_10240;
1449 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
1450 /* Set the upstream port this port should use */
1451 reg |= dsa_upstream_port(ds);
1452 /* enable forwarding of unknown multicast addresses to
1455 if (port == dsa_upstream_port(ds))
1456 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
1460 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1461 PORT_CONTROL_2, reg);
1466 /* Port Association Vector: when learning source addresses
1467 * of packets, add the address to the address database using
1468 * a port bitmap that has only the bit for this port set and
1469 * the other bits clear.
1471 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
1476 /* Egress rate control 2: disable egress rate control. */
1477 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
1482 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1483 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1484 mv88e6xxx_6320_family(ds)) {
1485 /* Do not limit the period of time that this port can
1486 * be paused for by the remote end or the period of
1487 * time that this port can pause the remote end.
1489 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1490 PORT_PAUSE_CTRL, 0x0000);
1494 /* Port ATU control: disable limiting the number of
1495 * address database entries that this port is allowed
1498 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1499 PORT_ATU_CONTROL, 0x0000);
1500 /* Priority Override: disable DA, SA and VTU priority
1503 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1504 PORT_PRI_OVERRIDE, 0x0000);
1508 /* Port Ethertype: use the Ethertype DSA Ethertype
1511 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1512 PORT_ETH_TYPE, ETH_P_EDSA);
1515 /* Tag Remap: use an identity 802.1p prio -> switch
1518 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1519 PORT_TAG_REGMAP_0123, 0x3210);
1523 /* Tag Remap 2: use an identity 802.1p prio -> switch
1526 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1527 PORT_TAG_REGMAP_4567, 0x7654);
1532 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1533 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1534 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1535 mv88e6xxx_6320_family(ds)) {
1536 /* Rate Control: disable ingress rate limiting. */
1537 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1538 PORT_RATE_CONTROL, 0x0001);
1543 /* Port Control 1: disable trunking, disable sending
1544 * learning messages to this port.
1546 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
1550 /* Port based VLAN map: give each port its own address
1551 * database, allow the CPU port to talk to each of the 'real'
1552 * ports, and allow each of the 'real' ports to only talk to
1553 * the upstream port.
1555 fid = __ffs(ps->fid_mask);
1556 ps->fid[port] = fid;
1557 ps->fid_mask &= ~(1 << fid);
1559 if (!dsa_is_cpu_port(ds, port))
1560 ps->bridge_mask[fid] = 1 << port;
1562 ret = _mv88e6xxx_update_port_config(ds, port);
1566 /* Default VLAN ID and priority: don't set a default VLAN
1567 * ID, and set the default packet priority to zero.
1569 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1572 mutex_unlock(&ps->smi_mutex);
1576 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
1578 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1582 for (i = 0; i < ps->num_ports; i++) {
1583 ret = mv88e6xxx_setup_port(ds, i);
1590 static int mv88e6xxx_regs_show(struct seq_file *s, void *p)
1592 struct dsa_switch *ds = s->private;
1594 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1597 seq_puts(s, " GLOBAL GLOBAL2 ");
1598 for (port = 0 ; port < ps->num_ports; port++)
1599 seq_printf(s, " %2d ", port);
1602 for (reg = 0; reg < 32; reg++) {
1603 seq_printf(s, "%2x: ", reg);
1604 seq_printf(s, " %4x %4x ",
1605 mv88e6xxx_reg_read(ds, REG_GLOBAL, reg),
1606 mv88e6xxx_reg_read(ds, REG_GLOBAL2, reg));
1608 for (port = 0 ; port < ps->num_ports; port++)
1609 seq_printf(s, "%4x ",
1610 mv88e6xxx_reg_read(ds, REG_PORT(port), reg));
1617 static int mv88e6xxx_regs_open(struct inode *inode, struct file *file)
1619 return single_open(file, mv88e6xxx_regs_show, inode->i_private);
1622 static const struct file_operations mv88e6xxx_regs_fops = {
1623 .open = mv88e6xxx_regs_open,
1625 .llseek = no_llseek,
1626 .release = single_release,
1627 .owner = THIS_MODULE,
1630 static void mv88e6xxx_atu_show_header(struct seq_file *s)
1632 seq_puts(s, "DB T/P Vec State Addr\n");
1635 static void mv88e6xxx_atu_show_entry(struct seq_file *s, int dbnum,
1636 unsigned char *addr, int data)
1638 bool trunk = !!(data & GLOBAL_ATU_DATA_TRUNK);
1639 int portvec = ((data & GLOBAL_ATU_DATA_PORT_VECTOR_MASK) >>
1640 GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT);
1641 int state = data & GLOBAL_ATU_DATA_STATE_MASK;
1643 seq_printf(s, "%03x %5s %10pb %x %pM\n",
1644 dbnum, (trunk ? "Trunk" : "Port"), &portvec, state, addr);
1647 static int mv88e6xxx_atu_show_db(struct seq_file *s, struct dsa_switch *ds,
1650 unsigned char bcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
1651 unsigned char addr[6];
1652 int ret, data, state;
1654 ret = __mv88e6xxx_write_addr(ds, bcast);
1659 ret = _mv88e6xxx_atu_cmd(ds, dbnum, GLOBAL_ATU_OP_GET_NEXT_DB);
1662 data = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1666 state = data & GLOBAL_ATU_DATA_STATE_MASK;
1667 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
1669 ret = __mv88e6xxx_read_addr(ds, addr);
1672 mv88e6xxx_atu_show_entry(s, dbnum, addr, data);
1673 } while (state != GLOBAL_ATU_DATA_STATE_UNUSED);
1678 static int mv88e6xxx_atu_show(struct seq_file *s, void *p)
1680 struct dsa_switch *ds = s->private;
1681 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1684 mv88e6xxx_atu_show_header(s);
1686 for (dbnum = 0; dbnum < 255; dbnum++) {
1687 mutex_lock(&ps->smi_mutex);
1688 mv88e6xxx_atu_show_db(s, ds, dbnum);
1689 mutex_unlock(&ps->smi_mutex);
1695 static int mv88e6xxx_atu_open(struct inode *inode, struct file *file)
1697 return single_open(file, mv88e6xxx_atu_show, inode->i_private);
1700 static const struct file_operations mv88e6xxx_atu_fops = {
1701 .open = mv88e6xxx_atu_open,
1703 .llseek = no_llseek,
1704 .release = single_release,
1705 .owner = THIS_MODULE,
1708 static void mv88e6xxx_stats_show_header(struct seq_file *s,
1709 struct mv88e6xxx_priv_state *ps)
1713 seq_puts(s, " Statistic ");
1714 for (port = 0 ; port < ps->num_ports; port++)
1715 seq_printf(s, "Port %2d ", port);
1719 static int mv88e6xxx_stats_show(struct seq_file *s, void *p)
1721 struct dsa_switch *ds = s->private;
1722 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1723 struct mv88e6xxx_hw_stat *stats = mv88e6xxx_hw_stats;
1724 int port, stat, max_stats;
1727 if (have_sw_in_discards(ds))
1728 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats);
1730 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
1732 mv88e6xxx_stats_show_header(s, ps);
1734 mutex_lock(&ps->smi_mutex);
1736 for (stat = 0; stat < max_stats; stat++) {
1737 seq_printf(s, "%19s: ", stats[stat].string);
1738 for (port = 0 ; port < ps->num_ports; port++) {
1739 _mv88e6xxx_stats_snapshot(ds, port);
1740 value = _mv88e6xxx_get_ethtool_stat(ds, stat, stats,
1742 seq_printf(s, "%8llu ", value);
1746 mutex_unlock(&ps->smi_mutex);
1751 static int mv88e6xxx_stats_open(struct inode *inode, struct file *file)
1753 return single_open(file, mv88e6xxx_stats_show, inode->i_private);
1756 static const struct file_operations mv88e6xxx_stats_fops = {
1757 .open = mv88e6xxx_stats_open,
1759 .llseek = no_llseek,
1760 .release = single_release,
1761 .owner = THIS_MODULE,
1764 static int mv88e6xxx_device_map_show(struct seq_file *s, void *p)
1766 struct dsa_switch *ds = s->private;
1767 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1770 seq_puts(s, "Target Port\n");
1772 mutex_lock(&ps->smi_mutex);
1773 for (target = 0; target < 32; target++) {
1774 ret = _mv88e6xxx_reg_write(
1775 ds, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
1776 target << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT);
1779 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
1780 GLOBAL2_DEVICE_MAPPING);
1781 seq_printf(s, " %2d %2d\n", target,
1782 ret & GLOBAL2_DEVICE_MAPPING_PORT_MASK);
1785 mutex_unlock(&ps->smi_mutex);
1790 static int mv88e6xxx_device_map_open(struct inode *inode, struct file *file)
1792 return single_open(file, mv88e6xxx_device_map_show, inode->i_private);
1795 static const struct file_operations mv88e6xxx_device_map_fops = {
1796 .open = mv88e6xxx_device_map_open,
1798 .llseek = no_llseek,
1799 .release = single_release,
1800 .owner = THIS_MODULE,
1803 static int mv88e6xxx_scratch_show(struct seq_file *s, void *p)
1805 struct dsa_switch *ds = s->private;
1806 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1809 seq_puts(s, "Register Value\n");
1811 mutex_lock(&ps->smi_mutex);
1812 for (reg = 0; reg < 0x80; reg++) {
1813 ret = _mv88e6xxx_reg_write(
1814 ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
1815 reg << GLOBAL2_SCRATCH_REGISTER_SHIFT);
1819 ret = _mv88e6xxx_scratch_wait(ds);
1823 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
1824 GLOBAL2_SCRATCH_MISC);
1825 seq_printf(s, " %2x %2x\n", reg,
1826 ret & GLOBAL2_SCRATCH_VALUE_MASK);
1829 mutex_unlock(&ps->smi_mutex);
1834 static int mv88e6xxx_scratch_open(struct inode *inode, struct file *file)
1836 return single_open(file, mv88e6xxx_scratch_show, inode->i_private);
1839 static const struct file_operations mv88e6xxx_scratch_fops = {
1840 .open = mv88e6xxx_scratch_open,
1842 .llseek = no_llseek,
1843 .release = single_release,
1844 .owner = THIS_MODULE,
1847 int mv88e6xxx_setup_common(struct dsa_switch *ds)
1849 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1852 mutex_init(&ps->smi_mutex);
1854 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
1856 ps->fid_mask = (1 << DSA_MAX_PORTS) - 1;
1858 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
1860 name = kasprintf(GFP_KERNEL, "dsa%d", ds->index);
1861 ps->dbgfs = debugfs_create_dir(name, NULL);
1864 debugfs_create_file("regs", S_IRUGO, ps->dbgfs, ds,
1865 &mv88e6xxx_regs_fops);
1867 debugfs_create_file("atu", S_IRUGO, ps->dbgfs, ds,
1868 &mv88e6xxx_atu_fops);
1870 debugfs_create_file("stats", S_IRUGO, ps->dbgfs, ds,
1871 &mv88e6xxx_stats_fops);
1873 debugfs_create_file("device_map", S_IRUGO, ps->dbgfs, ds,
1874 &mv88e6xxx_device_map_fops);
1876 debugfs_create_file("scratch", S_IRUGO, ps->dbgfs, ds,
1877 &mv88e6xxx_scratch_fops);
1881 int mv88e6xxx_setup_global(struct dsa_switch *ds)
1883 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1886 /* Set the default address aging time to 5 minutes, and
1887 * enable address learn messages to be sent to all message
1890 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
1891 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
1893 /* Configure the IP ToS mapping registers. */
1894 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
1895 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
1896 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
1897 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
1898 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
1899 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
1900 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
1901 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
1903 /* Configure the IEEE 802.1p priority mapping register. */
1904 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
1906 /* Send all frames with destination addresses matching
1907 * 01:80:c2:00:00:0x to the CPU port.
1909 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
1911 /* Ignore removed tag data on doubly tagged packets, disable
1912 * flow control messages, force flow control priority to the
1913 * highest, and send all special multicast frames to the CPU
1914 * port at the highest priority.
1916 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
1917 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
1918 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
1920 /* Program the DSA routing table. */
1921 for (i = 0; i < 32; i++) {
1924 if (ds->pd->rtable &&
1925 i != ds->index && i < ds->dst->pd->nr_chips)
1926 nexthop = ds->pd->rtable[i] & 0x1f;
1928 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
1929 GLOBAL2_DEVICE_MAPPING_UPDATE |
1930 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
1934 /* Clear all trunk masks. */
1935 for (i = 0; i < 8; i++)
1936 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
1937 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
1938 ((1 << ps->num_ports) - 1));
1940 /* Clear all trunk mappings. */
1941 for (i = 0; i < 16; i++)
1942 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
1943 GLOBAL2_TRUNK_MAPPING_UPDATE |
1944 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
1946 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1947 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1948 mv88e6xxx_6320_family(ds)) {
1949 /* Send all frames with destination addresses matching
1950 * 01:80:c2:00:00:2x to the CPU port.
1952 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
1954 /* Initialise cross-chip port VLAN table to reset
1957 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
1959 /* Clear the priority override table. */
1960 for (i = 0; i < 16; i++)
1961 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
1965 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1966 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1967 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1968 mv88e6xxx_6320_family(ds)) {
1969 /* Disable ingress rate limiting by resetting all
1970 * ingress rate limit registers to their initial
1973 for (i = 0; i < ps->num_ports; i++)
1974 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
1978 /* Clear the statistics counters for all ports */
1979 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
1981 /* Wait for the flush to complete. */
1982 _mv88e6xxx_stats_wait(ds);
1987 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
1989 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1990 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
1991 unsigned long timeout;
1995 /* Set all ports to the disabled state. */
1996 for (i = 0; i < ps->num_ports; i++) {
1997 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
1998 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2001 /* Wait for transmit queues to drain. */
2002 usleep_range(2000, 4000);
2004 /* Reset the switch. Keep the PPU active if requested. The PPU
2005 * needs to be active to support indirect phy register access
2006 * through global registers 0x18 and 0x19.
2009 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2011 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2013 /* Wait up to one second for reset to complete. */
2014 timeout = jiffies + 1 * HZ;
2015 while (time_before(jiffies, timeout)) {
2016 ret = REG_READ(REG_GLOBAL, 0x00);
2017 if ((ret & is_reset) == is_reset)
2019 usleep_range(1000, 2000);
2021 if (time_after(jiffies, timeout))
2027 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2029 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2032 mutex_lock(&ps->smi_mutex);
2033 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2036 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2038 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2039 mutex_unlock(&ps->smi_mutex);
2043 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2046 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2049 mutex_lock(&ps->smi_mutex);
2050 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2054 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2056 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2057 mutex_unlock(&ps->smi_mutex);
2061 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2063 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2065 if (port >= 0 && port < ps->num_ports)
2071 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2073 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2074 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2080 mutex_lock(&ps->smi_mutex);
2081 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2082 mutex_unlock(&ps->smi_mutex);
2087 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2089 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2090 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2096 mutex_lock(&ps->smi_mutex);
2097 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2098 mutex_unlock(&ps->smi_mutex);
2103 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2105 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2106 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2112 mutex_lock(&ps->smi_mutex);
2113 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2114 mutex_unlock(&ps->smi_mutex);
2119 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2122 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2123 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2129 mutex_lock(&ps->smi_mutex);
2130 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2131 mutex_unlock(&ps->smi_mutex);
2135 #ifdef CONFIG_NET_DSA_HWMON
2137 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2139 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2145 mutex_lock(&ps->smi_mutex);
2147 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2151 /* Enable temperature sensor */
2152 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2156 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2160 /* Wait for temperature to stabilize */
2161 usleep_range(10000, 12000);
2163 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2169 /* Disable temperature sensor */
2170 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2174 *temp = ((val & 0x1f) - 5) * 5;
2177 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2178 mutex_unlock(&ps->smi_mutex);
2182 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2184 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2189 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2193 *temp = (ret & 0xff) - 25;
2198 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2200 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2201 return mv88e63xx_get_temp(ds, temp);
2203 return mv88e61xx_get_temp(ds, temp);
2206 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2208 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2211 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2216 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2220 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2225 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2227 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2230 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2233 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2236 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2237 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2238 (ret & 0xe0ff) | (temp << 8));
2241 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2243 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2246 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2251 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2255 *alarm = !!(ret & 0x40);
2259 #endif /* CONFIG_NET_DSA_HWMON */
2261 static int __init mv88e6xxx_init(void)
2263 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2264 register_switch_driver(&mv88e6131_switch_driver);
2266 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2267 register_switch_driver(&mv88e6123_61_65_switch_driver);
2269 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2270 register_switch_driver(&mv88e6352_switch_driver);
2272 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2273 register_switch_driver(&mv88e6171_switch_driver);
2277 module_init(mv88e6xxx_init);
2279 static void __exit mv88e6xxx_cleanup(void)
2281 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2282 unregister_switch_driver(&mv88e6171_switch_driver);
2284 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2285 unregister_switch_driver(&mv88e6352_switch_driver);
2287 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2288 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2290 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2291 unregister_switch_driver(&mv88e6131_switch_driver);
2294 module_exit(mv88e6xxx_cleanup);
2296 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2297 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2298 MODULE_LICENSE("GPL");