2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/debugfs.h>
12 #include <linux/delay.h>
13 #include <linux/etherdevice.h>
14 #include <linux/if_bridge.h>
15 #include <linux/jiffies.h>
16 #include <linux/list.h>
17 #include <linux/module.h>
18 #include <linux/netdevice.h>
19 #include <linux/phy.h>
20 #include <linux/seq_file.h>
22 #include "mv88e6xxx.h"
24 /* MDIO bus access can be nested in the case of PHYs connected to the
25 * internal MDIO bus of the switch, which is accessed via MDIO bus of
26 * the Ethernet interface. Avoid lockdep false positives by using
27 * mutex_lock_nested().
29 static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
33 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
34 ret = bus->read(bus, addr, regnum);
35 mutex_unlock(&bus->mdio_lock);
40 static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum,
45 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
46 ret = bus->write(bus, addr, regnum, val);
47 mutex_unlock(&bus->mdio_lock);
52 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
53 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
54 * will be directly accessible on some {device address,register address}
55 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
56 * will only respond to SMI transactions to that specific address, and
57 * an indirect addressing mechanism needs to be used to access its
60 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
65 for (i = 0; i < 16; i++) {
66 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD);
70 if ((ret & SMI_CMD_BUSY) == 0)
77 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
82 return mv88e6xxx_mdiobus_read(bus, addr, reg);
84 /* Wait for the bus to become free. */
85 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
89 /* Transmit the read command. */
90 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
91 SMI_CMD_OP_22_READ | (addr << 5) | reg);
95 /* Wait for the read command to complete. */
96 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
101 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA);
108 /* Must be called with SMI mutex held */
109 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
111 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
117 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
121 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
127 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
129 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
132 mutex_lock(&ps->smi_mutex);
133 ret = _mv88e6xxx_reg_read(ds, addr, reg);
134 mutex_unlock(&ps->smi_mutex);
139 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
145 return mv88e6xxx_mdiobus_write(bus, addr, reg, val);
147 /* Wait for the bus to become free. */
148 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
152 /* Transmit the data to write. */
153 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val);
157 /* Transmit the write command. */
158 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
159 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
163 /* Wait for the write command to complete. */
164 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
171 /* Must be called with SMI mutex held */
172 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
175 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
180 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
183 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
186 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
188 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
191 mutex_lock(&ps->smi_mutex);
192 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
193 mutex_unlock(&ps->smi_mutex);
198 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
200 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
201 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
202 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
207 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
212 for (i = 0; i < 6; i++) {
215 /* Write the MAC address byte. */
216 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
217 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
219 /* Wait for the write to complete. */
220 for (j = 0; j < 16; j++) {
221 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
222 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
232 /* Must be called with SMI mutex held */
233 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
236 return _mv88e6xxx_reg_read(ds, addr, regnum);
240 /* Must be called with SMI mutex held */
241 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
245 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
249 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
250 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
253 unsigned long timeout;
255 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
256 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
257 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
259 timeout = jiffies + 1 * HZ;
260 while (time_before(jiffies, timeout)) {
261 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
262 usleep_range(1000, 2000);
263 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
264 GLOBAL_STATUS_PPU_POLLING)
271 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
274 unsigned long timeout;
276 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
277 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
279 timeout = jiffies + 1 * HZ;
280 while (time_before(jiffies, timeout)) {
281 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
282 usleep_range(1000, 2000);
283 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
284 GLOBAL_STATUS_PPU_POLLING)
291 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
293 struct mv88e6xxx_priv_state *ps;
295 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
296 if (mutex_trylock(&ps->ppu_mutex)) {
297 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
299 if (mv88e6xxx_ppu_enable(ds) == 0)
300 ps->ppu_disabled = 0;
301 mutex_unlock(&ps->ppu_mutex);
305 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
307 struct mv88e6xxx_priv_state *ps = (void *)_ps;
309 schedule_work(&ps->ppu_work);
312 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
314 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
317 mutex_lock(&ps->ppu_mutex);
319 /* If the PHY polling unit is enabled, disable it so that
320 * we can access the PHY registers. If it was already
321 * disabled, cancel the timer that is going to re-enable
324 if (!ps->ppu_disabled) {
325 ret = mv88e6xxx_ppu_disable(ds);
327 mutex_unlock(&ps->ppu_mutex);
330 ps->ppu_disabled = 1;
332 del_timer(&ps->ppu_timer);
339 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
341 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
343 /* Schedule a timer to re-enable the PHY polling unit. */
344 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
345 mutex_unlock(&ps->ppu_mutex);
348 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
350 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
352 mutex_init(&ps->ppu_mutex);
353 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
354 init_timer(&ps->ppu_timer);
355 ps->ppu_timer.data = (unsigned long)ps;
356 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
359 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
363 ret = mv88e6xxx_ppu_access_get(ds);
365 ret = mv88e6xxx_reg_read(ds, addr, regnum);
366 mv88e6xxx_ppu_access_put(ds);
372 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
377 ret = mv88e6xxx_ppu_access_get(ds);
379 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
380 mv88e6xxx_ppu_access_put(ds);
387 void mv88e6xxx_poll_link(struct dsa_switch *ds)
391 for (i = 0; i < DSA_MAX_PORTS; i++) {
392 struct net_device *dev;
393 int uninitialized_var(port_status);
404 if (dev->flags & IFF_UP) {
405 port_status = mv88e6xxx_reg_read(ds, REG_PORT(i),
410 link = !!(port_status & PORT_STATUS_LINK);
414 if (netif_carrier_ok(dev)) {
415 netdev_info(dev, "link down\n");
416 netif_carrier_off(dev);
421 switch (port_status & PORT_STATUS_SPEED_MASK) {
422 case PORT_STATUS_SPEED_10:
425 case PORT_STATUS_SPEED_100:
428 case PORT_STATUS_SPEED_1000:
435 duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0;
436 fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0;
438 if (!netif_carrier_ok(dev)) {
440 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
442 duplex ? "full" : "half",
444 netif_carrier_on(dev);
449 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
451 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
454 case PORT_SWITCH_ID_6031:
455 case PORT_SWITCH_ID_6061:
456 case PORT_SWITCH_ID_6035:
457 case PORT_SWITCH_ID_6065:
463 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
465 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
468 case PORT_SWITCH_ID_6092:
469 case PORT_SWITCH_ID_6095:
475 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
477 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
480 case PORT_SWITCH_ID_6046:
481 case PORT_SWITCH_ID_6085:
482 case PORT_SWITCH_ID_6096:
483 case PORT_SWITCH_ID_6097:
489 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
491 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
494 case PORT_SWITCH_ID_6123:
495 case PORT_SWITCH_ID_6161:
496 case PORT_SWITCH_ID_6165:
502 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
504 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
507 case PORT_SWITCH_ID_6121:
508 case PORT_SWITCH_ID_6122:
509 case PORT_SWITCH_ID_6152:
510 case PORT_SWITCH_ID_6155:
511 case PORT_SWITCH_ID_6182:
512 case PORT_SWITCH_ID_6185:
513 case PORT_SWITCH_ID_6108:
514 case PORT_SWITCH_ID_6131:
520 bool mv88e6xxx_6320_family(struct dsa_switch *ds)
522 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
525 case PORT_SWITCH_ID_6320:
526 case PORT_SWITCH_ID_6321:
532 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
534 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
537 case PORT_SWITCH_ID_6171:
538 case PORT_SWITCH_ID_6175:
539 case PORT_SWITCH_ID_6350:
540 case PORT_SWITCH_ID_6351:
546 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
548 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
551 case PORT_SWITCH_ID_6172:
552 case PORT_SWITCH_ID_6176:
553 case PORT_SWITCH_ID_6240:
554 case PORT_SWITCH_ID_6352:
560 /* Must be called with SMI mutex held */
561 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
566 for (i = 0; i < 10; i++) {
567 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
568 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
575 /* Must be called with SMI mutex held */
576 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
580 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
581 port = (port + 1) << 5;
583 /* Snapshot the hardware statistics counters for this port. */
584 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
585 GLOBAL_STATS_OP_CAPTURE_PORT |
586 GLOBAL_STATS_OP_HIST_RX_TX | port);
590 /* Wait for the snapshotting to complete. */
591 ret = _mv88e6xxx_stats_wait(ds);
598 /* Must be called with SMI mutex held */
599 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
606 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
607 GLOBAL_STATS_OP_READ_CAPTURED |
608 GLOBAL_STATS_OP_HIST_RX_TX | stat);
612 ret = _mv88e6xxx_stats_wait(ds);
616 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
622 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
629 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
630 { "in_good_octets", 8, 0x00, },
631 { "in_bad_octets", 4, 0x02, },
632 { "in_unicast", 4, 0x04, },
633 { "in_broadcasts", 4, 0x06, },
634 { "in_multicasts", 4, 0x07, },
635 { "in_pause", 4, 0x16, },
636 { "in_undersize", 4, 0x18, },
637 { "in_fragments", 4, 0x19, },
638 { "in_oversize", 4, 0x1a, },
639 { "in_jabber", 4, 0x1b, },
640 { "in_rx_error", 4, 0x1c, },
641 { "in_fcs_error", 4, 0x1d, },
642 { "out_octets", 8, 0x0e, },
643 { "out_unicast", 4, 0x10, },
644 { "out_broadcasts", 4, 0x13, },
645 { "out_multicasts", 4, 0x12, },
646 { "out_pause", 4, 0x15, },
647 { "excessive", 4, 0x11, },
648 { "collisions", 4, 0x1e, },
649 { "deferred", 4, 0x05, },
650 { "single", 4, 0x14, },
651 { "multiple", 4, 0x17, },
652 { "out_fcs_error", 4, 0x03, },
653 { "late", 4, 0x1f, },
654 { "hist_64bytes", 4, 0x08, },
655 { "hist_65_127bytes", 4, 0x09, },
656 { "hist_128_255bytes", 4, 0x0a, },
657 { "hist_256_511bytes", 4, 0x0b, },
658 { "hist_512_1023bytes", 4, 0x0c, },
659 { "hist_1024_max_bytes", 4, 0x0d, },
660 /* Not all devices have the following counters */
661 { "sw_in_discards", 4, 0x110, },
662 { "sw_in_filtered", 2, 0x112, },
663 { "sw_out_filtered", 2, 0x113, },
667 static bool have_sw_in_discards(struct dsa_switch *ds)
669 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
672 case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
673 case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
674 case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
675 case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
676 case PORT_SWITCH_ID_6352:
683 static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
685 struct mv88e6xxx_hw_stat *stats,
686 int port, uint8_t *data)
690 for (i = 0; i < nr_stats; i++) {
691 memcpy(data + i * ETH_GSTRING_LEN,
692 stats[i].string, ETH_GSTRING_LEN);
696 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
698 struct mv88e6xxx_hw_stat *stats,
701 struct mv88e6xxx_hw_stat *s = stats + stat;
707 if (s->reg >= 0x100) {
708 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
714 if (s->sizeof_stat == 4) {
715 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
722 _mv88e6xxx_stats_read(ds, s->reg, &low);
723 if (s->sizeof_stat == 8)
724 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
726 value = (((u64)high) << 16) | low;
730 static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
732 struct mv88e6xxx_hw_stat *stats,
733 int port, uint64_t *data)
735 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
739 mutex_lock(&ps->smi_mutex);
741 ret = _mv88e6xxx_stats_snapshot(ds, port);
743 mutex_unlock(&ps->smi_mutex);
747 /* Read each of the counters. */
748 for (i = 0; i < nr_stats; i++)
749 data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port);
751 mutex_unlock(&ps->smi_mutex);
754 /* All the statistics in the table */
756 mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
758 if (have_sw_in_discards(ds))
759 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
760 mv88e6xxx_hw_stats, port, data);
762 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
763 mv88e6xxx_hw_stats, port, data);
766 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
768 if (have_sw_in_discards(ds))
769 return ARRAY_SIZE(mv88e6xxx_hw_stats);
770 return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
774 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
775 int port, uint64_t *data)
777 if (have_sw_in_discards(ds))
778 _mv88e6xxx_get_ethtool_stats(
779 ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
780 mv88e6xxx_hw_stats, port, data);
782 _mv88e6xxx_get_ethtool_stats(
783 ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
784 mv88e6xxx_hw_stats, port, data);
787 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
789 return 32 * sizeof(u16);
792 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
793 struct ethtool_regs *regs, void *_p)
800 memset(p, 0xff, 32 * sizeof(u16));
802 for (i = 0; i < 32; i++) {
805 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
811 #ifdef CONFIG_NET_DSA_HWMON
813 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
815 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
821 mutex_lock(&ps->smi_mutex);
823 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
827 /* Enable temperature sensor */
828 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
832 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
836 /* Wait for temperature to stabilize */
837 usleep_range(10000, 12000);
839 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
845 /* Disable temperature sensor */
846 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
850 *temp = ((val & 0x1f) - 5) * 5;
853 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
854 mutex_unlock(&ps->smi_mutex);
857 #endif /* CONFIG_NET_DSA_HWMON */
859 /* Must be called with SMI lock held */
860 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
863 unsigned long timeout = jiffies + HZ / 10;
865 while (time_before(jiffies, timeout)) {
868 ret = _mv88e6xxx_reg_read(ds, reg, offset);
874 usleep_range(1000, 2000);
879 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
881 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
884 mutex_lock(&ps->smi_mutex);
885 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
886 mutex_unlock(&ps->smi_mutex);
891 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
893 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
894 GLOBAL2_SMI_OP_BUSY);
897 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
899 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
900 GLOBAL2_EEPROM_OP_LOAD);
903 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
905 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
906 GLOBAL2_EEPROM_OP_BUSY);
909 /* Must be called with SMI lock held */
910 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
912 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
916 /* Must be called with SMI lock held */
917 static int _mv88e6xxx_scratch_wait(struct dsa_switch *ds)
919 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
920 GLOBAL2_SCRATCH_BUSY);
923 /* Must be called with SMI mutex held */
924 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
929 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
930 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
935 ret = _mv88e6xxx_phy_wait(ds);
939 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
942 /* Must be called with SMI mutex held */
943 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
948 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
952 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
953 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
956 return _mv88e6xxx_phy_wait(ds);
959 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
961 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
964 mutex_lock(&ps->smi_mutex);
966 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
970 e->eee_enabled = !!(reg & 0x0200);
971 e->tx_lpi_enabled = !!(reg & 0x0100);
973 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
977 e->eee_active = !!(reg & PORT_STATUS_EEE);
981 mutex_unlock(&ps->smi_mutex);
985 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
986 struct phy_device *phydev, struct ethtool_eee *e)
988 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
992 mutex_lock(&ps->smi_mutex);
994 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
1001 if (e->tx_lpi_enabled)
1004 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
1006 mutex_unlock(&ps->smi_mutex);
1011 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
1015 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid);
1019 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1023 return _mv88e6xxx_atu_wait(ds);
1026 static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
1030 ret = _mv88e6xxx_atu_wait(ds);
1034 return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB);
1037 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1039 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1043 mutex_lock(&ps->smi_mutex);
1045 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1051 oldstate = reg & PORT_CONTROL_STATE_MASK;
1052 if (oldstate != state) {
1053 /* Flush forwarding database if we're moving a port
1054 * from Learning or Forwarding state to Disabled or
1055 * Blocking or Listening state.
1057 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1058 state <= PORT_CONTROL_STATE_BLOCKING) {
1059 ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
1063 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1064 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1069 mutex_unlock(&ps->smi_mutex);
1073 /* Must be called with smi lock held */
1074 static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
1076 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1077 u8 fid = ps->fid[port];
1078 u16 reg = fid << 12;
1080 if (dsa_is_cpu_port(ds, port))
1081 reg |= ds->phys_port_mask;
1083 reg |= (ps->bridge_mask[fid] |
1084 (1 << dsa_upstream_port(ds))) & ~(1 << port);
1086 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1089 /* Must be called with smi lock held */
1090 static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
1092 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1097 mask = ds->phys_port_mask;
1100 mask &= ~(1 << port);
1101 if (ps->fid[port] != fid)
1104 ret = _mv88e6xxx_update_port_config(ds, port);
1109 return _mv88e6xxx_flush_fid(ds, fid);
1112 /* Bridge handling functions */
1114 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1116 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1121 /* If the bridge group is not empty, join that group.
1122 * Otherwise create a new group.
1124 fid = ps->fid[port];
1125 nmask = br_port_mask & ~(1 << port);
1127 fid = ps->fid[__ffs(nmask)];
1129 nmask = ps->bridge_mask[fid] | (1 << port);
1130 if (nmask != br_port_mask) {
1131 netdev_err(ds->ports[port],
1132 "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1133 fid, br_port_mask, nmask);
1137 mutex_lock(&ps->smi_mutex);
1139 ps->bridge_mask[fid] = br_port_mask;
1141 if (fid != ps->fid[port]) {
1142 ps->fid_mask |= 1 << ps->fid[port];
1143 ps->fid[port] = fid;
1144 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1147 mutex_unlock(&ps->smi_mutex);
1152 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1154 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1158 fid = ps->fid[port];
1160 if (ps->bridge_mask[fid] != br_port_mask) {
1161 netdev_err(ds->ports[port],
1162 "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1163 fid, br_port_mask, ps->bridge_mask[fid]);
1167 /* If the port was the last port of a bridge, we are done.
1168 * Otherwise assign a new fid to the port, and fix up
1169 * the bridge configuration.
1171 if (br_port_mask == (1 << port))
1174 mutex_lock(&ps->smi_mutex);
1176 newfid = __ffs(ps->fid_mask);
1177 ps->fid[port] = newfid;
1178 ps->fid_mask &= ~(1 << newfid);
1179 ps->bridge_mask[fid] &= ~(1 << port);
1180 ps->bridge_mask[newfid] = 1 << port;
1182 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1184 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
1186 mutex_unlock(&ps->smi_mutex);
1191 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1193 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1197 case BR_STATE_DISABLED:
1198 stp_state = PORT_CONTROL_STATE_DISABLED;
1200 case BR_STATE_BLOCKING:
1201 case BR_STATE_LISTENING:
1202 stp_state = PORT_CONTROL_STATE_BLOCKING;
1204 case BR_STATE_LEARNING:
1205 stp_state = PORT_CONTROL_STATE_LEARNING;
1207 case BR_STATE_FORWARDING:
1209 stp_state = PORT_CONTROL_STATE_FORWARDING;
1213 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1215 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1216 * so we can not update the port state directly but need to schedule it.
1218 ps->port_state[port] = stp_state;
1219 set_bit(port, &ps->port_state_update_mask);
1220 schedule_work(&ps->bridge_work);
1225 static int __mv88e6xxx_write_addr(struct dsa_switch *ds,
1226 const unsigned char *addr)
1230 for (i = 0; i < 3; i++) {
1231 ret = _mv88e6xxx_reg_write(
1232 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1233 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1241 static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr)
1245 for (i = 0; i < 3; i++) {
1246 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1247 GLOBAL_ATU_MAC_01 + i);
1250 addr[i * 2] = ret >> 8;
1251 addr[i * 2 + 1] = ret & 0xff;
1257 static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port,
1258 const unsigned char *addr, int state)
1260 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1261 u8 fid = ps->fid[port];
1264 ret = _mv88e6xxx_atu_wait(ds);
1268 ret = __mv88e6xxx_write_addr(ds, addr);
1272 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA,
1273 (0x10 << port) | state);
1277 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_LOAD_DB);
1282 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1283 const unsigned char *addr, u16 vid)
1285 int state = is_multicast_ether_addr(addr) ?
1286 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1287 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1288 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1291 mutex_lock(&ps->smi_mutex);
1292 ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state);
1293 mutex_unlock(&ps->smi_mutex);
1298 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1299 const unsigned char *addr, u16 vid)
1301 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1304 mutex_lock(&ps->smi_mutex);
1305 ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr,
1306 GLOBAL_ATU_DATA_STATE_UNUSED);
1307 mutex_unlock(&ps->smi_mutex);
1312 static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port,
1313 unsigned char *addr, bool *is_static)
1315 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1316 u8 fid = ps->fid[port];
1319 ret = _mv88e6xxx_atu_wait(ds);
1323 ret = __mv88e6xxx_write_addr(ds, addr);
1328 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1332 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1335 state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1336 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
1338 } while (!(((ret >> 4) & 0xff) & (1 << port)));
1340 ret = __mv88e6xxx_read_addr(ds, addr);
1344 *is_static = state == (is_multicast_ether_addr(addr) ?
1345 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1346 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1351 /* get next entry for port */
1352 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
1353 unsigned char *addr, bool *is_static)
1355 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1358 mutex_lock(&ps->smi_mutex);
1359 ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static);
1360 mutex_unlock(&ps->smi_mutex);
1365 static void mv88e6xxx_bridge_work(struct work_struct *work)
1367 struct mv88e6xxx_priv_state *ps;
1368 struct dsa_switch *ds;
1371 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1372 ds = ((struct dsa_switch *)ps) - 1;
1374 while (ps->port_state_update_mask) {
1375 port = __ffs(ps->port_state_update_mask);
1376 clear_bit(port, &ps->port_state_update_mask);
1377 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1381 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
1383 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1387 mutex_lock(&ps->smi_mutex);
1389 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1390 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1391 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1392 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
1393 /* MAC Forcing register: don't force link, speed,
1394 * duplex or flow control state to any particular
1395 * values on physical ports, but force the CPU port
1396 * and all DSA ports to their maximum bandwidth and
1399 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
1400 if (dsa_is_cpu_port(ds, port) ||
1401 ds->dsa_port_mask & (1 << port)) {
1402 reg |= PORT_PCS_CTRL_FORCE_LINK |
1403 PORT_PCS_CTRL_LINK_UP |
1404 PORT_PCS_CTRL_DUPLEX_FULL |
1405 PORT_PCS_CTRL_FORCE_DUPLEX;
1406 if (mv88e6xxx_6065_family(ds))
1407 reg |= PORT_PCS_CTRL_100;
1409 reg |= PORT_PCS_CTRL_1000;
1411 reg |= PORT_PCS_CTRL_UNFORCED;
1414 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1415 PORT_PCS_CTRL, reg);
1420 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1421 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1422 * tunneling, determine priority by looking at 802.1p and IP
1423 * priority fields (IP prio has precedence), and set STP state
1426 * If this is the CPU link, use DSA or EDSA tagging depending
1427 * on which tagging mode was configured.
1429 * If this is a link to another switch, use DSA tagging mode.
1431 * If this is the upstream port for this switch, enable
1432 * forwarding of unknown unicasts and multicasts.
1435 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1436 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1437 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1438 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
1439 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
1440 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
1441 PORT_CONTROL_STATE_FORWARDING;
1442 if (dsa_is_cpu_port(ds, port)) {
1443 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1444 reg |= PORT_CONTROL_DSA_TAG;
1445 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1446 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1447 mv88e6xxx_6320_family(ds)) {
1448 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1449 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
1451 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1454 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1455 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1456 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1457 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
1458 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1459 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
1462 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1463 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1464 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1465 mv88e6xxx_6320_family(ds)) {
1466 if (ds->dsa_port_mask & (1 << port))
1467 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1468 if (port == dsa_upstream_port(ds))
1469 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
1470 PORT_CONTROL_FORWARD_UNKNOWN_MC;
1473 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1479 /* Port Control 2: don't force a good FCS, set the maximum
1480 * frame size to 10240 bytes, don't let the switch add or
1481 * strip 802.1q tags, don't discard tagged or untagged frames
1482 * on this port, do a destination address lookup on all
1483 * received packets as usual, disable ARP mirroring and don't
1484 * send a copy of all transmitted/received frames on this port
1488 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1489 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1490 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
1491 reg = PORT_CONTROL_2_MAP_DA;
1493 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1494 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
1495 reg |= PORT_CONTROL_2_JUMBO_10240;
1497 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
1498 /* Set the upstream port this port should use */
1499 reg |= dsa_upstream_port(ds);
1500 /* enable forwarding of unknown multicast addresses to
1503 if (port == dsa_upstream_port(ds))
1504 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
1508 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1509 PORT_CONTROL_2, reg);
1514 /* Port Association Vector: when learning source addresses
1515 * of packets, add the address to the address database using
1516 * a port bitmap that has only the bit for this port set and
1517 * the other bits clear.
1519 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
1524 /* Egress rate control 2: disable egress rate control. */
1525 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
1530 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1531 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1532 mv88e6xxx_6320_family(ds)) {
1533 /* Do not limit the period of time that this port can
1534 * be paused for by the remote end or the period of
1535 * time that this port can pause the remote end.
1537 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1538 PORT_PAUSE_CTRL, 0x0000);
1542 /* Port ATU control: disable limiting the number of
1543 * address database entries that this port is allowed
1546 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1547 PORT_ATU_CONTROL, 0x0000);
1548 /* Priority Override: disable DA, SA and VTU priority
1551 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1552 PORT_PRI_OVERRIDE, 0x0000);
1556 /* Port Ethertype: use the Ethertype DSA Ethertype
1559 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1560 PORT_ETH_TYPE, ETH_P_EDSA);
1563 /* Tag Remap: use an identity 802.1p prio -> switch
1566 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1567 PORT_TAG_REGMAP_0123, 0x3210);
1571 /* Tag Remap 2: use an identity 802.1p prio -> switch
1574 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1575 PORT_TAG_REGMAP_4567, 0x7654);
1580 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1581 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1582 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1583 mv88e6xxx_6320_family(ds)) {
1584 /* Rate Control: disable ingress rate limiting. */
1585 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1586 PORT_RATE_CONTROL, 0x0001);
1591 /* Port Control 1: disable trunking, disable sending
1592 * learning messages to this port.
1594 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
1598 /* Port based VLAN map: give each port its own address
1599 * database, allow the CPU port to talk to each of the 'real'
1600 * ports, and allow each of the 'real' ports to only talk to
1601 * the upstream port.
1603 fid = __ffs(ps->fid_mask);
1604 ps->fid[port] = fid;
1605 ps->fid_mask &= ~(1 << fid);
1607 if (!dsa_is_cpu_port(ds, port))
1608 ps->bridge_mask[fid] = 1 << port;
1610 ret = _mv88e6xxx_update_port_config(ds, port);
1614 /* Default VLAN ID and priority: don't set a default VLAN
1615 * ID, and set the default packet priority to zero.
1617 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1620 mutex_unlock(&ps->smi_mutex);
1624 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
1626 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1630 for (i = 0; i < ps->num_ports; i++) {
1631 ret = mv88e6xxx_setup_port(ds, i);
1638 static int mv88e6xxx_regs_show(struct seq_file *s, void *p)
1640 struct dsa_switch *ds = s->private;
1642 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1645 seq_puts(s, " GLOBAL GLOBAL2 ");
1646 for (port = 0 ; port < ps->num_ports; port++)
1647 seq_printf(s, " %2d ", port);
1650 for (reg = 0; reg < 32; reg++) {
1651 seq_printf(s, "%2x: ", reg);
1652 seq_printf(s, " %4x %4x ",
1653 mv88e6xxx_reg_read(ds, REG_GLOBAL, reg),
1654 mv88e6xxx_reg_read(ds, REG_GLOBAL2, reg));
1656 for (port = 0 ; port < ps->num_ports; port++)
1657 seq_printf(s, "%4x ",
1658 mv88e6xxx_reg_read(ds, REG_PORT(port), reg));
1665 static int mv88e6xxx_regs_open(struct inode *inode, struct file *file)
1667 return single_open(file, mv88e6xxx_regs_show, inode->i_private);
1670 static const struct file_operations mv88e6xxx_regs_fops = {
1671 .open = mv88e6xxx_regs_open,
1673 .llseek = no_llseek,
1674 .release = single_release,
1675 .owner = THIS_MODULE,
1678 static void mv88e6xxx_atu_show_header(struct seq_file *s)
1680 seq_puts(s, "DB T/P Vec State Addr\n");
1683 static void mv88e6xxx_atu_show_entry(struct seq_file *s, int dbnum,
1684 unsigned char *addr, int data)
1686 bool trunk = !!(data & GLOBAL_ATU_DATA_TRUNK);
1687 int portvec = ((data & GLOBAL_ATU_DATA_PORT_VECTOR_MASK) >>
1688 GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT);
1689 int state = data & GLOBAL_ATU_DATA_STATE_MASK;
1691 seq_printf(s, "%03x %5s %10pb %x %pM\n",
1692 dbnum, (trunk ? "Trunk" : "Port"), &portvec, state, addr);
1695 static int mv88e6xxx_atu_show_db(struct seq_file *s, struct dsa_switch *ds,
1698 unsigned char bcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
1699 unsigned char addr[6];
1700 int ret, data, state;
1702 ret = __mv88e6xxx_write_addr(ds, bcast);
1707 ret = _mv88e6xxx_atu_cmd(ds, dbnum, GLOBAL_ATU_OP_GET_NEXT_DB);
1710 data = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1714 state = data & GLOBAL_ATU_DATA_STATE_MASK;
1715 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
1717 ret = __mv88e6xxx_read_addr(ds, addr);
1720 mv88e6xxx_atu_show_entry(s, dbnum, addr, data);
1721 } while (state != GLOBAL_ATU_DATA_STATE_UNUSED);
1726 static int mv88e6xxx_atu_show(struct seq_file *s, void *p)
1728 struct dsa_switch *ds = s->private;
1729 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1732 mv88e6xxx_atu_show_header(s);
1734 for (dbnum = 0; dbnum < 255; dbnum++) {
1735 mutex_lock(&ps->smi_mutex);
1736 mv88e6xxx_atu_show_db(s, ds, dbnum);
1737 mutex_unlock(&ps->smi_mutex);
1743 static int mv88e6xxx_atu_open(struct inode *inode, struct file *file)
1745 return single_open(file, mv88e6xxx_atu_show, inode->i_private);
1748 static const struct file_operations mv88e6xxx_atu_fops = {
1749 .open = mv88e6xxx_atu_open,
1751 .llseek = no_llseek,
1752 .release = single_release,
1753 .owner = THIS_MODULE,
1756 static void mv88e6xxx_stats_show_header(struct seq_file *s,
1757 struct mv88e6xxx_priv_state *ps)
1761 seq_puts(s, " Statistic ");
1762 for (port = 0 ; port < ps->num_ports; port++)
1763 seq_printf(s, "Port %2d ", port);
1767 static int mv88e6xxx_stats_show(struct seq_file *s, void *p)
1769 struct dsa_switch *ds = s->private;
1770 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1771 struct mv88e6xxx_hw_stat *stats = mv88e6xxx_hw_stats;
1772 int port, stat, max_stats;
1775 if (have_sw_in_discards(ds))
1776 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats);
1778 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
1780 mv88e6xxx_stats_show_header(s, ps);
1782 mutex_lock(&ps->smi_mutex);
1784 for (stat = 0; stat < max_stats; stat++) {
1785 seq_printf(s, "%19s: ", stats[stat].string);
1786 for (port = 0 ; port < ps->num_ports; port++) {
1787 _mv88e6xxx_stats_snapshot(ds, port);
1788 value = _mv88e6xxx_get_ethtool_stat(ds, stat, stats,
1790 seq_printf(s, "%8llu ", value);
1794 mutex_unlock(&ps->smi_mutex);
1799 static int mv88e6xxx_stats_open(struct inode *inode, struct file *file)
1801 return single_open(file, mv88e6xxx_stats_show, inode->i_private);
1804 static const struct file_operations mv88e6xxx_stats_fops = {
1805 .open = mv88e6xxx_stats_open,
1807 .llseek = no_llseek,
1808 .release = single_release,
1809 .owner = THIS_MODULE,
1812 static int mv88e6xxx_device_map_show(struct seq_file *s, void *p)
1814 struct dsa_switch *ds = s->private;
1815 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1818 seq_puts(s, "Target Port\n");
1820 mutex_lock(&ps->smi_mutex);
1821 for (target = 0; target < 32; target++) {
1822 ret = _mv88e6xxx_reg_write(
1823 ds, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
1824 target << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT);
1827 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
1828 GLOBAL2_DEVICE_MAPPING);
1829 seq_printf(s, " %2d %2d\n", target,
1830 ret & GLOBAL2_DEVICE_MAPPING_PORT_MASK);
1833 mutex_unlock(&ps->smi_mutex);
1838 static int mv88e6xxx_device_map_open(struct inode *inode, struct file *file)
1840 return single_open(file, mv88e6xxx_device_map_show, inode->i_private);
1843 static const struct file_operations mv88e6xxx_device_map_fops = {
1844 .open = mv88e6xxx_device_map_open,
1846 .llseek = no_llseek,
1847 .release = single_release,
1848 .owner = THIS_MODULE,
1851 static int mv88e6xxx_scratch_show(struct seq_file *s, void *p)
1853 struct dsa_switch *ds = s->private;
1854 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1857 seq_puts(s, "Register Value\n");
1859 mutex_lock(&ps->smi_mutex);
1860 for (reg = 0; reg < 0x80; reg++) {
1861 ret = _mv88e6xxx_reg_write(
1862 ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
1863 reg << GLOBAL2_SCRATCH_REGISTER_SHIFT);
1867 ret = _mv88e6xxx_scratch_wait(ds);
1871 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
1872 GLOBAL2_SCRATCH_MISC);
1873 seq_printf(s, " %2x %2x\n", reg,
1874 ret & GLOBAL2_SCRATCH_VALUE_MASK);
1877 mutex_unlock(&ps->smi_mutex);
1882 static int mv88e6xxx_scratch_open(struct inode *inode, struct file *file)
1884 return single_open(file, mv88e6xxx_scratch_show, inode->i_private);
1887 static const struct file_operations mv88e6xxx_scratch_fops = {
1888 .open = mv88e6xxx_scratch_open,
1890 .llseek = no_llseek,
1891 .release = single_release,
1892 .owner = THIS_MODULE,
1895 int mv88e6xxx_setup_common(struct dsa_switch *ds)
1897 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1900 mutex_init(&ps->smi_mutex);
1902 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
1904 ps->fid_mask = (1 << DSA_MAX_PORTS) - 1;
1906 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
1908 name = kasprintf(GFP_KERNEL, "dsa%d", ds->index);
1909 ps->dbgfs = debugfs_create_dir(name, NULL);
1912 debugfs_create_file("regs", S_IRUGO, ps->dbgfs, ds,
1913 &mv88e6xxx_regs_fops);
1915 debugfs_create_file("atu", S_IRUGO, ps->dbgfs, ds,
1916 &mv88e6xxx_atu_fops);
1918 debugfs_create_file("stats", S_IRUGO, ps->dbgfs, ds,
1919 &mv88e6xxx_stats_fops);
1921 debugfs_create_file("device_map", S_IRUGO, ps->dbgfs, ds,
1922 &mv88e6xxx_device_map_fops);
1924 debugfs_create_file("scratch", S_IRUGO, ps->dbgfs, ds,
1925 &mv88e6xxx_scratch_fops);
1929 int mv88e6xxx_setup_global(struct dsa_switch *ds)
1931 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1934 /* Set the default address aging time to 5 minutes, and
1935 * enable address learn messages to be sent to all message
1938 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
1939 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
1941 /* Configure the IP ToS mapping registers. */
1942 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
1943 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
1944 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
1945 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
1946 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
1947 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
1948 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
1949 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
1951 /* Configure the IEEE 802.1p priority mapping register. */
1952 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
1954 /* Send all frames with destination addresses matching
1955 * 01:80:c2:00:00:0x to the CPU port.
1957 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
1959 /* Ignore removed tag data on doubly tagged packets, disable
1960 * flow control messages, force flow control priority to the
1961 * highest, and send all special multicast frames to the CPU
1962 * port at the highest priority.
1964 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
1965 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
1966 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
1968 /* Program the DSA routing table. */
1969 for (i = 0; i < 32; i++) {
1972 if (ds->pd->rtable &&
1973 i != ds->index && i < ds->dst->pd->nr_chips)
1974 nexthop = ds->pd->rtable[i] & 0x1f;
1976 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
1977 GLOBAL2_DEVICE_MAPPING_UPDATE |
1978 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
1982 /* Clear all trunk masks. */
1983 for (i = 0; i < 8; i++)
1984 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
1985 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
1986 ((1 << ps->num_ports) - 1));
1988 /* Clear all trunk mappings. */
1989 for (i = 0; i < 16; i++)
1990 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
1991 GLOBAL2_TRUNK_MAPPING_UPDATE |
1992 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
1994 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1995 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1996 mv88e6xxx_6320_family(ds)) {
1997 /* Send all frames with destination addresses matching
1998 * 01:80:c2:00:00:2x to the CPU port.
2000 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2002 /* Initialise cross-chip port VLAN table to reset
2005 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2007 /* Clear the priority override table. */
2008 for (i = 0; i < 16; i++)
2009 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2013 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2014 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2015 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2016 mv88e6xxx_6320_family(ds)) {
2017 /* Disable ingress rate limiting by resetting all
2018 * ingress rate limit registers to their initial
2021 for (i = 0; i < ps->num_ports; i++)
2022 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2026 /* Clear the statistics counters for all ports */
2027 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2029 /* Wait for the flush to complete. */
2030 _mv88e6xxx_stats_wait(ds);
2035 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2037 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2038 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2039 unsigned long timeout;
2043 /* Set all ports to the disabled state. */
2044 for (i = 0; i < ps->num_ports; i++) {
2045 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2046 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2049 /* Wait for transmit queues to drain. */
2050 usleep_range(2000, 4000);
2052 /* Reset the switch. Keep the PPU active if requested. The PPU
2053 * needs to be active to support indirect phy register access
2054 * through global registers 0x18 and 0x19.
2057 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2059 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2061 /* Wait up to one second for reset to complete. */
2062 timeout = jiffies + 1 * HZ;
2063 while (time_before(jiffies, timeout)) {
2064 ret = REG_READ(REG_GLOBAL, 0x00);
2065 if ((ret & is_reset) == is_reset)
2067 usleep_range(1000, 2000);
2069 if (time_after(jiffies, timeout))
2075 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2077 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2080 mutex_lock(&ps->smi_mutex);
2081 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2084 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2086 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2087 mutex_unlock(&ps->smi_mutex);
2091 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2094 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2097 mutex_lock(&ps->smi_mutex);
2098 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2102 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2104 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2105 mutex_unlock(&ps->smi_mutex);
2109 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2111 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2113 if (port >= 0 && port < ps->num_ports)
2119 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2121 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2122 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2128 mutex_lock(&ps->smi_mutex);
2129 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2130 mutex_unlock(&ps->smi_mutex);
2135 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2137 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2138 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2144 mutex_lock(&ps->smi_mutex);
2145 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2146 mutex_unlock(&ps->smi_mutex);
2151 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2153 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2154 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2160 mutex_lock(&ps->smi_mutex);
2161 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2162 mutex_unlock(&ps->smi_mutex);
2167 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2170 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2171 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2177 mutex_lock(&ps->smi_mutex);
2178 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2179 mutex_unlock(&ps->smi_mutex);
2183 static int __init mv88e6xxx_init(void)
2185 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2186 register_switch_driver(&mv88e6131_switch_driver);
2188 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2189 register_switch_driver(&mv88e6123_61_65_switch_driver);
2191 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2192 register_switch_driver(&mv88e6352_switch_driver);
2194 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2195 register_switch_driver(&mv88e6171_switch_driver);
2199 module_init(mv88e6xxx_init);
2201 static void __exit mv88e6xxx_cleanup(void)
2203 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2204 unregister_switch_driver(&mv88e6171_switch_driver);
2206 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2207 unregister_switch_driver(&mv88e6352_switch_driver);
2209 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2210 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2212 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2213 unregister_switch_driver(&mv88e6131_switch_driver);
2216 module_exit(mv88e6xxx_cleanup);
2218 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2219 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2220 MODULE_LICENSE("GPL");