1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
59 #define ICH_FLASH_GFPREG 0x0000
60 #define ICH_FLASH_HSFSTS 0x0004
61 #define ICH_FLASH_HSFCTL 0x0006
62 #define ICH_FLASH_FADDR 0x0008
63 #define ICH_FLASH_FDATA0 0x0010
64 #define ICH_FLASH_PR0 0x0074
66 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
69 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
70 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
72 #define ICH_CYCLE_READ 0
73 #define ICH_CYCLE_WRITE 2
74 #define ICH_CYCLE_ERASE 3
76 #define FLASH_GFPREG_BASE_MASK 0x1FFF
77 #define FLASH_SECTOR_ADDR_SHIFT 12
79 #define ICH_FLASH_SEG_SIZE_256 256
80 #define ICH_FLASH_SEG_SIZE_4K 4096
81 #define ICH_FLASH_SEG_SIZE_8K 8192
82 #define ICH_FLASH_SEG_SIZE_64K 65536
85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
86 /* FW established a valid mode */
87 #define E1000_ICH_FWSM_FW_VALID 0x00008000
89 #define E1000_ICH_MNG_IAMT_MODE 0x2
91 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
92 (ID_LED_DEF1_OFF2 << 8) | \
93 (ID_LED_DEF1_ON2 << 4) | \
96 #define E1000_ICH_NVM_SIG_WORD 0x13
97 #define E1000_ICH_NVM_SIG_MASK 0xC000
98 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
99 #define E1000_ICH_NVM_SIG_VALUE 0x80
101 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
103 #define E1000_FEXTNVM_SW_CONFIG 1
104 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
106 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
108 #define E1000_ICH_RAR_ENTRIES 7
110 #define PHY_PAGE_SHIFT 5
111 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
112 ((reg) & MAX_PHY_REG_ADDRESS))
113 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
114 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
116 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
117 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
118 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
120 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
122 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
124 /* SMBus Address Phy Register */
125 #define HV_SMB_ADDR PHY_REG(768, 26)
126 #define HV_SMB_ADDR_PEC_EN 0x0200
127 #define HV_SMB_ADDR_VALID 0x0080
129 /* Strapping Option Register - RO */
130 #define E1000_STRAP 0x0000C
131 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
132 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
134 /* OEM Bits Phy Register */
135 #define HV_OEM_BITS PHY_REG(768, 25)
136 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
137 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
138 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
140 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
141 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
143 /* KMRN Mode Control */
144 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
145 #define HV_KMRN_MDIO_SLOW 0x0400
147 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
148 /* Offset 04h HSFSTS */
149 union ich8_hws_flash_status {
151 u16 flcdone :1; /* bit 0 Flash Cycle Done */
152 u16 flcerr :1; /* bit 1 Flash Cycle Error */
153 u16 dael :1; /* bit 2 Direct Access error Log */
154 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
155 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
156 u16 reserved1 :2; /* bit 13:6 Reserved */
157 u16 reserved2 :6; /* bit 13:6 Reserved */
158 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
159 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
164 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
165 /* Offset 06h FLCTL */
166 union ich8_hws_flash_ctrl {
167 struct ich8_hsflctl {
168 u16 flcgo :1; /* 0 Flash Cycle Go */
169 u16 flcycle :2; /* 2:1 Flash Cycle */
170 u16 reserved :5; /* 7:3 Reserved */
171 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
172 u16 flockdn :6; /* 15:10 Reserved */
177 /* ICH Flash Region Access Permissions */
178 union ich8_hws_flash_regacc {
180 u32 grra :8; /* 0:7 GbE region Read Access */
181 u32 grwa :8; /* 8:15 GbE region Write Access */
182 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
183 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
188 /* ICH Flash Protected Region */
189 union ich8_flash_protected_range {
191 u32 base:13; /* 0:12 Protected Range Base */
192 u32 reserved1:2; /* 13:14 Reserved */
193 u32 rpe:1; /* 15 Read Protection Enable */
194 u32 limit:13; /* 16:28 Protected Range Limit */
195 u32 reserved2:2; /* 29:30 Reserved */
196 u32 wpe:1; /* 31 Write Protection Enable */
201 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
202 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
203 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
204 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
205 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
206 u32 offset, u8 byte);
207 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
209 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
211 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
213 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
214 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
215 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
216 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
217 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
218 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
219 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
220 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
221 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
222 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
223 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
224 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
225 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
226 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
227 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
228 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
230 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
232 return readw(hw->flash_address + reg);
235 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
237 return readl(hw->flash_address + reg);
240 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
242 writew(val, hw->flash_address + reg);
245 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
247 writel(val, hw->flash_address + reg);
250 #define er16flash(reg) __er16flash(hw, (reg))
251 #define er32flash(reg) __er32flash(hw, (reg))
252 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
253 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
256 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
257 * @hw: pointer to the HW structure
259 * Initialize family-specific PHY parameters and function pointers.
261 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
263 struct e1000_phy_info *phy = &hw->phy;
268 phy->reset_delay_us = 100;
270 phy->ops.read_reg = e1000_read_phy_reg_hv;
271 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
272 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
273 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
274 phy->ops.write_reg = e1000_write_phy_reg_hv;
275 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
276 phy->ops.power_up = e1000_power_up_phy_copper;
277 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
278 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
280 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
282 * The MAC-PHY interconnect may still be in SMBus mode
283 * after Sx->S0. Toggle the LANPHYPC Value bit to force
284 * the interconnect to PCIe mode, but only if there is no
285 * firmware present otherwise firmware will have done it.
288 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
289 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
292 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
297 phy->id = e1000_phy_unknown;
298 ret_val = e1000e_get_phy_id(hw);
301 if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
303 * In case the PHY needs to be in mdio slow mode (eg. 82577),
304 * set slow mode and try to get the PHY id again.
306 ret_val = e1000_set_mdio_slow_mode_hv(hw);
309 ret_val = e1000e_get_phy_id(hw);
313 phy->type = e1000e_get_phy_type_from_id(phy->id);
316 case e1000_phy_82577:
317 phy->ops.check_polarity = e1000_check_polarity_82577;
318 phy->ops.force_speed_duplex =
319 e1000_phy_force_speed_duplex_82577;
320 phy->ops.get_cable_length = e1000_get_cable_length_82577;
321 phy->ops.get_info = e1000_get_phy_info_82577;
322 phy->ops.commit = e1000e_phy_sw_reset;
323 case e1000_phy_82578:
324 phy->ops.check_polarity = e1000_check_polarity_m88;
325 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
326 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
327 phy->ops.get_info = e1000e_get_phy_info_m88;
330 ret_val = -E1000_ERR_PHY;
339 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
340 * @hw: pointer to the HW structure
342 * Initialize family-specific PHY parameters and function pointers.
344 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
346 struct e1000_phy_info *phy = &hw->phy;
351 phy->reset_delay_us = 100;
353 phy->ops.power_up = e1000_power_up_phy_copper;
354 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
357 * We may need to do this twice - once for IGP and if that fails,
358 * we'll set BM func pointers and try again
360 ret_val = e1000e_determine_phy_address(hw);
362 phy->ops.write_reg = e1000e_write_phy_reg_bm;
363 phy->ops.read_reg = e1000e_read_phy_reg_bm;
364 ret_val = e1000e_determine_phy_address(hw);
366 e_dbg("Cannot determine PHY addr. Erroring out\n");
372 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
375 ret_val = e1000e_get_phy_id(hw);
382 case IGP03E1000_E_PHY_ID:
383 phy->type = e1000_phy_igp_3;
384 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
385 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
386 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
387 phy->ops.get_info = e1000e_get_phy_info_igp;
388 phy->ops.check_polarity = e1000_check_polarity_igp;
389 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
392 case IFE_PLUS_E_PHY_ID:
394 phy->type = e1000_phy_ife;
395 phy->autoneg_mask = E1000_ALL_NOT_GIG;
396 phy->ops.get_info = e1000_get_phy_info_ife;
397 phy->ops.check_polarity = e1000_check_polarity_ife;
398 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
400 case BME1000_E_PHY_ID:
401 phy->type = e1000_phy_bm;
402 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
403 phy->ops.read_reg = e1000e_read_phy_reg_bm;
404 phy->ops.write_reg = e1000e_write_phy_reg_bm;
405 phy->ops.commit = e1000e_phy_sw_reset;
406 phy->ops.get_info = e1000e_get_phy_info_m88;
407 phy->ops.check_polarity = e1000_check_polarity_m88;
408 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
411 return -E1000_ERR_PHY;
419 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
420 * @hw: pointer to the HW structure
422 * Initialize family-specific NVM parameters and function
425 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
427 struct e1000_nvm_info *nvm = &hw->nvm;
428 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
429 u32 gfpreg, sector_base_addr, sector_end_addr;
432 /* Can't read flash registers if the register set isn't mapped. */
433 if (!hw->flash_address) {
434 e_dbg("ERROR: Flash registers not mapped\n");
435 return -E1000_ERR_CONFIG;
438 nvm->type = e1000_nvm_flash_sw;
440 gfpreg = er32flash(ICH_FLASH_GFPREG);
443 * sector_X_addr is a "sector"-aligned address (4096 bytes)
444 * Add 1 to sector_end_addr since this sector is included in
447 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
448 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
450 /* flash_base_addr is byte-aligned */
451 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
454 * find total size of the NVM, then cut in half since the total
455 * size represents two separate NVM banks.
457 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
458 << FLASH_SECTOR_ADDR_SHIFT;
459 nvm->flash_bank_size /= 2;
460 /* Adjust to word count */
461 nvm->flash_bank_size /= sizeof(u16);
463 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
465 /* Clear shadow ram */
466 for (i = 0; i < nvm->word_size; i++) {
467 dev_spec->shadow_ram[i].modified = false;
468 dev_spec->shadow_ram[i].value = 0xFFFF;
475 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
476 * @hw: pointer to the HW structure
478 * Initialize family-specific MAC parameters and function
481 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
483 struct e1000_hw *hw = &adapter->hw;
484 struct e1000_mac_info *mac = &hw->mac;
486 /* Set media type function pointer */
487 hw->phy.media_type = e1000_media_type_copper;
489 /* Set mta register count */
490 mac->mta_reg_count = 32;
491 /* Set rar entry count */
492 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
493 if (mac->type == e1000_ich8lan)
494 mac->rar_entry_count--;
495 /* Set if manageability features are enabled. */
496 mac->arc_subsystem_valid = true;
497 /* Adaptive IFS supported */
498 mac->adaptive_ifs = true;
506 mac->ops.id_led_init = e1000e_id_led_init;
508 mac->ops.setup_led = e1000e_setup_led_generic;
510 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
511 /* turn on/off LED */
512 mac->ops.led_on = e1000_led_on_ich8lan;
513 mac->ops.led_off = e1000_led_off_ich8lan;
517 mac->ops.id_led_init = e1000_id_led_init_pchlan;
519 mac->ops.setup_led = e1000_setup_led_pchlan;
521 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
522 /* turn on/off LED */
523 mac->ops.led_on = e1000_led_on_pchlan;
524 mac->ops.led_off = e1000_led_off_pchlan;
530 /* Enable PCS Lock-loss workaround for ICH8 */
531 if (mac->type == e1000_ich8lan)
532 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
538 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
539 * @hw: pointer to the HW structure
541 * Checks to see of the link status of the hardware has changed. If a
542 * change in link status has been detected, then we read the PHY registers
543 * to get the current speed/duplex if link exists.
545 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
547 struct e1000_mac_info *mac = &hw->mac;
552 * We only want to go out to the PHY registers to see if Auto-Neg
553 * has completed and/or if our link status has changed. The
554 * get_link_status flag is set upon receiving a Link Status
555 * Change or Rx Sequence Error interrupt.
557 if (!mac->get_link_status) {
563 * First we want to see if the MII Status Register reports
564 * link. If so, then we want to get the current speed/duplex
567 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
571 if (hw->mac.type == e1000_pchlan) {
572 ret_val = e1000_k1_gig_workaround_hv(hw, link);
578 goto out; /* No link detected */
580 mac->get_link_status = false;
582 if (hw->phy.type == e1000_phy_82578) {
583 ret_val = e1000_link_stall_workaround_hv(hw);
589 * Check if there was DownShift, must be checked
590 * immediately after link-up
592 e1000e_check_downshift(hw);
595 * If we are forcing speed/duplex, then we simply return since
596 * we have already determined whether we have link or not.
599 ret_val = -E1000_ERR_CONFIG;
604 * Auto-Neg is enabled. Auto Speed Detection takes care
605 * of MAC speed/duplex configuration. So we only need to
606 * configure Collision Distance in the MAC.
608 e1000e_config_collision_dist(hw);
611 * Configure Flow Control now that Auto-Neg has completed.
612 * First, we need to restore the desired flow control
613 * settings because we may have had to re-autoneg with a
614 * different link partner.
616 ret_val = e1000e_config_fc_after_link_up(hw);
618 e_dbg("Error configuring flow control\n");
624 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
626 struct e1000_hw *hw = &adapter->hw;
629 rc = e1000_init_mac_params_ich8lan(adapter);
633 rc = e1000_init_nvm_params_ich8lan(hw);
637 if (hw->mac.type == e1000_pchlan)
638 rc = e1000_init_phy_params_pchlan(hw);
640 rc = e1000_init_phy_params_ich8lan(hw);
644 if (adapter->hw.phy.type == e1000_phy_ife) {
645 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
646 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
649 if ((adapter->hw.mac.type == e1000_ich8lan) &&
650 (adapter->hw.phy.type == e1000_phy_igp_3))
651 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
656 static DEFINE_MUTEX(nvm_mutex);
659 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
660 * @hw: pointer to the HW structure
662 * Acquires the mutex for performing NVM operations.
664 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
666 mutex_lock(&nvm_mutex);
672 * e1000_release_nvm_ich8lan - Release NVM mutex
673 * @hw: pointer to the HW structure
675 * Releases the mutex used while performing NVM operations.
677 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
679 mutex_unlock(&nvm_mutex);
684 static DEFINE_MUTEX(swflag_mutex);
687 * e1000_acquire_swflag_ich8lan - Acquire software control flag
688 * @hw: pointer to the HW structure
690 * Acquires the software control flag for performing PHY and select
693 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
695 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
698 mutex_lock(&swflag_mutex);
701 extcnf_ctrl = er32(EXTCNF_CTRL);
702 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
710 e_dbg("SW/FW/HW has locked the resource for too long.\n");
711 ret_val = -E1000_ERR_CONFIG;
715 timeout = SW_FLAG_TIMEOUT;
717 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
718 ew32(EXTCNF_CTRL, extcnf_ctrl);
721 extcnf_ctrl = er32(EXTCNF_CTRL);
722 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
730 e_dbg("Failed to acquire the semaphore.\n");
731 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
732 ew32(EXTCNF_CTRL, extcnf_ctrl);
733 ret_val = -E1000_ERR_CONFIG;
739 mutex_unlock(&swflag_mutex);
745 * e1000_release_swflag_ich8lan - Release software control flag
746 * @hw: pointer to the HW structure
748 * Releases the software control flag for performing PHY and select
751 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
755 extcnf_ctrl = er32(EXTCNF_CTRL);
756 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
757 ew32(EXTCNF_CTRL, extcnf_ctrl);
759 mutex_unlock(&swflag_mutex);
765 * e1000_check_mng_mode_ich8lan - Checks management mode
766 * @hw: pointer to the HW structure
768 * This checks if the adapter has manageability enabled.
769 * This is a function pointer entry point only called by read/write
770 * routines for the PHY and NVM parts.
772 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
778 return (fwsm & E1000_FWSM_MODE_MASK) ==
779 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
783 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
784 * @hw: pointer to the HW structure
786 * Checks if firmware is blocking the reset of the PHY.
787 * This is a function pointer entry point only called by
790 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
796 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
800 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
801 * @hw: pointer to the HW structure
803 * SW should configure the LCD from the NVM extended configuration region
804 * as a workaround for certain parts.
806 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
808 struct e1000_phy_info *phy = &hw->phy;
809 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
811 u16 word_addr, reg_data, reg_addr, phy_page = 0;
813 ret_val = hw->phy.ops.acquire(hw);
818 * Initialize the PHY from the NVM on ICH platforms. This
819 * is needed due to an issue where the NVM configuration is
820 * not properly autoloaded after power transitions.
821 * Therefore, after each PHY reset, we will load the
822 * configuration data out of the NVM manually.
824 if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
825 (hw->mac.type == e1000_pchlan)) {
826 struct e1000_adapter *adapter = hw->adapter;
828 /* Check if SW needs to configure the PHY */
829 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
830 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
831 (hw->mac.type == e1000_pchlan))
832 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
834 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
836 data = er32(FEXTNVM);
837 if (!(data & sw_cfg_mask))
840 /* Wait for basic configuration completes before proceeding */
841 e1000_lan_init_done_ich8lan(hw);
844 * Make sure HW does not configure LCD from PHY
845 * extended configuration before SW configuration
847 data = er32(EXTCNF_CTRL);
848 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
851 cnf_size = er32(EXTCNF_SIZE);
852 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
853 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
857 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
858 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
860 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
861 (hw->mac.type == e1000_pchlan)) {
863 * HW configures the SMBus address and LEDs when the
864 * OEM and LCD Write Enable bits are set in the NVM.
865 * When both NVM bits are cleared, SW will configure
869 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
870 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
871 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
872 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
878 ret_val = e1000_write_phy_reg_hv_locked(hw,
884 /* Configure LCD from extended configuration region. */
886 /* cnf_base_addr is in DWORD */
887 word_addr = (u16)(cnf_base_addr << 1);
889 for (i = 0; i < cnf_size; i++) {
890 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
895 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
900 /* Save off the PHY page for future writes. */
901 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
906 reg_addr &= PHY_REG_MASK;
907 reg_addr |= phy_page;
909 ret_val = phy->ops.write_reg_locked(hw,
918 hw->phy.ops.release(hw);
923 * e1000_k1_gig_workaround_hv - K1 Si workaround
924 * @hw: pointer to the HW structure
925 * @link: link up bool flag
927 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
928 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
929 * If link is down, the function will restore the default K1 setting located
932 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
936 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
938 if (hw->mac.type != e1000_pchlan)
941 /* Wrap the whole flow with the sw flag */
942 ret_val = hw->phy.ops.acquire(hw);
946 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
948 if (hw->phy.type == e1000_phy_82578) {
949 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
954 status_reg &= BM_CS_STATUS_LINK_UP |
955 BM_CS_STATUS_RESOLVED |
956 BM_CS_STATUS_SPEED_MASK;
958 if (status_reg == (BM_CS_STATUS_LINK_UP |
959 BM_CS_STATUS_RESOLVED |
960 BM_CS_STATUS_SPEED_1000))
964 if (hw->phy.type == e1000_phy_82577) {
965 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
970 status_reg &= HV_M_STATUS_LINK_UP |
971 HV_M_STATUS_AUTONEG_COMPLETE |
972 HV_M_STATUS_SPEED_MASK;
974 if (status_reg == (HV_M_STATUS_LINK_UP |
975 HV_M_STATUS_AUTONEG_COMPLETE |
976 HV_M_STATUS_SPEED_1000))
980 /* Link stall fix for link up */
981 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
987 /* Link stall fix for link down */
988 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
994 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
997 hw->phy.ops.release(hw);
1003 * e1000_configure_k1_ich8lan - Configure K1 power state
1004 * @hw: pointer to the HW structure
1005 * @enable: K1 state to configure
1007 * Configure the K1 power state based on the provided parameter.
1008 * Assumes semaphore already acquired.
1010 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1012 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1020 ret_val = e1000e_read_kmrn_reg_locked(hw,
1021 E1000_KMRNCTRLSTA_K1_CONFIG,
1027 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1029 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1031 ret_val = e1000e_write_kmrn_reg_locked(hw,
1032 E1000_KMRNCTRLSTA_K1_CONFIG,
1038 ctrl_ext = er32(CTRL_EXT);
1039 ctrl_reg = er32(CTRL);
1041 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1042 reg |= E1000_CTRL_FRCSPD;
1045 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1047 ew32(CTRL, ctrl_reg);
1048 ew32(CTRL_EXT, ctrl_ext);
1056 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1057 * @hw: pointer to the HW structure
1058 * @d0_state: boolean if entering d0 or d3 device state
1060 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1061 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1062 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1064 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1070 if (hw->mac.type != e1000_pchlan)
1073 ret_val = hw->phy.ops.acquire(hw);
1077 mac_reg = er32(EXTCNF_CTRL);
1078 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1081 mac_reg = er32(FEXTNVM);
1082 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1085 mac_reg = er32(PHY_CTRL);
1087 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1091 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1094 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1095 oem_reg |= HV_OEM_BITS_GBE_DIS;
1097 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1098 oem_reg |= HV_OEM_BITS_LPLU;
1100 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1101 oem_reg |= HV_OEM_BITS_GBE_DIS;
1103 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1104 oem_reg |= HV_OEM_BITS_LPLU;
1106 /* Restart auto-neg to activate the bits */
1107 if (!e1000_check_reset_block(hw))
1108 oem_reg |= HV_OEM_BITS_RESTART_AN;
1109 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1112 hw->phy.ops.release(hw);
1119 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1120 * @hw: pointer to the HW structure
1122 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1127 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1131 data |= HV_KMRN_MDIO_SLOW;
1133 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1139 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1140 * done after every PHY reset.
1142 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1147 if (hw->mac.type != e1000_pchlan)
1150 /* Set MDIO slow mode before any other MDIO access */
1151 if (hw->phy.type == e1000_phy_82577) {
1152 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1157 if (((hw->phy.type == e1000_phy_82577) &&
1158 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1159 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1160 /* Disable generation of early preamble */
1161 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1165 /* Preamble tuning for SSC */
1166 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1171 if (hw->phy.type == e1000_phy_82578) {
1173 * Return registers to default by doing a soft reset then
1174 * writing 0x3140 to the control register.
1176 if (hw->phy.revision < 2) {
1177 e1000e_phy_sw_reset(hw);
1178 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1183 ret_val = hw->phy.ops.acquire(hw);
1188 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1189 hw->phy.ops.release(hw);
1194 * Configure the K1 Si workaround during phy reset assuming there is
1195 * link so that it disables K1 if link is in 1Gbps.
1197 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1201 /* Workaround for link disconnects on a busy hub in half duplex */
1202 ret_val = hw->phy.ops.acquire(hw);
1205 ret_val = hw->phy.ops.read_reg_locked(hw,
1206 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1210 ret_val = hw->phy.ops.write_reg_locked(hw,
1211 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1214 hw->phy.ops.release(hw);
1220 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1221 * @hw: pointer to the HW structure
1223 * Check the appropriate indication the MAC has finished configuring the
1224 * PHY after a software reset.
1226 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1228 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1230 /* Wait for basic configuration completes before proceeding */
1232 data = er32(STATUS);
1233 data &= E1000_STATUS_LAN_INIT_DONE;
1235 } while ((!data) && --loop);
1238 * If basic configuration is incomplete before the above loop
1239 * count reaches 0, loading the configuration from NVM will
1240 * leave the PHY in a bad state possibly resulting in no link.
1243 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1245 /* Clear the Init Done bit for the next init event */
1246 data = er32(STATUS);
1247 data &= ~E1000_STATUS_LAN_INIT_DONE;
1252 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1253 * @hw: pointer to the HW structure
1256 * This is a function pointer entry point called by drivers
1257 * or other shared routines.
1259 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1264 ret_val = e1000e_phy_hw_reset_generic(hw);
1268 /* Allow time for h/w to get to a quiescent state after reset */
1271 /* Perform any necessary post-reset workarounds */
1272 if (hw->mac.type == e1000_pchlan) {
1273 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1278 /* Dummy read to clear the phy wakeup bit after lcd reset */
1279 if (hw->mac.type == e1000_pchlan)
1280 e1e_rphy(hw, BM_WUC, ®);
1282 /* Configure the LCD with the extended configuration region in NVM */
1283 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1287 /* Configure the LCD with the OEM bits in NVM */
1288 if (hw->mac.type == e1000_pchlan)
1289 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1296 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1297 * @hw: pointer to the HW structure
1298 * @active: true to enable LPLU, false to disable
1300 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1301 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1302 * the phy speed. This function will manually set the LPLU bit and restart
1303 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1304 * since it configures the same bit.
1306 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1311 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1316 oem_reg |= HV_OEM_BITS_LPLU;
1318 oem_reg &= ~HV_OEM_BITS_LPLU;
1320 oem_reg |= HV_OEM_BITS_RESTART_AN;
1321 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1328 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1329 * @hw: pointer to the HW structure
1330 * @active: true to enable LPLU, false to disable
1332 * Sets the LPLU D0 state according to the active flag. When
1333 * activating LPLU this function also disables smart speed
1334 * and vice versa. LPLU will not be activated unless the
1335 * device autonegotiation advertisement meets standards of
1336 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1337 * This is a function pointer entry point only called by
1338 * PHY setup routines.
1340 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1342 struct e1000_phy_info *phy = &hw->phy;
1347 if (phy->type == e1000_phy_ife)
1350 phy_ctrl = er32(PHY_CTRL);
1353 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1354 ew32(PHY_CTRL, phy_ctrl);
1356 if (phy->type != e1000_phy_igp_3)
1360 * Call gig speed drop workaround on LPLU before accessing
1363 if (hw->mac.type == e1000_ich8lan)
1364 e1000e_gig_downshift_workaround_ich8lan(hw);
1366 /* When LPLU is enabled, we should disable SmartSpeed */
1367 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1368 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1369 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1373 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1374 ew32(PHY_CTRL, phy_ctrl);
1376 if (phy->type != e1000_phy_igp_3)
1380 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1381 * during Dx states where the power conservation is most
1382 * important. During driver activity we should enable
1383 * SmartSpeed, so performance is maintained.
1385 if (phy->smart_speed == e1000_smart_speed_on) {
1386 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1391 data |= IGP01E1000_PSCFR_SMART_SPEED;
1392 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1396 } else if (phy->smart_speed == e1000_smart_speed_off) {
1397 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1402 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1403 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1414 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1415 * @hw: pointer to the HW structure
1416 * @active: true to enable LPLU, false to disable
1418 * Sets the LPLU D3 state according to the active flag. When
1419 * activating LPLU this function also disables smart speed
1420 * and vice versa. LPLU will not be activated unless the
1421 * device autonegotiation advertisement meets standards of
1422 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1423 * This is a function pointer entry point only called by
1424 * PHY setup routines.
1426 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1428 struct e1000_phy_info *phy = &hw->phy;
1433 phy_ctrl = er32(PHY_CTRL);
1436 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1437 ew32(PHY_CTRL, phy_ctrl);
1439 if (phy->type != e1000_phy_igp_3)
1443 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1444 * during Dx states where the power conservation is most
1445 * important. During driver activity we should enable
1446 * SmartSpeed, so performance is maintained.
1448 if (phy->smart_speed == e1000_smart_speed_on) {
1449 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1454 data |= IGP01E1000_PSCFR_SMART_SPEED;
1455 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1459 } else if (phy->smart_speed == e1000_smart_speed_off) {
1460 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1465 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1466 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1471 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1472 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1473 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1474 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1475 ew32(PHY_CTRL, phy_ctrl);
1477 if (phy->type != e1000_phy_igp_3)
1481 * Call gig speed drop workaround on LPLU before accessing
1484 if (hw->mac.type == e1000_ich8lan)
1485 e1000e_gig_downshift_workaround_ich8lan(hw);
1487 /* When LPLU is enabled, we should disable SmartSpeed */
1488 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1492 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1493 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1500 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1501 * @hw: pointer to the HW structure
1502 * @bank: pointer to the variable that returns the active bank
1504 * Reads signature byte from the NVM using the flash access registers.
1505 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1507 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1510 struct e1000_nvm_info *nvm = &hw->nvm;
1511 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1512 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1516 switch (hw->mac.type) {
1520 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1521 E1000_EECD_SEC1VAL_VALID_MASK) {
1522 if (eecd & E1000_EECD_SEC1VAL)
1529 e_dbg("Unable to determine valid NVM bank via EEC - "
1530 "reading flash signature\n");
1533 /* set bank to 0 in case flash read fails */
1537 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1541 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1542 E1000_ICH_NVM_SIG_VALUE) {
1548 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1553 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1554 E1000_ICH_NVM_SIG_VALUE) {
1559 e_dbg("ERROR: No valid NVM bank present\n");
1560 return -E1000_ERR_NVM;
1567 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1568 * @hw: pointer to the HW structure
1569 * @offset: The offset (in bytes) of the word(s) to read.
1570 * @words: Size of data to read in words
1571 * @data: Pointer to the word(s) to read at offset.
1573 * Reads a word(s) from the NVM using the flash access registers.
1575 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1578 struct e1000_nvm_info *nvm = &hw->nvm;
1579 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1585 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1587 e_dbg("nvm parameter(s) out of bounds\n");
1588 ret_val = -E1000_ERR_NVM;
1592 nvm->ops.acquire(hw);
1594 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1596 e_dbg("Could not detect valid bank, assuming bank 0\n");
1600 act_offset = (bank) ? nvm->flash_bank_size : 0;
1601 act_offset += offset;
1604 for (i = 0; i < words; i++) {
1605 if ((dev_spec->shadow_ram) &&
1606 (dev_spec->shadow_ram[offset+i].modified)) {
1607 data[i] = dev_spec->shadow_ram[offset+i].value;
1609 ret_val = e1000_read_flash_word_ich8lan(hw,
1618 nvm->ops.release(hw);
1622 e_dbg("NVM read error: %d\n", ret_val);
1628 * e1000_flash_cycle_init_ich8lan - Initialize flash
1629 * @hw: pointer to the HW structure
1631 * This function does initial flash setup so that a new read/write/erase cycle
1634 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1636 union ich8_hws_flash_status hsfsts;
1637 s32 ret_val = -E1000_ERR_NVM;
1640 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1642 /* Check if the flash descriptor is valid */
1643 if (hsfsts.hsf_status.fldesvalid == 0) {
1644 e_dbg("Flash descriptor invalid. "
1645 "SW Sequencing must be used.\n");
1646 return -E1000_ERR_NVM;
1649 /* Clear FCERR and DAEL in hw status by writing 1 */
1650 hsfsts.hsf_status.flcerr = 1;
1651 hsfsts.hsf_status.dael = 1;
1653 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1656 * Either we should have a hardware SPI cycle in progress
1657 * bit to check against, in order to start a new cycle or
1658 * FDONE bit should be changed in the hardware so that it
1659 * is 1 after hardware reset, which can then be used as an
1660 * indication whether a cycle is in progress or has been
1664 if (hsfsts.hsf_status.flcinprog == 0) {
1666 * There is no cycle running at present,
1667 * so we can start a cycle.
1668 * Begin by setting Flash Cycle Done.
1670 hsfsts.hsf_status.flcdone = 1;
1671 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1675 * Otherwise poll for sometime so the current
1676 * cycle has a chance to end before giving up.
1678 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1679 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1680 if (hsfsts.hsf_status.flcinprog == 0) {
1688 * Successful in waiting for previous cycle to timeout,
1689 * now set the Flash Cycle Done.
1691 hsfsts.hsf_status.flcdone = 1;
1692 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1694 e_dbg("Flash controller busy, cannot get access\n");
1702 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1703 * @hw: pointer to the HW structure
1704 * @timeout: maximum time to wait for completion
1706 * This function starts a flash cycle and waits for its completion.
1708 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1710 union ich8_hws_flash_ctrl hsflctl;
1711 union ich8_hws_flash_status hsfsts;
1712 s32 ret_val = -E1000_ERR_NVM;
1715 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1716 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1717 hsflctl.hsf_ctrl.flcgo = 1;
1718 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1720 /* wait till FDONE bit is set to 1 */
1722 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1723 if (hsfsts.hsf_status.flcdone == 1)
1726 } while (i++ < timeout);
1728 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1735 * e1000_read_flash_word_ich8lan - Read word from flash
1736 * @hw: pointer to the HW structure
1737 * @offset: offset to data location
1738 * @data: pointer to the location for storing the data
1740 * Reads the flash word at offset into data. Offset is converted
1741 * to bytes before read.
1743 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1746 /* Must convert offset into bytes. */
1749 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1753 * e1000_read_flash_byte_ich8lan - Read byte from flash
1754 * @hw: pointer to the HW structure
1755 * @offset: The offset of the byte to read.
1756 * @data: Pointer to a byte to store the value read.
1758 * Reads a single byte from the NVM using the flash access registers.
1760 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1766 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1776 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1777 * @hw: pointer to the HW structure
1778 * @offset: The offset (in bytes) of the byte or word to read.
1779 * @size: Size of data to read, 1=byte 2=word
1780 * @data: Pointer to the word to store the value read.
1782 * Reads a byte or word from the NVM using the flash access registers.
1784 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1787 union ich8_hws_flash_status hsfsts;
1788 union ich8_hws_flash_ctrl hsflctl;
1789 u32 flash_linear_addr;
1791 s32 ret_val = -E1000_ERR_NVM;
1794 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1795 return -E1000_ERR_NVM;
1797 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1798 hw->nvm.flash_base_addr;
1803 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1807 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1808 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1809 hsflctl.hsf_ctrl.fldbcount = size - 1;
1810 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1811 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1813 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1815 ret_val = e1000_flash_cycle_ich8lan(hw,
1816 ICH_FLASH_READ_COMMAND_TIMEOUT);
1819 * Check if FCERR is set to 1, if set to 1, clear it
1820 * and try the whole sequence a few more times, else
1821 * read in (shift in) the Flash Data0, the order is
1822 * least significant byte first msb to lsb
1825 flash_data = er32flash(ICH_FLASH_FDATA0);
1827 *data = (u8)(flash_data & 0x000000FF);
1828 } else if (size == 2) {
1829 *data = (u16)(flash_data & 0x0000FFFF);
1834 * If we've gotten here, then things are probably
1835 * completely hosed, but if the error condition is
1836 * detected, it won't hurt to give it another try...
1837 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1839 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1840 if (hsfsts.hsf_status.flcerr == 1) {
1841 /* Repeat for some time before giving up. */
1843 } else if (hsfsts.hsf_status.flcdone == 0) {
1844 e_dbg("Timeout error - flash cycle "
1845 "did not complete.\n");
1849 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1855 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1856 * @hw: pointer to the HW structure
1857 * @offset: The offset (in bytes) of the word(s) to write.
1858 * @words: Size of data to write in words
1859 * @data: Pointer to the word(s) to write at offset.
1861 * Writes a byte or word to the NVM using the flash access registers.
1863 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1866 struct e1000_nvm_info *nvm = &hw->nvm;
1867 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1870 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1872 e_dbg("nvm parameter(s) out of bounds\n");
1873 return -E1000_ERR_NVM;
1876 nvm->ops.acquire(hw);
1878 for (i = 0; i < words; i++) {
1879 dev_spec->shadow_ram[offset+i].modified = true;
1880 dev_spec->shadow_ram[offset+i].value = data[i];
1883 nvm->ops.release(hw);
1889 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1890 * @hw: pointer to the HW structure
1892 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1893 * which writes the checksum to the shadow ram. The changes in the shadow
1894 * ram are then committed to the EEPROM by processing each bank at a time
1895 * checking for the modified bit and writing only the pending changes.
1896 * After a successful commit, the shadow ram is cleared and is ready for
1899 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1901 struct e1000_nvm_info *nvm = &hw->nvm;
1902 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1903 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1907 ret_val = e1000e_update_nvm_checksum_generic(hw);
1911 if (nvm->type != e1000_nvm_flash_sw)
1914 nvm->ops.acquire(hw);
1917 * We're writing to the opposite bank so if we're on bank 1,
1918 * write to bank 0 etc. We also need to erase the segment that
1919 * is going to be written
1921 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1923 e_dbg("Could not detect valid bank, assuming bank 0\n");
1928 new_bank_offset = nvm->flash_bank_size;
1929 old_bank_offset = 0;
1930 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1932 nvm->ops.release(hw);
1936 old_bank_offset = nvm->flash_bank_size;
1937 new_bank_offset = 0;
1938 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1940 nvm->ops.release(hw);
1945 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1947 * Determine whether to write the value stored
1948 * in the other NVM bank or a modified value stored
1951 if (dev_spec->shadow_ram[i].modified) {
1952 data = dev_spec->shadow_ram[i].value;
1954 ret_val = e1000_read_flash_word_ich8lan(hw, i +
1962 * If the word is 0x13, then make sure the signature bits
1963 * (15:14) are 11b until the commit has completed.
1964 * This will allow us to write 10b which indicates the
1965 * signature is valid. We want to do this after the write
1966 * has completed so that we don't mark the segment valid
1967 * while the write is still in progress
1969 if (i == E1000_ICH_NVM_SIG_WORD)
1970 data |= E1000_ICH_NVM_SIG_MASK;
1972 /* Convert offset to bytes. */
1973 act_offset = (i + new_bank_offset) << 1;
1976 /* Write the bytes to the new bank. */
1977 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1984 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1992 * Don't bother writing the segment valid bits if sector
1993 * programming failed.
1996 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1997 e_dbg("Flash commit failed.\n");
1998 nvm->ops.release(hw);
2003 * Finally validate the new segment by setting bit 15:14
2004 * to 10b in word 0x13 , this can be done without an
2005 * erase as well since these bits are 11 to start with
2006 * and we need to change bit 14 to 0b
2008 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2009 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2011 nvm->ops.release(hw);
2015 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2019 nvm->ops.release(hw);
2024 * And invalidate the previously valid segment by setting
2025 * its signature word (0x13) high_byte to 0b. This can be
2026 * done without an erase because flash erase sets all bits
2027 * to 1's. We can write 1's to 0's without an erase
2029 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2030 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2032 nvm->ops.release(hw);
2036 /* Great! Everything worked, we can now clear the cached entries. */
2037 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2038 dev_spec->shadow_ram[i].modified = false;
2039 dev_spec->shadow_ram[i].value = 0xFFFF;
2042 nvm->ops.release(hw);
2045 * Reload the EEPROM, or else modifications will not appear
2046 * until after the next adapter reset.
2048 e1000e_reload_nvm(hw);
2053 e_dbg("NVM update error: %d\n", ret_val);
2059 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2060 * @hw: pointer to the HW structure
2062 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2063 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2064 * calculated, in which case we need to calculate the checksum and set bit 6.
2066 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2072 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2073 * needs to be fixed. This bit is an indication that the NVM
2074 * was prepared by OEM software and did not calculate the
2075 * checksum...a likely scenario.
2077 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2081 if ((data & 0x40) == 0) {
2083 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2086 ret_val = e1000e_update_nvm_checksum(hw);
2091 return e1000e_validate_nvm_checksum_generic(hw);
2095 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2096 * @hw: pointer to the HW structure
2098 * To prevent malicious write/erase of the NVM, set it to be read-only
2099 * so that the hardware ignores all write/erase cycles of the NVM via
2100 * the flash control registers. The shadow-ram copy of the NVM will
2101 * still be updated, however any updates to this copy will not stick
2102 * across driver reloads.
2104 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2106 struct e1000_nvm_info *nvm = &hw->nvm;
2107 union ich8_flash_protected_range pr0;
2108 union ich8_hws_flash_status hsfsts;
2111 nvm->ops.acquire(hw);
2113 gfpreg = er32flash(ICH_FLASH_GFPREG);
2115 /* Write-protect GbE Sector of NVM */
2116 pr0.regval = er32flash(ICH_FLASH_PR0);
2117 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2118 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2119 pr0.range.wpe = true;
2120 ew32flash(ICH_FLASH_PR0, pr0.regval);
2123 * Lock down a subset of GbE Flash Control Registers, e.g.
2124 * PR0 to prevent the write-protection from being lifted.
2125 * Once FLOCKDN is set, the registers protected by it cannot
2126 * be written until FLOCKDN is cleared by a hardware reset.
2128 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2129 hsfsts.hsf_status.flockdn = true;
2130 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2132 nvm->ops.release(hw);
2136 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2137 * @hw: pointer to the HW structure
2138 * @offset: The offset (in bytes) of the byte/word to read.
2139 * @size: Size of data to read, 1=byte 2=word
2140 * @data: The byte(s) to write to the NVM.
2142 * Writes one/two bytes to the NVM using the flash access registers.
2144 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2147 union ich8_hws_flash_status hsfsts;
2148 union ich8_hws_flash_ctrl hsflctl;
2149 u32 flash_linear_addr;
2154 if (size < 1 || size > 2 || data > size * 0xff ||
2155 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2156 return -E1000_ERR_NVM;
2158 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2159 hw->nvm.flash_base_addr;
2164 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2168 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2169 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2170 hsflctl.hsf_ctrl.fldbcount = size -1;
2171 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2172 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2174 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2177 flash_data = (u32)data & 0x00FF;
2179 flash_data = (u32)data;
2181 ew32flash(ICH_FLASH_FDATA0, flash_data);
2184 * check if FCERR is set to 1 , if set to 1, clear it
2185 * and try the whole sequence a few more times else done
2187 ret_val = e1000_flash_cycle_ich8lan(hw,
2188 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2193 * If we're here, then things are most likely
2194 * completely hosed, but if the error condition
2195 * is detected, it won't hurt to give it another
2196 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2198 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2199 if (hsfsts.hsf_status.flcerr == 1)
2200 /* Repeat for some time before giving up. */
2202 if (hsfsts.hsf_status.flcdone == 0) {
2203 e_dbg("Timeout error - flash cycle "
2204 "did not complete.");
2207 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2213 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2214 * @hw: pointer to the HW structure
2215 * @offset: The index of the byte to read.
2216 * @data: The byte to write to the NVM.
2218 * Writes a single byte to the NVM using the flash access registers.
2220 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2223 u16 word = (u16)data;
2225 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2229 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2230 * @hw: pointer to the HW structure
2231 * @offset: The offset of the byte to write.
2232 * @byte: The byte to write to the NVM.
2234 * Writes a single byte to the NVM using the flash access registers.
2235 * Goes through a retry algorithm before giving up.
2237 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2238 u32 offset, u8 byte)
2241 u16 program_retries;
2243 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2247 for (program_retries = 0; program_retries < 100; program_retries++) {
2248 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2250 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2254 if (program_retries == 100)
2255 return -E1000_ERR_NVM;
2261 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2262 * @hw: pointer to the HW structure
2263 * @bank: 0 for first bank, 1 for second bank, etc.
2265 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2266 * bank N is 4096 * N + flash_reg_addr.
2268 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2270 struct e1000_nvm_info *nvm = &hw->nvm;
2271 union ich8_hws_flash_status hsfsts;
2272 union ich8_hws_flash_ctrl hsflctl;
2273 u32 flash_linear_addr;
2274 /* bank size is in 16bit words - adjust to bytes */
2275 u32 flash_bank_size = nvm->flash_bank_size * 2;
2278 s32 j, iteration, sector_size;
2280 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2283 * Determine HW Sector size: Read BERASE bits of hw flash status
2285 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2286 * consecutive sectors. The start index for the nth Hw sector
2287 * can be calculated as = bank * 4096 + n * 256
2288 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2289 * The start index for the nth Hw sector can be calculated
2291 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2292 * (ich9 only, otherwise error condition)
2293 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2295 switch (hsfsts.hsf_status.berasesz) {
2297 /* Hw sector size 256 */
2298 sector_size = ICH_FLASH_SEG_SIZE_256;
2299 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2302 sector_size = ICH_FLASH_SEG_SIZE_4K;
2306 sector_size = ICH_FLASH_SEG_SIZE_8K;
2310 sector_size = ICH_FLASH_SEG_SIZE_64K;
2314 return -E1000_ERR_NVM;
2317 /* Start with the base address, then add the sector offset. */
2318 flash_linear_addr = hw->nvm.flash_base_addr;
2319 flash_linear_addr += (bank) ? flash_bank_size : 0;
2321 for (j = 0; j < iteration ; j++) {
2324 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2329 * Write a value 11 (block Erase) in Flash
2330 * Cycle field in hw flash control
2332 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2333 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2334 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2337 * Write the last 24 bits of an index within the
2338 * block into Flash Linear address field in Flash
2341 flash_linear_addr += (j * sector_size);
2342 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2344 ret_val = e1000_flash_cycle_ich8lan(hw,
2345 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2350 * Check if FCERR is set to 1. If 1,
2351 * clear it and try the whole sequence
2352 * a few more times else Done
2354 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2355 if (hsfsts.hsf_status.flcerr == 1)
2356 /* repeat for some time before giving up */
2358 else if (hsfsts.hsf_status.flcdone == 0)
2360 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2367 * e1000_valid_led_default_ich8lan - Set the default LED settings
2368 * @hw: pointer to the HW structure
2369 * @data: Pointer to the LED settings
2371 * Reads the LED default settings from the NVM to data. If the NVM LED
2372 * settings is all 0's or F's, set the LED default to a valid LED default
2375 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2379 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2381 e_dbg("NVM Read Error\n");
2385 if (*data == ID_LED_RESERVED_0000 ||
2386 *data == ID_LED_RESERVED_FFFF)
2387 *data = ID_LED_DEFAULT_ICH8LAN;
2393 * e1000_id_led_init_pchlan - store LED configurations
2394 * @hw: pointer to the HW structure
2396 * PCH does not control LEDs via the LEDCTL register, rather it uses
2397 * the PHY LED configuration register.
2399 * PCH also does not have an "always on" or "always off" mode which
2400 * complicates the ID feature. Instead of using the "on" mode to indicate
2401 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2402 * use "link_up" mode. The LEDs will still ID on request if there is no
2403 * link based on logic in e1000_led_[on|off]_pchlan().
2405 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2407 struct e1000_mac_info *mac = &hw->mac;
2409 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2410 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2411 u16 data, i, temp, shift;
2413 /* Get default ID LED modes */
2414 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2418 mac->ledctl_default = er32(LEDCTL);
2419 mac->ledctl_mode1 = mac->ledctl_default;
2420 mac->ledctl_mode2 = mac->ledctl_default;
2422 for (i = 0; i < 4; i++) {
2423 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2426 case ID_LED_ON1_DEF2:
2427 case ID_LED_ON1_ON2:
2428 case ID_LED_ON1_OFF2:
2429 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2430 mac->ledctl_mode1 |= (ledctl_on << shift);
2432 case ID_LED_OFF1_DEF2:
2433 case ID_LED_OFF1_ON2:
2434 case ID_LED_OFF1_OFF2:
2435 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2436 mac->ledctl_mode1 |= (ledctl_off << shift);
2443 case ID_LED_DEF1_ON2:
2444 case ID_LED_ON1_ON2:
2445 case ID_LED_OFF1_ON2:
2446 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2447 mac->ledctl_mode2 |= (ledctl_on << shift);
2449 case ID_LED_DEF1_OFF2:
2450 case ID_LED_ON1_OFF2:
2451 case ID_LED_OFF1_OFF2:
2452 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2453 mac->ledctl_mode2 |= (ledctl_off << shift);
2466 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2467 * @hw: pointer to the HW structure
2469 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2470 * register, so the the bus width is hard coded.
2472 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2474 struct e1000_bus_info *bus = &hw->bus;
2477 ret_val = e1000e_get_bus_info_pcie(hw);
2480 * ICH devices are "PCI Express"-ish. They have
2481 * a configuration space, but do not contain
2482 * PCI Express Capability registers, so bus width
2483 * must be hardcoded.
2485 if (bus->width == e1000_bus_width_unknown)
2486 bus->width = e1000_bus_width_pcie_x1;
2492 * e1000_reset_hw_ich8lan - Reset the hardware
2493 * @hw: pointer to the HW structure
2495 * Does a full reset of the hardware which includes a reset of the PHY and
2498 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2500 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2506 * Prevent the PCI-E bus from sticking if there is no TLP connection
2507 * on the last TLP read/write transaction when MAC is reset.
2509 ret_val = e1000e_disable_pcie_master(hw);
2511 e_dbg("PCI-E Master disable polling has failed.\n");
2514 e_dbg("Masking off all interrupts\n");
2515 ew32(IMC, 0xffffffff);
2518 * Disable the Transmit and Receive units. Then delay to allow
2519 * any pending transactions to complete before we hit the MAC
2520 * with the global reset.
2523 ew32(TCTL, E1000_TCTL_PSP);
2528 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2529 if (hw->mac.type == e1000_ich8lan) {
2530 /* Set Tx and Rx buffer allocation to 8k apiece. */
2531 ew32(PBA, E1000_PBA_8K);
2532 /* Set Packet Buffer Size to 16k. */
2533 ew32(PBS, E1000_PBS_16K);
2536 if (hw->mac.type == e1000_pchlan) {
2537 /* Save the NVM K1 bit setting*/
2538 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®);
2542 if (reg & E1000_NVM_K1_ENABLE)
2543 dev_spec->nvm_k1_enabled = true;
2545 dev_spec->nvm_k1_enabled = false;
2550 if (!e1000_check_reset_block(hw)) {
2551 /* Clear PHY Reset Asserted bit */
2552 if (hw->mac.type >= e1000_pchlan) {
2553 u32 status = er32(STATUS);
2554 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2558 * PHY HW reset requires MAC CORE reset at the same
2559 * time to make sure the interface between MAC and the
2560 * external PHY is reset.
2562 ctrl |= E1000_CTRL_PHY_RST;
2564 ret_val = e1000_acquire_swflag_ich8lan(hw);
2565 e_dbg("Issuing a global reset to ich8lan\n");
2566 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2570 e1000_release_swflag_ich8lan(hw);
2572 /* Perform any necessary post-reset workarounds */
2573 if (hw->mac.type == e1000_pchlan)
2574 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2576 if (ctrl & E1000_CTRL_PHY_RST)
2577 ret_val = hw->phy.ops.get_cfg_done(hw);
2579 if (hw->mac.type >= e1000_ich10lan) {
2580 e1000_lan_init_done_ich8lan(hw);
2582 ret_val = e1000e_get_auto_rd_done(hw);
2585 * When auto config read does not complete, do not
2586 * return with an error. This can happen in situations
2587 * where there is no eeprom and prevents getting link.
2589 e_dbg("Auto Read Done did not complete\n");
2592 /* Dummy read to clear the phy wakeup bit after lcd reset */
2593 if (hw->mac.type == e1000_pchlan)
2594 e1e_rphy(hw, BM_WUC, ®);
2596 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2600 if (hw->mac.type == e1000_pchlan) {
2601 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2606 * For PCH, this write will make sure that any noise
2607 * will be detected as a CRC error and be dropped rather than show up
2608 * as a bad packet to the DMA engine.
2610 if (hw->mac.type == e1000_pchlan)
2611 ew32(CRC_OFFSET, 0x65656565);
2613 ew32(IMC, 0xffffffff);
2616 kab = er32(KABGTXD);
2617 kab |= E1000_KABGTXD_BGSQLBIAS;
2625 * e1000_init_hw_ich8lan - Initialize the hardware
2626 * @hw: pointer to the HW structure
2628 * Prepares the hardware for transmit and receive by doing the following:
2629 * - initialize hardware bits
2630 * - initialize LED identification
2631 * - setup receive address registers
2632 * - setup flow control
2633 * - setup transmit descriptors
2634 * - clear statistics
2636 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2638 struct e1000_mac_info *mac = &hw->mac;
2639 u32 ctrl_ext, txdctl, snoop;
2643 e1000_initialize_hw_bits_ich8lan(hw);
2645 /* Initialize identification LED */
2646 ret_val = mac->ops.id_led_init(hw);
2648 e_dbg("Error initializing identification LED\n");
2649 /* This is not fatal and we should not stop init due to this */
2651 /* Setup the receive address. */
2652 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2654 /* Zero out the Multicast HASH table */
2655 e_dbg("Zeroing the MTA\n");
2656 for (i = 0; i < mac->mta_reg_count; i++)
2657 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2660 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2661 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2662 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2664 if (hw->phy.type == e1000_phy_82578) {
2665 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2666 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2671 /* Setup link and flow control */
2672 ret_val = e1000_setup_link_ich8lan(hw);
2674 /* Set the transmit descriptor write-back policy for both queues */
2675 txdctl = er32(TXDCTL(0));
2676 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2677 E1000_TXDCTL_FULL_TX_DESC_WB;
2678 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2679 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2680 ew32(TXDCTL(0), txdctl);
2681 txdctl = er32(TXDCTL(1));
2682 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2683 E1000_TXDCTL_FULL_TX_DESC_WB;
2684 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2685 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2686 ew32(TXDCTL(1), txdctl);
2689 * ICH8 has opposite polarity of no_snoop bits.
2690 * By default, we should use snoop behavior.
2692 if (mac->type == e1000_ich8lan)
2693 snoop = PCIE_ICH8_SNOOP_ALL;
2695 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2696 e1000e_set_pcie_no_snoop(hw, snoop);
2698 ctrl_ext = er32(CTRL_EXT);
2699 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2700 ew32(CTRL_EXT, ctrl_ext);
2703 * Clear all of the statistics registers (clear on read). It is
2704 * important that we do this after we have tried to establish link
2705 * because the symbol error count will increment wildly if there
2708 e1000_clear_hw_cntrs_ich8lan(hw);
2713 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2714 * @hw: pointer to the HW structure
2716 * Sets/Clears required hardware bits necessary for correctly setting up the
2717 * hardware for transmit and receive.
2719 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2723 /* Extended Device Control */
2724 reg = er32(CTRL_EXT);
2726 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2727 if (hw->mac.type >= e1000_pchlan)
2728 reg |= E1000_CTRL_EXT_PHYPDEN;
2729 ew32(CTRL_EXT, reg);
2731 /* Transmit Descriptor Control 0 */
2732 reg = er32(TXDCTL(0));
2734 ew32(TXDCTL(0), reg);
2736 /* Transmit Descriptor Control 1 */
2737 reg = er32(TXDCTL(1));
2739 ew32(TXDCTL(1), reg);
2741 /* Transmit Arbitration Control 0 */
2742 reg = er32(TARC(0));
2743 if (hw->mac.type == e1000_ich8lan)
2744 reg |= (1 << 28) | (1 << 29);
2745 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2748 /* Transmit Arbitration Control 1 */
2749 reg = er32(TARC(1));
2750 if (er32(TCTL) & E1000_TCTL_MULR)
2754 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2758 if (hw->mac.type == e1000_ich8lan) {
2765 * work-around descriptor data corruption issue during nfs v2 udp
2766 * traffic, just disable the nfs filtering capability
2769 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
2776 * e1000_setup_link_ich8lan - Setup flow control and link settings
2777 * @hw: pointer to the HW structure
2779 * Determines which flow control settings to use, then configures flow
2780 * control. Calls the appropriate media-specific link configuration
2781 * function. Assuming the adapter has a valid link partner, a valid link
2782 * should be established. Assumes the hardware has previously been reset
2783 * and the transmitter and receiver are not enabled.
2785 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2789 if (e1000_check_reset_block(hw))
2793 * ICH parts do not have a word in the NVM to determine
2794 * the default flow control setting, so we explicitly
2797 if (hw->fc.requested_mode == e1000_fc_default) {
2798 /* Workaround h/w hang when Tx flow control enabled */
2799 if (hw->mac.type == e1000_pchlan)
2800 hw->fc.requested_mode = e1000_fc_rx_pause;
2802 hw->fc.requested_mode = e1000_fc_full;
2806 * Save off the requested flow control mode for use later. Depending
2807 * on the link partner's capabilities, we may or may not use this mode.
2809 hw->fc.current_mode = hw->fc.requested_mode;
2811 e_dbg("After fix-ups FlowControl is now = %x\n",
2812 hw->fc.current_mode);
2814 /* Continue to configure the copper link. */
2815 ret_val = e1000_setup_copper_link_ich8lan(hw);
2819 ew32(FCTTV, hw->fc.pause_time);
2820 if ((hw->phy.type == e1000_phy_82578) ||
2821 (hw->phy.type == e1000_phy_82577)) {
2822 ret_val = hw->phy.ops.write_reg(hw,
2823 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2829 return e1000e_set_fc_watermarks(hw);
2833 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2834 * @hw: pointer to the HW structure
2836 * Configures the kumeran interface to the PHY to wait the appropriate time
2837 * when polling the PHY, then call the generic setup_copper_link to finish
2838 * configuring the copper link.
2840 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2847 ctrl |= E1000_CTRL_SLU;
2848 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2852 * Set the mac to wait the maximum time between each iteration
2853 * and increase the max iterations when polling the phy;
2854 * this fixes erroneous timeouts at 10Mbps.
2856 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
2859 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2864 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2869 switch (hw->phy.type) {
2870 case e1000_phy_igp_3:
2871 ret_val = e1000e_copper_link_setup_igp(hw);
2876 case e1000_phy_82578:
2877 ret_val = e1000e_copper_link_setup_m88(hw);
2881 case e1000_phy_82577:
2882 ret_val = e1000_copper_link_setup_82577(hw);
2887 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2892 reg_data &= ~IFE_PMC_AUTO_MDIX;
2894 switch (hw->phy.mdix) {
2896 reg_data &= ~IFE_PMC_FORCE_MDIX;
2899 reg_data |= IFE_PMC_FORCE_MDIX;
2903 reg_data |= IFE_PMC_AUTO_MDIX;
2906 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2914 return e1000e_setup_copper_link(hw);
2918 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2919 * @hw: pointer to the HW structure
2920 * @speed: pointer to store current link speed
2921 * @duplex: pointer to store the current link duplex
2923 * Calls the generic get_speed_and_duplex to retrieve the current link
2924 * information and then calls the Kumeran lock loss workaround for links at
2927 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2932 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2936 if ((hw->mac.type == e1000_ich8lan) &&
2937 (hw->phy.type == e1000_phy_igp_3) &&
2938 (*speed == SPEED_1000)) {
2939 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2946 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2947 * @hw: pointer to the HW structure
2949 * Work-around for 82566 Kumeran PCS lock loss:
2950 * On link status change (i.e. PCI reset, speed change) and link is up and
2952 * 0) if workaround is optionally disabled do nothing
2953 * 1) wait 1ms for Kumeran link to come up
2954 * 2) check Kumeran Diagnostic register PCS lock loss bit
2955 * 3) if not set the link is locked (all is good), otherwise...
2957 * 5) repeat up to 10 times
2958 * Note: this is only called for IGP3 copper when speed is 1gb.
2960 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2962 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2968 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2972 * Make sure link is up before proceeding. If not just return.
2973 * Attempting this while link is negotiating fouled up link
2976 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2980 for (i = 0; i < 10; i++) {
2981 /* read once to clear */
2982 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2985 /* and again to get new status */
2986 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2990 /* check for PCS lock */
2991 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2994 /* Issue PHY reset */
2995 e1000_phy_hw_reset(hw);
2998 /* Disable GigE link negotiation */
2999 phy_ctrl = er32(PHY_CTRL);
3000 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3001 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3002 ew32(PHY_CTRL, phy_ctrl);
3005 * Call gig speed drop workaround on Gig disable before accessing
3008 e1000e_gig_downshift_workaround_ich8lan(hw);
3010 /* unable to acquire PCS lock */
3011 return -E1000_ERR_PHY;
3015 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3016 * @hw: pointer to the HW structure
3017 * @state: boolean value used to set the current Kumeran workaround state
3019 * If ICH8, set the current Kumeran workaround state (enabled - true
3020 * /disabled - false).
3022 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3025 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3027 if (hw->mac.type != e1000_ich8lan) {
3028 e_dbg("Workaround applies to ICH8 only.\n");
3032 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3036 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3037 * @hw: pointer to the HW structure
3039 * Workaround for 82566 power-down on D3 entry:
3040 * 1) disable gigabit link
3041 * 2) write VR power-down enable
3043 * Continue if successful, else issue LCD reset and repeat
3045 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3051 if (hw->phy.type != e1000_phy_igp_3)
3054 /* Try the workaround twice (if needed) */
3057 reg = er32(PHY_CTRL);
3058 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3059 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3060 ew32(PHY_CTRL, reg);
3063 * Call gig speed drop workaround on Gig disable before
3064 * accessing any PHY registers
3066 if (hw->mac.type == e1000_ich8lan)
3067 e1000e_gig_downshift_workaround_ich8lan(hw);
3069 /* Write VR power-down enable */
3070 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3071 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3072 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3074 /* Read it back and test */
3075 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3076 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3077 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3080 /* Issue PHY reset and repeat at most one more time */
3082 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3088 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3089 * @hw: pointer to the HW structure
3091 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3092 * LPLU, Gig disable, MDIC PHY reset):
3093 * 1) Set Kumeran Near-end loopback
3094 * 2) Clear Kumeran Near-end loopback
3095 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3097 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3102 if ((hw->mac.type != e1000_ich8lan) ||
3103 (hw->phy.type != e1000_phy_igp_3))
3106 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3110 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3111 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3115 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3116 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3121 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3122 * @hw: pointer to the HW structure
3124 * During S0 to Sx transition, it is possible the link remains at gig
3125 * instead of negotiating to a lower speed. Before going to Sx, set
3126 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3129 * Should only be called for applicable parts.
3131 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3135 switch (hw->mac.type) {
3138 case e1000_ich10lan:
3140 phy_ctrl = er32(PHY_CTRL);
3141 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3142 E1000_PHY_CTRL_GBE_DISABLE;
3143 ew32(PHY_CTRL, phy_ctrl);
3145 if (hw->mac.type == e1000_pchlan)
3146 e1000_phy_hw_reset_ich8lan(hw);
3155 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3156 * @hw: pointer to the HW structure
3158 * Return the LED back to the default configuration.
3160 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3162 if (hw->phy.type == e1000_phy_ife)
3163 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3165 ew32(LEDCTL, hw->mac.ledctl_default);
3170 * e1000_led_on_ich8lan - Turn LEDs on
3171 * @hw: pointer to the HW structure
3175 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3177 if (hw->phy.type == e1000_phy_ife)
3178 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3179 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3181 ew32(LEDCTL, hw->mac.ledctl_mode2);
3186 * e1000_led_off_ich8lan - Turn LEDs off
3187 * @hw: pointer to the HW structure
3189 * Turn off the LEDs.
3191 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3193 if (hw->phy.type == e1000_phy_ife)
3194 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3195 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3197 ew32(LEDCTL, hw->mac.ledctl_mode1);
3202 * e1000_setup_led_pchlan - Configures SW controllable LED
3203 * @hw: pointer to the HW structure
3205 * This prepares the SW controllable LED for use.
3207 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3209 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3210 (u16)hw->mac.ledctl_mode1);
3214 * e1000_cleanup_led_pchlan - Restore the default LED operation
3215 * @hw: pointer to the HW structure
3217 * Return the LED back to the default configuration.
3219 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3221 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3222 (u16)hw->mac.ledctl_default);
3226 * e1000_led_on_pchlan - Turn LEDs on
3227 * @hw: pointer to the HW structure
3231 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3233 u16 data = (u16)hw->mac.ledctl_mode2;
3237 * If no link, then turn LED on by setting the invert bit
3238 * for each LED that's mode is "link_up" in ledctl_mode2.
3240 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3241 for (i = 0; i < 3; i++) {
3242 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3243 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3244 E1000_LEDCTL_MODE_LINK_UP)
3246 if (led & E1000_PHY_LED0_IVRT)
3247 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3249 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3253 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3257 * e1000_led_off_pchlan - Turn LEDs off
3258 * @hw: pointer to the HW structure
3260 * Turn off the LEDs.
3262 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3264 u16 data = (u16)hw->mac.ledctl_mode1;
3268 * If no link, then turn LED off by clearing the invert bit
3269 * for each LED that's mode is "link_up" in ledctl_mode1.
3271 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3272 for (i = 0; i < 3; i++) {
3273 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3274 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3275 E1000_LEDCTL_MODE_LINK_UP)
3277 if (led & E1000_PHY_LED0_IVRT)
3278 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3280 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3284 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3288 * e1000_get_cfg_done_ich8lan - Read config done bit
3289 * @hw: pointer to the HW structure
3291 * Read the management control register for the config done bit for
3292 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3293 * to read the config done bit, so an error is *ONLY* logged and returns
3294 * 0. If we were to return with error, EEPROM-less silicon
3295 * would not be able to be reset or change link.
3297 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3301 if (hw->mac.type >= e1000_pchlan) {
3302 u32 status = er32(STATUS);
3304 if (status & E1000_STATUS_PHYRA)
3305 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3307 e_dbg("PHY Reset Asserted not set - needs delay\n");
3310 e1000e_get_cfg_done(hw);
3312 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3313 if ((hw->mac.type != e1000_ich10lan) &&
3314 (hw->mac.type != e1000_pchlan)) {
3315 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3316 (hw->phy.type == e1000_phy_igp_3)) {
3317 e1000e_phy_init_script_igp3(hw);
3320 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3321 /* Maybe we should do a basic PHY config */
3322 e_dbg("EEPROM not present\n");
3323 return -E1000_ERR_CONFIG;
3331 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3332 * @hw: pointer to the HW structure
3334 * In the case of a PHY power down to save power, or to turn off link during a
3335 * driver unload, or wake on lan is not enabled, remove the link.
3337 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3339 /* If the management interface is not enabled, then power down */
3340 if (!(hw->mac.ops.check_mng_mode(hw) ||
3341 hw->phy.ops.check_reset_block(hw)))
3342 e1000_power_down_phy_copper(hw);
3348 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3349 * @hw: pointer to the HW structure
3351 * Clears hardware counters specific to the silicon family and calls
3352 * clear_hw_cntrs_generic to clear all general purpose counters.
3354 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3358 e1000e_clear_hw_cntrs_base(hw);
3374 /* Clear PHY statistics registers */
3375 if ((hw->phy.type == e1000_phy_82578) ||
3376 (hw->phy.type == e1000_phy_82577)) {
3377 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3378 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3379 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3380 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3381 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3382 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3383 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3384 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3385 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3386 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3387 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3388 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3389 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3390 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3394 static struct e1000_mac_operations ich8_mac_ops = {
3395 .id_led_init = e1000e_id_led_init,
3396 .check_mng_mode = e1000_check_mng_mode_ich8lan,
3397 .check_for_link = e1000_check_for_copper_link_ich8lan,
3398 /* cleanup_led dependent on mac type */
3399 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3400 .get_bus_info = e1000_get_bus_info_ich8lan,
3401 .set_lan_id = e1000_set_lan_id_single_port,
3402 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3403 /* led_on dependent on mac type */
3404 /* led_off dependent on mac type */
3405 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3406 .reset_hw = e1000_reset_hw_ich8lan,
3407 .init_hw = e1000_init_hw_ich8lan,
3408 .setup_link = e1000_setup_link_ich8lan,
3409 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3410 /* id_led_init dependent on mac type */
3413 static struct e1000_phy_operations ich8_phy_ops = {
3414 .acquire = e1000_acquire_swflag_ich8lan,
3415 .check_reset_block = e1000_check_reset_block_ich8lan,
3417 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3418 .get_cable_length = e1000e_get_cable_length_igp_2,
3419 .read_reg = e1000e_read_phy_reg_igp,
3420 .release = e1000_release_swflag_ich8lan,
3421 .reset = e1000_phy_hw_reset_ich8lan,
3422 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3423 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3424 .write_reg = e1000e_write_phy_reg_igp,
3427 static struct e1000_nvm_operations ich8_nvm_ops = {
3428 .acquire = e1000_acquire_nvm_ich8lan,
3429 .read = e1000_read_nvm_ich8lan,
3430 .release = e1000_release_nvm_ich8lan,
3431 .update = e1000_update_nvm_checksum_ich8lan,
3432 .valid_led_default = e1000_valid_led_default_ich8lan,
3433 .validate = e1000_validate_nvm_checksum_ich8lan,
3434 .write = e1000_write_nvm_ich8lan,
3437 struct e1000_info e1000_ich8_info = {
3438 .mac = e1000_ich8lan,
3439 .flags = FLAG_HAS_WOL
3441 | FLAG_RX_CSUM_ENABLED
3442 | FLAG_HAS_CTRLEXT_ON_LOAD
3447 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3448 .get_variants = e1000_get_variants_ich8lan,
3449 .mac_ops = &ich8_mac_ops,
3450 .phy_ops = &ich8_phy_ops,
3451 .nvm_ops = &ich8_nvm_ops,
3454 struct e1000_info e1000_ich9_info = {
3455 .mac = e1000_ich9lan,
3456 .flags = FLAG_HAS_JUMBO_FRAMES
3459 | FLAG_RX_CSUM_ENABLED
3460 | FLAG_HAS_CTRLEXT_ON_LOAD
3466 .max_hw_frame_size = DEFAULT_JUMBO,
3467 .get_variants = e1000_get_variants_ich8lan,
3468 .mac_ops = &ich8_mac_ops,
3469 .phy_ops = &ich8_phy_ops,
3470 .nvm_ops = &ich8_nvm_ops,
3473 struct e1000_info e1000_ich10_info = {
3474 .mac = e1000_ich10lan,
3475 .flags = FLAG_HAS_JUMBO_FRAMES
3478 | FLAG_RX_CSUM_ENABLED
3479 | FLAG_HAS_CTRLEXT_ON_LOAD
3485 .max_hw_frame_size = DEFAULT_JUMBO,
3486 .get_variants = e1000_get_variants_ich8lan,
3487 .mac_ops = &ich8_mac_ops,
3488 .phy_ops = &ich8_phy_ops,
3489 .nvm_ops = &ich8_nvm_ops,
3492 struct e1000_info e1000_pch_info = {
3493 .mac = e1000_pchlan,
3494 .flags = FLAG_IS_ICH
3496 | FLAG_RX_CSUM_ENABLED
3497 | FLAG_HAS_CTRLEXT_ON_LOAD
3500 | FLAG_HAS_JUMBO_FRAMES
3501 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3504 .max_hw_frame_size = 4096,
3505 .get_variants = e1000_get_variants_ich8lan,
3506 .mac_ops = &ich8_mac_ops,
3507 .phy_ops = &ich8_phy_ops,
3508 .nvm_ops = &ich8_nvm_ops,