1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
59 #define ICH_FLASH_GFPREG 0x0000
60 #define ICH_FLASH_HSFSTS 0x0004
61 #define ICH_FLASH_HSFCTL 0x0006
62 #define ICH_FLASH_FADDR 0x0008
63 #define ICH_FLASH_FDATA0 0x0010
64 #define ICH_FLASH_PR0 0x0074
66 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
69 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
70 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
72 #define ICH_CYCLE_READ 0
73 #define ICH_CYCLE_WRITE 2
74 #define ICH_CYCLE_ERASE 3
76 #define FLASH_GFPREG_BASE_MASK 0x1FFF
77 #define FLASH_SECTOR_ADDR_SHIFT 12
79 #define ICH_FLASH_SEG_SIZE_256 256
80 #define ICH_FLASH_SEG_SIZE_4K 4096
81 #define ICH_FLASH_SEG_SIZE_8K 8192
82 #define ICH_FLASH_SEG_SIZE_64K 65536
85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
87 #define E1000_ICH_MNG_IAMT_MODE 0x2
89 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
90 (ID_LED_DEF1_OFF2 << 8) | \
91 (ID_LED_DEF1_ON2 << 4) | \
94 #define E1000_ICH_NVM_SIG_WORD 0x13
95 #define E1000_ICH_NVM_SIG_MASK 0xC000
96 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
97 #define E1000_ICH_NVM_SIG_VALUE 0x80
99 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
101 #define E1000_FEXTNVM_SW_CONFIG 1
102 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
104 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
106 #define E1000_ICH_RAR_ENTRIES 7
108 #define PHY_PAGE_SHIFT 5
109 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
110 ((reg) & MAX_PHY_REG_ADDRESS))
111 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
112 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
114 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
115 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
116 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
118 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
120 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
122 /* SMBus Address Phy Register */
123 #define HV_SMB_ADDR PHY_REG(768, 26)
124 #define HV_SMB_ADDR_PEC_EN 0x0200
125 #define HV_SMB_ADDR_VALID 0x0080
127 /* Strapping Option Register - RO */
128 #define E1000_STRAP 0x0000C
129 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
130 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
132 /* OEM Bits Phy Register */
133 #define HV_OEM_BITS PHY_REG(768, 25)
134 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
135 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
136 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
138 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
139 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
141 /* KMRN Mode Control */
142 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
143 #define HV_KMRN_MDIO_SLOW 0x0400
145 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
146 /* Offset 04h HSFSTS */
147 union ich8_hws_flash_status {
149 u16 flcdone :1; /* bit 0 Flash Cycle Done */
150 u16 flcerr :1; /* bit 1 Flash Cycle Error */
151 u16 dael :1; /* bit 2 Direct Access error Log */
152 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
153 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
154 u16 reserved1 :2; /* bit 13:6 Reserved */
155 u16 reserved2 :6; /* bit 13:6 Reserved */
156 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
157 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
162 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
163 /* Offset 06h FLCTL */
164 union ich8_hws_flash_ctrl {
165 struct ich8_hsflctl {
166 u16 flcgo :1; /* 0 Flash Cycle Go */
167 u16 flcycle :2; /* 2:1 Flash Cycle */
168 u16 reserved :5; /* 7:3 Reserved */
169 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
170 u16 flockdn :6; /* 15:10 Reserved */
175 /* ICH Flash Region Access Permissions */
176 union ich8_hws_flash_regacc {
178 u32 grra :8; /* 0:7 GbE region Read Access */
179 u32 grwa :8; /* 8:15 GbE region Write Access */
180 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
181 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
186 /* ICH Flash Protected Region */
187 union ich8_flash_protected_range {
189 u32 base:13; /* 0:12 Protected Range Base */
190 u32 reserved1:2; /* 13:14 Reserved */
191 u32 rpe:1; /* 15 Read Protection Enable */
192 u32 limit:13; /* 16:28 Protected Range Limit */
193 u32 reserved2:2; /* 29:30 Reserved */
194 u32 wpe:1; /* 31 Write Protection Enable */
199 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
200 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
201 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
202 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
203 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
204 u32 offset, u8 byte);
205 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
207 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
209 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
211 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
212 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
213 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
214 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
215 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
216 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
217 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
218 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
219 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
220 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
221 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
222 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
223 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
224 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
225 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
226 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
228 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
230 return readw(hw->flash_address + reg);
233 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
235 return readl(hw->flash_address + reg);
238 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
240 writew(val, hw->flash_address + reg);
243 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
245 writel(val, hw->flash_address + reg);
248 #define er16flash(reg) __er16flash(hw, (reg))
249 #define er32flash(reg) __er32flash(hw, (reg))
250 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
251 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
254 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
255 * @hw: pointer to the HW structure
257 * Initialize family-specific PHY parameters and function pointers.
259 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
261 struct e1000_phy_info *phy = &hw->phy;
265 phy->reset_delay_us = 100;
267 phy->ops.read_reg = e1000_read_phy_reg_hv;
268 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
269 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
270 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
271 phy->ops.write_reg = e1000_write_phy_reg_hv;
272 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
273 phy->ops.power_up = e1000_power_up_phy_copper;
274 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
275 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
277 phy->id = e1000_phy_unknown;
278 ret_val = e1000e_get_phy_id(hw);
281 if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
283 * In case the PHY needs to be in mdio slow mode (eg. 82577),
284 * set slow mode and try to get the PHY id again.
286 ret_val = e1000_set_mdio_slow_mode_hv(hw);
289 ret_val = e1000e_get_phy_id(hw);
293 phy->type = e1000e_get_phy_type_from_id(phy->id);
296 case e1000_phy_82577:
297 phy->ops.check_polarity = e1000_check_polarity_82577;
298 phy->ops.force_speed_duplex =
299 e1000_phy_force_speed_duplex_82577;
300 phy->ops.get_cable_length = e1000_get_cable_length_82577;
301 phy->ops.get_info = e1000_get_phy_info_82577;
302 phy->ops.commit = e1000e_phy_sw_reset;
303 case e1000_phy_82578:
304 phy->ops.check_polarity = e1000_check_polarity_m88;
305 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
306 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
307 phy->ops.get_info = e1000e_get_phy_info_m88;
310 ret_val = -E1000_ERR_PHY;
319 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
320 * @hw: pointer to the HW structure
322 * Initialize family-specific PHY parameters and function pointers.
324 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
326 struct e1000_phy_info *phy = &hw->phy;
331 phy->reset_delay_us = 100;
333 phy->ops.power_up = e1000_power_up_phy_copper;
334 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
337 * We may need to do this twice - once for IGP and if that fails,
338 * we'll set BM func pointers and try again
340 ret_val = e1000e_determine_phy_address(hw);
342 phy->ops.write_reg = e1000e_write_phy_reg_bm;
343 phy->ops.read_reg = e1000e_read_phy_reg_bm;
344 ret_val = e1000e_determine_phy_address(hw);
346 e_dbg("Cannot determine PHY addr. Erroring out\n");
352 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
355 ret_val = e1000e_get_phy_id(hw);
362 case IGP03E1000_E_PHY_ID:
363 phy->type = e1000_phy_igp_3;
364 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
365 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
366 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
367 phy->ops.get_info = e1000e_get_phy_info_igp;
368 phy->ops.check_polarity = e1000_check_polarity_igp;
369 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
372 case IFE_PLUS_E_PHY_ID:
374 phy->type = e1000_phy_ife;
375 phy->autoneg_mask = E1000_ALL_NOT_GIG;
376 phy->ops.get_info = e1000_get_phy_info_ife;
377 phy->ops.check_polarity = e1000_check_polarity_ife;
378 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
380 case BME1000_E_PHY_ID:
381 phy->type = e1000_phy_bm;
382 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
383 phy->ops.read_reg = e1000e_read_phy_reg_bm;
384 phy->ops.write_reg = e1000e_write_phy_reg_bm;
385 phy->ops.commit = e1000e_phy_sw_reset;
386 phy->ops.get_info = e1000e_get_phy_info_m88;
387 phy->ops.check_polarity = e1000_check_polarity_m88;
388 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
391 return -E1000_ERR_PHY;
399 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
400 * @hw: pointer to the HW structure
402 * Initialize family-specific NVM parameters and function
405 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
407 struct e1000_nvm_info *nvm = &hw->nvm;
408 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
409 u32 gfpreg, sector_base_addr, sector_end_addr;
412 /* Can't read flash registers if the register set isn't mapped. */
413 if (!hw->flash_address) {
414 e_dbg("ERROR: Flash registers not mapped\n");
415 return -E1000_ERR_CONFIG;
418 nvm->type = e1000_nvm_flash_sw;
420 gfpreg = er32flash(ICH_FLASH_GFPREG);
423 * sector_X_addr is a "sector"-aligned address (4096 bytes)
424 * Add 1 to sector_end_addr since this sector is included in
427 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
428 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
430 /* flash_base_addr is byte-aligned */
431 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
434 * find total size of the NVM, then cut in half since the total
435 * size represents two separate NVM banks.
437 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
438 << FLASH_SECTOR_ADDR_SHIFT;
439 nvm->flash_bank_size /= 2;
440 /* Adjust to word count */
441 nvm->flash_bank_size /= sizeof(u16);
443 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
445 /* Clear shadow ram */
446 for (i = 0; i < nvm->word_size; i++) {
447 dev_spec->shadow_ram[i].modified = false;
448 dev_spec->shadow_ram[i].value = 0xFFFF;
455 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
456 * @hw: pointer to the HW structure
458 * Initialize family-specific MAC parameters and function
461 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
463 struct e1000_hw *hw = &adapter->hw;
464 struct e1000_mac_info *mac = &hw->mac;
466 /* Set media type function pointer */
467 hw->phy.media_type = e1000_media_type_copper;
469 /* Set mta register count */
470 mac->mta_reg_count = 32;
471 /* Set rar entry count */
472 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
473 if (mac->type == e1000_ich8lan)
474 mac->rar_entry_count--;
475 /* Set if manageability features are enabled. */
476 mac->arc_subsystem_valid = true;
477 /* Adaptive IFS supported */
478 mac->adaptive_ifs = true;
486 mac->ops.id_led_init = e1000e_id_led_init;
488 mac->ops.setup_led = e1000e_setup_led_generic;
490 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
491 /* turn on/off LED */
492 mac->ops.led_on = e1000_led_on_ich8lan;
493 mac->ops.led_off = e1000_led_off_ich8lan;
497 mac->ops.id_led_init = e1000_id_led_init_pchlan;
499 mac->ops.setup_led = e1000_setup_led_pchlan;
501 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
502 /* turn on/off LED */
503 mac->ops.led_on = e1000_led_on_pchlan;
504 mac->ops.led_off = e1000_led_off_pchlan;
510 /* Enable PCS Lock-loss workaround for ICH8 */
511 if (mac->type == e1000_ich8lan)
512 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
518 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
519 * @hw: pointer to the HW structure
521 * Checks to see of the link status of the hardware has changed. If a
522 * change in link status has been detected, then we read the PHY registers
523 * to get the current speed/duplex if link exists.
525 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
527 struct e1000_mac_info *mac = &hw->mac;
532 * We only want to go out to the PHY registers to see if Auto-Neg
533 * has completed and/or if our link status has changed. The
534 * get_link_status flag is set upon receiving a Link Status
535 * Change or Rx Sequence Error interrupt.
537 if (!mac->get_link_status) {
543 * First we want to see if the MII Status Register reports
544 * link. If so, then we want to get the current speed/duplex
547 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
551 if (hw->mac.type == e1000_pchlan) {
552 ret_val = e1000_k1_gig_workaround_hv(hw, link);
558 goto out; /* No link detected */
560 mac->get_link_status = false;
562 if (hw->phy.type == e1000_phy_82578) {
563 ret_val = e1000_link_stall_workaround_hv(hw);
569 * Check if there was DownShift, must be checked
570 * immediately after link-up
572 e1000e_check_downshift(hw);
575 * If we are forcing speed/duplex, then we simply return since
576 * we have already determined whether we have link or not.
579 ret_val = -E1000_ERR_CONFIG;
584 * Auto-Neg is enabled. Auto Speed Detection takes care
585 * of MAC speed/duplex configuration. So we only need to
586 * configure Collision Distance in the MAC.
588 e1000e_config_collision_dist(hw);
591 * Configure Flow Control now that Auto-Neg has completed.
592 * First, we need to restore the desired flow control
593 * settings because we may have had to re-autoneg with a
594 * different link partner.
596 ret_val = e1000e_config_fc_after_link_up(hw);
598 e_dbg("Error configuring flow control\n");
604 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
606 struct e1000_hw *hw = &adapter->hw;
609 rc = e1000_init_mac_params_ich8lan(adapter);
613 rc = e1000_init_nvm_params_ich8lan(hw);
617 if (hw->mac.type == e1000_pchlan)
618 rc = e1000_init_phy_params_pchlan(hw);
620 rc = e1000_init_phy_params_ich8lan(hw);
624 if (adapter->hw.phy.type == e1000_phy_ife) {
625 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
626 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
629 if ((adapter->hw.mac.type == e1000_ich8lan) &&
630 (adapter->hw.phy.type == e1000_phy_igp_3))
631 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
636 static DEFINE_MUTEX(nvm_mutex);
639 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
640 * @hw: pointer to the HW structure
642 * Acquires the mutex for performing NVM operations.
644 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
646 mutex_lock(&nvm_mutex);
652 * e1000_release_nvm_ich8lan - Release NVM mutex
653 * @hw: pointer to the HW structure
655 * Releases the mutex used while performing NVM operations.
657 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
659 mutex_unlock(&nvm_mutex);
664 static DEFINE_MUTEX(swflag_mutex);
667 * e1000_acquire_swflag_ich8lan - Acquire software control flag
668 * @hw: pointer to the HW structure
670 * Acquires the software control flag for performing PHY and select
673 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
675 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
678 mutex_lock(&swflag_mutex);
681 extcnf_ctrl = er32(EXTCNF_CTRL);
682 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
690 e_dbg("SW/FW/HW has locked the resource for too long.\n");
691 ret_val = -E1000_ERR_CONFIG;
695 timeout = SW_FLAG_TIMEOUT;
697 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
698 ew32(EXTCNF_CTRL, extcnf_ctrl);
701 extcnf_ctrl = er32(EXTCNF_CTRL);
702 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
710 e_dbg("Failed to acquire the semaphore.\n");
711 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
712 ew32(EXTCNF_CTRL, extcnf_ctrl);
713 ret_val = -E1000_ERR_CONFIG;
719 mutex_unlock(&swflag_mutex);
725 * e1000_release_swflag_ich8lan - Release software control flag
726 * @hw: pointer to the HW structure
728 * Releases the software control flag for performing PHY and select
731 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
735 extcnf_ctrl = er32(EXTCNF_CTRL);
736 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
737 ew32(EXTCNF_CTRL, extcnf_ctrl);
739 mutex_unlock(&swflag_mutex);
745 * e1000_check_mng_mode_ich8lan - Checks management mode
746 * @hw: pointer to the HW structure
748 * This checks if the adapter has manageability enabled.
749 * This is a function pointer entry point only called by read/write
750 * routines for the PHY and NVM parts.
752 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
758 return (fwsm & E1000_FWSM_MODE_MASK) ==
759 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
763 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
764 * @hw: pointer to the HW structure
766 * Checks if firmware is blocking the reset of the PHY.
767 * This is a function pointer entry point only called by
770 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
776 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
780 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
781 * @hw: pointer to the HW structure
783 * SW should configure the LCD from the NVM extended configuration region
784 * as a workaround for certain parts.
786 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
788 struct e1000_phy_info *phy = &hw->phy;
789 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
791 u16 word_addr, reg_data, reg_addr, phy_page = 0;
793 ret_val = hw->phy.ops.acquire(hw);
798 * Initialize the PHY from the NVM on ICH platforms. This
799 * is needed due to an issue where the NVM configuration is
800 * not properly autoloaded after power transitions.
801 * Therefore, after each PHY reset, we will load the
802 * configuration data out of the NVM manually.
804 if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
805 (hw->mac.type == e1000_pchlan)) {
806 struct e1000_adapter *adapter = hw->adapter;
808 /* Check if SW needs to configure the PHY */
809 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
810 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
811 (hw->mac.type == e1000_pchlan))
812 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
814 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
816 data = er32(FEXTNVM);
817 if (!(data & sw_cfg_mask))
820 /* Wait for basic configuration completes before proceeding */
821 e1000_lan_init_done_ich8lan(hw);
824 * Make sure HW does not configure LCD from PHY
825 * extended configuration before SW configuration
827 data = er32(EXTCNF_CTRL);
828 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
831 cnf_size = er32(EXTCNF_SIZE);
832 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
833 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
837 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
838 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
840 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
841 (hw->mac.type == e1000_pchlan)) {
843 * HW configures the SMBus address and LEDs when the
844 * OEM and LCD Write Enable bits are set in the NVM.
845 * When both NVM bits are cleared, SW will configure
849 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
850 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
851 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
852 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
858 ret_val = e1000_write_phy_reg_hv_locked(hw,
864 /* Configure LCD from extended configuration region. */
866 /* cnf_base_addr is in DWORD */
867 word_addr = (u16)(cnf_base_addr << 1);
869 for (i = 0; i < cnf_size; i++) {
870 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
875 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
880 /* Save off the PHY page for future writes. */
881 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
886 reg_addr &= PHY_REG_MASK;
887 reg_addr |= phy_page;
889 ret_val = phy->ops.write_reg_locked(hw,
898 hw->phy.ops.release(hw);
903 * e1000_k1_gig_workaround_hv - K1 Si workaround
904 * @hw: pointer to the HW structure
905 * @link: link up bool flag
907 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
908 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
909 * If link is down, the function will restore the default K1 setting located
912 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
916 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
918 if (hw->mac.type != e1000_pchlan)
921 /* Wrap the whole flow with the sw flag */
922 ret_val = hw->phy.ops.acquire(hw);
926 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
928 if (hw->phy.type == e1000_phy_82578) {
929 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
934 status_reg &= BM_CS_STATUS_LINK_UP |
935 BM_CS_STATUS_RESOLVED |
936 BM_CS_STATUS_SPEED_MASK;
938 if (status_reg == (BM_CS_STATUS_LINK_UP |
939 BM_CS_STATUS_RESOLVED |
940 BM_CS_STATUS_SPEED_1000))
944 if (hw->phy.type == e1000_phy_82577) {
945 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
950 status_reg &= HV_M_STATUS_LINK_UP |
951 HV_M_STATUS_AUTONEG_COMPLETE |
952 HV_M_STATUS_SPEED_MASK;
954 if (status_reg == (HV_M_STATUS_LINK_UP |
955 HV_M_STATUS_AUTONEG_COMPLETE |
956 HV_M_STATUS_SPEED_1000))
960 /* Link stall fix for link up */
961 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
967 /* Link stall fix for link down */
968 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
974 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
977 hw->phy.ops.release(hw);
983 * e1000_configure_k1_ich8lan - Configure K1 power state
984 * @hw: pointer to the HW structure
985 * @enable: K1 state to configure
987 * Configure the K1 power state based on the provided parameter.
988 * Assumes semaphore already acquired.
990 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
992 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1000 ret_val = e1000e_read_kmrn_reg_locked(hw,
1001 E1000_KMRNCTRLSTA_K1_CONFIG,
1007 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1009 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1011 ret_val = e1000e_write_kmrn_reg_locked(hw,
1012 E1000_KMRNCTRLSTA_K1_CONFIG,
1018 ctrl_ext = er32(CTRL_EXT);
1019 ctrl_reg = er32(CTRL);
1021 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1022 reg |= E1000_CTRL_FRCSPD;
1025 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1027 ew32(CTRL, ctrl_reg);
1028 ew32(CTRL_EXT, ctrl_ext);
1036 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1037 * @hw: pointer to the HW structure
1038 * @d0_state: boolean if entering d0 or d3 device state
1040 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1041 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1042 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1044 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1050 if (hw->mac.type != e1000_pchlan)
1053 ret_val = hw->phy.ops.acquire(hw);
1057 mac_reg = er32(EXTCNF_CTRL);
1058 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1061 mac_reg = er32(FEXTNVM);
1062 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1065 mac_reg = er32(PHY_CTRL);
1067 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1071 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1074 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1075 oem_reg |= HV_OEM_BITS_GBE_DIS;
1077 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1078 oem_reg |= HV_OEM_BITS_LPLU;
1080 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1081 oem_reg |= HV_OEM_BITS_GBE_DIS;
1083 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1084 oem_reg |= HV_OEM_BITS_LPLU;
1086 /* Restart auto-neg to activate the bits */
1087 if (!e1000_check_reset_block(hw))
1088 oem_reg |= HV_OEM_BITS_RESTART_AN;
1089 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1092 hw->phy.ops.release(hw);
1099 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1100 * @hw: pointer to the HW structure
1102 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1107 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1111 data |= HV_KMRN_MDIO_SLOW;
1113 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1119 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1120 * done after every PHY reset.
1122 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1126 if (hw->mac.type != e1000_pchlan)
1129 /* Set MDIO slow mode before any other MDIO access */
1130 if (hw->phy.type == e1000_phy_82577) {
1131 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1136 if (((hw->phy.type == e1000_phy_82577) &&
1137 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1138 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1139 /* Disable generation of early preamble */
1140 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1144 /* Preamble tuning for SSC */
1145 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1150 if (hw->phy.type == e1000_phy_82578) {
1152 * Return registers to default by doing a soft reset then
1153 * writing 0x3140 to the control register.
1155 if (hw->phy.revision < 2) {
1156 e1000e_phy_sw_reset(hw);
1157 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1162 ret_val = hw->phy.ops.acquire(hw);
1167 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1170 hw->phy.ops.release(hw);
1173 * Configure the K1 Si workaround during phy reset assuming there is
1174 * link so that it disables K1 if link is in 1Gbps.
1176 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1183 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1184 * @hw: pointer to the HW structure
1186 * Check the appropriate indication the MAC has finished configuring the
1187 * PHY after a software reset.
1189 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1191 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1193 /* Wait for basic configuration completes before proceeding */
1195 data = er32(STATUS);
1196 data &= E1000_STATUS_LAN_INIT_DONE;
1198 } while ((!data) && --loop);
1201 * If basic configuration is incomplete before the above loop
1202 * count reaches 0, loading the configuration from NVM will
1203 * leave the PHY in a bad state possibly resulting in no link.
1206 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1208 /* Clear the Init Done bit for the next init event */
1209 data = er32(STATUS);
1210 data &= ~E1000_STATUS_LAN_INIT_DONE;
1215 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1216 * @hw: pointer to the HW structure
1219 * This is a function pointer entry point called by drivers
1220 * or other shared routines.
1222 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1227 ret_val = e1000e_phy_hw_reset_generic(hw);
1231 /* Allow time for h/w to get to a quiescent state after reset */
1234 /* Perform any necessary post-reset workarounds */
1235 if (hw->mac.type == e1000_pchlan) {
1236 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1241 /* Dummy read to clear the phy wakeup bit after lcd reset */
1242 if (hw->mac.type == e1000_pchlan)
1243 e1e_rphy(hw, BM_WUC, ®);
1245 /* Configure the LCD with the extended configuration region in NVM */
1246 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1250 /* Configure the LCD with the OEM bits in NVM */
1251 if (hw->mac.type == e1000_pchlan)
1252 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1259 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1260 * @hw: pointer to the HW structure
1261 * @active: true to enable LPLU, false to disable
1263 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1264 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1265 * the phy speed. This function will manually set the LPLU bit and restart
1266 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1267 * since it configures the same bit.
1269 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1274 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1279 oem_reg |= HV_OEM_BITS_LPLU;
1281 oem_reg &= ~HV_OEM_BITS_LPLU;
1283 oem_reg |= HV_OEM_BITS_RESTART_AN;
1284 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1291 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1292 * @hw: pointer to the HW structure
1293 * @active: true to enable LPLU, false to disable
1295 * Sets the LPLU D0 state according to the active flag. When
1296 * activating LPLU this function also disables smart speed
1297 * and vice versa. LPLU will not be activated unless the
1298 * device autonegotiation advertisement meets standards of
1299 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1300 * This is a function pointer entry point only called by
1301 * PHY setup routines.
1303 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1305 struct e1000_phy_info *phy = &hw->phy;
1310 if (phy->type == e1000_phy_ife)
1313 phy_ctrl = er32(PHY_CTRL);
1316 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1317 ew32(PHY_CTRL, phy_ctrl);
1319 if (phy->type != e1000_phy_igp_3)
1323 * Call gig speed drop workaround on LPLU before accessing
1326 if (hw->mac.type == e1000_ich8lan)
1327 e1000e_gig_downshift_workaround_ich8lan(hw);
1329 /* When LPLU is enabled, we should disable SmartSpeed */
1330 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1331 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1332 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1336 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1337 ew32(PHY_CTRL, phy_ctrl);
1339 if (phy->type != e1000_phy_igp_3)
1343 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1344 * during Dx states where the power conservation is most
1345 * important. During driver activity we should enable
1346 * SmartSpeed, so performance is maintained.
1348 if (phy->smart_speed == e1000_smart_speed_on) {
1349 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1354 data |= IGP01E1000_PSCFR_SMART_SPEED;
1355 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1359 } else if (phy->smart_speed == e1000_smart_speed_off) {
1360 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1365 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1366 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1377 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1378 * @hw: pointer to the HW structure
1379 * @active: true to enable LPLU, false to disable
1381 * Sets the LPLU D3 state according to the active flag. When
1382 * activating LPLU this function also disables smart speed
1383 * and vice versa. LPLU will not be activated unless the
1384 * device autonegotiation advertisement meets standards of
1385 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1386 * This is a function pointer entry point only called by
1387 * PHY setup routines.
1389 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1391 struct e1000_phy_info *phy = &hw->phy;
1396 phy_ctrl = er32(PHY_CTRL);
1399 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1400 ew32(PHY_CTRL, phy_ctrl);
1402 if (phy->type != e1000_phy_igp_3)
1406 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1407 * during Dx states where the power conservation is most
1408 * important. During driver activity we should enable
1409 * SmartSpeed, so performance is maintained.
1411 if (phy->smart_speed == e1000_smart_speed_on) {
1412 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1417 data |= IGP01E1000_PSCFR_SMART_SPEED;
1418 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1422 } else if (phy->smart_speed == e1000_smart_speed_off) {
1423 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1428 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1429 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1434 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1435 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1436 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1437 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1438 ew32(PHY_CTRL, phy_ctrl);
1440 if (phy->type != e1000_phy_igp_3)
1444 * Call gig speed drop workaround on LPLU before accessing
1447 if (hw->mac.type == e1000_ich8lan)
1448 e1000e_gig_downshift_workaround_ich8lan(hw);
1450 /* When LPLU is enabled, we should disable SmartSpeed */
1451 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1455 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1456 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1463 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1464 * @hw: pointer to the HW structure
1465 * @bank: pointer to the variable that returns the active bank
1467 * Reads signature byte from the NVM using the flash access registers.
1468 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1470 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1473 struct e1000_nvm_info *nvm = &hw->nvm;
1474 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1475 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1479 switch (hw->mac.type) {
1483 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1484 E1000_EECD_SEC1VAL_VALID_MASK) {
1485 if (eecd & E1000_EECD_SEC1VAL)
1492 e_dbg("Unable to determine valid NVM bank via EEC - "
1493 "reading flash signature\n");
1496 /* set bank to 0 in case flash read fails */
1500 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1504 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1505 E1000_ICH_NVM_SIG_VALUE) {
1511 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1516 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1517 E1000_ICH_NVM_SIG_VALUE) {
1522 e_dbg("ERROR: No valid NVM bank present\n");
1523 return -E1000_ERR_NVM;
1530 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1531 * @hw: pointer to the HW structure
1532 * @offset: The offset (in bytes) of the word(s) to read.
1533 * @words: Size of data to read in words
1534 * @data: Pointer to the word(s) to read at offset.
1536 * Reads a word(s) from the NVM using the flash access registers.
1538 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1541 struct e1000_nvm_info *nvm = &hw->nvm;
1542 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1548 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1550 e_dbg("nvm parameter(s) out of bounds\n");
1551 ret_val = -E1000_ERR_NVM;
1555 nvm->ops.acquire(hw);
1557 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1559 e_dbg("Could not detect valid bank, assuming bank 0\n");
1563 act_offset = (bank) ? nvm->flash_bank_size : 0;
1564 act_offset += offset;
1567 for (i = 0; i < words; i++) {
1568 if ((dev_spec->shadow_ram) &&
1569 (dev_spec->shadow_ram[offset+i].modified)) {
1570 data[i] = dev_spec->shadow_ram[offset+i].value;
1572 ret_val = e1000_read_flash_word_ich8lan(hw,
1581 nvm->ops.release(hw);
1585 e_dbg("NVM read error: %d\n", ret_val);
1591 * e1000_flash_cycle_init_ich8lan - Initialize flash
1592 * @hw: pointer to the HW structure
1594 * This function does initial flash setup so that a new read/write/erase cycle
1597 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1599 union ich8_hws_flash_status hsfsts;
1600 s32 ret_val = -E1000_ERR_NVM;
1603 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1605 /* Check if the flash descriptor is valid */
1606 if (hsfsts.hsf_status.fldesvalid == 0) {
1607 e_dbg("Flash descriptor invalid. "
1608 "SW Sequencing must be used.");
1609 return -E1000_ERR_NVM;
1612 /* Clear FCERR and DAEL in hw status by writing 1 */
1613 hsfsts.hsf_status.flcerr = 1;
1614 hsfsts.hsf_status.dael = 1;
1616 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1619 * Either we should have a hardware SPI cycle in progress
1620 * bit to check against, in order to start a new cycle or
1621 * FDONE bit should be changed in the hardware so that it
1622 * is 1 after hardware reset, which can then be used as an
1623 * indication whether a cycle is in progress or has been
1627 if (hsfsts.hsf_status.flcinprog == 0) {
1629 * There is no cycle running at present,
1630 * so we can start a cycle.
1631 * Begin by setting Flash Cycle Done.
1633 hsfsts.hsf_status.flcdone = 1;
1634 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1638 * Otherwise poll for sometime so the current
1639 * cycle has a chance to end before giving up.
1641 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1642 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1643 if (hsfsts.hsf_status.flcinprog == 0) {
1651 * Successful in waiting for previous cycle to timeout,
1652 * now set the Flash Cycle Done.
1654 hsfsts.hsf_status.flcdone = 1;
1655 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1657 e_dbg("Flash controller busy, cannot get access");
1665 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1666 * @hw: pointer to the HW structure
1667 * @timeout: maximum time to wait for completion
1669 * This function starts a flash cycle and waits for its completion.
1671 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1673 union ich8_hws_flash_ctrl hsflctl;
1674 union ich8_hws_flash_status hsfsts;
1675 s32 ret_val = -E1000_ERR_NVM;
1678 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1679 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1680 hsflctl.hsf_ctrl.flcgo = 1;
1681 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1683 /* wait till FDONE bit is set to 1 */
1685 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1686 if (hsfsts.hsf_status.flcdone == 1)
1689 } while (i++ < timeout);
1691 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1698 * e1000_read_flash_word_ich8lan - Read word from flash
1699 * @hw: pointer to the HW structure
1700 * @offset: offset to data location
1701 * @data: pointer to the location for storing the data
1703 * Reads the flash word at offset into data. Offset is converted
1704 * to bytes before read.
1706 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1709 /* Must convert offset into bytes. */
1712 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1716 * e1000_read_flash_byte_ich8lan - Read byte from flash
1717 * @hw: pointer to the HW structure
1718 * @offset: The offset of the byte to read.
1719 * @data: Pointer to a byte to store the value read.
1721 * Reads a single byte from the NVM using the flash access registers.
1723 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1729 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1739 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1740 * @hw: pointer to the HW structure
1741 * @offset: The offset (in bytes) of the byte or word to read.
1742 * @size: Size of data to read, 1=byte 2=word
1743 * @data: Pointer to the word to store the value read.
1745 * Reads a byte or word from the NVM using the flash access registers.
1747 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1750 union ich8_hws_flash_status hsfsts;
1751 union ich8_hws_flash_ctrl hsflctl;
1752 u32 flash_linear_addr;
1754 s32 ret_val = -E1000_ERR_NVM;
1757 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1758 return -E1000_ERR_NVM;
1760 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1761 hw->nvm.flash_base_addr;
1766 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1770 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1771 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1772 hsflctl.hsf_ctrl.fldbcount = size - 1;
1773 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1774 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1776 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1778 ret_val = e1000_flash_cycle_ich8lan(hw,
1779 ICH_FLASH_READ_COMMAND_TIMEOUT);
1782 * Check if FCERR is set to 1, if set to 1, clear it
1783 * and try the whole sequence a few more times, else
1784 * read in (shift in) the Flash Data0, the order is
1785 * least significant byte first msb to lsb
1788 flash_data = er32flash(ICH_FLASH_FDATA0);
1790 *data = (u8)(flash_data & 0x000000FF);
1791 } else if (size == 2) {
1792 *data = (u16)(flash_data & 0x0000FFFF);
1797 * If we've gotten here, then things are probably
1798 * completely hosed, but if the error condition is
1799 * detected, it won't hurt to give it another try...
1800 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1802 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1803 if (hsfsts.hsf_status.flcerr == 1) {
1804 /* Repeat for some time before giving up. */
1806 } else if (hsfsts.hsf_status.flcdone == 0) {
1807 e_dbg("Timeout error - flash cycle "
1808 "did not complete.");
1812 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1818 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1819 * @hw: pointer to the HW structure
1820 * @offset: The offset (in bytes) of the word(s) to write.
1821 * @words: Size of data to write in words
1822 * @data: Pointer to the word(s) to write at offset.
1824 * Writes a byte or word to the NVM using the flash access registers.
1826 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1829 struct e1000_nvm_info *nvm = &hw->nvm;
1830 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1833 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1835 e_dbg("nvm parameter(s) out of bounds\n");
1836 return -E1000_ERR_NVM;
1839 nvm->ops.acquire(hw);
1841 for (i = 0; i < words; i++) {
1842 dev_spec->shadow_ram[offset+i].modified = true;
1843 dev_spec->shadow_ram[offset+i].value = data[i];
1846 nvm->ops.release(hw);
1852 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1853 * @hw: pointer to the HW structure
1855 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1856 * which writes the checksum to the shadow ram. The changes in the shadow
1857 * ram are then committed to the EEPROM by processing each bank at a time
1858 * checking for the modified bit and writing only the pending changes.
1859 * After a successful commit, the shadow ram is cleared and is ready for
1862 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1864 struct e1000_nvm_info *nvm = &hw->nvm;
1865 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1866 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1870 ret_val = e1000e_update_nvm_checksum_generic(hw);
1874 if (nvm->type != e1000_nvm_flash_sw)
1877 nvm->ops.acquire(hw);
1880 * We're writing to the opposite bank so if we're on bank 1,
1881 * write to bank 0 etc. We also need to erase the segment that
1882 * is going to be written
1884 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1886 e_dbg("Could not detect valid bank, assuming bank 0\n");
1891 new_bank_offset = nvm->flash_bank_size;
1892 old_bank_offset = 0;
1893 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1895 nvm->ops.release(hw);
1899 old_bank_offset = nvm->flash_bank_size;
1900 new_bank_offset = 0;
1901 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1903 nvm->ops.release(hw);
1908 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1910 * Determine whether to write the value stored
1911 * in the other NVM bank or a modified value stored
1914 if (dev_spec->shadow_ram[i].modified) {
1915 data = dev_spec->shadow_ram[i].value;
1917 ret_val = e1000_read_flash_word_ich8lan(hw, i +
1925 * If the word is 0x13, then make sure the signature bits
1926 * (15:14) are 11b until the commit has completed.
1927 * This will allow us to write 10b which indicates the
1928 * signature is valid. We want to do this after the write
1929 * has completed so that we don't mark the segment valid
1930 * while the write is still in progress
1932 if (i == E1000_ICH_NVM_SIG_WORD)
1933 data |= E1000_ICH_NVM_SIG_MASK;
1935 /* Convert offset to bytes. */
1936 act_offset = (i + new_bank_offset) << 1;
1939 /* Write the bytes to the new bank. */
1940 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1947 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1955 * Don't bother writing the segment valid bits if sector
1956 * programming failed.
1959 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1960 e_dbg("Flash commit failed.\n");
1961 nvm->ops.release(hw);
1966 * Finally validate the new segment by setting bit 15:14
1967 * to 10b in word 0x13 , this can be done without an
1968 * erase as well since these bits are 11 to start with
1969 * and we need to change bit 14 to 0b
1971 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1972 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1974 nvm->ops.release(hw);
1978 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1982 nvm->ops.release(hw);
1987 * And invalidate the previously valid segment by setting
1988 * its signature word (0x13) high_byte to 0b. This can be
1989 * done without an erase because flash erase sets all bits
1990 * to 1's. We can write 1's to 0's without an erase
1992 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1993 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1995 nvm->ops.release(hw);
1999 /* Great! Everything worked, we can now clear the cached entries. */
2000 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2001 dev_spec->shadow_ram[i].modified = false;
2002 dev_spec->shadow_ram[i].value = 0xFFFF;
2005 nvm->ops.release(hw);
2008 * Reload the EEPROM, or else modifications will not appear
2009 * until after the next adapter reset.
2011 e1000e_reload_nvm(hw);
2016 e_dbg("NVM update error: %d\n", ret_val);
2022 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2023 * @hw: pointer to the HW structure
2025 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2026 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2027 * calculated, in which case we need to calculate the checksum and set bit 6.
2029 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2035 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2036 * needs to be fixed. This bit is an indication that the NVM
2037 * was prepared by OEM software and did not calculate the
2038 * checksum...a likely scenario.
2040 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2044 if ((data & 0x40) == 0) {
2046 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2049 ret_val = e1000e_update_nvm_checksum(hw);
2054 return e1000e_validate_nvm_checksum_generic(hw);
2058 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2059 * @hw: pointer to the HW structure
2061 * To prevent malicious write/erase of the NVM, set it to be read-only
2062 * so that the hardware ignores all write/erase cycles of the NVM via
2063 * the flash control registers. The shadow-ram copy of the NVM will
2064 * still be updated, however any updates to this copy will not stick
2065 * across driver reloads.
2067 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2069 struct e1000_nvm_info *nvm = &hw->nvm;
2070 union ich8_flash_protected_range pr0;
2071 union ich8_hws_flash_status hsfsts;
2074 nvm->ops.acquire(hw);
2076 gfpreg = er32flash(ICH_FLASH_GFPREG);
2078 /* Write-protect GbE Sector of NVM */
2079 pr0.regval = er32flash(ICH_FLASH_PR0);
2080 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2081 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2082 pr0.range.wpe = true;
2083 ew32flash(ICH_FLASH_PR0, pr0.regval);
2086 * Lock down a subset of GbE Flash Control Registers, e.g.
2087 * PR0 to prevent the write-protection from being lifted.
2088 * Once FLOCKDN is set, the registers protected by it cannot
2089 * be written until FLOCKDN is cleared by a hardware reset.
2091 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2092 hsfsts.hsf_status.flockdn = true;
2093 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2095 nvm->ops.release(hw);
2099 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2100 * @hw: pointer to the HW structure
2101 * @offset: The offset (in bytes) of the byte/word to read.
2102 * @size: Size of data to read, 1=byte 2=word
2103 * @data: The byte(s) to write to the NVM.
2105 * Writes one/two bytes to the NVM using the flash access registers.
2107 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2110 union ich8_hws_flash_status hsfsts;
2111 union ich8_hws_flash_ctrl hsflctl;
2112 u32 flash_linear_addr;
2117 if (size < 1 || size > 2 || data > size * 0xff ||
2118 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2119 return -E1000_ERR_NVM;
2121 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2122 hw->nvm.flash_base_addr;
2127 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2131 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2132 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2133 hsflctl.hsf_ctrl.fldbcount = size -1;
2134 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2135 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2137 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2140 flash_data = (u32)data & 0x00FF;
2142 flash_data = (u32)data;
2144 ew32flash(ICH_FLASH_FDATA0, flash_data);
2147 * check if FCERR is set to 1 , if set to 1, clear it
2148 * and try the whole sequence a few more times else done
2150 ret_val = e1000_flash_cycle_ich8lan(hw,
2151 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2156 * If we're here, then things are most likely
2157 * completely hosed, but if the error condition
2158 * is detected, it won't hurt to give it another
2159 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2161 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2162 if (hsfsts.hsf_status.flcerr == 1)
2163 /* Repeat for some time before giving up. */
2165 if (hsfsts.hsf_status.flcdone == 0) {
2166 e_dbg("Timeout error - flash cycle "
2167 "did not complete.");
2170 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2176 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2177 * @hw: pointer to the HW structure
2178 * @offset: The index of the byte to read.
2179 * @data: The byte to write to the NVM.
2181 * Writes a single byte to the NVM using the flash access registers.
2183 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2186 u16 word = (u16)data;
2188 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2192 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2193 * @hw: pointer to the HW structure
2194 * @offset: The offset of the byte to write.
2195 * @byte: The byte to write to the NVM.
2197 * Writes a single byte to the NVM using the flash access registers.
2198 * Goes through a retry algorithm before giving up.
2200 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2201 u32 offset, u8 byte)
2204 u16 program_retries;
2206 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2210 for (program_retries = 0; program_retries < 100; program_retries++) {
2211 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2213 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2217 if (program_retries == 100)
2218 return -E1000_ERR_NVM;
2224 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2225 * @hw: pointer to the HW structure
2226 * @bank: 0 for first bank, 1 for second bank, etc.
2228 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2229 * bank N is 4096 * N + flash_reg_addr.
2231 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2233 struct e1000_nvm_info *nvm = &hw->nvm;
2234 union ich8_hws_flash_status hsfsts;
2235 union ich8_hws_flash_ctrl hsflctl;
2236 u32 flash_linear_addr;
2237 /* bank size is in 16bit words - adjust to bytes */
2238 u32 flash_bank_size = nvm->flash_bank_size * 2;
2241 s32 j, iteration, sector_size;
2243 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2246 * Determine HW Sector size: Read BERASE bits of hw flash status
2248 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2249 * consecutive sectors. The start index for the nth Hw sector
2250 * can be calculated as = bank * 4096 + n * 256
2251 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2252 * The start index for the nth Hw sector can be calculated
2254 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2255 * (ich9 only, otherwise error condition)
2256 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2258 switch (hsfsts.hsf_status.berasesz) {
2260 /* Hw sector size 256 */
2261 sector_size = ICH_FLASH_SEG_SIZE_256;
2262 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2265 sector_size = ICH_FLASH_SEG_SIZE_4K;
2269 sector_size = ICH_FLASH_SEG_SIZE_8K;
2273 sector_size = ICH_FLASH_SEG_SIZE_64K;
2277 return -E1000_ERR_NVM;
2280 /* Start with the base address, then add the sector offset. */
2281 flash_linear_addr = hw->nvm.flash_base_addr;
2282 flash_linear_addr += (bank) ? flash_bank_size : 0;
2284 for (j = 0; j < iteration ; j++) {
2287 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2292 * Write a value 11 (block Erase) in Flash
2293 * Cycle field in hw flash control
2295 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2296 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2297 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2300 * Write the last 24 bits of an index within the
2301 * block into Flash Linear address field in Flash
2304 flash_linear_addr += (j * sector_size);
2305 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2307 ret_val = e1000_flash_cycle_ich8lan(hw,
2308 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2313 * Check if FCERR is set to 1. If 1,
2314 * clear it and try the whole sequence
2315 * a few more times else Done
2317 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2318 if (hsfsts.hsf_status.flcerr == 1)
2319 /* repeat for some time before giving up */
2321 else if (hsfsts.hsf_status.flcdone == 0)
2323 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2330 * e1000_valid_led_default_ich8lan - Set the default LED settings
2331 * @hw: pointer to the HW structure
2332 * @data: Pointer to the LED settings
2334 * Reads the LED default settings from the NVM to data. If the NVM LED
2335 * settings is all 0's or F's, set the LED default to a valid LED default
2338 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2342 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2344 e_dbg("NVM Read Error\n");
2348 if (*data == ID_LED_RESERVED_0000 ||
2349 *data == ID_LED_RESERVED_FFFF)
2350 *data = ID_LED_DEFAULT_ICH8LAN;
2356 * e1000_id_led_init_pchlan - store LED configurations
2357 * @hw: pointer to the HW structure
2359 * PCH does not control LEDs via the LEDCTL register, rather it uses
2360 * the PHY LED configuration register.
2362 * PCH also does not have an "always on" or "always off" mode which
2363 * complicates the ID feature. Instead of using the "on" mode to indicate
2364 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2365 * use "link_up" mode. The LEDs will still ID on request if there is no
2366 * link based on logic in e1000_led_[on|off]_pchlan().
2368 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2370 struct e1000_mac_info *mac = &hw->mac;
2372 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2373 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2374 u16 data, i, temp, shift;
2376 /* Get default ID LED modes */
2377 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2381 mac->ledctl_default = er32(LEDCTL);
2382 mac->ledctl_mode1 = mac->ledctl_default;
2383 mac->ledctl_mode2 = mac->ledctl_default;
2385 for (i = 0; i < 4; i++) {
2386 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2389 case ID_LED_ON1_DEF2:
2390 case ID_LED_ON1_ON2:
2391 case ID_LED_ON1_OFF2:
2392 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2393 mac->ledctl_mode1 |= (ledctl_on << shift);
2395 case ID_LED_OFF1_DEF2:
2396 case ID_LED_OFF1_ON2:
2397 case ID_LED_OFF1_OFF2:
2398 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2399 mac->ledctl_mode1 |= (ledctl_off << shift);
2406 case ID_LED_DEF1_ON2:
2407 case ID_LED_ON1_ON2:
2408 case ID_LED_OFF1_ON2:
2409 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2410 mac->ledctl_mode2 |= (ledctl_on << shift);
2412 case ID_LED_DEF1_OFF2:
2413 case ID_LED_ON1_OFF2:
2414 case ID_LED_OFF1_OFF2:
2415 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2416 mac->ledctl_mode2 |= (ledctl_off << shift);
2429 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2430 * @hw: pointer to the HW structure
2432 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2433 * register, so the the bus width is hard coded.
2435 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2437 struct e1000_bus_info *bus = &hw->bus;
2440 ret_val = e1000e_get_bus_info_pcie(hw);
2443 * ICH devices are "PCI Express"-ish. They have
2444 * a configuration space, but do not contain
2445 * PCI Express Capability registers, so bus width
2446 * must be hardcoded.
2448 if (bus->width == e1000_bus_width_unknown)
2449 bus->width = e1000_bus_width_pcie_x1;
2455 * e1000_reset_hw_ich8lan - Reset the hardware
2456 * @hw: pointer to the HW structure
2458 * Does a full reset of the hardware which includes a reset of the PHY and
2461 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2463 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2469 * Prevent the PCI-E bus from sticking if there is no TLP connection
2470 * on the last TLP read/write transaction when MAC is reset.
2472 ret_val = e1000e_disable_pcie_master(hw);
2474 e_dbg("PCI-E Master disable polling has failed.\n");
2477 e_dbg("Masking off all interrupts\n");
2478 ew32(IMC, 0xffffffff);
2481 * Disable the Transmit and Receive units. Then delay to allow
2482 * any pending transactions to complete before we hit the MAC
2483 * with the global reset.
2486 ew32(TCTL, E1000_TCTL_PSP);
2491 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2492 if (hw->mac.type == e1000_ich8lan) {
2493 /* Set Tx and Rx buffer allocation to 8k apiece. */
2494 ew32(PBA, E1000_PBA_8K);
2495 /* Set Packet Buffer Size to 16k. */
2496 ew32(PBS, E1000_PBS_16K);
2499 if (hw->mac.type == e1000_pchlan) {
2500 /* Save the NVM K1 bit setting*/
2501 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®);
2505 if (reg & E1000_NVM_K1_ENABLE)
2506 dev_spec->nvm_k1_enabled = true;
2508 dev_spec->nvm_k1_enabled = false;
2513 if (!e1000_check_reset_block(hw)) {
2514 /* Clear PHY Reset Asserted bit */
2515 if (hw->mac.type >= e1000_pchlan) {
2516 u32 status = er32(STATUS);
2517 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2521 * PHY HW reset requires MAC CORE reset at the same
2522 * time to make sure the interface between MAC and the
2523 * external PHY is reset.
2525 ctrl |= E1000_CTRL_PHY_RST;
2527 ret_val = e1000_acquire_swflag_ich8lan(hw);
2528 e_dbg("Issuing a global reset to ich8lan\n");
2529 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2533 e1000_release_swflag_ich8lan(hw);
2535 /* Perform any necessary post-reset workarounds */
2536 if (hw->mac.type == e1000_pchlan)
2537 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2539 if (ctrl & E1000_CTRL_PHY_RST)
2540 ret_val = hw->phy.ops.get_cfg_done(hw);
2542 if (hw->mac.type >= e1000_ich10lan) {
2543 e1000_lan_init_done_ich8lan(hw);
2545 ret_val = e1000e_get_auto_rd_done(hw);
2548 * When auto config read does not complete, do not
2549 * return with an error. This can happen in situations
2550 * where there is no eeprom and prevents getting link.
2552 e_dbg("Auto Read Done did not complete\n");
2555 /* Dummy read to clear the phy wakeup bit after lcd reset */
2556 if (hw->mac.type == e1000_pchlan)
2557 e1e_rphy(hw, BM_WUC, ®);
2559 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2563 if (hw->mac.type == e1000_pchlan) {
2564 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2569 * For PCH, this write will make sure that any noise
2570 * will be detected as a CRC error and be dropped rather than show up
2571 * as a bad packet to the DMA engine.
2573 if (hw->mac.type == e1000_pchlan)
2574 ew32(CRC_OFFSET, 0x65656565);
2576 ew32(IMC, 0xffffffff);
2579 kab = er32(KABGTXD);
2580 kab |= E1000_KABGTXD_BGSQLBIAS;
2588 * e1000_init_hw_ich8lan - Initialize the hardware
2589 * @hw: pointer to the HW structure
2591 * Prepares the hardware for transmit and receive by doing the following:
2592 * - initialize hardware bits
2593 * - initialize LED identification
2594 * - setup receive address registers
2595 * - setup flow control
2596 * - setup transmit descriptors
2597 * - clear statistics
2599 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2601 struct e1000_mac_info *mac = &hw->mac;
2602 u32 ctrl_ext, txdctl, snoop;
2606 e1000_initialize_hw_bits_ich8lan(hw);
2608 /* Initialize identification LED */
2609 ret_val = mac->ops.id_led_init(hw);
2611 e_dbg("Error initializing identification LED\n");
2612 /* This is not fatal and we should not stop init due to this */
2614 /* Setup the receive address. */
2615 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2617 /* Zero out the Multicast HASH table */
2618 e_dbg("Zeroing the MTA\n");
2619 for (i = 0; i < mac->mta_reg_count; i++)
2620 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2623 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2624 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2625 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2627 if (hw->phy.type == e1000_phy_82578) {
2628 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2629 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2634 /* Setup link and flow control */
2635 ret_val = e1000_setup_link_ich8lan(hw);
2637 /* Set the transmit descriptor write-back policy for both queues */
2638 txdctl = er32(TXDCTL(0));
2639 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2640 E1000_TXDCTL_FULL_TX_DESC_WB;
2641 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2642 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2643 ew32(TXDCTL(0), txdctl);
2644 txdctl = er32(TXDCTL(1));
2645 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2646 E1000_TXDCTL_FULL_TX_DESC_WB;
2647 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2648 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2649 ew32(TXDCTL(1), txdctl);
2652 * ICH8 has opposite polarity of no_snoop bits.
2653 * By default, we should use snoop behavior.
2655 if (mac->type == e1000_ich8lan)
2656 snoop = PCIE_ICH8_SNOOP_ALL;
2658 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2659 e1000e_set_pcie_no_snoop(hw, snoop);
2661 ctrl_ext = er32(CTRL_EXT);
2662 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2663 ew32(CTRL_EXT, ctrl_ext);
2666 * Clear all of the statistics registers (clear on read). It is
2667 * important that we do this after we have tried to establish link
2668 * because the symbol error count will increment wildly if there
2671 e1000_clear_hw_cntrs_ich8lan(hw);
2676 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2677 * @hw: pointer to the HW structure
2679 * Sets/Clears required hardware bits necessary for correctly setting up the
2680 * hardware for transmit and receive.
2682 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2686 /* Extended Device Control */
2687 reg = er32(CTRL_EXT);
2689 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2690 if (hw->mac.type >= e1000_pchlan)
2691 reg |= E1000_CTRL_EXT_PHYPDEN;
2692 ew32(CTRL_EXT, reg);
2694 /* Transmit Descriptor Control 0 */
2695 reg = er32(TXDCTL(0));
2697 ew32(TXDCTL(0), reg);
2699 /* Transmit Descriptor Control 1 */
2700 reg = er32(TXDCTL(1));
2702 ew32(TXDCTL(1), reg);
2704 /* Transmit Arbitration Control 0 */
2705 reg = er32(TARC(0));
2706 if (hw->mac.type == e1000_ich8lan)
2707 reg |= (1 << 28) | (1 << 29);
2708 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2711 /* Transmit Arbitration Control 1 */
2712 reg = er32(TARC(1));
2713 if (er32(TCTL) & E1000_TCTL_MULR)
2717 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2721 if (hw->mac.type == e1000_ich8lan) {
2729 * e1000_setup_link_ich8lan - Setup flow control and link settings
2730 * @hw: pointer to the HW structure
2732 * Determines which flow control settings to use, then configures flow
2733 * control. Calls the appropriate media-specific link configuration
2734 * function. Assuming the adapter has a valid link partner, a valid link
2735 * should be established. Assumes the hardware has previously been reset
2736 * and the transmitter and receiver are not enabled.
2738 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2742 if (e1000_check_reset_block(hw))
2746 * ICH parts do not have a word in the NVM to determine
2747 * the default flow control setting, so we explicitly
2750 if (hw->fc.requested_mode == e1000_fc_default) {
2751 /* Workaround h/w hang when Tx flow control enabled */
2752 if (hw->mac.type == e1000_pchlan)
2753 hw->fc.requested_mode = e1000_fc_rx_pause;
2755 hw->fc.requested_mode = e1000_fc_full;
2759 * Save off the requested flow control mode for use later. Depending
2760 * on the link partner's capabilities, we may or may not use this mode.
2762 hw->fc.current_mode = hw->fc.requested_mode;
2764 e_dbg("After fix-ups FlowControl is now = %x\n",
2765 hw->fc.current_mode);
2767 /* Continue to configure the copper link. */
2768 ret_val = e1000_setup_copper_link_ich8lan(hw);
2772 ew32(FCTTV, hw->fc.pause_time);
2773 if ((hw->phy.type == e1000_phy_82578) ||
2774 (hw->phy.type == e1000_phy_82577)) {
2775 ret_val = hw->phy.ops.write_reg(hw,
2776 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2782 return e1000e_set_fc_watermarks(hw);
2786 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2787 * @hw: pointer to the HW structure
2789 * Configures the kumeran interface to the PHY to wait the appropriate time
2790 * when polling the PHY, then call the generic setup_copper_link to finish
2791 * configuring the copper link.
2793 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2800 ctrl |= E1000_CTRL_SLU;
2801 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2805 * Set the mac to wait the maximum time between each iteration
2806 * and increase the max iterations when polling the phy;
2807 * this fixes erroneous timeouts at 10Mbps.
2809 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
2812 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2817 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2822 switch (hw->phy.type) {
2823 case e1000_phy_igp_3:
2824 ret_val = e1000e_copper_link_setup_igp(hw);
2829 case e1000_phy_82578:
2830 ret_val = e1000e_copper_link_setup_m88(hw);
2834 case e1000_phy_82577:
2835 ret_val = e1000_copper_link_setup_82577(hw);
2840 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2845 reg_data &= ~IFE_PMC_AUTO_MDIX;
2847 switch (hw->phy.mdix) {
2849 reg_data &= ~IFE_PMC_FORCE_MDIX;
2852 reg_data |= IFE_PMC_FORCE_MDIX;
2856 reg_data |= IFE_PMC_AUTO_MDIX;
2859 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2867 return e1000e_setup_copper_link(hw);
2871 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2872 * @hw: pointer to the HW structure
2873 * @speed: pointer to store current link speed
2874 * @duplex: pointer to store the current link duplex
2876 * Calls the generic get_speed_and_duplex to retrieve the current link
2877 * information and then calls the Kumeran lock loss workaround for links at
2880 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2885 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2889 if ((hw->mac.type == e1000_ich8lan) &&
2890 (hw->phy.type == e1000_phy_igp_3) &&
2891 (*speed == SPEED_1000)) {
2892 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2899 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2900 * @hw: pointer to the HW structure
2902 * Work-around for 82566 Kumeran PCS lock loss:
2903 * On link status change (i.e. PCI reset, speed change) and link is up and
2905 * 0) if workaround is optionally disabled do nothing
2906 * 1) wait 1ms for Kumeran link to come up
2907 * 2) check Kumeran Diagnostic register PCS lock loss bit
2908 * 3) if not set the link is locked (all is good), otherwise...
2910 * 5) repeat up to 10 times
2911 * Note: this is only called for IGP3 copper when speed is 1gb.
2913 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2915 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2921 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2925 * Make sure link is up before proceeding. If not just return.
2926 * Attempting this while link is negotiating fouled up link
2929 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2933 for (i = 0; i < 10; i++) {
2934 /* read once to clear */
2935 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2938 /* and again to get new status */
2939 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2943 /* check for PCS lock */
2944 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2947 /* Issue PHY reset */
2948 e1000_phy_hw_reset(hw);
2951 /* Disable GigE link negotiation */
2952 phy_ctrl = er32(PHY_CTRL);
2953 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2954 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2955 ew32(PHY_CTRL, phy_ctrl);
2958 * Call gig speed drop workaround on Gig disable before accessing
2961 e1000e_gig_downshift_workaround_ich8lan(hw);
2963 /* unable to acquire PCS lock */
2964 return -E1000_ERR_PHY;
2968 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2969 * @hw: pointer to the HW structure
2970 * @state: boolean value used to set the current Kumeran workaround state
2972 * If ICH8, set the current Kumeran workaround state (enabled - true
2973 * /disabled - false).
2975 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2978 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2980 if (hw->mac.type != e1000_ich8lan) {
2981 e_dbg("Workaround applies to ICH8 only.\n");
2985 dev_spec->kmrn_lock_loss_workaround_enabled = state;
2989 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2990 * @hw: pointer to the HW structure
2992 * Workaround for 82566 power-down on D3 entry:
2993 * 1) disable gigabit link
2994 * 2) write VR power-down enable
2996 * Continue if successful, else issue LCD reset and repeat
2998 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3004 if (hw->phy.type != e1000_phy_igp_3)
3007 /* Try the workaround twice (if needed) */
3010 reg = er32(PHY_CTRL);
3011 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3012 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3013 ew32(PHY_CTRL, reg);
3016 * Call gig speed drop workaround on Gig disable before
3017 * accessing any PHY registers
3019 if (hw->mac.type == e1000_ich8lan)
3020 e1000e_gig_downshift_workaround_ich8lan(hw);
3022 /* Write VR power-down enable */
3023 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3024 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3025 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3027 /* Read it back and test */
3028 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3029 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3030 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3033 /* Issue PHY reset and repeat at most one more time */
3035 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3041 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3042 * @hw: pointer to the HW structure
3044 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3045 * LPLU, Gig disable, MDIC PHY reset):
3046 * 1) Set Kumeran Near-end loopback
3047 * 2) Clear Kumeran Near-end loopback
3048 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3050 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3055 if ((hw->mac.type != e1000_ich8lan) ||
3056 (hw->phy.type != e1000_phy_igp_3))
3059 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3063 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3064 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3068 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3069 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3074 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3075 * @hw: pointer to the HW structure
3077 * During S0 to Sx transition, it is possible the link remains at gig
3078 * instead of negotiating to a lower speed. Before going to Sx, set
3079 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3082 * Should only be called for applicable parts.
3084 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3088 switch (hw->mac.type) {
3091 case e1000_ich10lan:
3093 phy_ctrl = er32(PHY_CTRL);
3094 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3095 E1000_PHY_CTRL_GBE_DISABLE;
3096 ew32(PHY_CTRL, phy_ctrl);
3098 if (hw->mac.type == e1000_pchlan)
3099 e1000_phy_hw_reset_ich8lan(hw);
3108 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3109 * @hw: pointer to the HW structure
3111 * Return the LED back to the default configuration.
3113 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3115 if (hw->phy.type == e1000_phy_ife)
3116 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3118 ew32(LEDCTL, hw->mac.ledctl_default);
3123 * e1000_led_on_ich8lan - Turn LEDs on
3124 * @hw: pointer to the HW structure
3128 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3130 if (hw->phy.type == e1000_phy_ife)
3131 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3132 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3134 ew32(LEDCTL, hw->mac.ledctl_mode2);
3139 * e1000_led_off_ich8lan - Turn LEDs off
3140 * @hw: pointer to the HW structure
3142 * Turn off the LEDs.
3144 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3146 if (hw->phy.type == e1000_phy_ife)
3147 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3148 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3150 ew32(LEDCTL, hw->mac.ledctl_mode1);
3155 * e1000_setup_led_pchlan - Configures SW controllable LED
3156 * @hw: pointer to the HW structure
3158 * This prepares the SW controllable LED for use.
3160 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3162 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3163 (u16)hw->mac.ledctl_mode1);
3167 * e1000_cleanup_led_pchlan - Restore the default LED operation
3168 * @hw: pointer to the HW structure
3170 * Return the LED back to the default configuration.
3172 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3174 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3175 (u16)hw->mac.ledctl_default);
3179 * e1000_led_on_pchlan - Turn LEDs on
3180 * @hw: pointer to the HW structure
3184 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3186 u16 data = (u16)hw->mac.ledctl_mode2;
3190 * If no link, then turn LED on by setting the invert bit
3191 * for each LED that's mode is "link_up" in ledctl_mode2.
3193 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3194 for (i = 0; i < 3; i++) {
3195 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3196 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3197 E1000_LEDCTL_MODE_LINK_UP)
3199 if (led & E1000_PHY_LED0_IVRT)
3200 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3202 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3206 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3210 * e1000_led_off_pchlan - Turn LEDs off
3211 * @hw: pointer to the HW structure
3213 * Turn off the LEDs.
3215 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3217 u16 data = (u16)hw->mac.ledctl_mode1;
3221 * If no link, then turn LED off by clearing the invert bit
3222 * for each LED that's mode is "link_up" in ledctl_mode1.
3224 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3225 for (i = 0; i < 3; i++) {
3226 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3227 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3228 E1000_LEDCTL_MODE_LINK_UP)
3230 if (led & E1000_PHY_LED0_IVRT)
3231 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3233 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3237 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3241 * e1000_get_cfg_done_ich8lan - Read config done bit
3242 * @hw: pointer to the HW structure
3244 * Read the management control register for the config done bit for
3245 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3246 * to read the config done bit, so an error is *ONLY* logged and returns
3247 * 0. If we were to return with error, EEPROM-less silicon
3248 * would not be able to be reset or change link.
3250 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3254 if (hw->mac.type >= e1000_pchlan) {
3255 u32 status = er32(STATUS);
3257 if (status & E1000_STATUS_PHYRA)
3258 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3260 e_dbg("PHY Reset Asserted not set - needs delay\n");
3263 e1000e_get_cfg_done(hw);
3265 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3266 if ((hw->mac.type != e1000_ich10lan) &&
3267 (hw->mac.type != e1000_pchlan)) {
3268 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3269 (hw->phy.type == e1000_phy_igp_3)) {
3270 e1000e_phy_init_script_igp3(hw);
3273 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3274 /* Maybe we should do a basic PHY config */
3275 e_dbg("EEPROM not present\n");
3276 return -E1000_ERR_CONFIG;
3284 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3285 * @hw: pointer to the HW structure
3287 * In the case of a PHY power down to save power, or to turn off link during a
3288 * driver unload, or wake on lan is not enabled, remove the link.
3290 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3292 /* If the management interface is not enabled, then power down */
3293 if (!(hw->mac.ops.check_mng_mode(hw) ||
3294 hw->phy.ops.check_reset_block(hw)))
3295 e1000_power_down_phy_copper(hw);
3301 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3302 * @hw: pointer to the HW structure
3304 * Clears hardware counters specific to the silicon family and calls
3305 * clear_hw_cntrs_generic to clear all general purpose counters.
3307 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3311 e1000e_clear_hw_cntrs_base(hw);
3327 /* Clear PHY statistics registers */
3328 if ((hw->phy.type == e1000_phy_82578) ||
3329 (hw->phy.type == e1000_phy_82577)) {
3330 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3331 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3332 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3333 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3334 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3335 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3336 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3337 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3338 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3339 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3340 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3341 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3342 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3343 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3347 static struct e1000_mac_operations ich8_mac_ops = {
3348 .id_led_init = e1000e_id_led_init,
3349 .check_mng_mode = e1000_check_mng_mode_ich8lan,
3350 .check_for_link = e1000_check_for_copper_link_ich8lan,
3351 /* cleanup_led dependent on mac type */
3352 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3353 .get_bus_info = e1000_get_bus_info_ich8lan,
3354 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3355 /* led_on dependent on mac type */
3356 /* led_off dependent on mac type */
3357 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3358 .reset_hw = e1000_reset_hw_ich8lan,
3359 .init_hw = e1000_init_hw_ich8lan,
3360 .setup_link = e1000_setup_link_ich8lan,
3361 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3362 /* id_led_init dependent on mac type */
3365 static struct e1000_phy_operations ich8_phy_ops = {
3366 .acquire = e1000_acquire_swflag_ich8lan,
3367 .check_reset_block = e1000_check_reset_block_ich8lan,
3369 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3370 .get_cable_length = e1000e_get_cable_length_igp_2,
3371 .read_reg = e1000e_read_phy_reg_igp,
3372 .release = e1000_release_swflag_ich8lan,
3373 .reset = e1000_phy_hw_reset_ich8lan,
3374 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3375 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3376 .write_reg = e1000e_write_phy_reg_igp,
3379 static struct e1000_nvm_operations ich8_nvm_ops = {
3380 .acquire = e1000_acquire_nvm_ich8lan,
3381 .read = e1000_read_nvm_ich8lan,
3382 .release = e1000_release_nvm_ich8lan,
3383 .update = e1000_update_nvm_checksum_ich8lan,
3384 .valid_led_default = e1000_valid_led_default_ich8lan,
3385 .validate = e1000_validate_nvm_checksum_ich8lan,
3386 .write = e1000_write_nvm_ich8lan,
3389 struct e1000_info e1000_ich8_info = {
3390 .mac = e1000_ich8lan,
3391 .flags = FLAG_HAS_WOL
3393 | FLAG_RX_CSUM_ENABLED
3394 | FLAG_HAS_CTRLEXT_ON_LOAD
3399 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3400 .get_variants = e1000_get_variants_ich8lan,
3401 .mac_ops = &ich8_mac_ops,
3402 .phy_ops = &ich8_phy_ops,
3403 .nvm_ops = &ich8_nvm_ops,
3406 struct e1000_info e1000_ich9_info = {
3407 .mac = e1000_ich9lan,
3408 .flags = FLAG_HAS_JUMBO_FRAMES
3411 | FLAG_RX_CSUM_ENABLED
3412 | FLAG_HAS_CTRLEXT_ON_LOAD
3418 .max_hw_frame_size = DEFAULT_JUMBO,
3419 .get_variants = e1000_get_variants_ich8lan,
3420 .mac_ops = &ich8_mac_ops,
3421 .phy_ops = &ich8_phy_ops,
3422 .nvm_ops = &ich8_nvm_ops,
3425 struct e1000_info e1000_ich10_info = {
3426 .mac = e1000_ich10lan,
3427 .flags = FLAG_HAS_JUMBO_FRAMES
3430 | FLAG_RX_CSUM_ENABLED
3431 | FLAG_HAS_CTRLEXT_ON_LOAD
3437 .max_hw_frame_size = DEFAULT_JUMBO,
3438 .get_variants = e1000_get_variants_ich8lan,
3439 .mac_ops = &ich8_mac_ops,
3440 .phy_ops = &ich8_phy_ops,
3441 .nvm_ops = &ich8_nvm_ops,
3444 struct e1000_info e1000_pch_info = {
3445 .mac = e1000_pchlan,
3446 .flags = FLAG_IS_ICH
3448 | FLAG_RX_CSUM_ENABLED
3449 | FLAG_HAS_CTRLEXT_ON_LOAD
3452 | FLAG_HAS_JUMBO_FRAMES
3453 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3456 .max_hw_frame_size = 4096,
3457 .get_variants = e1000_get_variants_ich8lan,
3458 .mac_ops = &ich8_mac_ops,
3459 .phy_ops = &ich8_phy_ops,
3460 .nvm_ops = &ich8_nvm_ops,