1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
61 #define ICH_FLASH_GFPREG 0x0000
62 #define ICH_FLASH_HSFSTS 0x0004
63 #define ICH_FLASH_HSFCTL 0x0006
64 #define ICH_FLASH_FADDR 0x0008
65 #define ICH_FLASH_FDATA0 0x0010
66 #define ICH_FLASH_PR0 0x0074
68 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
74 #define ICH_CYCLE_READ 0
75 #define ICH_CYCLE_WRITE 2
76 #define ICH_CYCLE_ERASE 3
78 #define FLASH_GFPREG_BASE_MASK 0x1FFF
79 #define FLASH_SECTOR_ADDR_SHIFT 12
81 #define ICH_FLASH_SEG_SIZE_256 256
82 #define ICH_FLASH_SEG_SIZE_4K 4096
83 #define ICH_FLASH_SEG_SIZE_8K 8192
84 #define ICH_FLASH_SEG_SIZE_64K 65536
87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
88 /* FW established a valid mode */
89 #define E1000_ICH_FWSM_FW_VALID 0x00008000
91 #define E1000_ICH_MNG_IAMT_MODE 0x2
93 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
98 #define E1000_ICH_NVM_SIG_WORD 0x13
99 #define E1000_ICH_NVM_SIG_MASK 0xC000
100 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101 #define E1000_ICH_NVM_SIG_VALUE 0x80
103 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
105 #define E1000_FEXTNVM_SW_CONFIG 1
106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
108 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
110 #define E1000_ICH_RAR_ENTRIES 7
112 #define PHY_PAGE_SHIFT 5
113 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
114 ((reg) & MAX_PHY_REG_ADDRESS))
115 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
116 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
118 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
119 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
120 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
122 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
124 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
126 /* SMBus Address Phy Register */
127 #define HV_SMB_ADDR PHY_REG(768, 26)
128 #define HV_SMB_ADDR_PEC_EN 0x0200
129 #define HV_SMB_ADDR_VALID 0x0080
131 /* PHY Power Management Control */
132 #define HV_PM_CTRL PHY_REG(770, 17)
134 /* PHY Low Power Idle Control */
135 #define I82579_LPI_CTRL PHY_REG(772, 20)
136 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
138 /* Strapping Option Register - RO */
139 #define E1000_STRAP 0x0000C
140 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
141 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
143 /* OEM Bits Phy Register */
144 #define HV_OEM_BITS PHY_REG(768, 25)
145 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
146 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
147 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
149 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
150 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
152 /* KMRN Mode Control */
153 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
154 #define HV_KMRN_MDIO_SLOW 0x0400
156 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
157 /* Offset 04h HSFSTS */
158 union ich8_hws_flash_status {
160 u16 flcdone :1; /* bit 0 Flash Cycle Done */
161 u16 flcerr :1; /* bit 1 Flash Cycle Error */
162 u16 dael :1; /* bit 2 Direct Access error Log */
163 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
164 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
165 u16 reserved1 :2; /* bit 13:6 Reserved */
166 u16 reserved2 :6; /* bit 13:6 Reserved */
167 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
168 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
173 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
174 /* Offset 06h FLCTL */
175 union ich8_hws_flash_ctrl {
176 struct ich8_hsflctl {
177 u16 flcgo :1; /* 0 Flash Cycle Go */
178 u16 flcycle :2; /* 2:1 Flash Cycle */
179 u16 reserved :5; /* 7:3 Reserved */
180 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
181 u16 flockdn :6; /* 15:10 Reserved */
186 /* ICH Flash Region Access Permissions */
187 union ich8_hws_flash_regacc {
189 u32 grra :8; /* 0:7 GbE region Read Access */
190 u32 grwa :8; /* 8:15 GbE region Write Access */
191 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
192 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
197 /* ICH Flash Protected Region */
198 union ich8_flash_protected_range {
200 u32 base:13; /* 0:12 Protected Range Base */
201 u32 reserved1:2; /* 13:14 Reserved */
202 u32 rpe:1; /* 15 Read Protection Enable */
203 u32 limit:13; /* 16:28 Protected Range Limit */
204 u32 reserved2:2; /* 29:30 Reserved */
205 u32 wpe:1; /* 31 Write Protection Enable */
210 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
211 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
212 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
213 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
214 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
215 u32 offset, u8 byte);
216 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
218 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
220 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
222 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
223 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
224 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
225 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
226 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
227 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
228 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
229 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
230 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
231 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
232 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
233 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
234 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
235 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
236 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
237 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
238 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
239 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
241 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
243 return readw(hw->flash_address + reg);
246 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
248 return readl(hw->flash_address + reg);
251 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
253 writew(val, hw->flash_address + reg);
256 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
258 writel(val, hw->flash_address + reg);
261 #define er16flash(reg) __er16flash(hw, (reg))
262 #define er32flash(reg) __er32flash(hw, (reg))
263 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
264 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
267 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
268 * @hw: pointer to the HW structure
270 * Initialize family-specific PHY parameters and function pointers.
272 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
274 struct e1000_phy_info *phy = &hw->phy;
279 phy->reset_delay_us = 100;
281 phy->ops.read_reg = e1000_read_phy_reg_hv;
282 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
283 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
284 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
285 phy->ops.write_reg = e1000_write_phy_reg_hv;
286 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
287 phy->ops.power_up = e1000_power_up_phy_copper;
288 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
289 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
292 * The MAC-PHY interconnect may still be in SMBus mode
293 * after Sx->S0. If the manageability engine (ME) is
294 * disabled, then toggle the LANPHYPC Value bit to force
295 * the interconnect to PCIe mode.
297 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
299 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
300 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
303 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
309 * Reset the PHY before any acccess to it. Doing so, ensures that
310 * the PHY is in a known good state before we read/write PHY registers.
311 * The generic reset is sufficient here, because we haven't determined
314 ret_val = e1000e_phy_hw_reset_generic(hw);
318 phy->id = e1000_phy_unknown;
319 ret_val = e1000e_get_phy_id(hw);
322 if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
324 * In case the PHY needs to be in mdio slow mode (eg. 82577),
325 * set slow mode and try to get the PHY id again.
327 ret_val = e1000_set_mdio_slow_mode_hv(hw);
330 ret_val = e1000e_get_phy_id(hw);
334 phy->type = e1000e_get_phy_type_from_id(phy->id);
337 case e1000_phy_82577:
338 case e1000_phy_82579:
339 phy->ops.check_polarity = e1000_check_polarity_82577;
340 phy->ops.force_speed_duplex =
341 e1000_phy_force_speed_duplex_82577;
342 phy->ops.get_cable_length = e1000_get_cable_length_82577;
343 phy->ops.get_info = e1000_get_phy_info_82577;
344 phy->ops.commit = e1000e_phy_sw_reset;
346 case e1000_phy_82578:
347 phy->ops.check_polarity = e1000_check_polarity_m88;
348 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
349 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
350 phy->ops.get_info = e1000e_get_phy_info_m88;
353 ret_val = -E1000_ERR_PHY;
362 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
363 * @hw: pointer to the HW structure
365 * Initialize family-specific PHY parameters and function pointers.
367 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
369 struct e1000_phy_info *phy = &hw->phy;
374 phy->reset_delay_us = 100;
376 phy->ops.power_up = e1000_power_up_phy_copper;
377 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
380 * We may need to do this twice - once for IGP and if that fails,
381 * we'll set BM func pointers and try again
383 ret_val = e1000e_determine_phy_address(hw);
385 phy->ops.write_reg = e1000e_write_phy_reg_bm;
386 phy->ops.read_reg = e1000e_read_phy_reg_bm;
387 ret_val = e1000e_determine_phy_address(hw);
389 e_dbg("Cannot determine PHY addr. Erroring out\n");
395 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
398 ret_val = e1000e_get_phy_id(hw);
405 case IGP03E1000_E_PHY_ID:
406 phy->type = e1000_phy_igp_3;
407 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
408 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
409 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
410 phy->ops.get_info = e1000e_get_phy_info_igp;
411 phy->ops.check_polarity = e1000_check_polarity_igp;
412 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
415 case IFE_PLUS_E_PHY_ID:
417 phy->type = e1000_phy_ife;
418 phy->autoneg_mask = E1000_ALL_NOT_GIG;
419 phy->ops.get_info = e1000_get_phy_info_ife;
420 phy->ops.check_polarity = e1000_check_polarity_ife;
421 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
423 case BME1000_E_PHY_ID:
424 phy->type = e1000_phy_bm;
425 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
426 phy->ops.read_reg = e1000e_read_phy_reg_bm;
427 phy->ops.write_reg = e1000e_write_phy_reg_bm;
428 phy->ops.commit = e1000e_phy_sw_reset;
429 phy->ops.get_info = e1000e_get_phy_info_m88;
430 phy->ops.check_polarity = e1000_check_polarity_m88;
431 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
434 return -E1000_ERR_PHY;
442 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
443 * @hw: pointer to the HW structure
445 * Initialize family-specific NVM parameters and function
448 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
450 struct e1000_nvm_info *nvm = &hw->nvm;
451 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
452 u32 gfpreg, sector_base_addr, sector_end_addr;
455 /* Can't read flash registers if the register set isn't mapped. */
456 if (!hw->flash_address) {
457 e_dbg("ERROR: Flash registers not mapped\n");
458 return -E1000_ERR_CONFIG;
461 nvm->type = e1000_nvm_flash_sw;
463 gfpreg = er32flash(ICH_FLASH_GFPREG);
466 * sector_X_addr is a "sector"-aligned address (4096 bytes)
467 * Add 1 to sector_end_addr since this sector is included in
470 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
471 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
473 /* flash_base_addr is byte-aligned */
474 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
477 * find total size of the NVM, then cut in half since the total
478 * size represents two separate NVM banks.
480 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
481 << FLASH_SECTOR_ADDR_SHIFT;
482 nvm->flash_bank_size /= 2;
483 /* Adjust to word count */
484 nvm->flash_bank_size /= sizeof(u16);
486 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
488 /* Clear shadow ram */
489 for (i = 0; i < nvm->word_size; i++) {
490 dev_spec->shadow_ram[i].modified = false;
491 dev_spec->shadow_ram[i].value = 0xFFFF;
498 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
499 * @hw: pointer to the HW structure
501 * Initialize family-specific MAC parameters and function
504 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
506 struct e1000_hw *hw = &adapter->hw;
507 struct e1000_mac_info *mac = &hw->mac;
509 /* Set media type function pointer */
510 hw->phy.media_type = e1000_media_type_copper;
512 /* Set mta register count */
513 mac->mta_reg_count = 32;
514 /* Set rar entry count */
515 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
516 if (mac->type == e1000_ich8lan)
517 mac->rar_entry_count--;
519 mac->has_fwsm = true;
520 /* ARC subsystem not supported */
521 mac->arc_subsystem_valid = false;
522 /* Adaptive IFS supported */
523 mac->adaptive_ifs = true;
530 /* check management mode */
531 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
533 mac->ops.id_led_init = e1000e_id_led_init;
535 mac->ops.setup_led = e1000e_setup_led_generic;
537 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
538 /* turn on/off LED */
539 mac->ops.led_on = e1000_led_on_ich8lan;
540 mac->ops.led_off = e1000_led_off_ich8lan;
544 /* check management mode */
545 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
547 mac->ops.id_led_init = e1000_id_led_init_pchlan;
549 mac->ops.setup_led = e1000_setup_led_pchlan;
551 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
552 /* turn on/off LED */
553 mac->ops.led_on = e1000_led_on_pchlan;
554 mac->ops.led_off = e1000_led_off_pchlan;
560 /* Enable PCS Lock-loss workaround for ICH8 */
561 if (mac->type == e1000_ich8lan)
562 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
564 /* Disable PHY configuration by hardware, config by software */
565 if (mac->type == e1000_pch2lan) {
566 u32 extcnf_ctrl = er32(EXTCNF_CTRL);
568 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
569 ew32(EXTCNF_CTRL, extcnf_ctrl);
576 * e1000_set_eee_pchlan - Enable/disable EEE support
577 * @hw: pointer to the HW structure
579 * Enable/disable EEE based on setting in dev_spec structure. The bits in
580 * the LPI Control register will remain set only if/when link is up.
582 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
587 if (hw->phy.type != e1000_phy_82579)
590 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
594 if (hw->dev_spec.ich8lan.eee_disable)
595 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
597 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
599 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
605 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
606 * @hw: pointer to the HW structure
608 * Checks to see of the link status of the hardware has changed. If a
609 * change in link status has been detected, then we read the PHY registers
610 * to get the current speed/duplex if link exists.
612 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
614 struct e1000_mac_info *mac = &hw->mac;
619 * We only want to go out to the PHY registers to see if Auto-Neg
620 * has completed and/or if our link status has changed. The
621 * get_link_status flag is set upon receiving a Link Status
622 * Change or Rx Sequence Error interrupt.
624 if (!mac->get_link_status) {
630 * First we want to see if the MII Status Register reports
631 * link. If so, then we want to get the current speed/duplex
634 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
638 if (hw->mac.type == e1000_pchlan) {
639 ret_val = e1000_k1_gig_workaround_hv(hw, link);
645 goto out; /* No link detected */
647 mac->get_link_status = false;
649 if (hw->phy.type == e1000_phy_82578) {
650 ret_val = e1000_link_stall_workaround_hv(hw);
656 * Check if there was DownShift, must be checked
657 * immediately after link-up
659 e1000e_check_downshift(hw);
661 /* Enable/Disable EEE after link up */
662 ret_val = e1000_set_eee_pchlan(hw);
667 * If we are forcing speed/duplex, then we simply return since
668 * we have already determined whether we have link or not.
671 ret_val = -E1000_ERR_CONFIG;
676 * Auto-Neg is enabled. Auto Speed Detection takes care
677 * of MAC speed/duplex configuration. So we only need to
678 * configure Collision Distance in the MAC.
680 e1000e_config_collision_dist(hw);
683 * Configure Flow Control now that Auto-Neg has completed.
684 * First, we need to restore the desired flow control
685 * settings because we may have had to re-autoneg with a
686 * different link partner.
688 ret_val = e1000e_config_fc_after_link_up(hw);
690 e_dbg("Error configuring flow control\n");
696 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
698 struct e1000_hw *hw = &adapter->hw;
701 rc = e1000_init_mac_params_ich8lan(adapter);
705 rc = e1000_init_nvm_params_ich8lan(hw);
709 switch (hw->mac.type) {
713 rc = e1000_init_phy_params_ich8lan(hw);
717 rc = e1000_init_phy_params_pchlan(hw);
725 if (adapter->hw.phy.type == e1000_phy_ife) {
726 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
727 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
730 if ((adapter->hw.mac.type == e1000_ich8lan) &&
731 (adapter->hw.phy.type == e1000_phy_igp_3))
732 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
734 /* Disable EEE by default until IEEE802.3az spec is finalized */
735 if (adapter->flags2 & FLAG2_HAS_EEE)
736 adapter->hw.dev_spec.ich8lan.eee_disable = true;
741 static DEFINE_MUTEX(nvm_mutex);
744 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
745 * @hw: pointer to the HW structure
747 * Acquires the mutex for performing NVM operations.
749 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
751 mutex_lock(&nvm_mutex);
757 * e1000_release_nvm_ich8lan - Release NVM mutex
758 * @hw: pointer to the HW structure
760 * Releases the mutex used while performing NVM operations.
762 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
764 mutex_unlock(&nvm_mutex);
767 static DEFINE_MUTEX(swflag_mutex);
770 * e1000_acquire_swflag_ich8lan - Acquire software control flag
771 * @hw: pointer to the HW structure
773 * Acquires the software control flag for performing PHY and select
776 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
778 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
781 mutex_lock(&swflag_mutex);
784 extcnf_ctrl = er32(EXTCNF_CTRL);
785 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
793 e_dbg("SW/FW/HW has locked the resource for too long.\n");
794 ret_val = -E1000_ERR_CONFIG;
798 timeout = SW_FLAG_TIMEOUT;
800 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
801 ew32(EXTCNF_CTRL, extcnf_ctrl);
804 extcnf_ctrl = er32(EXTCNF_CTRL);
805 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
813 e_dbg("Failed to acquire the semaphore.\n");
814 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
815 ew32(EXTCNF_CTRL, extcnf_ctrl);
816 ret_val = -E1000_ERR_CONFIG;
822 mutex_unlock(&swflag_mutex);
828 * e1000_release_swflag_ich8lan - Release software control flag
829 * @hw: pointer to the HW structure
831 * Releases the software control flag for performing PHY and select
834 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
838 extcnf_ctrl = er32(EXTCNF_CTRL);
839 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
840 ew32(EXTCNF_CTRL, extcnf_ctrl);
842 mutex_unlock(&swflag_mutex);
846 * e1000_check_mng_mode_ich8lan - Checks management mode
847 * @hw: pointer to the HW structure
849 * This checks if the adapter has any manageability enabled.
850 * This is a function pointer entry point only called by read/write
851 * routines for the PHY and NVM parts.
853 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
858 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
859 ((fwsm & E1000_FWSM_MODE_MASK) ==
860 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
864 * e1000_check_mng_mode_pchlan - Checks management mode
865 * @hw: pointer to the HW structure
867 * This checks if the adapter has iAMT enabled.
868 * This is a function pointer entry point only called by read/write
869 * routines for the PHY and NVM parts.
871 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
876 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
877 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
881 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
882 * @hw: pointer to the HW structure
884 * Checks if firmware is blocking the reset of the PHY.
885 * This is a function pointer entry point only called by
888 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
894 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
898 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
899 * @hw: pointer to the HW structure
901 * SW should configure the LCD from the NVM extended configuration region
902 * as a workaround for certain parts.
904 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
906 struct e1000_adapter *adapter = hw->adapter;
907 struct e1000_phy_info *phy = &hw->phy;
908 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
910 u16 word_addr, reg_data, reg_addr, phy_page = 0;
913 * Initialize the PHY from the NVM on ICH platforms. This
914 * is needed due to an issue where the NVM configuration is
915 * not properly autoloaded after power transitions.
916 * Therefore, after each PHY reset, we will load the
917 * configuration data out of the NVM manually.
919 switch (hw->mac.type) {
921 if (phy->type != e1000_phy_igp_3)
924 if (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) {
925 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
931 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
937 ret_val = hw->phy.ops.acquire(hw);
941 data = er32(FEXTNVM);
942 if (!(data & sw_cfg_mask))
946 * Make sure HW does not configure LCD from PHY
947 * extended configuration before SW configuration
949 data = er32(EXTCNF_CTRL);
950 if (!(hw->mac.type == e1000_pch2lan)) {
951 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
955 cnf_size = er32(EXTCNF_SIZE);
956 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
957 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
961 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
962 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
964 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
965 ((hw->mac.type == e1000_pchlan) ||
966 (hw->mac.type == e1000_pch2lan))) {
968 * HW configures the SMBus address and LEDs when the
969 * OEM and LCD Write Enable bits are set in the NVM.
970 * When both NVM bits are cleared, SW will configure
974 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
975 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
976 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
977 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
983 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
989 /* Configure LCD from extended configuration region. */
991 /* cnf_base_addr is in DWORD */
992 word_addr = (u16)(cnf_base_addr << 1);
994 for (i = 0; i < cnf_size; i++) {
995 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1000 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1005 /* Save off the PHY page for future writes. */
1006 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1007 phy_page = reg_data;
1011 reg_addr &= PHY_REG_MASK;
1012 reg_addr |= phy_page;
1014 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1021 hw->phy.ops.release(hw);
1026 * e1000_k1_gig_workaround_hv - K1 Si workaround
1027 * @hw: pointer to the HW structure
1028 * @link: link up bool flag
1030 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1031 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1032 * If link is down, the function will restore the default K1 setting located
1035 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1039 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1041 if (hw->mac.type != e1000_pchlan)
1044 /* Wrap the whole flow with the sw flag */
1045 ret_val = hw->phy.ops.acquire(hw);
1049 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1051 if (hw->phy.type == e1000_phy_82578) {
1052 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1057 status_reg &= BM_CS_STATUS_LINK_UP |
1058 BM_CS_STATUS_RESOLVED |
1059 BM_CS_STATUS_SPEED_MASK;
1061 if (status_reg == (BM_CS_STATUS_LINK_UP |
1062 BM_CS_STATUS_RESOLVED |
1063 BM_CS_STATUS_SPEED_1000))
1067 if (hw->phy.type == e1000_phy_82577) {
1068 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1073 status_reg &= HV_M_STATUS_LINK_UP |
1074 HV_M_STATUS_AUTONEG_COMPLETE |
1075 HV_M_STATUS_SPEED_MASK;
1077 if (status_reg == (HV_M_STATUS_LINK_UP |
1078 HV_M_STATUS_AUTONEG_COMPLETE |
1079 HV_M_STATUS_SPEED_1000))
1083 /* Link stall fix for link up */
1084 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1090 /* Link stall fix for link down */
1091 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1097 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1100 hw->phy.ops.release(hw);
1106 * e1000_configure_k1_ich8lan - Configure K1 power state
1107 * @hw: pointer to the HW structure
1108 * @enable: K1 state to configure
1110 * Configure the K1 power state based on the provided parameter.
1111 * Assumes semaphore already acquired.
1113 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1115 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1123 ret_val = e1000e_read_kmrn_reg_locked(hw,
1124 E1000_KMRNCTRLSTA_K1_CONFIG,
1130 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1132 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1134 ret_val = e1000e_write_kmrn_reg_locked(hw,
1135 E1000_KMRNCTRLSTA_K1_CONFIG,
1141 ctrl_ext = er32(CTRL_EXT);
1142 ctrl_reg = er32(CTRL);
1144 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1145 reg |= E1000_CTRL_FRCSPD;
1148 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1150 ew32(CTRL, ctrl_reg);
1151 ew32(CTRL_EXT, ctrl_ext);
1159 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1160 * @hw: pointer to the HW structure
1161 * @d0_state: boolean if entering d0 or d3 device state
1163 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1164 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1165 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1167 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1173 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1176 ret_val = hw->phy.ops.acquire(hw);
1180 if (!(hw->mac.type == e1000_pch2lan)) {
1181 mac_reg = er32(EXTCNF_CTRL);
1182 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1186 mac_reg = er32(FEXTNVM);
1187 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1190 mac_reg = er32(PHY_CTRL);
1192 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1196 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1199 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1200 oem_reg |= HV_OEM_BITS_GBE_DIS;
1202 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1203 oem_reg |= HV_OEM_BITS_LPLU;
1205 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1206 oem_reg |= HV_OEM_BITS_GBE_DIS;
1208 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1209 oem_reg |= HV_OEM_BITS_LPLU;
1211 /* Restart auto-neg to activate the bits */
1212 if (!e1000_check_reset_block(hw))
1213 oem_reg |= HV_OEM_BITS_RESTART_AN;
1214 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1217 hw->phy.ops.release(hw);
1224 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1225 * @hw: pointer to the HW structure
1227 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1232 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1236 data |= HV_KMRN_MDIO_SLOW;
1238 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1244 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1245 * done after every PHY reset.
1247 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1252 if (hw->mac.type != e1000_pchlan)
1255 /* Set MDIO slow mode before any other MDIO access */
1256 if (hw->phy.type == e1000_phy_82577) {
1257 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1262 if (((hw->phy.type == e1000_phy_82577) &&
1263 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1264 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1265 /* Disable generation of early preamble */
1266 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1270 /* Preamble tuning for SSC */
1271 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1276 if (hw->phy.type == e1000_phy_82578) {
1278 * Return registers to default by doing a soft reset then
1279 * writing 0x3140 to the control register.
1281 if (hw->phy.revision < 2) {
1282 e1000e_phy_sw_reset(hw);
1283 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1288 ret_val = hw->phy.ops.acquire(hw);
1293 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1294 hw->phy.ops.release(hw);
1299 * Configure the K1 Si workaround during phy reset assuming there is
1300 * link so that it disables K1 if link is in 1Gbps.
1302 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1306 /* Workaround for link disconnects on a busy hub in half duplex */
1307 ret_val = hw->phy.ops.acquire(hw);
1310 ret_val = hw->phy.ops.read_reg_locked(hw,
1311 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1315 ret_val = hw->phy.ops.write_reg_locked(hw,
1316 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1319 hw->phy.ops.release(hw);
1325 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1326 * @hw: pointer to the HW structure
1328 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1333 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1334 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1335 mac_reg = er32(RAL(i));
1336 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1337 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1338 mac_reg = er32(RAH(i));
1339 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1340 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1344 static u32 e1000_calc_rx_da_crc(u8 mac[])
1346 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
1347 u32 i, j, mask, crc;
1350 for (i = 0; i < 6; i++) {
1352 for (j = 8; j > 0; j--) {
1353 mask = (crc & 1) * (-1);
1354 crc = (crc >> 1) ^ (poly & mask);
1361 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1363 * @hw: pointer to the HW structure
1364 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1366 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1373 if (hw->mac.type != e1000_pch2lan)
1376 /* disable Rx path while enabling/disabling workaround */
1377 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1378 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1384 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1385 * SHRAL/H) and initial CRC values to the MAC
1387 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1388 u8 mac_addr[ETH_ALEN] = {0};
1389 u32 addr_high, addr_low;
1391 addr_high = er32(RAH(i));
1392 if (!(addr_high & E1000_RAH_AV))
1394 addr_low = er32(RAL(i));
1395 mac_addr[0] = (addr_low & 0xFF);
1396 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1397 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1398 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1399 mac_addr[4] = (addr_high & 0xFF);
1400 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1403 e1000_calc_rx_da_crc(mac_addr));
1406 /* Write Rx addresses to the PHY */
1407 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1409 /* Enable jumbo frame workaround in the MAC */
1410 mac_reg = er32(FFLT_DBG);
1411 mac_reg &= ~(1 << 14);
1412 mac_reg |= (7 << 15);
1413 ew32(FFLT_DBG, mac_reg);
1415 mac_reg = er32(RCTL);
1416 mac_reg |= E1000_RCTL_SECRC;
1417 ew32(RCTL, mac_reg);
1419 ret_val = e1000e_read_kmrn_reg(hw,
1420 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1424 ret_val = e1000e_write_kmrn_reg(hw,
1425 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1429 ret_val = e1000e_read_kmrn_reg(hw,
1430 E1000_KMRNCTRLSTA_HD_CTRL,
1434 data &= ~(0xF << 8);
1436 ret_val = e1000e_write_kmrn_reg(hw,
1437 E1000_KMRNCTRLSTA_HD_CTRL,
1442 /* Enable jumbo frame workaround in the PHY */
1443 e1e_rphy(hw, PHY_REG(769, 20), &data);
1444 ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
1447 e1e_rphy(hw, PHY_REG(769, 23), &data);
1448 data &= ~(0x7F << 5);
1449 data |= (0x37 << 5);
1450 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1453 e1e_rphy(hw, PHY_REG(769, 16), &data);
1456 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1459 e1e_rphy(hw, PHY_REG(776, 20), &data);
1460 data &= ~(0x3FF << 2);
1461 data |= (0x1A << 2);
1462 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1465 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1468 e1e_rphy(hw, HV_PM_CTRL, &data);
1469 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1473 /* Write MAC register values back to h/w defaults */
1474 mac_reg = er32(FFLT_DBG);
1475 mac_reg &= ~(0xF << 14);
1476 ew32(FFLT_DBG, mac_reg);
1478 mac_reg = er32(RCTL);
1479 mac_reg &= ~E1000_RCTL_SECRC;
1480 ew32(FFLT_DBG, mac_reg);
1482 ret_val = e1000e_read_kmrn_reg(hw,
1483 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1487 ret_val = e1000e_write_kmrn_reg(hw,
1488 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1492 ret_val = e1000e_read_kmrn_reg(hw,
1493 E1000_KMRNCTRLSTA_HD_CTRL,
1497 data &= ~(0xF << 8);
1499 ret_val = e1000e_write_kmrn_reg(hw,
1500 E1000_KMRNCTRLSTA_HD_CTRL,
1505 /* Write PHY register values back to h/w defaults */
1506 e1e_rphy(hw, PHY_REG(769, 20), &data);
1507 ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
1510 e1e_rphy(hw, PHY_REG(769, 23), &data);
1511 data &= ~(0x7F << 5);
1512 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1515 e1e_rphy(hw, PHY_REG(769, 16), &data);
1518 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1521 e1e_rphy(hw, PHY_REG(776, 20), &data);
1522 data &= ~(0x3FF << 2);
1524 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1527 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1530 e1e_rphy(hw, HV_PM_CTRL, &data);
1531 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1536 /* re-enable Rx path after enabling/disabling workaround */
1537 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1544 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1545 * done after every PHY reset.
1547 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1551 if (hw->mac.type != e1000_pch2lan)
1554 /* Set MDIO slow mode before any other MDIO access */
1555 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1562 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1563 * @hw: pointer to the HW structure
1565 * Check the appropriate indication the MAC has finished configuring the
1566 * PHY after a software reset.
1568 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1570 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1572 /* Wait for basic configuration completes before proceeding */
1574 data = er32(STATUS);
1575 data &= E1000_STATUS_LAN_INIT_DONE;
1577 } while ((!data) && --loop);
1580 * If basic configuration is incomplete before the above loop
1581 * count reaches 0, loading the configuration from NVM will
1582 * leave the PHY in a bad state possibly resulting in no link.
1585 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1587 /* Clear the Init Done bit for the next init event */
1588 data = er32(STATUS);
1589 data &= ~E1000_STATUS_LAN_INIT_DONE;
1594 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1595 * @hw: pointer to the HW structure
1597 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1602 if (e1000_check_reset_block(hw))
1605 /* Perform any necessary post-reset workarounds */
1606 switch (hw->mac.type) {
1608 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1613 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1621 /* Dummy read to clear the phy wakeup bit after lcd reset */
1622 if (hw->mac.type >= e1000_pchlan)
1623 e1e_rphy(hw, BM_WUC, ®);
1625 /* Configure the LCD with the extended configuration region in NVM */
1626 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1630 /* Configure the LCD with the OEM bits in NVM */
1631 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1638 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1639 * @hw: pointer to the HW structure
1642 * This is a function pointer entry point called by drivers
1643 * or other shared routines.
1645 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1649 ret_val = e1000e_phy_hw_reset_generic(hw);
1653 ret_val = e1000_post_phy_reset_ich8lan(hw);
1660 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1661 * @hw: pointer to the HW structure
1662 * @active: true to enable LPLU, false to disable
1664 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1665 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1666 * the phy speed. This function will manually set the LPLU bit and restart
1667 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1668 * since it configures the same bit.
1670 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1675 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1680 oem_reg |= HV_OEM_BITS_LPLU;
1682 oem_reg &= ~HV_OEM_BITS_LPLU;
1684 oem_reg |= HV_OEM_BITS_RESTART_AN;
1685 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1692 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1693 * @hw: pointer to the HW structure
1694 * @active: true to enable LPLU, false to disable
1696 * Sets the LPLU D0 state according to the active flag. When
1697 * activating LPLU this function also disables smart speed
1698 * and vice versa. LPLU will not be activated unless the
1699 * device autonegotiation advertisement meets standards of
1700 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1701 * This is a function pointer entry point only called by
1702 * PHY setup routines.
1704 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1706 struct e1000_phy_info *phy = &hw->phy;
1711 if (phy->type == e1000_phy_ife)
1714 phy_ctrl = er32(PHY_CTRL);
1717 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1718 ew32(PHY_CTRL, phy_ctrl);
1720 if (phy->type != e1000_phy_igp_3)
1724 * Call gig speed drop workaround on LPLU before accessing
1727 if (hw->mac.type == e1000_ich8lan)
1728 e1000e_gig_downshift_workaround_ich8lan(hw);
1730 /* When LPLU is enabled, we should disable SmartSpeed */
1731 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1732 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1733 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1737 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1738 ew32(PHY_CTRL, phy_ctrl);
1740 if (phy->type != e1000_phy_igp_3)
1744 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1745 * during Dx states where the power conservation is most
1746 * important. During driver activity we should enable
1747 * SmartSpeed, so performance is maintained.
1749 if (phy->smart_speed == e1000_smart_speed_on) {
1750 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1755 data |= IGP01E1000_PSCFR_SMART_SPEED;
1756 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1760 } else if (phy->smart_speed == e1000_smart_speed_off) {
1761 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1766 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1767 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1778 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1779 * @hw: pointer to the HW structure
1780 * @active: true to enable LPLU, false to disable
1782 * Sets the LPLU D3 state according to the active flag. When
1783 * activating LPLU this function also disables smart speed
1784 * and vice versa. LPLU will not be activated unless the
1785 * device autonegotiation advertisement meets standards of
1786 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1787 * This is a function pointer entry point only called by
1788 * PHY setup routines.
1790 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1792 struct e1000_phy_info *phy = &hw->phy;
1797 phy_ctrl = er32(PHY_CTRL);
1800 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1801 ew32(PHY_CTRL, phy_ctrl);
1803 if (phy->type != e1000_phy_igp_3)
1807 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1808 * during Dx states where the power conservation is most
1809 * important. During driver activity we should enable
1810 * SmartSpeed, so performance is maintained.
1812 if (phy->smart_speed == e1000_smart_speed_on) {
1813 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1818 data |= IGP01E1000_PSCFR_SMART_SPEED;
1819 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1823 } else if (phy->smart_speed == e1000_smart_speed_off) {
1824 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1829 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1830 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1835 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1836 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1837 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1838 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1839 ew32(PHY_CTRL, phy_ctrl);
1841 if (phy->type != e1000_phy_igp_3)
1845 * Call gig speed drop workaround on LPLU before accessing
1848 if (hw->mac.type == e1000_ich8lan)
1849 e1000e_gig_downshift_workaround_ich8lan(hw);
1851 /* When LPLU is enabled, we should disable SmartSpeed */
1852 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1856 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1857 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1864 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1865 * @hw: pointer to the HW structure
1866 * @bank: pointer to the variable that returns the active bank
1868 * Reads signature byte from the NVM using the flash access registers.
1869 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1871 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1874 struct e1000_nvm_info *nvm = &hw->nvm;
1875 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1876 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1880 switch (hw->mac.type) {
1884 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1885 E1000_EECD_SEC1VAL_VALID_MASK) {
1886 if (eecd & E1000_EECD_SEC1VAL)
1893 e_dbg("Unable to determine valid NVM bank via EEC - "
1894 "reading flash signature\n");
1897 /* set bank to 0 in case flash read fails */
1901 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1905 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1906 E1000_ICH_NVM_SIG_VALUE) {
1912 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1917 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1918 E1000_ICH_NVM_SIG_VALUE) {
1923 e_dbg("ERROR: No valid NVM bank present\n");
1924 return -E1000_ERR_NVM;
1931 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1932 * @hw: pointer to the HW structure
1933 * @offset: The offset (in bytes) of the word(s) to read.
1934 * @words: Size of data to read in words
1935 * @data: Pointer to the word(s) to read at offset.
1937 * Reads a word(s) from the NVM using the flash access registers.
1939 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1942 struct e1000_nvm_info *nvm = &hw->nvm;
1943 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1949 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1951 e_dbg("nvm parameter(s) out of bounds\n");
1952 ret_val = -E1000_ERR_NVM;
1956 nvm->ops.acquire(hw);
1958 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1960 e_dbg("Could not detect valid bank, assuming bank 0\n");
1964 act_offset = (bank) ? nvm->flash_bank_size : 0;
1965 act_offset += offset;
1968 for (i = 0; i < words; i++) {
1969 if ((dev_spec->shadow_ram) &&
1970 (dev_spec->shadow_ram[offset+i].modified)) {
1971 data[i] = dev_spec->shadow_ram[offset+i].value;
1973 ret_val = e1000_read_flash_word_ich8lan(hw,
1982 nvm->ops.release(hw);
1986 e_dbg("NVM read error: %d\n", ret_val);
1992 * e1000_flash_cycle_init_ich8lan - Initialize flash
1993 * @hw: pointer to the HW structure
1995 * This function does initial flash setup so that a new read/write/erase cycle
1998 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2000 union ich8_hws_flash_status hsfsts;
2001 s32 ret_val = -E1000_ERR_NVM;
2004 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2006 /* Check if the flash descriptor is valid */
2007 if (hsfsts.hsf_status.fldesvalid == 0) {
2008 e_dbg("Flash descriptor invalid. "
2009 "SW Sequencing must be used.\n");
2010 return -E1000_ERR_NVM;
2013 /* Clear FCERR and DAEL in hw status by writing 1 */
2014 hsfsts.hsf_status.flcerr = 1;
2015 hsfsts.hsf_status.dael = 1;
2017 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2020 * Either we should have a hardware SPI cycle in progress
2021 * bit to check against, in order to start a new cycle or
2022 * FDONE bit should be changed in the hardware so that it
2023 * is 1 after hardware reset, which can then be used as an
2024 * indication whether a cycle is in progress or has been
2028 if (hsfsts.hsf_status.flcinprog == 0) {
2030 * There is no cycle running at present,
2031 * so we can start a cycle.
2032 * Begin by setting Flash Cycle Done.
2034 hsfsts.hsf_status.flcdone = 1;
2035 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2039 * Otherwise poll for sometime so the current
2040 * cycle has a chance to end before giving up.
2042 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2043 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2044 if (hsfsts.hsf_status.flcinprog == 0) {
2052 * Successful in waiting for previous cycle to timeout,
2053 * now set the Flash Cycle Done.
2055 hsfsts.hsf_status.flcdone = 1;
2056 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2058 e_dbg("Flash controller busy, cannot get access\n");
2066 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2067 * @hw: pointer to the HW structure
2068 * @timeout: maximum time to wait for completion
2070 * This function starts a flash cycle and waits for its completion.
2072 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2074 union ich8_hws_flash_ctrl hsflctl;
2075 union ich8_hws_flash_status hsfsts;
2076 s32 ret_val = -E1000_ERR_NVM;
2079 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2080 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2081 hsflctl.hsf_ctrl.flcgo = 1;
2082 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2084 /* wait till FDONE bit is set to 1 */
2086 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2087 if (hsfsts.hsf_status.flcdone == 1)
2090 } while (i++ < timeout);
2092 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2099 * e1000_read_flash_word_ich8lan - Read word from flash
2100 * @hw: pointer to the HW structure
2101 * @offset: offset to data location
2102 * @data: pointer to the location for storing the data
2104 * Reads the flash word at offset into data. Offset is converted
2105 * to bytes before read.
2107 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2110 /* Must convert offset into bytes. */
2113 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2117 * e1000_read_flash_byte_ich8lan - Read byte from flash
2118 * @hw: pointer to the HW structure
2119 * @offset: The offset of the byte to read.
2120 * @data: Pointer to a byte to store the value read.
2122 * Reads a single byte from the NVM using the flash access registers.
2124 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2130 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2140 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2141 * @hw: pointer to the HW structure
2142 * @offset: The offset (in bytes) of the byte or word to read.
2143 * @size: Size of data to read, 1=byte 2=word
2144 * @data: Pointer to the word to store the value read.
2146 * Reads a byte or word from the NVM using the flash access registers.
2148 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2151 union ich8_hws_flash_status hsfsts;
2152 union ich8_hws_flash_ctrl hsflctl;
2153 u32 flash_linear_addr;
2155 s32 ret_val = -E1000_ERR_NVM;
2158 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2159 return -E1000_ERR_NVM;
2161 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2162 hw->nvm.flash_base_addr;
2167 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2171 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2172 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2173 hsflctl.hsf_ctrl.fldbcount = size - 1;
2174 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2175 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2177 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2179 ret_val = e1000_flash_cycle_ich8lan(hw,
2180 ICH_FLASH_READ_COMMAND_TIMEOUT);
2183 * Check if FCERR is set to 1, if set to 1, clear it
2184 * and try the whole sequence a few more times, else
2185 * read in (shift in) the Flash Data0, the order is
2186 * least significant byte first msb to lsb
2189 flash_data = er32flash(ICH_FLASH_FDATA0);
2191 *data = (u8)(flash_data & 0x000000FF);
2192 } else if (size == 2) {
2193 *data = (u16)(flash_data & 0x0000FFFF);
2198 * If we've gotten here, then things are probably
2199 * completely hosed, but if the error condition is
2200 * detected, it won't hurt to give it another try...
2201 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2203 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2204 if (hsfsts.hsf_status.flcerr == 1) {
2205 /* Repeat for some time before giving up. */
2207 } else if (hsfsts.hsf_status.flcdone == 0) {
2208 e_dbg("Timeout error - flash cycle "
2209 "did not complete.\n");
2213 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2219 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2220 * @hw: pointer to the HW structure
2221 * @offset: The offset (in bytes) of the word(s) to write.
2222 * @words: Size of data to write in words
2223 * @data: Pointer to the word(s) to write at offset.
2225 * Writes a byte or word to the NVM using the flash access registers.
2227 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2230 struct e1000_nvm_info *nvm = &hw->nvm;
2231 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2234 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2236 e_dbg("nvm parameter(s) out of bounds\n");
2237 return -E1000_ERR_NVM;
2240 nvm->ops.acquire(hw);
2242 for (i = 0; i < words; i++) {
2243 dev_spec->shadow_ram[offset+i].modified = true;
2244 dev_spec->shadow_ram[offset+i].value = data[i];
2247 nvm->ops.release(hw);
2253 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2254 * @hw: pointer to the HW structure
2256 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2257 * which writes the checksum to the shadow ram. The changes in the shadow
2258 * ram are then committed to the EEPROM by processing each bank at a time
2259 * checking for the modified bit and writing only the pending changes.
2260 * After a successful commit, the shadow ram is cleared and is ready for
2263 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2265 struct e1000_nvm_info *nvm = &hw->nvm;
2266 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2267 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2271 ret_val = e1000e_update_nvm_checksum_generic(hw);
2275 if (nvm->type != e1000_nvm_flash_sw)
2278 nvm->ops.acquire(hw);
2281 * We're writing to the opposite bank so if we're on bank 1,
2282 * write to bank 0 etc. We also need to erase the segment that
2283 * is going to be written
2285 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2287 e_dbg("Could not detect valid bank, assuming bank 0\n");
2292 new_bank_offset = nvm->flash_bank_size;
2293 old_bank_offset = 0;
2294 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2298 old_bank_offset = nvm->flash_bank_size;
2299 new_bank_offset = 0;
2300 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2305 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2307 * Determine whether to write the value stored
2308 * in the other NVM bank or a modified value stored
2311 if (dev_spec->shadow_ram[i].modified) {
2312 data = dev_spec->shadow_ram[i].value;
2314 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2322 * If the word is 0x13, then make sure the signature bits
2323 * (15:14) are 11b until the commit has completed.
2324 * This will allow us to write 10b which indicates the
2325 * signature is valid. We want to do this after the write
2326 * has completed so that we don't mark the segment valid
2327 * while the write is still in progress
2329 if (i == E1000_ICH_NVM_SIG_WORD)
2330 data |= E1000_ICH_NVM_SIG_MASK;
2332 /* Convert offset to bytes. */
2333 act_offset = (i + new_bank_offset) << 1;
2336 /* Write the bytes to the new bank. */
2337 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2344 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2352 * Don't bother writing the segment valid bits if sector
2353 * programming failed.
2356 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2357 e_dbg("Flash commit failed.\n");
2362 * Finally validate the new segment by setting bit 15:14
2363 * to 10b in word 0x13 , this can be done without an
2364 * erase as well since these bits are 11 to start with
2365 * and we need to change bit 14 to 0b
2367 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2368 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2373 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2380 * And invalidate the previously valid segment by setting
2381 * its signature word (0x13) high_byte to 0b. This can be
2382 * done without an erase because flash erase sets all bits
2383 * to 1's. We can write 1's to 0's without an erase
2385 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2386 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2390 /* Great! Everything worked, we can now clear the cached entries. */
2391 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2392 dev_spec->shadow_ram[i].modified = false;
2393 dev_spec->shadow_ram[i].value = 0xFFFF;
2397 nvm->ops.release(hw);
2400 * Reload the EEPROM, or else modifications will not appear
2401 * until after the next adapter reset.
2404 e1000e_reload_nvm(hw);
2410 e_dbg("NVM update error: %d\n", ret_val);
2416 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2417 * @hw: pointer to the HW structure
2419 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2420 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2421 * calculated, in which case we need to calculate the checksum and set bit 6.
2423 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2429 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2430 * needs to be fixed. This bit is an indication that the NVM
2431 * was prepared by OEM software and did not calculate the
2432 * checksum...a likely scenario.
2434 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2438 if ((data & 0x40) == 0) {
2440 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2443 ret_val = e1000e_update_nvm_checksum(hw);
2448 return e1000e_validate_nvm_checksum_generic(hw);
2452 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2453 * @hw: pointer to the HW structure
2455 * To prevent malicious write/erase of the NVM, set it to be read-only
2456 * so that the hardware ignores all write/erase cycles of the NVM via
2457 * the flash control registers. The shadow-ram copy of the NVM will
2458 * still be updated, however any updates to this copy will not stick
2459 * across driver reloads.
2461 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2463 struct e1000_nvm_info *nvm = &hw->nvm;
2464 union ich8_flash_protected_range pr0;
2465 union ich8_hws_flash_status hsfsts;
2468 nvm->ops.acquire(hw);
2470 gfpreg = er32flash(ICH_FLASH_GFPREG);
2472 /* Write-protect GbE Sector of NVM */
2473 pr0.regval = er32flash(ICH_FLASH_PR0);
2474 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2475 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2476 pr0.range.wpe = true;
2477 ew32flash(ICH_FLASH_PR0, pr0.regval);
2480 * Lock down a subset of GbE Flash Control Registers, e.g.
2481 * PR0 to prevent the write-protection from being lifted.
2482 * Once FLOCKDN is set, the registers protected by it cannot
2483 * be written until FLOCKDN is cleared by a hardware reset.
2485 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2486 hsfsts.hsf_status.flockdn = true;
2487 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2489 nvm->ops.release(hw);
2493 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2494 * @hw: pointer to the HW structure
2495 * @offset: The offset (in bytes) of the byte/word to read.
2496 * @size: Size of data to read, 1=byte 2=word
2497 * @data: The byte(s) to write to the NVM.
2499 * Writes one/two bytes to the NVM using the flash access registers.
2501 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2504 union ich8_hws_flash_status hsfsts;
2505 union ich8_hws_flash_ctrl hsflctl;
2506 u32 flash_linear_addr;
2511 if (size < 1 || size > 2 || data > size * 0xff ||
2512 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2513 return -E1000_ERR_NVM;
2515 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2516 hw->nvm.flash_base_addr;
2521 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2525 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2526 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2527 hsflctl.hsf_ctrl.fldbcount = size -1;
2528 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2529 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2531 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2534 flash_data = (u32)data & 0x00FF;
2536 flash_data = (u32)data;
2538 ew32flash(ICH_FLASH_FDATA0, flash_data);
2541 * check if FCERR is set to 1 , if set to 1, clear it
2542 * and try the whole sequence a few more times else done
2544 ret_val = e1000_flash_cycle_ich8lan(hw,
2545 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2550 * If we're here, then things are most likely
2551 * completely hosed, but if the error condition
2552 * is detected, it won't hurt to give it another
2553 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2555 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2556 if (hsfsts.hsf_status.flcerr == 1)
2557 /* Repeat for some time before giving up. */
2559 if (hsfsts.hsf_status.flcdone == 0) {
2560 e_dbg("Timeout error - flash cycle "
2561 "did not complete.");
2564 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2570 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2571 * @hw: pointer to the HW structure
2572 * @offset: The index of the byte to read.
2573 * @data: The byte to write to the NVM.
2575 * Writes a single byte to the NVM using the flash access registers.
2577 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2580 u16 word = (u16)data;
2582 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2586 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2587 * @hw: pointer to the HW structure
2588 * @offset: The offset of the byte to write.
2589 * @byte: The byte to write to the NVM.
2591 * Writes a single byte to the NVM using the flash access registers.
2592 * Goes through a retry algorithm before giving up.
2594 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2595 u32 offset, u8 byte)
2598 u16 program_retries;
2600 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2604 for (program_retries = 0; program_retries < 100; program_retries++) {
2605 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2607 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2611 if (program_retries == 100)
2612 return -E1000_ERR_NVM;
2618 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2619 * @hw: pointer to the HW structure
2620 * @bank: 0 for first bank, 1 for second bank, etc.
2622 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2623 * bank N is 4096 * N + flash_reg_addr.
2625 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2627 struct e1000_nvm_info *nvm = &hw->nvm;
2628 union ich8_hws_flash_status hsfsts;
2629 union ich8_hws_flash_ctrl hsflctl;
2630 u32 flash_linear_addr;
2631 /* bank size is in 16bit words - adjust to bytes */
2632 u32 flash_bank_size = nvm->flash_bank_size * 2;
2635 s32 j, iteration, sector_size;
2637 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2640 * Determine HW Sector size: Read BERASE bits of hw flash status
2642 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2643 * consecutive sectors. The start index for the nth Hw sector
2644 * can be calculated as = bank * 4096 + n * 256
2645 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2646 * The start index for the nth Hw sector can be calculated
2648 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2649 * (ich9 only, otherwise error condition)
2650 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2652 switch (hsfsts.hsf_status.berasesz) {
2654 /* Hw sector size 256 */
2655 sector_size = ICH_FLASH_SEG_SIZE_256;
2656 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2659 sector_size = ICH_FLASH_SEG_SIZE_4K;
2663 sector_size = ICH_FLASH_SEG_SIZE_8K;
2667 sector_size = ICH_FLASH_SEG_SIZE_64K;
2671 return -E1000_ERR_NVM;
2674 /* Start with the base address, then add the sector offset. */
2675 flash_linear_addr = hw->nvm.flash_base_addr;
2676 flash_linear_addr += (bank) ? flash_bank_size : 0;
2678 for (j = 0; j < iteration ; j++) {
2681 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2686 * Write a value 11 (block Erase) in Flash
2687 * Cycle field in hw flash control
2689 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2690 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2691 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2694 * Write the last 24 bits of an index within the
2695 * block into Flash Linear address field in Flash
2698 flash_linear_addr += (j * sector_size);
2699 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2701 ret_val = e1000_flash_cycle_ich8lan(hw,
2702 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2707 * Check if FCERR is set to 1. If 1,
2708 * clear it and try the whole sequence
2709 * a few more times else Done
2711 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2712 if (hsfsts.hsf_status.flcerr == 1)
2713 /* repeat for some time before giving up */
2715 else if (hsfsts.hsf_status.flcdone == 0)
2717 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2724 * e1000_valid_led_default_ich8lan - Set the default LED settings
2725 * @hw: pointer to the HW structure
2726 * @data: Pointer to the LED settings
2728 * Reads the LED default settings from the NVM to data. If the NVM LED
2729 * settings is all 0's or F's, set the LED default to a valid LED default
2732 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2736 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2738 e_dbg("NVM Read Error\n");
2742 if (*data == ID_LED_RESERVED_0000 ||
2743 *data == ID_LED_RESERVED_FFFF)
2744 *data = ID_LED_DEFAULT_ICH8LAN;
2750 * e1000_id_led_init_pchlan - store LED configurations
2751 * @hw: pointer to the HW structure
2753 * PCH does not control LEDs via the LEDCTL register, rather it uses
2754 * the PHY LED configuration register.
2756 * PCH also does not have an "always on" or "always off" mode which
2757 * complicates the ID feature. Instead of using the "on" mode to indicate
2758 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2759 * use "link_up" mode. The LEDs will still ID on request if there is no
2760 * link based on logic in e1000_led_[on|off]_pchlan().
2762 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2764 struct e1000_mac_info *mac = &hw->mac;
2766 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2767 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2768 u16 data, i, temp, shift;
2770 /* Get default ID LED modes */
2771 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2775 mac->ledctl_default = er32(LEDCTL);
2776 mac->ledctl_mode1 = mac->ledctl_default;
2777 mac->ledctl_mode2 = mac->ledctl_default;
2779 for (i = 0; i < 4; i++) {
2780 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2783 case ID_LED_ON1_DEF2:
2784 case ID_LED_ON1_ON2:
2785 case ID_LED_ON1_OFF2:
2786 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2787 mac->ledctl_mode1 |= (ledctl_on << shift);
2789 case ID_LED_OFF1_DEF2:
2790 case ID_LED_OFF1_ON2:
2791 case ID_LED_OFF1_OFF2:
2792 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2793 mac->ledctl_mode1 |= (ledctl_off << shift);
2800 case ID_LED_DEF1_ON2:
2801 case ID_LED_ON1_ON2:
2802 case ID_LED_OFF1_ON2:
2803 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2804 mac->ledctl_mode2 |= (ledctl_on << shift);
2806 case ID_LED_DEF1_OFF2:
2807 case ID_LED_ON1_OFF2:
2808 case ID_LED_OFF1_OFF2:
2809 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2810 mac->ledctl_mode2 |= (ledctl_off << shift);
2823 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2824 * @hw: pointer to the HW structure
2826 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2827 * register, so the the bus width is hard coded.
2829 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2831 struct e1000_bus_info *bus = &hw->bus;
2834 ret_val = e1000e_get_bus_info_pcie(hw);
2837 * ICH devices are "PCI Express"-ish. They have
2838 * a configuration space, but do not contain
2839 * PCI Express Capability registers, so bus width
2840 * must be hardcoded.
2842 if (bus->width == e1000_bus_width_unknown)
2843 bus->width = e1000_bus_width_pcie_x1;
2849 * e1000_reset_hw_ich8lan - Reset the hardware
2850 * @hw: pointer to the HW structure
2852 * Does a full reset of the hardware which includes a reset of the PHY and
2855 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2857 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2863 * Prevent the PCI-E bus from sticking if there is no TLP connection
2864 * on the last TLP read/write transaction when MAC is reset.
2866 ret_val = e1000e_disable_pcie_master(hw);
2868 e_dbg("PCI-E Master disable polling has failed.\n");
2870 e_dbg("Masking off all interrupts\n");
2871 ew32(IMC, 0xffffffff);
2874 * Disable the Transmit and Receive units. Then delay to allow
2875 * any pending transactions to complete before we hit the MAC
2876 * with the global reset.
2879 ew32(TCTL, E1000_TCTL_PSP);
2884 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2885 if (hw->mac.type == e1000_ich8lan) {
2886 /* Set Tx and Rx buffer allocation to 8k apiece. */
2887 ew32(PBA, E1000_PBA_8K);
2888 /* Set Packet Buffer Size to 16k. */
2889 ew32(PBS, E1000_PBS_16K);
2892 if (hw->mac.type == e1000_pchlan) {
2893 /* Save the NVM K1 bit setting*/
2894 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®);
2898 if (reg & E1000_NVM_K1_ENABLE)
2899 dev_spec->nvm_k1_enabled = true;
2901 dev_spec->nvm_k1_enabled = false;
2906 if (!e1000_check_reset_block(hw)) {
2908 * Full-chip reset requires MAC and PHY reset at the same
2909 * time to make sure the interface between MAC and the
2910 * external PHY is reset.
2912 ctrl |= E1000_CTRL_PHY_RST;
2914 ret_val = e1000_acquire_swflag_ich8lan(hw);
2915 e_dbg("Issuing a global reset to ich8lan\n");
2916 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2920 e1000_release_swflag_ich8lan(hw);
2922 if (ctrl & E1000_CTRL_PHY_RST) {
2923 ret_val = hw->phy.ops.get_cfg_done(hw);
2927 ret_val = e1000_post_phy_reset_ich8lan(hw);
2933 * For PCH, this write will make sure that any noise
2934 * will be detected as a CRC error and be dropped rather than show up
2935 * as a bad packet to the DMA engine.
2937 if (hw->mac.type == e1000_pchlan)
2938 ew32(CRC_OFFSET, 0x65656565);
2940 ew32(IMC, 0xffffffff);
2943 kab = er32(KABGTXD);
2944 kab |= E1000_KABGTXD_BGSQLBIAS;
2952 * e1000_init_hw_ich8lan - Initialize the hardware
2953 * @hw: pointer to the HW structure
2955 * Prepares the hardware for transmit and receive by doing the following:
2956 * - initialize hardware bits
2957 * - initialize LED identification
2958 * - setup receive address registers
2959 * - setup flow control
2960 * - setup transmit descriptors
2961 * - clear statistics
2963 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2965 struct e1000_mac_info *mac = &hw->mac;
2966 u32 ctrl_ext, txdctl, snoop;
2970 e1000_initialize_hw_bits_ich8lan(hw);
2972 /* Initialize identification LED */
2973 ret_val = mac->ops.id_led_init(hw);
2975 e_dbg("Error initializing identification LED\n");
2976 /* This is not fatal and we should not stop init due to this */
2978 /* Setup the receive address. */
2979 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2981 /* Zero out the Multicast HASH table */
2982 e_dbg("Zeroing the MTA\n");
2983 for (i = 0; i < mac->mta_reg_count; i++)
2984 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2987 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2988 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2989 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2991 if (hw->phy.type == e1000_phy_82578) {
2992 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2993 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2998 /* Setup link and flow control */
2999 ret_val = e1000_setup_link_ich8lan(hw);
3001 /* Set the transmit descriptor write-back policy for both queues */
3002 txdctl = er32(TXDCTL(0));
3003 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3004 E1000_TXDCTL_FULL_TX_DESC_WB;
3005 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3006 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3007 ew32(TXDCTL(0), txdctl);
3008 txdctl = er32(TXDCTL(1));
3009 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3010 E1000_TXDCTL_FULL_TX_DESC_WB;
3011 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3012 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3013 ew32(TXDCTL(1), txdctl);
3016 * ICH8 has opposite polarity of no_snoop bits.
3017 * By default, we should use snoop behavior.
3019 if (mac->type == e1000_ich8lan)
3020 snoop = PCIE_ICH8_SNOOP_ALL;
3022 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3023 e1000e_set_pcie_no_snoop(hw, snoop);
3025 ctrl_ext = er32(CTRL_EXT);
3026 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3027 ew32(CTRL_EXT, ctrl_ext);
3030 * Clear all of the statistics registers (clear on read). It is
3031 * important that we do this after we have tried to establish link
3032 * because the symbol error count will increment wildly if there
3035 e1000_clear_hw_cntrs_ich8lan(hw);
3040 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3041 * @hw: pointer to the HW structure
3043 * Sets/Clears required hardware bits necessary for correctly setting up the
3044 * hardware for transmit and receive.
3046 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3050 /* Extended Device Control */
3051 reg = er32(CTRL_EXT);
3053 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3054 if (hw->mac.type >= e1000_pchlan)
3055 reg |= E1000_CTRL_EXT_PHYPDEN;
3056 ew32(CTRL_EXT, reg);
3058 /* Transmit Descriptor Control 0 */
3059 reg = er32(TXDCTL(0));
3061 ew32(TXDCTL(0), reg);
3063 /* Transmit Descriptor Control 1 */
3064 reg = er32(TXDCTL(1));
3066 ew32(TXDCTL(1), reg);
3068 /* Transmit Arbitration Control 0 */
3069 reg = er32(TARC(0));
3070 if (hw->mac.type == e1000_ich8lan)
3071 reg |= (1 << 28) | (1 << 29);
3072 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3075 /* Transmit Arbitration Control 1 */
3076 reg = er32(TARC(1));
3077 if (er32(TCTL) & E1000_TCTL_MULR)
3081 reg |= (1 << 24) | (1 << 26) | (1 << 30);
3085 if (hw->mac.type == e1000_ich8lan) {
3092 * work-around descriptor data corruption issue during nfs v2 udp
3093 * traffic, just disable the nfs filtering capability
3096 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3101 * e1000_setup_link_ich8lan - Setup flow control and link settings
3102 * @hw: pointer to the HW structure
3104 * Determines which flow control settings to use, then configures flow
3105 * control. Calls the appropriate media-specific link configuration
3106 * function. Assuming the adapter has a valid link partner, a valid link
3107 * should be established. Assumes the hardware has previously been reset
3108 * and the transmitter and receiver are not enabled.
3110 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3114 if (e1000_check_reset_block(hw))
3118 * ICH parts do not have a word in the NVM to determine
3119 * the default flow control setting, so we explicitly
3122 if (hw->fc.requested_mode == e1000_fc_default) {
3123 /* Workaround h/w hang when Tx flow control enabled */
3124 if (hw->mac.type == e1000_pchlan)
3125 hw->fc.requested_mode = e1000_fc_rx_pause;
3127 hw->fc.requested_mode = e1000_fc_full;
3131 * Save off the requested flow control mode for use later. Depending
3132 * on the link partner's capabilities, we may or may not use this mode.
3134 hw->fc.current_mode = hw->fc.requested_mode;
3136 e_dbg("After fix-ups FlowControl is now = %x\n",
3137 hw->fc.current_mode);
3139 /* Continue to configure the copper link. */
3140 ret_val = e1000_setup_copper_link_ich8lan(hw);
3144 ew32(FCTTV, hw->fc.pause_time);
3145 if ((hw->phy.type == e1000_phy_82578) ||
3146 (hw->phy.type == e1000_phy_82579) ||
3147 (hw->phy.type == e1000_phy_82577)) {
3148 ew32(FCRTV_PCH, hw->fc.refresh_time);
3150 ret_val = hw->phy.ops.write_reg(hw,
3151 PHY_REG(BM_PORT_CTRL_PAGE, 27),
3157 return e1000e_set_fc_watermarks(hw);
3161 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3162 * @hw: pointer to the HW structure
3164 * Configures the kumeran interface to the PHY to wait the appropriate time
3165 * when polling the PHY, then call the generic setup_copper_link to finish
3166 * configuring the copper link.
3168 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3175 ctrl |= E1000_CTRL_SLU;
3176 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3180 * Set the mac to wait the maximum time between each iteration
3181 * and increase the max iterations when polling the phy;
3182 * this fixes erroneous timeouts at 10Mbps.
3184 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3187 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3192 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3197 switch (hw->phy.type) {
3198 case e1000_phy_igp_3:
3199 ret_val = e1000e_copper_link_setup_igp(hw);
3204 case e1000_phy_82578:
3205 ret_val = e1000e_copper_link_setup_m88(hw);
3209 case e1000_phy_82577:
3210 case e1000_phy_82579:
3211 ret_val = e1000_copper_link_setup_82577(hw);
3216 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3221 reg_data &= ~IFE_PMC_AUTO_MDIX;
3223 switch (hw->phy.mdix) {
3225 reg_data &= ~IFE_PMC_FORCE_MDIX;
3228 reg_data |= IFE_PMC_FORCE_MDIX;
3232 reg_data |= IFE_PMC_AUTO_MDIX;
3235 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3243 return e1000e_setup_copper_link(hw);
3247 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3248 * @hw: pointer to the HW structure
3249 * @speed: pointer to store current link speed
3250 * @duplex: pointer to store the current link duplex
3252 * Calls the generic get_speed_and_duplex to retrieve the current link
3253 * information and then calls the Kumeran lock loss workaround for links at
3256 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3261 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3265 if ((hw->mac.type == e1000_ich8lan) &&
3266 (hw->phy.type == e1000_phy_igp_3) &&
3267 (*speed == SPEED_1000)) {
3268 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3275 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3276 * @hw: pointer to the HW structure
3278 * Work-around for 82566 Kumeran PCS lock loss:
3279 * On link status change (i.e. PCI reset, speed change) and link is up and
3281 * 0) if workaround is optionally disabled do nothing
3282 * 1) wait 1ms for Kumeran link to come up
3283 * 2) check Kumeran Diagnostic register PCS lock loss bit
3284 * 3) if not set the link is locked (all is good), otherwise...
3286 * 5) repeat up to 10 times
3287 * Note: this is only called for IGP3 copper when speed is 1gb.
3289 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3291 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3297 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3301 * Make sure link is up before proceeding. If not just return.
3302 * Attempting this while link is negotiating fouled up link
3305 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3309 for (i = 0; i < 10; i++) {
3310 /* read once to clear */
3311 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3314 /* and again to get new status */
3315 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3319 /* check for PCS lock */
3320 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3323 /* Issue PHY reset */
3324 e1000_phy_hw_reset(hw);
3327 /* Disable GigE link negotiation */
3328 phy_ctrl = er32(PHY_CTRL);
3329 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3330 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3331 ew32(PHY_CTRL, phy_ctrl);
3334 * Call gig speed drop workaround on Gig disable before accessing
3337 e1000e_gig_downshift_workaround_ich8lan(hw);
3339 /* unable to acquire PCS lock */
3340 return -E1000_ERR_PHY;
3344 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3345 * @hw: pointer to the HW structure
3346 * @state: boolean value used to set the current Kumeran workaround state
3348 * If ICH8, set the current Kumeran workaround state (enabled - true
3349 * /disabled - false).
3351 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3354 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3356 if (hw->mac.type != e1000_ich8lan) {
3357 e_dbg("Workaround applies to ICH8 only.\n");
3361 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3365 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3366 * @hw: pointer to the HW structure
3368 * Workaround for 82566 power-down on D3 entry:
3369 * 1) disable gigabit link
3370 * 2) write VR power-down enable
3372 * Continue if successful, else issue LCD reset and repeat
3374 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3380 if (hw->phy.type != e1000_phy_igp_3)
3383 /* Try the workaround twice (if needed) */
3386 reg = er32(PHY_CTRL);
3387 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3388 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3389 ew32(PHY_CTRL, reg);
3392 * Call gig speed drop workaround on Gig disable before
3393 * accessing any PHY registers
3395 if (hw->mac.type == e1000_ich8lan)
3396 e1000e_gig_downshift_workaround_ich8lan(hw);
3398 /* Write VR power-down enable */
3399 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3400 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3401 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3403 /* Read it back and test */
3404 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3405 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3406 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3409 /* Issue PHY reset and repeat at most one more time */
3411 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3417 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3418 * @hw: pointer to the HW structure
3420 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3421 * LPLU, Gig disable, MDIC PHY reset):
3422 * 1) Set Kumeran Near-end loopback
3423 * 2) Clear Kumeran Near-end loopback
3424 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3426 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3431 if ((hw->mac.type != e1000_ich8lan) ||
3432 (hw->phy.type != e1000_phy_igp_3))
3435 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3439 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3440 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3444 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3445 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3450 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3451 * @hw: pointer to the HW structure
3453 * During S0 to Sx transition, it is possible the link remains at gig
3454 * instead of negotiating to a lower speed. Before going to Sx, set
3455 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3458 * Should only be called for applicable parts.
3460 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3464 phy_ctrl = er32(PHY_CTRL);
3465 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3466 ew32(PHY_CTRL, phy_ctrl);
3468 if (hw->mac.type >= e1000_pchlan)
3469 e1000_phy_hw_reset_ich8lan(hw);
3473 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3474 * @hw: pointer to the HW structure
3476 * Return the LED back to the default configuration.
3478 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3480 if (hw->phy.type == e1000_phy_ife)
3481 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3483 ew32(LEDCTL, hw->mac.ledctl_default);
3488 * e1000_led_on_ich8lan - Turn LEDs on
3489 * @hw: pointer to the HW structure
3493 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3495 if (hw->phy.type == e1000_phy_ife)
3496 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3497 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3499 ew32(LEDCTL, hw->mac.ledctl_mode2);
3504 * e1000_led_off_ich8lan - Turn LEDs off
3505 * @hw: pointer to the HW structure
3507 * Turn off the LEDs.
3509 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3511 if (hw->phy.type == e1000_phy_ife)
3512 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3513 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3515 ew32(LEDCTL, hw->mac.ledctl_mode1);
3520 * e1000_setup_led_pchlan - Configures SW controllable LED
3521 * @hw: pointer to the HW structure
3523 * This prepares the SW controllable LED for use.
3525 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3527 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3528 (u16)hw->mac.ledctl_mode1);
3532 * e1000_cleanup_led_pchlan - Restore the default LED operation
3533 * @hw: pointer to the HW structure
3535 * Return the LED back to the default configuration.
3537 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3539 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3540 (u16)hw->mac.ledctl_default);
3544 * e1000_led_on_pchlan - Turn LEDs on
3545 * @hw: pointer to the HW structure
3549 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3551 u16 data = (u16)hw->mac.ledctl_mode2;
3555 * If no link, then turn LED on by setting the invert bit
3556 * for each LED that's mode is "link_up" in ledctl_mode2.
3558 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3559 for (i = 0; i < 3; i++) {
3560 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3561 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3562 E1000_LEDCTL_MODE_LINK_UP)
3564 if (led & E1000_PHY_LED0_IVRT)
3565 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3567 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3571 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3575 * e1000_led_off_pchlan - Turn LEDs off
3576 * @hw: pointer to the HW structure
3578 * Turn off the LEDs.
3580 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3582 u16 data = (u16)hw->mac.ledctl_mode1;
3586 * If no link, then turn LED off by clearing the invert bit
3587 * for each LED that's mode is "link_up" in ledctl_mode1.
3589 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3590 for (i = 0; i < 3; i++) {
3591 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3592 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3593 E1000_LEDCTL_MODE_LINK_UP)
3595 if (led & E1000_PHY_LED0_IVRT)
3596 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3598 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3602 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3606 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3607 * @hw: pointer to the HW structure
3609 * Read appropriate register for the config done bit for completion status
3610 * and configure the PHY through s/w for EEPROM-less parts.
3612 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3613 * config done bit, so only an error is logged and continues. If we were
3614 * to return with error, EEPROM-less silicon would not be able to be reset
3617 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3623 e1000e_get_cfg_done(hw);
3625 /* Wait for indication from h/w that it has completed basic config */
3626 if (hw->mac.type >= e1000_ich10lan) {
3627 e1000_lan_init_done_ich8lan(hw);
3629 ret_val = e1000e_get_auto_rd_done(hw);
3632 * When auto config read does not complete, do not
3633 * return with an error. This can happen in situations
3634 * where there is no eeprom and prevents getting link.
3636 e_dbg("Auto Read Done did not complete\n");
3641 /* Clear PHY Reset Asserted bit */
3642 status = er32(STATUS);
3643 if (status & E1000_STATUS_PHYRA)
3644 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3646 e_dbg("PHY Reset Asserted not set - needs delay\n");
3648 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3649 if (hw->mac.type <= e1000_ich9lan) {
3650 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3651 (hw->phy.type == e1000_phy_igp_3)) {
3652 e1000e_phy_init_script_igp3(hw);
3655 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3656 /* Maybe we should do a basic PHY config */
3657 e_dbg("EEPROM not present\n");
3658 ret_val = -E1000_ERR_CONFIG;
3666 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3667 * @hw: pointer to the HW structure
3669 * In the case of a PHY power down to save power, or to turn off link during a
3670 * driver unload, or wake on lan is not enabled, remove the link.
3672 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3674 /* If the management interface is not enabled, then power down */
3675 if (!(hw->mac.ops.check_mng_mode(hw) ||
3676 hw->phy.ops.check_reset_block(hw)))
3677 e1000_power_down_phy_copper(hw);
3681 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3682 * @hw: pointer to the HW structure
3684 * Clears hardware counters specific to the silicon family and calls
3685 * clear_hw_cntrs_generic to clear all general purpose counters.
3687 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3691 e1000e_clear_hw_cntrs_base(hw);
3707 /* Clear PHY statistics registers */
3708 if ((hw->phy.type == e1000_phy_82578) ||
3709 (hw->phy.type == e1000_phy_82579) ||
3710 (hw->phy.type == e1000_phy_82577)) {
3711 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3712 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3713 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3714 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3715 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3716 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3717 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3718 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3719 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3720 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3721 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3722 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3723 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3724 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3728 static struct e1000_mac_operations ich8_mac_ops = {
3729 .id_led_init = e1000e_id_led_init,
3730 /* check_mng_mode dependent on mac type */
3731 .check_for_link = e1000_check_for_copper_link_ich8lan,
3732 /* cleanup_led dependent on mac type */
3733 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3734 .get_bus_info = e1000_get_bus_info_ich8lan,
3735 .set_lan_id = e1000_set_lan_id_single_port,
3736 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3737 /* led_on dependent on mac type */
3738 /* led_off dependent on mac type */
3739 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3740 .reset_hw = e1000_reset_hw_ich8lan,
3741 .init_hw = e1000_init_hw_ich8lan,
3742 .setup_link = e1000_setup_link_ich8lan,
3743 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3744 /* id_led_init dependent on mac type */
3747 static struct e1000_phy_operations ich8_phy_ops = {
3748 .acquire = e1000_acquire_swflag_ich8lan,
3749 .check_reset_block = e1000_check_reset_block_ich8lan,
3751 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3752 .get_cable_length = e1000e_get_cable_length_igp_2,
3753 .read_reg = e1000e_read_phy_reg_igp,
3754 .release = e1000_release_swflag_ich8lan,
3755 .reset = e1000_phy_hw_reset_ich8lan,
3756 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3757 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3758 .write_reg = e1000e_write_phy_reg_igp,
3761 static struct e1000_nvm_operations ich8_nvm_ops = {
3762 .acquire = e1000_acquire_nvm_ich8lan,
3763 .read = e1000_read_nvm_ich8lan,
3764 .release = e1000_release_nvm_ich8lan,
3765 .update = e1000_update_nvm_checksum_ich8lan,
3766 .valid_led_default = e1000_valid_led_default_ich8lan,
3767 .validate = e1000_validate_nvm_checksum_ich8lan,
3768 .write = e1000_write_nvm_ich8lan,
3771 struct e1000_info e1000_ich8_info = {
3772 .mac = e1000_ich8lan,
3773 .flags = FLAG_HAS_WOL
3775 | FLAG_RX_CSUM_ENABLED
3776 | FLAG_HAS_CTRLEXT_ON_LOAD
3781 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3782 .get_variants = e1000_get_variants_ich8lan,
3783 .mac_ops = &ich8_mac_ops,
3784 .phy_ops = &ich8_phy_ops,
3785 .nvm_ops = &ich8_nvm_ops,
3788 struct e1000_info e1000_ich9_info = {
3789 .mac = e1000_ich9lan,
3790 .flags = FLAG_HAS_JUMBO_FRAMES
3793 | FLAG_RX_CSUM_ENABLED
3794 | FLAG_HAS_CTRLEXT_ON_LOAD
3800 .max_hw_frame_size = DEFAULT_JUMBO,
3801 .get_variants = e1000_get_variants_ich8lan,
3802 .mac_ops = &ich8_mac_ops,
3803 .phy_ops = &ich8_phy_ops,
3804 .nvm_ops = &ich8_nvm_ops,
3807 struct e1000_info e1000_ich10_info = {
3808 .mac = e1000_ich10lan,
3809 .flags = FLAG_HAS_JUMBO_FRAMES
3812 | FLAG_RX_CSUM_ENABLED
3813 | FLAG_HAS_CTRLEXT_ON_LOAD
3819 .max_hw_frame_size = DEFAULT_JUMBO,
3820 .get_variants = e1000_get_variants_ich8lan,
3821 .mac_ops = &ich8_mac_ops,
3822 .phy_ops = &ich8_phy_ops,
3823 .nvm_ops = &ich8_nvm_ops,
3826 struct e1000_info e1000_pch_info = {
3827 .mac = e1000_pchlan,
3828 .flags = FLAG_IS_ICH
3830 | FLAG_RX_CSUM_ENABLED
3831 | FLAG_HAS_CTRLEXT_ON_LOAD
3834 | FLAG_HAS_JUMBO_FRAMES
3835 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3837 .flags2 = FLAG2_HAS_PHY_STATS,
3839 .max_hw_frame_size = 4096,
3840 .get_variants = e1000_get_variants_ich8lan,
3841 .mac_ops = &ich8_mac_ops,
3842 .phy_ops = &ich8_phy_ops,
3843 .nvm_ops = &ich8_nvm_ops,
3846 struct e1000_info e1000_pch2_info = {
3847 .mac = e1000_pch2lan,
3848 .flags = FLAG_IS_ICH
3850 | FLAG_RX_CSUM_ENABLED
3851 | FLAG_HAS_CTRLEXT_ON_LOAD
3854 | FLAG_HAS_JUMBO_FRAMES
3856 .flags2 = FLAG2_HAS_PHY_STATS
3859 .max_hw_frame_size = DEFAULT_JUMBO,
3860 .get_variants = e1000_get_variants_ich8lan,
3861 .mac_ops = &ich8_mac_ops,
3862 .phy_ops = &ich8_phy_ops,
3863 .nvm_ops = &ich8_nvm_ops,