1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 e1000_mng_mode_none = 0,
36 e1000_mng_mode_host_if_only
39 #define E1000_FACTPS_MNGCG 0x20000000
41 /* Intel(R) Active Management Technology signature */
42 #define E1000_IAMT_SIGNATURE 0x544D4149
45 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure
48 * Determines and stores the system bus information for a particular
49 * network interface. The following bus information is determined and stored:
50 * bus speed, bus width, type (PCIe), and PCIe function.
52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
54 struct e1000_bus_info *bus = &hw->bus;
55 struct e1000_adapter *adapter = hw->adapter;
57 u16 pcie_link_status, pci_header_type, cap_offset;
59 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
61 bus->width = e1000_bus_width_unknown;
63 pci_read_config_word(adapter->pdev,
64 cap_offset + PCIE_LINK_STATUS,
66 bus->width = (enum e1000_bus_width)((pcie_link_status &
67 PCIE_LINK_WIDTH_MASK) >>
68 PCIE_LINK_WIDTH_SHIFT);
71 pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER,
73 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
74 status = er32(STATUS);
75 bus->func = (status & E1000_STATUS_FUNC_MASK)
76 >> E1000_STATUS_FUNC_SHIFT;
85 * e1000_clear_vfta_generic - Clear VLAN filter table
86 * @hw: pointer to the HW structure
88 * Clears the register array which contains the VLAN filter table by
89 * setting all the values to 0.
91 void e1000_clear_vfta_generic(struct e1000_hw *hw)
95 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
96 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
102 * e1000_write_vfta_generic - Write value to VLAN filter table
103 * @hw: pointer to the HW structure
104 * @offset: register offset in VLAN filter table
105 * @value: register value written to VLAN filter table
107 * Writes value at the given offset in the register array which stores
108 * the VLAN filter table.
110 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
112 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
117 * e1000e_init_rx_addrs - Initialize receive address's
118 * @hw: pointer to the HW structure
119 * @rar_count: receive address registers
121 * Setups the receive address registers by setting the base receive address
122 * register to the devices MAC address and clearing all the other receive
123 * address registers to 0.
125 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
128 u8 mac_addr[ETH_ALEN] = {0};
130 /* Setup the receive address */
131 e_dbg("Programming MAC Address into RAR[0]\n");
133 e1000e_rar_set(hw, hw->mac.addr, 0);
135 /* Zero out the other (rar_entry_count - 1) receive addresses */
136 e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
137 for (i = 1; i < rar_count; i++)
138 e1000e_rar_set(hw, mac_addr, i);
142 * e1000e_rar_set - Set receive address register
143 * @hw: pointer to the HW structure
144 * @addr: pointer to the receive address
145 * @index: receive address array register
147 * Sets the receive address array register at index to the address passed
150 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
152 u32 rar_low, rar_high;
155 * HW expects these in little endian so we reverse the byte order
156 * from network order (big endian) to little endian
158 rar_low = ((u32) addr[0] |
159 ((u32) addr[1] << 8) |
160 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
162 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
164 /* If MAC address zero, no need to set the AV bit */
165 if (rar_low || rar_high)
166 rar_high |= E1000_RAH_AV;
169 * Some bridges will combine consecutive 32-bit writes into
170 * a single burst write, which will malfunction on some parts.
171 * The flushes avoid this.
173 ew32(RAL(index), rar_low);
175 ew32(RAH(index), rar_high);
180 * e1000_hash_mc_addr - Generate a multicast hash value
181 * @hw: pointer to the HW structure
182 * @mc_addr: pointer to a multicast address
184 * Generates a multicast address hash value which is used to determine
185 * the multicast filter table array address and new table value. See
186 * e1000_mta_set_generic()
188 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
190 u32 hash_value, hash_mask;
193 /* Register count multiplied by bits per register */
194 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
197 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
198 * where 0xFF would still fall within the hash mask.
200 while (hash_mask >> bit_shift != 0xFF)
204 * The portion of the address that is used for the hash table
205 * is determined by the mc_filter_type setting.
206 * The algorithm is such that there is a total of 8 bits of shifting.
207 * The bit_shift for a mc_filter_type of 0 represents the number of
208 * left-shifts where the MSB of mc_addr[5] would still fall within
209 * the hash_mask. Case 0 does this exactly. Since there are a total
210 * of 8 bits of shifting, then mc_addr[4] will shift right the
211 * remaining number of bits. Thus 8 - bit_shift. The rest of the
212 * cases are a variation of this algorithm...essentially raising the
213 * number of bits to shift mc_addr[5] left, while still keeping the
214 * 8-bit shifting total.
216 * For example, given the following Destination MAC Address and an
217 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
218 * we can see that the bit_shift for case 0 is 4. These are the hash
219 * values resulting from each mc_filter_type...
220 * [0] [1] [2] [3] [4] [5]
224 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
225 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
226 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
227 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
229 switch (hw->mac.mc_filter_type) {
244 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
245 (((u16) mc_addr[5]) << bit_shift)));
251 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
252 * @hw: pointer to the HW structure
253 * @mc_addr_list: array of multicast addresses to program
254 * @mc_addr_count: number of multicast addresses to program
255 * @rar_used_count: the first RAR register free to program
256 * @rar_count: total number of supported Receive Address Registers
258 * Updates the Receive Address Registers and Multicast Table Array.
259 * The caller must have a packed mc_addr_list of multicast addresses.
260 * The parameter rar_count will usually be hw->mac.rar_entry_count
261 * unless there are workarounds that change this.
263 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
264 u8 *mc_addr_list, u32 mc_addr_count,
265 u32 rar_used_count, u32 rar_count)
268 u32 *mcarray = kzalloc(hw->mac.mta_reg_count * sizeof(u32), GFP_ATOMIC);
271 printk(KERN_ERR "multicast array memory allocation failed\n");
276 * Load the first set of multicast addresses into the exact
277 * filters (RAR). If there are not enough to fill the RAR
278 * array, clear the filters.
280 for (i = rar_used_count; i < rar_count; i++) {
282 e1000e_rar_set(hw, mc_addr_list, i);
284 mc_addr_list += ETH_ALEN;
286 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);
288 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);
293 /* Load any remaining multicast addresses into the hash table. */
294 for (; mc_addr_count > 0; mc_addr_count--) {
295 u32 hash_value, hash_reg, hash_bit, mta;
296 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
297 e_dbg("Hash value = 0x%03X\n", hash_value);
298 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
299 hash_bit = hash_value & 0x1F;
300 mta = (1 << hash_bit);
301 mcarray[hash_reg] |= mta;
302 mc_addr_list += ETH_ALEN;
305 /* write the hash table completely */
306 for (i = 0; i < hw->mac.mta_reg_count; i++)
307 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, mcarray[i]);
314 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
315 * @hw: pointer to the HW structure
317 * Clears the base hardware counters by reading the counter registers.
319 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
361 * e1000e_check_for_copper_link - Check for link (Copper)
362 * @hw: pointer to the HW structure
364 * Checks to see of the link status of the hardware has changed. If a
365 * change in link status has been detected, then we read the PHY registers
366 * to get the current speed/duplex if link exists.
368 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
370 struct e1000_mac_info *mac = &hw->mac;
375 * We only want to go out to the PHY registers to see if Auto-Neg
376 * has completed and/or if our link status has changed. The
377 * get_link_status flag is set upon receiving a Link Status
378 * Change or Rx Sequence Error interrupt.
380 if (!mac->get_link_status)
384 * First we want to see if the MII Status Register reports
385 * link. If so, then we want to get the current speed/duplex
388 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
393 return ret_val; /* No link detected */
395 mac->get_link_status = false;
398 * Check if there was DownShift, must be checked
399 * immediately after link-up
401 e1000e_check_downshift(hw);
404 * If we are forcing speed/duplex, then we simply return since
405 * we have already determined whether we have link or not.
408 ret_val = -E1000_ERR_CONFIG;
413 * Auto-Neg is enabled. Auto Speed Detection takes care
414 * of MAC speed/duplex configuration. So we only need to
415 * configure Collision Distance in the MAC.
417 e1000e_config_collision_dist(hw);
420 * Configure Flow Control now that Auto-Neg has completed.
421 * First, we need to restore the desired flow control
422 * settings because we may have had to re-autoneg with a
423 * different link partner.
425 ret_val = e1000e_config_fc_after_link_up(hw);
427 e_dbg("Error configuring flow control\n");
434 * e1000e_check_for_fiber_link - Check for link (Fiber)
435 * @hw: pointer to the HW structure
437 * Checks for link up on the hardware. If link is not up and we have
438 * a signal, then we need to force link up.
440 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
442 struct e1000_mac_info *mac = &hw->mac;
449 status = er32(STATUS);
453 * If we don't have link (auto-negotiation failed or link partner
454 * cannot auto-negotiate), the cable is plugged in (we have signal),
455 * and our link partner is not trying to auto-negotiate with us (we
456 * are receiving idles or data), we need to force link up. We also
457 * need to give auto-negotiation time to complete, in case the cable
458 * was just plugged in. The autoneg_failed flag does this.
460 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
461 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
462 (!(rxcw & E1000_RXCW_C))) {
463 if (mac->autoneg_failed == 0) {
464 mac->autoneg_failed = 1;
467 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
469 /* Disable auto-negotiation in the TXCW register */
470 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
472 /* Force link-up and also force full-duplex. */
474 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
477 /* Configure Flow Control after forcing link up. */
478 ret_val = e1000e_config_fc_after_link_up(hw);
480 e_dbg("Error configuring flow control\n");
483 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
485 * If we are forcing link and we are receiving /C/ ordered
486 * sets, re-enable auto-negotiation in the TXCW register
487 * and disable forced link in the Device Control register
488 * in an attempt to auto-negotiate with our link partner.
490 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
491 ew32(TXCW, mac->txcw);
492 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
494 mac->serdes_has_link = true;
501 * e1000e_check_for_serdes_link - Check for link (Serdes)
502 * @hw: pointer to the HW structure
504 * Checks for link up on the hardware. If link is not up and we have
505 * a signal, then we need to force link up.
507 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
509 struct e1000_mac_info *mac = &hw->mac;
516 status = er32(STATUS);
520 * If we don't have link (auto-negotiation failed or link partner
521 * cannot auto-negotiate), and our link partner is not trying to
522 * auto-negotiate with us (we are receiving idles or data),
523 * we need to force link up. We also need to give auto-negotiation
526 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
527 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
528 if (mac->autoneg_failed == 0) {
529 mac->autoneg_failed = 1;
532 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
534 /* Disable auto-negotiation in the TXCW register */
535 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
537 /* Force link-up and also force full-duplex. */
539 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
542 /* Configure Flow Control after forcing link up. */
543 ret_val = e1000e_config_fc_after_link_up(hw);
545 e_dbg("Error configuring flow control\n");
548 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
550 * If we are forcing link and we are receiving /C/ ordered
551 * sets, re-enable auto-negotiation in the TXCW register
552 * and disable forced link in the Device Control register
553 * in an attempt to auto-negotiate with our link partner.
555 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
556 ew32(TXCW, mac->txcw);
557 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
559 mac->serdes_has_link = true;
560 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
562 * If we force link for non-auto-negotiation switch, check
563 * link status based on MAC synchronization for internal
566 /* SYNCH bit and IV bit are sticky. */
569 if (rxcw & E1000_RXCW_SYNCH) {
570 if (!(rxcw & E1000_RXCW_IV)) {
571 mac->serdes_has_link = true;
572 e_dbg("SERDES: Link up - forced.\n");
575 mac->serdes_has_link = false;
576 e_dbg("SERDES: Link down - force failed.\n");
580 if (E1000_TXCW_ANE & er32(TXCW)) {
581 status = er32(STATUS);
582 if (status & E1000_STATUS_LU) {
583 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
586 if (rxcw & E1000_RXCW_SYNCH) {
587 if (!(rxcw & E1000_RXCW_IV)) {
588 mac->serdes_has_link = true;
589 e_dbg("SERDES: Link up - autoneg "
590 "completed successfully.\n");
592 mac->serdes_has_link = false;
593 e_dbg("SERDES: Link down - invalid"
594 "codewords detected in autoneg.\n");
597 mac->serdes_has_link = false;
598 e_dbg("SERDES: Link down - no sync.\n");
601 mac->serdes_has_link = false;
602 e_dbg("SERDES: Link down - autoneg failed\n");
610 * e1000_set_default_fc_generic - Set flow control default values
611 * @hw: pointer to the HW structure
613 * Read the EEPROM for the default values for flow control and store the
616 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
622 * Read and store word 0x0F of the EEPROM. This word contains bits
623 * that determine the hardware's default PAUSE (flow control) mode,
624 * a bit that determines whether the HW defaults to enabling or
625 * disabling auto-negotiation, and the direction of the
626 * SW defined pins. If there is no SW over-ride of the flow
627 * control setting, then the variable hw->fc will
628 * be initialized based on a value in the EEPROM.
630 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
633 e_dbg("NVM Read Error\n");
637 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
638 hw->fc.requested_mode = e1000_fc_none;
639 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
641 hw->fc.requested_mode = e1000_fc_tx_pause;
643 hw->fc.requested_mode = e1000_fc_full;
649 * e1000e_setup_link - Setup flow control and link settings
650 * @hw: pointer to the HW structure
652 * Determines which flow control settings to use, then configures flow
653 * control. Calls the appropriate media-specific link configuration
654 * function. Assuming the adapter has a valid link partner, a valid link
655 * should be established. Assumes the hardware has previously been reset
656 * and the transmitter and receiver are not enabled.
658 s32 e1000e_setup_link(struct e1000_hw *hw)
660 struct e1000_mac_info *mac = &hw->mac;
664 * In the case of the phy reset being blocked, we already have a link.
665 * We do not need to set it up again.
667 if (e1000_check_reset_block(hw))
671 * If requested flow control is set to default, set flow control
672 * based on the EEPROM flow control settings.
674 if (hw->fc.requested_mode == e1000_fc_default) {
675 ret_val = e1000_set_default_fc_generic(hw);
681 * Save off the requested flow control mode for use later. Depending
682 * on the link partner's capabilities, we may or may not use this mode.
684 hw->fc.current_mode = hw->fc.requested_mode;
686 e_dbg("After fix-ups FlowControl is now = %x\n",
687 hw->fc.current_mode);
689 /* Call the necessary media_type subroutine to configure the link. */
690 ret_val = mac->ops.setup_physical_interface(hw);
695 * Initialize the flow control address, type, and PAUSE timer
696 * registers to their default values. This is done even if flow
697 * control is disabled, because it does not hurt anything to
698 * initialize these registers.
700 e_dbg("Initializing the Flow Control address, type and timer regs\n");
701 ew32(FCT, FLOW_CONTROL_TYPE);
702 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
703 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
705 ew32(FCTTV, hw->fc.pause_time);
707 return e1000e_set_fc_watermarks(hw);
711 * e1000_commit_fc_settings_generic - Configure flow control
712 * @hw: pointer to the HW structure
714 * Write the flow control settings to the Transmit Config Word Register (TXCW)
715 * base on the flow control settings in e1000_mac_info.
717 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
719 struct e1000_mac_info *mac = &hw->mac;
723 * Check for a software override of the flow control settings, and
724 * setup the device accordingly. If auto-negotiation is enabled, then
725 * software will have to set the "PAUSE" bits to the correct value in
726 * the Transmit Config Word Register (TXCW) and re-start auto-
727 * negotiation. However, if auto-negotiation is disabled, then
728 * software will have to manually configure the two flow control enable
729 * bits in the CTRL register.
731 * The possible values of the "fc" parameter are:
732 * 0: Flow control is completely disabled
733 * 1: Rx flow control is enabled (we can receive pause frames,
734 * but not send pause frames).
735 * 2: Tx flow control is enabled (we can send pause frames but we
736 * do not support receiving pause frames).
737 * 3: Both Rx and Tx flow control (symmetric) are enabled.
739 switch (hw->fc.current_mode) {
741 /* Flow control completely disabled by a software over-ride. */
742 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
744 case e1000_fc_rx_pause:
746 * Rx Flow control is enabled and Tx Flow control is disabled
747 * by a software over-ride. Since there really isn't a way to
748 * advertise that we are capable of Rx Pause ONLY, we will
749 * advertise that we support both symmetric and asymmetric Rx
750 * PAUSE. Later, we will disable the adapter's ability to send
753 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
755 case e1000_fc_tx_pause:
757 * Tx Flow control is enabled, and Rx Flow control is disabled,
758 * by a software over-ride.
760 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
764 * Flow control (both Rx and Tx) is enabled by a software
767 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
770 e_dbg("Flow control param set incorrectly\n");
771 return -E1000_ERR_CONFIG;
782 * e1000_poll_fiber_serdes_link_generic - Poll for link up
783 * @hw: pointer to the HW structure
785 * Polls for link up by reading the status register, if link fails to come
786 * up with auto-negotiation, then the link is forced if a signal is detected.
788 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
790 struct e1000_mac_info *mac = &hw->mac;
795 * If we have a signal (the cable is plugged in, or assumed true for
796 * serdes media) then poll for a "Link-Up" indication in the Device
797 * Status Register. Time-out if a link isn't seen in 500 milliseconds
798 * seconds (Auto-negotiation should complete in less than 500
799 * milliseconds even if the other end is doing it in SW).
801 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
803 status = er32(STATUS);
804 if (status & E1000_STATUS_LU)
807 if (i == FIBER_LINK_UP_LIMIT) {
808 e_dbg("Never got a valid link from auto-neg!!!\n");
809 mac->autoneg_failed = 1;
811 * AutoNeg failed to achieve a link, so we'll call
812 * mac->check_for_link. This routine will force the
813 * link up if we detect a signal. This will allow us to
814 * communicate with non-autonegotiating link partners.
816 ret_val = mac->ops.check_for_link(hw);
818 e_dbg("Error while checking for link\n");
821 mac->autoneg_failed = 0;
823 mac->autoneg_failed = 0;
824 e_dbg("Valid Link Found\n");
831 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
832 * @hw: pointer to the HW structure
834 * Configures collision distance and flow control for fiber and serdes
835 * links. Upon successful setup, poll for link.
837 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
844 /* Take the link out of reset */
845 ctrl &= ~E1000_CTRL_LRST;
847 e1000e_config_collision_dist(hw);
849 ret_val = e1000_commit_fc_settings_generic(hw);
854 * Since auto-negotiation is enabled, take the link out of reset (the
855 * link will be in reset, because we previously reset the chip). This
856 * will restart auto-negotiation. If auto-negotiation is successful
857 * then the link-up status bit will be set and the flow control enable
858 * bits (RFCE and TFCE) will be set according to their negotiated value.
860 e_dbg("Auto-negotiation enabled\n");
867 * For these adapters, the SW definable pin 1 is set when the optics
868 * detect a signal. If we have a signal, then poll for a "Link-Up"
871 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
872 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
873 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
875 e_dbg("No signal detected\n");
882 * e1000e_config_collision_dist - Configure collision distance
883 * @hw: pointer to the HW structure
885 * Configures the collision distance to the default value and is used
886 * during link setup. Currently no func pointer exists and all
887 * implementations are handled in the generic version of this function.
889 void e1000e_config_collision_dist(struct e1000_hw *hw)
895 tctl &= ~E1000_TCTL_COLD;
896 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
903 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
904 * @hw: pointer to the HW structure
906 * Sets the flow control high/low threshold (watermark) registers. If
907 * flow control XON frame transmission is enabled, then set XON frame
908 * transmission as well.
910 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
912 u32 fcrtl = 0, fcrth = 0;
915 * Set the flow control receive threshold registers. Normally,
916 * these registers will be set to a default threshold that may be
917 * adjusted later by the driver's runtime code. However, if the
918 * ability to transmit pause frames is not enabled, then these
919 * registers will be set to 0.
921 if (hw->fc.current_mode & e1000_fc_tx_pause) {
923 * We need to set up the Receive Threshold high and low water
924 * marks as well as (optionally) enabling the transmission of
927 fcrtl = hw->fc.low_water;
928 fcrtl |= E1000_FCRTL_XONE;
929 fcrth = hw->fc.high_water;
938 * e1000e_force_mac_fc - Force the MAC's flow control settings
939 * @hw: pointer to the HW structure
941 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
942 * device control register to reflect the adapter settings. TFCE and RFCE
943 * need to be explicitly set by software when a copper PHY is used because
944 * autonegotiation is managed by the PHY rather than the MAC. Software must
945 * also configure these bits when link is forced on a fiber connection.
947 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
954 * Because we didn't get link via the internal auto-negotiation
955 * mechanism (we either forced link or we got link via PHY
956 * auto-neg), we have to manually enable/disable transmit an
957 * receive flow control.
959 * The "Case" statement below enables/disable flow control
960 * according to the "hw->fc.current_mode" parameter.
962 * The possible values of the "fc" parameter are:
963 * 0: Flow control is completely disabled
964 * 1: Rx flow control is enabled (we can receive pause
965 * frames but not send pause frames).
966 * 2: Tx flow control is enabled (we can send pause frames
967 * frames but we do not receive pause frames).
968 * 3: Both Rx and Tx flow control (symmetric) is enabled.
969 * other: No other values should be possible at this point.
971 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
973 switch (hw->fc.current_mode) {
975 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
977 case e1000_fc_rx_pause:
978 ctrl &= (~E1000_CTRL_TFCE);
979 ctrl |= E1000_CTRL_RFCE;
981 case e1000_fc_tx_pause:
982 ctrl &= (~E1000_CTRL_RFCE);
983 ctrl |= E1000_CTRL_TFCE;
986 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
989 e_dbg("Flow control param set incorrectly\n");
990 return -E1000_ERR_CONFIG;
999 * e1000e_config_fc_after_link_up - Configures flow control after link
1000 * @hw: pointer to the HW structure
1002 * Checks the status of auto-negotiation after link up to ensure that the
1003 * speed and duplex were not forced. If the link needed to be forced, then
1004 * flow control needs to be forced also. If auto-negotiation is enabled
1005 * and did not fail, then we configure flow control based on our link
1008 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1010 struct e1000_mac_info *mac = &hw->mac;
1012 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1016 * Check for the case where we have fiber media and auto-neg failed
1017 * so we had to force link. In this case, we need to force the
1018 * configuration of the MAC to match the "fc" parameter.
1020 if (mac->autoneg_failed) {
1021 if (hw->phy.media_type == e1000_media_type_fiber ||
1022 hw->phy.media_type == e1000_media_type_internal_serdes)
1023 ret_val = e1000e_force_mac_fc(hw);
1025 if (hw->phy.media_type == e1000_media_type_copper)
1026 ret_val = e1000e_force_mac_fc(hw);
1030 e_dbg("Error forcing flow control settings\n");
1035 * Check for the case where we have copper media and auto-neg is
1036 * enabled. In this case, we need to check and see if Auto-Neg
1037 * has completed, and if so, how the PHY and link partner has
1038 * flow control configured.
1040 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1042 * Read the MII Status Register and check to see if AutoNeg
1043 * has completed. We read this twice because this reg has
1044 * some "sticky" (latched) bits.
1046 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1049 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1053 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1054 e_dbg("Copper PHY and Auto Neg "
1055 "has not completed.\n");
1060 * The AutoNeg process has completed, so we now need to
1061 * read both the Auto Negotiation Advertisement
1062 * Register (Address 4) and the Auto_Negotiation Base
1063 * Page Ability Register (Address 5) to determine how
1064 * flow control was negotiated.
1066 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1069 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1074 * Two bits in the Auto Negotiation Advertisement Register
1075 * (Address 4) and two bits in the Auto Negotiation Base
1076 * Page Ability Register (Address 5) determine flow control
1077 * for both the PHY and the link partner. The following
1078 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1079 * 1999, describes these PAUSE resolution bits and how flow
1080 * control is determined based upon these settings.
1081 * NOTE: DC = Don't Care
1083 * LOCAL DEVICE | LINK PARTNER
1084 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1085 *-------|---------|-------|---------|--------------------
1086 * 0 | 0 | DC | DC | e1000_fc_none
1087 * 0 | 1 | 0 | DC | e1000_fc_none
1088 * 0 | 1 | 1 | 0 | e1000_fc_none
1089 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1090 * 1 | 0 | 0 | DC | e1000_fc_none
1091 * 1 | DC | 1 | DC | e1000_fc_full
1092 * 1 | 1 | 0 | 0 | e1000_fc_none
1093 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1095 * Are both PAUSE bits set to 1? If so, this implies
1096 * Symmetric Flow Control is enabled at both ends. The
1097 * ASM_DIR bits are irrelevant per the spec.
1099 * For Symmetric Flow Control:
1101 * LOCAL DEVICE | LINK PARTNER
1102 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1103 *-------|---------|-------|---------|--------------------
1104 * 1 | DC | 1 | DC | E1000_fc_full
1107 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1108 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1110 * Now we need to check if the user selected Rx ONLY
1111 * of pause frames. In this case, we had to advertise
1112 * FULL flow control because we could not advertise Rx
1113 * ONLY. Hence, we must now check to see if we need to
1114 * turn OFF the TRANSMISSION of PAUSE frames.
1116 if (hw->fc.requested_mode == e1000_fc_full) {
1117 hw->fc.current_mode = e1000_fc_full;
1118 e_dbg("Flow Control = FULL.\r\n");
1120 hw->fc.current_mode = e1000_fc_rx_pause;
1121 e_dbg("Flow Control = "
1122 "RX PAUSE frames only.\r\n");
1126 * For receiving PAUSE frames ONLY.
1128 * LOCAL DEVICE | LINK PARTNER
1129 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1130 *-------|---------|-------|---------|--------------------
1131 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1133 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1134 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1135 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1136 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1137 hw->fc.current_mode = e1000_fc_tx_pause;
1138 e_dbg("Flow Control = Tx PAUSE frames only.\r\n");
1141 * For transmitting PAUSE frames ONLY.
1143 * LOCAL DEVICE | LINK PARTNER
1144 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1145 *-------|---------|-------|---------|--------------------
1146 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1148 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1149 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1150 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1151 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1152 hw->fc.current_mode = e1000_fc_rx_pause;
1153 e_dbg("Flow Control = Rx PAUSE frames only.\r\n");
1156 * Per the IEEE spec, at this point flow control
1157 * should be disabled.
1159 hw->fc.current_mode = e1000_fc_none;
1160 e_dbg("Flow Control = NONE.\r\n");
1164 * Now we need to do one last check... If we auto-
1165 * negotiated to HALF DUPLEX, flow control should not be
1166 * enabled per IEEE 802.3 spec.
1168 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1170 e_dbg("Error getting link speed and duplex\n");
1174 if (duplex == HALF_DUPLEX)
1175 hw->fc.current_mode = e1000_fc_none;
1178 * Now we call a subroutine to actually force the MAC
1179 * controller to use the correct flow control settings.
1181 ret_val = e1000e_force_mac_fc(hw);
1183 e_dbg("Error forcing flow control settings\n");
1192 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1193 * @hw: pointer to the HW structure
1194 * @speed: stores the current speed
1195 * @duplex: stores the current duplex
1197 * Read the status register for the current speed/duplex and store the current
1198 * speed and duplex for copper connections.
1200 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1204 status = er32(STATUS);
1205 if (status & E1000_STATUS_SPEED_1000) {
1206 *speed = SPEED_1000;
1207 e_dbg("1000 Mbs, ");
1208 } else if (status & E1000_STATUS_SPEED_100) {
1216 if (status & E1000_STATUS_FD) {
1217 *duplex = FULL_DUPLEX;
1218 e_dbg("Full Duplex\n");
1220 *duplex = HALF_DUPLEX;
1221 e_dbg("Half Duplex\n");
1228 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1229 * @hw: pointer to the HW structure
1230 * @speed: stores the current speed
1231 * @duplex: stores the current duplex
1233 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1234 * for fiber/serdes links.
1236 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1238 *speed = SPEED_1000;
1239 *duplex = FULL_DUPLEX;
1245 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1246 * @hw: pointer to the HW structure
1248 * Acquire the HW semaphore to access the PHY or NVM
1250 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1253 s32 timeout = hw->nvm.word_size + 1;
1256 /* Get the SW semaphore */
1257 while (i < timeout) {
1259 if (!(swsm & E1000_SWSM_SMBI))
1267 e_dbg("Driver can't access device - SMBI bit is set.\n");
1268 return -E1000_ERR_NVM;
1271 /* Get the FW semaphore. */
1272 for (i = 0; i < timeout; i++) {
1274 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1276 /* Semaphore acquired if bit latched */
1277 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1284 /* Release semaphores */
1285 e1000e_put_hw_semaphore(hw);
1286 e_dbg("Driver can't access the NVM\n");
1287 return -E1000_ERR_NVM;
1294 * e1000e_put_hw_semaphore - Release hardware semaphore
1295 * @hw: pointer to the HW structure
1297 * Release hardware semaphore used to access the PHY or NVM
1299 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1304 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1309 * e1000e_get_auto_rd_done - Check for auto read completion
1310 * @hw: pointer to the HW structure
1312 * Check EEPROM for Auto Read done bit.
1314 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1318 while (i < AUTO_READ_DONE_TIMEOUT) {
1319 if (er32(EECD) & E1000_EECD_AUTO_RD)
1325 if (i == AUTO_READ_DONE_TIMEOUT) {
1326 e_dbg("Auto read by HW from NVM has not completed.\n");
1327 return -E1000_ERR_RESET;
1334 * e1000e_valid_led_default - Verify a valid default LED config
1335 * @hw: pointer to the HW structure
1336 * @data: pointer to the NVM (EEPROM)
1338 * Read the EEPROM for the current default LED configuration. If the
1339 * LED configuration is not valid, set to a valid LED configuration.
1341 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1345 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1347 e_dbg("NVM Read Error\n");
1351 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1352 *data = ID_LED_DEFAULT;
1358 * e1000e_id_led_init -
1359 * @hw: pointer to the HW structure
1362 s32 e1000e_id_led_init(struct e1000_hw *hw)
1364 struct e1000_mac_info *mac = &hw->mac;
1366 const u32 ledctl_mask = 0x000000FF;
1367 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1368 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1370 const u16 led_mask = 0x0F;
1372 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1376 mac->ledctl_default = er32(LEDCTL);
1377 mac->ledctl_mode1 = mac->ledctl_default;
1378 mac->ledctl_mode2 = mac->ledctl_default;
1380 for (i = 0; i < 4; i++) {
1381 temp = (data >> (i << 2)) & led_mask;
1383 case ID_LED_ON1_DEF2:
1384 case ID_LED_ON1_ON2:
1385 case ID_LED_ON1_OFF2:
1386 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1387 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1389 case ID_LED_OFF1_DEF2:
1390 case ID_LED_OFF1_ON2:
1391 case ID_LED_OFF1_OFF2:
1392 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1393 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1400 case ID_LED_DEF1_ON2:
1401 case ID_LED_ON1_ON2:
1402 case ID_LED_OFF1_ON2:
1403 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1404 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1406 case ID_LED_DEF1_OFF2:
1407 case ID_LED_ON1_OFF2:
1408 case ID_LED_OFF1_OFF2:
1409 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1410 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1422 * e1000e_setup_led_generic - Configures SW controllable LED
1423 * @hw: pointer to the HW structure
1425 * This prepares the SW controllable LED for use and saves the current state
1426 * of the LED so it can be later restored.
1428 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1432 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) {
1433 return -E1000_ERR_CONFIG;
1436 if (hw->phy.media_type == e1000_media_type_fiber) {
1437 ledctl = er32(LEDCTL);
1438 hw->mac.ledctl_default = ledctl;
1440 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1441 E1000_LEDCTL_LED0_BLINK |
1442 E1000_LEDCTL_LED0_MODE_MASK);
1443 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1444 E1000_LEDCTL_LED0_MODE_SHIFT);
1445 ew32(LEDCTL, ledctl);
1446 } else if (hw->phy.media_type == e1000_media_type_copper) {
1447 ew32(LEDCTL, hw->mac.ledctl_mode1);
1454 * e1000e_cleanup_led_generic - Set LED config to default operation
1455 * @hw: pointer to the HW structure
1457 * Remove the current LED configuration and set the LED configuration
1458 * to the default value, saved from the EEPROM.
1460 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1462 ew32(LEDCTL, hw->mac.ledctl_default);
1467 * e1000e_blink_led - Blink LED
1468 * @hw: pointer to the HW structure
1470 * Blink the LEDs which are set to be on.
1472 s32 e1000e_blink_led(struct e1000_hw *hw)
1474 u32 ledctl_blink = 0;
1477 if (hw->phy.media_type == e1000_media_type_fiber) {
1478 /* always blink LED0 for PCI-E fiber */
1479 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1480 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1483 * set the blink bit for each LED that's "on" (0x0E)
1486 ledctl_blink = hw->mac.ledctl_mode2;
1487 for (i = 0; i < 4; i++)
1488 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1489 E1000_LEDCTL_MODE_LED_ON)
1490 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1494 ew32(LEDCTL, ledctl_blink);
1500 * e1000e_led_on_generic - Turn LED on
1501 * @hw: pointer to the HW structure
1505 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1509 switch (hw->phy.media_type) {
1510 case e1000_media_type_fiber:
1512 ctrl &= ~E1000_CTRL_SWDPIN0;
1513 ctrl |= E1000_CTRL_SWDPIO0;
1516 case e1000_media_type_copper:
1517 ew32(LEDCTL, hw->mac.ledctl_mode2);
1527 * e1000e_led_off_generic - Turn LED off
1528 * @hw: pointer to the HW structure
1532 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1536 switch (hw->phy.media_type) {
1537 case e1000_media_type_fiber:
1539 ctrl |= E1000_CTRL_SWDPIN0;
1540 ctrl |= E1000_CTRL_SWDPIO0;
1543 case e1000_media_type_copper:
1544 ew32(LEDCTL, hw->mac.ledctl_mode1);
1554 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1555 * @hw: pointer to the HW structure
1556 * @no_snoop: bitmap of snoop events
1558 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1560 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1566 gcr &= ~(PCIE_NO_SNOOP_ALL);
1573 * e1000e_disable_pcie_master - Disables PCI-express master access
1574 * @hw: pointer to the HW structure
1576 * Returns 0 if successful, else returns -10
1577 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1578 * the master requests to be disabled.
1580 * Disables PCI-Express master access and verifies there are no pending
1583 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1586 s32 timeout = MASTER_DISABLE_TIMEOUT;
1589 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1593 if (!(er32(STATUS) &
1594 E1000_STATUS_GIO_MASTER_ENABLE))
1601 e_dbg("Master requests are pending.\n");
1602 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1609 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1610 * @hw: pointer to the HW structure
1612 * Reset the Adaptive Interframe Spacing throttle to default values.
1614 void e1000e_reset_adaptive(struct e1000_hw *hw)
1616 struct e1000_mac_info *mac = &hw->mac;
1618 if (!mac->adaptive_ifs) {
1619 e_dbg("Not in Adaptive IFS mode!\n");
1623 mac->current_ifs_val = 0;
1624 mac->ifs_min_val = IFS_MIN;
1625 mac->ifs_max_val = IFS_MAX;
1626 mac->ifs_step_size = IFS_STEP;
1627 mac->ifs_ratio = IFS_RATIO;
1629 mac->in_ifs_mode = false;
1636 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1637 * @hw: pointer to the HW structure
1639 * Update the Adaptive Interframe Spacing Throttle value based on the
1640 * time between transmitted packets and time between collisions.
1642 void e1000e_update_adaptive(struct e1000_hw *hw)
1644 struct e1000_mac_info *mac = &hw->mac;
1646 if (!mac->adaptive_ifs) {
1647 e_dbg("Not in Adaptive IFS mode!\n");
1651 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1652 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1653 mac->in_ifs_mode = true;
1654 if (mac->current_ifs_val < mac->ifs_max_val) {
1655 if (!mac->current_ifs_val)
1656 mac->current_ifs_val = mac->ifs_min_val;
1658 mac->current_ifs_val +=
1660 ew32(AIT, mac->current_ifs_val);
1664 if (mac->in_ifs_mode &&
1665 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1666 mac->current_ifs_val = 0;
1667 mac->in_ifs_mode = false;
1676 * e1000_raise_eec_clk - Raise EEPROM clock
1677 * @hw: pointer to the HW structure
1678 * @eecd: pointer to the EEPROM
1680 * Enable/Raise the EEPROM clock bit.
1682 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1684 *eecd = *eecd | E1000_EECD_SK;
1687 udelay(hw->nvm.delay_usec);
1691 * e1000_lower_eec_clk - Lower EEPROM clock
1692 * @hw: pointer to the HW structure
1693 * @eecd: pointer to the EEPROM
1695 * Clear/Lower the EEPROM clock bit.
1697 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1699 *eecd = *eecd & ~E1000_EECD_SK;
1702 udelay(hw->nvm.delay_usec);
1706 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1707 * @hw: pointer to the HW structure
1708 * @data: data to send to the EEPROM
1709 * @count: number of bits to shift out
1711 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1712 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1713 * In order to do this, "data" must be broken down into bits.
1715 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1717 struct e1000_nvm_info *nvm = &hw->nvm;
1718 u32 eecd = er32(EECD);
1721 mask = 0x01 << (count - 1);
1722 if (nvm->type == e1000_nvm_eeprom_spi)
1723 eecd |= E1000_EECD_DO;
1726 eecd &= ~E1000_EECD_DI;
1729 eecd |= E1000_EECD_DI;
1734 udelay(nvm->delay_usec);
1736 e1000_raise_eec_clk(hw, &eecd);
1737 e1000_lower_eec_clk(hw, &eecd);
1742 eecd &= ~E1000_EECD_DI;
1747 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1748 * @hw: pointer to the HW structure
1749 * @count: number of bits to shift in
1751 * In order to read a register from the EEPROM, we need to shift 'count' bits
1752 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1753 * the EEPROM (setting the SK bit), and then reading the value of the data out
1754 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1757 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1765 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1768 for (i = 0; i < count; i++) {
1770 e1000_raise_eec_clk(hw, &eecd);
1774 eecd &= ~E1000_EECD_DI;
1775 if (eecd & E1000_EECD_DO)
1778 e1000_lower_eec_clk(hw, &eecd);
1785 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1786 * @hw: pointer to the HW structure
1787 * @ee_reg: EEPROM flag for polling
1789 * Polls the EEPROM status bit for either read or write completion based
1790 * upon the value of 'ee_reg'.
1792 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1794 u32 attempts = 100000;
1797 for (i = 0; i < attempts; i++) {
1798 if (ee_reg == E1000_NVM_POLL_READ)
1803 if (reg & E1000_NVM_RW_REG_DONE)
1809 return -E1000_ERR_NVM;
1813 * e1000e_acquire_nvm - Generic request for access to EEPROM
1814 * @hw: pointer to the HW structure
1816 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1817 * Return successful if access grant bit set, else clear the request for
1818 * EEPROM access and return -E1000_ERR_NVM (-1).
1820 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1822 u32 eecd = er32(EECD);
1823 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1825 ew32(EECD, eecd | E1000_EECD_REQ);
1829 if (eecd & E1000_EECD_GNT)
1837 eecd &= ~E1000_EECD_REQ;
1839 e_dbg("Could not acquire NVM grant\n");
1840 return -E1000_ERR_NVM;
1847 * e1000_standby_nvm - Return EEPROM to standby state
1848 * @hw: pointer to the HW structure
1850 * Return the EEPROM to a standby state.
1852 static void e1000_standby_nvm(struct e1000_hw *hw)
1854 struct e1000_nvm_info *nvm = &hw->nvm;
1855 u32 eecd = er32(EECD);
1857 if (nvm->type == e1000_nvm_eeprom_spi) {
1858 /* Toggle CS to flush commands */
1859 eecd |= E1000_EECD_CS;
1862 udelay(nvm->delay_usec);
1863 eecd &= ~E1000_EECD_CS;
1866 udelay(nvm->delay_usec);
1871 * e1000_stop_nvm - Terminate EEPROM command
1872 * @hw: pointer to the HW structure
1874 * Terminates the current command by inverting the EEPROM's chip select pin.
1876 static void e1000_stop_nvm(struct e1000_hw *hw)
1881 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1883 eecd |= E1000_EECD_CS;
1884 e1000_lower_eec_clk(hw, &eecd);
1889 * e1000e_release_nvm - Release exclusive access to EEPROM
1890 * @hw: pointer to the HW structure
1892 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1894 void e1000e_release_nvm(struct e1000_hw *hw)
1901 eecd &= ~E1000_EECD_REQ;
1906 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1907 * @hw: pointer to the HW structure
1909 * Setups the EEPROM for reading and writing.
1911 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1913 struct e1000_nvm_info *nvm = &hw->nvm;
1914 u32 eecd = er32(EECD);
1918 if (nvm->type == e1000_nvm_eeprom_spi) {
1919 /* Clear SK and CS */
1920 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1923 timeout = NVM_MAX_RETRY_SPI;
1926 * Read "Status Register" repeatedly until the LSB is cleared.
1927 * The EEPROM will signal that the command has been completed
1928 * by clearing bit 0 of the internal status register. If it's
1929 * not cleared within 'timeout', then error out.
1932 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
1933 hw->nvm.opcode_bits);
1934 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
1935 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
1939 e1000_standby_nvm(hw);
1944 e_dbg("SPI NVM Status error\n");
1945 return -E1000_ERR_NVM;
1953 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
1954 * @hw: pointer to the HW structure
1955 * @offset: offset of word in the EEPROM to read
1956 * @words: number of words to read
1957 * @data: word read from the EEPROM
1959 * Reads a 16 bit word from the EEPROM using the EERD register.
1961 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1963 struct e1000_nvm_info *nvm = &hw->nvm;
1968 * A check for invalid values: offset too large, too many words,
1969 * too many words for the offset, and not enough words.
1971 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
1973 e_dbg("nvm parameter(s) out of bounds\n");
1974 return -E1000_ERR_NVM;
1977 for (i = 0; i < words; i++) {
1978 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
1979 E1000_NVM_RW_REG_START;
1982 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
1986 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
1993 * e1000e_write_nvm_spi - Write to EEPROM using SPI
1994 * @hw: pointer to the HW structure
1995 * @offset: offset within the EEPROM to be written to
1996 * @words: number of words to write
1997 * @data: 16 bit word(s) to be written to the EEPROM
1999 * Writes data to EEPROM at offset using SPI interface.
2001 * If e1000e_update_nvm_checksum is not called after this function , the
2002 * EEPROM will most likely contain an invalid checksum.
2004 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2006 struct e1000_nvm_info *nvm = &hw->nvm;
2011 * A check for invalid values: offset too large, too many words,
2012 * and not enough words.
2014 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2016 e_dbg("nvm parameter(s) out of bounds\n");
2017 return -E1000_ERR_NVM;
2020 ret_val = nvm->ops.acquire(hw);
2026 while (widx < words) {
2027 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
2029 ret_val = e1000_ready_nvm_eeprom(hw);
2031 nvm->ops.release(hw);
2035 e1000_standby_nvm(hw);
2037 /* Send the WRITE ENABLE command (8 bit opcode) */
2038 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2041 e1000_standby_nvm(hw);
2044 * Some SPI eeproms use the 8th address bit embedded in the
2047 if ((nvm->address_bits == 8) && (offset >= 128))
2048 write_opcode |= NVM_A8_OPCODE_SPI;
2050 /* Send the Write command (8-bit opcode + addr) */
2051 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2052 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2055 /* Loop to allow for up to whole page write of eeprom */
2056 while (widx < words) {
2057 u16 word_out = data[widx];
2058 word_out = (word_out >> 8) | (word_out << 8);
2059 e1000_shift_out_eec_bits(hw, word_out, 16);
2062 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2063 e1000_standby_nvm(hw);
2070 nvm->ops.release(hw);
2075 * e1000e_read_mac_addr - Read device MAC address
2076 * @hw: pointer to the HW structure
2078 * Reads the device MAC address from the EEPROM and stores the value.
2079 * Since devices with two ports use the same EEPROM, we increment the
2080 * last bit in the MAC address for the second port.
2082 s32 e1000e_read_mac_addr(struct e1000_hw *hw)
2085 u16 offset, nvm_data, i;
2086 u16 mac_addr_offset = 0;
2088 if (hw->mac.type == e1000_82571) {
2089 /* Check for an alternate MAC address. An alternate MAC
2090 * address can be setup by pre-boot software and must be
2091 * treated like a permanent address and must override the
2092 * actual permanent MAC address.*/
2093 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
2096 e_dbg("NVM Read Error\n");
2099 if (mac_addr_offset == 0xFFFF)
2100 mac_addr_offset = 0;
2102 if (mac_addr_offset) {
2103 if (hw->bus.func == E1000_FUNC_1)
2104 mac_addr_offset += ETH_ALEN/sizeof(u16);
2106 /* make sure we have a valid mac address here
2107 * before using it */
2108 ret_val = e1000_read_nvm(hw, mac_addr_offset, 1,
2111 e_dbg("NVM Read Error\n");
2114 if (nvm_data & 0x0001)
2115 mac_addr_offset = 0;
2118 if (mac_addr_offset)
2119 hw->dev_spec.e82571.alt_mac_addr_is_present = 1;
2122 for (i = 0; i < ETH_ALEN; i += 2) {
2123 offset = mac_addr_offset + (i >> 1);
2124 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
2126 e_dbg("NVM Read Error\n");
2129 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
2130 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
2133 /* Flip last bit of mac address if we're on second port */
2134 if (!mac_addr_offset && hw->bus.func == E1000_FUNC_1)
2135 hw->mac.perm_addr[5] ^= 1;
2137 for (i = 0; i < ETH_ALEN; i++)
2138 hw->mac.addr[i] = hw->mac.perm_addr[i];
2144 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2145 * @hw: pointer to the HW structure
2147 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2148 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2150 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2156 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2157 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2159 e_dbg("NVM Read Error\n");
2162 checksum += nvm_data;
2165 if (checksum != (u16) NVM_SUM) {
2166 e_dbg("NVM Checksum Invalid\n");
2167 return -E1000_ERR_NVM;
2174 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2175 * @hw: pointer to the HW structure
2177 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2178 * up to the checksum. Then calculates the EEPROM checksum and writes the
2179 * value to the EEPROM.
2181 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2187 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2188 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2190 e_dbg("NVM Read Error while updating checksum.\n");
2193 checksum += nvm_data;
2195 checksum = (u16) NVM_SUM - checksum;
2196 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2198 e_dbg("NVM Write Error while updating checksum.\n");
2204 * e1000e_reload_nvm - Reloads EEPROM
2205 * @hw: pointer to the HW structure
2207 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2208 * extended control register.
2210 void e1000e_reload_nvm(struct e1000_hw *hw)
2215 ctrl_ext = er32(CTRL_EXT);
2216 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2217 ew32(CTRL_EXT, ctrl_ext);
2222 * e1000_calculate_checksum - Calculate checksum for buffer
2223 * @buffer: pointer to EEPROM
2224 * @length: size of EEPROM to calculate a checksum for
2226 * Calculates the checksum for some buffer on a specified length. The
2227 * checksum calculated is returned.
2229 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2237 for (i = 0; i < length; i++)
2240 return (u8) (0 - sum);
2244 * e1000_mng_enable_host_if - Checks host interface is enabled
2245 * @hw: pointer to the HW structure
2247 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2249 * This function checks whether the HOST IF is enabled for command operation
2250 * and also checks whether the previous command is completed. It busy waits
2251 * in case of previous command is not completed.
2253 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2258 /* Check that the host interface is enabled. */
2260 if ((hicr & E1000_HICR_EN) == 0) {
2261 e_dbg("E1000_HOST_EN bit disabled.\n");
2262 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2264 /* check the previous command is completed */
2265 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2267 if (!(hicr & E1000_HICR_C))
2272 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2273 e_dbg("Previous command timeout failed .\n");
2274 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2281 * e1000e_check_mng_mode_generic - check management mode
2282 * @hw: pointer to the HW structure
2284 * Reads the firmware semaphore register and returns true (>0) if
2285 * manageability is enabled, else false (0).
2287 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2289 u32 fwsm = er32(FWSM);
2291 return (fwsm & E1000_FWSM_MODE_MASK) ==
2292 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2296 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2297 * @hw: pointer to the HW structure
2299 * Enables packet filtering on transmit packets if manageability is enabled
2300 * and host interface is enabled.
2302 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2304 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2305 u32 *buffer = (u32 *)&hw->mng_cookie;
2307 s32 ret_val, hdr_csum, csum;
2310 hw->mac.tx_pkt_filtering = true;
2312 /* No manageability, no filtering */
2313 if (!e1000e_check_mng_mode(hw)) {
2314 hw->mac.tx_pkt_filtering = false;
2319 * If we can't read from the host interface for whatever
2320 * reason, disable filtering.
2322 ret_val = e1000_mng_enable_host_if(hw);
2324 hw->mac.tx_pkt_filtering = false;
2328 /* Read in the header. Length and offset are in dwords. */
2329 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2330 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2331 for (i = 0; i < len; i++)
2332 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2333 hdr_csum = hdr->checksum;
2335 csum = e1000_calculate_checksum((u8 *)hdr,
2336 E1000_MNG_DHCP_COOKIE_LENGTH);
2338 * If either the checksums or signature don't match, then
2339 * the cookie area isn't considered valid, in which case we
2340 * take the safe route of assuming Tx filtering is enabled.
2342 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2343 hw->mac.tx_pkt_filtering = true;
2347 /* Cookie area is valid, make the final check for filtering. */
2348 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2349 hw->mac.tx_pkt_filtering = false;
2354 return hw->mac.tx_pkt_filtering;
2358 * e1000_mng_write_cmd_header - Writes manageability command header
2359 * @hw: pointer to the HW structure
2360 * @hdr: pointer to the host interface command header
2362 * Writes the command header after does the checksum calculation.
2364 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2365 struct e1000_host_mng_command_header *hdr)
2367 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2369 /* Write the whole command header structure with new checksum. */
2371 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2374 /* Write the relevant command block into the ram area. */
2375 for (i = 0; i < length; i++) {
2376 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2377 *((u32 *) hdr + i));
2385 * e1000_mng_host_if_write - Write to the manageability host interface
2386 * @hw: pointer to the HW structure
2387 * @buffer: pointer to the host interface buffer
2388 * @length: size of the buffer
2389 * @offset: location in the buffer to write to
2390 * @sum: sum of the data (not checksum)
2392 * This function writes the buffer content at the offset given on the host if.
2393 * It also does alignment considerations to do the writes in most efficient
2394 * way. Also fills up the sum of the buffer in *buffer parameter.
2396 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2397 u16 length, u16 offset, u8 *sum)
2400 u8 *bufptr = buffer;
2402 u16 remaining, i, j, prev_bytes;
2404 /* sum = only sum of the data and it is not checksum */
2406 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2407 return -E1000_ERR_PARAM;
2410 prev_bytes = offset & 0x3;
2414 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2415 for (j = prev_bytes; j < sizeof(u32); j++) {
2416 *(tmp + j) = *bufptr++;
2419 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2420 length -= j - prev_bytes;
2424 remaining = length & 0x3;
2425 length -= remaining;
2427 /* Calculate length in DWORDs */
2431 * The device driver writes the relevant command block into the
2434 for (i = 0; i < length; i++) {
2435 for (j = 0; j < sizeof(u32); j++) {
2436 *(tmp + j) = *bufptr++;
2440 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2443 for (j = 0; j < sizeof(u32); j++) {
2445 *(tmp + j) = *bufptr++;
2451 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2458 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2459 * @hw: pointer to the HW structure
2460 * @buffer: pointer to the host interface
2461 * @length: size of the buffer
2463 * Writes the DHCP information to the host interface.
2465 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2467 struct e1000_host_mng_command_header hdr;
2471 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2472 hdr.command_length = length;
2477 /* Enable the host interface */
2478 ret_val = e1000_mng_enable_host_if(hw);
2482 /* Populate the host interface with the contents of "buffer". */
2483 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2484 sizeof(hdr), &(hdr.checksum));
2488 /* Write the manageability command header */
2489 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2493 /* Tell the ARC a new command is pending. */
2495 ew32(HICR, hicr | E1000_HICR_C);
2501 * e1000e_enable_mng_pass_thru - Enable processing of ARP's
2502 * @hw: pointer to the HW structure
2504 * Verifies the hardware needs to allow ARPs to be processed by the host.
2506 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2510 bool ret_val = false;
2514 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
2515 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
2518 if (hw->mac.arc_subsystem_valid) {
2520 factps = er32(FACTPS);
2522 if (!(factps & E1000_FACTPS_MNGCG) &&
2523 ((fwsm & E1000_FWSM_MODE_MASK) ==
2524 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2529 if ((manc & E1000_MANC_SMBUS_EN) &&
2530 !(manc & E1000_MANC_ASF_EN)) {
2539 s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
2544 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2546 e_dbg("NVM Read Error\n");
2549 *pba_num = (u32)(nvm_data << 16);
2551 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
2553 e_dbg("NVM Read Error\n");
2556 *pba_num |= nvm_data;