1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 e1000_mng_mode_none = 0,
36 e1000_mng_mode_host_if_only
39 #define E1000_FACTPS_MNGCG 0x20000000
41 /* Intel(R) Active Management Technology signature */
42 #define E1000_IAMT_SIGNATURE 0x544D4149
45 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure
48 * Determines and stores the system bus information for a particular
49 * network interface. The following bus information is determined and stored:
50 * bus speed, bus width, type (PCIe), and PCIe function.
52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
54 struct e1000_mac_info *mac = &hw->mac;
55 struct e1000_bus_info *bus = &hw->bus;
56 struct e1000_adapter *adapter = hw->adapter;
57 u16 pcie_link_status, cap_offset;
59 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
61 bus->width = e1000_bus_width_unknown;
63 pci_read_config_word(adapter->pdev,
64 cap_offset + PCIE_LINK_STATUS,
66 bus->width = (enum e1000_bus_width)((pcie_link_status &
67 PCIE_LINK_WIDTH_MASK) >>
68 PCIE_LINK_WIDTH_SHIFT);
71 mac->ops.set_lan_id(hw);
77 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
79 * @hw: pointer to the HW structure
81 * Determines the LAN function id by reading memory-mapped registers
82 * and swaps the port value if requested.
84 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
86 struct e1000_bus_info *bus = &hw->bus;
90 * The status register reports the correct function number
91 * for the device regardless of function swap state.
94 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
98 * e1000_set_lan_id_single_port - Set LAN id for a single port device
99 * @hw: pointer to the HW structure
101 * Sets the LAN function id to zero for a single port device.
103 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
105 struct e1000_bus_info *bus = &hw->bus;
111 * e1000_clear_vfta_generic - Clear VLAN filter table
112 * @hw: pointer to the HW structure
114 * Clears the register array which contains the VLAN filter table by
115 * setting all the values to 0.
117 void e1000_clear_vfta_generic(struct e1000_hw *hw)
121 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
122 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
128 * e1000_write_vfta_generic - Write value to VLAN filter table
129 * @hw: pointer to the HW structure
130 * @offset: register offset in VLAN filter table
131 * @value: register value written to VLAN filter table
133 * Writes value at the given offset in the register array which stores
134 * the VLAN filter table.
136 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
138 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
143 * e1000e_init_rx_addrs - Initialize receive address's
144 * @hw: pointer to the HW structure
145 * @rar_count: receive address registers
147 * Setups the receive address registers by setting the base receive address
148 * register to the devices MAC address and clearing all the other receive
149 * address registers to 0.
151 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
154 u8 mac_addr[ETH_ALEN] = {0};
156 /* Setup the receive address */
157 e_dbg("Programming MAC Address into RAR[0]\n");
159 e1000e_rar_set(hw, hw->mac.addr, 0);
161 /* Zero out the other (rar_entry_count - 1) receive addresses */
162 e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
163 for (i = 1; i < rar_count; i++)
164 e1000e_rar_set(hw, mac_addr, i);
168 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
169 * @hw: pointer to the HW structure
171 * Checks the nvm for an alternate MAC address. An alternate MAC address
172 * can be setup by pre-boot software and must be treated like a permanent
173 * address and must override the actual permanent MAC address. If an
174 * alternate MAC address is found it is programmed into RAR0, replacing
175 * the permanent address that was installed into RAR0 by the Si on reset.
176 * This function will return SUCCESS unless it encounters an error while
177 * reading the EEPROM.
179 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
183 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
184 u8 alt_mac_addr[ETH_ALEN];
186 ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);
190 /* Check for LOM (vs. NIC) or one of two valid mezzanine cards */
191 if (!((nvm_data & NVM_COMPAT_LOM) ||
192 (hw->adapter->pdev->device == E1000_DEV_ID_82571EB_SERDES_DUAL) ||
193 (hw->adapter->pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)))
196 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
197 &nvm_alt_mac_addr_offset);
199 e_dbg("NVM Read Error\n");
203 if (nvm_alt_mac_addr_offset == 0xFFFF) {
204 /* There is no Alternate MAC Address */
208 if (hw->bus.func == E1000_FUNC_1)
209 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
210 for (i = 0; i < ETH_ALEN; i += 2) {
211 offset = nvm_alt_mac_addr_offset + (i >> 1);
212 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
214 e_dbg("NVM Read Error\n");
218 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
219 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
222 /* if multicast bit is set, the alternate address will not be used */
223 if (alt_mac_addr[0] & 0x01) {
224 e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
229 * We have a valid alternate MAC address, and we want to treat it the
230 * same as the normal permanent MAC address stored by the HW into the
231 * RAR. Do this by mapping this address into RAR0.
233 e1000e_rar_set(hw, alt_mac_addr, 0);
240 * e1000e_rar_set - Set receive address register
241 * @hw: pointer to the HW structure
242 * @addr: pointer to the receive address
243 * @index: receive address array register
245 * Sets the receive address array register at index to the address passed
248 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
250 u32 rar_low, rar_high;
253 * HW expects these in little endian so we reverse the byte order
254 * from network order (big endian) to little endian
256 rar_low = ((u32) addr[0] |
257 ((u32) addr[1] << 8) |
258 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
260 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
262 /* If MAC address zero, no need to set the AV bit */
263 if (rar_low || rar_high)
264 rar_high |= E1000_RAH_AV;
267 * Some bridges will combine consecutive 32-bit writes into
268 * a single burst write, which will malfunction on some parts.
269 * The flushes avoid this.
271 ew32(RAL(index), rar_low);
273 ew32(RAH(index), rar_high);
278 * e1000_hash_mc_addr - Generate a multicast hash value
279 * @hw: pointer to the HW structure
280 * @mc_addr: pointer to a multicast address
282 * Generates a multicast address hash value which is used to determine
283 * the multicast filter table array address and new table value. See
284 * e1000_mta_set_generic()
286 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
288 u32 hash_value, hash_mask;
291 /* Register count multiplied by bits per register */
292 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
295 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
296 * where 0xFF would still fall within the hash mask.
298 while (hash_mask >> bit_shift != 0xFF)
302 * The portion of the address that is used for the hash table
303 * is determined by the mc_filter_type setting.
304 * The algorithm is such that there is a total of 8 bits of shifting.
305 * The bit_shift for a mc_filter_type of 0 represents the number of
306 * left-shifts where the MSB of mc_addr[5] would still fall within
307 * the hash_mask. Case 0 does this exactly. Since there are a total
308 * of 8 bits of shifting, then mc_addr[4] will shift right the
309 * remaining number of bits. Thus 8 - bit_shift. The rest of the
310 * cases are a variation of this algorithm...essentially raising the
311 * number of bits to shift mc_addr[5] left, while still keeping the
312 * 8-bit shifting total.
314 * For example, given the following Destination MAC Address and an
315 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
316 * we can see that the bit_shift for case 0 is 4. These are the hash
317 * values resulting from each mc_filter_type...
318 * [0] [1] [2] [3] [4] [5]
322 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
323 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
324 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
325 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
327 switch (hw->mac.mc_filter_type) {
342 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
343 (((u16) mc_addr[5]) << bit_shift)));
349 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
350 * @hw: pointer to the HW structure
351 * @mc_addr_list: array of multicast addresses to program
352 * @mc_addr_count: number of multicast addresses to program
354 * Updates entire Multicast Table Array.
355 * The caller must have a packed mc_addr_list of multicast addresses.
357 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
358 u8 *mc_addr_list, u32 mc_addr_count)
360 u32 hash_value, hash_bit, hash_reg;
363 /* clear mta_shadow */
364 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
366 /* update mta_shadow from mc_addr_list */
367 for (i = 0; (u32) i < mc_addr_count; i++) {
368 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
370 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
371 hash_bit = hash_value & 0x1F;
373 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
374 mc_addr_list += (ETH_ALEN);
377 /* replace the entire MTA table */
378 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
379 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
384 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
385 * @hw: pointer to the HW structure
387 * Clears the base hardware counters by reading the counter registers.
389 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
431 * e1000e_check_for_copper_link - Check for link (Copper)
432 * @hw: pointer to the HW structure
434 * Checks to see of the link status of the hardware has changed. If a
435 * change in link status has been detected, then we read the PHY registers
436 * to get the current speed/duplex if link exists.
438 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
440 struct e1000_mac_info *mac = &hw->mac;
445 * We only want to go out to the PHY registers to see if Auto-Neg
446 * has completed and/or if our link status has changed. The
447 * get_link_status flag is set upon receiving a Link Status
448 * Change or Rx Sequence Error interrupt.
450 if (!mac->get_link_status)
454 * First we want to see if the MII Status Register reports
455 * link. If so, then we want to get the current speed/duplex
458 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
463 return ret_val; /* No link detected */
465 mac->get_link_status = false;
468 * Check if there was DownShift, must be checked
469 * immediately after link-up
471 e1000e_check_downshift(hw);
474 * If we are forcing speed/duplex, then we simply return since
475 * we have already determined whether we have link or not.
478 ret_val = -E1000_ERR_CONFIG;
483 * Auto-Neg is enabled. Auto Speed Detection takes care
484 * of MAC speed/duplex configuration. So we only need to
485 * configure Collision Distance in the MAC.
487 e1000e_config_collision_dist(hw);
490 * Configure Flow Control now that Auto-Neg has completed.
491 * First, we need to restore the desired flow control
492 * settings because we may have had to re-autoneg with a
493 * different link partner.
495 ret_val = e1000e_config_fc_after_link_up(hw);
497 e_dbg("Error configuring flow control\n");
503 * e1000e_check_for_fiber_link - Check for link (Fiber)
504 * @hw: pointer to the HW structure
506 * Checks for link up on the hardware. If link is not up and we have
507 * a signal, then we need to force link up.
509 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
511 struct e1000_mac_info *mac = &hw->mac;
518 status = er32(STATUS);
522 * If we don't have link (auto-negotiation failed or link partner
523 * cannot auto-negotiate), the cable is plugged in (we have signal),
524 * and our link partner is not trying to auto-negotiate with us (we
525 * are receiving idles or data), we need to force link up. We also
526 * need to give auto-negotiation time to complete, in case the cable
527 * was just plugged in. The autoneg_failed flag does this.
529 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
530 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
531 (!(rxcw & E1000_RXCW_C))) {
532 if (mac->autoneg_failed == 0) {
533 mac->autoneg_failed = 1;
536 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
538 /* Disable auto-negotiation in the TXCW register */
539 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
541 /* Force link-up and also force full-duplex. */
543 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
546 /* Configure Flow Control after forcing link up. */
547 ret_val = e1000e_config_fc_after_link_up(hw);
549 e_dbg("Error configuring flow control\n");
552 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
554 * If we are forcing link and we are receiving /C/ ordered
555 * sets, re-enable auto-negotiation in the TXCW register
556 * and disable forced link in the Device Control register
557 * in an attempt to auto-negotiate with our link partner.
559 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
560 ew32(TXCW, mac->txcw);
561 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
563 mac->serdes_has_link = true;
570 * e1000e_check_for_serdes_link - Check for link (Serdes)
571 * @hw: pointer to the HW structure
573 * Checks for link up on the hardware. If link is not up and we have
574 * a signal, then we need to force link up.
576 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
578 struct e1000_mac_info *mac = &hw->mac;
585 status = er32(STATUS);
589 * If we don't have link (auto-negotiation failed or link partner
590 * cannot auto-negotiate), and our link partner is not trying to
591 * auto-negotiate with us (we are receiving idles or data),
592 * we need to force link up. We also need to give auto-negotiation
595 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
596 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
597 if (mac->autoneg_failed == 0) {
598 mac->autoneg_failed = 1;
601 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
603 /* Disable auto-negotiation in the TXCW register */
604 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
606 /* Force link-up and also force full-duplex. */
608 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
611 /* Configure Flow Control after forcing link up. */
612 ret_val = e1000e_config_fc_after_link_up(hw);
614 e_dbg("Error configuring flow control\n");
617 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
619 * If we are forcing link and we are receiving /C/ ordered
620 * sets, re-enable auto-negotiation in the TXCW register
621 * and disable forced link in the Device Control register
622 * in an attempt to auto-negotiate with our link partner.
624 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
625 ew32(TXCW, mac->txcw);
626 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
628 mac->serdes_has_link = true;
629 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
631 * If we force link for non-auto-negotiation switch, check
632 * link status based on MAC synchronization for internal
635 /* SYNCH bit and IV bit are sticky. */
638 if (rxcw & E1000_RXCW_SYNCH) {
639 if (!(rxcw & E1000_RXCW_IV)) {
640 mac->serdes_has_link = true;
641 e_dbg("SERDES: Link up - forced.\n");
644 mac->serdes_has_link = false;
645 e_dbg("SERDES: Link down - force failed.\n");
649 if (E1000_TXCW_ANE & er32(TXCW)) {
650 status = er32(STATUS);
651 if (status & E1000_STATUS_LU) {
652 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
655 if (rxcw & E1000_RXCW_SYNCH) {
656 if (!(rxcw & E1000_RXCW_IV)) {
657 mac->serdes_has_link = true;
658 e_dbg("SERDES: Link up - autoneg "
659 "completed successfully.\n");
661 mac->serdes_has_link = false;
662 e_dbg("SERDES: Link down - invalid"
663 "codewords detected in autoneg.\n");
666 mac->serdes_has_link = false;
667 e_dbg("SERDES: Link down - no sync.\n");
670 mac->serdes_has_link = false;
671 e_dbg("SERDES: Link down - autoneg failed\n");
679 * e1000_set_default_fc_generic - Set flow control default values
680 * @hw: pointer to the HW structure
682 * Read the EEPROM for the default values for flow control and store the
685 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
691 * Read and store word 0x0F of the EEPROM. This word contains bits
692 * that determine the hardware's default PAUSE (flow control) mode,
693 * a bit that determines whether the HW defaults to enabling or
694 * disabling auto-negotiation, and the direction of the
695 * SW defined pins. If there is no SW over-ride of the flow
696 * control setting, then the variable hw->fc will
697 * be initialized based on a value in the EEPROM.
699 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
702 e_dbg("NVM Read Error\n");
706 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
707 hw->fc.requested_mode = e1000_fc_none;
708 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
710 hw->fc.requested_mode = e1000_fc_tx_pause;
712 hw->fc.requested_mode = e1000_fc_full;
718 * e1000e_setup_link - Setup flow control and link settings
719 * @hw: pointer to the HW structure
721 * Determines which flow control settings to use, then configures flow
722 * control. Calls the appropriate media-specific link configuration
723 * function. Assuming the adapter has a valid link partner, a valid link
724 * should be established. Assumes the hardware has previously been reset
725 * and the transmitter and receiver are not enabled.
727 s32 e1000e_setup_link(struct e1000_hw *hw)
729 struct e1000_mac_info *mac = &hw->mac;
733 * In the case of the phy reset being blocked, we already have a link.
734 * We do not need to set it up again.
736 if (e1000_check_reset_block(hw))
740 * If requested flow control is set to default, set flow control
741 * based on the EEPROM flow control settings.
743 if (hw->fc.requested_mode == e1000_fc_default) {
744 ret_val = e1000_set_default_fc_generic(hw);
750 * Save off the requested flow control mode for use later. Depending
751 * on the link partner's capabilities, we may or may not use this mode.
753 hw->fc.current_mode = hw->fc.requested_mode;
755 e_dbg("After fix-ups FlowControl is now = %x\n",
756 hw->fc.current_mode);
758 /* Call the necessary media_type subroutine to configure the link. */
759 ret_val = mac->ops.setup_physical_interface(hw);
764 * Initialize the flow control address, type, and PAUSE timer
765 * registers to their default values. This is done even if flow
766 * control is disabled, because it does not hurt anything to
767 * initialize these registers.
769 e_dbg("Initializing the Flow Control address, type and timer regs\n");
770 ew32(FCT, FLOW_CONTROL_TYPE);
771 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
772 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
774 ew32(FCTTV, hw->fc.pause_time);
776 return e1000e_set_fc_watermarks(hw);
780 * e1000_commit_fc_settings_generic - Configure flow control
781 * @hw: pointer to the HW structure
783 * Write the flow control settings to the Transmit Config Word Register (TXCW)
784 * base on the flow control settings in e1000_mac_info.
786 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
788 struct e1000_mac_info *mac = &hw->mac;
792 * Check for a software override of the flow control settings, and
793 * setup the device accordingly. If auto-negotiation is enabled, then
794 * software will have to set the "PAUSE" bits to the correct value in
795 * the Transmit Config Word Register (TXCW) and re-start auto-
796 * negotiation. However, if auto-negotiation is disabled, then
797 * software will have to manually configure the two flow control enable
798 * bits in the CTRL register.
800 * The possible values of the "fc" parameter are:
801 * 0: Flow control is completely disabled
802 * 1: Rx flow control is enabled (we can receive pause frames,
803 * but not send pause frames).
804 * 2: Tx flow control is enabled (we can send pause frames but we
805 * do not support receiving pause frames).
806 * 3: Both Rx and Tx flow control (symmetric) are enabled.
808 switch (hw->fc.current_mode) {
810 /* Flow control completely disabled by a software over-ride. */
811 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
813 case e1000_fc_rx_pause:
815 * Rx Flow control is enabled and Tx Flow control is disabled
816 * by a software over-ride. Since there really isn't a way to
817 * advertise that we are capable of Rx Pause ONLY, we will
818 * advertise that we support both symmetric and asymmetric Rx
819 * PAUSE. Later, we will disable the adapter's ability to send
822 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
824 case e1000_fc_tx_pause:
826 * Tx Flow control is enabled, and Rx Flow control is disabled,
827 * by a software over-ride.
829 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
833 * Flow control (both Rx and Tx) is enabled by a software
836 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
839 e_dbg("Flow control param set incorrectly\n");
840 return -E1000_ERR_CONFIG;
851 * e1000_poll_fiber_serdes_link_generic - Poll for link up
852 * @hw: pointer to the HW structure
854 * Polls for link up by reading the status register, if link fails to come
855 * up with auto-negotiation, then the link is forced if a signal is detected.
857 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
859 struct e1000_mac_info *mac = &hw->mac;
864 * If we have a signal (the cable is plugged in, or assumed true for
865 * serdes media) then poll for a "Link-Up" indication in the Device
866 * Status Register. Time-out if a link isn't seen in 500 milliseconds
867 * seconds (Auto-negotiation should complete in less than 500
868 * milliseconds even if the other end is doing it in SW).
870 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
872 status = er32(STATUS);
873 if (status & E1000_STATUS_LU)
876 if (i == FIBER_LINK_UP_LIMIT) {
877 e_dbg("Never got a valid link from auto-neg!!!\n");
878 mac->autoneg_failed = 1;
880 * AutoNeg failed to achieve a link, so we'll call
881 * mac->check_for_link. This routine will force the
882 * link up if we detect a signal. This will allow us to
883 * communicate with non-autonegotiating link partners.
885 ret_val = mac->ops.check_for_link(hw);
887 e_dbg("Error while checking for link\n");
890 mac->autoneg_failed = 0;
892 mac->autoneg_failed = 0;
893 e_dbg("Valid Link Found\n");
900 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
901 * @hw: pointer to the HW structure
903 * Configures collision distance and flow control for fiber and serdes
904 * links. Upon successful setup, poll for link.
906 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
913 /* Take the link out of reset */
914 ctrl &= ~E1000_CTRL_LRST;
916 e1000e_config_collision_dist(hw);
918 ret_val = e1000_commit_fc_settings_generic(hw);
923 * Since auto-negotiation is enabled, take the link out of reset (the
924 * link will be in reset, because we previously reset the chip). This
925 * will restart auto-negotiation. If auto-negotiation is successful
926 * then the link-up status bit will be set and the flow control enable
927 * bits (RFCE and TFCE) will be set according to their negotiated value.
929 e_dbg("Auto-negotiation enabled\n");
936 * For these adapters, the SW definable pin 1 is set when the optics
937 * detect a signal. If we have a signal, then poll for a "Link-Up"
940 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
941 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
942 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
944 e_dbg("No signal detected\n");
951 * e1000e_config_collision_dist - Configure collision distance
952 * @hw: pointer to the HW structure
954 * Configures the collision distance to the default value and is used
955 * during link setup. Currently no func pointer exists and all
956 * implementations are handled in the generic version of this function.
958 void e1000e_config_collision_dist(struct e1000_hw *hw)
964 tctl &= ~E1000_TCTL_COLD;
965 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
972 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
973 * @hw: pointer to the HW structure
975 * Sets the flow control high/low threshold (watermark) registers. If
976 * flow control XON frame transmission is enabled, then set XON frame
977 * transmission as well.
979 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
981 u32 fcrtl = 0, fcrth = 0;
984 * Set the flow control receive threshold registers. Normally,
985 * these registers will be set to a default threshold that may be
986 * adjusted later by the driver's runtime code. However, if the
987 * ability to transmit pause frames is not enabled, then these
988 * registers will be set to 0.
990 if (hw->fc.current_mode & e1000_fc_tx_pause) {
992 * We need to set up the Receive Threshold high and low water
993 * marks as well as (optionally) enabling the transmission of
996 fcrtl = hw->fc.low_water;
997 fcrtl |= E1000_FCRTL_XONE;
998 fcrth = hw->fc.high_water;
1007 * e1000e_force_mac_fc - Force the MAC's flow control settings
1008 * @hw: pointer to the HW structure
1010 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1011 * device control register to reflect the adapter settings. TFCE and RFCE
1012 * need to be explicitly set by software when a copper PHY is used because
1013 * autonegotiation is managed by the PHY rather than the MAC. Software must
1014 * also configure these bits when link is forced on a fiber connection.
1016 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
1023 * Because we didn't get link via the internal auto-negotiation
1024 * mechanism (we either forced link or we got link via PHY
1025 * auto-neg), we have to manually enable/disable transmit an
1026 * receive flow control.
1028 * The "Case" statement below enables/disable flow control
1029 * according to the "hw->fc.current_mode" parameter.
1031 * The possible values of the "fc" parameter are:
1032 * 0: Flow control is completely disabled
1033 * 1: Rx flow control is enabled (we can receive pause
1034 * frames but not send pause frames).
1035 * 2: Tx flow control is enabled (we can send pause frames
1036 * frames but we do not receive pause frames).
1037 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1038 * other: No other values should be possible at this point.
1040 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1042 switch (hw->fc.current_mode) {
1044 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1046 case e1000_fc_rx_pause:
1047 ctrl &= (~E1000_CTRL_TFCE);
1048 ctrl |= E1000_CTRL_RFCE;
1050 case e1000_fc_tx_pause:
1051 ctrl &= (~E1000_CTRL_RFCE);
1052 ctrl |= E1000_CTRL_TFCE;
1055 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1058 e_dbg("Flow control param set incorrectly\n");
1059 return -E1000_ERR_CONFIG;
1068 * e1000e_config_fc_after_link_up - Configures flow control after link
1069 * @hw: pointer to the HW structure
1071 * Checks the status of auto-negotiation after link up to ensure that the
1072 * speed and duplex were not forced. If the link needed to be forced, then
1073 * flow control needs to be forced also. If auto-negotiation is enabled
1074 * and did not fail, then we configure flow control based on our link
1077 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1079 struct e1000_mac_info *mac = &hw->mac;
1081 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1085 * Check for the case where we have fiber media and auto-neg failed
1086 * so we had to force link. In this case, we need to force the
1087 * configuration of the MAC to match the "fc" parameter.
1089 if (mac->autoneg_failed) {
1090 if (hw->phy.media_type == e1000_media_type_fiber ||
1091 hw->phy.media_type == e1000_media_type_internal_serdes)
1092 ret_val = e1000e_force_mac_fc(hw);
1094 if (hw->phy.media_type == e1000_media_type_copper)
1095 ret_val = e1000e_force_mac_fc(hw);
1099 e_dbg("Error forcing flow control settings\n");
1104 * Check for the case where we have copper media and auto-neg is
1105 * enabled. In this case, we need to check and see if Auto-Neg
1106 * has completed, and if so, how the PHY and link partner has
1107 * flow control configured.
1109 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1111 * Read the MII Status Register and check to see if AutoNeg
1112 * has completed. We read this twice because this reg has
1113 * some "sticky" (latched) bits.
1115 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1118 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1122 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1123 e_dbg("Copper PHY and Auto Neg "
1124 "has not completed.\n");
1129 * The AutoNeg process has completed, so we now need to
1130 * read both the Auto Negotiation Advertisement
1131 * Register (Address 4) and the Auto_Negotiation Base
1132 * Page Ability Register (Address 5) to determine how
1133 * flow control was negotiated.
1135 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1138 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1143 * Two bits in the Auto Negotiation Advertisement Register
1144 * (Address 4) and two bits in the Auto Negotiation Base
1145 * Page Ability Register (Address 5) determine flow control
1146 * for both the PHY and the link partner. The following
1147 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1148 * 1999, describes these PAUSE resolution bits and how flow
1149 * control is determined based upon these settings.
1150 * NOTE: DC = Don't Care
1152 * LOCAL DEVICE | LINK PARTNER
1153 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1154 *-------|---------|-------|---------|--------------------
1155 * 0 | 0 | DC | DC | e1000_fc_none
1156 * 0 | 1 | 0 | DC | e1000_fc_none
1157 * 0 | 1 | 1 | 0 | e1000_fc_none
1158 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1159 * 1 | 0 | 0 | DC | e1000_fc_none
1160 * 1 | DC | 1 | DC | e1000_fc_full
1161 * 1 | 1 | 0 | 0 | e1000_fc_none
1162 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1164 * Are both PAUSE bits set to 1? If so, this implies
1165 * Symmetric Flow Control is enabled at both ends. The
1166 * ASM_DIR bits are irrelevant per the spec.
1168 * For Symmetric Flow Control:
1170 * LOCAL DEVICE | LINK PARTNER
1171 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1172 *-------|---------|-------|---------|--------------------
1173 * 1 | DC | 1 | DC | E1000_fc_full
1176 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1177 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1179 * Now we need to check if the user selected Rx ONLY
1180 * of pause frames. In this case, we had to advertise
1181 * FULL flow control because we could not advertise Rx
1182 * ONLY. Hence, we must now check to see if we need to
1183 * turn OFF the TRANSMISSION of PAUSE frames.
1185 if (hw->fc.requested_mode == e1000_fc_full) {
1186 hw->fc.current_mode = e1000_fc_full;
1187 e_dbg("Flow Control = FULL.\r\n");
1189 hw->fc.current_mode = e1000_fc_rx_pause;
1190 e_dbg("Flow Control = "
1191 "RX PAUSE frames only.\r\n");
1195 * For receiving PAUSE frames ONLY.
1197 * LOCAL DEVICE | LINK PARTNER
1198 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1199 *-------|---------|-------|---------|--------------------
1200 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1202 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1203 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1204 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1205 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1206 hw->fc.current_mode = e1000_fc_tx_pause;
1207 e_dbg("Flow Control = Tx PAUSE frames only.\r\n");
1210 * For transmitting PAUSE frames ONLY.
1212 * LOCAL DEVICE | LINK PARTNER
1213 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1214 *-------|---------|-------|---------|--------------------
1215 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1217 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1218 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1219 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1220 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1221 hw->fc.current_mode = e1000_fc_rx_pause;
1222 e_dbg("Flow Control = Rx PAUSE frames only.\r\n");
1225 * Per the IEEE spec, at this point flow control
1226 * should be disabled.
1228 hw->fc.current_mode = e1000_fc_none;
1229 e_dbg("Flow Control = NONE.\r\n");
1233 * Now we need to do one last check... If we auto-
1234 * negotiated to HALF DUPLEX, flow control should not be
1235 * enabled per IEEE 802.3 spec.
1237 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1239 e_dbg("Error getting link speed and duplex\n");
1243 if (duplex == HALF_DUPLEX)
1244 hw->fc.current_mode = e1000_fc_none;
1247 * Now we call a subroutine to actually force the MAC
1248 * controller to use the correct flow control settings.
1250 ret_val = e1000e_force_mac_fc(hw);
1252 e_dbg("Error forcing flow control settings\n");
1261 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1262 * @hw: pointer to the HW structure
1263 * @speed: stores the current speed
1264 * @duplex: stores the current duplex
1266 * Read the status register for the current speed/duplex and store the current
1267 * speed and duplex for copper connections.
1269 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1273 status = er32(STATUS);
1274 if (status & E1000_STATUS_SPEED_1000)
1275 *speed = SPEED_1000;
1276 else if (status & E1000_STATUS_SPEED_100)
1281 if (status & E1000_STATUS_FD)
1282 *duplex = FULL_DUPLEX;
1284 *duplex = HALF_DUPLEX;
1286 e_dbg("%u Mbps, %s Duplex\n",
1287 *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10,
1288 *duplex == FULL_DUPLEX ? "Full" : "Half");
1294 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1295 * @hw: pointer to the HW structure
1296 * @speed: stores the current speed
1297 * @duplex: stores the current duplex
1299 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1300 * for fiber/serdes links.
1302 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1304 *speed = SPEED_1000;
1305 *duplex = FULL_DUPLEX;
1311 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1312 * @hw: pointer to the HW structure
1314 * Acquire the HW semaphore to access the PHY or NVM
1316 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1319 s32 timeout = hw->nvm.word_size + 1;
1322 /* Get the SW semaphore */
1323 while (i < timeout) {
1325 if (!(swsm & E1000_SWSM_SMBI))
1333 e_dbg("Driver can't access device - SMBI bit is set.\n");
1334 return -E1000_ERR_NVM;
1337 /* Get the FW semaphore. */
1338 for (i = 0; i < timeout; i++) {
1340 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1342 /* Semaphore acquired if bit latched */
1343 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1350 /* Release semaphores */
1351 e1000e_put_hw_semaphore(hw);
1352 e_dbg("Driver can't access the NVM\n");
1353 return -E1000_ERR_NVM;
1360 * e1000e_put_hw_semaphore - Release hardware semaphore
1361 * @hw: pointer to the HW structure
1363 * Release hardware semaphore used to access the PHY or NVM
1365 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1370 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1375 * e1000e_get_auto_rd_done - Check for auto read completion
1376 * @hw: pointer to the HW structure
1378 * Check EEPROM for Auto Read done bit.
1380 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1384 while (i < AUTO_READ_DONE_TIMEOUT) {
1385 if (er32(EECD) & E1000_EECD_AUTO_RD)
1391 if (i == AUTO_READ_DONE_TIMEOUT) {
1392 e_dbg("Auto read by HW from NVM has not completed.\n");
1393 return -E1000_ERR_RESET;
1400 * e1000e_valid_led_default - Verify a valid default LED config
1401 * @hw: pointer to the HW structure
1402 * @data: pointer to the NVM (EEPROM)
1404 * Read the EEPROM for the current default LED configuration. If the
1405 * LED configuration is not valid, set to a valid LED configuration.
1407 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1411 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1413 e_dbg("NVM Read Error\n");
1417 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1418 *data = ID_LED_DEFAULT;
1424 * e1000e_id_led_init -
1425 * @hw: pointer to the HW structure
1428 s32 e1000e_id_led_init(struct e1000_hw *hw)
1430 struct e1000_mac_info *mac = &hw->mac;
1432 const u32 ledctl_mask = 0x000000FF;
1433 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1434 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1436 const u16 led_mask = 0x0F;
1438 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1442 mac->ledctl_default = er32(LEDCTL);
1443 mac->ledctl_mode1 = mac->ledctl_default;
1444 mac->ledctl_mode2 = mac->ledctl_default;
1446 for (i = 0; i < 4; i++) {
1447 temp = (data >> (i << 2)) & led_mask;
1449 case ID_LED_ON1_DEF2:
1450 case ID_LED_ON1_ON2:
1451 case ID_LED_ON1_OFF2:
1452 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1453 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1455 case ID_LED_OFF1_DEF2:
1456 case ID_LED_OFF1_ON2:
1457 case ID_LED_OFF1_OFF2:
1458 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1459 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1466 case ID_LED_DEF1_ON2:
1467 case ID_LED_ON1_ON2:
1468 case ID_LED_OFF1_ON2:
1469 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1470 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1472 case ID_LED_DEF1_OFF2:
1473 case ID_LED_ON1_OFF2:
1474 case ID_LED_OFF1_OFF2:
1475 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1476 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1488 * e1000e_setup_led_generic - Configures SW controllable LED
1489 * @hw: pointer to the HW structure
1491 * This prepares the SW controllable LED for use and saves the current state
1492 * of the LED so it can be later restored.
1494 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1498 if (hw->mac.ops.setup_led != e1000e_setup_led_generic)
1499 return -E1000_ERR_CONFIG;
1501 if (hw->phy.media_type == e1000_media_type_fiber) {
1502 ledctl = er32(LEDCTL);
1503 hw->mac.ledctl_default = ledctl;
1505 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1506 E1000_LEDCTL_LED0_BLINK |
1507 E1000_LEDCTL_LED0_MODE_MASK);
1508 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1509 E1000_LEDCTL_LED0_MODE_SHIFT);
1510 ew32(LEDCTL, ledctl);
1511 } else if (hw->phy.media_type == e1000_media_type_copper) {
1512 ew32(LEDCTL, hw->mac.ledctl_mode1);
1519 * e1000e_cleanup_led_generic - Set LED config to default operation
1520 * @hw: pointer to the HW structure
1522 * Remove the current LED configuration and set the LED configuration
1523 * to the default value, saved from the EEPROM.
1525 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1527 ew32(LEDCTL, hw->mac.ledctl_default);
1532 * e1000e_blink_led - Blink LED
1533 * @hw: pointer to the HW structure
1535 * Blink the LEDs which are set to be on.
1537 s32 e1000e_blink_led(struct e1000_hw *hw)
1539 u32 ledctl_blink = 0;
1542 if (hw->phy.media_type == e1000_media_type_fiber) {
1543 /* always blink LED0 for PCI-E fiber */
1544 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1545 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1548 * set the blink bit for each LED that's "on" (0x0E)
1551 ledctl_blink = hw->mac.ledctl_mode2;
1552 for (i = 0; i < 4; i++)
1553 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1554 E1000_LEDCTL_MODE_LED_ON)
1555 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1559 ew32(LEDCTL, ledctl_blink);
1565 * e1000e_led_on_generic - Turn LED on
1566 * @hw: pointer to the HW structure
1570 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1574 switch (hw->phy.media_type) {
1575 case e1000_media_type_fiber:
1577 ctrl &= ~E1000_CTRL_SWDPIN0;
1578 ctrl |= E1000_CTRL_SWDPIO0;
1581 case e1000_media_type_copper:
1582 ew32(LEDCTL, hw->mac.ledctl_mode2);
1592 * e1000e_led_off_generic - Turn LED off
1593 * @hw: pointer to the HW structure
1597 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1601 switch (hw->phy.media_type) {
1602 case e1000_media_type_fiber:
1604 ctrl |= E1000_CTRL_SWDPIN0;
1605 ctrl |= E1000_CTRL_SWDPIO0;
1608 case e1000_media_type_copper:
1609 ew32(LEDCTL, hw->mac.ledctl_mode1);
1619 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1620 * @hw: pointer to the HW structure
1621 * @no_snoop: bitmap of snoop events
1623 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1625 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1631 gcr &= ~(PCIE_NO_SNOOP_ALL);
1638 * e1000e_disable_pcie_master - Disables PCI-express master access
1639 * @hw: pointer to the HW structure
1641 * Returns 0 if successful, else returns -10
1642 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1643 * the master requests to be disabled.
1645 * Disables PCI-Express master access and verifies there are no pending
1648 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1651 s32 timeout = MASTER_DISABLE_TIMEOUT;
1654 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1658 if (!(er32(STATUS) &
1659 E1000_STATUS_GIO_MASTER_ENABLE))
1666 e_dbg("Master requests are pending.\n");
1667 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1674 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1675 * @hw: pointer to the HW structure
1677 * Reset the Adaptive Interframe Spacing throttle to default values.
1679 void e1000e_reset_adaptive(struct e1000_hw *hw)
1681 struct e1000_mac_info *mac = &hw->mac;
1683 if (!mac->adaptive_ifs) {
1684 e_dbg("Not in Adaptive IFS mode!\n");
1688 mac->current_ifs_val = 0;
1689 mac->ifs_min_val = IFS_MIN;
1690 mac->ifs_max_val = IFS_MAX;
1691 mac->ifs_step_size = IFS_STEP;
1692 mac->ifs_ratio = IFS_RATIO;
1694 mac->in_ifs_mode = false;
1701 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1702 * @hw: pointer to the HW structure
1704 * Update the Adaptive Interframe Spacing Throttle value based on the
1705 * time between transmitted packets and time between collisions.
1707 void e1000e_update_adaptive(struct e1000_hw *hw)
1709 struct e1000_mac_info *mac = &hw->mac;
1711 if (!mac->adaptive_ifs) {
1712 e_dbg("Not in Adaptive IFS mode!\n");
1716 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1717 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1718 mac->in_ifs_mode = true;
1719 if (mac->current_ifs_val < mac->ifs_max_val) {
1720 if (!mac->current_ifs_val)
1721 mac->current_ifs_val = mac->ifs_min_val;
1723 mac->current_ifs_val +=
1725 ew32(AIT, mac->current_ifs_val);
1729 if (mac->in_ifs_mode &&
1730 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1731 mac->current_ifs_val = 0;
1732 mac->in_ifs_mode = false;
1741 * e1000_raise_eec_clk - Raise EEPROM clock
1742 * @hw: pointer to the HW structure
1743 * @eecd: pointer to the EEPROM
1745 * Enable/Raise the EEPROM clock bit.
1747 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1749 *eecd = *eecd | E1000_EECD_SK;
1752 udelay(hw->nvm.delay_usec);
1756 * e1000_lower_eec_clk - Lower EEPROM clock
1757 * @hw: pointer to the HW structure
1758 * @eecd: pointer to the EEPROM
1760 * Clear/Lower the EEPROM clock bit.
1762 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1764 *eecd = *eecd & ~E1000_EECD_SK;
1767 udelay(hw->nvm.delay_usec);
1771 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1772 * @hw: pointer to the HW structure
1773 * @data: data to send to the EEPROM
1774 * @count: number of bits to shift out
1776 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1777 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1778 * In order to do this, "data" must be broken down into bits.
1780 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1782 struct e1000_nvm_info *nvm = &hw->nvm;
1783 u32 eecd = er32(EECD);
1786 mask = 0x01 << (count - 1);
1787 if (nvm->type == e1000_nvm_eeprom_spi)
1788 eecd |= E1000_EECD_DO;
1791 eecd &= ~E1000_EECD_DI;
1794 eecd |= E1000_EECD_DI;
1799 udelay(nvm->delay_usec);
1801 e1000_raise_eec_clk(hw, &eecd);
1802 e1000_lower_eec_clk(hw, &eecd);
1807 eecd &= ~E1000_EECD_DI;
1812 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1813 * @hw: pointer to the HW structure
1814 * @count: number of bits to shift in
1816 * In order to read a register from the EEPROM, we need to shift 'count' bits
1817 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1818 * the EEPROM (setting the SK bit), and then reading the value of the data out
1819 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1822 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1830 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1833 for (i = 0; i < count; i++) {
1835 e1000_raise_eec_clk(hw, &eecd);
1839 eecd &= ~E1000_EECD_DI;
1840 if (eecd & E1000_EECD_DO)
1843 e1000_lower_eec_clk(hw, &eecd);
1850 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1851 * @hw: pointer to the HW structure
1852 * @ee_reg: EEPROM flag for polling
1854 * Polls the EEPROM status bit for either read or write completion based
1855 * upon the value of 'ee_reg'.
1857 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1859 u32 attempts = 100000;
1862 for (i = 0; i < attempts; i++) {
1863 if (ee_reg == E1000_NVM_POLL_READ)
1868 if (reg & E1000_NVM_RW_REG_DONE)
1874 return -E1000_ERR_NVM;
1878 * e1000e_acquire_nvm - Generic request for access to EEPROM
1879 * @hw: pointer to the HW structure
1881 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1882 * Return successful if access grant bit set, else clear the request for
1883 * EEPROM access and return -E1000_ERR_NVM (-1).
1885 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1887 u32 eecd = er32(EECD);
1888 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1890 ew32(EECD, eecd | E1000_EECD_REQ);
1894 if (eecd & E1000_EECD_GNT)
1902 eecd &= ~E1000_EECD_REQ;
1904 e_dbg("Could not acquire NVM grant\n");
1905 return -E1000_ERR_NVM;
1912 * e1000_standby_nvm - Return EEPROM to standby state
1913 * @hw: pointer to the HW structure
1915 * Return the EEPROM to a standby state.
1917 static void e1000_standby_nvm(struct e1000_hw *hw)
1919 struct e1000_nvm_info *nvm = &hw->nvm;
1920 u32 eecd = er32(EECD);
1922 if (nvm->type == e1000_nvm_eeprom_spi) {
1923 /* Toggle CS to flush commands */
1924 eecd |= E1000_EECD_CS;
1927 udelay(nvm->delay_usec);
1928 eecd &= ~E1000_EECD_CS;
1931 udelay(nvm->delay_usec);
1936 * e1000_stop_nvm - Terminate EEPROM command
1937 * @hw: pointer to the HW structure
1939 * Terminates the current command by inverting the EEPROM's chip select pin.
1941 static void e1000_stop_nvm(struct e1000_hw *hw)
1946 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1948 eecd |= E1000_EECD_CS;
1949 e1000_lower_eec_clk(hw, &eecd);
1954 * e1000e_release_nvm - Release exclusive access to EEPROM
1955 * @hw: pointer to the HW structure
1957 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1959 void e1000e_release_nvm(struct e1000_hw *hw)
1966 eecd &= ~E1000_EECD_REQ;
1971 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1972 * @hw: pointer to the HW structure
1974 * Setups the EEPROM for reading and writing.
1976 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1978 struct e1000_nvm_info *nvm = &hw->nvm;
1979 u32 eecd = er32(EECD);
1983 if (nvm->type == e1000_nvm_eeprom_spi) {
1984 /* Clear SK and CS */
1985 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1988 timeout = NVM_MAX_RETRY_SPI;
1991 * Read "Status Register" repeatedly until the LSB is cleared.
1992 * The EEPROM will signal that the command has been completed
1993 * by clearing bit 0 of the internal status register. If it's
1994 * not cleared within 'timeout', then error out.
1997 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
1998 hw->nvm.opcode_bits);
1999 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
2000 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
2004 e1000_standby_nvm(hw);
2009 e_dbg("SPI NVM Status error\n");
2010 return -E1000_ERR_NVM;
2018 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
2019 * @hw: pointer to the HW structure
2020 * @offset: offset of word in the EEPROM to read
2021 * @words: number of words to read
2022 * @data: word read from the EEPROM
2024 * Reads a 16 bit word from the EEPROM using the EERD register.
2026 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2028 struct e1000_nvm_info *nvm = &hw->nvm;
2033 * A check for invalid values: offset too large, too many words,
2034 * too many words for the offset, and not enough words.
2036 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2038 e_dbg("nvm parameter(s) out of bounds\n");
2039 return -E1000_ERR_NVM;
2042 for (i = 0; i < words; i++) {
2043 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
2044 E1000_NVM_RW_REG_START;
2047 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
2051 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
2058 * e1000e_write_nvm_spi - Write to EEPROM using SPI
2059 * @hw: pointer to the HW structure
2060 * @offset: offset within the EEPROM to be written to
2061 * @words: number of words to write
2062 * @data: 16 bit word(s) to be written to the EEPROM
2064 * Writes data to EEPROM at offset using SPI interface.
2066 * If e1000e_update_nvm_checksum is not called after this function , the
2067 * EEPROM will most likely contain an invalid checksum.
2069 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2071 struct e1000_nvm_info *nvm = &hw->nvm;
2076 * A check for invalid values: offset too large, too many words,
2077 * and not enough words.
2079 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2081 e_dbg("nvm parameter(s) out of bounds\n");
2082 return -E1000_ERR_NVM;
2085 ret_val = nvm->ops.acquire(hw);
2091 while (widx < words) {
2092 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
2094 ret_val = e1000_ready_nvm_eeprom(hw);
2096 nvm->ops.release(hw);
2100 e1000_standby_nvm(hw);
2102 /* Send the WRITE ENABLE command (8 bit opcode) */
2103 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2106 e1000_standby_nvm(hw);
2109 * Some SPI eeproms use the 8th address bit embedded in the
2112 if ((nvm->address_bits == 8) && (offset >= 128))
2113 write_opcode |= NVM_A8_OPCODE_SPI;
2115 /* Send the Write command (8-bit opcode + addr) */
2116 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2117 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2120 /* Loop to allow for up to whole page write of eeprom */
2121 while (widx < words) {
2122 u16 word_out = data[widx];
2123 word_out = (word_out >> 8) | (word_out << 8);
2124 e1000_shift_out_eec_bits(hw, word_out, 16);
2127 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2128 e1000_standby_nvm(hw);
2135 nvm->ops.release(hw);
2140 * e1000_read_pba_string_generic - Read device part number
2141 * @hw: pointer to the HW structure
2142 * @pba_num: pointer to device part number
2143 * @pba_num_size: size of part number buffer
2145 * Reads the product board assembly (PBA) number from the EEPROM and stores
2146 * the value in pba_num.
2148 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
2157 if (pba_num == NULL) {
2158 e_dbg("PBA string buffer was null\n");
2159 ret_val = E1000_ERR_INVALID_ARGUMENT;
2163 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2165 e_dbg("NVM Read Error\n");
2169 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
2171 e_dbg("NVM Read Error\n");
2176 * if nvm_data is not ptr guard the PBA must be in legacy format which
2177 * means pba_ptr is actually our second data word for the PBA number
2178 * and we can decode it into an ascii string
2180 if (nvm_data != NVM_PBA_PTR_GUARD) {
2181 e_dbg("NVM PBA number is not stored as string\n");
2183 /* we will need 11 characters to store the PBA */
2184 if (pba_num_size < 11) {
2185 e_dbg("PBA string buffer too small\n");
2186 return E1000_ERR_NO_SPACE;
2189 /* extract hex string from data and pba_ptr */
2190 pba_num[0] = (nvm_data >> 12) & 0xF;
2191 pba_num[1] = (nvm_data >> 8) & 0xF;
2192 pba_num[2] = (nvm_data >> 4) & 0xF;
2193 pba_num[3] = nvm_data & 0xF;
2194 pba_num[4] = (pba_ptr >> 12) & 0xF;
2195 pba_num[5] = (pba_ptr >> 8) & 0xF;
2198 pba_num[8] = (pba_ptr >> 4) & 0xF;
2199 pba_num[9] = pba_ptr & 0xF;
2201 /* put a null character on the end of our string */
2204 /* switch all the data but the '-' to hex char */
2205 for (offset = 0; offset < 10; offset++) {
2206 if (pba_num[offset] < 0xA)
2207 pba_num[offset] += '0';
2208 else if (pba_num[offset] < 0x10)
2209 pba_num[offset] += 'A' - 0xA;
2215 ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length);
2217 e_dbg("NVM Read Error\n");
2221 if (length == 0xFFFF || length == 0) {
2222 e_dbg("NVM PBA number section invalid length\n");
2223 ret_val = E1000_ERR_NVM_PBA_SECTION;
2226 /* check if pba_num buffer is big enough */
2227 if (pba_num_size < (((u32)length * 2) - 1)) {
2228 e_dbg("PBA string buffer too small\n");
2229 ret_val = E1000_ERR_NO_SPACE;
2233 /* trim pba length from start of string */
2237 for (offset = 0; offset < length; offset++) {
2238 ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data);
2240 e_dbg("NVM Read Error\n");
2243 pba_num[offset * 2] = (u8)(nvm_data >> 8);
2244 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
2246 pba_num[offset * 2] = '\0';
2253 * e1000_read_mac_addr_generic - Read device MAC address
2254 * @hw: pointer to the HW structure
2256 * Reads the device MAC address from the EEPROM and stores the value.
2257 * Since devices with two ports use the same EEPROM, we increment the
2258 * last bit in the MAC address for the second port.
2260 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
2266 rar_high = er32(RAH(0));
2267 rar_low = er32(RAL(0));
2269 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
2270 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
2272 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
2273 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
2275 for (i = 0; i < ETH_ALEN; i++)
2276 hw->mac.addr[i] = hw->mac.perm_addr[i];
2282 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2283 * @hw: pointer to the HW structure
2285 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2286 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2288 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2294 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2295 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2297 e_dbg("NVM Read Error\n");
2300 checksum += nvm_data;
2303 if (checksum != (u16) NVM_SUM) {
2304 e_dbg("NVM Checksum Invalid\n");
2305 return -E1000_ERR_NVM;
2312 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2313 * @hw: pointer to the HW structure
2315 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2316 * up to the checksum. Then calculates the EEPROM checksum and writes the
2317 * value to the EEPROM.
2319 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2325 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2326 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2328 e_dbg("NVM Read Error while updating checksum.\n");
2331 checksum += nvm_data;
2333 checksum = (u16) NVM_SUM - checksum;
2334 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2336 e_dbg("NVM Write Error while updating checksum.\n");
2342 * e1000e_reload_nvm - Reloads EEPROM
2343 * @hw: pointer to the HW structure
2345 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2346 * extended control register.
2348 void e1000e_reload_nvm(struct e1000_hw *hw)
2353 ctrl_ext = er32(CTRL_EXT);
2354 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2355 ew32(CTRL_EXT, ctrl_ext);
2360 * e1000_calculate_checksum - Calculate checksum for buffer
2361 * @buffer: pointer to EEPROM
2362 * @length: size of EEPROM to calculate a checksum for
2364 * Calculates the checksum for some buffer on a specified length. The
2365 * checksum calculated is returned.
2367 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2375 for (i = 0; i < length; i++)
2378 return (u8) (0 - sum);
2382 * e1000_mng_enable_host_if - Checks host interface is enabled
2383 * @hw: pointer to the HW structure
2385 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2387 * This function checks whether the HOST IF is enabled for command operation
2388 * and also checks whether the previous command is completed. It busy waits
2389 * in case of previous command is not completed.
2391 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2396 if (!(hw->mac.arc_subsystem_valid)) {
2397 e_dbg("ARC subsystem not valid.\n");
2398 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2401 /* Check that the host interface is enabled. */
2403 if ((hicr & E1000_HICR_EN) == 0) {
2404 e_dbg("E1000_HOST_EN bit disabled.\n");
2405 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2407 /* check the previous command is completed */
2408 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2410 if (!(hicr & E1000_HICR_C))
2415 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2416 e_dbg("Previous command timeout failed .\n");
2417 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2424 * e1000e_check_mng_mode_generic - check management mode
2425 * @hw: pointer to the HW structure
2427 * Reads the firmware semaphore register and returns true (>0) if
2428 * manageability is enabled, else false (0).
2430 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2432 u32 fwsm = er32(FWSM);
2434 return (fwsm & E1000_FWSM_MODE_MASK) ==
2435 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2439 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2440 * @hw: pointer to the HW structure
2442 * Enables packet filtering on transmit packets if manageability is enabled
2443 * and host interface is enabled.
2445 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2447 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2448 u32 *buffer = (u32 *)&hw->mng_cookie;
2450 s32 ret_val, hdr_csum, csum;
2453 hw->mac.tx_pkt_filtering = true;
2455 /* No manageability, no filtering */
2456 if (!e1000e_check_mng_mode(hw)) {
2457 hw->mac.tx_pkt_filtering = false;
2462 * If we can't read from the host interface for whatever
2463 * reason, disable filtering.
2465 ret_val = e1000_mng_enable_host_if(hw);
2467 hw->mac.tx_pkt_filtering = false;
2471 /* Read in the header. Length and offset are in dwords. */
2472 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2473 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2474 for (i = 0; i < len; i++)
2475 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2476 hdr_csum = hdr->checksum;
2478 csum = e1000_calculate_checksum((u8 *)hdr,
2479 E1000_MNG_DHCP_COOKIE_LENGTH);
2481 * If either the checksums or signature don't match, then
2482 * the cookie area isn't considered valid, in which case we
2483 * take the safe route of assuming Tx filtering is enabled.
2485 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2486 hw->mac.tx_pkt_filtering = true;
2490 /* Cookie area is valid, make the final check for filtering. */
2491 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2492 hw->mac.tx_pkt_filtering = false;
2497 return hw->mac.tx_pkt_filtering;
2501 * e1000_mng_write_cmd_header - Writes manageability command header
2502 * @hw: pointer to the HW structure
2503 * @hdr: pointer to the host interface command header
2505 * Writes the command header after does the checksum calculation.
2507 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2508 struct e1000_host_mng_command_header *hdr)
2510 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2512 /* Write the whole command header structure with new checksum. */
2514 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2517 /* Write the relevant command block into the ram area. */
2518 for (i = 0; i < length; i++) {
2519 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2520 *((u32 *) hdr + i));
2528 * e1000_mng_host_if_write - Write to the manageability host interface
2529 * @hw: pointer to the HW structure
2530 * @buffer: pointer to the host interface buffer
2531 * @length: size of the buffer
2532 * @offset: location in the buffer to write to
2533 * @sum: sum of the data (not checksum)
2535 * This function writes the buffer content at the offset given on the host if.
2536 * It also does alignment considerations to do the writes in most efficient
2537 * way. Also fills up the sum of the buffer in *buffer parameter.
2539 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2540 u16 length, u16 offset, u8 *sum)
2543 u8 *bufptr = buffer;
2545 u16 remaining, i, j, prev_bytes;
2547 /* sum = only sum of the data and it is not checksum */
2549 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2550 return -E1000_ERR_PARAM;
2553 prev_bytes = offset & 0x3;
2557 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2558 for (j = prev_bytes; j < sizeof(u32); j++) {
2559 *(tmp + j) = *bufptr++;
2562 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2563 length -= j - prev_bytes;
2567 remaining = length & 0x3;
2568 length -= remaining;
2570 /* Calculate length in DWORDs */
2574 * The device driver writes the relevant command block into the
2577 for (i = 0; i < length; i++) {
2578 for (j = 0; j < sizeof(u32); j++) {
2579 *(tmp + j) = *bufptr++;
2583 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2586 for (j = 0; j < sizeof(u32); j++) {
2588 *(tmp + j) = *bufptr++;
2594 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2601 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2602 * @hw: pointer to the HW structure
2603 * @buffer: pointer to the host interface
2604 * @length: size of the buffer
2606 * Writes the DHCP information to the host interface.
2608 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2610 struct e1000_host_mng_command_header hdr;
2614 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2615 hdr.command_length = length;
2620 /* Enable the host interface */
2621 ret_val = e1000_mng_enable_host_if(hw);
2625 /* Populate the host interface with the contents of "buffer". */
2626 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2627 sizeof(hdr), &(hdr.checksum));
2631 /* Write the manageability command header */
2632 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2636 /* Tell the ARC a new command is pending. */
2638 ew32(HICR, hicr | E1000_HICR_C);
2644 * e1000e_enable_mng_pass_thru - Check if management passthrough is needed
2645 * @hw: pointer to the HW structure
2647 * Verifies the hardware needs to leave interface enabled so that frames can
2648 * be directed to and from the management interface.
2650 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2654 bool ret_val = false;
2658 if (!(manc & E1000_MANC_RCV_TCO_EN))
2661 if (hw->mac.has_fwsm) {
2663 factps = er32(FACTPS);
2665 if (!(factps & E1000_FACTPS_MNGCG) &&
2666 ((fwsm & E1000_FWSM_MODE_MASK) ==
2667 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2671 } else if ((hw->mac.type == e1000_82574) ||
2672 (hw->mac.type == e1000_82583)) {
2675 factps = er32(FACTPS);
2676 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
2678 if (!(factps & E1000_FACTPS_MNGCG) &&
2679 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
2680 (e1000_mng_mode_pt << 13))) {
2684 } else if ((manc & E1000_MANC_SMBUS_EN) &&
2685 !(manc & E1000_MANC_ASF_EN)) {