1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/delay.h>
33 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 ARRAY_SIZE(e1000_m88_cable_length_table)
50 static const u16 e1000_igp_2_cable_length_table[] = {
51 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
52 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
53 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
54 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
55 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
56 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
57 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
60 ARRAY_SIZE(e1000_igp_2_cable_length_table)
62 #define BM_PHY_REG_PAGE(offset) \
63 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
64 #define BM_PHY_REG_NUM(offset) \
65 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
66 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
67 ~MAX_PHY_REG_ADDRESS)))
69 #define HV_INTC_FC_PAGE_START 768
70 #define I82578_ADDR_REG 29
71 #define I82577_ADDR_REG 16
72 #define I82577_CFG_REG 22
73 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
74 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
75 #define I82577_CTRL_REG 23
77 /* 82577 specific PHY registers */
78 #define I82577_PHY_CTRL_2 18
79 #define I82577_PHY_STATUS_2 26
80 #define I82577_PHY_DIAG_STATUS 31
82 /* I82577 PHY Status 2 */
83 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
84 #define I82577_PHY_STATUS2_MDIX 0x0800
85 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
86 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
88 /* I82577 PHY Control 2 */
89 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
90 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
92 /* I82577 PHY Diagnostics Status */
93 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
94 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
96 /* BM PHY Copper Specific Control 1 */
97 #define BM_CS_CTRL1 16
99 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
100 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
101 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
104 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
105 * @hw: pointer to the HW structure
107 * Read the PHY management control register and check whether a PHY reset
108 * is blocked. If a reset is not blocked return 0, otherwise
109 * return E1000_BLK_PHY_RESET (12).
111 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
117 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
118 E1000_BLK_PHY_RESET : 0;
122 * e1000e_get_phy_id - Retrieve the PHY ID and revision
123 * @hw: pointer to the HW structure
125 * Reads the PHY registers and stores the PHY ID and possibly the PHY
126 * revision in the hardware structure.
128 s32 e1000e_get_phy_id(struct e1000_hw *hw)
130 struct e1000_phy_info *phy = &hw->phy;
135 if (!(phy->ops.read_reg))
138 while (retry_count < 2) {
139 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
143 phy->id = (u32)(phy_id << 16);
145 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
149 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
150 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
152 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
162 * e1000e_phy_reset_dsp - Reset PHY DSP
163 * @hw: pointer to the HW structure
165 * Reset the digital signal processor.
167 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
171 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
175 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
179 * e1000e_read_phy_reg_mdic - Read MDI control register
180 * @hw: pointer to the HW structure
181 * @offset: register offset to be read
182 * @data: pointer to the read data
184 * Reads the MDI control register in the PHY at offset and stores the
185 * information read to data.
187 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
189 struct e1000_phy_info *phy = &hw->phy;
192 if (offset > MAX_PHY_REG_ADDRESS) {
193 e_dbg("PHY Address %d is out of range\n", offset);
194 return -E1000_ERR_PARAM;
198 * Set up Op-code, Phy Address, and register offset in the MDI
199 * Control register. The MAC will take care of interfacing with the
200 * PHY to retrieve the desired data.
202 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
203 (phy->addr << E1000_MDIC_PHY_SHIFT) |
204 (E1000_MDIC_OP_READ));
209 * Poll the ready bit to see if the MDI read completed
210 * Increasing the time out as testing showed failures with
213 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
216 if (mdic & E1000_MDIC_READY)
219 if (!(mdic & E1000_MDIC_READY)) {
220 e_dbg("MDI Read did not complete\n");
221 return -E1000_ERR_PHY;
223 if (mdic & E1000_MDIC_ERROR) {
224 e_dbg("MDI Error\n");
225 return -E1000_ERR_PHY;
230 * Allow some time after each MDIC transaction to avoid
231 * reading duplicate data in the next MDIC transaction.
233 if (hw->mac.type == e1000_pch2lan)
240 * e1000e_write_phy_reg_mdic - Write MDI control register
241 * @hw: pointer to the HW structure
242 * @offset: register offset to write to
243 * @data: data to write to register at offset
245 * Writes data to MDI control register in the PHY at offset.
247 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
249 struct e1000_phy_info *phy = &hw->phy;
252 if (offset > MAX_PHY_REG_ADDRESS) {
253 e_dbg("PHY Address %d is out of range\n", offset);
254 return -E1000_ERR_PARAM;
258 * Set up Op-code, Phy Address, and register offset in the MDI
259 * Control register. The MAC will take care of interfacing with the
260 * PHY to retrieve the desired data.
262 mdic = (((u32)data) |
263 (offset << E1000_MDIC_REG_SHIFT) |
264 (phy->addr << E1000_MDIC_PHY_SHIFT) |
265 (E1000_MDIC_OP_WRITE));
270 * Poll the ready bit to see if the MDI read completed
271 * Increasing the time out as testing showed failures with
274 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
277 if (mdic & E1000_MDIC_READY)
280 if (!(mdic & E1000_MDIC_READY)) {
281 e_dbg("MDI Write did not complete\n");
282 return -E1000_ERR_PHY;
284 if (mdic & E1000_MDIC_ERROR) {
285 e_dbg("MDI Error\n");
286 return -E1000_ERR_PHY;
290 * Allow some time after each MDIC transaction to avoid
291 * reading duplicate data in the next MDIC transaction.
293 if (hw->mac.type == e1000_pch2lan)
300 * e1000e_read_phy_reg_m88 - Read m88 PHY register
301 * @hw: pointer to the HW structure
302 * @offset: register offset to be read
303 * @data: pointer to the read data
305 * Acquires semaphore, if necessary, then reads the PHY register at offset
306 * and storing the retrieved information in data. Release any acquired
307 * semaphores before exiting.
309 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
313 ret_val = hw->phy.ops.acquire(hw);
317 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
320 hw->phy.ops.release(hw);
326 * e1000e_write_phy_reg_m88 - Write m88 PHY register
327 * @hw: pointer to the HW structure
328 * @offset: register offset to write to
329 * @data: data to write at register offset
331 * Acquires semaphore, if necessary, then writes the data to PHY register
332 * at the offset. Release any acquired semaphores before exiting.
334 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
338 ret_val = hw->phy.ops.acquire(hw);
342 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
345 hw->phy.ops.release(hw);
351 * __e1000e_read_phy_reg_igp - Read igp PHY register
352 * @hw: pointer to the HW structure
353 * @offset: register offset to be read
354 * @data: pointer to the read data
355 * @locked: semaphore has already been acquired or not
357 * Acquires semaphore, if necessary, then reads the PHY register at offset
358 * and stores the retrieved information in data. Release any acquired
359 * semaphores before exiting.
361 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
367 if (!(hw->phy.ops.acquire))
370 ret_val = hw->phy.ops.acquire(hw);
375 if (offset > MAX_PHY_MULTI_PAGE_REG) {
376 ret_val = e1000e_write_phy_reg_mdic(hw,
377 IGP01E1000_PHY_PAGE_SELECT,
383 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
388 hw->phy.ops.release(hw);
394 * e1000e_read_phy_reg_igp - Read igp PHY register
395 * @hw: pointer to the HW structure
396 * @offset: register offset to be read
397 * @data: pointer to the read data
399 * Acquires semaphore then reads the PHY register at offset and stores the
400 * retrieved information in data.
401 * Release the acquired semaphore before exiting.
403 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
405 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
409 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
410 * @hw: pointer to the HW structure
411 * @offset: register offset to be read
412 * @data: pointer to the read data
414 * Reads the PHY register at offset and stores the retrieved information
415 * in data. Assumes semaphore already acquired.
417 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
419 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
423 * e1000e_write_phy_reg_igp - Write igp PHY register
424 * @hw: pointer to the HW structure
425 * @offset: register offset to write to
426 * @data: data to write at register offset
427 * @locked: semaphore has already been acquired or not
429 * Acquires semaphore, if necessary, then writes the data to PHY register
430 * at the offset. Release any acquired semaphores before exiting.
432 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
438 if (!(hw->phy.ops.acquire))
441 ret_val = hw->phy.ops.acquire(hw);
446 if (offset > MAX_PHY_MULTI_PAGE_REG) {
447 ret_val = e1000e_write_phy_reg_mdic(hw,
448 IGP01E1000_PHY_PAGE_SELECT,
454 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
459 hw->phy.ops.release(hw);
466 * e1000e_write_phy_reg_igp - Write igp PHY register
467 * @hw: pointer to the HW structure
468 * @offset: register offset to write to
469 * @data: data to write at register offset
471 * Acquires semaphore then writes the data to PHY register
472 * at the offset. Release any acquired semaphores before exiting.
474 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
476 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
480 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
481 * @hw: pointer to the HW structure
482 * @offset: register offset to write to
483 * @data: data to write at register offset
485 * Writes the data to PHY register at the offset.
486 * Assumes semaphore already acquired.
488 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
490 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
494 * __e1000_read_kmrn_reg - Read kumeran register
495 * @hw: pointer to the HW structure
496 * @offset: register offset to be read
497 * @data: pointer to the read data
498 * @locked: semaphore has already been acquired or not
500 * Acquires semaphore, if necessary. Then reads the PHY register at offset
501 * using the kumeran interface. The information retrieved is stored in data.
502 * Release any acquired semaphores before exiting.
504 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
511 if (!(hw->phy.ops.acquire))
514 ret_val = hw->phy.ops.acquire(hw);
519 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
520 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
521 ew32(KMRNCTRLSTA, kmrnctrlsta);
525 kmrnctrlsta = er32(KMRNCTRLSTA);
526 *data = (u16)kmrnctrlsta;
529 hw->phy.ops.release(hw);
536 * e1000e_read_kmrn_reg - Read kumeran register
537 * @hw: pointer to the HW structure
538 * @offset: register offset to be read
539 * @data: pointer to the read data
541 * Acquires semaphore then reads the PHY register at offset using the
542 * kumeran interface. The information retrieved is stored in data.
543 * Release the acquired semaphore before exiting.
545 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
547 return __e1000_read_kmrn_reg(hw, offset, data, false);
551 * e1000e_read_kmrn_reg_locked - Read kumeran register
552 * @hw: pointer to the HW structure
553 * @offset: register offset to be read
554 * @data: pointer to the read data
556 * Reads the PHY register at offset using the kumeran interface. The
557 * information retrieved is stored in data.
558 * Assumes semaphore already acquired.
560 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
562 return __e1000_read_kmrn_reg(hw, offset, data, true);
566 * __e1000_write_kmrn_reg - Write kumeran register
567 * @hw: pointer to the HW structure
568 * @offset: register offset to write to
569 * @data: data to write at register offset
570 * @locked: semaphore has already been acquired or not
572 * Acquires semaphore, if necessary. Then write the data to PHY register
573 * at the offset using the kumeran interface. Release any acquired semaphores
576 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
583 if (!(hw->phy.ops.acquire))
586 ret_val = hw->phy.ops.acquire(hw);
591 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
592 E1000_KMRNCTRLSTA_OFFSET) | data;
593 ew32(KMRNCTRLSTA, kmrnctrlsta);
598 hw->phy.ops.release(hw);
605 * e1000e_write_kmrn_reg - Write kumeran register
606 * @hw: pointer to the HW structure
607 * @offset: register offset to write to
608 * @data: data to write at register offset
610 * Acquires semaphore then writes the data to the PHY register at the offset
611 * using the kumeran interface. Release the acquired semaphore before exiting.
613 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
615 return __e1000_write_kmrn_reg(hw, offset, data, false);
619 * e1000e_write_kmrn_reg_locked - Write kumeran register
620 * @hw: pointer to the HW structure
621 * @offset: register offset to write to
622 * @data: data to write at register offset
624 * Write the data to PHY register at the offset using the kumeran interface.
625 * Assumes semaphore already acquired.
627 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
629 return __e1000_write_kmrn_reg(hw, offset, data, true);
633 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
634 * @hw: pointer to the HW structure
636 * Sets up Carrier-sense on Transmit and downshift values.
638 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
640 struct e1000_phy_info *phy = &hw->phy;
644 /* Enable CRS on TX. This must be set for half-duplex operation. */
645 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data);
649 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
651 /* Enable downshift */
652 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
654 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data);
661 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
662 * @hw: pointer to the HW structure
664 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
665 * and downshift values are set also.
667 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
669 struct e1000_phy_info *phy = &hw->phy;
673 /* Enable CRS on Tx. This must be set for half-duplex operation. */
674 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
678 /* For BM PHY this bit is downshift enable */
679 if (phy->type != e1000_phy_bm)
680 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
684 * MDI/MDI-X = 0 (default)
685 * 0 - Auto for all speeds
688 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
690 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
694 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
697 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
700 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
704 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
710 * disable_polarity_correction = 0 (default)
711 * Automatic Correction for Reversed Cable Polarity
715 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
716 if (phy->disable_polarity_correction == 1)
717 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
719 /* Enable downshift on BM (disabled by default) */
720 if (phy->type == e1000_phy_bm)
721 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
723 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
727 if ((phy->type == e1000_phy_m88) &&
728 (phy->revision < E1000_REVISION_4) &&
729 (phy->id != BME1000_E_PHY_ID_R2)) {
731 * Force TX_CLK in the Extended PHY Specific Control Register
734 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
738 phy_data |= M88E1000_EPSCR_TX_CLK_25;
740 if ((phy->revision == 2) &&
741 (phy->id == M88E1111_I_PHY_ID)) {
742 /* 82573L PHY - set the downshift counter to 5x. */
743 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
744 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
746 /* Configure Master and Slave downshift values */
747 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
748 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
749 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
750 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
752 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
757 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
758 /* Set PHY page 0, register 29 to 0x0003 */
759 ret_val = e1e_wphy(hw, 29, 0x0003);
763 /* Set PHY page 0, register 30 to 0x0000 */
764 ret_val = e1e_wphy(hw, 30, 0x0000);
769 /* Commit the changes. */
770 ret_val = e1000e_commit_phy(hw);
772 e_dbg("Error committing the PHY changes\n");
776 if (phy->type == e1000_phy_82578) {
777 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
782 /* 82578 PHY - set the downshift count to 1x. */
783 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
784 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
785 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
795 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
796 * @hw: pointer to the HW structure
798 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
801 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
803 struct e1000_phy_info *phy = &hw->phy;
807 ret_val = e1000_phy_hw_reset(hw);
809 e_dbg("Error resetting the PHY.\n");
814 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
815 * timeout issues when LFS is enabled.
819 /* disable lplu d0 during driver init */
820 ret_val = e1000_set_d0_lplu_state(hw, false);
822 e_dbg("Error Disabling LPLU D0\n");
825 /* Configure mdi-mdix settings */
826 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
830 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
834 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
837 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
841 data |= IGP01E1000_PSCR_AUTO_MDIX;
844 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
848 /* set auto-master slave resolution settings */
849 if (hw->mac.autoneg) {
851 * when autonegotiation advertisement is only 1000Mbps then we
852 * should disable SmartSpeed and enable Auto MasterSlave
853 * resolution as hardware default.
855 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
856 /* Disable SmartSpeed */
857 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
862 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
863 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
868 /* Set auto Master/Slave resolution process */
869 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
873 data &= ~CR_1000T_MS_ENABLE;
874 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
879 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
883 /* load defaults for future use */
884 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
885 ((data & CR_1000T_MS_VALUE) ?
886 e1000_ms_force_master :
887 e1000_ms_force_slave) :
890 switch (phy->ms_type) {
891 case e1000_ms_force_master:
892 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
894 case e1000_ms_force_slave:
895 data |= CR_1000T_MS_ENABLE;
896 data &= ~(CR_1000T_MS_VALUE);
899 data &= ~CR_1000T_MS_ENABLE;
903 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
910 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
911 * @hw: pointer to the HW structure
913 * Reads the MII auto-neg advertisement register and/or the 1000T control
914 * register and if the PHY is already setup for auto-negotiation, then
915 * return successful. Otherwise, setup advertisement and flow control to
916 * the appropriate values for the wanted auto-negotiation.
918 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
920 struct e1000_phy_info *phy = &hw->phy;
922 u16 mii_autoneg_adv_reg;
923 u16 mii_1000t_ctrl_reg = 0;
925 phy->autoneg_advertised &= phy->autoneg_mask;
927 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
928 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
932 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
933 /* Read the MII 1000Base-T Control Register (Address 9). */
934 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
940 * Need to parse both autoneg_advertised and fc and set up
941 * the appropriate PHY registers. First we will parse for
942 * autoneg_advertised software override. Since we can advertise
943 * a plethora of combinations, we need to check each bit
948 * First we clear all the 10/100 mb speed bits in the Auto-Neg
949 * Advertisement Register (Address 4) and the 1000 mb speed bits in
950 * the 1000Base-T Control Register (Address 9).
952 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
953 NWAY_AR_100TX_HD_CAPS |
954 NWAY_AR_10T_FD_CAPS |
955 NWAY_AR_10T_HD_CAPS);
956 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
958 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
960 /* Do we want to advertise 10 Mb Half Duplex? */
961 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
962 e_dbg("Advertise 10mb Half duplex\n");
963 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
966 /* Do we want to advertise 10 Mb Full Duplex? */
967 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
968 e_dbg("Advertise 10mb Full duplex\n");
969 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
972 /* Do we want to advertise 100 Mb Half Duplex? */
973 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
974 e_dbg("Advertise 100mb Half duplex\n");
975 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
978 /* Do we want to advertise 100 Mb Full Duplex? */
979 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
980 e_dbg("Advertise 100mb Full duplex\n");
981 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
984 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
985 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
986 e_dbg("Advertise 1000mb Half duplex request denied!\n");
988 /* Do we want to advertise 1000 Mb Full Duplex? */
989 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
990 e_dbg("Advertise 1000mb Full duplex\n");
991 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
995 * Check for a software override of the flow control settings, and
996 * setup the PHY advertisement registers accordingly. If
997 * auto-negotiation is enabled, then software will have to set the
998 * "PAUSE" bits to the correct value in the Auto-Negotiation
999 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1002 * The possible values of the "fc" parameter are:
1003 * 0: Flow control is completely disabled
1004 * 1: Rx flow control is enabled (we can receive pause frames
1005 * but not send pause frames).
1006 * 2: Tx flow control is enabled (we can send pause frames
1007 * but we do not support receiving pause frames).
1008 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1009 * other: No software override. The flow control configuration
1010 * in the EEPROM is used.
1012 switch (hw->fc.current_mode) {
1015 * Flow control (Rx & Tx) is completely disabled by a
1016 * software over-ride.
1018 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1020 case e1000_fc_rx_pause:
1022 * Rx Flow control is enabled, and Tx Flow control is
1023 * disabled, by a software over-ride.
1025 * Since there really isn't a way to advertise that we are
1026 * capable of Rx Pause ONLY, we will advertise that we
1027 * support both symmetric and asymmetric Rx PAUSE. Later
1028 * (in e1000e_config_fc_after_link_up) we will disable the
1029 * hw's ability to send PAUSE frames.
1031 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1033 case e1000_fc_tx_pause:
1035 * Tx Flow control is enabled, and Rx Flow control is
1036 * disabled, by a software over-ride.
1038 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1039 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1043 * Flow control (both Rx and Tx) is enabled by a software
1046 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1049 e_dbg("Flow control param set incorrectly\n");
1050 ret_val = -E1000_ERR_CONFIG;
1054 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1058 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1060 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1061 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1067 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1068 * @hw: pointer to the HW structure
1070 * Performs initial bounds checking on autoneg advertisement parameter, then
1071 * configure to advertise the full capability. Setup the PHY to autoneg
1072 * and restart the negotiation process between the link partner. If
1073 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1075 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1077 struct e1000_phy_info *phy = &hw->phy;
1082 * Perform some bounds checking on the autoneg advertisement
1085 phy->autoneg_advertised &= phy->autoneg_mask;
1088 * If autoneg_advertised is zero, we assume it was not defaulted
1089 * by the calling code so we set to advertise full capability.
1091 if (phy->autoneg_advertised == 0)
1092 phy->autoneg_advertised = phy->autoneg_mask;
1094 e_dbg("Reconfiguring auto-neg advertisement params\n");
1095 ret_val = e1000_phy_setup_autoneg(hw);
1097 e_dbg("Error Setting up Auto-Negotiation\n");
1100 e_dbg("Restarting Auto-Neg\n");
1103 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1104 * the Auto Neg Restart bit in the PHY control register.
1106 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1110 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1111 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1116 * Does the user want to wait for Auto-Neg to complete here, or
1117 * check at a later time (for example, callback routine).
1119 if (phy->autoneg_wait_to_complete) {
1120 ret_val = e1000_wait_autoneg(hw);
1122 e_dbg("Error while waiting for "
1123 "autoneg to complete\n");
1128 hw->mac.get_link_status = 1;
1134 * e1000e_setup_copper_link - Configure copper link settings
1135 * @hw: pointer to the HW structure
1137 * Calls the appropriate function to configure the link for auto-neg or forced
1138 * speed and duplex. Then we check for link, once link is established calls
1139 * to configure collision distance and flow control are called. If link is
1140 * not established, we return -E1000_ERR_PHY (-2).
1142 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1147 if (hw->mac.autoneg) {
1149 * Setup autoneg and flow control advertisement and perform
1152 ret_val = e1000_copper_link_autoneg(hw);
1157 * PHY will be set to 10H, 10F, 100H or 100F
1158 * depending on user settings.
1160 e_dbg("Forcing Speed and Duplex\n");
1161 ret_val = e1000_phy_force_speed_duplex(hw);
1163 e_dbg("Error Forcing Speed and Duplex\n");
1169 * Check link status. Wait up to 100 microseconds for link to become
1172 ret_val = e1000e_phy_has_link_generic(hw,
1173 COPPER_LINK_UP_LIMIT,
1180 e_dbg("Valid link established!!!\n");
1181 e1000e_config_collision_dist(hw);
1182 ret_val = e1000e_config_fc_after_link_up(hw);
1184 e_dbg("Unable to establish link!!!\n");
1191 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1192 * @hw: pointer to the HW structure
1194 * Calls the PHY setup function to force speed and duplex. Clears the
1195 * auto-crossover to force MDI manually. Waits for link and returns
1196 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1198 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1200 struct e1000_phy_info *phy = &hw->phy;
1205 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1209 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1211 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1216 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1217 * forced whenever speed and duplex are forced.
1219 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1223 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1224 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1226 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1230 e_dbg("IGP PSCR: %X\n", phy_data);
1234 if (phy->autoneg_wait_to_complete) {
1235 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1237 ret_val = e1000e_phy_has_link_generic(hw,
1245 e_dbg("Link taking longer than expected.\n");
1248 ret_val = e1000e_phy_has_link_generic(hw,
1260 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1261 * @hw: pointer to the HW structure
1263 * Calls the PHY setup function to force speed and duplex. Clears the
1264 * auto-crossover to force MDI manually. Resets the PHY to commit the
1265 * changes. If time expires while waiting for link up, we reset the DSP.
1266 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1267 * successful completion, else return corresponding error code.
1269 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1271 struct e1000_phy_info *phy = &hw->phy;
1277 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1278 * forced whenever speed and duplex are forced.
1280 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1284 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1285 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1289 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1291 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1295 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1297 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1301 /* Reset the phy to commit changes. */
1302 ret_val = e1000e_commit_phy(hw);
1306 if (phy->autoneg_wait_to_complete) {
1307 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1309 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1315 if (hw->phy.type != e1000_phy_m88) {
1316 e_dbg("Link taking longer than expected.\n");
1319 * We didn't get link.
1320 * Reset the DSP and cross our fingers.
1322 ret_val = e1e_wphy(hw,
1323 M88E1000_PHY_PAGE_SELECT,
1327 ret_val = e1000e_phy_reset_dsp(hw);
1334 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1340 if (hw->phy.type != e1000_phy_m88)
1343 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1348 * Resetting the phy means we need to re-force TX_CLK in the
1349 * Extended PHY Specific Control Register to 25MHz clock from
1350 * the reset value of 2.5MHz.
1352 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1353 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1358 * In addition, we must re-enable CRS on Tx for both half and full
1361 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1365 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1366 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1372 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1373 * @hw: pointer to the HW structure
1375 * Forces the speed and duplex settings of the PHY.
1376 * This is a function pointer entry point only called by
1377 * PHY setup routines.
1379 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1381 struct e1000_phy_info *phy = &hw->phy;
1386 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1390 e1000e_phy_force_speed_duplex_setup(hw, &data);
1392 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1396 /* Disable MDI-X support for 10/100 */
1397 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1401 data &= ~IFE_PMC_AUTO_MDIX;
1402 data &= ~IFE_PMC_FORCE_MDIX;
1404 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1408 e_dbg("IFE PMC: %X\n", data);
1412 if (phy->autoneg_wait_to_complete) {
1413 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1415 ret_val = e1000e_phy_has_link_generic(hw,
1423 e_dbg("Link taking longer than expected.\n");
1426 ret_val = e1000e_phy_has_link_generic(hw,
1439 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1440 * @hw: pointer to the HW structure
1441 * @phy_ctrl: pointer to current value of PHY_CONTROL
1443 * Forces speed and duplex on the PHY by doing the following: disable flow
1444 * control, force speed/duplex on the MAC, disable auto speed detection,
1445 * disable auto-negotiation, configure duplex, configure speed, configure
1446 * the collision distance, write configuration to CTRL register. The
1447 * caller must write to the PHY_CONTROL register for these settings to
1450 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1452 struct e1000_mac_info *mac = &hw->mac;
1455 /* Turn off flow control when forcing speed/duplex */
1456 hw->fc.current_mode = e1000_fc_none;
1458 /* Force speed/duplex on the mac */
1460 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1461 ctrl &= ~E1000_CTRL_SPD_SEL;
1463 /* Disable Auto Speed Detection */
1464 ctrl &= ~E1000_CTRL_ASDE;
1466 /* Disable autoneg on the phy */
1467 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1469 /* Forcing Full or Half Duplex? */
1470 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1471 ctrl &= ~E1000_CTRL_FD;
1472 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1473 e_dbg("Half Duplex\n");
1475 ctrl |= E1000_CTRL_FD;
1476 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1477 e_dbg("Full Duplex\n");
1480 /* Forcing 10mb or 100mb? */
1481 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1482 ctrl |= E1000_CTRL_SPD_100;
1483 *phy_ctrl |= MII_CR_SPEED_100;
1484 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1485 e_dbg("Forcing 100mb\n");
1487 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1488 *phy_ctrl |= MII_CR_SPEED_10;
1489 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1490 e_dbg("Forcing 10mb\n");
1493 e1000e_config_collision_dist(hw);
1499 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1500 * @hw: pointer to the HW structure
1501 * @active: boolean used to enable/disable lplu
1503 * Success returns 0, Failure returns 1
1505 * The low power link up (lplu) state is set to the power management level D3
1506 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1507 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1508 * is used during Dx states where the power conservation is most important.
1509 * During driver activity, SmartSpeed should be enabled so performance is
1512 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1514 struct e1000_phy_info *phy = &hw->phy;
1518 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1523 data &= ~IGP02E1000_PM_D3_LPLU;
1524 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1528 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1529 * during Dx states where the power conservation is most
1530 * important. During driver activity we should enable
1531 * SmartSpeed, so performance is maintained.
1533 if (phy->smart_speed == e1000_smart_speed_on) {
1534 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1539 data |= IGP01E1000_PSCFR_SMART_SPEED;
1540 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1544 } else if (phy->smart_speed == e1000_smart_speed_off) {
1545 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1550 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1551 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1556 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1557 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1558 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1559 data |= IGP02E1000_PM_D3_LPLU;
1560 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1564 /* When LPLU is enabled, we should disable SmartSpeed */
1565 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1569 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1570 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1577 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1578 * @hw: pointer to the HW structure
1580 * Success returns 0, Failure returns 1
1582 * A downshift is detected by querying the PHY link health.
1584 s32 e1000e_check_downshift(struct e1000_hw *hw)
1586 struct e1000_phy_info *phy = &hw->phy;
1588 u16 phy_data, offset, mask;
1590 switch (phy->type) {
1592 case e1000_phy_gg82563:
1594 case e1000_phy_82578:
1595 offset = M88E1000_PHY_SPEC_STATUS;
1596 mask = M88E1000_PSSR_DOWNSHIFT;
1598 case e1000_phy_igp_2:
1599 case e1000_phy_igp_3:
1600 offset = IGP01E1000_PHY_LINK_HEALTH;
1601 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1604 /* speed downshift not supported */
1605 phy->speed_downgraded = false;
1609 ret_val = e1e_rphy(hw, offset, &phy_data);
1612 phy->speed_downgraded = (phy_data & mask);
1618 * e1000_check_polarity_m88 - Checks the polarity.
1619 * @hw: pointer to the HW structure
1621 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1623 * Polarity is determined based on the PHY specific status register.
1625 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1627 struct e1000_phy_info *phy = &hw->phy;
1631 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1634 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1635 ? e1000_rev_polarity_reversed
1636 : e1000_rev_polarity_normal;
1642 * e1000_check_polarity_igp - Checks the polarity.
1643 * @hw: pointer to the HW structure
1645 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1647 * Polarity is determined based on the PHY port status register, and the
1648 * current speed (since there is no polarity at 100Mbps).
1650 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1652 struct e1000_phy_info *phy = &hw->phy;
1654 u16 data, offset, mask;
1657 * Polarity is determined based on the speed of
1660 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1664 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1665 IGP01E1000_PSSR_SPEED_1000MBPS) {
1666 offset = IGP01E1000_PHY_PCS_INIT_REG;
1667 mask = IGP01E1000_PHY_POLARITY_MASK;
1670 * This really only applies to 10Mbps since
1671 * there is no polarity for 100Mbps (always 0).
1673 offset = IGP01E1000_PHY_PORT_STATUS;
1674 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1677 ret_val = e1e_rphy(hw, offset, &data);
1680 phy->cable_polarity = (data & mask)
1681 ? e1000_rev_polarity_reversed
1682 : e1000_rev_polarity_normal;
1688 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1689 * @hw: pointer to the HW structure
1691 * Polarity is determined on the polarity reversal feature being enabled.
1693 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1695 struct e1000_phy_info *phy = &hw->phy;
1697 u16 phy_data, offset, mask;
1700 * Polarity is determined based on the reversal feature being enabled.
1702 if (phy->polarity_correction) {
1703 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1704 mask = IFE_PESC_POLARITY_REVERSED;
1706 offset = IFE_PHY_SPECIAL_CONTROL;
1707 mask = IFE_PSC_FORCE_POLARITY;
1710 ret_val = e1e_rphy(hw, offset, &phy_data);
1713 phy->cable_polarity = (phy_data & mask)
1714 ? e1000_rev_polarity_reversed
1715 : e1000_rev_polarity_normal;
1721 * e1000_wait_autoneg - Wait for auto-neg completion
1722 * @hw: pointer to the HW structure
1724 * Waits for auto-negotiation to complete or for the auto-negotiation time
1725 * limit to expire, which ever happens first.
1727 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1732 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1733 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1734 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1737 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1740 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1746 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1753 * e1000e_phy_has_link_generic - Polls PHY for link
1754 * @hw: pointer to the HW structure
1755 * @iterations: number of times to poll for link
1756 * @usec_interval: delay between polling attempts
1757 * @success: pointer to whether polling was successful or not
1759 * Polls the PHY status register for link, 'iterations' number of times.
1761 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1762 u32 usec_interval, bool *success)
1767 for (i = 0; i < iterations; i++) {
1769 * Some PHYs require the PHY_STATUS register to be read
1770 * twice due to the link bit being sticky. No harm doing
1771 * it across the board.
1773 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1776 * If the first read fails, another entity may have
1777 * ownership of the resources, wait and try again to
1778 * see if they have relinquished the resources yet.
1780 udelay(usec_interval);
1781 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1784 if (phy_status & MII_SR_LINK_STATUS)
1786 if (usec_interval >= 1000)
1787 mdelay(usec_interval/1000);
1789 udelay(usec_interval);
1792 *success = (i < iterations);
1798 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1799 * @hw: pointer to the HW structure
1801 * Reads the PHY specific status register to retrieve the cable length
1802 * information. The cable length is determined by averaging the minimum and
1803 * maximum values to get the "average" cable length. The m88 PHY has four
1804 * possible cable length values, which are:
1805 * Register Value Cable Length
1809 * 3 110 - 140 meters
1812 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1814 struct e1000_phy_info *phy = &hw->phy;
1816 u16 phy_data, index;
1818 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1822 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1823 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1824 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1825 ret_val = -E1000_ERR_PHY;
1829 phy->min_cable_length = e1000_m88_cable_length_table[index];
1830 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1832 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1839 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1840 * @hw: pointer to the HW structure
1842 * The automatic gain control (agc) normalizes the amplitude of the
1843 * received signal, adjusting for the attenuation produced by the
1844 * cable. By reading the AGC registers, which represent the
1845 * combination of coarse and fine gain value, the value can be put
1846 * into a lookup table to obtain the approximate cable length
1849 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1851 struct e1000_phy_info *phy = &hw->phy;
1853 u16 phy_data, i, agc_value = 0;
1854 u16 cur_agc_index, max_agc_index = 0;
1855 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1856 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1857 IGP02E1000_PHY_AGC_A,
1858 IGP02E1000_PHY_AGC_B,
1859 IGP02E1000_PHY_AGC_C,
1860 IGP02E1000_PHY_AGC_D
1863 /* Read the AGC registers for all channels */
1864 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1865 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1870 * Getting bits 15:9, which represent the combination of
1871 * coarse and fine gain values. The result is a number
1872 * that can be put into the lookup table to obtain the
1873 * approximate cable length.
1875 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1876 IGP02E1000_AGC_LENGTH_MASK;
1878 /* Array index bound check. */
1879 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1880 (cur_agc_index == 0))
1881 return -E1000_ERR_PHY;
1883 /* Remove min & max AGC values from calculation. */
1884 if (e1000_igp_2_cable_length_table[min_agc_index] >
1885 e1000_igp_2_cable_length_table[cur_agc_index])
1886 min_agc_index = cur_agc_index;
1887 if (e1000_igp_2_cable_length_table[max_agc_index] <
1888 e1000_igp_2_cable_length_table[cur_agc_index])
1889 max_agc_index = cur_agc_index;
1891 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1894 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1895 e1000_igp_2_cable_length_table[max_agc_index]);
1896 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1898 /* Calculate cable length with the error range of +/- 10 meters. */
1899 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1900 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1901 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1903 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1909 * e1000e_get_phy_info_m88 - Retrieve PHY information
1910 * @hw: pointer to the HW structure
1912 * Valid for only copper links. Read the PHY status register (sticky read)
1913 * to verify that link is up. Read the PHY special control register to
1914 * determine the polarity and 10base-T extended distance. Read the PHY
1915 * special status register to determine MDI/MDIx and current speed. If
1916 * speed is 1000, then determine cable length, local and remote receiver.
1918 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1920 struct e1000_phy_info *phy = &hw->phy;
1925 if (phy->media_type != e1000_media_type_copper) {
1926 e_dbg("Phy info is only valid for copper media\n");
1927 return -E1000_ERR_CONFIG;
1930 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1935 e_dbg("Phy info is only valid if link is up\n");
1936 return -E1000_ERR_CONFIG;
1939 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1943 phy->polarity_correction = (phy_data &
1944 M88E1000_PSCR_POLARITY_REVERSAL);
1946 ret_val = e1000_check_polarity_m88(hw);
1950 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1954 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1956 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1957 ret_val = e1000_get_cable_length(hw);
1961 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1965 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1966 ? e1000_1000t_rx_status_ok
1967 : e1000_1000t_rx_status_not_ok;
1969 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1970 ? e1000_1000t_rx_status_ok
1971 : e1000_1000t_rx_status_not_ok;
1973 /* Set values to "undefined" */
1974 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1975 phy->local_rx = e1000_1000t_rx_status_undefined;
1976 phy->remote_rx = e1000_1000t_rx_status_undefined;
1983 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1984 * @hw: pointer to the HW structure
1986 * Read PHY status to determine if link is up. If link is up, then
1987 * set/determine 10base-T extended distance and polarity correction. Read
1988 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1989 * determine on the cable length, local and remote receiver.
1991 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1993 struct e1000_phy_info *phy = &hw->phy;
1998 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2003 e_dbg("Phy info is only valid if link is up\n");
2004 return -E1000_ERR_CONFIG;
2007 phy->polarity_correction = true;
2009 ret_val = e1000_check_polarity_igp(hw);
2013 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2017 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
2019 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2020 IGP01E1000_PSSR_SPEED_1000MBPS) {
2021 ret_val = e1000_get_cable_length(hw);
2025 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
2029 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2030 ? e1000_1000t_rx_status_ok
2031 : e1000_1000t_rx_status_not_ok;
2033 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2034 ? e1000_1000t_rx_status_ok
2035 : e1000_1000t_rx_status_not_ok;
2037 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2038 phy->local_rx = e1000_1000t_rx_status_undefined;
2039 phy->remote_rx = e1000_1000t_rx_status_undefined;
2046 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2047 * @hw: pointer to the HW structure
2049 * Populates "phy" structure with various feature states.
2051 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2053 struct e1000_phy_info *phy = &hw->phy;
2058 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2063 e_dbg("Phy info is only valid if link is up\n");
2064 ret_val = -E1000_ERR_CONFIG;
2068 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2071 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2074 if (phy->polarity_correction) {
2075 ret_val = e1000_check_polarity_ife(hw);
2079 /* Polarity is forced */
2080 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2081 ? e1000_rev_polarity_reversed
2082 : e1000_rev_polarity_normal;
2085 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2089 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
2091 /* The following parameters are undefined for 10/100 operation. */
2092 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2093 phy->local_rx = e1000_1000t_rx_status_undefined;
2094 phy->remote_rx = e1000_1000t_rx_status_undefined;
2101 * e1000e_phy_sw_reset - PHY software reset
2102 * @hw: pointer to the HW structure
2104 * Does a software reset of the PHY by reading the PHY control register and
2105 * setting/write the control register reset bit to the PHY.
2107 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2112 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
2116 phy_ctrl |= MII_CR_RESET;
2117 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
2127 * e1000e_phy_hw_reset_generic - PHY hardware reset
2128 * @hw: pointer to the HW structure
2130 * Verify the reset block is not blocking us from resetting. Acquire
2131 * semaphore (if necessary) and read/set/write the device control reset
2132 * bit in the PHY. Wait the appropriate delay time for the device to
2133 * reset and release the semaphore (if necessary).
2135 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2137 struct e1000_phy_info *phy = &hw->phy;
2141 ret_val = e1000_check_reset_block(hw);
2145 ret_val = phy->ops.acquire(hw);
2150 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2153 udelay(phy->reset_delay_us);
2160 phy->ops.release(hw);
2162 return e1000_get_phy_cfg_done(hw);
2166 * e1000e_get_cfg_done - Generic configuration done
2167 * @hw: pointer to the HW structure
2169 * Generic function to wait 10 milli-seconds for configuration to complete
2170 * and return success.
2172 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2179 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2180 * @hw: pointer to the HW structure
2182 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2184 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2186 e_dbg("Running IGP 3 PHY init script\n");
2188 /* PHY init IGP 3 */
2189 /* Enable rise/fall, 10-mode work in class-A */
2190 e1e_wphy(hw, 0x2F5B, 0x9018);
2191 /* Remove all caps from Replica path filter */
2192 e1e_wphy(hw, 0x2F52, 0x0000);
2193 /* Bias trimming for ADC, AFE and Driver (Default) */
2194 e1e_wphy(hw, 0x2FB1, 0x8B24);
2195 /* Increase Hybrid poly bias */
2196 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2197 /* Add 4% to Tx amplitude in Gig mode */
2198 e1e_wphy(hw, 0x2010, 0x10B0);
2199 /* Disable trimming (TTT) */
2200 e1e_wphy(hw, 0x2011, 0x0000);
2201 /* Poly DC correction to 94.6% + 2% for all channels */
2202 e1e_wphy(hw, 0x20DD, 0x249A);
2203 /* ABS DC correction to 95.9% */
2204 e1e_wphy(hw, 0x20DE, 0x00D3);
2205 /* BG temp curve trim */
2206 e1e_wphy(hw, 0x28B4, 0x04CE);
2207 /* Increasing ADC OPAMP stage 1 currents to max */
2208 e1e_wphy(hw, 0x2F70, 0x29E4);
2209 /* Force 1000 ( required for enabling PHY regs configuration) */
2210 e1e_wphy(hw, 0x0000, 0x0140);
2211 /* Set upd_freq to 6 */
2212 e1e_wphy(hw, 0x1F30, 0x1606);
2214 e1e_wphy(hw, 0x1F31, 0xB814);
2215 /* Disable adaptive fixed FFE (Default) */
2216 e1e_wphy(hw, 0x1F35, 0x002A);
2217 /* Enable FFE hysteresis */
2218 e1e_wphy(hw, 0x1F3E, 0x0067);
2219 /* Fixed FFE for short cable lengths */
2220 e1e_wphy(hw, 0x1F54, 0x0065);
2221 /* Fixed FFE for medium cable lengths */
2222 e1e_wphy(hw, 0x1F55, 0x002A);
2223 /* Fixed FFE for long cable lengths */
2224 e1e_wphy(hw, 0x1F56, 0x002A);
2225 /* Enable Adaptive Clip Threshold */
2226 e1e_wphy(hw, 0x1F72, 0x3FB0);
2227 /* AHT reset limit to 1 */
2228 e1e_wphy(hw, 0x1F76, 0xC0FF);
2229 /* Set AHT master delay to 127 msec */
2230 e1e_wphy(hw, 0x1F77, 0x1DEC);
2231 /* Set scan bits for AHT */
2232 e1e_wphy(hw, 0x1F78, 0xF9EF);
2233 /* Set AHT Preset bits */
2234 e1e_wphy(hw, 0x1F79, 0x0210);
2235 /* Change integ_factor of channel A to 3 */
2236 e1e_wphy(hw, 0x1895, 0x0003);
2237 /* Change prop_factor of channels BCD to 8 */
2238 e1e_wphy(hw, 0x1796, 0x0008);
2239 /* Change cg_icount + enable integbp for channels BCD */
2240 e1e_wphy(hw, 0x1798, 0xD008);
2242 * Change cg_icount + enable integbp + change prop_factor_master
2243 * to 8 for channel A
2245 e1e_wphy(hw, 0x1898, 0xD918);
2246 /* Disable AHT in Slave mode on channel A */
2247 e1e_wphy(hw, 0x187A, 0x0800);
2249 * Enable LPLU and disable AN to 1000 in non-D0a states,
2252 e1e_wphy(hw, 0x0019, 0x008D);
2253 /* Enable restart AN on an1000_dis change */
2254 e1e_wphy(hw, 0x001B, 0x2080);
2255 /* Enable wh_fifo read clock in 10/100 modes */
2256 e1e_wphy(hw, 0x0014, 0x0045);
2257 /* Restart AN, Speed selection is 1000 */
2258 e1e_wphy(hw, 0x0000, 0x1340);
2263 /* Internal function pointers */
2266 * e1000_get_phy_cfg_done - Generic PHY configuration done
2267 * @hw: pointer to the HW structure
2269 * Return success if silicon family did not implement a family specific
2270 * get_cfg_done function.
2272 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
2274 if (hw->phy.ops.get_cfg_done)
2275 return hw->phy.ops.get_cfg_done(hw);
2281 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
2282 * @hw: pointer to the HW structure
2284 * When the silicon family has not implemented a forced speed/duplex
2285 * function for the PHY, simply return 0.
2287 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2289 if (hw->phy.ops.force_speed_duplex)
2290 return hw->phy.ops.force_speed_duplex(hw);
2296 * e1000e_get_phy_type_from_id - Get PHY type from id
2297 * @phy_id: phy_id read from the phy
2299 * Returns the phy type from the id.
2301 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2303 enum e1000_phy_type phy_type = e1000_phy_unknown;
2306 case M88E1000_I_PHY_ID:
2307 case M88E1000_E_PHY_ID:
2308 case M88E1111_I_PHY_ID:
2309 case M88E1011_I_PHY_ID:
2310 phy_type = e1000_phy_m88;
2312 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2313 phy_type = e1000_phy_igp_2;
2315 case GG82563_E_PHY_ID:
2316 phy_type = e1000_phy_gg82563;
2318 case IGP03E1000_E_PHY_ID:
2319 phy_type = e1000_phy_igp_3;
2322 case IFE_PLUS_E_PHY_ID:
2323 case IFE_C_E_PHY_ID:
2324 phy_type = e1000_phy_ife;
2326 case BME1000_E_PHY_ID:
2327 case BME1000_E_PHY_ID_R2:
2328 phy_type = e1000_phy_bm;
2330 case I82578_E_PHY_ID:
2331 phy_type = e1000_phy_82578;
2333 case I82577_E_PHY_ID:
2334 phy_type = e1000_phy_82577;
2336 case I82579_E_PHY_ID:
2337 phy_type = e1000_phy_82579;
2340 phy_type = e1000_phy_unknown;
2347 * e1000e_determine_phy_address - Determines PHY address.
2348 * @hw: pointer to the HW structure
2350 * This uses a trial and error method to loop through possible PHY
2351 * addresses. It tests each by reading the PHY ID registers and
2352 * checking for a match.
2354 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2356 s32 ret_val = -E1000_ERR_PHY_TYPE;
2359 enum e1000_phy_type phy_type = e1000_phy_unknown;
2361 hw->phy.id = phy_type;
2363 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2364 hw->phy.addr = phy_addr;
2368 e1000e_get_phy_id(hw);
2369 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2372 * If phy_type is valid, break - we found our
2375 if (phy_type != e1000_phy_unknown) {
2389 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2390 * @page: page to access
2392 * Returns the phy address for the page requested.
2394 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2398 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2405 * e1000e_write_phy_reg_bm - Write BM PHY register
2406 * @hw: pointer to the HW structure
2407 * @offset: register offset to write to
2408 * @data: data to write at register offset
2410 * Acquires semaphore, if necessary, then writes the data to PHY register
2411 * at the offset. Release any acquired semaphores before exiting.
2413 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2416 u32 page_select = 0;
2417 u32 page = offset >> IGP_PAGE_SHIFT;
2420 ret_val = hw->phy.ops.acquire(hw);
2424 /* Page 800 works differently than the rest so it has its own func */
2425 if (page == BM_WUC_PAGE) {
2426 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2431 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2433 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2435 * Page select is register 31 for phy address 1 and 22 for
2436 * phy address 2 and 3. Page select is shifted only for
2439 if (hw->phy.addr == 1) {
2440 page_shift = IGP_PAGE_SHIFT;
2441 page_select = IGP01E1000_PHY_PAGE_SELECT;
2444 page_select = BM_PHY_PAGE_SELECT;
2447 /* Page is shifted left, PHY expects (page x 32) */
2448 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2449 (page << page_shift));
2454 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2458 hw->phy.ops.release(hw);
2463 * e1000e_read_phy_reg_bm - Read BM PHY register
2464 * @hw: pointer to the HW structure
2465 * @offset: register offset to be read
2466 * @data: pointer to the read data
2468 * Acquires semaphore, if necessary, then reads the PHY register at offset
2469 * and storing the retrieved information in data. Release any acquired
2470 * semaphores before exiting.
2472 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2475 u32 page_select = 0;
2476 u32 page = offset >> IGP_PAGE_SHIFT;
2479 ret_val = hw->phy.ops.acquire(hw);
2483 /* Page 800 works differently than the rest so it has its own func */
2484 if (page == BM_WUC_PAGE) {
2485 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2490 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2492 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2494 * Page select is register 31 for phy address 1 and 22 for
2495 * phy address 2 and 3. Page select is shifted only for
2498 if (hw->phy.addr == 1) {
2499 page_shift = IGP_PAGE_SHIFT;
2500 page_select = IGP01E1000_PHY_PAGE_SELECT;
2503 page_select = BM_PHY_PAGE_SELECT;
2506 /* Page is shifted left, PHY expects (page x 32) */
2507 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2508 (page << page_shift));
2513 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2516 hw->phy.ops.release(hw);
2521 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2522 * @hw: pointer to the HW structure
2523 * @offset: register offset to be read
2524 * @data: pointer to the read data
2526 * Acquires semaphore, if necessary, then reads the PHY register at offset
2527 * and storing the retrieved information in data. Release any acquired
2528 * semaphores before exiting.
2530 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2533 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2535 ret_val = hw->phy.ops.acquire(hw);
2539 /* Page 800 works differently than the rest so it has its own func */
2540 if (page == BM_WUC_PAGE) {
2541 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2548 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2550 /* Page is shifted left, PHY expects (page x 32) */
2551 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2558 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2561 hw->phy.ops.release(hw);
2566 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2567 * @hw: pointer to the HW structure
2568 * @offset: register offset to write to
2569 * @data: data to write at register offset
2571 * Acquires semaphore, if necessary, then writes the data to PHY register
2572 * at the offset. Release any acquired semaphores before exiting.
2574 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2577 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2579 ret_val = hw->phy.ops.acquire(hw);
2583 /* Page 800 works differently than the rest so it has its own func */
2584 if (page == BM_WUC_PAGE) {
2585 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2592 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2593 /* Page is shifted left, PHY expects (page x 32) */
2594 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2601 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2605 hw->phy.ops.release(hw);
2610 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
2611 * @hw: pointer to the HW structure
2612 * @offset: register offset to be read or written
2613 * @data: pointer to the data to read or write
2614 * @read: determines if operation is read or write
2616 * Acquires semaphore, if necessary, then reads the PHY register at offset
2617 * and storing the retrieved information in data. Release any acquired
2618 * semaphores before exiting. Note that procedure to read the wakeup
2619 * registers are different. It works as such:
2620 * 1) Set page 769, register 17, bit 2 = 1
2621 * 2) Set page to 800 for host (801 if we were manageability)
2622 * 3) Write the address using the address opcode (0x11)
2623 * 4) Read or write the data using the data opcode (0x12)
2624 * 5) Restore 769_17.2 to its original value
2626 * Assumes semaphore already acquired.
2628 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2629 u16 *data, bool read)
2632 u16 reg = BM_PHY_REG_NUM(offset);
2635 /* Gig must be disabled for MDIO accesses to page 800 */
2636 if ((hw->mac.type == e1000_pchlan) &&
2637 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2638 e_dbg("Attempting to access page 800 while gig enabled.\n");
2640 /* All operations in this function are phy address 1 */
2644 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2645 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2647 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
2649 e_dbg("Could not read PHY page 769\n");
2653 /* First clear bit 4 to avoid a power state change */
2654 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
2655 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2657 e_dbg("Could not clear PHY page 769 bit 4\n");
2661 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2662 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
2663 phy_reg | BM_WUC_ENABLE_BIT);
2665 e_dbg("Could not write PHY page 769 bit 2\n");
2669 /* Select page 800 */
2670 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2671 (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2673 /* Write the page 800 offset value using opcode 0x11 */
2674 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2676 e_dbg("Could not write address opcode to page 800\n");
2681 /* Read the page 800 value using opcode 0x12 */
2682 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2685 /* Write the page 800 value using opcode 0x12 */
2686 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2691 e_dbg("Could not access data value from page 800\n");
2696 * Restore 769_17.2 to its original value
2699 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2700 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2702 /* Clear 769_17.2 */
2703 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2705 e_dbg("Could not clear PHY page 769 bit 2\n");
2714 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2715 * @hw: pointer to the HW structure
2717 * In the case of a PHY power down to save power, or to turn off link during a
2718 * driver unload, or wake on lan is not enabled, restore the link to previous
2721 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2725 /* The PHY will retain its settings across a power down/up cycle */
2726 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2727 mii_reg &= ~MII_CR_POWER_DOWN;
2728 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2732 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2733 * @hw: pointer to the HW structure
2735 * In the case of a PHY power down to save power, or to turn off link during a
2736 * driver unload, or wake on lan is not enabled, restore the link to previous
2739 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2743 /* The PHY will retain its settings across a power down/up cycle */
2744 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2745 mii_reg |= MII_CR_POWER_DOWN;
2746 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2751 * e1000e_commit_phy - Soft PHY reset
2752 * @hw: pointer to the HW structure
2754 * Performs a soft PHY reset on those that apply. This is a function pointer
2755 * entry point called by drivers.
2757 s32 e1000e_commit_phy(struct e1000_hw *hw)
2759 if (hw->phy.ops.commit)
2760 return hw->phy.ops.commit(hw);
2766 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2767 * @hw: pointer to the HW structure
2768 * @active: boolean used to enable/disable lplu
2770 * Success returns 0, Failure returns 1
2772 * The low power link up (lplu) state is set to the power management level D0
2773 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2774 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2775 * is used during Dx states where the power conservation is most important.
2776 * During driver activity, SmartSpeed should be enabled so performance is
2777 * maintained. This is a function pointer entry point called by drivers.
2779 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2781 if (hw->phy.ops.set_d0_lplu_state)
2782 return hw->phy.ops.set_d0_lplu_state(hw, active);
2788 * __e1000_read_phy_reg_hv - Read HV PHY register
2789 * @hw: pointer to the HW structure
2790 * @offset: register offset to be read
2791 * @data: pointer to the read data
2792 * @locked: semaphore has already been acquired or not
2794 * Acquires semaphore, if necessary, then reads the PHY register at offset
2795 * and stores the retrieved information in data. Release any acquired
2796 * semaphore before exiting.
2798 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2802 u16 page = BM_PHY_REG_PAGE(offset);
2803 u16 reg = BM_PHY_REG_NUM(offset);
2806 ret_val = hw->phy.ops.acquire(hw);
2811 /* Page 800 works differently than the rest so it has its own func */
2812 if (page == BM_WUC_PAGE) {
2813 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
2818 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2819 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2824 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2826 if (page == HV_INTC_FC_PAGE_START)
2829 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2830 u32 phy_addr = hw->phy.addr;
2834 /* Page is shifted left, PHY expects (page x 32) */
2835 ret_val = e1000e_write_phy_reg_mdic(hw,
2836 IGP01E1000_PHY_PAGE_SELECT,
2837 (page << IGP_PAGE_SHIFT));
2838 hw->phy.addr = phy_addr;
2844 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2848 hw->phy.ops.release(hw);
2854 * e1000_read_phy_reg_hv - Read HV PHY register
2855 * @hw: pointer to the HW structure
2856 * @offset: register offset to be read
2857 * @data: pointer to the read data
2859 * Acquires semaphore then reads the PHY register at offset and stores
2860 * the retrieved information in data. Release the acquired semaphore
2863 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2865 return __e1000_read_phy_reg_hv(hw, offset, data, false);
2869 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2870 * @hw: pointer to the HW structure
2871 * @offset: register offset to be read
2872 * @data: pointer to the read data
2874 * Reads the PHY register at offset and stores the retrieved information
2875 * in data. Assumes semaphore already acquired.
2877 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2879 return __e1000_read_phy_reg_hv(hw, offset, data, true);
2883 * __e1000_write_phy_reg_hv - Write HV PHY register
2884 * @hw: pointer to the HW structure
2885 * @offset: register offset to write to
2886 * @data: data to write at register offset
2887 * @locked: semaphore has already been acquired or not
2889 * Acquires semaphore, if necessary, then writes the data to PHY register
2890 * at the offset. Release any acquired semaphores before exiting.
2892 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2896 u16 page = BM_PHY_REG_PAGE(offset);
2897 u16 reg = BM_PHY_REG_NUM(offset);
2900 ret_val = hw->phy.ops.acquire(hw);
2905 /* Page 800 works differently than the rest so it has its own func */
2906 if (page == BM_WUC_PAGE) {
2907 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
2912 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2913 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2918 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2920 if (page == HV_INTC_FC_PAGE_START)
2924 * Workaround MDIO accesses being disabled after entering IEEE Power
2925 * Down (whenever bit 11 of the PHY Control register is set)
2927 if ((hw->phy.type == e1000_phy_82578) &&
2928 (hw->phy.revision >= 1) &&
2929 (hw->phy.addr == 2) &&
2930 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
2931 (data & (1 << 11))) {
2933 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
2939 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2940 u32 phy_addr = hw->phy.addr;
2944 /* Page is shifted left, PHY expects (page x 32) */
2945 ret_val = e1000e_write_phy_reg_mdic(hw,
2946 IGP01E1000_PHY_PAGE_SELECT,
2947 (page << IGP_PAGE_SHIFT));
2948 hw->phy.addr = phy_addr;
2954 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2959 hw->phy.ops.release(hw);
2965 * e1000_write_phy_reg_hv - Write HV PHY register
2966 * @hw: pointer to the HW structure
2967 * @offset: register offset to write to
2968 * @data: data to write at register offset
2970 * Acquires semaphore then writes the data to PHY register at the offset.
2971 * Release the acquired semaphores before exiting.
2973 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2975 return __e1000_write_phy_reg_hv(hw, offset, data, false);
2979 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2980 * @hw: pointer to the HW structure
2981 * @offset: register offset to write to
2982 * @data: data to write at register offset
2984 * Writes the data to PHY register at the offset. Assumes semaphore
2987 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2989 return __e1000_write_phy_reg_hv(hw, offset, data, true);
2993 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
2994 * @page: page to be accessed
2996 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3000 if (page >= HV_INTC_FC_PAGE_START)
3007 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3008 * @hw: pointer to the HW structure
3009 * @offset: register offset to be read or written
3010 * @data: pointer to the data to be read or written
3011 * @read: determines if operation is read or written
3013 * Reads the PHY register at offset and stores the retreived information
3014 * in data. Assumes semaphore already acquired. Note that the procedure
3015 * to read these regs uses the address port and data port to read/write.
3017 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3018 u16 *data, bool read)
3024 /* This takes care of the difference with desktop vs mobile phy */
3025 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3026 I82578_ADDR_REG : I82577_ADDR_REG;
3027 data_reg = addr_reg + 1;
3029 /* All operations in this function are phy address 2 */
3032 /* masking with 0x3F to remove the page from offset */
3033 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3035 e_dbg("Could not write PHY the HV address register\n");
3039 /* Read or write the data value next */
3041 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3043 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3046 e_dbg("Could not read data value from HV data register\n");
3055 * e1000_link_stall_workaround_hv - Si workaround
3056 * @hw: pointer to the HW structure
3058 * This function works around a Si bug where the link partner can get
3059 * a link up indication before the PHY does. If small packets are sent
3060 * by the link partner they can be placed in the packet buffer without
3061 * being properly accounted for by the PHY and will stall preventing
3062 * further packets from being received. The workaround is to clear the
3063 * packet buffer after the PHY detects link up.
3065 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3070 if (hw->phy.type != e1000_phy_82578)
3073 /* Do not apply workaround if in PHY loopback bit 14 set */
3074 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3075 if (data & PHY_CONTROL_LB)
3078 /* check if link is up and at 1Gbps */
3079 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3083 data &= BM_CS_STATUS_LINK_UP |
3084 BM_CS_STATUS_RESOLVED |
3085 BM_CS_STATUS_SPEED_MASK;
3087 if (data != (BM_CS_STATUS_LINK_UP |
3088 BM_CS_STATUS_RESOLVED |
3089 BM_CS_STATUS_SPEED_1000))
3094 /* flush the packets in the fifo buffer */
3095 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3096 HV_MUX_DATA_CTRL_GEN_TO_MAC |
3097 HV_MUX_DATA_CTRL_FORCE_SPEED);
3101 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3102 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3109 * e1000_check_polarity_82577 - Checks the polarity.
3110 * @hw: pointer to the HW structure
3112 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3114 * Polarity is determined based on the PHY specific status register.
3116 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3118 struct e1000_phy_info *phy = &hw->phy;
3122 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3125 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3126 ? e1000_rev_polarity_reversed
3127 : e1000_rev_polarity_normal;
3133 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3134 * @hw: pointer to the HW structure
3136 * Calls the PHY setup function to force speed and duplex.
3138 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3140 struct e1000_phy_info *phy = &hw->phy;
3145 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3149 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3151 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3157 if (phy->autoneg_wait_to_complete) {
3158 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3160 ret_val = e1000e_phy_has_link_generic(hw,
3168 e_dbg("Link taking longer than expected.\n");
3171 ret_val = e1000e_phy_has_link_generic(hw,
3184 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3185 * @hw: pointer to the HW structure
3187 * Read PHY status to determine if link is up. If link is up, then
3188 * set/determine 10base-T extended distance and polarity correction. Read
3189 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3190 * determine on the cable length, local and remote receiver.
3192 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3194 struct e1000_phy_info *phy = &hw->phy;
3199 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3204 e_dbg("Phy info is only valid if link is up\n");
3205 ret_val = -E1000_ERR_CONFIG;
3209 phy->polarity_correction = true;
3211 ret_val = e1000_check_polarity_82577(hw);
3215 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3219 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
3221 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3222 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3223 ret_val = hw->phy.ops.get_cable_length(hw);
3227 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3231 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3232 ? e1000_1000t_rx_status_ok
3233 : e1000_1000t_rx_status_not_ok;
3235 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3236 ? e1000_1000t_rx_status_ok
3237 : e1000_1000t_rx_status_not_ok;
3239 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3240 phy->local_rx = e1000_1000t_rx_status_undefined;
3241 phy->remote_rx = e1000_1000t_rx_status_undefined;
3249 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3250 * @hw: pointer to the HW structure
3252 * Reads the diagnostic status register and verifies result is valid before
3253 * placing it in the phy_cable_length field.
3255 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3257 struct e1000_phy_info *phy = &hw->phy;
3259 u16 phy_data, length;
3261 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3265 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3266 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3268 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3269 ret_val = -E1000_ERR_PHY;
3271 phy->cable_length = length;