2 * Microchip ENC28J60 ethernet driver (MAC + PHY)
4 * Copyright (C) 2007 Eurek srl
5 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
6 * based on enc28j60.c written by David Anders for 2.4 kernel version
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/fcntl.h>
20 #include <linux/interrupt.h>
21 #include <linux/string.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/tcp.h>
28 #include <linux/skbuff.h>
29 #include <linux/delay.h>
30 #include <linux/spi/spi.h>
31 #include <mach/gpio.h>
33 #include "enc28j60_hw.h"
35 #define MAC_INT_PORT RK2818_PIN_PE2
36 #define DRV_NAME "enc28j60"
37 #define DRV_VERSION "1.01"
41 #define ENC28J60_MSG_DEFAULT \
42 (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
44 /* Buffer size required for the largest SPI transfer (i.e., reading a
46 #define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN)
48 #define TX_TIMEOUT (4 * HZ)
50 /* Max TX retries in case of collision as suggested by errata datasheet */
51 #define MAX_TX_RETRYCOUNT 16
59 /* Driver local data */
61 struct net_device *netdev;
62 struct spi_device *spi;
64 struct sk_buff *tx_skb;
65 struct work_struct tx_work;
66 struct work_struct irq_work;
67 struct work_struct setrx_work;
68 struct work_struct restart_work;
69 u8 bank; /* current register bank selected */
70 u16 next_pk_ptr; /* next packet pointer within FIFO */
71 u16 max_pk_counter; /* statistics: max packet counter */
77 u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
80 /* use ethtool to change the level for any given device */
87 * wait for the SPI transfer and copy received data to destination
90 spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
92 u8 *rx_buf = priv->spi_transfer_buf + 4;
93 u8 *tx_buf = priv->spi_transfer_buf;
94 struct spi_transfer t = {
97 .len = SPI_OPLEN + len,
99 struct spi_message msg;
102 tx_buf[0] = ENC28J60_READ_BUF_MEM;
103 tx_buf[1] = tx_buf[2] = tx_buf[3] = 0; /* don't care */
105 spi_message_init(&msg);
106 spi_message_add_tail(&t, &msg);
107 ret = spi_sync(priv->spi, &msg);
109 memcpy(data, &rx_buf[SPI_OPLEN], len);
112 if (ret && netif_msg_drv(priv))
113 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
122 static int spi_write_buf(struct enc28j60_net *priv, int len,
127 if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
130 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
131 memcpy(&priv->spi_transfer_buf[1], data, len);
132 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
133 if (ret && netif_msg_drv(priv))
134 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
141 * basic SPI read operation
143 static u8 spi_read_op(struct enc28j60_net *priv, u8 op,
150 int slen = SPI_OPLEN;
152 /* do dummy read if needed */
153 if (addr & SPRD_MASK)
156 tx_buf[0] = op | (addr & ADDR_MASK);
157 ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
159 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
162 val = rx_buf[slen - 1];
168 * basic SPI write operation
170 static int spi_write_op(struct enc28j60_net *priv, u8 op,
175 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
176 priv->spi_transfer_buf[1] = val;
177 ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
178 if (ret && netif_msg_drv(priv))
179 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
184 static void enc28j60_soft_reset(struct enc28j60_net *priv)
186 if (netif_msg_hw(priv))
187 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
189 spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
190 /* Errata workaround #1, CLKRDY check is unreliable,
191 * delay at least 1 mS instead */
196 * select the current register bank if necessary
198 static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
200 u8 b = (addr & BANK_MASK) >> 5;
202 /* These registers (EIE, EIR, ESTAT, ECON2, ECON1)
203 * are present in all banks, no need to switch bank
205 if (addr >= EIE && addr <= ECON1)
208 /* Clear or set each bank selection bit as needed */
209 if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) {
211 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
214 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
217 if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) {
219 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
222 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
229 * Register access routines through the SPI bus.
230 * Every register access comes in two flavours:
231 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
232 * atomically more than one register
233 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
235 * Some registers can be accessed through the bit field clear and
236 * bit field set to avoid a read modify write cycle.
240 * Register bit field Set
242 static void nolock_reg_bfset(struct enc28j60_net *priv,
245 enc28j60_set_bank(priv, addr);
246 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
249 static void locked_reg_bfset(struct enc28j60_net *priv,
252 mutex_lock(&priv->lock);
253 nolock_reg_bfset(priv, addr, mask);
254 mutex_unlock(&priv->lock);
258 * Register bit field Clear
260 static void nolock_reg_bfclr(struct enc28j60_net *priv,
263 enc28j60_set_bank(priv, addr);
264 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
267 static void locked_reg_bfclr(struct enc28j60_net *priv,
270 mutex_lock(&priv->lock);
271 nolock_reg_bfclr(priv, addr, mask);
272 mutex_unlock(&priv->lock);
278 static int nolock_regb_read(struct enc28j60_net *priv,
281 enc28j60_set_bank(priv, address);
282 return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
285 static int locked_regb_read(struct enc28j60_net *priv,
290 mutex_lock(&priv->lock);
291 ret = nolock_regb_read(priv, address);
292 mutex_unlock(&priv->lock);
300 static int nolock_regw_read(struct enc28j60_net *priv,
305 enc28j60_set_bank(priv, address);
306 rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
307 rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
309 return (rh << 8) | rl;
312 static int locked_regw_read(struct enc28j60_net *priv,
317 mutex_lock(&priv->lock);
318 ret = nolock_regw_read(priv, address);
319 mutex_unlock(&priv->lock);
325 * Register byte write
327 static void nolock_regb_write(struct enc28j60_net *priv,
330 enc28j60_set_bank(priv, address);
331 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
334 static void locked_regb_write(struct enc28j60_net *priv,
337 mutex_lock(&priv->lock);
338 nolock_regb_write(priv, address, data);
339 mutex_unlock(&priv->lock);
343 * Register word write
345 static void nolock_regw_write(struct enc28j60_net *priv,
346 u8 address, u16 data)
348 enc28j60_set_bank(priv, address);
349 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
350 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
354 static void locked_regw_write(struct enc28j60_net *priv,
355 u8 address, u16 data)
357 mutex_lock(&priv->lock);
358 nolock_regw_write(priv, address, data);
359 mutex_unlock(&priv->lock);
364 * Select the starting address and execute a SPI buffer read
366 static void enc28j60_mem_read(struct enc28j60_net *priv,
367 u16 addr, int len, u8 *data)
369 mutex_lock(&priv->lock);
370 nolock_regw_write(priv, ERDPTL, addr);
371 #ifdef CONFIG_ENC28J60_WRITEVERIFY
372 if (netif_msg_drv(priv)) {
374 reg = nolock_regw_read(priv, ERDPTL);
376 printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT "
377 "(0x%04x - 0x%04x)\n", __func__, reg, addr);
380 spi_read_buf(priv, len, data);
381 mutex_unlock(&priv->lock);
385 * Write packet to enc28j60 TX buffer memory
388 enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
390 mutex_lock(&priv->lock);
391 /* Set the write pointer to start of transmit buffer area */
392 nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
393 #ifdef CONFIG_ENC28J60_WRITEVERIFY
394 if (netif_msg_drv(priv)) {
396 reg = nolock_regw_read(priv, EWRPTL);
397 if (reg != TXSTART_INIT)
398 printk(KERN_DEBUG DRV_NAME
399 ": %s() ERWPT:0x%04x != 0x%04x\n",
400 __func__, reg, TXSTART_INIT);
403 /* Set the TXND pointer to correspond to the packet size given */
404 nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
405 /* write per-packet control byte */
406 spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
407 if (netif_msg_hw(priv))
408 printk(KERN_DEBUG DRV_NAME
409 ": %s() after control byte ERWPT:0x%04x\n",
410 __func__, nolock_regw_read(priv, EWRPTL));
411 /* copy the packet into the transmit buffer */
412 spi_write_buf(priv, len, data);
413 if (netif_msg_hw(priv))
414 printk(KERN_DEBUG DRV_NAME
415 ": %s() after write packet ERWPT:0x%04x, len=%d\n",
416 __func__, nolock_regw_read(priv, EWRPTL), len);
417 mutex_unlock(&priv->lock);
420 static unsigned long msec20_to_jiffies;
422 static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
424 unsigned long timeout = jiffies + msec20_to_jiffies;
426 /* 20 msec timeout read */
427 while ((nolock_regb_read(priv, reg) & mask) != val) {
428 if (time_after(jiffies, timeout)) {
429 if (netif_msg_drv(priv))
430 dev_dbg(&priv->spi->dev,
431 "reg %02x ready timeout!\n", reg);
440 * Wait until the PHY operation is complete.
442 static int wait_phy_ready(struct enc28j60_net *priv)
444 return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
449 * PHY registers are not accessed directly, but through the MII
451 static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
455 mutex_lock(&priv->lock);
456 /* set the PHY register address */
457 nolock_regb_write(priv, MIREGADR, address);
458 /* start the register read operation */
459 nolock_regb_write(priv, MICMD, MICMD_MIIRD);
460 /* wait until the PHY read completes */
461 wait_phy_ready(priv);
463 nolock_regb_write(priv, MICMD, 0x00);
464 /* return the data */
465 ret = nolock_regw_read(priv, MIRDL);
466 mutex_unlock(&priv->lock);
471 static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
475 mutex_lock(&priv->lock);
476 /* set the PHY register address */
477 nolock_regb_write(priv, MIREGADR, address);
478 /* write the PHY data */
479 nolock_regw_write(priv, MIWRL, data);
480 /* wait until the PHY write completes and return */
481 ret = wait_phy_ready(priv);
482 mutex_unlock(&priv->lock);
488 * Program the hardware MAC address from dev->dev_addr.
490 static int enc28j60_set_hw_macaddr(struct net_device *ndev)
493 struct enc28j60_net *priv = netdev_priv(ndev);
495 mutex_lock(&priv->lock);
496 if (!priv->hw_enable) {
497 if (netif_msg_drv(priv))
498 printk(KERN_INFO DRV_NAME
499 ": %s: Setting MAC address to %pM\n",
500 ndev->name, ndev->dev_addr);
501 /* NOTE: MAC address in ENC28J60 is byte-backward */
502 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
503 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
504 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
505 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
506 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
507 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
510 if (netif_msg_drv(priv))
511 printk(KERN_DEBUG DRV_NAME
512 ": %s() Hardware must be disabled to set "
513 "Mac address\n", __func__);
516 mutex_unlock(&priv->lock);
521 * Store the new hardware address in dev->dev_addr, and update the MAC.
523 static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
525 struct sockaddr *address = addr;
527 if (netif_running(dev))
529 if (!is_valid_ether_addr(address->sa_data))
530 return -EADDRNOTAVAIL;
532 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
533 return enc28j60_set_hw_macaddr(dev);
537 * Debug routine to dump useful register contents
539 static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
541 mutex_lock(&priv->lock);
542 printk(KERN_DEBUG DRV_NAME " %s\n"
544 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
545 " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n"
546 "MAC : MACON1 MACON3 MACON4\n"
547 " 0x%02x 0x%02x 0x%02x\n"
548 "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
549 " 0x%04x 0x%04x 0x%04x 0x%04x "
550 "0x%02x 0x%02x 0x%04x\n"
551 "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"
552 " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
553 msg, nolock_regb_read(priv, EREVID),
554 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
555 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
556 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
557 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
558 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
559 nolock_regw_read(priv, ERXWRPTL),
560 nolock_regw_read(priv, ERXRDPTL),
561 nolock_regb_read(priv, ERXFCON),
562 nolock_regb_read(priv, EPKTCNT),
563 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
564 nolock_regw_read(priv, ETXNDL),
565 nolock_regb_read(priv, MACLCON1),
566 nolock_regb_read(priv, MACLCON2),
567 nolock_regb_read(priv, MAPHSUP));
568 mutex_unlock(&priv->lock);
572 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
574 static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
578 if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
581 erxrdpt = next_packet_ptr - 1;
587 * Calculate wrap around when reading beyond the end of the RX buffer
589 static u16 rx_packet_start(u16 ptr)
591 if (ptr + RSV_SIZE > RXEND_INIT)
592 return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1);
594 return ptr + RSV_SIZE;
597 static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
601 if (start > 0x1FFF || end > 0x1FFF || start > end) {
602 if (netif_msg_drv(priv))
603 printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO "
604 "bad parameters!\n", __func__, start, end);
607 /* set receive buffer start + end */
608 priv->next_pk_ptr = start;
609 nolock_regw_write(priv, ERXSTL, start);
610 erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
611 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
612 nolock_regw_write(priv, ERXNDL, end);
615 static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
617 if (start > 0x1FFF || end > 0x1FFF || start > end) {
618 if (netif_msg_drv(priv))
619 printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO "
620 "bad parameters!\n", __func__, start, end);
623 /* set transmit buffer start + end */
624 nolock_regw_write(priv, ETXSTL, start);
625 nolock_regw_write(priv, ETXNDL, end);
629 * Low power mode shrinks power consumption about 100x, so we'd like
630 * the chip to be in that mode whenever it's inactive. (However, we
631 * can't stay in lowpower mode during suspend with WOL active.)
633 static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
635 if (netif_msg_drv(priv))
636 dev_dbg(&priv->spi->dev, "%s power...\n",
637 is_low ? "low" : "high");
639 mutex_lock(&priv->lock);
641 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
642 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
643 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
644 /* ECON2_VRPS was set during initialization */
645 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
647 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
648 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
649 /* caller sets ECON1_RXEN */
651 mutex_unlock(&priv->lock);
654 static int enc28j60_hw_init(struct enc28j60_net *priv)
658 if (netif_msg_drv(priv))
659 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __func__,
660 priv->full_duplex ? "FullDuplex" : "HalfDuplex");
662 mutex_lock(&priv->lock);
663 /* first reset the chip */
664 enc28j60_soft_reset(priv);
666 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
668 priv->hw_enable = false;
669 priv->tx_retry_count = 0;
670 priv->max_pk_counter = 0;
671 priv->rxfilter = RXFILTER_NORMAL;
672 /* enable address auto increment and voltage regulator powersave */
673 nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
675 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
676 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
677 mutex_unlock(&priv->lock);
681 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
684 reg = locked_regb_read(priv, EREVID);
685 if (netif_msg_drv(priv))
686 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg);
687 if (reg == 0x00 || reg == 0xff) {
688 if (netif_msg_drv(priv))
689 printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n",
694 /* default filter mode: (unicast OR broadcast) AND crc valid */
695 locked_regb_write(priv, ERXFCON,
696 ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
698 /* enable MAC receive */
699 locked_regb_write(priv, MACON1,
700 MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
701 /* enable automatic padding and CRC operations */
702 if (priv->full_duplex) {
703 locked_regb_write(priv, MACON3,
704 MACON3_PADCFG0 | MACON3_TXCRCEN |
705 MACON3_FRMLNEN | MACON3_FULDPX);
706 /* set inter-frame gap (non-back-to-back) */
707 locked_regb_write(priv, MAIPGL, 0x12);
708 /* set inter-frame gap (back-to-back) */
709 locked_regb_write(priv, MABBIPG, 0x15);
711 locked_regb_write(priv, MACON3,
712 MACON3_PADCFG0 | MACON3_TXCRCEN |
714 locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */
715 /* set inter-frame gap (non-back-to-back) */
716 locked_regw_write(priv, MAIPGL, 0x0C12);
717 /* set inter-frame gap (back-to-back) */
718 locked_regb_write(priv, MABBIPG, 0x12);
723 * Set the maximum packet size which the controller will accept
725 locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
728 if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
731 if (priv->full_duplex) {
732 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
734 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
737 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
739 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
742 if (netif_msg_hw(priv))
743 enc28j60_dump_regs(priv, "Hw initialized.");
748 static void enc28j60_hw_enable(struct enc28j60_net *priv)
750 /* enable interrupts */
751 if (netif_msg_hw(priv))
752 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
755 enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
757 mutex_lock(&priv->lock);
758 nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
759 EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
760 nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
761 EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
763 /* enable receive logic */
764 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
765 priv->hw_enable = true;
766 mutex_unlock(&priv->lock);
769 static void enc28j60_hw_disable(struct enc28j60_net *priv)
771 mutex_lock(&priv->lock);
772 /* disable interrutps and packet reception */
773 nolock_regb_write(priv, EIE, 0x00);
774 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
775 priv->hw_enable = false;
776 mutex_unlock(&priv->lock);
780 enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
782 struct enc28j60_net *priv = netdev_priv(ndev);
785 if (!priv->hw_enable) {
786 /* link is in low power mode now; duplex setting
787 * will take effect on next enc28j60_hw_init().
789 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
790 priv->full_duplex = (duplex == DUPLEX_FULL);
792 if (netif_msg_link(priv))
794 "unsupported link setting\n");
798 if (netif_msg_link(priv))
799 dev_warn(&ndev->dev, "Warning: hw must be disabled "
800 "to set link mode\n");
807 * Read the Transmit Status Vector
809 static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
813 endptr = locked_regw_read(priv, ETXNDL);
814 if (netif_msg_hw(priv))
815 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n",
817 enc28j60_mem_read(priv, endptr + 1, TSV_SIZE, tsv);
820 static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
825 printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg);
834 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d,"
835 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2);
836 printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
837 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE),
838 TSV_GETBIT(tsv, TSV_TXCRCERROR),
839 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
840 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
841 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
842 "PacketDefer: %d, ExDefer: %d\n",
843 TSV_GETBIT(tsv, TSV_TXMULTICAST),
844 TSV_GETBIT(tsv, TSV_TXBROADCAST),
845 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
846 TSV_GETBIT(tsv, TSV_TXEXDEFER));
847 printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, "
848 "Giant: %d, Underrun: %d\n",
849 TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
850 TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
851 TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
852 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, "
853 "BackPressApp: %d, VLanTagFrame: %d\n",
854 TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
855 TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
856 TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
857 TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
861 * Receive Status vector
863 static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
864 u16 pk_ptr, int len, u16 sts)
866 printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n",
868 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len,
869 RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
870 printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
871 " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK),
872 RSV_GETBIT(sts, RSV_CRCERROR),
873 RSV_GETBIT(sts, RSV_LENCHECKERR),
874 RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
875 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
876 "LongDropEvent: %d, CarrierEvent: %d\n",
877 RSV_GETBIT(sts, RSV_RXMULTICAST),
878 RSV_GETBIT(sts, RSV_RXBROADCAST),
879 RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
880 RSV_GETBIT(sts, RSV_CARRIEREV));
881 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d,"
882 " UnknownOp: %d, VLanTagFrame: %d\n",
883 RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
884 RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
885 RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
886 RSV_GETBIT(sts, RSV_RXTYPEVLAN));
889 static void dump_packet(const char *msg, int len, const char *data)
891 printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
892 print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
897 * Hardware receive function.
898 * Read the buffer memory, update the FIFO pointer to free the buffer,
899 * check the status vector and decrement the packet counter.
901 static void enc28j60_hw_rx(struct net_device *ndev)
903 struct enc28j60_net *priv = netdev_priv(ndev);
904 struct sk_buff *skb = NULL;
905 u16 erxrdpt, next_packet, rxstat;
909 if (netif_msg_rx_status(priv))
910 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n",
913 if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
914 if (netif_msg_rx_err(priv))
916 "%s() Invalid packet address!! 0x%04x\n",
917 __func__, priv->next_pk_ptr);
918 /* packet address corrupted: reset RX logic */
919 mutex_lock(&priv->lock);
920 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
921 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
922 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
923 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
924 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
925 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
926 mutex_unlock(&priv->lock);
927 ndev->stats.rx_errors++;
930 /* Read next packet pointer and rx status vector */
931 enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
933 next_packet = rsv[1];
935 next_packet |= rsv[0];
945 if (netif_msg_rx_status(priv))
946 enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
948 if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) {
949 if (netif_msg_rx_err(priv))
950 dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
951 ndev->stats.rx_errors++;
952 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
953 ndev->stats.rx_crc_errors++;
954 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
955 ndev->stats.rx_frame_errors++;
956 if (len > MAX_FRAMELEN)
957 ndev->stats.rx_over_errors++;
959 skb = dev_alloc_skb(len + NET_IP_ALIGN);
961 if (netif_msg_rx_err(priv))
963 "out of memory for Rx'd frame\n");
964 ndev->stats.rx_dropped++;
967 skb_reserve(skb, NET_IP_ALIGN);
968 /* copy the packet from the receive buffer */
969 enc28j60_mem_read(priv,
970 rx_packet_start(priv->next_pk_ptr),
971 len, skb_put(skb, len));
972 if (netif_msg_pktdata(priv))
973 dump_packet(__func__, skb->len, skb->data);
974 skb->protocol = eth_type_trans(skb, ndev);
975 /* update statistics */
976 ndev->stats.rx_packets++;
977 ndev->stats.rx_bytes += len;
982 * Move the RX read pointer to the start of the next
984 * This frees the memory we just read out
986 erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
987 if (netif_msg_hw(priv))
988 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n",
991 mutex_lock(&priv->lock);
992 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
993 #ifdef CONFIG_ENC28J60_WRITEVERIFY
994 if (netif_msg_drv(priv)) {
996 reg = nolock_regw_read(priv, ERXRDPTL);
998 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify "
999 "error (0x%04x - 0x%04x)\n", __func__,
1003 priv->next_pk_ptr = next_packet;
1004 /* we are done with this packet, decrement the packet counter */
1005 nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
1006 mutex_unlock(&priv->lock);
1010 * Calculate free space in RxFIFO
1012 static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
1014 int epkcnt, erxst, erxnd, erxwr, erxrd;
1017 mutex_lock(&priv->lock);
1018 epkcnt = nolock_regb_read(priv, EPKTCNT);
1022 erxst = nolock_regw_read(priv, ERXSTL);
1023 erxnd = nolock_regw_read(priv, ERXNDL);
1024 erxwr = nolock_regw_read(priv, ERXWRPTL);
1025 erxrd = nolock_regw_read(priv, ERXRDPTL);
1028 free_space = (erxnd - erxst) - (erxwr - erxrd);
1029 else if (erxwr == erxrd)
1030 free_space = (erxnd - erxst);
1032 free_space = erxrd - erxwr - 1;
1034 mutex_unlock(&priv->lock);
1035 if (netif_msg_rx_status(priv))
1036 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n",
1037 __func__, free_space);
1042 * Access the PHY to determine link status
1044 static void enc28j60_check_link_status(struct net_device *ndev)
1046 struct enc28j60_net *priv = netdev_priv(ndev);
1050 reg = enc28j60_phy_read(priv, PHSTAT2);
1051 if (netif_msg_hw(priv))
1052 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, "
1053 "PHSTAT2: %04x\n", __func__,
1054 enc28j60_phy_read(priv, PHSTAT1), reg);
1055 duplex = reg & PHSTAT2_DPXSTAT;
1057 if (reg & PHSTAT2_LSTAT) {
1058 netif_carrier_on(ndev);
1059 if (netif_msg_ifup(priv))
1060 dev_info(&ndev->dev, "link up - %s\n",
1061 duplex ? "Full duplex" : "Half duplex");
1063 if (netif_msg_ifdown(priv))
1064 dev_info(&ndev->dev, "link down\n");
1065 netif_carrier_off(ndev);
1069 static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1071 struct enc28j60_net *priv = netdev_priv(ndev);
1074 ndev->stats.tx_errors++;
1076 ndev->stats.tx_packets++;
1080 ndev->stats.tx_bytes += priv->tx_skb->len;
1081 dev_kfree_skb(priv->tx_skb);
1082 priv->tx_skb = NULL;
1084 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1085 netif_wake_queue(ndev);
1090 * ignore PKTIF because is unreliable! (look at the errata datasheet)
1091 * check EPKTCNT is the suggested workaround.
1092 * We don't need to clear interrupt flag, automatically done when
1093 * enc28j60_hw_rx() decrements the packet counter.
1094 * Returns how many packet processed.
1096 static int enc28j60_rx_interrupt(struct net_device *ndev)
1098 struct enc28j60_net *priv = netdev_priv(ndev);
1099 int pk_counter, ret;
1101 pk_counter = locked_regb_read(priv, EPKTCNT);
1102 if (pk_counter && netif_msg_intr(priv))
1103 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter);
1104 if (pk_counter > priv->max_pk_counter) {
1105 /* update statistics */
1106 priv->max_pk_counter = pk_counter;
1107 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1108 printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n",
1109 priv->max_pk_counter);
1112 while (pk_counter-- > 0)
1113 enc28j60_hw_rx(ndev);
1118 static void enc28j60_irq_work_handler(struct work_struct *work)
1120 struct enc28j60_net *priv =
1121 container_of(work, struct enc28j60_net, irq_work);
1122 struct net_device *ndev = priv->netdev;
1125 if (netif_msg_intr(priv))
1126 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1127 /* disable further interrupts */
1128 locked_reg_bfclr(priv, EIE, EIE_INTIE);
1132 intflags = locked_regb_read(priv, EIR);
1133 /* DMA interrupt handler (not currently used) */
1134 if ((intflags & EIR_DMAIF) != 0) {
1136 if (netif_msg_intr(priv))
1137 printk(KERN_DEBUG DRV_NAME
1138 ": intDMA(%d)\n", loop);
1139 locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1141 /* LINK changed handler */
1142 if ((intflags & EIR_LINKIF) != 0) {
1144 if (netif_msg_intr(priv))
1145 printk(KERN_DEBUG DRV_NAME
1146 ": intLINK(%d)\n", loop);
1147 enc28j60_check_link_status(ndev);
1148 /* read PHIR to clear the flag */
1149 enc28j60_phy_read(priv, PHIR);
1151 /* TX complete handler */
1152 if ((intflags & EIR_TXIF) != 0) {
1155 if (netif_msg_intr(priv))
1156 printk(KERN_DEBUG DRV_NAME
1157 ": intTX(%d)\n", loop);
1158 priv->tx_retry_count = 0;
1159 if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1160 if (netif_msg_tx_err(priv))
1162 "Tx Error (aborted)\n");
1165 if (netif_msg_tx_done(priv)) {
1167 enc28j60_read_tsv(priv, tsv);
1168 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1170 enc28j60_tx_clear(ndev, err);
1171 locked_reg_bfclr(priv, EIR, EIR_TXIF);
1173 /* TX Error handler */
1174 if ((intflags & EIR_TXERIF) != 0) {
1178 if (netif_msg_intr(priv))
1179 printk(KERN_DEBUG DRV_NAME
1180 ": intTXErr(%d)\n", loop);
1181 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1182 enc28j60_read_tsv(priv, tsv);
1183 if (netif_msg_tx_err(priv))
1184 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1185 /* Reset TX logic */
1186 mutex_lock(&priv->lock);
1187 nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1188 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1189 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1190 mutex_unlock(&priv->lock);
1191 /* Transmit Late collision check for retransmit */
1192 if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1193 if (netif_msg_tx_err(priv))
1194 printk(KERN_DEBUG DRV_NAME
1195 ": LateCollision TXErr (%d)\n",
1196 priv->tx_retry_count);
1197 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1198 locked_reg_bfset(priv, ECON1,
1201 enc28j60_tx_clear(ndev, true);
1203 enc28j60_tx_clear(ndev, true);
1204 locked_reg_bfclr(priv, EIR, EIR_TXERIF);
1206 /* RX Error handler */
1207 if ((intflags & EIR_RXERIF) != 0) {
1209 if (netif_msg_intr(priv))
1210 printk(KERN_DEBUG DRV_NAME
1211 ": intRXErr(%d)\n", loop);
1212 /* Check free FIFO space to flag RX overrun */
1213 if (enc28j60_get_free_rxfifo(priv) <= 0) {
1214 if (netif_msg_rx_err(priv))
1215 printk(KERN_DEBUG DRV_NAME
1217 ndev->stats.rx_dropped++;
1219 locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1222 if (enc28j60_rx_interrupt(ndev))
1226 /* re-enable interrupts */
1227 locked_reg_bfset(priv, EIE, EIE_INTIE);
1228 if (netif_msg_intr(priv))
1229 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __func__);
1233 * Hardware transmit function.
1234 * Fill the buffer memory and send the contents of the transmit buffer
1237 static void enc28j60_hw_tx(struct enc28j60_net *priv)
1239 if (netif_msg_tx_queued(priv))
1240 printk(KERN_DEBUG DRV_NAME
1241 ": Tx Packet Len:%d\n", priv->tx_skb->len);
1243 if (netif_msg_pktdata(priv))
1244 dump_packet(__func__,
1245 priv->tx_skb->len, priv->tx_skb->data);
1246 enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1248 #ifdef CONFIG_ENC28J60_WRITEVERIFY
1249 /* readback and verify written data */
1250 if (netif_msg_drv(priv)) {
1252 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1255 test_len = priv->tx_skb->len;
1256 if (test_len > sizeof(test_buf))
1257 test_len = sizeof(test_buf);
1259 /* + 1 to skip control byte */
1260 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1262 for (k = 0; k < test_len; k++) {
1263 if (priv->tx_skb->data[k] != test_buf[k]) {
1264 printk(KERN_DEBUG DRV_NAME
1265 ": Error, %d location differ: "
1266 "0x%02x-0x%02x\n", k,
1267 priv->tx_skb->data[k], test_buf[k]);
1272 printk(KERN_DEBUG DRV_NAME ": Tx write buffer, "
1276 /* set TX request flag */
1277 locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1280 static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb,
1281 struct net_device *dev)
1283 struct enc28j60_net *priv = netdev_priv(dev);
1285 if (netif_msg_tx_queued(priv))
1286 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1288 /* If some error occurs while trying to transmit this
1289 * packet, you should return '1' from this function.
1290 * In such a case you _may not_ do anything to the
1291 * SKB, it is still owned by the network queueing
1292 * layer when an error is returned. This means you
1293 * may not modify any SKB fields, you may not free
1296 netif_stop_queue(dev);
1298 /* Remember the skb for deferred processing */
1300 schedule_work(&priv->tx_work);
1302 return NETDEV_TX_OK;
1305 static void enc28j60_tx_work_handler(struct work_struct *work)
1307 struct enc28j60_net *priv =
1308 container_of(work, struct enc28j60_net, tx_work);
1310 /* actual delivery of data */
1311 enc28j60_hw_tx(priv);
1314 static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1316 struct enc28j60_net *priv = dev_id;
1319 * Can't do anything in interrupt context because we need to
1320 * block (spi_sync() is blocking) so fire of the interrupt
1321 * handling workqueue.
1322 * Remember that we access enc28j60 registers through SPI bus
1323 * via spi_sync() call.
1325 schedule_work(&priv->irq_work);
1330 static void enc28j60_tx_timeout(struct net_device *ndev)
1332 struct enc28j60_net *priv = netdev_priv(ndev);
1334 if (netif_msg_timer(priv))
1335 dev_err(&ndev->dev, DRV_NAME " tx timeout\n");
1337 ndev->stats.tx_errors++;
1338 /* can't restart safely under softirq */
1339 schedule_work(&priv->restart_work);
1343 * Open/initialize the board. This is called (in the current kernel)
1344 * sometime after booting when the 'ifconfig' program is run.
1346 * This routine should set everything up anew at each open, even
1347 * registers that "should" only need to be set once at boot, so that
1348 * there is non-reboot way to recover if something goes wrong.
1350 static int enc28j60_net_open(struct net_device *dev)
1352 struct enc28j60_net *priv = netdev_priv(dev);
1354 if (netif_msg_drv(priv))
1355 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1357 if (!is_valid_ether_addr(dev->dev_addr)) {
1358 if (netif_msg_ifup(priv))
1359 dev_err(&dev->dev, "invalid MAC address %pM\n",
1361 return -EADDRNOTAVAIL;
1363 /* Reset the hardware here (and take it out of low power mode) */
1364 enc28j60_lowpower(priv, false);
1365 enc28j60_hw_disable(priv);
1366 if (!enc28j60_hw_init(priv)) {
1367 if (netif_msg_ifup(priv))
1368 dev_err(&dev->dev, "hw_reset() failed\n");
1371 /* Update the MAC address (in case user has changed it) */
1372 enc28j60_set_hw_macaddr(dev);
1373 /* Enable interrupts */
1374 enc28j60_hw_enable(priv);
1375 /* check link status */
1376 enc28j60_check_link_status(dev);
1377 /* We are now ready to accept transmit requests from
1378 * the queueing layer of the networking.
1380 netif_start_queue(dev);
1385 /* The inverse routine to net_open(). */
1386 static int enc28j60_net_close(struct net_device *dev)
1388 struct enc28j60_net *priv = netdev_priv(dev);
1390 if (netif_msg_drv(priv))
1391 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1393 enc28j60_hw_disable(priv);
1394 enc28j60_lowpower(priv, true);
1395 netif_stop_queue(dev);
1401 * Set or clear the multicast filter for this adapter
1402 * num_addrs == -1 Promiscuous mode, receive all packets
1403 * num_addrs == 0 Normal mode, filter out multicast packets
1404 * num_addrs > 0 Multicast mode, receive normal and MC packets
1406 static void enc28j60_set_multicast_list(struct net_device *dev)
1408 struct enc28j60_net *priv = netdev_priv(dev);
1409 int oldfilter = priv->rxfilter;
1411 if (dev->flags & IFF_PROMISC) {
1412 if (netif_msg_link(priv))
1413 dev_info(&dev->dev, "promiscuous mode\n");
1414 priv->rxfilter = RXFILTER_PROMISC;
1415 } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
1416 if (netif_msg_link(priv))
1417 dev_info(&dev->dev, "%smulticast mode\n",
1418 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1419 priv->rxfilter = RXFILTER_MULTI;
1421 if (netif_msg_link(priv))
1422 dev_info(&dev->dev, "normal mode\n");
1423 priv->rxfilter = RXFILTER_NORMAL;
1426 if (oldfilter != priv->rxfilter)
1427 schedule_work(&priv->setrx_work);
1430 static void enc28j60_setrx_work_handler(struct work_struct *work)
1432 struct enc28j60_net *priv =
1433 container_of(work, struct enc28j60_net, setrx_work);
1435 if (priv->rxfilter == RXFILTER_PROMISC) {
1436 if (netif_msg_drv(priv))
1437 printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n");
1438 locked_regb_write(priv, ERXFCON, 0x00);
1439 } else if (priv->rxfilter == RXFILTER_MULTI) {
1440 if (netif_msg_drv(priv))
1441 printk(KERN_DEBUG DRV_NAME ": multicast mode\n");
1442 locked_regb_write(priv, ERXFCON,
1443 ERXFCON_UCEN | ERXFCON_CRCEN |
1444 ERXFCON_BCEN | ERXFCON_MCEN);
1446 if (netif_msg_drv(priv))
1447 printk(KERN_DEBUG DRV_NAME ": normal mode\n");
1448 locked_regb_write(priv, ERXFCON,
1449 ERXFCON_UCEN | ERXFCON_CRCEN |
1454 static void enc28j60_restart_work_handler(struct work_struct *work)
1456 struct enc28j60_net *priv =
1457 container_of(work, struct enc28j60_net, restart_work);
1458 struct net_device *ndev = priv->netdev;
1462 if (netif_running(ndev)) {
1463 enc28j60_net_close(ndev);
1464 ret = enc28j60_net_open(ndev);
1465 if (unlikely(ret)) {
1466 dev_info(&ndev->dev, " could not restart %d\n", ret);
1473 /* ......................... ETHTOOL SUPPORT ........................... */
1476 enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1478 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1479 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1480 strlcpy(info->bus_info,
1481 dev_name(dev->dev.parent), sizeof(info->bus_info));
1485 enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1487 struct enc28j60_net *priv = netdev_priv(dev);
1489 cmd->transceiver = XCVR_INTERNAL;
1490 cmd->supported = SUPPORTED_10baseT_Half
1491 | SUPPORTED_10baseT_Full
1493 ethtool_cmd_speed_set(cmd, SPEED_10);
1494 cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1495 cmd->port = PORT_TP;
1496 cmd->autoneg = AUTONEG_DISABLE;
1502 enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1504 return enc28j60_setlink(dev, cmd->autoneg,
1505 ethtool_cmd_speed(cmd), cmd->duplex);
1508 static u32 enc28j60_get_msglevel(struct net_device *dev)
1510 struct enc28j60_net *priv = netdev_priv(dev);
1511 return priv->msg_enable;
1514 static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1516 struct enc28j60_net *priv = netdev_priv(dev);
1517 priv->msg_enable = val;
1520 static const struct ethtool_ops enc28j60_ethtool_ops = {
1521 .get_settings = enc28j60_get_settings,
1522 .set_settings = enc28j60_set_settings,
1523 .get_drvinfo = enc28j60_get_drvinfo,
1524 .get_msglevel = enc28j60_get_msglevel,
1525 .set_msglevel = enc28j60_set_msglevel,
1528 static int enc28j60_chipset_init(struct net_device *dev)
1530 struct enc28j60_net *priv = netdev_priv(dev);
1532 return enc28j60_hw_init(priv);
1535 static const struct net_device_ops enc28j60_netdev_ops = {
1536 .ndo_open = enc28j60_net_open,
1537 .ndo_stop = enc28j60_net_close,
1538 .ndo_start_xmit = enc28j60_send_packet,
1539 .ndo_set_multicast_list = enc28j60_set_multicast_list,
1540 .ndo_set_mac_address = enc28j60_set_mac_address,
1541 .ndo_tx_timeout = enc28j60_tx_timeout,
1542 .ndo_change_mtu = eth_change_mtu,
1543 .ndo_validate_addr = eth_validate_addr,
1546 static int __devinit enc28j60_probe(struct spi_device *spi)
1548 struct net_device *dev;
1549 struct enc28j60_net *priv;
1551 unsigned long req_flags = IRQF_TRIGGER_FALLING;
1552 int gpioToIrq = gpio_to_irq (MAC_INT_PORT);
1554 gpio_request(MAC_INT_PORT, "DRV_NAME");
1555 if (netif_msg_drv(&debug))
1556 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
1559 dev = alloc_etherdev(sizeof(struct enc28j60_net));
1561 if (netif_msg_drv(&debug))
1562 dev_err(&spi->dev, DRV_NAME
1563 ": unable to alloc new ethernet\n");
1567 priv = netdev_priv(dev);
1569 priv->netdev = dev; /* priv to netdev reference */
1570 priv->spi = spi; /* priv to spi reference */
1571 priv->msg_enable = netif_msg_init(debug.msg_enable,
1572 ENC28J60_MSG_DEFAULT);
1573 mutex_init(&priv->lock);
1574 INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1575 INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1576 INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1577 INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1578 dev_set_drvdata(&spi->dev, priv); /* spi to priv reference */
1579 SET_NETDEV_DEV(dev, &spi->dev);
1581 if (!enc28j60_chipset_init(dev)) {
1582 if (netif_msg_probe(priv))
1583 dev_info(&spi->dev, DRV_NAME " chip not found\n");
1587 random_ether_addr(dev->dev_addr);
1588 enc28j60_set_hw_macaddr(dev);
1590 /* Board setup must set the relevant edge trigger type;
1591 * level triggers won't currently work.
1593 gpio_pull_updown(MAC_INT_PORT, GPIOPullUp);
1595 ret = request_irq(gpioToIrq, enc28j60_irq,req_flags, "DRV_NAME", priv);
1599 ///ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv);
1601 if (netif_msg_probe(priv))
1602 dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
1603 "(ret = %d)\n", spi->irq, ret);
1607 dev->if_port = IF_PORT_10BASET;
1608 dev->irq = spi->irq;
1609 dev->netdev_ops = &enc28j60_netdev_ops;
1610 dev->watchdog_timeo = TX_TIMEOUT;
1611 SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops);
1613 enc28j60_lowpower(priv, true);
1615 ret = register_netdev(dev);
1617 if (netif_msg_probe(priv))
1618 dev_err(&spi->dev, "register netdev " DRV_NAME
1619 " failed (ret = %d)\n", ret);
1620 goto error_register;
1622 dev_info(&dev->dev, DRV_NAME " driver registered\n");
1627 free_irq(spi->irq, priv);
1634 static int __devexit enc28j60_remove(struct spi_device *spi)
1636 struct enc28j60_net *priv = dev_get_drvdata(&spi->dev);
1638 if (netif_msg_drv(priv))
1639 printk(KERN_DEBUG DRV_NAME ": remove\n");
1641 unregister_netdev(priv->netdev);
1642 free_irq(spi->irq, priv);
1643 free_netdev(priv->netdev);
1648 static struct spi_driver enc28j60_driver = {
1651 .owner = THIS_MODULE,
1653 .probe = enc28j60_probe,
1654 .remove = __devexit_p(enc28j60_remove),
1657 static int __init enc28j60_init(void)
1659 msec20_to_jiffies = msecs_to_jiffies(20);
1661 return spi_register_driver(&enc28j60_driver);
1664 module_init(enc28j60_init);
1666 static void __exit enc28j60_exit(void)
1668 spi_unregister_driver(&enc28j60_driver);
1671 module_exit(enc28j60_exit);
1673 MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1674 MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1675 MODULE_LICENSE("GPL");
1676 module_param_named(debug, debug.msg_enable, int, 0);
1677 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");
1678 MODULE_ALIAS("spi:" DRV_NAME);