1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
3 Written 1996-1999 by Donald Becker.
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
12 Problem reports and questions should be directed to
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
32 #define DRV_NAME "3c59x"
36 /* A few values that may be tweaked. */
37 /* Keep the ring sizes a power of two for efficiency. */
38 #define TX_RING_SIZE 16
39 #define RX_RING_SIZE 32
40 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
42 /* "Knobs" that adjust features and parameters. */
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
46 static int rx_copybreak = 200;
48 /* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50 static int rx_copybreak = 1513;
52 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53 static const int mtu = 1500;
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static int max_interrupt_work = 32;
56 /* Tx timeout interval (millisecs) */
57 static int watchdog = 5000;
59 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
63 #define tx_interrupt_mitigation 1
65 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66 #define vortex_debug debug
68 static int vortex_debug = VORTEX_DEBUG;
70 static int vortex_debug = 1;
73 #include <linux/module.h>
74 #include <linux/kernel.h>
75 #include <linux/string.h>
76 #include <linux/timer.h>
77 #include <linux/errno.h>
79 #include <linux/ioport.h>
80 #include <linux/interrupt.h>
81 #include <linux/pci.h>
82 #include <linux/mii.h>
83 #include <linux/init.h>
84 #include <linux/netdevice.h>
85 #include <linux/etherdevice.h>
86 #include <linux/skbuff.h>
87 #include <linux/ethtool.h>
88 #include <linux/highmem.h>
89 #include <linux/eisa.h>
90 #include <linux/bitops.h>
91 #include <linux/jiffies.h>
92 #include <linux/gfp.h>
93 #include <asm/irq.h> /* For nr_irqs only. */
95 #include <asm/uaccess.h>
97 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
100 #define RUN_AT(x) (jiffies + (x))
102 #include <linux/delay.h>
105 static const char version[] =
106 DRV_NAME ": Donald Becker and others.\n";
108 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110 MODULE_LICENSE("GPL");
113 /* Operational parameter that usually are not changed. */
115 /* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119 #define VORTEX_TOTAL_SIZE 0x20
120 #define BOOMERANG_TOTAL_SIZE 0x40
122 /* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125 static char mii_preamble_required;
127 #define PFX DRV_NAME ": "
134 I. Board Compatibility
136 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138 versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
141 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142 with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
145 II. Board-specific settings
147 PCI bus devices are configured by the system at boot time, so no jumpers
148 need to be set on the board. The system BIOS should be set to assign the
149 PCI INTA signal to an otherwise unused system IRQ line.
151 The EEPROM settings for media type and forced-full-duplex are observed.
152 The EEPROM media type should be left at the default "autoselect" unless using
153 10base2 or AUI connections which cannot be reliably detected.
155 III. Driver operation
157 The 3c59x series use an interface that's very similar to the previous 3c5x9
158 series. The primary interface is two programmed-I/O FIFOs, with an
159 alternate single-contiguous-region bus-master transfer (see next).
161 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164 programmed-I/O interface that has been removed in 'B' and subsequent board
167 One extension that is advertised in a very large font is that the adapters
168 are capable of being bus masters. On the Vortex chip this capability was
169 only for a single contiguous region making it far less useful than the full
170 bus master capability. There is a significant performance impact of taking
171 an extra interrupt or polling for the completion of each transfer, as well
172 as difficulty sharing the single transfer engine between the transmit and
173 receive threads. Using DMA transfers is a win only with large blocks or
174 with the flawed versions of the Intel Orion motherboard PCI controller.
176 The Boomerang chip's full-bus-master interface is useful, and has the
177 currently-unused advantages over other similar chips that queued transmit
178 packets may be reordered and receive buffer groups are associated with a
181 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182 Rather than a fixed intermediate receive buffer, this scheme allocates
183 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184 the copying breakpoint: it is chosen to trade-off the memory wasted by
185 passing the full-sized skbuff to the queue layer for all frames vs. the
186 copying cost of copying a frame to a correctly-sized skbuff.
188 IIIC. Synchronization
189 The driver runs as two independent, single-threaded flows of control. One
190 is the send-packet routine, which enforces single-threaded use by the
191 dev->tbusy flag. The other thread is the interrupt handler, which is single
192 threaded by the hardware and other software.
196 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
197 3c590, 3c595, and 3c900 boards.
198 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199 the EISA version is called "Demon". According to Terry these names come
200 from rides at the local amusement park.
202 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203 This driver only supports ethernet packets because of the skbuff allocation
207 /* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
214 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
271 /* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
275 static struct vortex_chip_info {
280 } vortex_info_tbl[] = {
281 {"3c590 Vortex 10Mbps",
282 PCI_USES_MASTER, IS_VORTEX, 32, },
283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
284 PCI_USES_MASTER, IS_VORTEX, 32, },
285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
286 PCI_USES_MASTER, IS_VORTEX, 32, },
287 {"3c595 Vortex 100baseTx",
288 PCI_USES_MASTER, IS_VORTEX, 32, },
289 {"3c595 Vortex 100baseT4",
290 PCI_USES_MASTER, IS_VORTEX, 32, },
292 {"3c595 Vortex 100base-MII",
293 PCI_USES_MASTER, IS_VORTEX, 32, },
294 {"3c900 Boomerang 10baseT",
295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
296 {"3c900 Boomerang 10Mbps Combo",
297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
300 {"3c900 Cyclone 10Mbps Combo",
301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
305 {"3c900B-FL Cyclone 10base-FL",
306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
307 {"3c905 Boomerang 100baseTx",
308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
309 {"3c905 Boomerang 100baseT4",
310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 100baseTx",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
316 {"3c905B Cyclone 10/100/BNC",
317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
318 {"3c905B-FX Cyclone 100baseFx",
319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
329 {"3cSOHO100-TX Hurricane",
330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
331 {"3c555 Laptop Hurricane",
332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
333 {"3c556 Laptop Tornado",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
336 {"3c556B Laptop Hurricane",
337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
342 {"3c575 Boomerang CardBus",
343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
344 {"3CCFE575BT Cyclone CardBus",
345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
364 {"3c982 Hydra Dual Port A",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
367 {"3c982 Hydra Dual Port B",
368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
371 {"3c920B-EMB-WNM Tornado",
372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
374 {NULL,}, /* NULL terminated list. */
378 static const struct pci_device_id vortex_pci_tbl[] = {
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
426 {0,} /* 0 terminated list. */
428 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
431 /* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
439 #define EL3_STATUS 0x0e
441 /* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
459 /* The SetRxFilter command accepts the following classes: */
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
463 /* Bits in the general status register. */
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
473 /* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
485 enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
490 /* EEPROM locations. */
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
497 enum Window2 { /* Window 2. */
500 enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
504 #define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
507 #define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
511 #define RAM_SIZE(v) BFEXT(v, 0, 3)
512 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
513 #define RAM_SPEED(v) BFEXT(v, 4, 2)
514 #define ROM_SIZE(v) BFEXT(v, 6, 2)
515 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
516 #define XCVR(v) BFEXT(v, 20, 4)
517 #define AUTOSELECT(v) BFEXT(v, 24, 1)
519 enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
522 enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
528 enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
532 /* Boomerang bus master control registers. */
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
538 /* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543 struct boom_rx_desc {
544 __le32 next; /* Last entry points to 0. */
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
549 /* Values for the Rx status entry. */
550 enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
558 #define DO_ZEROCOPY 1
560 #define DO_ZEROCOPY 0
563 struct boom_tx_desc {
564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
570 } frag[1+MAX_SKB_FRAGS];
577 /* Values for the Tx status entry. */
578 enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
584 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
585 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
587 struct vortex_extra_stats {
588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
595 struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
610 /* PCI configuration space information. */
611 struct device *gendev;
612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
625 full_duplex:1, autoselect:1,
626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
635 large_frames:1, /* accept large frames */
636 handling_irq:1; /* private in_irq indicator */
637 /* {get|set}_wol operations are already serialized by rtnl.
638 * no additional locking is required for the enable_wol and acpi_set_WOL()
643 u16 available_media; /* From Wn3_Options. */
644 u16 capabilities, info1, info2; /* Various, from EEPROM. */
645 u16 advertising; /* NWay media advertisement */
646 unsigned char phys[2]; /* MII device addresses. */
647 u16 deferred; /* Resend these interrupts when we
648 * bale from the ISR */
649 u16 io_size; /* Size of PCI region (for release_region) */
651 /* Serialises access to hardware other than MII and variables below.
652 * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
655 spinlock_t mii_lock; /* Serialises access to MII */
656 struct mii_if_info mii; /* MII lib hooks/info */
657 spinlock_t window_lock; /* Serialises access to windowed regs */
658 int window; /* Register window */
661 static void window_set(struct vortex_private *vp, int window)
663 if (window != vp->window) {
664 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
669 #define DEFINE_WINDOW_IO(size) \
671 window_read ## size(struct vortex_private *vp, int window, int addr) \
673 unsigned long flags; \
675 spin_lock_irqsave(&vp->window_lock, flags); \
676 window_set(vp, window); \
677 ret = ioread ## size(vp->ioaddr + addr); \
678 spin_unlock_irqrestore(&vp->window_lock, flags); \
682 window_write ## size(struct vortex_private *vp, u ## size value, \
683 int window, int addr) \
685 unsigned long flags; \
686 spin_lock_irqsave(&vp->window_lock, flags); \
687 window_set(vp, window); \
688 iowrite ## size(value, vp->ioaddr + addr); \
689 spin_unlock_irqrestore(&vp->window_lock, flags); \
696 #define DEVICE_PCI(dev) ((dev_is_pci(dev)) ? to_pci_dev((dev)) : NULL)
698 #define DEVICE_PCI(dev) NULL
701 #define VORTEX_PCI(vp) \
702 ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
705 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
707 #define DEVICE_EISA(dev) NULL
710 #define VORTEX_EISA(vp) \
711 ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
713 /* The action to take with a media selection timer tick.
714 Note that we deviate from the 3Com order by checking 10base2 before AUI.
717 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
718 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
721 static const struct media_table {
723 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
724 mask:8, /* The transceiver-present bit in Wn3_Config.*/
725 next:8; /* The media type to try next. */
726 int wait; /* Time before we check media status. */
728 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
729 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
730 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
731 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
732 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
733 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
734 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
735 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
736 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
737 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
738 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
742 const char str[ETH_GSTRING_LEN];
743 } ethtool_stats_keys[] = {
745 { "tx_max_collisions" },
746 { "tx_multiple_collisions" },
747 { "tx_single_collisions" },
751 /* number of ETHTOOL_GSTATS u64's */
752 #define VORTEX_NUM_STATS 5
754 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
755 int chip_idx, int card_idx);
756 static int vortex_up(struct net_device *dev);
757 static void vortex_down(struct net_device *dev, int final);
758 static int vortex_open(struct net_device *dev);
759 static void mdio_sync(struct vortex_private *vp, int bits);
760 static int mdio_read(struct net_device *dev, int phy_id, int location);
761 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
762 static void vortex_timer(unsigned long arg);
763 static void rx_oom_timer(unsigned long arg);
764 static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
765 struct net_device *dev);
766 static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
767 struct net_device *dev);
768 static int vortex_rx(struct net_device *dev);
769 static int boomerang_rx(struct net_device *dev);
770 static irqreturn_t vortex_interrupt(int irq, void *dev_id);
771 static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
772 static int vortex_close(struct net_device *dev);
773 static void dump_tx_ring(struct net_device *dev);
774 static void update_stats(void __iomem *ioaddr, struct net_device *dev);
775 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
776 static void set_rx_mode(struct net_device *dev);
778 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
780 static void vortex_tx_timeout(struct net_device *dev);
781 static void acpi_set_WOL(struct net_device *dev);
782 static const struct ethtool_ops vortex_ethtool_ops;
783 static void set_8021q_mode(struct net_device *dev, int enable);
785 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
786 /* Option count limit only -- unlimited interfaces are supported. */
788 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
789 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
790 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
791 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
792 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
793 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
794 static int global_options = -1;
795 static int global_full_duplex = -1;
796 static int global_enable_wol = -1;
797 static int global_use_mmio = -1;
799 /* Variables to work-around the Compaq PCI BIOS32 problem. */
800 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
801 static struct net_device *compaq_net_device;
803 static int vortex_cards_found;
805 module_param(debug, int, 0);
806 module_param(global_options, int, 0);
807 module_param_array(options, int, NULL, 0);
808 module_param(global_full_duplex, int, 0);
809 module_param_array(full_duplex, int, NULL, 0);
810 module_param_array(hw_checksums, int, NULL, 0);
811 module_param_array(flow_ctrl, int, NULL, 0);
812 module_param(global_enable_wol, int, 0);
813 module_param_array(enable_wol, int, NULL, 0);
814 module_param(rx_copybreak, int, 0);
815 module_param(max_interrupt_work, int, 0);
816 module_param(compaq_ioaddr, int, 0);
817 module_param(compaq_irq, int, 0);
818 module_param(compaq_device_id, int, 0);
819 module_param(watchdog, int, 0);
820 module_param(global_use_mmio, int, 0);
821 module_param_array(use_mmio, int, NULL, 0);
822 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
823 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
824 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
825 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
826 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
827 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
828 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
829 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
830 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
831 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
832 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
833 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
834 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
835 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
836 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
837 MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
838 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
840 #ifdef CONFIG_NET_POLL_CONTROLLER
841 static void poll_vortex(struct net_device *dev)
843 struct vortex_private *vp = netdev_priv(dev);
845 local_irq_save(flags);
846 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
847 local_irq_restore(flags);
853 static int vortex_suspend(struct device *dev)
855 struct pci_dev *pdev = to_pci_dev(dev);
856 struct net_device *ndev = pci_get_drvdata(pdev);
858 if (!ndev || !netif_running(ndev))
861 netif_device_detach(ndev);
862 vortex_down(ndev, 1);
867 static int vortex_resume(struct device *dev)
869 struct pci_dev *pdev = to_pci_dev(dev);
870 struct net_device *ndev = pci_get_drvdata(pdev);
873 if (!ndev || !netif_running(ndev))
876 err = vortex_up(ndev);
880 netif_device_attach(ndev);
885 static const struct dev_pm_ops vortex_pm_ops = {
886 .suspend = vortex_suspend,
887 .resume = vortex_resume,
888 .freeze = vortex_suspend,
889 .thaw = vortex_resume,
890 .poweroff = vortex_suspend,
891 .restore = vortex_resume,
894 #define VORTEX_PM_OPS (&vortex_pm_ops)
896 #else /* !CONFIG_PM */
898 #define VORTEX_PM_OPS NULL
900 #endif /* !CONFIG_PM */
903 static struct eisa_device_id vortex_eisa_ids[] = {
904 { "TCM5920", CH_3C592 },
905 { "TCM5970", CH_3C597 },
908 MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
910 static int __init vortex_eisa_probe(struct device *device)
912 void __iomem *ioaddr;
913 struct eisa_device *edev;
915 edev = to_eisa_device(device);
917 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
920 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
922 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
923 edev->id.driver_data, vortex_cards_found)) {
924 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
928 vortex_cards_found++;
933 static int vortex_eisa_remove(struct device *device)
935 struct eisa_device *edev;
936 struct net_device *dev;
937 struct vortex_private *vp;
938 void __iomem *ioaddr;
940 edev = to_eisa_device(device);
941 dev = eisa_get_drvdata(edev);
944 pr_err("vortex_eisa_remove called for Compaq device!\n");
948 vp = netdev_priv(dev);
951 unregister_netdev(dev);
952 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
953 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
959 static struct eisa_driver vortex_eisa_driver = {
960 .id_table = vortex_eisa_ids,
963 .probe = vortex_eisa_probe,
964 .remove = vortex_eisa_remove
968 #endif /* CONFIG_EISA */
970 /* returns count found (>= 0), or negative on error */
971 static int __init vortex_eisa_init(void)
974 int orig_cards_found = vortex_cards_found;
979 err = eisa_driver_register (&vortex_eisa_driver);
982 * Because of the way EISA bus is probed, we cannot assume
983 * any device have been found when we exit from
984 * eisa_driver_register (the bus root driver may not be
985 * initialized yet). So we blindly assume something was
986 * found, and let the sysfs magic happened...
992 /* Special code to work-around the Compaq PCI BIOS32 problem. */
994 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
995 compaq_irq, compaq_device_id, vortex_cards_found++);
998 return vortex_cards_found - orig_cards_found + eisa_found;
1001 /* returns count (>= 0), or negative on error */
1002 static int vortex_init_one(struct pci_dev *pdev,
1003 const struct pci_device_id *ent)
1005 int rc, unit, pci_bar;
1006 struct vortex_chip_info *vci;
1007 void __iomem *ioaddr;
1009 /* wake up and enable device */
1010 rc = pci_enable_device(pdev);
1014 rc = pci_request_regions(pdev, DRV_NAME);
1018 unit = vortex_cards_found;
1020 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1021 /* Determine the default if the user didn't override us */
1022 vci = &vortex_info_tbl[ent->driver_data];
1023 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1024 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1025 pci_bar = use_mmio[unit] ? 1 : 0;
1027 pci_bar = global_use_mmio ? 1 : 0;
1029 ioaddr = pci_iomap(pdev, pci_bar, 0);
1030 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1031 ioaddr = pci_iomap(pdev, 0, 0);
1037 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1038 ent->driver_data, unit);
1042 vortex_cards_found++;
1046 pci_iounmap(pdev, ioaddr);
1048 pci_release_regions(pdev);
1050 pci_disable_device(pdev);
1055 static const struct net_device_ops boomrang_netdev_ops = {
1056 .ndo_open = vortex_open,
1057 .ndo_stop = vortex_close,
1058 .ndo_start_xmit = boomerang_start_xmit,
1059 .ndo_tx_timeout = vortex_tx_timeout,
1060 .ndo_get_stats = vortex_get_stats,
1062 .ndo_do_ioctl = vortex_ioctl,
1064 .ndo_set_rx_mode = set_rx_mode,
1065 .ndo_change_mtu = eth_change_mtu,
1066 .ndo_set_mac_address = eth_mac_addr,
1067 .ndo_validate_addr = eth_validate_addr,
1068 #ifdef CONFIG_NET_POLL_CONTROLLER
1069 .ndo_poll_controller = poll_vortex,
1073 static const struct net_device_ops vortex_netdev_ops = {
1074 .ndo_open = vortex_open,
1075 .ndo_stop = vortex_close,
1076 .ndo_start_xmit = vortex_start_xmit,
1077 .ndo_tx_timeout = vortex_tx_timeout,
1078 .ndo_get_stats = vortex_get_stats,
1080 .ndo_do_ioctl = vortex_ioctl,
1082 .ndo_set_rx_mode = set_rx_mode,
1083 .ndo_change_mtu = eth_change_mtu,
1084 .ndo_set_mac_address = eth_mac_addr,
1085 .ndo_validate_addr = eth_validate_addr,
1086 #ifdef CONFIG_NET_POLL_CONTROLLER
1087 .ndo_poll_controller = poll_vortex,
1092 * Start up the PCI/EISA device which is described by *gendev.
1093 * Return 0 on success.
1095 * NOTE: pdev can be NULL, for the case of a Compaq device
1097 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1098 int chip_idx, int card_idx)
1100 struct vortex_private *vp;
1102 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1104 struct net_device *dev;
1105 static int printed_version;
1106 int retval, print_info;
1107 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1108 const char *print_name = "3c59x";
1109 struct pci_dev *pdev = NULL;
1110 struct eisa_device *edev = NULL;
1112 if (!printed_version) {
1113 pr_info("%s", version);
1114 printed_version = 1;
1118 if ((pdev = DEVICE_PCI(gendev))) {
1119 print_name = pci_name(pdev);
1122 if ((edev = DEVICE_EISA(gendev))) {
1123 print_name = dev_name(&edev->dev);
1127 dev = alloc_etherdev(sizeof(*vp));
1132 SET_NETDEV_DEV(dev, gendev);
1133 vp = netdev_priv(dev);
1135 option = global_options;
1137 /* The lower four bits are the media type. */
1138 if (dev->mem_start) {
1140 * The 'options' param is passed in as the third arg to the
1141 * LILO 'ether=' argument for non-modular use
1143 option = dev->mem_start;
1145 else if (card_idx < MAX_UNITS) {
1146 if (options[card_idx] >= 0)
1147 option = options[card_idx];
1151 if (option & 0x8000)
1153 if (option & 0x4000)
1155 if (option & 0x0400)
1159 print_info = (vortex_debug > 1);
1161 pr_info("See Documentation/networking/vortex.txt\n");
1163 pr_info("%s: 3Com %s %s at %p.\n",
1165 pdev ? "PCI" : "EISA",
1169 dev->base_addr = (unsigned long)ioaddr;
1172 vp->ioaddr = ioaddr;
1173 vp->large_frames = mtu > 1500;
1174 vp->drv_flags = vci->drv_flags;
1175 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1176 vp->io_size = vci->io_size;
1177 vp->card_idx = card_idx;
1180 /* module list only for Compaq device */
1181 if (gendev == NULL) {
1182 compaq_net_device = dev;
1185 /* PCI-only startup logic */
1187 /* enable bus-mastering if necessary */
1188 if (vci->flags & PCI_USES_MASTER)
1189 pci_set_master(pdev);
1191 if (vci->drv_flags & IS_VORTEX) {
1193 u8 new_latency = 248;
1195 /* Check the PCI latency value. On the 3c590 series the latency timer
1196 must be set to the maximum value to avoid data corruption that occurs
1197 when the timer expires during a transfer. This bug exists the Vortex
1199 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1200 if (pci_latency < new_latency) {
1201 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1202 print_name, pci_latency, new_latency);
1203 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1208 spin_lock_init(&vp->lock);
1209 spin_lock_init(&vp->mii_lock);
1210 spin_lock_init(&vp->window_lock);
1211 vp->gendev = gendev;
1213 vp->mii.mdio_read = mdio_read;
1214 vp->mii.mdio_write = mdio_write;
1215 vp->mii.phy_id_mask = 0x1f;
1216 vp->mii.reg_num_mask = 0x1f;
1218 /* Makes sure rings are at least 16 byte aligned. */
1219 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1220 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1226 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1227 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1229 /* if we are a PCI driver, we store info in pdev->driver_data
1230 * instead of a module list */
1232 pci_set_drvdata(pdev, dev);
1234 eisa_set_drvdata(edev, dev);
1236 vp->media_override = 7;
1238 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1239 if (vp->media_override != 7)
1241 vp->full_duplex = (option & 0x200) ? 1 : 0;
1242 vp->bus_master = (option & 16) ? 1 : 0;
1245 if (global_full_duplex > 0)
1246 vp->full_duplex = 1;
1247 if (global_enable_wol > 0)
1250 if (card_idx < MAX_UNITS) {
1251 if (full_duplex[card_idx] > 0)
1252 vp->full_duplex = 1;
1253 if (flow_ctrl[card_idx] > 0)
1255 if (enable_wol[card_idx] > 0)
1259 vp->mii.force_media = vp->full_duplex;
1260 vp->options = option;
1261 /* Read the station address from the EEPROM. */
1265 if (vci->drv_flags & EEPROM_8BIT)
1267 else if (vci->drv_flags & EEPROM_OFFSET)
1268 base = EEPROM_Read + 0x30;
1272 for (i = 0; i < 0x40; i++) {
1274 window_write16(vp, base + i, 0, Wn0EepromCmd);
1275 /* Pause for at least 162 us. for the read to take place. */
1276 for (timer = 10; timer >= 0; timer--) {
1278 if ((window_read16(vp, 0, Wn0EepromCmd) &
1282 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1285 for (i = 0; i < 0x18; i++)
1286 checksum ^= eeprom[i];
1287 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1288 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1290 checksum ^= eeprom[i++];
1291 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1293 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1294 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1295 for (i = 0; i < 3; i++)
1296 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1298 pr_cont(" %pM", dev->dev_addr);
1299 /* Unfortunately an all zero eeprom passes the checksum and this
1300 gets found in the wild in failure cases. Crypto is hard 8) */
1301 if (!is_valid_ether_addr(dev->dev_addr)) {
1303 pr_err("*** EEPROM MAC address is invalid.\n");
1304 goto free_ring; /* With every pack */
1306 for (i = 0; i < 6; i++)
1307 window_write8(vp, dev->dev_addr[i], 2, i);
1310 pr_cont(", IRQ %d\n", dev->irq);
1311 /* Tell them about an invalid IRQ. */
1312 if (dev->irq <= 0 || dev->irq >= nr_irqs)
1313 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1316 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1318 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1319 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1320 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1324 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1327 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1328 if (!vp->cb_fn_base) {
1334 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1336 (unsigned long long)pci_resource_start(pdev, 2),
1340 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1341 if (vp->drv_flags & INVERT_LED_PWR)
1343 if (vp->drv_flags & INVERT_MII_PWR)
1345 window_write16(vp, n, 2, Wn2_ResetOptions);
1346 if (vp->drv_flags & WNO_XCVR_PWR) {
1347 window_write16(vp, 0x0800, 0, 0);
1351 /* Extract our information from the EEPROM data. */
1352 vp->info1 = eeprom[13];
1353 vp->info2 = eeprom[15];
1354 vp->capabilities = eeprom[16];
1356 if (vp->info1 & 0x8000) {
1357 vp->full_duplex = 1;
1359 pr_info("Full duplex capable\n");
1363 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1364 unsigned int config;
1365 vp->available_media = window_read16(vp, 3, Wn3_Options);
1366 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1367 vp->available_media = 0x40;
1368 config = window_read32(vp, 3, Wn3_Config);
1370 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1371 config, window_read16(vp, 3, Wn3_Options));
1372 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1373 8 << RAM_SIZE(config),
1374 RAM_WIDTH(config) ? "word" : "byte",
1375 ram_split[RAM_SPLIT(config)],
1376 AUTOSELECT(config) ? "autoselect/" : "",
1377 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1378 media_tbl[XCVR(config)].name);
1380 vp->default_media = XCVR(config);
1381 if (vp->default_media == XCVR_NWAY)
1383 vp->autoselect = AUTOSELECT(config);
1386 if (vp->media_override != 7) {
1387 pr_info("%s: Media override to transceiver type %d (%s).\n",
1388 print_name, vp->media_override,
1389 media_tbl[vp->media_override].name);
1390 dev->if_port = vp->media_override;
1392 dev->if_port = vp->default_media;
1394 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1395 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1396 int phy, phy_idx = 0;
1397 mii_preamble_required++;
1398 if (vp->drv_flags & EXTRA_PREAMBLE)
1399 mii_preamble_required++;
1401 mdio_read(dev, 24, MII_BMSR);
1402 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1403 int mii_status, phyx;
1406 * For the 3c905CX we look at index 24 first, because it bogusly
1407 * reports an external PHY at all indices
1415 mii_status = mdio_read(dev, phyx, MII_BMSR);
1416 if (mii_status && mii_status != 0xffff) {
1417 vp->phys[phy_idx++] = phyx;
1419 pr_info(" MII transceiver found at address %d, status %4x.\n",
1422 if ((mii_status & 0x0040) == 0)
1423 mii_preamble_required++;
1426 mii_preamble_required--;
1428 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1431 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1432 if (vp->full_duplex) {
1433 /* Only advertise the FD media types. */
1434 vp->advertising &= ~0x02A0;
1435 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1438 vp->mii.phy_id = vp->phys[0];
1441 if (vp->capabilities & CapBusMaster) {
1442 vp->full_bus_master_tx = 1;
1444 pr_info(" Enabling bus-master transmits and %s receives.\n",
1445 (vp->info2 & 1) ? "early" : "whole-frame" );
1447 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1448 vp->bus_master = 0; /* AKPM: vortex only */
1451 /* The 3c59x-specific entries in the device structure. */
1452 if (vp->full_bus_master_tx) {
1453 dev->netdev_ops = &boomrang_netdev_ops;
1454 /* Actually, it still should work with iommu. */
1455 if (card_idx < MAX_UNITS &&
1456 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1457 hw_checksums[card_idx] == 1)) {
1458 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1461 dev->netdev_ops = &vortex_netdev_ops;
1464 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1466 (dev->features & NETIF_F_SG) ? "en":"dis",
1467 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1470 dev->ethtool_ops = &vortex_ethtool_ops;
1471 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1474 vp->pm_state_valid = 1;
1475 pci_save_state(pdev);
1478 retval = register_netdev(dev);
1483 pci_free_consistent(pdev,
1484 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1485 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1490 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1496 issue_and_wait(struct net_device *dev, int cmd)
1498 struct vortex_private *vp = netdev_priv(dev);
1499 void __iomem *ioaddr = vp->ioaddr;
1502 iowrite16(cmd, ioaddr + EL3_CMD);
1503 for (i = 0; i < 2000; i++) {
1504 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1508 /* OK, that didn't work. Do it the slow way. One second */
1509 for (i = 0; i < 100000; i++) {
1510 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1511 if (vortex_debug > 1)
1512 pr_info("%s: command 0x%04x took %d usecs\n",
1513 dev->name, cmd, i * 10);
1518 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1519 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1523 vortex_set_duplex(struct net_device *dev)
1525 struct vortex_private *vp = netdev_priv(dev);
1527 pr_info("%s: setting %s-duplex.\n",
1528 dev->name, (vp->full_duplex) ? "full" : "half");
1530 /* Set the full-duplex bit. */
1532 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1533 (vp->large_frames ? 0x40 : 0) |
1534 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1539 static void vortex_check_media(struct net_device *dev, unsigned int init)
1541 struct vortex_private *vp = netdev_priv(dev);
1542 unsigned int ok_to_print = 0;
1544 if (vortex_debug > 3)
1547 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1548 vp->full_duplex = vp->mii.full_duplex;
1549 vortex_set_duplex(dev);
1551 vortex_set_duplex(dev);
1556 vortex_up(struct net_device *dev)
1558 struct vortex_private *vp = netdev_priv(dev);
1559 void __iomem *ioaddr = vp->ioaddr;
1560 unsigned int config;
1561 int i, mii_reg1, mii_reg5, err = 0;
1563 if (VORTEX_PCI(vp)) {
1564 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1565 if (vp->pm_state_valid)
1566 pci_restore_state(VORTEX_PCI(vp));
1567 err = pci_enable_device(VORTEX_PCI(vp));
1569 pr_warning("%s: Could not enable device\n",
1575 /* Before initializing select the active media port. */
1576 config = window_read32(vp, 3, Wn3_Config);
1578 if (vp->media_override != 7) {
1579 pr_info("%s: Media override to transceiver %d (%s).\n",
1580 dev->name, vp->media_override,
1581 media_tbl[vp->media_override].name);
1582 dev->if_port = vp->media_override;
1583 } else if (vp->autoselect) {
1585 if (vortex_debug > 1)
1586 pr_info("%s: using NWAY device table, not %d\n",
1587 dev->name, dev->if_port);
1588 dev->if_port = XCVR_NWAY;
1590 /* Find first available media type, starting with 100baseTx. */
1591 dev->if_port = XCVR_100baseTx;
1592 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1593 dev->if_port = media_tbl[dev->if_port].next;
1594 if (vortex_debug > 1)
1595 pr_info("%s: first available media type: %s\n",
1596 dev->name, media_tbl[dev->if_port].name);
1599 dev->if_port = vp->default_media;
1600 if (vortex_debug > 1)
1601 pr_info("%s: using default media %s\n",
1602 dev->name, media_tbl[dev->if_port].name);
1605 init_timer(&vp->timer);
1606 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1607 vp->timer.data = (unsigned long)dev;
1608 vp->timer.function = vortex_timer; /* timer handler */
1609 add_timer(&vp->timer);
1611 init_timer(&vp->rx_oom_timer);
1612 vp->rx_oom_timer.data = (unsigned long)dev;
1613 vp->rx_oom_timer.function = rx_oom_timer;
1615 if (vortex_debug > 1)
1616 pr_debug("%s: Initial media type %s.\n",
1617 dev->name, media_tbl[dev->if_port].name);
1619 vp->full_duplex = vp->mii.force_media;
1620 config = BFINS(config, dev->if_port, 20, 4);
1621 if (vortex_debug > 6)
1622 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1623 window_write32(vp, config, 3, Wn3_Config);
1625 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1626 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1627 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1628 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1629 vp->mii.full_duplex = vp->full_duplex;
1631 vortex_check_media(dev, 1);
1634 vortex_set_duplex(dev);
1636 issue_and_wait(dev, TxReset);
1638 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1640 issue_and_wait(dev, RxReset|0x04);
1643 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1645 if (vortex_debug > 1) {
1646 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1647 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1650 /* Set the station address and mask in window 2 each time opened. */
1651 for (i = 0; i < 6; i++)
1652 window_write8(vp, dev->dev_addr[i], 2, i);
1653 for (; i < 12; i+=2)
1654 window_write16(vp, 0, 2, i);
1656 if (vp->cb_fn_base) {
1657 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1658 if (vp->drv_flags & INVERT_LED_PWR)
1660 if (vp->drv_flags & INVERT_MII_PWR)
1662 window_write16(vp, n, 2, Wn2_ResetOptions);
1665 if (dev->if_port == XCVR_10base2)
1666 /* Start the thinnet transceiver. We should really wait 50ms...*/
1667 iowrite16(StartCoax, ioaddr + EL3_CMD);
1668 if (dev->if_port != XCVR_NWAY) {
1670 (window_read16(vp, 4, Wn4_Media) &
1671 ~(Media_10TP|Media_SQE)) |
1672 media_tbl[dev->if_port].media_bits,
1676 /* Switch to the stats window, and clear all stats by reading. */
1677 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1678 for (i = 0; i < 10; i++)
1679 window_read8(vp, 6, i);
1680 window_read16(vp, 6, 10);
1681 window_read16(vp, 6, 12);
1682 /* New: On the Vortex we must also clear the BadSSD counter. */
1683 window_read8(vp, 4, 12);
1684 /* ..and on the Boomerang we enable the extra statistics bits. */
1685 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1687 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1688 vp->cur_rx = vp->dirty_rx = 0;
1689 /* Initialize the RxEarly register as recommended. */
1690 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1691 iowrite32(0x0020, ioaddr + PktStatus);
1692 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1694 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1695 vp->cur_tx = vp->dirty_tx = 0;
1696 if (vp->drv_flags & IS_BOOMERANG)
1697 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1698 /* Clear the Rx, Tx rings. */
1699 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1700 vp->rx_ring[i].status = 0;
1701 for (i = 0; i < TX_RING_SIZE; i++)
1702 vp->tx_skbuff[i] = NULL;
1703 iowrite32(0, ioaddr + DownListPtr);
1705 /* Set receiver mode: presumably accept b-case and phys addr only. */
1707 /* enable 802.1q tagged frames */
1708 set_8021q_mode(dev, 1);
1709 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1711 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1712 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1713 /* Allow status bits to be seen. */
1714 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1715 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1716 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1717 (vp->bus_master ? DMADone : 0);
1718 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1719 (vp->full_bus_master_rx ? 0 : RxComplete) |
1720 StatsFull | HostError | TxComplete | IntReq
1721 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1722 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1723 /* Ack all pending events, and set active indicator mask. */
1724 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1726 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1727 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1728 iowrite32(0x8000, vp->cb_fn_base + 4);
1729 netif_start_queue (dev);
1735 vortex_open(struct net_device *dev)
1737 struct vortex_private *vp = netdev_priv(dev);
1741 /* Use the now-standard shared IRQ implementation. */
1742 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1743 boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1744 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1748 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1749 if (vortex_debug > 2)
1750 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1751 for (i = 0; i < RX_RING_SIZE; i++) {
1752 struct sk_buff *skb;
1753 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1754 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1755 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1757 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1759 vp->rx_skbuff[i] = skb;
1761 break; /* Bad news! */
1763 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1764 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1766 if (i != RX_RING_SIZE) {
1768 pr_emerg("%s: no memory for rx ring\n", dev->name);
1769 for (j = 0; j < i; j++) {
1770 if (vp->rx_skbuff[j]) {
1771 dev_kfree_skb(vp->rx_skbuff[j]);
1772 vp->rx_skbuff[j] = NULL;
1778 /* Wrap the ring. */
1779 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1782 retval = vortex_up(dev);
1787 free_irq(dev->irq, dev);
1789 if (vortex_debug > 1)
1790 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1796 vortex_timer(unsigned long data)
1798 struct net_device *dev = (struct net_device *)data;
1799 struct vortex_private *vp = netdev_priv(dev);
1800 void __iomem *ioaddr = vp->ioaddr;
1801 int next_tick = 60*HZ;
1805 if (vortex_debug > 2) {
1806 pr_debug("%s: Media selection timer tick happened, %s.\n",
1807 dev->name, media_tbl[dev->if_port].name);
1808 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1811 media_status = window_read16(vp, 4, Wn4_Media);
1812 switch (dev->if_port) {
1813 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1814 if (media_status & Media_LnkBeat) {
1815 netif_carrier_on(dev);
1817 if (vortex_debug > 1)
1818 pr_debug("%s: Media %s has link beat, %x.\n",
1819 dev->name, media_tbl[dev->if_port].name, media_status);
1821 netif_carrier_off(dev);
1822 if (vortex_debug > 1) {
1823 pr_debug("%s: Media %s has no link beat, %x.\n",
1824 dev->name, media_tbl[dev->if_port].name, media_status);
1828 case XCVR_MII: case XCVR_NWAY:
1831 vortex_check_media(dev, 0);
1834 default: /* Other media types handled by Tx timeouts. */
1835 if (vortex_debug > 1)
1836 pr_debug("%s: Media %s has no indication, %x.\n",
1837 dev->name, media_tbl[dev->if_port].name, media_status);
1841 if (dev->flags & IFF_SLAVE || !netif_carrier_ok(dev))
1845 goto leave_media_alone;
1848 unsigned int config;
1850 spin_lock_irq(&vp->lock);
1853 dev->if_port = media_tbl[dev->if_port].next;
1854 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1855 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1856 dev->if_port = vp->default_media;
1857 if (vortex_debug > 1)
1858 pr_debug("%s: Media selection failing, using default %s port.\n",
1859 dev->name, media_tbl[dev->if_port].name);
1861 if (vortex_debug > 1)
1862 pr_debug("%s: Media selection failed, now trying %s port.\n",
1863 dev->name, media_tbl[dev->if_port].name);
1864 next_tick = media_tbl[dev->if_port].wait;
1867 (media_status & ~(Media_10TP|Media_SQE)) |
1868 media_tbl[dev->if_port].media_bits,
1871 config = window_read32(vp, 3, Wn3_Config);
1872 config = BFINS(config, dev->if_port, 20, 4);
1873 window_write32(vp, config, 3, Wn3_Config);
1875 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1877 if (vortex_debug > 1)
1878 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1879 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1881 spin_unlock_irq(&vp->lock);
1885 if (vortex_debug > 2)
1886 pr_debug("%s: Media selection timer finished, %s.\n",
1887 dev->name, media_tbl[dev->if_port].name);
1889 mod_timer(&vp->timer, RUN_AT(next_tick));
1891 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1894 static void vortex_tx_timeout(struct net_device *dev)
1896 struct vortex_private *vp = netdev_priv(dev);
1897 void __iomem *ioaddr = vp->ioaddr;
1899 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1900 dev->name, ioread8(ioaddr + TxStatus),
1901 ioread16(ioaddr + EL3_STATUS));
1902 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1903 window_read16(vp, 4, Wn4_NetDiag),
1904 window_read16(vp, 4, Wn4_Media),
1905 ioread32(ioaddr + PktStatus),
1906 window_read16(vp, 4, Wn4_FIFODiag));
1907 /* Slight code bloat to be user friendly. */
1908 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1909 pr_err("%s: Transmitter encountered 16 collisions --"
1910 " network cable problem?\n", dev->name);
1911 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1912 pr_err("%s: Interrupt posted but not delivered --"
1913 " IRQ blocked by another device?\n", dev->name);
1914 /* Bad idea here.. but we might as well handle a few events. */
1917 * Block interrupts because vortex_interrupt does a bare spin_lock()
1919 unsigned long flags;
1920 local_irq_save(flags);
1921 if (vp->full_bus_master_tx)
1922 boomerang_interrupt(dev->irq, dev);
1924 vortex_interrupt(dev->irq, dev);
1925 local_irq_restore(flags);
1929 if (vortex_debug > 0)
1932 issue_and_wait(dev, TxReset);
1934 dev->stats.tx_errors++;
1935 if (vp->full_bus_master_tx) {
1936 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1937 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1938 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1939 ioaddr + DownListPtr);
1940 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1941 netif_wake_queue (dev);
1942 if (vp->drv_flags & IS_BOOMERANG)
1943 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1944 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1946 dev->stats.tx_dropped++;
1947 netif_wake_queue(dev);
1950 /* Issue Tx Enable */
1951 iowrite16(TxEnable, ioaddr + EL3_CMD);
1952 dev->trans_start = jiffies; /* prevent tx timeout */
1956 * Handle uncommon interrupt sources. This is a separate routine to minimize
1960 vortex_error(struct net_device *dev, int status)
1962 struct vortex_private *vp = netdev_priv(dev);
1963 void __iomem *ioaddr = vp->ioaddr;
1964 int do_tx_reset = 0, reset_mask = 0;
1965 unsigned char tx_status = 0;
1967 if (vortex_debug > 2) {
1968 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1971 if (status & TxComplete) { /* Really "TxError" for us. */
1972 tx_status = ioread8(ioaddr + TxStatus);
1973 /* Presumably a tx-timeout. We must merely re-enable. */
1974 if (vortex_debug > 2 ||
1975 (tx_status != 0x88 && vortex_debug > 0)) {
1976 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1977 dev->name, tx_status);
1978 if (tx_status == 0x82) {
1979 pr_err("Probably a duplex mismatch. See "
1980 "Documentation/networking/vortex.txt\n");
1984 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1985 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1986 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1987 iowrite8(0, ioaddr + TxStatus);
1988 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1990 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1992 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1993 } else { /* Merely re-enable the transmitter. */
1994 iowrite16(TxEnable, ioaddr + EL3_CMD);
1998 if (status & RxEarly) /* Rx early is unused. */
1999 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
2001 if (status & StatsFull) { /* Empty statistics. */
2002 static int DoneDidThat;
2003 if (vortex_debug > 4)
2004 pr_debug("%s: Updating stats.\n", dev->name);
2005 update_stats(ioaddr, dev);
2006 /* HACK: Disable statistics as an interrupt source. */
2007 /* This occurs when we have the wrong media type! */
2008 if (DoneDidThat == 0 &&
2009 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
2010 pr_warning("%s: Updating statistics failed, disabling "
2011 "stats as an interrupt source.\n", dev->name);
2012 iowrite16(SetIntrEnb |
2013 (window_read16(vp, 5, 10) & ~StatsFull),
2015 vp->intr_enable &= ~StatsFull;
2019 if (status & IntReq) { /* Restore all interrupt sources. */
2020 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2021 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2023 if (status & HostError) {
2025 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2026 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2027 dev->name, fifo_diag);
2028 /* Adapter failure requires Tx/Rx reset and reinit. */
2029 if (vp->full_bus_master_tx) {
2030 int bus_status = ioread32(ioaddr + PktStatus);
2031 /* 0x80000000 PCI master abort. */
2032 /* 0x40000000 PCI target abort. */
2034 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2036 /* In this case, blow the card away */
2037 /* Must not enter D3 or we can't legally issue the reset! */
2038 vortex_down(dev, 0);
2039 issue_and_wait(dev, TotalReset | 0xff);
2040 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2041 } else if (fifo_diag & 0x0400)
2043 if (fifo_diag & 0x3000) {
2044 /* Reset Rx fifo and upload logic */
2045 issue_and_wait(dev, RxReset|0x07);
2046 /* Set the Rx filter to the current state. */
2048 /* enable 802.1q VLAN tagged frames */
2049 set_8021q_mode(dev, 1);
2050 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2051 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2056 issue_and_wait(dev, TxReset|reset_mask);
2057 iowrite16(TxEnable, ioaddr + EL3_CMD);
2058 if (!vp->full_bus_master_tx)
2059 netif_wake_queue(dev);
2064 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2066 struct vortex_private *vp = netdev_priv(dev);
2067 void __iomem *ioaddr = vp->ioaddr;
2069 /* Put out the doubleword header... */
2070 iowrite32(skb->len, ioaddr + TX_FIFO);
2071 if (vp->bus_master) {
2072 /* Set the bus-master controller to transfer the packet. */
2073 int len = (skb->len + 3) & ~3;
2074 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2076 spin_lock_irq(&vp->window_lock);
2078 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2079 iowrite16(len, ioaddr + Wn7_MasterLen);
2080 spin_unlock_irq(&vp->window_lock);
2082 skb_tx_timestamp(skb);
2083 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2084 /* netif_wake_queue() will be called at the DMADone interrupt. */
2086 /* ... and the packet rounded to a doubleword. */
2087 skb_tx_timestamp(skb);
2088 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2089 dev_consume_skb_any (skb);
2090 if (ioread16(ioaddr + TxFree) > 1536) {
2091 netif_start_queue (dev); /* AKPM: redundant? */
2093 /* Interrupt us when the FIFO has room for max-sized packet. */
2094 netif_stop_queue(dev);
2095 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2100 /* Clear the Tx status stack. */
2105 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2106 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2107 if (vortex_debug > 2)
2108 pr_debug("%s: Tx error, status %2.2x.\n",
2109 dev->name, tx_status);
2110 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2111 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2112 if (tx_status & 0x30) {
2113 issue_and_wait(dev, TxReset);
2115 iowrite16(TxEnable, ioaddr + EL3_CMD);
2117 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2120 return NETDEV_TX_OK;
2124 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2126 struct vortex_private *vp = netdev_priv(dev);
2127 void __iomem *ioaddr = vp->ioaddr;
2128 /* Calculate the next Tx descriptor entry. */
2129 int entry = vp->cur_tx % TX_RING_SIZE;
2130 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2131 unsigned long flags;
2132 dma_addr_t dma_addr;
2134 if (vortex_debug > 6) {
2135 pr_debug("boomerang_start_xmit()\n");
2136 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2137 dev->name, vp->cur_tx);
2141 * We can't allow a recursion from our interrupt handler back into the
2142 * tx routine, as they take the same spin lock, and that causes
2143 * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
2146 if (vp->handling_irq)
2147 return NETDEV_TX_BUSY;
2149 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2150 if (vortex_debug > 0)
2151 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
2153 netif_stop_queue(dev);
2154 return NETDEV_TX_BUSY;
2157 vp->tx_skbuff[entry] = skb;
2159 vp->tx_ring[entry].next = 0;
2161 if (skb->ip_summed != CHECKSUM_PARTIAL)
2162 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2164 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2166 if (!skb_shinfo(skb)->nr_frags) {
2167 dma_addr = pci_map_single(VORTEX_PCI(vp), skb->data, skb->len,
2169 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr))
2172 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2173 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2177 dma_addr = pci_map_single(VORTEX_PCI(vp), skb->data,
2178 skb_headlen(skb), PCI_DMA_TODEVICE);
2179 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr))
2182 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2183 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2185 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2186 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2188 dma_addr = skb_frag_dma_map(&VORTEX_PCI(vp)->dev, frag,
2192 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr)) {
2193 for(i = i-1; i >= 0; i--)
2194 dma_unmap_page(&VORTEX_PCI(vp)->dev,
2195 le32_to_cpu(vp->tx_ring[entry].frag[i+1].addr),
2196 le32_to_cpu(vp->tx_ring[entry].frag[i+1].length),
2199 pci_unmap_single(VORTEX_PCI(vp),
2200 le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
2201 le32_to_cpu(vp->tx_ring[entry].frag[0].length),
2207 vp->tx_ring[entry].frag[i+1].addr =
2208 cpu_to_le32(dma_addr);
2210 if (i == skb_shinfo(skb)->nr_frags-1)
2211 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG);
2213 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag));
2217 dma_addr = pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE);
2218 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr))
2220 vp->tx_ring[entry].addr = cpu_to_le32(dma_addr);
2221 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2222 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2225 spin_lock_irqsave(&vp->lock, flags);
2226 /* Wait for the stall to complete. */
2227 issue_and_wait(dev, DownStall);
2228 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2229 if (ioread32(ioaddr + DownListPtr) == 0) {
2230 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2231 vp->queued_packet++;
2235 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2236 netif_stop_queue (dev);
2237 } else { /* Clear previous interrupt enable. */
2238 #if defined(tx_interrupt_mitigation)
2239 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2240 * were selected, this would corrupt DN_COMPLETE. No?
2242 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2245 skb_tx_timestamp(skb);
2246 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2247 spin_unlock_irqrestore(&vp->lock, flags);
2249 return NETDEV_TX_OK;
2251 dev_err(&VORTEX_PCI(vp)->dev, "Error mapping dma buffer\n");
2255 /* The interrupt handler does all of the Rx thread work and cleans up
2256 after the Tx thread. */
2259 * This is the ISR for the vortex series chips.
2260 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2264 vortex_interrupt(int irq, void *dev_id)
2266 struct net_device *dev = dev_id;
2267 struct vortex_private *vp = netdev_priv(dev);
2268 void __iomem *ioaddr;
2270 int work_done = max_interrupt_work;
2273 ioaddr = vp->ioaddr;
2274 spin_lock(&vp->lock);
2276 status = ioread16(ioaddr + EL3_STATUS);
2278 if (vortex_debug > 6)
2279 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2281 if ((status & IntLatch) == 0)
2282 goto handler_exit; /* No interrupt: shared IRQs cause this */
2285 if (status & IntReq) {
2286 status |= vp->deferred;
2290 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2293 if (vortex_debug > 4)
2294 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2295 dev->name, status, ioread8(ioaddr + Timer));
2297 spin_lock(&vp->window_lock);
2301 if (vortex_debug > 5)
2302 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2304 if (status & RxComplete)
2307 if (status & TxAvailable) {
2308 if (vortex_debug > 5)
2309 pr_debug(" TX room bit was handled.\n");
2310 /* There's room in the FIFO for a full-sized packet. */
2311 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2312 netif_wake_queue (dev);
2315 if (status & DMADone) {
2316 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2317 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2318 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2319 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2320 if (ioread16(ioaddr + TxFree) > 1536) {
2322 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2323 * insufficient FIFO room, the TxAvailable test will succeed and call
2324 * netif_wake_queue()
2326 netif_wake_queue(dev);
2327 } else { /* Interrupt when FIFO has room for max-sized packet. */
2328 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2329 netif_stop_queue(dev);
2333 /* Check for all uncommon interrupts at once. */
2334 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2335 if (status == 0xffff)
2337 if (status & RxEarly)
2339 spin_unlock(&vp->window_lock);
2340 vortex_error(dev, status);
2341 spin_lock(&vp->window_lock);
2345 if (--work_done < 0) {
2346 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2348 /* Disable all pending interrupts. */
2350 vp->deferred |= status;
2351 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2353 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2354 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2355 /* The timer will reenable interrupts. */
2356 mod_timer(&vp->timer, jiffies + 1*HZ);
2359 /* Acknowledge the IRQ. */
2360 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2361 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2363 spin_unlock(&vp->window_lock);
2365 if (vortex_debug > 4)
2366 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2369 spin_unlock(&vp->lock);
2370 return IRQ_RETVAL(handled);
2374 * This is the ISR for the boomerang series chips.
2375 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2379 boomerang_interrupt(int irq, void *dev_id)
2381 struct net_device *dev = dev_id;
2382 struct vortex_private *vp = netdev_priv(dev);
2383 void __iomem *ioaddr;
2385 int work_done = max_interrupt_work;
2387 ioaddr = vp->ioaddr;
2391 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2392 * and boomerang_start_xmit
2394 spin_lock(&vp->lock);
2395 vp->handling_irq = 1;
2397 status = ioread16(ioaddr + EL3_STATUS);
2399 if (vortex_debug > 6)
2400 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2402 if ((status & IntLatch) == 0)
2403 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2405 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2406 if (vortex_debug > 1)
2407 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2411 if (status & IntReq) {
2412 status |= vp->deferred;
2416 if (vortex_debug > 4)
2417 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2418 dev->name, status, ioread8(ioaddr + Timer));
2420 if (vortex_debug > 5)
2421 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2423 if (status & UpComplete) {
2424 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2425 if (vortex_debug > 5)
2426 pr_debug("boomerang_interrupt->boomerang_rx\n");
2430 if (status & DownComplete) {
2431 unsigned int dirty_tx = vp->dirty_tx;
2433 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2434 while (vp->cur_tx - dirty_tx > 0) {
2435 int entry = dirty_tx % TX_RING_SIZE;
2436 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2437 if (ioread32(ioaddr + DownListPtr) ==
2438 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2439 break; /* It still hasn't been processed. */
2441 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2442 break; /* It still hasn't been processed. */
2445 if (vp->tx_skbuff[entry]) {
2446 struct sk_buff *skb = vp->tx_skbuff[entry];
2449 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2450 pci_unmap_single(VORTEX_PCI(vp),
2451 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2452 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2455 pci_unmap_single(VORTEX_PCI(vp),
2456 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2458 dev_kfree_skb_irq(skb);
2459 vp->tx_skbuff[entry] = NULL;
2461 pr_debug("boomerang_interrupt: no skb!\n");
2463 /* dev->stats.tx_packets++; Counted below. */
2466 vp->dirty_tx = dirty_tx;
2467 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2468 if (vortex_debug > 6)
2469 pr_debug("boomerang_interrupt: wake queue\n");
2470 netif_wake_queue (dev);
2474 /* Check for all uncommon interrupts at once. */
2475 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2476 vortex_error(dev, status);
2478 if (--work_done < 0) {
2479 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2481 /* Disable all pending interrupts. */
2483 vp->deferred |= status;
2484 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2486 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2487 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2488 /* The timer will reenable interrupts. */
2489 mod_timer(&vp->timer, jiffies + 1*HZ);
2492 /* Acknowledge the IRQ. */
2493 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2494 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2495 iowrite32(0x8000, vp->cb_fn_base + 4);
2497 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2499 if (vortex_debug > 4)
2500 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2503 vp->handling_irq = 0;
2504 spin_unlock(&vp->lock);
2508 static int vortex_rx(struct net_device *dev)
2510 struct vortex_private *vp = netdev_priv(dev);
2511 void __iomem *ioaddr = vp->ioaddr;
2515 if (vortex_debug > 5)
2516 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2517 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2518 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2519 if (rx_status & 0x4000) { /* Error, update stats. */
2520 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2521 if (vortex_debug > 2)
2522 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2523 dev->stats.rx_errors++;
2524 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2525 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2526 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2527 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2528 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2530 /* The packet length: up to 4.5K!. */
2531 int pkt_len = rx_status & 0x1fff;
2532 struct sk_buff *skb;
2534 skb = netdev_alloc_skb(dev, pkt_len + 5);
2535 if (vortex_debug > 4)
2536 pr_debug("Receiving packet size %d status %4.4x.\n",
2537 pkt_len, rx_status);
2539 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2540 /* 'skb_put()' points to the start of sk_buff data area. */
2541 if (vp->bus_master &&
2542 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2543 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2544 pkt_len, PCI_DMA_FROMDEVICE);
2545 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2546 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2547 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2548 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2550 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2552 ioread32_rep(ioaddr + RX_FIFO,
2553 skb_put(skb, pkt_len),
2554 (pkt_len + 3) >> 2);
2556 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2557 skb->protocol = eth_type_trans(skb, dev);
2559 dev->stats.rx_packets++;
2560 /* Wait a limited time to go to next packet. */
2561 for (i = 200; i >= 0; i--)
2562 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2565 } else if (vortex_debug > 0)
2566 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2567 dev->name, pkt_len);
2568 dev->stats.rx_dropped++;
2570 issue_and_wait(dev, RxDiscard);
2577 boomerang_rx(struct net_device *dev)
2579 struct vortex_private *vp = netdev_priv(dev);
2580 int entry = vp->cur_rx % RX_RING_SIZE;
2581 void __iomem *ioaddr = vp->ioaddr;
2583 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2585 if (vortex_debug > 5)
2586 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2588 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2589 if (--rx_work_limit < 0)
2591 if (rx_status & RxDError) { /* Error, update stats. */
2592 unsigned char rx_error = rx_status >> 16;
2593 if (vortex_debug > 2)
2594 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2595 dev->stats.rx_errors++;
2596 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2597 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2598 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2599 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2600 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2602 /* The packet length: up to 4.5K!. */
2603 int pkt_len = rx_status & 0x1fff;
2604 struct sk_buff *skb;
2605 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2607 if (vortex_debug > 4)
2608 pr_debug("Receiving packet size %d status %4.4x.\n",
2609 pkt_len, rx_status);
2611 /* Check if the packet is long enough to just accept without
2612 copying to a properly sized skbuff. */
2613 if (pkt_len < rx_copybreak &&
2614 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
2615 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2616 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2617 /* 'skb_put()' points to the start of sk_buff data area. */
2618 memcpy(skb_put(skb, pkt_len),
2619 vp->rx_skbuff[entry]->data,
2621 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2624 /* Pass up the skbuff already on the Rx ring. */
2625 skb = vp->rx_skbuff[entry];
2626 vp->rx_skbuff[entry] = NULL;
2627 skb_put(skb, pkt_len);
2628 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2631 skb->protocol = eth_type_trans(skb, dev);
2632 { /* Use hardware checksum info. */
2633 int csum_bits = rx_status & 0xee000000;
2635 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2636 csum_bits == (IPChksumValid | UDPChksumValid))) {
2637 skb->ip_summed = CHECKSUM_UNNECESSARY;
2642 dev->stats.rx_packets++;
2644 entry = (++vp->cur_rx) % RX_RING_SIZE;
2646 /* Refill the Rx ring buffers. */
2647 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2648 struct sk_buff *skb;
2649 entry = vp->dirty_rx % RX_RING_SIZE;
2650 if (vp->rx_skbuff[entry] == NULL) {
2651 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2653 static unsigned long last_jif;
2654 if (time_after(jiffies, last_jif + 10 * HZ)) {
2655 pr_warning("%s: memory shortage\n", dev->name);
2658 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2659 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2660 break; /* Bad news! */
2663 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2664 vp->rx_skbuff[entry] = skb;
2666 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2667 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2673 * If we've hit a total OOM refilling the Rx ring we poll once a second
2674 * for some memory. Otherwise there is no way to restart the rx process.
2677 rx_oom_timer(unsigned long arg)
2679 struct net_device *dev = (struct net_device *)arg;
2680 struct vortex_private *vp = netdev_priv(dev);
2682 spin_lock_irq(&vp->lock);
2683 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2685 if (vortex_debug > 1) {
2686 pr_debug("%s: rx_oom_timer %s\n", dev->name,
2687 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2689 spin_unlock_irq(&vp->lock);
2693 vortex_down(struct net_device *dev, int final_down)
2695 struct vortex_private *vp = netdev_priv(dev);
2696 void __iomem *ioaddr = vp->ioaddr;
2698 netif_stop_queue (dev);
2700 del_timer_sync(&vp->rx_oom_timer);
2701 del_timer_sync(&vp->timer);
2703 /* Turn off statistics ASAP. We update dev->stats below. */
2704 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2706 /* Disable the receiver and transmitter. */
2707 iowrite16(RxDisable, ioaddr + EL3_CMD);
2708 iowrite16(TxDisable, ioaddr + EL3_CMD);
2710 /* Disable receiving 802.1q tagged frames */
2711 set_8021q_mode(dev, 0);
2713 if (dev->if_port == XCVR_10base2)
2714 /* Turn off thinnet power. Green! */
2715 iowrite16(StopCoax, ioaddr + EL3_CMD);
2717 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2719 update_stats(ioaddr, dev);
2720 if (vp->full_bus_master_rx)
2721 iowrite32(0, ioaddr + UpListPtr);
2722 if (vp->full_bus_master_tx)
2723 iowrite32(0, ioaddr + DownListPtr);
2725 if (final_down && VORTEX_PCI(vp)) {
2726 vp->pm_state_valid = 1;
2727 pci_save_state(VORTEX_PCI(vp));
2733 vortex_close(struct net_device *dev)
2735 struct vortex_private *vp = netdev_priv(dev);
2736 void __iomem *ioaddr = vp->ioaddr;
2739 if (netif_device_present(dev))
2740 vortex_down(dev, 1);
2742 if (vortex_debug > 1) {
2743 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2744 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2745 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2746 " tx_queued %d Rx pre-checksummed %d.\n",
2747 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2751 if (vp->rx_csumhits &&
2752 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2753 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2754 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
2758 free_irq(dev->irq, dev);
2760 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2761 for (i = 0; i < RX_RING_SIZE; i++)
2762 if (vp->rx_skbuff[i]) {
2763 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2764 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2765 dev_kfree_skb(vp->rx_skbuff[i]);
2766 vp->rx_skbuff[i] = NULL;
2769 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2770 for (i = 0; i < TX_RING_SIZE; i++) {
2771 if (vp->tx_skbuff[i]) {
2772 struct sk_buff *skb = vp->tx_skbuff[i];
2776 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2777 pci_unmap_single(VORTEX_PCI(vp),
2778 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2779 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2782 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2785 vp->tx_skbuff[i] = NULL;
2794 dump_tx_ring(struct net_device *dev)
2796 if (vortex_debug > 0) {
2797 struct vortex_private *vp = netdev_priv(dev);
2798 void __iomem *ioaddr = vp->ioaddr;
2800 if (vp->full_bus_master_tx) {
2802 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2804 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2805 vp->full_bus_master_tx,
2806 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2807 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2808 pr_err(" Transmit list %8.8x vs. %p.\n",
2809 ioread32(ioaddr + DownListPtr),
2810 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2811 issue_and_wait(dev, DownStall);
2812 for (i = 0; i < TX_RING_SIZE; i++) {
2813 unsigned int length;
2816 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2818 length = le32_to_cpu(vp->tx_ring[i].length);
2820 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2821 i, &vp->tx_ring[i], length,
2822 le32_to_cpu(vp->tx_ring[i].status));
2825 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2830 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2832 struct vortex_private *vp = netdev_priv(dev);
2833 void __iomem *ioaddr = vp->ioaddr;
2834 unsigned long flags;
2836 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2837 spin_lock_irqsave (&vp->lock, flags);
2838 update_stats(ioaddr, dev);
2839 spin_unlock_irqrestore (&vp->lock, flags);
2844 /* Update statistics.
2845 Unlike with the EL3 we need not worry about interrupts changing
2846 the window setting from underneath us, but we must still guard
2847 against a race condition with a StatsUpdate interrupt updating the
2848 table. This is done by checking that the ASM (!) code generated uses
2849 atomic updates with '+='.
2851 static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2853 struct vortex_private *vp = netdev_priv(dev);
2855 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2856 /* Switch to the stats window, and read everything. */
2857 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2858 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2859 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2860 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2861 dev->stats.tx_packets += window_read8(vp, 6, 6);
2862 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2864 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
2865 /* Don't bother with register 9, an extension of registers 6&7.
2866 If we do use the 6&7 values the atomic update assumption above
2868 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2869 dev->stats.tx_bytes += window_read16(vp, 6, 12);
2870 /* Extra stats for get_ethtool_stats() */
2871 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2872 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2873 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2874 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
2876 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2877 + vp->xstats.tx_single_collisions
2878 + vp->xstats.tx_max_collisions;
2881 u8 up = window_read8(vp, 4, 13);
2882 dev->stats.rx_bytes += (up & 0x0f) << 16;
2883 dev->stats.tx_bytes += (up & 0xf0) << 12;
2887 static int vortex_nway_reset(struct net_device *dev)
2889 struct vortex_private *vp = netdev_priv(dev);
2891 return mii_nway_restart(&vp->mii);
2894 static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2896 struct vortex_private *vp = netdev_priv(dev);
2898 return mii_ethtool_gset(&vp->mii, cmd);
2901 static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2903 struct vortex_private *vp = netdev_priv(dev);
2905 return mii_ethtool_sset(&vp->mii, cmd);
2908 static u32 vortex_get_msglevel(struct net_device *dev)
2910 return vortex_debug;
2913 static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2918 static int vortex_get_sset_count(struct net_device *dev, int sset)
2922 return VORTEX_NUM_STATS;
2928 static void vortex_get_ethtool_stats(struct net_device *dev,
2929 struct ethtool_stats *stats, u64 *data)
2931 struct vortex_private *vp = netdev_priv(dev);
2932 void __iomem *ioaddr = vp->ioaddr;
2933 unsigned long flags;
2935 spin_lock_irqsave(&vp->lock, flags);
2936 update_stats(ioaddr, dev);
2937 spin_unlock_irqrestore(&vp->lock, flags);
2939 data[0] = vp->xstats.tx_deferred;
2940 data[1] = vp->xstats.tx_max_collisions;
2941 data[2] = vp->xstats.tx_multiple_collisions;
2942 data[3] = vp->xstats.tx_single_collisions;
2943 data[4] = vp->xstats.rx_bad_ssd;
2947 static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2949 switch (stringset) {
2951 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
2959 static void vortex_get_drvinfo(struct net_device *dev,
2960 struct ethtool_drvinfo *info)
2962 struct vortex_private *vp = netdev_priv(dev);
2964 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2965 if (VORTEX_PCI(vp)) {
2966 strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)),
2967 sizeof(info->bus_info));
2969 if (VORTEX_EISA(vp))
2970 strlcpy(info->bus_info, dev_name(vp->gendev),
2971 sizeof(info->bus_info));
2973 snprintf(info->bus_info, sizeof(info->bus_info),
2974 "EISA 0x%lx %d", dev->base_addr, dev->irq);
2978 static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2980 struct vortex_private *vp = netdev_priv(dev);
2982 if (!VORTEX_PCI(vp))
2985 wol->supported = WAKE_MAGIC;
2989 wol->wolopts |= WAKE_MAGIC;
2992 static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2994 struct vortex_private *vp = netdev_priv(dev);
2996 if (!VORTEX_PCI(vp))
2999 if (wol->wolopts & ~WAKE_MAGIC)
3002 if (wol->wolopts & WAKE_MAGIC)
3011 static const struct ethtool_ops vortex_ethtool_ops = {
3012 .get_drvinfo = vortex_get_drvinfo,
3013 .get_strings = vortex_get_strings,
3014 .get_msglevel = vortex_get_msglevel,
3015 .set_msglevel = vortex_set_msglevel,
3016 .get_ethtool_stats = vortex_get_ethtool_stats,
3017 .get_sset_count = vortex_get_sset_count,
3018 .get_settings = vortex_get_settings,
3019 .set_settings = vortex_set_settings,
3020 .get_link = ethtool_op_get_link,
3021 .nway_reset = vortex_nway_reset,
3022 .get_wol = vortex_get_wol,
3023 .set_wol = vortex_set_wol,
3024 .get_ts_info = ethtool_op_get_ts_info,
3029 * Must power the device up to do MDIO operations
3031 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3034 struct vortex_private *vp = netdev_priv(dev);
3035 pci_power_t state = 0;
3038 state = VORTEX_PCI(vp)->current_state;
3040 /* The kernel core really should have pci_get_power_state() */
3043 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3044 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3046 pci_set_power_state(VORTEX_PCI(vp), state);
3053 /* Pre-Cyclone chips have no documented multicast filter, so the only
3054 multicast setting is to receive all multicast frames. At least
3055 the chip has a very clean way to set the mode, unlike many others. */
3056 static void set_rx_mode(struct net_device *dev)
3058 struct vortex_private *vp = netdev_priv(dev);
3059 void __iomem *ioaddr = vp->ioaddr;
3062 if (dev->flags & IFF_PROMISC) {
3063 if (vortex_debug > 3)
3064 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
3065 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3066 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
3067 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3069 new_mode = SetRxFilter | RxStation | RxBroadcast;
3071 iowrite16(new_mode, ioaddr + EL3_CMD);
3074 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3075 /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3076 Note that this must be done after each RxReset due to some backwards
3077 compatibility logic in the Cyclone and Tornado ASICs */
3079 /* The Ethernet Type used for 802.1q tagged frames */
3080 #define VLAN_ETHER_TYPE 0x8100
3082 static void set_8021q_mode(struct net_device *dev, int enable)
3084 struct vortex_private *vp = netdev_priv(dev);
3087 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3088 /* cyclone and tornado chipsets can recognize 802.1q
3089 * tagged frames and treat them correctly */
3091 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3093 max_pkt_size += 4; /* 802.1Q VLAN tag */
3095 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3097 /* set VlanEtherType to let the hardware checksumming
3098 treat tagged frames correctly */
3099 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3101 /* on older cards we have to enable large frames */
3103 vp->large_frames = dev->mtu > 1500 || enable;
3105 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3106 if (vp->large_frames)
3110 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3115 static void set_8021q_mode(struct net_device *dev, int enable)
3122 /* MII transceiver control section.
3123 Read and write the MII registers using software-generated serial
3124 MDIO protocol. See the MII specifications or DP83840A data sheet
3127 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3128 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3129 "overclocking" issues. */
3130 static void mdio_delay(struct vortex_private *vp)
3132 window_read32(vp, 4, Wn4_PhysicalMgmt);
3135 #define MDIO_SHIFT_CLK 0x01
3136 #define MDIO_DIR_WRITE 0x04
3137 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3138 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3139 #define MDIO_DATA_READ 0x02
3140 #define MDIO_ENB_IN 0x00
3142 /* Generate the preamble required for initial synchronization and
3143 a few older transceivers. */
3144 static void mdio_sync(struct vortex_private *vp, int bits)
3146 /* Establish sync by sending at least 32 logic ones. */
3147 while (-- bits >= 0) {
3148 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3150 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3151 4, Wn4_PhysicalMgmt);
3156 static int mdio_read(struct net_device *dev, int phy_id, int location)
3159 struct vortex_private *vp = netdev_priv(dev);
3160 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3161 unsigned int retval = 0;
3163 spin_lock_bh(&vp->mii_lock);
3165 if (mii_preamble_required)
3168 /* Shift the read command bits out. */
3169 for (i = 14; i >= 0; i--) {
3170 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3171 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3173 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3174 4, Wn4_PhysicalMgmt);
3177 /* Read the two transition, 16 data, and wire-idle bits. */
3178 for (i = 19; i > 0; i--) {
3179 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3181 retval = (retval << 1) |
3182 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3183 MDIO_DATA_READ) ? 1 : 0);
3184 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3185 4, Wn4_PhysicalMgmt);
3189 spin_unlock_bh(&vp->mii_lock);
3191 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3194 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3196 struct vortex_private *vp = netdev_priv(dev);
3197 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3200 spin_lock_bh(&vp->mii_lock);
3202 if (mii_preamble_required)
3205 /* Shift the command bits out. */
3206 for (i = 31; i >= 0; i--) {
3207 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3208 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3210 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3211 4, Wn4_PhysicalMgmt);
3214 /* Leave the interface idle. */
3215 for (i = 1; i >= 0; i--) {
3216 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3218 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3219 4, Wn4_PhysicalMgmt);
3223 spin_unlock_bh(&vp->mii_lock);
3226 /* ACPI: Advanced Configuration and Power Interface. */
3227 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3228 static void acpi_set_WOL(struct net_device *dev)
3230 struct vortex_private *vp = netdev_priv(dev);
3231 void __iomem *ioaddr = vp->ioaddr;
3233 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3235 if (vp->enable_wol) {
3236 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3237 window_write16(vp, 2, 7, 0x0c);
3238 /* The RxFilter must accept the WOL frames. */
3239 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3240 iowrite16(RxEnable, ioaddr + EL3_CMD);
3242 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3243 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3249 if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3252 /* Change the power state to D3; RxEnable doesn't take effect. */
3253 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3258 static void vortex_remove_one(struct pci_dev *pdev)
3260 struct net_device *dev = pci_get_drvdata(pdev);
3261 struct vortex_private *vp;
3264 pr_err("vortex_remove_one called for Compaq device!\n");
3268 vp = netdev_priv(dev);
3271 pci_iounmap(pdev, vp->cb_fn_base);
3273 unregister_netdev(dev);
3275 pci_set_power_state(pdev, PCI_D0); /* Go active */
3276 if (vp->pm_state_valid)
3277 pci_restore_state(pdev);
3278 pci_disable_device(pdev);
3280 /* Should really use issue_and_wait() here */
3281 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3282 vp->ioaddr + EL3_CMD);
3284 pci_iounmap(pdev, vp->ioaddr);
3286 pci_free_consistent(pdev,
3287 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3288 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3292 pci_release_regions(pdev);
3298 static struct pci_driver vortex_driver = {
3300 .probe = vortex_init_one,
3301 .remove = vortex_remove_one,
3302 .id_table = vortex_pci_tbl,
3303 .driver.pm = VORTEX_PM_OPS,
3307 static int vortex_have_pci;
3308 static int vortex_have_eisa;
3311 static int __init vortex_init(void)
3313 int pci_rc, eisa_rc;
3315 pci_rc = pci_register_driver(&vortex_driver);
3316 eisa_rc = vortex_eisa_init();
3319 vortex_have_pci = 1;
3321 vortex_have_eisa = 1;
3323 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3327 static void __exit vortex_eisa_cleanup(void)
3329 void __iomem *ioaddr;
3332 /* Take care of the EISA devices */
3333 eisa_driver_unregister(&vortex_eisa_driver);
3336 if (compaq_net_device) {
3337 ioaddr = ioport_map(compaq_net_device->base_addr,
3340 unregister_netdev(compaq_net_device);
3341 iowrite16(TotalReset, ioaddr + EL3_CMD);
3342 release_region(compaq_net_device->base_addr,
3345 free_netdev(compaq_net_device);
3350 static void __exit vortex_cleanup(void)
3352 if (vortex_have_pci)
3353 pci_unregister_driver(&vortex_driver);
3354 if (vortex_have_eisa)
3355 vortex_eisa_cleanup();
3359 module_init(vortex_init);
3360 module_exit(vortex_cleanup);