2 * Blackfin On-Chip MAC Driver
4 * Copyright 2004-2010 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #define DRV_VERSION "1.1"
12 #define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/irq.h>
26 #include <linux/ioport.h>
27 #include <linux/crc32.h>
28 #include <linux/device.h>
29 #include <linux/spinlock.h>
30 #include <linux/mii.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/platform_device.h>
38 #include <linux/dma-mapping.h>
40 #include <asm/div64.h>
42 #include <asm/blackfin.h>
43 #include <asm/cacheflush.h>
44 #include <asm/portmux.h>
49 MODULE_AUTHOR("Bryan Wu, Luke Yang");
50 MODULE_LICENSE("GPL");
51 MODULE_DESCRIPTION(DRV_DESC);
52 MODULE_ALIAS("platform:bfin_mac");
54 #if defined(CONFIG_BFIN_MAC_USE_L1)
55 # define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num)
56 # define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr)
58 # define bfin_mac_alloc(dma_handle, size, num) \
59 dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL)
60 # define bfin_mac_free(dma_handle, ptr, num) \
61 dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle)
64 #define PKT_BUF_SZ 1580
66 #define MAX_TIMEOUT_CNT 500
68 /* pointers to maintain transmit list */
69 static struct net_dma_desc_tx *tx_list_head;
70 static struct net_dma_desc_tx *tx_list_tail;
71 static struct net_dma_desc_rx *rx_list_head;
72 static struct net_dma_desc_rx *rx_list_tail;
73 static struct net_dma_desc_rx *current_rx_ptr;
74 static struct net_dma_desc_tx *current_tx_ptr;
75 static struct net_dma_desc_tx *tx_desc;
76 static struct net_dma_desc_rx *rx_desc;
78 static void desc_list_free(void)
80 struct net_dma_desc_rx *r;
81 struct net_dma_desc_tx *t;
83 #if !defined(CONFIG_BFIN_MAC_USE_L1)
84 dma_addr_t dma_handle = 0;
89 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
92 dev_kfree_skb(t->skb);
98 bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM);
103 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
106 dev_kfree_skb(r->skb);
112 bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM);
116 static int desc_list_init(struct net_device *dev)
119 struct sk_buff *new_skb;
120 #if !defined(CONFIG_BFIN_MAC_USE_L1)
122 * This dma_handle is useless in Blackfin dma_alloc_coherent().
123 * The real dma handler is the return value of dma_alloc_coherent().
125 dma_addr_t dma_handle;
128 tx_desc = bfin_mac_alloc(&dma_handle,
129 sizeof(struct net_dma_desc_tx),
130 CONFIG_BFIN_TX_DESC_NUM);
134 rx_desc = bfin_mac_alloc(&dma_handle,
135 sizeof(struct net_dma_desc_rx),
136 CONFIG_BFIN_RX_DESC_NUM);
141 tx_list_head = tx_list_tail = tx_desc;
143 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
144 struct net_dma_desc_tx *t = tx_desc + i;
145 struct dma_descriptor *a = &(t->desc_a);
146 struct dma_descriptor *b = &(t->desc_b);
150 * read from memory WNR = 0
151 * wordsize is 32 bits
152 * 6 half words is desc size
155 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
156 a->start_addr = (unsigned long)t->packet;
158 a->next_dma_desc = b;
162 * write to memory WNR = 1
163 * wordsize is 32 bits
165 * 6 half words is desc size
168 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
169 b->start_addr = (unsigned long)(&(t->status));
173 tx_list_tail->desc_b.next_dma_desc = a;
174 tx_list_tail->next = t;
177 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
178 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
179 current_tx_ptr = tx_list_head;
182 rx_list_head = rx_list_tail = rx_desc;
184 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
185 struct net_dma_desc_rx *r = rx_desc + i;
186 struct dma_descriptor *a = &(r->desc_a);
187 struct dma_descriptor *b = &(r->desc_b);
189 /* allocate a new skb for next time receive */
190 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
194 skb_reserve(new_skb, NET_IP_ALIGN);
195 /* Invidate the data cache of skb->data range when it is write back
196 * cache. It will prevent overwritting the new data from DMA
198 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
199 (unsigned long)new_skb->end);
204 * write to memory WNR = 1
205 * wordsize is 32 bits
207 * 6 half words is desc size
210 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
211 /* since RXDWA is enabled */
212 a->start_addr = (unsigned long)new_skb->data - 2;
214 a->next_dma_desc = b;
218 * write to memory WNR = 1
219 * wordsize is 32 bits
221 * 6 half words is desc size
224 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
225 NDSIZE_6 | DMAFLOW_LARGE;
226 b->start_addr = (unsigned long)(&(r->status));
229 rx_list_tail->desc_b.next_dma_desc = a;
230 rx_list_tail->next = r;
233 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
234 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
235 current_rx_ptr = rx_list_head;
241 pr_err("kmalloc failed\n");
246 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
251 /* Wait until the previous MDC/MDIO transaction has completed */
252 static int bfin_mdio_poll(void)
254 int timeout_cnt = MAX_TIMEOUT_CNT;
256 /* poll the STABUSY bit */
257 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
259 if (timeout_cnt-- < 0) {
260 pr_err("wait MDC/MDIO transaction to complete timeout\n");
268 /* Read an off-chip register in a PHY through the MDC/MDIO port */
269 static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
273 ret = bfin_mdio_poll();
278 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
279 SET_REGAD((u16) regnum) |
282 ret = bfin_mdio_poll();
286 return (int) bfin_read_EMAC_STADAT();
289 /* Write an off-chip register in a PHY through the MDC/MDIO port */
290 static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
295 ret = bfin_mdio_poll();
299 bfin_write_EMAC_STADAT((u32) value);
302 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
303 SET_REGAD((u16) regnum) |
307 return bfin_mdio_poll();
310 static int bfin_mdiobus_reset(struct mii_bus *bus)
315 static void bfin_mac_adjust_link(struct net_device *dev)
317 struct bfin_mac_local *lp = netdev_priv(dev);
318 struct phy_device *phydev = lp->phydev;
322 spin_lock_irqsave(&lp->lock, flags);
324 /* Now we make sure that we can be in full duplex mode.
325 * If not, we operate in half-duplex mode. */
326 if (phydev->duplex != lp->old_duplex) {
327 u32 opmode = bfin_read_EMAC_OPMODE();
335 bfin_write_EMAC_OPMODE(opmode);
336 lp->old_duplex = phydev->duplex;
339 if (phydev->speed != lp->old_speed) {
340 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
341 u32 opmode = bfin_read_EMAC_OPMODE();
342 switch (phydev->speed) {
351 "Ack! Speed (%d) is not 10/100!\n",
355 bfin_write_EMAC_OPMODE(opmode);
359 lp->old_speed = phydev->speed;
366 } else if (lp->old_link) {
374 u32 opmode = bfin_read_EMAC_OPMODE();
375 phy_print_status(phydev);
376 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
379 spin_unlock_irqrestore(&lp->lock, flags);
383 #define MDC_CLK 2500000
385 static int mii_probe(struct net_device *dev, int phy_mode)
387 struct bfin_mac_local *lp = netdev_priv(dev);
388 struct phy_device *phydev = NULL;
389 unsigned short sysctl;
393 /* Enable PHY output early */
394 if (!(bfin_read_VR_CTL() & CLKBUFOE))
395 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
398 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
400 sysctl = bfin_read_EMAC_SYSCTL();
401 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
402 bfin_write_EMAC_SYSCTL(sysctl);
404 /* search for connected PHY device */
405 for (i = 0; i < PHY_MAX_ADDR; ++i) {
406 struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
409 continue; /* no PHY here... */
412 break; /* found it */
415 /* now we are supposed to have a proper phydev, to attach to... */
417 netdev_err(dev, "no phy device found\n");
421 if (phy_mode != PHY_INTERFACE_MODE_RMII &&
422 phy_mode != PHY_INTERFACE_MODE_MII) {
423 netdev_err(dev, "invalid phy interface mode\n");
427 phydev = phy_connect(dev, dev_name(&phydev->dev),
428 &bfin_mac_adjust_link, phy_mode);
430 if (IS_ERR(phydev)) {
431 netdev_err(dev, "could not attach PHY\n");
432 return PTR_ERR(phydev);
435 /* mask with MAC supported features */
436 phydev->supported &= (SUPPORTED_10baseT_Half
437 | SUPPORTED_10baseT_Full
438 | SUPPORTED_100baseT_Half
439 | SUPPORTED_100baseT_Full
441 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
445 phydev->advertising = phydev->supported;
452 pr_info("attached PHY driver [%s] "
453 "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
454 phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
455 MDC_CLK, mdc_div, sclk/1000000);
465 * interrupt routine for magic packet wakeup
467 static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
473 bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
475 struct bfin_mac_local *lp = netdev_priv(dev);
478 return phy_ethtool_gset(lp->phydev, cmd);
484 bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
486 struct bfin_mac_local *lp = netdev_priv(dev);
488 if (!capable(CAP_NET_ADMIN))
492 return phy_ethtool_sset(lp->phydev, cmd);
497 static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
498 struct ethtool_drvinfo *info)
500 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
501 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
502 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
503 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
506 static void bfin_mac_ethtool_getwol(struct net_device *dev,
507 struct ethtool_wolinfo *wolinfo)
509 struct bfin_mac_local *lp = netdev_priv(dev);
511 wolinfo->supported = WAKE_MAGIC;
512 wolinfo->wolopts = lp->wol;
515 static int bfin_mac_ethtool_setwol(struct net_device *dev,
516 struct ethtool_wolinfo *wolinfo)
518 struct bfin_mac_local *lp = netdev_priv(dev);
521 if (wolinfo->wolopts & (WAKE_MAGICSECURE |
528 lp->wol = wolinfo->wolopts;
530 if (lp->wol && !lp->irq_wake_requested) {
531 /* register wake irq handler */
532 rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
533 IRQF_DISABLED, "EMAC_WAKE", dev);
536 lp->irq_wake_requested = true;
539 if (!lp->wol && lp->irq_wake_requested) {
540 free_irq(IRQ_MAC_WAKEDET, dev);
541 lp->irq_wake_requested = false;
544 /* Make sure the PHY driver doesn't suspend */
545 device_init_wakeup(&dev->dev, lp->wol);
550 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
551 static int bfin_mac_ethtool_get_ts_info(struct net_device *dev,
552 struct ethtool_ts_info *info)
554 struct bfin_mac_local *lp = netdev_priv(dev);
556 info->so_timestamping =
557 SOF_TIMESTAMPING_TX_HARDWARE |
558 SOF_TIMESTAMPING_RX_HARDWARE |
559 SOF_TIMESTAMPING_RAW_HARDWARE;
560 info->phc_index = lp->phc_index;
562 (1 << HWTSTAMP_TX_OFF) |
563 (1 << HWTSTAMP_TX_ON);
565 (1 << HWTSTAMP_FILTER_NONE) |
566 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
567 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
568 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
573 static const struct ethtool_ops bfin_mac_ethtool_ops = {
574 .get_settings = bfin_mac_ethtool_getsettings,
575 .set_settings = bfin_mac_ethtool_setsettings,
576 .get_link = ethtool_op_get_link,
577 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
578 .get_wol = bfin_mac_ethtool_getwol,
579 .set_wol = bfin_mac_ethtool_setwol,
580 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
581 .get_ts_info = bfin_mac_ethtool_get_ts_info,
585 /**************************************************************************/
586 static void setup_system_regs(struct net_device *dev)
588 struct bfin_mac_local *lp = netdev_priv(dev);
590 unsigned short sysctl;
593 * Odd word alignment for Receive Frame DMA word
594 * Configure checksum support and rcve frame word alignment
596 sysctl = bfin_read_EMAC_SYSCTL();
598 * check if interrupt is requested for any PHY,
599 * enable PHY interrupt only if needed
601 for (i = 0; i < PHY_MAX_ADDR; ++i)
602 if (lp->mii_bus->irq[i] != PHY_POLL)
604 if (i < PHY_MAX_ADDR)
607 #if defined(BFIN_MAC_CSUM_OFFLOAD)
612 bfin_write_EMAC_SYSCTL(sysctl);
614 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
616 /* Set vlan regs to let 1522 bytes long packets pass through */
617 bfin_write_EMAC_VLAN1(lp->vlan1_mask);
618 bfin_write_EMAC_VLAN2(lp->vlan2_mask);
620 /* Initialize the TX DMA channel registers */
621 bfin_write_DMA2_X_COUNT(0);
622 bfin_write_DMA2_X_MODIFY(4);
623 bfin_write_DMA2_Y_COUNT(0);
624 bfin_write_DMA2_Y_MODIFY(0);
626 /* Initialize the RX DMA channel registers */
627 bfin_write_DMA1_X_COUNT(0);
628 bfin_write_DMA1_X_MODIFY(4);
629 bfin_write_DMA1_Y_COUNT(0);
630 bfin_write_DMA1_Y_MODIFY(0);
633 static void setup_mac_addr(u8 *mac_addr)
635 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
636 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
638 /* this depends on a little-endian machine */
639 bfin_write_EMAC_ADDRLO(addr_low);
640 bfin_write_EMAC_ADDRHI(addr_hi);
643 static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
645 struct sockaddr *addr = p;
646 if (netif_running(dev))
648 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
649 setup_mac_addr(dev->dev_addr);
653 #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
654 #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
656 static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result)
658 u32 ipn = 1000000000UL / input_clk;
660 unsigned int shift = 0;
666 *shift_result = shift;
667 return 1000000000UL / ppn;
670 static int bfin_mac_hwtstamp_ioctl(struct net_device *netdev,
671 struct ifreq *ifr, int cmd)
673 struct hwtstamp_config config;
674 struct bfin_mac_local *lp = netdev_priv(netdev);
676 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
678 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
681 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
682 __func__, config.flags, config.tx_type, config.rx_filter);
684 /* reserved for future extensions */
688 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
689 (config.tx_type != HWTSTAMP_TX_ON))
692 ptpctl = bfin_read_EMAC_PTP_CTL();
694 switch (config.rx_filter) {
695 case HWTSTAMP_FILTER_NONE:
697 * Dont allow any timestamping
700 bfin_write_EMAC_PTP_FV3(ptpfv3);
702 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
703 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
704 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
706 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
707 * to enable all the field matches.
710 bfin_write_EMAC_PTP_CTL(ptpctl);
712 * Keep the default values of the EMAC_PTP_FOFF register.
714 ptpfoff = 0x4A24170C;
715 bfin_write_EMAC_PTP_FOFF(ptpfoff);
717 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
721 bfin_write_EMAC_PTP_FV1(ptpfv1);
723 bfin_write_EMAC_PTP_FV2(ptpfv2);
725 * The default value (0xFFFC) allows the timestamping of both
726 * received Sync messages and Delay_Req messages.
729 bfin_write_EMAC_PTP_FV3(ptpfv3);
731 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
733 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
734 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
735 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
736 /* Clear all five comparison mask bits (bits[12:8]) in the
737 * EMAC_PTP_CTL register to enable all the field matches.
740 bfin_write_EMAC_PTP_CTL(ptpctl);
742 * Keep the default values of the EMAC_PTP_FOFF register, except set
743 * the PTPCOF field to 0x2A.
745 ptpfoff = 0x2A24170C;
746 bfin_write_EMAC_PTP_FOFF(ptpfoff);
748 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
752 bfin_write_EMAC_PTP_FV1(ptpfv1);
754 bfin_write_EMAC_PTP_FV2(ptpfv2);
756 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
757 * the value to 0xFFF0.
760 bfin_write_EMAC_PTP_FV3(ptpfv3);
762 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
764 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
765 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
766 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
768 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
769 * EFTM and PTPCM field comparison.
772 bfin_write_EMAC_PTP_CTL(ptpctl);
774 * Keep the default values of all the fields of the EMAC_PTP_FOFF
775 * register, except set the PTPCOF field to 0x0E.
777 ptpfoff = 0x0E24170C;
778 bfin_write_EMAC_PTP_FOFF(ptpfoff);
780 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
781 * corresponds to PTP messages on the MAC layer.
784 bfin_write_EMAC_PTP_FV1(ptpfv1);
786 bfin_write_EMAC_PTP_FV2(ptpfv2);
788 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
789 * messages, set the value to 0xFFF0.
792 bfin_write_EMAC_PTP_FV3(ptpfv3);
794 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
800 if (config.tx_type == HWTSTAMP_TX_OFF &&
801 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
803 bfin_write_EMAC_PTP_CTL(ptpctl);
808 bfin_write_EMAC_PTP_CTL(ptpctl);
811 * clear any existing timestamp
813 bfin_read_EMAC_PTP_RXSNAPLO();
814 bfin_read_EMAC_PTP_RXSNAPHI();
816 bfin_read_EMAC_PTP_TXSNAPLO();
817 bfin_read_EMAC_PTP_TXSNAPHI();
822 lp->stamp_cfg = config;
823 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
827 static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
829 struct bfin_mac_local *lp = netdev_priv(netdev);
831 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
832 int timeout_cnt = MAX_TIMEOUT_CNT;
834 /* When doing time stamping, keep the connection to the socket
837 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
840 * The timestamping is done at the EMAC module's MII/RMII interface
841 * when the module sees the Start of Frame of an event message packet. This
842 * interface is the closest possible place to the physical Ethernet transmission
843 * medium, providing the best timing accuracy.
845 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
847 if (timeout_cnt == 0)
848 netdev_err(netdev, "timestamp the TX packet failed\n");
850 struct skb_shared_hwtstamps shhwtstamps;
854 regval = bfin_read_EMAC_PTP_TXSNAPLO();
855 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
856 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
857 ns = regval << lp->shift;
858 shhwtstamps.hwtstamp = ns_to_ktime(ns);
859 skb_tstamp_tx(skb, &shhwtstamps);
864 static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
866 struct bfin_mac_local *lp = netdev_priv(netdev);
869 struct skb_shared_hwtstamps *shhwtstamps;
871 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
874 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
878 shhwtstamps = skb_hwtstamps(skb);
880 regval = bfin_read_EMAC_PTP_RXSNAPLO();
881 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
882 ns = regval << lp->shift;
883 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
884 shhwtstamps->hwtstamp = ns_to_ktime(ns);
887 static void bfin_mac_hwtstamp_init(struct net_device *netdev)
889 struct bfin_mac_local *lp = netdev_priv(netdev);
891 u32 input_clk, phc_clk;
893 /* Initialize hardware timer */
894 input_clk = get_sclk();
895 phc_clk = bfin_select_phc_clock(input_clk, &lp->shift);
896 addend = phc_clk * (1ULL << 32);
897 do_div(addend, input_clk);
898 bfin_write_EMAC_PTP_ADDEND((u32)addend);
901 ppb = 1000000000ULL * input_clk;
902 do_div(ppb, phc_clk);
903 lp->max_ppb = ppb - 1000000000ULL - 1ULL;
905 /* Initialize hwstamp config */
906 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
907 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
910 static u64 bfin_ptp_time_read(struct bfin_mac_local *lp)
915 lo = bfin_read_EMAC_PTP_TIMELO();
916 hi = bfin_read_EMAC_PTP_TIMEHI();
918 ns = ((u64) hi) << 32;
925 static void bfin_ptp_time_write(struct bfin_mac_local *lp, u64 ns)
931 lo = ns & 0xffffffff;
933 bfin_write_EMAC_PTP_TIMELO(lo);
934 bfin_write_EMAC_PTP_TIMEHI(hi);
937 /* PTP Hardware Clock operations */
939 static int bfin_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
944 struct bfin_mac_local *lp =
945 container_of(ptp, struct bfin_mac_local, caps);
954 diff = div_u64(adj, 1000000000ULL);
956 addend = neg_adj ? addend - diff : addend + diff;
958 bfin_write_EMAC_PTP_ADDEND(addend);
963 static int bfin_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
967 struct bfin_mac_local *lp =
968 container_of(ptp, struct bfin_mac_local, caps);
970 spin_lock_irqsave(&lp->phc_lock, flags);
972 now = bfin_ptp_time_read(lp);
974 bfin_ptp_time_write(lp, now);
976 spin_unlock_irqrestore(&lp->phc_lock, flags);
981 static int bfin_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
986 struct bfin_mac_local *lp =
987 container_of(ptp, struct bfin_mac_local, caps);
989 spin_lock_irqsave(&lp->phc_lock, flags);
991 ns = bfin_ptp_time_read(lp);
993 spin_unlock_irqrestore(&lp->phc_lock, flags);
995 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
996 ts->tv_nsec = remainder;
1000 static int bfin_ptp_settime(struct ptp_clock_info *ptp,
1001 const struct timespec *ts)
1004 unsigned long flags;
1005 struct bfin_mac_local *lp =
1006 container_of(ptp, struct bfin_mac_local, caps);
1008 ns = ts->tv_sec * 1000000000ULL;
1011 spin_lock_irqsave(&lp->phc_lock, flags);
1013 bfin_ptp_time_write(lp, ns);
1015 spin_unlock_irqrestore(&lp->phc_lock, flags);
1020 static int bfin_ptp_enable(struct ptp_clock_info *ptp,
1021 struct ptp_clock_request *rq, int on)
1026 static struct ptp_clock_info bfin_ptp_caps = {
1027 .owner = THIS_MODULE,
1028 .name = "BF518 clock",
1034 .adjfreq = bfin_ptp_adjfreq,
1035 .adjtime = bfin_ptp_adjtime,
1036 .gettime = bfin_ptp_gettime,
1037 .settime = bfin_ptp_settime,
1038 .enable = bfin_ptp_enable,
1041 static int bfin_phc_init(struct net_device *netdev, struct device *dev)
1043 struct bfin_mac_local *lp = netdev_priv(netdev);
1045 lp->caps = bfin_ptp_caps;
1046 lp->caps.max_adj = lp->max_ppb;
1047 lp->clock = ptp_clock_register(&lp->caps, dev);
1048 if (IS_ERR(lp->clock))
1049 return PTR_ERR(lp->clock);
1051 lp->phc_index = ptp_clock_index(lp->clock);
1052 spin_lock_init(&lp->phc_lock);
1057 static void bfin_phc_release(struct bfin_mac_local *lp)
1059 ptp_clock_unregister(lp->clock);
1063 # define bfin_mac_hwtstamp_is_none(cfg) 0
1064 # define bfin_mac_hwtstamp_init(dev)
1065 # define bfin_mac_hwtstamp_ioctl(dev, ifr, cmd) (-EOPNOTSUPP)
1066 # define bfin_rx_hwtstamp(dev, skb)
1067 # define bfin_tx_hwtstamp(dev, skb)
1068 # define bfin_phc_init(netdev, dev) 0
1069 # define bfin_phc_release(lp)
1072 static inline void _tx_reclaim_skb(void)
1075 tx_list_head->desc_a.config &= ~DMAEN;
1076 tx_list_head->status.status_word = 0;
1077 if (tx_list_head->skb) {
1078 dev_kfree_skb(tx_list_head->skb);
1079 tx_list_head->skb = NULL;
1081 tx_list_head = tx_list_head->next;
1083 } while (tx_list_head->status.status_word != 0);
1086 static void tx_reclaim_skb(struct bfin_mac_local *lp)
1088 int timeout_cnt = MAX_TIMEOUT_CNT;
1090 if (tx_list_head->status.status_word != 0)
1093 if (current_tx_ptr->next == tx_list_head) {
1094 while (tx_list_head->status.status_word == 0) {
1095 /* slow down polling to avoid too many queue stop. */
1097 /* reclaim skb if DMA is not running. */
1098 if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
1100 if (timeout_cnt-- < 0)
1104 if (timeout_cnt >= 0)
1107 netif_stop_queue(lp->ndev);
1110 if (current_tx_ptr->next != tx_list_head &&
1111 netif_queue_stopped(lp->ndev))
1112 netif_wake_queue(lp->ndev);
1114 if (tx_list_head != current_tx_ptr) {
1115 /* shorten the timer interval if tx queue is stopped */
1116 if (netif_queue_stopped(lp->ndev))
1117 lp->tx_reclaim_timer.expires =
1118 jiffies + (TX_RECLAIM_JIFFIES >> 4);
1120 lp->tx_reclaim_timer.expires =
1121 jiffies + TX_RECLAIM_JIFFIES;
1123 mod_timer(&lp->tx_reclaim_timer,
1124 lp->tx_reclaim_timer.expires);
1130 static void tx_reclaim_skb_timeout(unsigned long lp)
1132 tx_reclaim_skb((struct bfin_mac_local *)lp);
1135 static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
1136 struct net_device *dev)
1138 struct bfin_mac_local *lp = netdev_priv(dev);
1140 u32 data_align = (unsigned long)(skb->data) & 0x3;
1142 current_tx_ptr->skb = skb;
1144 if (data_align == 0x2) {
1145 /* move skb->data to current_tx_ptr payload */
1146 data = (u16 *)(skb->data) - 1;
1147 *data = (u16)(skb->len);
1149 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
1150 * a DMA_Length_Word field associated with the packet. The lower 12 bits
1151 * of this field are the length of the packet payload in bytes and the higher
1152 * 4 bits are the timestamping enable field.
1154 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
1157 current_tx_ptr->desc_a.start_addr = (u32)data;
1158 /* this is important! */
1159 blackfin_dcache_flush_range((u32)data,
1160 (u32)((u8 *)data + skb->len + 4));
1162 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
1163 /* enable timestamping for the sent packet */
1164 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
1165 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
1166 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1168 current_tx_ptr->desc_a.start_addr =
1169 (u32)current_tx_ptr->packet;
1170 blackfin_dcache_flush_range(
1171 (u32)current_tx_ptr->packet,
1172 (u32)(current_tx_ptr->packet + skb->len + 2));
1175 /* make sure the internal data buffers in the core are drained
1176 * so that the DMA descriptors are completely written when the
1177 * DMA engine goes to fetch them below
1181 /* always clear status buffer before start tx dma */
1182 current_tx_ptr->status.status_word = 0;
1184 /* enable this packet's dma */
1185 current_tx_ptr->desc_a.config |= DMAEN;
1187 /* tx dma is running, just return */
1188 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
1191 /* tx dma is not running */
1192 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1193 /* dma enabled, read from memory, size is 6 */
1194 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1195 /* Turn on the EMAC tx */
1196 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1199 bfin_tx_hwtstamp(dev, skb);
1201 current_tx_ptr = current_tx_ptr->next;
1202 dev->stats.tx_packets++;
1203 dev->stats.tx_bytes += (skb->len);
1207 return NETDEV_TX_OK;
1210 #define IP_HEADER_OFF 0
1211 #define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1212 RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1214 static void bfin_mac_rx(struct net_device *dev)
1216 struct sk_buff *skb, *new_skb;
1218 struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev);
1219 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1221 unsigned char fcs[ETH_FCS_LEN + 1];
1224 /* check if frame status word reports an error condition
1225 * we which case we simply drop the packet
1227 if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
1228 netdev_notice(dev, "rx: receive error - packet dropped\n");
1229 dev->stats.rx_dropped++;
1233 /* allocate a new skb for next time receive */
1234 skb = current_rx_ptr->skb;
1236 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
1238 dev->stats.rx_dropped++;
1241 /* reserve 2 bytes for RXDWA padding */
1242 skb_reserve(new_skb, NET_IP_ALIGN);
1243 /* Invidate the data cache of skb->data range when it is write back
1244 * cache. It will prevent overwritting the new data from DMA
1246 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1247 (unsigned long)new_skb->end);
1249 current_rx_ptr->skb = new_skb;
1250 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1252 len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
1253 /* Deduce Ethernet FCS length from Ethernet payload length */
1257 skb->protocol = eth_type_trans(skb, dev);
1259 bfin_rx_hwtstamp(dev, skb);
1261 #if defined(BFIN_MAC_CSUM_OFFLOAD)
1262 /* Checksum offloading only works for IPv4 packets with the standard IP header
1263 * length of 20 bytes, because the blackfin MAC checksum calculation is
1264 * based on that assumption. We must NOT use the calculated checksum if our
1265 * IP version or header break that assumption.
1267 if (skb->data[IP_HEADER_OFF] == 0x45) {
1268 skb->csum = current_rx_ptr->status.ip_payload_csum;
1270 * Deduce Ethernet FCS from hardware generated IP payload checksum.
1271 * IP checksum is based on 16-bit one's complement algorithm.
1272 * To deduce a value from checksum is equal to add its inversion.
1273 * If the IP payload len is odd, the inversed FCS should also
1274 * begin from odd address and leave first byte zero.
1278 for (i = 0; i < ETH_FCS_LEN; i++)
1279 fcs[i + 1] = ~skb->data[skb->len + i];
1280 skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1282 for (i = 0; i < ETH_FCS_LEN; i++)
1283 fcs[i] = ~skb->data[skb->len + i];
1284 skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1286 skb->ip_summed = CHECKSUM_COMPLETE;
1291 dev->stats.rx_packets++;
1292 dev->stats.rx_bytes += len;
1294 current_rx_ptr->status.status_word = 0x00000000;
1295 current_rx_ptr = current_rx_ptr->next;
1298 /* interrupt routine to handle rx and error signal */
1299 static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
1301 struct net_device *dev = dev_id;
1305 if (current_rx_ptr->status.status_word == 0) {
1306 /* no more new packet received */
1308 if (current_rx_ptr->next->status.status_word != 0) {
1309 current_rx_ptr = current_rx_ptr->next;
1313 bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
1314 DMA_DONE | DMA_ERR);
1321 goto get_one_packet;
1324 #ifdef CONFIG_NET_POLL_CONTROLLER
1325 static void bfin_mac_poll(struct net_device *dev)
1327 struct bfin_mac_local *lp = netdev_priv(dev);
1329 disable_irq(IRQ_MAC_RX);
1330 bfin_mac_interrupt(IRQ_MAC_RX, dev);
1332 enable_irq(IRQ_MAC_RX);
1334 #endif /* CONFIG_NET_POLL_CONTROLLER */
1336 static void bfin_mac_disable(void)
1338 unsigned int opmode;
1340 opmode = bfin_read_EMAC_OPMODE();
1343 /* Turn off the EMAC */
1344 bfin_write_EMAC_OPMODE(opmode);
1348 * Enable Interrupts, Receive, and Transmit
1350 static int bfin_mac_enable(struct phy_device *phydev)
1355 pr_debug("%s\n", __func__);
1358 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1359 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1362 ret = bfin_mdio_poll();
1366 /* We enable only RX here */
1367 /* ASTP : Enable Automatic Pad Stripping
1368 PR : Promiscuous Mode for test
1369 PSF : Receive frames with total length less than 64 bytes.
1370 FDMODE : Full Duplex Mode
1371 LB : Internal Loopback for test
1372 RE : Receiver Enable */
1373 opmode = bfin_read_EMAC_OPMODE();
1374 if (opmode & FDMODE)
1377 opmode |= DRO | DC | PSF;
1380 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
1381 opmode |= RMII; /* For Now only 100MBit are supported */
1382 #if defined(CONFIG_BF537) || defined(CONFIG_BF536)
1383 if (__SILICON_REVISION__ < 3) {
1385 * This isn't publicly documented (fun times!), but in
1386 * silicon <=0.2, the RX and TX pins are clocked together.
1387 * So in order to recv, we must enable the transmit side
1388 * as well. This will cause a spurious TX interrupt too,
1389 * but we can easily consume that.
1396 /* Turn on the EMAC rx */
1397 bfin_write_EMAC_OPMODE(opmode);
1402 /* Our watchdog timed out. Called by the networking layer */
1403 static void bfin_mac_timeout(struct net_device *dev)
1405 struct bfin_mac_local *lp = netdev_priv(dev);
1407 pr_debug("%s: %s\n", dev->name, __func__);
1411 del_timer(&lp->tx_reclaim_timer);
1413 /* reset tx queue and free skb */
1414 while (tx_list_head != current_tx_ptr) {
1415 tx_list_head->desc_a.config &= ~DMAEN;
1416 tx_list_head->status.status_word = 0;
1417 if (tx_list_head->skb) {
1418 dev_kfree_skb(tx_list_head->skb);
1419 tx_list_head->skb = NULL;
1421 tx_list_head = tx_list_head->next;
1424 if (netif_queue_stopped(lp->ndev))
1425 netif_wake_queue(lp->ndev);
1427 bfin_mac_enable(lp->phydev);
1429 /* We can accept TX packets again */
1430 dev->trans_start = jiffies; /* prevent tx timeout */
1431 netif_wake_queue(dev);
1434 static void bfin_mac_multicast_hash(struct net_device *dev)
1436 u32 emac_hashhi, emac_hashlo;
1437 struct netdev_hw_addr *ha;
1440 emac_hashhi = emac_hashlo = 0;
1442 netdev_for_each_mc_addr(ha, dev) {
1443 crc = ether_crc(ETH_ALEN, ha->addr);
1447 emac_hashhi |= 1 << (crc & 0x1f);
1449 emac_hashlo |= 1 << (crc & 0x1f);
1452 bfin_write_EMAC_HASHHI(emac_hashhi);
1453 bfin_write_EMAC_HASHLO(emac_hashlo);
1457 * This routine will, depending on the values passed to it,
1458 * either make it accept multicast packets, go into
1459 * promiscuous mode (for TCPDUMP and cousins) or accept
1460 * a select set of multicast packets
1462 static void bfin_mac_set_multicast_list(struct net_device *dev)
1466 if (dev->flags & IFF_PROMISC) {
1467 netdev_info(dev, "set promisc mode\n");
1468 sysctl = bfin_read_EMAC_OPMODE();
1470 bfin_write_EMAC_OPMODE(sysctl);
1471 } else if (dev->flags & IFF_ALLMULTI) {
1472 /* accept all multicast */
1473 sysctl = bfin_read_EMAC_OPMODE();
1475 bfin_write_EMAC_OPMODE(sysctl);
1476 } else if (!netdev_mc_empty(dev)) {
1477 /* set up multicast hash table */
1478 sysctl = bfin_read_EMAC_OPMODE();
1480 bfin_write_EMAC_OPMODE(sysctl);
1481 bfin_mac_multicast_hash(dev);
1483 /* clear promisc or multicast mode */
1484 sysctl = bfin_read_EMAC_OPMODE();
1485 sysctl &= ~(RAF | PAM);
1486 bfin_write_EMAC_OPMODE(sysctl);
1490 static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1492 struct bfin_mac_local *lp = netdev_priv(netdev);
1494 if (!netif_running(netdev))
1499 return bfin_mac_hwtstamp_ioctl(netdev, ifr, cmd);
1502 return phy_mii_ioctl(lp->phydev, ifr, cmd);
1509 * this puts the device in an inactive state
1511 static void bfin_mac_shutdown(struct net_device *dev)
1513 /* Turn off the EMAC */
1514 bfin_write_EMAC_OPMODE(0x00000000);
1515 /* Turn off the EMAC RX DMA */
1516 bfin_write_DMA1_CONFIG(0x0000);
1517 bfin_write_DMA2_CONFIG(0x0000);
1521 * Open and Initialize the interface
1523 * Set up everything, reset the card, etc..
1525 static int bfin_mac_open(struct net_device *dev)
1527 struct bfin_mac_local *lp = netdev_priv(dev);
1529 pr_debug("%s: %s\n", dev->name, __func__);
1532 * Check that the address is valid. If its not, refuse
1533 * to bring the device up. The user must specify an
1534 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1536 if (!is_valid_ether_addr(dev->dev_addr)) {
1537 netdev_warn(dev, "no valid ethernet hw addr\n");
1541 /* initial rx and tx list */
1542 ret = desc_list_init(dev);
1546 phy_start(lp->phydev);
1547 phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
1548 setup_system_regs(dev);
1549 setup_mac_addr(dev->dev_addr);
1552 ret = bfin_mac_enable(lp->phydev);
1555 pr_debug("hardware init finished\n");
1557 netif_start_queue(dev);
1558 netif_carrier_on(dev);
1564 * this makes the board clean up everything that it can
1565 * and not talk to the outside world. Caused by
1566 * an 'ifconfig ethX down'
1568 static int bfin_mac_close(struct net_device *dev)
1570 struct bfin_mac_local *lp = netdev_priv(dev);
1571 pr_debug("%s: %s\n", dev->name, __func__);
1573 netif_stop_queue(dev);
1574 netif_carrier_off(dev);
1576 phy_stop(lp->phydev);
1577 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
1579 /* clear everything */
1580 bfin_mac_shutdown(dev);
1582 /* free the rx/tx buffers */
1588 static const struct net_device_ops bfin_mac_netdev_ops = {
1589 .ndo_open = bfin_mac_open,
1590 .ndo_stop = bfin_mac_close,
1591 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1592 .ndo_set_mac_address = bfin_mac_set_mac_address,
1593 .ndo_tx_timeout = bfin_mac_timeout,
1594 .ndo_set_rx_mode = bfin_mac_set_multicast_list,
1595 .ndo_do_ioctl = bfin_mac_ioctl,
1596 .ndo_validate_addr = eth_validate_addr,
1597 .ndo_change_mtu = eth_change_mtu,
1598 #ifdef CONFIG_NET_POLL_CONTROLLER
1599 .ndo_poll_controller = bfin_mac_poll,
1603 static int bfin_mac_probe(struct platform_device *pdev)
1605 struct net_device *ndev;
1606 struct bfin_mac_local *lp;
1607 struct platform_device *pd;
1608 struct bfin_mii_bus_platform_data *mii_bus_data;
1611 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
1615 SET_NETDEV_DEV(ndev, &pdev->dev);
1616 platform_set_drvdata(pdev, ndev);
1617 lp = netdev_priv(ndev);
1620 /* Grab the MAC address in the MAC */
1621 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1622 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
1625 /*todo: how to proble? which is revision_register */
1626 bfin_write_EMAC_ADDRLO(0x12345678);
1627 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
1628 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1630 goto out_err_probe_mac;
1635 * Is it valid? (Did bootloader initialize it?)
1636 * Grab the MAC from the board somehow
1637 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1639 if (!is_valid_ether_addr(ndev->dev_addr)) {
1640 if (bfin_get_ether_addr(ndev->dev_addr) ||
1641 !is_valid_ether_addr(ndev->dev_addr)) {
1642 /* Still not valid, get a random one */
1643 netdev_warn(ndev, "Setting Ethernet MAC to a random one\n");
1644 eth_hw_addr_random(ndev);
1648 setup_mac_addr(ndev->dev_addr);
1650 if (!dev_get_platdata(&pdev->dev)) {
1651 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1653 goto out_err_probe_mac;
1655 pd = dev_get_platdata(&pdev->dev);
1656 lp->mii_bus = platform_get_drvdata(pd);
1658 dev_err(&pdev->dev, "Cannot get mii_bus!\n");
1660 goto out_err_probe_mac;
1662 lp->mii_bus->priv = ndev;
1663 mii_bus_data = dev_get_platdata(&pd->dev);
1665 rc = mii_probe(ndev, mii_bus_data->phy_mode);
1667 dev_err(&pdev->dev, "MII Probe failed!\n");
1668 goto out_err_mii_probe;
1671 lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
1672 lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
1674 /* Fill in the fields of the device structure with ethernet values. */
1677 ndev->netdev_ops = &bfin_mac_netdev_ops;
1678 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
1680 init_timer(&lp->tx_reclaim_timer);
1681 lp->tx_reclaim_timer.data = (unsigned long)lp;
1682 lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout;
1684 spin_lock_init(&lp->lock);
1686 /* now, enable interrupts */
1687 /* register irq handler */
1688 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
1689 IRQF_DISABLED, "EMAC_RX", ndev);
1691 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1693 goto out_err_request_irq;
1696 rc = register_netdev(ndev);
1698 dev_err(&pdev->dev, "Cannot register net device!\n");
1699 goto out_err_reg_ndev;
1702 bfin_mac_hwtstamp_init(ndev);
1703 rc = bfin_phc_init(ndev, &pdev->dev);
1705 dev_err(&pdev->dev, "Cannot register PHC device!\n");
1709 /* now, print out the card info, in a short format.. */
1710 netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
1716 free_irq(IRQ_MAC_RX, ndev);
1717 out_err_request_irq:
1719 mdiobus_unregister(lp->mii_bus);
1720 mdiobus_free(lp->mii_bus);
1727 static int bfin_mac_remove(struct platform_device *pdev)
1729 struct net_device *ndev = platform_get_drvdata(pdev);
1730 struct bfin_mac_local *lp = netdev_priv(ndev);
1732 bfin_phc_release(lp);
1734 lp->mii_bus->priv = NULL;
1736 unregister_netdev(ndev);
1738 free_irq(IRQ_MAC_RX, ndev);
1746 static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
1748 struct net_device *net_dev = platform_get_drvdata(pdev);
1749 struct bfin_mac_local *lp = netdev_priv(net_dev);
1752 bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1753 bfin_write_EMAC_WKUP_CTL(MPKE);
1754 enable_irq_wake(IRQ_MAC_WAKEDET);
1756 if (netif_running(net_dev))
1757 bfin_mac_close(net_dev);
1763 static int bfin_mac_resume(struct platform_device *pdev)
1765 struct net_device *net_dev = platform_get_drvdata(pdev);
1766 struct bfin_mac_local *lp = netdev_priv(net_dev);
1769 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1770 bfin_write_EMAC_WKUP_CTL(0);
1771 disable_irq_wake(IRQ_MAC_WAKEDET);
1773 if (netif_running(net_dev))
1774 bfin_mac_open(net_dev);
1780 #define bfin_mac_suspend NULL
1781 #define bfin_mac_resume NULL
1782 #endif /* CONFIG_PM */
1784 static int bfin_mii_bus_probe(struct platform_device *pdev)
1786 struct mii_bus *miibus;
1787 struct bfin_mii_bus_platform_data *mii_bus_pd;
1788 const unsigned short *pin_req;
1791 mii_bus_pd = dev_get_platdata(&pdev->dev);
1793 dev_err(&pdev->dev, "No peripherals in platform data!\n");
1798 * We are setting up a network card,
1799 * so set the GPIO pins to Ethernet mode
1801 pin_req = mii_bus_pd->mac_peripherals;
1802 rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
1804 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1809 miibus = mdiobus_alloc();
1812 miibus->read = bfin_mdiobus_read;
1813 miibus->write = bfin_mdiobus_write;
1814 miibus->reset = bfin_mdiobus_reset;
1816 miibus->parent = &pdev->dev;
1817 miibus->name = "bfin_mii_bus";
1818 miibus->phy_mask = mii_bus_pd->phy_mask;
1820 snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
1821 pdev->name, pdev->id);
1822 miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1824 goto out_err_irq_alloc;
1826 for (i = rc; i < PHY_MAX_ADDR; ++i)
1827 miibus->irq[i] = PHY_POLL;
1829 rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
1830 if (rc != mii_bus_pd->phydev_number)
1831 dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
1832 mii_bus_pd->phydev_number);
1833 for (i = 0; i < rc; ++i) {
1834 unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
1835 if (phyaddr < PHY_MAX_ADDR)
1836 miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
1839 "Invalid PHY address %i for phydev %i\n",
1843 rc = mdiobus_register(miibus);
1845 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1846 goto out_err_mdiobus_register;
1849 platform_set_drvdata(pdev, miibus);
1852 out_err_mdiobus_register:
1855 mdiobus_free(miibus);
1857 peripheral_free_list(pin_req);
1862 static int bfin_mii_bus_remove(struct platform_device *pdev)
1864 struct mii_bus *miibus = platform_get_drvdata(pdev);
1865 struct bfin_mii_bus_platform_data *mii_bus_pd =
1866 dev_get_platdata(&pdev->dev);
1868 mdiobus_unregister(miibus);
1870 mdiobus_free(miibus);
1871 peripheral_free_list(mii_bus_pd->mac_peripherals);
1876 static struct platform_driver bfin_mii_bus_driver = {
1877 .probe = bfin_mii_bus_probe,
1878 .remove = bfin_mii_bus_remove,
1880 .name = "bfin_mii_bus",
1881 .owner = THIS_MODULE,
1885 static struct platform_driver bfin_mac_driver = {
1886 .probe = bfin_mac_probe,
1887 .remove = bfin_mac_remove,
1888 .resume = bfin_mac_resume,
1889 .suspend = bfin_mac_suspend,
1891 .name = KBUILD_MODNAME,
1892 .owner = THIS_MODULE,
1896 static int __init bfin_mac_init(void)
1899 ret = platform_driver_register(&bfin_mii_bus_driver);
1901 return platform_driver_register(&bfin_mac_driver);
1905 module_init(bfin_mac_init);
1907 static void __exit bfin_mac_cleanup(void)
1909 platform_driver_unregister(&bfin_mac_driver);
1910 platform_driver_unregister(&bfin_mii_bus_driver);
1913 module_exit(bfin_mac_cleanup);