2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #ifndef __XGBE_COMMON_H__
118 #define __XGBE_COMMON_H__
120 /* DMA register offsets */
121 #define DMA_MR 0x3000
122 #define DMA_SBMR 0x3004
123 #define DMA_ISR 0x3008
124 #define DMA_AXIARCR 0x3010
125 #define DMA_AXIAWCR 0x3018
126 #define DMA_DSR0 0x3020
127 #define DMA_DSR1 0x3024
128 #define DMA_DSR2 0x3028
129 #define DMA_DSR3 0x302c
130 #define DMA_DSR4 0x3030
132 /* DMA register entry bit positions and sizes */
133 #define DMA_AXIARCR_DRC_INDEX 0
134 #define DMA_AXIARCR_DRC_WIDTH 4
135 #define DMA_AXIARCR_DRD_INDEX 4
136 #define DMA_AXIARCR_DRD_WIDTH 2
137 #define DMA_AXIARCR_TEC_INDEX 8
138 #define DMA_AXIARCR_TEC_WIDTH 4
139 #define DMA_AXIARCR_TED_INDEX 12
140 #define DMA_AXIARCR_TED_WIDTH 2
141 #define DMA_AXIARCR_THC_INDEX 16
142 #define DMA_AXIARCR_THC_WIDTH 4
143 #define DMA_AXIARCR_THD_INDEX 20
144 #define DMA_AXIARCR_THD_WIDTH 2
145 #define DMA_AXIAWCR_DWC_INDEX 0
146 #define DMA_AXIAWCR_DWC_WIDTH 4
147 #define DMA_AXIAWCR_DWD_INDEX 4
148 #define DMA_AXIAWCR_DWD_WIDTH 2
149 #define DMA_AXIAWCR_RPC_INDEX 8
150 #define DMA_AXIAWCR_RPC_WIDTH 4
151 #define DMA_AXIAWCR_RPD_INDEX 12
152 #define DMA_AXIAWCR_RPD_WIDTH 2
153 #define DMA_AXIAWCR_RHC_INDEX 16
154 #define DMA_AXIAWCR_RHC_WIDTH 4
155 #define DMA_AXIAWCR_RHD_INDEX 20
156 #define DMA_AXIAWCR_RHD_WIDTH 2
157 #define DMA_AXIAWCR_TDC_INDEX 24
158 #define DMA_AXIAWCR_TDC_WIDTH 4
159 #define DMA_AXIAWCR_TDD_INDEX 28
160 #define DMA_AXIAWCR_TDD_WIDTH 2
161 #define DMA_DSR0_RPS_INDEX 8
162 #define DMA_DSR0_RPS_WIDTH 4
163 #define DMA_DSR0_TPS_INDEX 12
164 #define DMA_DSR0_TPS_WIDTH 4
165 #define DMA_ISR_MACIS_INDEX 17
166 #define DMA_ISR_MACIS_WIDTH 1
167 #define DMA_ISR_MTLIS_INDEX 16
168 #define DMA_ISR_MTLIS_WIDTH 1
169 #define DMA_MR_SWR_INDEX 0
170 #define DMA_MR_SWR_WIDTH 1
171 #define DMA_SBMR_EAME_INDEX 11
172 #define DMA_SBMR_EAME_WIDTH 1
173 #define DMA_SBMR_UNDEF_INDEX 0
174 #define DMA_SBMR_UNDEF_WIDTH 1
176 /* DMA channel register offsets
177 * Multiple channels can be active. The first channel has registers
178 * that begin at 0x3100. Each subsequent channel has registers that
179 * are accessed using an offset of 0x80 from the previous channel.
181 #define DMA_CH_BASE 0x3100
182 #define DMA_CH_INC 0x80
184 #define DMA_CH_CR 0x00
185 #define DMA_CH_TCR 0x04
186 #define DMA_CH_RCR 0x08
187 #define DMA_CH_TDLR_HI 0x10
188 #define DMA_CH_TDLR_LO 0x14
189 #define DMA_CH_RDLR_HI 0x18
190 #define DMA_CH_RDLR_LO 0x1c
191 #define DMA_CH_TDTR_LO 0x24
192 #define DMA_CH_RDTR_LO 0x2c
193 #define DMA_CH_TDRLR 0x30
194 #define DMA_CH_RDRLR 0x34
195 #define DMA_CH_IER 0x38
196 #define DMA_CH_RIWT 0x3c
197 #define DMA_CH_CATDR_LO 0x44
198 #define DMA_CH_CARDR_LO 0x4c
199 #define DMA_CH_CATBR_HI 0x50
200 #define DMA_CH_CATBR_LO 0x54
201 #define DMA_CH_CARBR_HI 0x58
202 #define DMA_CH_CARBR_LO 0x5c
203 #define DMA_CH_SR 0x60
205 /* DMA channel register entry bit positions and sizes */
206 #define DMA_CH_CR_PBLX8_INDEX 16
207 #define DMA_CH_CR_PBLX8_WIDTH 1
208 #define DMA_CH_IER_AIE_INDEX 15
209 #define DMA_CH_IER_AIE_WIDTH 1
210 #define DMA_CH_IER_FBEE_INDEX 12
211 #define DMA_CH_IER_FBEE_WIDTH 1
212 #define DMA_CH_IER_NIE_INDEX 16
213 #define DMA_CH_IER_NIE_WIDTH 1
214 #define DMA_CH_IER_RBUE_INDEX 7
215 #define DMA_CH_IER_RBUE_WIDTH 1
216 #define DMA_CH_IER_RIE_INDEX 6
217 #define DMA_CH_IER_RIE_WIDTH 1
218 #define DMA_CH_IER_RSE_INDEX 8
219 #define DMA_CH_IER_RSE_WIDTH 1
220 #define DMA_CH_IER_TBUE_INDEX 2
221 #define DMA_CH_IER_TBUE_WIDTH 1
222 #define DMA_CH_IER_TIE_INDEX 0
223 #define DMA_CH_IER_TIE_WIDTH 1
224 #define DMA_CH_IER_TXSE_INDEX 1
225 #define DMA_CH_IER_TXSE_WIDTH 1
226 #define DMA_CH_RCR_PBL_INDEX 16
227 #define DMA_CH_RCR_PBL_WIDTH 6
228 #define DMA_CH_RCR_RBSZ_INDEX 1
229 #define DMA_CH_RCR_RBSZ_WIDTH 14
230 #define DMA_CH_RCR_SR_INDEX 0
231 #define DMA_CH_RCR_SR_WIDTH 1
232 #define DMA_CH_RIWT_RWT_INDEX 0
233 #define DMA_CH_RIWT_RWT_WIDTH 8
234 #define DMA_CH_SR_FBE_INDEX 12
235 #define DMA_CH_SR_FBE_WIDTH 1
236 #define DMA_CH_SR_RBU_INDEX 7
237 #define DMA_CH_SR_RBU_WIDTH 1
238 #define DMA_CH_SR_RI_INDEX 6
239 #define DMA_CH_SR_RI_WIDTH 1
240 #define DMA_CH_SR_RPS_INDEX 8
241 #define DMA_CH_SR_RPS_WIDTH 1
242 #define DMA_CH_SR_TBU_INDEX 2
243 #define DMA_CH_SR_TBU_WIDTH 1
244 #define DMA_CH_SR_TI_INDEX 0
245 #define DMA_CH_SR_TI_WIDTH 1
246 #define DMA_CH_SR_TPS_INDEX 1
247 #define DMA_CH_SR_TPS_WIDTH 1
248 #define DMA_CH_TCR_OSP_INDEX 4
249 #define DMA_CH_TCR_OSP_WIDTH 1
250 #define DMA_CH_TCR_PBL_INDEX 16
251 #define DMA_CH_TCR_PBL_WIDTH 6
252 #define DMA_CH_TCR_ST_INDEX 0
253 #define DMA_CH_TCR_ST_WIDTH 1
254 #define DMA_CH_TCR_TSE_INDEX 12
255 #define DMA_CH_TCR_TSE_WIDTH 1
257 /* DMA channel register values */
258 #define DMA_OSP_DISABLE 0x00
259 #define DMA_OSP_ENABLE 0x01
264 #define DMA_PBL_16 16
265 #define DMA_PBL_32 32
266 #define DMA_PBL_64 64 /* 8 x 8 */
267 #define DMA_PBL_128 128 /* 8 x 16 */
268 #define DMA_PBL_256 256 /* 8 x 32 */
269 #define DMA_PBL_X8_DISABLE 0x00
270 #define DMA_PBL_X8_ENABLE 0x01
273 /* MAC register offsets */
274 #define MAC_TCR 0x0000
275 #define MAC_RCR 0x0004
276 #define MAC_PFR 0x0008
277 #define MAC_WTR 0x000c
278 #define MAC_HTR0 0x0010
279 #define MAC_HTR1 0x0014
280 #define MAC_HTR2 0x0018
281 #define MAC_HTR3 0x001c
282 #define MAC_HTR4 0x0020
283 #define MAC_HTR5 0x0024
284 #define MAC_HTR6 0x0028
285 #define MAC_HTR7 0x002c
286 #define MAC_VLANTR 0x0050
287 #define MAC_VLANHTR 0x0058
288 #define MAC_VLANIR 0x0060
289 #define MAC_IVLANIR 0x0064
290 #define MAC_RETMR 0x006c
291 #define MAC_Q0TFCR 0x0070
292 #define MAC_RFCR 0x0090
293 #define MAC_RQC0R 0x00a0
294 #define MAC_RQC1R 0x00a4
295 #define MAC_RQC2R 0x00a8
296 #define MAC_RQC3R 0x00ac
297 #define MAC_ISR 0x00b0
298 #define MAC_IER 0x00b4
299 #define MAC_RTSR 0x00b8
300 #define MAC_PMTCSR 0x00c0
301 #define MAC_RWKPFR 0x00c4
302 #define MAC_LPICSR 0x00d0
303 #define MAC_LPITCR 0x00d4
304 #define MAC_VR 0x0110
305 #define MAC_DR 0x0114
306 #define MAC_HWF0R 0x011c
307 #define MAC_HWF1R 0x0120
308 #define MAC_HWF2R 0x0124
309 #define MAC_GPIOCR 0x0278
310 #define MAC_GPIOSR 0x027c
311 #define MAC_MACA0HR 0x0300
312 #define MAC_MACA0LR 0x0304
313 #define MAC_MACA1HR 0x0308
314 #define MAC_MACA1LR 0x030c
316 #define MAC_QTFCR_INC 4
317 #define MAC_MACA_INC 4
319 /* MAC register entry bit positions and sizes */
320 #define MAC_HWF0R_ADDMACADRSEL_INDEX 18
321 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
322 #define MAC_HWF0R_ARPOFFSEL_INDEX 9
323 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1
324 #define MAC_HWF0R_EEESEL_INDEX 13
325 #define MAC_HWF0R_EEESEL_WIDTH 1
326 #define MAC_HWF0R_GMIISEL_INDEX 1
327 #define MAC_HWF0R_GMIISEL_WIDTH 1
328 #define MAC_HWF0R_MGKSEL_INDEX 7
329 #define MAC_HWF0R_MGKSEL_WIDTH 1
330 #define MAC_HWF0R_MMCSEL_INDEX 8
331 #define MAC_HWF0R_MMCSEL_WIDTH 1
332 #define MAC_HWF0R_RWKSEL_INDEX 6
333 #define MAC_HWF0R_RWKSEL_WIDTH 1
334 #define MAC_HWF0R_RXCOESEL_INDEX 16
335 #define MAC_HWF0R_RXCOESEL_WIDTH 1
336 #define MAC_HWF0R_SAVLANINS_INDEX 27
337 #define MAC_HWF0R_SAVLANINS_WIDTH 1
338 #define MAC_HWF0R_SMASEL_INDEX 5
339 #define MAC_HWF0R_SMASEL_WIDTH 1
340 #define MAC_HWF0R_TSSEL_INDEX 12
341 #define MAC_HWF0R_TSSEL_WIDTH 1
342 #define MAC_HWF0R_TSSTSSEL_INDEX 25
343 #define MAC_HWF0R_TSSTSSEL_WIDTH 2
344 #define MAC_HWF0R_TXCOESEL_INDEX 14
345 #define MAC_HWF0R_TXCOESEL_WIDTH 1
346 #define MAC_HWF0R_VLHASH_INDEX 4
347 #define MAC_HWF0R_VLHASH_WIDTH 1
348 #define MAC_HWF1R_ADVTHWORD_INDEX 13
349 #define MAC_HWF1R_ADVTHWORD_WIDTH 1
350 #define MAC_HWF1R_DBGMEMA_INDEX 19
351 #define MAC_HWF1R_DBGMEMA_WIDTH 1
352 #define MAC_HWF1R_DCBEN_INDEX 16
353 #define MAC_HWF1R_DCBEN_WIDTH 1
354 #define MAC_HWF1R_HASHTBLSZ_INDEX 24
355 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3
356 #define MAC_HWF1R_L3L4FNUM_INDEX 27
357 #define MAC_HWF1R_L3L4FNUM_WIDTH 4
358 #define MAC_HWF1R_RSSEN_INDEX 20
359 #define MAC_HWF1R_RSSEN_WIDTH 1
360 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0
361 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5
362 #define MAC_HWF1R_SPHEN_INDEX 17
363 #define MAC_HWF1R_SPHEN_WIDTH 1
364 #define MAC_HWF1R_TSOEN_INDEX 18
365 #define MAC_HWF1R_TSOEN_WIDTH 1
366 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6
367 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5
368 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28
369 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3
370 #define MAC_HWF2R_PPSOUTNUM_INDEX 24
371 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3
372 #define MAC_HWF2R_RXCHCNT_INDEX 12
373 #define MAC_HWF2R_RXCHCNT_WIDTH 4
374 #define MAC_HWF2R_RXQCNT_INDEX 0
375 #define MAC_HWF2R_RXQCNT_WIDTH 4
376 #define MAC_HWF2R_TXCHCNT_INDEX 18
377 #define MAC_HWF2R_TXCHCNT_WIDTH 4
378 #define MAC_HWF2R_TXQCNT_INDEX 6
379 #define MAC_HWF2R_TXQCNT_WIDTH 4
380 #define MAC_ISR_MMCRXIS_INDEX 9
381 #define MAC_ISR_MMCRXIS_WIDTH 1
382 #define MAC_ISR_MMCTXIS_INDEX 10
383 #define MAC_ISR_MMCTXIS_WIDTH 1
384 #define MAC_ISR_PMTIS_INDEX 4
385 #define MAC_ISR_PMTIS_WIDTH 1
386 #define MAC_MACA1HR_AE_INDEX 31
387 #define MAC_MACA1HR_AE_WIDTH 1
388 #define MAC_PFR_HMC_INDEX 2
389 #define MAC_PFR_HMC_WIDTH 1
390 #define MAC_PFR_HUC_INDEX 1
391 #define MAC_PFR_HUC_WIDTH 1
392 #define MAC_PFR_PM_INDEX 4
393 #define MAC_PFR_PM_WIDTH 1
394 #define MAC_PFR_PR_INDEX 0
395 #define MAC_PFR_PR_WIDTH 1
396 #define MAC_PFR_VTFE_INDEX 16
397 #define MAC_PFR_VTFE_WIDTH 1
398 #define MAC_PMTCSR_MGKPKTEN_INDEX 1
399 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1
400 #define MAC_PMTCSR_PWRDWN_INDEX 0
401 #define MAC_PMTCSR_PWRDWN_WIDTH 1
402 #define MAC_PMTCSR_RWKFILTRST_INDEX 31
403 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1
404 #define MAC_PMTCSR_RWKPKTEN_INDEX 2
405 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1
406 #define MAC_Q0TFCR_PT_INDEX 16
407 #define MAC_Q0TFCR_PT_WIDTH 16
408 #define MAC_Q0TFCR_TFE_INDEX 1
409 #define MAC_Q0TFCR_TFE_WIDTH 1
410 #define MAC_RCR_ACS_INDEX 1
411 #define MAC_RCR_ACS_WIDTH 1
412 #define MAC_RCR_CST_INDEX 2
413 #define MAC_RCR_CST_WIDTH 1
414 #define MAC_RCR_DCRCC_INDEX 3
415 #define MAC_RCR_DCRCC_WIDTH 1
416 #define MAC_RCR_IPC_INDEX 9
417 #define MAC_RCR_IPC_WIDTH 1
418 #define MAC_RCR_JE_INDEX 8
419 #define MAC_RCR_JE_WIDTH 1
420 #define MAC_RCR_LM_INDEX 10
421 #define MAC_RCR_LM_WIDTH 1
422 #define MAC_RCR_RE_INDEX 0
423 #define MAC_RCR_RE_WIDTH 1
424 #define MAC_RFCR_RFE_INDEX 0
425 #define MAC_RFCR_RFE_WIDTH 1
426 #define MAC_RQC0R_RXQ0EN_INDEX 0
427 #define MAC_RQC0R_RXQ0EN_WIDTH 2
428 #define MAC_TCR_SS_INDEX 29
429 #define MAC_TCR_SS_WIDTH 2
430 #define MAC_TCR_TE_INDEX 0
431 #define MAC_TCR_TE_WIDTH 1
432 #define MAC_VLANHTR_VLHT_INDEX 0
433 #define MAC_VLANHTR_VLHT_WIDTH 16
434 #define MAC_VLANIR_VLTI_INDEX 20
435 #define MAC_VLANIR_VLTI_WIDTH 1
436 #define MAC_VLANIR_CSVL_INDEX 19
437 #define MAC_VLANIR_CSVL_WIDTH 1
438 #define MAC_VLANTR_DOVLTC_INDEX 20
439 #define MAC_VLANTR_DOVLTC_WIDTH 1
440 #define MAC_VLANTR_ERSVLM_INDEX 19
441 #define MAC_VLANTR_ERSVLM_WIDTH 1
442 #define MAC_VLANTR_ESVL_INDEX 18
443 #define MAC_VLANTR_ESVL_WIDTH 1
444 #define MAC_VLANTR_ETV_INDEX 16
445 #define MAC_VLANTR_ETV_WIDTH 1
446 #define MAC_VLANTR_EVLS_INDEX 21
447 #define MAC_VLANTR_EVLS_WIDTH 2
448 #define MAC_VLANTR_EVLRXS_INDEX 24
449 #define MAC_VLANTR_EVLRXS_WIDTH 1
450 #define MAC_VLANTR_VL_INDEX 0
451 #define MAC_VLANTR_VL_WIDTH 16
452 #define MAC_VLANTR_VTHM_INDEX 25
453 #define MAC_VLANTR_VTHM_WIDTH 1
454 #define MAC_VLANTR_VTIM_INDEX 17
455 #define MAC_VLANTR_VTIM_WIDTH 1
456 #define MAC_VR_DEVID_INDEX 8
457 #define MAC_VR_DEVID_WIDTH 8
458 #define MAC_VR_SNPSVER_INDEX 0
459 #define MAC_VR_SNPSVER_WIDTH 8
460 #define MAC_VR_USERVER_INDEX 16
461 #define MAC_VR_USERVER_WIDTH 8
463 /* MMC register offsets */
464 #define MMC_CR 0x0800
465 #define MMC_RISR 0x0804
466 #define MMC_TISR 0x0808
467 #define MMC_RIER 0x080c
468 #define MMC_TIER 0x0810
469 #define MMC_TXOCTETCOUNT_GB_LO 0x0814
470 #define MMC_TXOCTETCOUNT_GB_HI 0x0818
471 #define MMC_TXFRAMECOUNT_GB_LO 0x081c
472 #define MMC_TXFRAMECOUNT_GB_HI 0x0820
473 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824
474 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828
475 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c
476 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830
477 #define MMC_TX64OCTETS_GB_LO 0x0834
478 #define MMC_TX64OCTETS_GB_HI 0x0838
479 #define MMC_TX65TO127OCTETS_GB_LO 0x083c
480 #define MMC_TX65TO127OCTETS_GB_HI 0x0840
481 #define MMC_TX128TO255OCTETS_GB_LO 0x0844
482 #define MMC_TX128TO255OCTETS_GB_HI 0x0848
483 #define MMC_TX256TO511OCTETS_GB_LO 0x084c
484 #define MMC_TX256TO511OCTETS_GB_HI 0x0850
485 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854
486 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858
487 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c
488 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860
489 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864
490 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868
491 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c
492 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870
493 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874
494 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878
495 #define MMC_TXUNDERFLOWERROR_LO 0x087c
496 #define MMC_TXUNDERFLOWERROR_HI 0x0880
497 #define MMC_TXOCTETCOUNT_G_LO 0x0884
498 #define MMC_TXOCTETCOUNT_G_HI 0x0888
499 #define MMC_TXFRAMECOUNT_G_LO 0x088c
500 #define MMC_TXFRAMECOUNT_G_HI 0x0890
501 #define MMC_TXPAUSEFRAMES_LO 0x0894
502 #define MMC_TXPAUSEFRAMES_HI 0x0898
503 #define MMC_TXVLANFRAMES_G_LO 0x089c
504 #define MMC_TXVLANFRAMES_G_HI 0x08a0
505 #define MMC_RXFRAMECOUNT_GB_LO 0x0900
506 #define MMC_RXFRAMECOUNT_GB_HI 0x0904
507 #define MMC_RXOCTETCOUNT_GB_LO 0x0908
508 #define MMC_RXOCTETCOUNT_GB_HI 0x090c
509 #define MMC_RXOCTETCOUNT_G_LO 0x0910
510 #define MMC_RXOCTETCOUNT_G_HI 0x0914
511 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918
512 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c
513 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920
514 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924
515 #define MMC_RXCRCERROR_LO 0x0928
516 #define MMC_RXCRCERROR_HI 0x092c
517 #define MMC_RXRUNTERROR 0x0930
518 #define MMC_RXJABBERERROR 0x0934
519 #define MMC_RXUNDERSIZE_G 0x0938
520 #define MMC_RXOVERSIZE_G 0x093c
521 #define MMC_RX64OCTETS_GB_LO 0x0940
522 #define MMC_RX64OCTETS_GB_HI 0x0944
523 #define MMC_RX65TO127OCTETS_GB_LO 0x0948
524 #define MMC_RX65TO127OCTETS_GB_HI 0x094c
525 #define MMC_RX128TO255OCTETS_GB_LO 0x0950
526 #define MMC_RX128TO255OCTETS_GB_HI 0x0954
527 #define MMC_RX256TO511OCTETS_GB_LO 0x0958
528 #define MMC_RX256TO511OCTETS_GB_HI 0x095c
529 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960
530 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964
531 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968
532 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c
533 #define MMC_RXUNICASTFRAMES_G_LO 0x0970
534 #define MMC_RXUNICASTFRAMES_G_HI 0x0974
535 #define MMC_RXLENGTHERROR_LO 0x0978
536 #define MMC_RXLENGTHERROR_HI 0x097c
537 #define MMC_RXOUTOFRANGETYPE_LO 0x0980
538 #define MMC_RXOUTOFRANGETYPE_HI 0x0984
539 #define MMC_RXPAUSEFRAMES_LO 0x0988
540 #define MMC_RXPAUSEFRAMES_HI 0x098c
541 #define MMC_RXFIFOOVERFLOW_LO 0x0990
542 #define MMC_RXFIFOOVERFLOW_HI 0x0994
543 #define MMC_RXVLANFRAMES_GB_LO 0x0998
544 #define MMC_RXVLANFRAMES_GB_HI 0x099c
545 #define MMC_RXWATCHDOGERROR 0x09a0
547 /* MMC register entry bit positions and sizes */
548 #define MMC_CR_CR_INDEX 0
549 #define MMC_CR_CR_WIDTH 1
550 #define MMC_CR_CSR_INDEX 1
551 #define MMC_CR_CSR_WIDTH 1
552 #define MMC_CR_ROR_INDEX 2
553 #define MMC_CR_ROR_WIDTH 1
554 #define MMC_CR_MCF_INDEX 3
555 #define MMC_CR_MCF_WIDTH 1
556 #define MMC_CR_MCT_INDEX 4
557 #define MMC_CR_MCT_WIDTH 2
558 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0
559 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23
560 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0
561 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1
562 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1
563 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1
564 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2
565 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1
566 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3
567 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1
568 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4
569 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1
570 #define MMC_RISR_RXCRCERROR_INDEX 5
571 #define MMC_RISR_RXCRCERROR_WIDTH 1
572 #define MMC_RISR_RXRUNTERROR_INDEX 6
573 #define MMC_RISR_RXRUNTERROR_WIDTH 1
574 #define MMC_RISR_RXJABBERERROR_INDEX 7
575 #define MMC_RISR_RXJABBERERROR_WIDTH 1
576 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8
577 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1
578 #define MMC_RISR_RXOVERSIZE_G_INDEX 9
579 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1
580 #define MMC_RISR_RX64OCTETS_GB_INDEX 10
581 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1
582 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11
583 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1
584 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12
585 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1
586 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13
587 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1
588 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14
589 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1
590 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15
591 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1
592 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16
593 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1
594 #define MMC_RISR_RXLENGTHERROR_INDEX 17
595 #define MMC_RISR_RXLENGTHERROR_WIDTH 1
596 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18
597 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1
598 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19
599 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1
600 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20
601 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1
602 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21
603 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1
604 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22
605 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1
606 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0
607 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18
608 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0
609 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1
610 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1
611 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1
612 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2
613 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1
614 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3
615 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1
616 #define MMC_TISR_TX64OCTETS_GB_INDEX 4
617 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1
618 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5
619 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1
620 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6
621 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1
622 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7
623 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1
624 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8
625 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1
626 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9
627 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1
628 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10
629 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1
630 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11
631 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1
632 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12
633 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1
634 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13
635 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1
636 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14
637 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1
638 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15
639 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1
640 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16
641 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1
642 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17
643 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1
645 /* MTL register offsets */
646 #define MTL_OMR 0x1000
647 #define MTL_FDCR 0x1008
648 #define MTL_FDSR 0x100c
649 #define MTL_FDDR 0x1010
650 #define MTL_ISR 0x1020
651 #define MTL_RQDCM0R 0x1030
652 #define MTL_TCPM0R 0x1040
653 #define MTL_TCPM1R 0x1044
655 #define MTL_RQDCM_INC 4
656 #define MTL_RQDCM_Q_PER_REG 4
658 /* MTL register entry bit positions and sizes */
659 #define MTL_OMR_ETSALG_INDEX 5
660 #define MTL_OMR_ETSALG_WIDTH 2
661 #define MTL_OMR_RAA_INDEX 2
662 #define MTL_OMR_RAA_WIDTH 1
664 /* MTL queue register offsets
665 * Multiple queues can be active. The first queue has registers
666 * that begin at 0x1100. Each subsequent queue has registers that
667 * are accessed using an offset of 0x80 from the previous queue.
669 #define MTL_Q_BASE 0x1100
670 #define MTL_Q_INC 0x80
672 #define MTL_Q_TQOMR 0x00
673 #define MTL_Q_TQUR 0x04
674 #define MTL_Q_TQDR 0x08
675 #define MTL_Q_TCECR 0x10
676 #define MTL_Q_TCESR 0x14
677 #define MTL_Q_TCQWR 0x18
678 #define MTL_Q_RQOMR 0x40
679 #define MTL_Q_RQMPOCR 0x44
680 #define MTL_Q_RQDR 0x4c
681 #define MTL_Q_IER 0x70
682 #define MTL_Q_ISR 0x74
684 /* MTL queue register entry bit positions and sizes */
685 #define MTL_Q_TCQWR_QW_INDEX 0
686 #define MTL_Q_TCQWR_QW_WIDTH 21
687 #define MTL_Q_RQOMR_EHFC_INDEX 7
688 #define MTL_Q_RQOMR_EHFC_WIDTH 1
689 #define MTL_Q_RQOMR_RFA_INDEX 8
690 #define MTL_Q_RQOMR_RFA_WIDTH 3
691 #define MTL_Q_RQOMR_RFD_INDEX 13
692 #define MTL_Q_RQOMR_RFD_WIDTH 3
693 #define MTL_Q_RQOMR_RQS_INDEX 16
694 #define MTL_Q_RQOMR_RQS_WIDTH 9
695 #define MTL_Q_RQOMR_RSF_INDEX 5
696 #define MTL_Q_RQOMR_RSF_WIDTH 1
697 #define MTL_Q_RQOMR_RTC_INDEX 0
698 #define MTL_Q_RQOMR_RTC_WIDTH 2
699 #define MTL_Q_TQOMR_FTQ_INDEX 0
700 #define MTL_Q_TQOMR_FTQ_WIDTH 1
701 #define MTL_Q_TQOMR_TQS_INDEX 16
702 #define MTL_Q_TQOMR_TQS_WIDTH 10
703 #define MTL_Q_TQOMR_TSF_INDEX 1
704 #define MTL_Q_TQOMR_TSF_WIDTH 1
705 #define MTL_Q_TQOMR_TTC_INDEX 4
706 #define MTL_Q_TQOMR_TTC_WIDTH 3
707 #define MTL_Q_TQOMR_TXQEN_INDEX 2
708 #define MTL_Q_TQOMR_TXQEN_WIDTH 2
710 /* MTL queue register value */
711 #define MTL_RSF_DISABLE 0x00
712 #define MTL_RSF_ENABLE 0x01
713 #define MTL_TSF_DISABLE 0x00
714 #define MTL_TSF_ENABLE 0x01
716 #define MTL_RX_THRESHOLD_64 0x00
717 #define MTL_RX_THRESHOLD_96 0x02
718 #define MTL_RX_THRESHOLD_128 0x03
719 #define MTL_TX_THRESHOLD_32 0x01
720 #define MTL_TX_THRESHOLD_64 0x00
721 #define MTL_TX_THRESHOLD_96 0x02
722 #define MTL_TX_THRESHOLD_128 0x03
723 #define MTL_TX_THRESHOLD_192 0x04
724 #define MTL_TX_THRESHOLD_256 0x05
725 #define MTL_TX_THRESHOLD_384 0x06
726 #define MTL_TX_THRESHOLD_512 0x07
728 #define MTL_ETSALG_WRR 0x00
729 #define MTL_ETSALG_WFQ 0x01
730 #define MTL_ETSALG_DWRR 0x02
731 #define MTL_RAA_SP 0x00
732 #define MTL_RAA_WSP 0x01
734 #define MTL_Q_DISABLED 0x00
735 #define MTL_Q_ENABLED 0x02
738 /* MTL traffic class register offsets
739 * Multiple traffic classes can be active. The first class has registers
740 * that begin at 0x1100. Each subsequent queue has registers that
741 * are accessed using an offset of 0x80 from the previous queue.
743 #define MTL_TC_BASE MTL_Q_BASE
744 #define MTL_TC_INC MTL_Q_INC
746 #define MTL_TC_ETSCR 0x10
748 /* MTL traffic class register entry bit positions and sizes */
749 #define MTL_TC_ETSCR_TSA_INDEX 0
750 #define MTL_TC_ETSCR_TSA_WIDTH 2
752 /* MTL traffic class register value */
753 #define MTL_TSA_SP 0x00
754 #define MTL_TSA_ETS 0x02
757 /* PCS MMD select register offset
758 * The MMD select register is used for accessing PCS registers
759 * when the underlying APB3 interface is using indirect addressing.
760 * Indirect addressing requires accessing registers in two phases,
761 * an address phase and a data phase. The address phases requires
762 * writing an address selection value to the MMD select regiesters.
764 #define PCS_MMD_SELECT 0xff
767 /* Descriptor/Packet entry bit positions and sizes */
768 #define RX_PACKET_ERRORS_CRC_INDEX 2
769 #define RX_PACKET_ERRORS_CRC_WIDTH 1
770 #define RX_PACKET_ERRORS_FRAME_INDEX 3
771 #define RX_PACKET_ERRORS_FRAME_WIDTH 1
772 #define RX_PACKET_ERRORS_LENGTH_INDEX 0
773 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1
774 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1
775 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1
777 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0
778 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1
779 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1
780 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
781 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2
782 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1
784 #define RX_NORMAL_DESC0_OVT_INDEX 0
785 #define RX_NORMAL_DESC0_OVT_WIDTH 16
786 #define RX_NORMAL_DESC3_ES_INDEX 15
787 #define RX_NORMAL_DESC3_ES_WIDTH 1
788 #define RX_NORMAL_DESC3_ETLT_INDEX 16
789 #define RX_NORMAL_DESC3_ETLT_WIDTH 4
790 #define RX_NORMAL_DESC3_INTE_INDEX 30
791 #define RX_NORMAL_DESC3_INTE_WIDTH 1
792 #define RX_NORMAL_DESC3_LD_INDEX 28
793 #define RX_NORMAL_DESC3_LD_WIDTH 1
794 #define RX_NORMAL_DESC3_OWN_INDEX 31
795 #define RX_NORMAL_DESC3_OWN_WIDTH 1
796 #define RX_NORMAL_DESC3_PL_INDEX 0
797 #define RX_NORMAL_DESC3_PL_WIDTH 14
799 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
800 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1
801 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1
802 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1
803 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2
804 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
806 #define TX_CONTEXT_DESC2_MSS_INDEX 0
807 #define TX_CONTEXT_DESC2_MSS_WIDTH 15
808 #define TX_CONTEXT_DESC3_CTXT_INDEX 30
809 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1
810 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26
811 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1
812 #define TX_CONTEXT_DESC3_VLTV_INDEX 16
813 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1
814 #define TX_CONTEXT_DESC3_VT_INDEX 0
815 #define TX_CONTEXT_DESC3_VT_WIDTH 16
817 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0
818 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14
819 #define TX_NORMAL_DESC2_IC_INDEX 31
820 #define TX_NORMAL_DESC2_IC_WIDTH 1
821 #define TX_NORMAL_DESC2_VTIR_INDEX 14
822 #define TX_NORMAL_DESC2_VTIR_WIDTH 2
823 #define TX_NORMAL_DESC3_CIC_INDEX 16
824 #define TX_NORMAL_DESC3_CIC_WIDTH 2
825 #define TX_NORMAL_DESC3_CPC_INDEX 26
826 #define TX_NORMAL_DESC3_CPC_WIDTH 2
827 #define TX_NORMAL_DESC3_CTXT_INDEX 30
828 #define TX_NORMAL_DESC3_CTXT_WIDTH 1
829 #define TX_NORMAL_DESC3_FD_INDEX 29
830 #define TX_NORMAL_DESC3_FD_WIDTH 1
831 #define TX_NORMAL_DESC3_FL_INDEX 0
832 #define TX_NORMAL_DESC3_FL_WIDTH 15
833 #define TX_NORMAL_DESC3_LD_INDEX 28
834 #define TX_NORMAL_DESC3_LD_WIDTH 1
835 #define TX_NORMAL_DESC3_OWN_INDEX 31
836 #define TX_NORMAL_DESC3_OWN_WIDTH 1
837 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19
838 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4
839 #define TX_NORMAL_DESC3_TCPPL_INDEX 0
840 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18
841 #define TX_NORMAL_DESC3_TSE_INDEX 18
842 #define TX_NORMAL_DESC3_TSE_WIDTH 1
844 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2
846 /* MDIO undefined or vendor specific registers */
847 #ifndef MDIO_AN_COMP_STAT
848 #define MDIO_AN_COMP_STAT 0x0030
852 /* Bit setting and getting macros
853 * The get macro will extract the current bit field value from within
856 * The set macro will clear the current bit field value within the
857 * variable and then set the bit field of the variable to the
860 #define GET_BITS(_var, _index, _width) \
861 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
863 #define SET_BITS(_var, _index, _width, _val) \
865 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
866 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
869 #define GET_BITS_LE(_var, _index, _width) \
870 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
872 #define SET_BITS_LE(_var, _index, _width, _val) \
874 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \
875 (_var) |= cpu_to_le32((((_val) & \
876 ((0x1 << (_width)) - 1)) << (_index))); \
880 /* Bit setting and getting macros based on register fields
881 * The get macro uses the bit field definitions formed using the input
882 * names to extract the current bit field value from within the
885 * The set macro uses the bit field definitions formed using the input
886 * names to set the bit field of the variable to the specified value
888 #define XGMAC_GET_BITS(_var, _prefix, _field) \
890 _prefix##_##_field##_INDEX, \
891 _prefix##_##_field##_WIDTH)
893 #define XGMAC_SET_BITS(_var, _prefix, _field, _val) \
895 _prefix##_##_field##_INDEX, \
896 _prefix##_##_field##_WIDTH, (_val))
898 #define XGMAC_GET_BITS_LE(_var, _prefix, _field) \
899 GET_BITS_LE((_var), \
900 _prefix##_##_field##_INDEX, \
901 _prefix##_##_field##_WIDTH)
903 #define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \
904 SET_BITS_LE((_var), \
905 _prefix##_##_field##_INDEX, \
906 _prefix##_##_field##_WIDTH, (_val))
909 /* Macros for reading or writing registers
910 * The ioread macros will get bit fields or full values using the
911 * register definitions formed using the input names
913 * The iowrite macros will set bit fields or full values using the
914 * register definitions formed using the input names
916 #define XGMAC_IOREAD(_pdata, _reg) \
917 ioread32((_pdata)->xgmac_regs + _reg)
919 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \
920 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \
921 _reg##_##_field##_INDEX, \
922 _reg##_##_field##_WIDTH)
924 #define XGMAC_IOWRITE(_pdata, _reg, _val) \
925 iowrite32((_val), (_pdata)->xgmac_regs + _reg)
927 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
929 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \
931 _reg##_##_field##_INDEX, \
932 _reg##_##_field##_WIDTH, (_val)); \
933 XGMAC_IOWRITE((_pdata), _reg, reg_val); \
937 /* Macros for reading or writing MTL queue or traffic class registers
938 * Similar to the standard read and write macros except that the
939 * base register value is calculated by the queue or traffic class number
941 #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \
942 ioread32((_pdata)->xgmac_regs + \
943 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)
945 #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \
946 GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \
947 _reg##_##_field##_INDEX, \
948 _reg##_##_field##_WIDTH)
950 #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
951 iowrite32((_val), (_pdata)->xgmac_regs + \
952 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)
954 #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
956 u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \
958 _reg##_##_field##_INDEX, \
959 _reg##_##_field##_WIDTH, (_val)); \
960 XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \
964 /* Macros for reading or writing DMA channel registers
965 * Similar to the standard read and write macros except that the
966 * base register value is obtained from the ring
968 #define XGMAC_DMA_IOREAD(_channel, _reg) \
969 ioread32((_channel)->dma_regs + _reg)
971 #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
972 GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \
973 _reg##_##_field##_INDEX, \
974 _reg##_##_field##_WIDTH)
976 #define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \
977 iowrite32((_val), (_channel)->dma_regs + _reg)
979 #define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
981 u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \
983 _reg##_##_field##_INDEX, \
984 _reg##_##_field##_WIDTH, (_val)); \
985 XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \
989 /* Macros for building, reading or writing register values or bits
990 * within the register values of XPCS registers.
992 #define XPCS_IOWRITE(_pdata, _off, _val) \
993 iowrite32(_val, (_pdata)->xpcs_regs + (_off))
995 #define XPCS_IOREAD(_pdata, _off) \
996 ioread32((_pdata)->xpcs_regs + (_off))
999 /* Macros for building, reading or writing register values or bits
1000 * using MDIO. Different from above because of the use of standardized
1001 * Linux include values. No shifting is performed with the bit
1002 * operations, everything works on mask values.
1004 #define XMDIO_READ(_pdata, _mmd, _reg) \
1005 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \
1006 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff)))
1008 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \
1009 (XMDIO_READ((_pdata), _mmd, _reg) & _mask)
1011 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \
1012 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \
1013 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val)))
1015 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \
1017 u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \
1018 mmd_val &= ~_mask; \
1019 mmd_val |= (_val); \
1020 XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \