2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
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63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
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68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
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71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/phy.h>
118 #include <linux/clk.h>
119 #include <linux/bitrev.h>
120 #include <linux/crc32.h>
123 #include "xgbe-common.h"
126 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
132 DBGPR("-->xgbe_usec_to_riwt\n");
134 rate = clk_get_rate(pdata->sysclk);
137 * Convert the input usec value to the watchdog timer value. Each
138 * watchdog timer value is equivalent to 256 clock cycles.
139 * Calculate the required value as:
140 * ( usec * ( system_clock_mhz / 10^6 ) / 256
142 ret = (usec * (rate / 1000000)) / 256;
144 DBGPR("<--xgbe_usec_to_riwt\n");
149 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
155 DBGPR("-->xgbe_riwt_to_usec\n");
157 rate = clk_get_rate(pdata->sysclk);
160 * Convert the input watchdog timer value to the usec value. Each
161 * watchdog timer value is equivalent to 256 clock cycles.
162 * Calculate the required value as:
163 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
165 ret = (riwt * 256) / (rate / 1000000);
167 DBGPR("<--xgbe_riwt_to_usec\n");
172 static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)
174 struct xgbe_channel *channel;
177 channel = pdata->channel;
178 for (i = 0; i < pdata->channel_count; i++, channel++)
179 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8,
185 static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)
187 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL);
190 static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)
192 struct xgbe_channel *channel;
195 channel = pdata->channel;
196 for (i = 0; i < pdata->channel_count; i++, channel++) {
197 if (!channel->tx_ring)
200 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL,
207 static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)
209 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL);
212 static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)
214 struct xgbe_channel *channel;
217 channel = pdata->channel;
218 for (i = 0; i < pdata->channel_count; i++, channel++) {
219 if (!channel->rx_ring)
222 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL,
229 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
231 struct xgbe_channel *channel;
234 channel = pdata->channel;
235 for (i = 0; i < pdata->channel_count; i++, channel++) {
236 if (!channel->tx_ring)
239 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP,
246 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
250 for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++)
251 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
256 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
260 for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++)
261 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
266 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
271 for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++)
272 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
277 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
282 for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++)
283 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
288 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
290 struct xgbe_channel *channel;
293 channel = pdata->channel;
294 for (i = 0; i < pdata->channel_count; i++, channel++) {
295 if (!channel->rx_ring)
298 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT,
305 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
310 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
312 struct xgbe_channel *channel;
315 channel = pdata->channel;
316 for (i = 0; i < pdata->channel_count; i++, channel++) {
317 if (!channel->rx_ring)
320 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ,
325 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
327 struct xgbe_channel *channel;
330 channel = pdata->channel;
331 for (i = 0; i < pdata->channel_count; i++, channel++) {
332 if (!channel->tx_ring)
335 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1);
339 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
341 unsigned int max_q_count, q_count;
342 unsigned int reg, reg_val;
345 /* Clear MTL flow control */
346 for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++)
347 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
349 /* Clear MAC flow control */
350 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
351 q_count = min_t(unsigned int, pdata->hw_feat.rx_q_cnt, max_q_count);
353 for (i = 0; i < q_count; i++) {
354 reg_val = XGMAC_IOREAD(pdata, reg);
355 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
356 XGMAC_IOWRITE(pdata, reg, reg_val);
358 reg += MAC_QTFCR_INC;
364 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
366 unsigned int max_q_count, q_count;
367 unsigned int reg, reg_val;
370 /* Set MTL flow control */
371 for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++)
372 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1);
374 /* Set MAC flow control */
375 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
376 q_count = min_t(unsigned int, pdata->hw_feat.rx_q_cnt, max_q_count);
378 for (i = 0; i < q_count; i++) {
379 reg_val = XGMAC_IOREAD(pdata, reg);
381 /* Enable transmit flow control */
382 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
384 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
386 XGMAC_IOWRITE(pdata, reg, reg_val);
388 reg += MAC_QTFCR_INC;
394 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
396 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
401 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
403 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
408 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
411 xgbe_enable_tx_flow_control(pdata);
413 xgbe_disable_tx_flow_control(pdata);
418 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
421 xgbe_enable_rx_flow_control(pdata);
423 xgbe_disable_rx_flow_control(pdata);
428 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
430 xgbe_config_tx_flow_control(pdata);
431 xgbe_config_rx_flow_control(pdata);
434 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
436 struct xgbe_channel *channel;
437 unsigned int dma_ch_isr, dma_ch_ier;
440 channel = pdata->channel;
441 for (i = 0; i < pdata->channel_count; i++, channel++) {
442 /* Clear all the interrupts which are set */
443 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
444 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
446 /* Clear all interrupt enable bits */
449 /* Enable following interrupts
450 * NIE - Normal Interrupt Summary Enable
451 * AIE - Abnormal Interrupt Summary Enable
452 * FBEE - Fatal Bus Error Enable
454 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1);
455 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1);
456 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
458 if (channel->tx_ring) {
459 /* Enable the following Tx interrupts
460 * TIE - Transmit Interrupt Enable (unless polling)
462 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
464 if (channel->rx_ring) {
465 /* Enable following Rx interrupts
466 * RBUE - Receive Buffer Unavailable Enable
467 * RIE - Receive Interrupt Enable
469 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
470 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
473 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
477 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
479 unsigned int mtl_q_isr;
480 unsigned int q_count, i;
482 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
483 for (i = 0; i < q_count; i++) {
484 /* Clear all the interrupts which are set */
485 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
486 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
488 /* No MTL interrupts to be enabled */
489 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
493 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
495 unsigned int mac_ier = 0;
497 /* Enable Timestamp interrupt */
498 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
500 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
502 /* Enable all counter interrupts */
503 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xff);
504 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xff);
507 static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata)
509 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3);
514 static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata)
516 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2);
521 static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata)
523 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0);
528 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
531 unsigned int val = enable ? 1 : 0;
533 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
536 DBGPR(" %s promiscuous mode\n", enable ? "entering" : "leaving");
537 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
542 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
545 unsigned int val = enable ? 1 : 0;
547 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
550 DBGPR(" %s allmulti mode\n", enable ? "entering" : "leaving");
551 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
556 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
557 struct netdev_hw_addr *ha, unsigned int *mac_reg)
559 unsigned int mac_addr_hi, mac_addr_lo;
566 mac_addr = (u8 *)&mac_addr_lo;
567 mac_addr[0] = ha->addr[0];
568 mac_addr[1] = ha->addr[1];
569 mac_addr[2] = ha->addr[2];
570 mac_addr[3] = ha->addr[3];
571 mac_addr = (u8 *)&mac_addr_hi;
572 mac_addr[0] = ha->addr[4];
573 mac_addr[1] = ha->addr[5];
575 DBGPR(" adding mac address %pM at 0x%04x\n", ha->addr,
578 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
581 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
582 *mac_reg += MAC_MACA_INC;
583 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
584 *mac_reg += MAC_MACA_INC;
587 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
589 struct net_device *netdev = pdata->netdev;
590 struct netdev_hw_addr *ha;
591 unsigned int mac_reg;
592 unsigned int addn_macs;
594 mac_reg = MAC_MACA1HR;
595 addn_macs = pdata->hw_feat.addn_mac;
597 if (netdev_uc_count(netdev) > addn_macs) {
598 xgbe_set_promiscuous_mode(pdata, 1);
600 netdev_for_each_uc_addr(ha, netdev) {
601 xgbe_set_mac_reg(pdata, ha, &mac_reg);
605 if (netdev_mc_count(netdev) > addn_macs) {
606 xgbe_set_all_multicast_mode(pdata, 1);
608 netdev_for_each_mc_addr(ha, netdev) {
609 xgbe_set_mac_reg(pdata, ha, &mac_reg);
615 /* Clear remaining additional MAC address entries */
617 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
620 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
622 struct net_device *netdev = pdata->netdev;
623 struct netdev_hw_addr *ha;
624 unsigned int hash_reg;
625 unsigned int hash_table_shift, hash_table_count;
626 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
630 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
631 hash_table_count = pdata->hw_feat.hash_table_size / 32;
632 memset(hash_table, 0, sizeof(hash_table));
634 /* Build the MAC Hash Table register values */
635 netdev_for_each_uc_addr(ha, netdev) {
636 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
637 crc >>= hash_table_shift;
638 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
641 netdev_for_each_mc_addr(ha, netdev) {
642 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
643 crc >>= hash_table_shift;
644 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
647 /* Set the MAC Hash Table registers */
649 for (i = 0; i < hash_table_count; i++) {
650 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
651 hash_reg += MAC_HTR_INC;
655 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
657 if (pdata->hw_feat.hash_table_size)
658 xgbe_set_mac_hash_table(pdata);
660 xgbe_set_mac_addn_addrs(pdata);
665 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
667 unsigned int mac_addr_hi, mac_addr_lo;
669 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
670 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
671 (addr[1] << 8) | (addr[0] << 0);
673 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
674 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
679 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
682 unsigned int mmd_address;
685 if (mmd_reg & MII_ADDR_C45)
686 mmd_address = mmd_reg & ~MII_ADDR_C45;
688 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
690 /* The PCS registers are accessed using mmio. The underlying APB3
691 * management interface uses indirect addressing to access the MMD
692 * register sets. This requires accessing of the PCS register in two
693 * phases, an address phase and a data phase.
695 * The mmio interface is based on 32-bit offsets and values. All
696 * register offsets must therefore be adjusted by left shifting the
697 * offset 2 bits and reading 32 bits of data.
699 mutex_lock(&pdata->xpcs_mutex);
700 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
701 mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2);
702 mutex_unlock(&pdata->xpcs_mutex);
707 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
708 int mmd_reg, int mmd_data)
710 unsigned int mmd_address;
712 if (mmd_reg & MII_ADDR_C45)
713 mmd_address = mmd_reg & ~MII_ADDR_C45;
715 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
717 /* The PCS registers are accessed using mmio. The underlying APB3
718 * management interface uses indirect addressing to access the MMD
719 * register sets. This requires accessing of the PCS register in two
720 * phases, an address phase and a data phase.
722 * The mmio interface is based on 32-bit offsets and values. All
723 * register offsets must therefore be adjusted by left shifting the
724 * offset 2 bits and reading 32 bits of data.
726 mutex_lock(&pdata->xpcs_mutex);
727 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
728 XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
729 mutex_unlock(&pdata->xpcs_mutex);
732 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
734 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
737 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
739 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
744 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
746 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
751 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
753 /* Put the VLAN tag in the Rx descriptor */
754 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
756 /* Don't check the VLAN type */
757 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
759 /* Check only C-TAG (0x8100) packets */
760 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
762 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
763 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
765 /* Enable VLAN tag stripping */
766 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
771 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
773 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
778 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
780 /* Enable VLAN filtering */
781 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
783 /* Enable VLAN Hash Table filtering */
784 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
786 /* Disable VLAN tag inverse matching */
787 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
789 /* Only filter on the lower 12-bits of the VLAN tag */
790 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
792 /* In order for the VLAN Hash Table filtering to be effective,
793 * the VLAN tag identifier in the VLAN Tag Register must not
794 * be zero. Set the VLAN tag identifier to "1" to enable the
795 * VLAN Hash Table filtering. This implies that a VLAN tag of
796 * 1 will always pass filtering.
798 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
803 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
805 /* Disable VLAN filtering */
806 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
812 #define CRCPOLY_LE 0xedb88320
814 static u32 xgbe_vid_crc32_le(__le16 vid_le)
816 u32 poly = CRCPOLY_LE;
819 unsigned char *data = (unsigned char *)&vid_le;
820 unsigned char data_byte = 0;
823 bits = get_bitmask_order(VLAN_VID_MASK);
824 for (i = 0; i < bits; i++) {
826 data_byte = data[i / 8];
828 temp = ((crc & 1) ^ data_byte) & 1;
839 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
844 u16 vlan_hash_table = 0;
846 /* Generate the VLAN Hash Table value */
847 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
848 /* Get the CRC32 value of the VLAN ID */
849 vid_le = cpu_to_le16(vid);
850 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
852 vlan_hash_table |= (1 << crc);
855 /* Set the VLAN Hash Table filtering register */
856 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
861 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
863 struct xgbe_ring_desc *rdesc = rdata->rdesc;
865 /* Reset the Tx descriptor
866 * Set buffer 1 (lo) address to zero
867 * Set buffer 1 (hi) address to zero
868 * Reset all other control bits (IC, TTSE, B2L & B1L)
869 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
877 static void xgbe_tx_desc_init(struct xgbe_channel *channel)
879 struct xgbe_ring *ring = channel->tx_ring;
880 struct xgbe_ring_data *rdata;
881 struct xgbe_ring_desc *rdesc;
883 int start_index = ring->cur;
885 DBGPR("-->tx_desc_init\n");
887 /* Initialze all descriptors */
888 for (i = 0; i < ring->rdesc_count; i++) {
889 rdata = XGBE_GET_DESC_DATA(ring, i);
890 rdesc = rdata->rdesc;
892 /* Initialize Tx descriptor
893 * Set buffer 1 (lo) address to zero
894 * Set buffer 1 (hi) address to zero
895 * Reset all other control bits (IC, TTSE, B2L & B1L)
896 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC,
905 /* Make sure everything is written to the descriptor(s) before
906 * telling the device about them
910 /* Update the total number of Tx descriptors */
911 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
913 /* Update the starting address of descriptor ring */
914 rdata = XGBE_GET_DESC_DATA(ring, start_index);
915 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
916 upper_32_bits(rdata->rdesc_dma));
917 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
918 lower_32_bits(rdata->rdesc_dma));
920 DBGPR("<--tx_desc_init\n");
923 static void xgbe_rx_desc_reset(struct xgbe_ring_data *rdata)
925 struct xgbe_ring_desc *rdesc = rdata->rdesc;
927 /* Reset the Rx descriptor
928 * Set buffer 1 (lo) address to dma address (lo)
929 * Set buffer 1 (hi) address to dma address (hi)
930 * Set buffer 2 (lo) address to zero
931 * Set buffer 2 (hi) address to zero and set control bits
934 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
935 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
939 if (rdata->interrupt)
940 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, 1);
942 /* Since the Rx DMA engine is likely running, make sure everything
943 * is written to the descriptor(s) before setting the OWN bit
948 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
950 /* Make sure ownership is written to the descriptor */
954 static void xgbe_rx_desc_init(struct xgbe_channel *channel)
956 struct xgbe_prv_data *pdata = channel->pdata;
957 struct xgbe_ring *ring = channel->rx_ring;
958 struct xgbe_ring_data *rdata;
959 struct xgbe_ring_desc *rdesc;
960 unsigned int start_index = ring->cur;
961 unsigned int rx_coalesce, rx_frames;
964 DBGPR("-->rx_desc_init\n");
966 rx_coalesce = (pdata->rx_riwt || pdata->rx_frames) ? 1 : 0;
967 rx_frames = pdata->rx_frames;
969 /* Initialize all descriptors */
970 for (i = 0; i < ring->rdesc_count; i++) {
971 rdata = XGBE_GET_DESC_DATA(ring, i);
972 rdesc = rdata->rdesc;
974 /* Initialize Rx descriptor
975 * Set buffer 1 (lo) address to dma address (lo)
976 * Set buffer 1 (hi) address to dma address (hi)
977 * Set buffer 2 (lo) address to zero
978 * Set buffer 2 (hi) address to zero and set control
979 * bits OWN and INTE appropriateley
981 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
982 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
985 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
986 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, 1);
987 rdata->interrupt = 1;
988 if (rx_coalesce && (!rx_frames || ((i + 1) % rx_frames))) {
989 /* Clear interrupt on completion bit */
990 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE,
992 rdata->interrupt = 0;
996 /* Make sure everything is written to the descriptors before
997 * telling the device about them
1001 /* Update the total number of Rx descriptors */
1002 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1004 /* Update the starting address of descriptor ring */
1005 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1006 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1007 upper_32_bits(rdata->rdesc_dma));
1008 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1009 lower_32_bits(rdata->rdesc_dma));
1011 /* Update the Rx Descriptor Tail Pointer */
1012 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
1013 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1014 lower_32_bits(rdata->rdesc_dma));
1016 DBGPR("<--rx_desc_init\n");
1019 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1020 unsigned int addend)
1022 /* Set the addend register value and tell the device */
1023 XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1024 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1026 /* Wait for addend update to complete */
1027 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1031 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1034 /* Set the time values and tell the device */
1035 XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1036 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1037 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1039 /* Wait for time update to complete */
1040 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1044 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1048 nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1049 nsec *= NSEC_PER_SEC;
1050 nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1055 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1057 unsigned int tx_snr;
1060 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1061 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
1064 nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
1065 nsec *= NSEC_PER_SEC;
1071 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1072 struct xgbe_ring_desc *rdesc)
1076 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
1077 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
1078 nsec = le32_to_cpu(rdesc->desc1);
1080 nsec |= le32_to_cpu(rdesc->desc0);
1081 if (nsec != 0xffffffffffffffffULL) {
1082 packet->rx_tstamp = nsec;
1083 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1089 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1090 unsigned int mac_tscr)
1092 /* Set one nano-second accuracy */
1093 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1095 /* Set fine timestamp update */
1096 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1098 /* Overwrite earlier timestamps */
1099 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1101 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1103 /* Exit if timestamping is not enabled */
1104 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
1107 /* Initialize time registers */
1108 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1109 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1110 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1111 xgbe_set_tstamp_time(pdata, 0, 0);
1113 /* Initialize the timecounter */
1114 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1115 ktime_to_ns(ktime_get_real()));
1120 static void xgbe_pre_xmit(struct xgbe_channel *channel)
1122 struct xgbe_prv_data *pdata = channel->pdata;
1123 struct xgbe_ring *ring = channel->tx_ring;
1124 struct xgbe_ring_data *rdata;
1125 struct xgbe_ring_desc *rdesc;
1126 struct xgbe_packet_data *packet = &ring->packet_data;
1127 unsigned int csum, tso, vlan;
1128 unsigned int tso_context, vlan_context;
1129 unsigned int tx_coalesce, tx_frames;
1130 int start_index = ring->cur;
1133 DBGPR("-->xgbe_pre_xmit\n");
1135 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1137 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1139 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1142 if (tso && (packet->mss != ring->tx.cur_mss))
1147 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
1152 tx_coalesce = (pdata->tx_usecs || pdata->tx_frames) ? 1 : 0;
1153 tx_frames = pdata->tx_frames;
1154 if (tx_coalesce && !channel->tx_timer_active)
1155 ring->coalesce_count = 0;
1157 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1158 rdesc = rdata->rdesc;
1160 /* Create a context descriptor if this is a TSO packet */
1161 if (tso_context || vlan_context) {
1163 DBGPR(" TSO context descriptor, mss=%u\n",
1166 /* Set the MSS size */
1167 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
1170 /* Mark it as a CONTEXT descriptor */
1171 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1174 /* Indicate this descriptor contains the MSS */
1175 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1178 ring->tx.cur_mss = packet->mss;
1182 DBGPR(" VLAN context descriptor, ctag=%u\n",
1185 /* Mark it as a CONTEXT descriptor */
1186 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1189 /* Set the VLAN tag */
1190 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1191 VT, packet->vlan_ctag);
1193 /* Indicate this descriptor contains the VLAN tag */
1194 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1197 ring->tx.cur_vlan_ctag = packet->vlan_ctag;
1201 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1202 rdesc = rdata->rdesc;
1205 /* Update buffer address (for TSO this is the header) */
1206 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1207 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1209 /* Update the buffer length */
1210 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1211 rdata->skb_dma_len);
1213 /* VLAN tag insertion check */
1215 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
1216 TX_NORMAL_DESC2_VLAN_INSERT);
1218 /* Timestamp enablement check */
1219 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1220 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
1222 /* Set IC bit based on Tx coalescing settings */
1223 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1224 if (tx_coalesce && (!tx_frames ||
1225 (++ring->coalesce_count % tx_frames)))
1227 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 0);
1229 /* Mark it as First Descriptor */
1230 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
1232 /* Mark it as a NORMAL descriptor */
1233 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1235 /* Set OWN bit if not the first descriptor */
1236 if (ring->cur != start_index)
1237 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1241 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
1242 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
1243 packet->tcp_payload_len);
1244 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
1245 packet->tcp_header_len / 4);
1247 /* Enable CRC and Pad Insertion */
1248 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
1250 /* Enable HW CSUM */
1252 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1255 /* Set the total length to be transmitted */
1256 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
1260 for (i = ring->cur - start_index + 1; i < packet->rdesc_count; i++) {
1262 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1263 rdesc = rdata->rdesc;
1265 /* Update buffer address */
1266 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1267 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1269 /* Update the buffer length */
1270 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1271 rdata->skb_dma_len);
1273 /* Set IC bit based on Tx coalescing settings */
1274 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1275 if (tx_coalesce && (!tx_frames ||
1276 (++ring->coalesce_count % tx_frames)))
1278 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 0);
1281 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1283 /* Mark it as NORMAL descriptor */
1284 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1286 /* Enable HW CSUM */
1288 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1292 /* Set LAST bit for the last descriptor */
1293 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
1295 /* In case the Tx DMA engine is running, make sure everything
1296 * is written to the descriptor(s) before setting the OWN bit
1297 * for the first descriptor
1301 /* Set OWN bit for the first descriptor */
1302 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1303 rdesc = rdata->rdesc;
1304 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1306 #ifdef XGMAC_ENABLE_TX_DESC_DUMP
1307 xgbe_dump_tx_desc(ring, start_index, packet->rdesc_count, 1);
1310 /* Make sure ownership is written to the descriptor */
1313 /* Issue a poll command to Tx DMA by writing address
1314 * of next immediate free descriptor */
1316 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1317 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1318 lower_32_bits(rdata->rdesc_dma));
1320 /* Start the Tx coalescing timer */
1321 if (tx_coalesce && !channel->tx_timer_active) {
1322 channel->tx_timer_active = 1;
1323 hrtimer_start(&channel->tx_timer,
1324 ktime_set(0, pdata->tx_usecs * NSEC_PER_USEC),
1328 DBGPR(" %s: descriptors %u to %u written\n",
1329 channel->name, start_index & (ring->rdesc_count - 1),
1330 (ring->cur - 1) & (ring->rdesc_count - 1));
1332 DBGPR("<--xgbe_pre_xmit\n");
1335 static int xgbe_dev_read(struct xgbe_channel *channel)
1337 struct xgbe_ring *ring = channel->rx_ring;
1338 struct xgbe_ring_data *rdata;
1339 struct xgbe_ring_desc *rdesc;
1340 struct xgbe_packet_data *packet = &ring->packet_data;
1341 struct net_device *netdev = channel->pdata->netdev;
1342 unsigned int err, etlt;
1344 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
1346 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1347 rdesc = rdata->rdesc;
1349 /* Check for data availability */
1350 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1353 #ifdef XGMAC_ENABLE_RX_DESC_DUMP
1354 xgbe_dump_rx_desc(ring, rdesc, ring->cur);
1357 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1358 /* Timestamp Context Descriptor */
1359 xgbe_get_rx_tstamp(packet, rdesc);
1361 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1363 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1368 /* Normal Descriptor, be sure Context Descriptor bit is off */
1369 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1371 /* Indicate if a Context Descriptor is next */
1372 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1373 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1376 /* Get the packet length */
1377 rdata->len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
1379 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
1380 /* Not all the data has been transferred for this packet */
1381 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1386 /* This is the last of the data for this packet */
1387 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1390 /* Set checksum done indicator as appropriate */
1391 if (channel->pdata->netdev->features & NETIF_F_RXCSUM)
1392 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1395 /* Check for errors (only valid in last descriptor) */
1396 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
1397 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
1398 DBGPR(" err=%u, etlt=%#x\n", err, etlt);
1400 if (!err || (err && !etlt)) {
1401 if ((etlt == 0x09) &&
1402 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1403 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1405 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
1408 DBGPR(" vlan-ctag=0x%04x\n", packet->vlan_ctag);
1411 if ((etlt == 0x05) || (etlt == 0x06))
1412 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1415 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
1419 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
1420 ring->cur & (ring->rdesc_count - 1), ring->cur);
1425 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
1427 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
1428 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
1431 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
1433 /* Rx and Tx share LD bit, so check TDES3.LD bit */
1434 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
1437 static int xgbe_enable_int(struct xgbe_channel *channel,
1438 enum xgbe_int int_id)
1440 unsigned int dma_ch_ier;
1442 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1445 case XGMAC_INT_DMA_CH_SR_TI:
1446 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1448 case XGMAC_INT_DMA_CH_SR_TPS:
1449 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1);
1451 case XGMAC_INT_DMA_CH_SR_TBU:
1452 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1);
1454 case XGMAC_INT_DMA_CH_SR_RI:
1455 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1457 case XGMAC_INT_DMA_CH_SR_RBU:
1458 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
1460 case XGMAC_INT_DMA_CH_SR_RPS:
1461 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1);
1463 case XGMAC_INT_DMA_CH_SR_TI_RI:
1464 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1465 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1467 case XGMAC_INT_DMA_CH_SR_FBE:
1468 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
1470 case XGMAC_INT_DMA_ALL:
1471 dma_ch_ier |= channel->saved_ier;
1477 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1482 static int xgbe_disable_int(struct xgbe_channel *channel,
1483 enum xgbe_int int_id)
1485 unsigned int dma_ch_ier;
1487 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1490 case XGMAC_INT_DMA_CH_SR_TI:
1491 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1493 case XGMAC_INT_DMA_CH_SR_TPS:
1494 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0);
1496 case XGMAC_INT_DMA_CH_SR_TBU:
1497 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0);
1499 case XGMAC_INT_DMA_CH_SR_RI:
1500 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1502 case XGMAC_INT_DMA_CH_SR_RBU:
1503 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0);
1505 case XGMAC_INT_DMA_CH_SR_RPS:
1506 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0);
1508 case XGMAC_INT_DMA_CH_SR_TI_RI:
1509 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1510 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1512 case XGMAC_INT_DMA_CH_SR_FBE:
1513 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0);
1515 case XGMAC_INT_DMA_ALL:
1516 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK;
1517 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK;
1523 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1528 static int xgbe_exit(struct xgbe_prv_data *pdata)
1530 unsigned int count = 2000;
1532 DBGPR("-->xgbe_exit\n");
1534 /* Issue a software reset */
1535 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
1536 usleep_range(10, 15);
1538 /* Poll Until Poll Condition */
1539 while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
1540 usleep_range(500, 600);
1545 DBGPR("<--xgbe_exit\n");
1550 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
1552 unsigned int i, count;
1554 for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++)
1555 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
1557 /* Poll Until Poll Condition */
1558 for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++) {
1560 while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i,
1562 usleep_range(500, 600);
1571 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
1573 /* Set enhanced addressing mode */
1574 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);
1576 /* Set the System Bus mode */
1577 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
1578 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);
1581 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
1583 unsigned int arcache, awcache;
1586 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);
1587 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);
1588 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);
1589 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);
1590 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);
1591 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);
1592 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
1595 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);
1596 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);
1597 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);
1598 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);
1599 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);
1600 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);
1601 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);
1602 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);
1603 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
1606 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
1610 /* Set Tx to weighted round robin scheduling algorithm (when
1611 * traffic class is using ETS algorithm)
1613 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
1615 /* Set Tx traffic classes to strict priority algorithm */
1616 for (i = 0; i < XGBE_TC_CNT; i++)
1617 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, MTL_TSA_SP);
1619 /* Set Rx to strict priority algorithm */
1620 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
1623 static unsigned int xgbe_calculate_per_queue_fifo(unsigned long fifo_size,
1624 unsigned char queue_count)
1626 unsigned int q_fifo_size = 0;
1627 enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1629 /* Calculate Tx/Rx fifo share per queue */
1630 switch (fifo_size) {
1632 q_fifo_size = XGBE_FIFO_SIZE_B(128);
1635 q_fifo_size = XGBE_FIFO_SIZE_B(256);
1638 q_fifo_size = XGBE_FIFO_SIZE_B(512);
1641 q_fifo_size = XGBE_FIFO_SIZE_KB(1);
1644 q_fifo_size = XGBE_FIFO_SIZE_KB(2);
1647 q_fifo_size = XGBE_FIFO_SIZE_KB(4);
1650 q_fifo_size = XGBE_FIFO_SIZE_KB(8);
1653 q_fifo_size = XGBE_FIFO_SIZE_KB(16);
1656 q_fifo_size = XGBE_FIFO_SIZE_KB(32);
1659 q_fifo_size = XGBE_FIFO_SIZE_KB(64);
1662 q_fifo_size = XGBE_FIFO_SIZE_KB(128);
1665 q_fifo_size = XGBE_FIFO_SIZE_KB(256);
1668 q_fifo_size = q_fifo_size / queue_count;
1670 /* Set the queue fifo size programmable value */
1671 if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256))
1672 p_fifo = XGMAC_MTL_FIFO_SIZE_256K;
1673 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128))
1674 p_fifo = XGMAC_MTL_FIFO_SIZE_128K;
1675 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64))
1676 p_fifo = XGMAC_MTL_FIFO_SIZE_64K;
1677 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32))
1678 p_fifo = XGMAC_MTL_FIFO_SIZE_32K;
1679 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16))
1680 p_fifo = XGMAC_MTL_FIFO_SIZE_16K;
1681 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8))
1682 p_fifo = XGMAC_MTL_FIFO_SIZE_8K;
1683 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4))
1684 p_fifo = XGMAC_MTL_FIFO_SIZE_4K;
1685 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2))
1686 p_fifo = XGMAC_MTL_FIFO_SIZE_2K;
1687 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1))
1688 p_fifo = XGMAC_MTL_FIFO_SIZE_1K;
1689 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512))
1690 p_fifo = XGMAC_MTL_FIFO_SIZE_512;
1691 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256))
1692 p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1697 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
1699 enum xgbe_mtl_fifo_size fifo_size;
1702 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size,
1703 pdata->hw_feat.tx_q_cnt);
1705 for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++)
1706 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size);
1708 netdev_notice(pdata->netdev, "%d Tx queues, %d byte fifo per queue\n",
1709 pdata->hw_feat.tx_q_cnt, ((fifo_size + 1) * 256));
1712 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
1714 enum xgbe_mtl_fifo_size fifo_size;
1717 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size,
1718 pdata->hw_feat.rx_q_cnt);
1720 for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++)
1721 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size);
1723 netdev_notice(pdata->netdev, "%d Rx queues, %d byte fifo per queue\n",
1724 pdata->hw_feat.rx_q_cnt, ((fifo_size + 1) * 256));
1727 static void xgbe_config_rx_queue_mapping(struct xgbe_prv_data *pdata)
1729 unsigned int i, reg, reg_val;
1730 unsigned int q_count = pdata->hw_feat.rx_q_cnt;
1732 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
1735 for (i = 0; i < q_count;) {
1736 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
1738 if ((i % MTL_RQDCM_Q_PER_REG) && (i != q_count))
1741 XGMAC_IOWRITE(pdata, reg, reg_val);
1743 reg += MTL_RQDCM_INC;
1748 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
1752 for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++) {
1753 /* Activate flow control when less than 4k left in fifo */
1754 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFA, 2);
1756 /* De-activate flow control when more than 6k left in fifo */
1757 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFD, 4);
1761 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
1763 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
1765 /* Filtering is done using perfect filtering and hash filtering */
1766 if (pdata->hw_feat.hash_table_size) {
1767 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
1768 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
1769 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
1773 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
1777 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
1779 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
1782 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
1784 if (pdata->netdev->features & NETIF_F_RXCSUM)
1785 xgbe_enable_rx_csum(pdata);
1787 xgbe_disable_rx_csum(pdata);
1790 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
1792 /* Indicate that VLAN Tx CTAGs come from context descriptors */
1793 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
1794 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
1796 /* Set the current VLAN Hash Table register value */
1797 xgbe_update_vlan_hash_table(pdata);
1799 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
1800 xgbe_enable_rx_vlan_filtering(pdata);
1802 xgbe_disable_rx_vlan_filtering(pdata);
1804 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
1805 xgbe_enable_rx_vlan_stripping(pdata);
1807 xgbe_disable_rx_vlan_stripping(pdata);
1810 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
1812 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1813 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
1815 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
1816 stats->txoctetcount_gb +=
1817 XGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO);
1819 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
1820 stats->txframecount_gb +=
1821 XGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO);
1823 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
1824 stats->txbroadcastframes_g +=
1825 XGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO);
1827 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
1828 stats->txmulticastframes_g +=
1829 XGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO);
1831 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
1832 stats->tx64octets_gb +=
1833 XGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO);
1835 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
1836 stats->tx65to127octets_gb +=
1837 XGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO);
1839 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
1840 stats->tx128to255octets_gb +=
1841 XGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO);
1843 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
1844 stats->tx256to511octets_gb +=
1845 XGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO);
1847 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
1848 stats->tx512to1023octets_gb +=
1849 XGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO);
1851 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
1852 stats->tx1024tomaxoctets_gb +=
1853 XGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
1855 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
1856 stats->txunicastframes_gb +=
1857 XGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO);
1859 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
1860 stats->txmulticastframes_gb +=
1861 XGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
1863 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
1864 stats->txbroadcastframes_g +=
1865 XGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
1867 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
1868 stats->txunderflowerror +=
1869 XGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO);
1871 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
1872 stats->txoctetcount_g +=
1873 XGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO);
1875 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
1876 stats->txframecount_g +=
1877 XGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO);
1879 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
1880 stats->txpauseframes +=
1881 XGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO);
1883 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
1884 stats->txvlanframes_g +=
1885 XGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO);
1888 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
1890 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1891 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
1893 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
1894 stats->rxframecount_gb +=
1895 XGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO);
1897 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
1898 stats->rxoctetcount_gb +=
1899 XGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO);
1901 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
1902 stats->rxoctetcount_g +=
1903 XGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO);
1905 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
1906 stats->rxbroadcastframes_g +=
1907 XGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO);
1909 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
1910 stats->rxmulticastframes_g +=
1911 XGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO);
1913 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
1914 stats->rxcrcerror +=
1915 XGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO);
1917 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
1918 stats->rxrunterror +=
1919 XGMAC_IOREAD(pdata, MMC_RXRUNTERROR);
1921 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
1922 stats->rxjabbererror +=
1923 XGMAC_IOREAD(pdata, MMC_RXJABBERERROR);
1925 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
1926 stats->rxundersize_g +=
1927 XGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G);
1929 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
1930 stats->rxoversize_g +=
1931 XGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G);
1933 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
1934 stats->rx64octets_gb +=
1935 XGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO);
1937 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
1938 stats->rx65to127octets_gb +=
1939 XGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO);
1941 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
1942 stats->rx128to255octets_gb +=
1943 XGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO);
1945 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
1946 stats->rx256to511octets_gb +=
1947 XGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO);
1949 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
1950 stats->rx512to1023octets_gb +=
1951 XGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO);
1953 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
1954 stats->rx1024tomaxoctets_gb +=
1955 XGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
1957 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
1958 stats->rxunicastframes_g +=
1959 XGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO);
1961 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
1962 stats->rxlengtherror +=
1963 XGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO);
1965 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
1966 stats->rxoutofrangetype +=
1967 XGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO);
1969 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
1970 stats->rxpauseframes +=
1971 XGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO);
1973 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
1974 stats->rxfifooverflow +=
1975 XGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO);
1977 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
1978 stats->rxvlanframes_gb +=
1979 XGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO);
1981 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
1982 stats->rxwatchdogerror +=
1983 XGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR);
1986 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
1988 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1990 /* Freeze counters */
1991 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
1993 stats->txoctetcount_gb +=
1994 XGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO);
1996 stats->txframecount_gb +=
1997 XGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO);
1999 stats->txbroadcastframes_g +=
2000 XGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2002 stats->txmulticastframes_g +=
2003 XGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2005 stats->tx64octets_gb +=
2006 XGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO);
2008 stats->tx65to127octets_gb +=
2009 XGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO);
2011 stats->tx128to255octets_gb +=
2012 XGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO);
2014 stats->tx256to511octets_gb +=
2015 XGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO);
2017 stats->tx512to1023octets_gb +=
2018 XGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2020 stats->tx1024tomaxoctets_gb +=
2021 XGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2023 stats->txunicastframes_gb +=
2024 XGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2026 stats->txmulticastframes_gb +=
2027 XGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2029 stats->txbroadcastframes_g +=
2030 XGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2032 stats->txunderflowerror +=
2033 XGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO);
2035 stats->txoctetcount_g +=
2036 XGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO);
2038 stats->txframecount_g +=
2039 XGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO);
2041 stats->txpauseframes +=
2042 XGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO);
2044 stats->txvlanframes_g +=
2045 XGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO);
2047 stats->rxframecount_gb +=
2048 XGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO);
2050 stats->rxoctetcount_gb +=
2051 XGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO);
2053 stats->rxoctetcount_g +=
2054 XGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO);
2056 stats->rxbroadcastframes_g +=
2057 XGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2059 stats->rxmulticastframes_g +=
2060 XGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2062 stats->rxcrcerror +=
2063 XGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO);
2065 stats->rxrunterror +=
2066 XGMAC_IOREAD(pdata, MMC_RXRUNTERROR);
2068 stats->rxjabbererror +=
2069 XGMAC_IOREAD(pdata, MMC_RXJABBERERROR);
2071 stats->rxundersize_g +=
2072 XGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G);
2074 stats->rxoversize_g +=
2075 XGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G);
2077 stats->rx64octets_gb +=
2078 XGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO);
2080 stats->rx65to127octets_gb +=
2081 XGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO);
2083 stats->rx128to255octets_gb +=
2084 XGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO);
2086 stats->rx256to511octets_gb +=
2087 XGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO);
2089 stats->rx512to1023octets_gb +=
2090 XGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2092 stats->rx1024tomaxoctets_gb +=
2093 XGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2095 stats->rxunicastframes_g +=
2096 XGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO);
2098 stats->rxlengtherror +=
2099 XGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO);
2101 stats->rxoutofrangetype +=
2102 XGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO);
2104 stats->rxpauseframes +=
2105 XGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO);
2107 stats->rxfifooverflow +=
2108 XGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO);
2110 stats->rxvlanframes_gb +=
2111 XGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO);
2113 stats->rxwatchdogerror +=
2114 XGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR);
2116 /* Un-freeze counters */
2117 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
2120 static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
2122 /* Set counters to reset on read */
2123 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
2125 /* Reset the counters */
2126 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
2129 static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
2131 struct xgbe_channel *channel;
2134 /* Enable each Tx DMA channel */
2135 channel = pdata->channel;
2136 for (i = 0; i < pdata->channel_count; i++, channel++) {
2137 if (!channel->tx_ring)
2140 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2143 /* Enable each Tx queue */
2144 for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++)
2145 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
2149 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2152 static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
2154 struct xgbe_channel *channel;
2157 /* Disable MAC Tx */
2158 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2160 /* Disable each Tx queue */
2161 for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++)
2162 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
2164 /* Disable each Tx DMA channel */
2165 channel = pdata->channel;
2166 for (i = 0; i < pdata->channel_count; i++, channel++) {
2167 if (!channel->tx_ring)
2170 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2174 static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
2176 struct xgbe_channel *channel;
2177 unsigned int reg_val, i;
2179 /* Enable each Rx DMA channel */
2180 channel = pdata->channel;
2181 for (i = 0; i < pdata->channel_count; i++, channel++) {
2182 if (!channel->rx_ring)
2185 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2188 /* Enable each Rx queue */
2190 for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++)
2191 reg_val |= (0x02 << (i << 1));
2192 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
2195 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
2196 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
2197 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
2198 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
2201 static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
2203 struct xgbe_channel *channel;
2206 /* Disable MAC Rx */
2207 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
2208 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
2209 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
2210 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
2212 /* Disable each Rx queue */
2213 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
2215 /* Disable each Rx DMA channel */
2216 channel = pdata->channel;
2217 for (i = 0; i < pdata->channel_count; i++, channel++) {
2218 if (!channel->rx_ring)
2221 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2225 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
2227 struct xgbe_channel *channel;
2230 /* Enable each Tx DMA channel */
2231 channel = pdata->channel;
2232 for (i = 0; i < pdata->channel_count; i++, channel++) {
2233 if (!channel->tx_ring)
2236 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2240 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2243 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
2245 struct xgbe_channel *channel;
2248 /* Disable MAC Tx */
2249 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2251 /* Disable each Tx DMA channel */
2252 channel = pdata->channel;
2253 for (i = 0; i < pdata->channel_count; i++, channel++) {
2254 if (!channel->tx_ring)
2257 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2261 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
2263 struct xgbe_channel *channel;
2266 /* Enable each Rx DMA channel */
2267 channel = pdata->channel;
2268 for (i = 0; i < pdata->channel_count; i++, channel++) {
2269 if (!channel->rx_ring)
2272 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2276 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
2278 struct xgbe_channel *channel;
2281 /* Disable each Rx DMA channel */
2282 channel = pdata->channel;
2283 for (i = 0; i < pdata->channel_count; i++, channel++) {
2284 if (!channel->rx_ring)
2287 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2291 static int xgbe_init(struct xgbe_prv_data *pdata)
2293 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2296 DBGPR("-->xgbe_init\n");
2298 /* Flush Tx queues */
2299 ret = xgbe_flush_tx_queues(pdata);
2304 * Initialize DMA related features
2306 xgbe_config_dma_bus(pdata);
2307 xgbe_config_dma_cache(pdata);
2308 xgbe_config_osp_mode(pdata);
2309 xgbe_config_pblx8(pdata);
2310 xgbe_config_tx_pbl_val(pdata);
2311 xgbe_config_rx_pbl_val(pdata);
2312 xgbe_config_rx_coalesce(pdata);
2313 xgbe_config_tx_coalesce(pdata);
2314 xgbe_config_rx_buffer_size(pdata);
2315 xgbe_config_tso_mode(pdata);
2316 desc_if->wrapper_tx_desc_init(pdata);
2317 desc_if->wrapper_rx_desc_init(pdata);
2318 xgbe_enable_dma_interrupts(pdata);
2321 * Initialize MTL related features
2323 xgbe_config_mtl_mode(pdata);
2324 xgbe_config_rx_queue_mapping(pdata);
2325 /*TODO: Program the priorities mapped to the Selected Traffic Classes
2326 in MTL_TC_Prty_Map0-3 registers */
2327 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
2328 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
2329 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
2330 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
2331 xgbe_config_tx_fifo_size(pdata);
2332 xgbe_config_rx_fifo_size(pdata);
2333 xgbe_config_flow_control_threshold(pdata);
2334 /*TODO: Queue to Traffic Class Mapping (Q2TCMAP) */
2335 /*TODO: Error Packet and undersized good Packet forwarding enable
2338 xgbe_enable_mtl_interrupts(pdata);
2340 /* Transmit Class Weight */
2341 XGMAC_IOWRITE_BITS(pdata, MTL_Q_TCQWR, QW, 0x10);
2344 * Initialize MAC related features
2346 xgbe_config_mac_address(pdata);
2347 xgbe_config_jumbo_enable(pdata);
2348 xgbe_config_flow_control(pdata);
2349 xgbe_config_checksum_offload(pdata);
2350 xgbe_config_vlan_support(pdata);
2351 xgbe_config_mmc(pdata);
2352 xgbe_enable_mac_interrupts(pdata);
2354 DBGPR("<--xgbe_init\n");
2359 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
2361 DBGPR("-->xgbe_init_function_ptrs\n");
2363 hw_if->tx_complete = xgbe_tx_complete;
2365 hw_if->set_promiscuous_mode = xgbe_set_promiscuous_mode;
2366 hw_if->set_all_multicast_mode = xgbe_set_all_multicast_mode;
2367 hw_if->add_mac_addresses = xgbe_add_mac_addresses;
2368 hw_if->set_mac_address = xgbe_set_mac_address;
2370 hw_if->enable_rx_csum = xgbe_enable_rx_csum;
2371 hw_if->disable_rx_csum = xgbe_disable_rx_csum;
2373 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
2374 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
2375 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
2376 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
2377 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
2379 hw_if->read_mmd_regs = xgbe_read_mmd_regs;
2380 hw_if->write_mmd_regs = xgbe_write_mmd_regs;
2382 hw_if->set_gmii_speed = xgbe_set_gmii_speed;
2383 hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed;
2384 hw_if->set_xgmii_speed = xgbe_set_xgmii_speed;
2386 hw_if->enable_tx = xgbe_enable_tx;
2387 hw_if->disable_tx = xgbe_disable_tx;
2388 hw_if->enable_rx = xgbe_enable_rx;
2389 hw_if->disable_rx = xgbe_disable_rx;
2391 hw_if->powerup_tx = xgbe_powerup_tx;
2392 hw_if->powerdown_tx = xgbe_powerdown_tx;
2393 hw_if->powerup_rx = xgbe_powerup_rx;
2394 hw_if->powerdown_rx = xgbe_powerdown_rx;
2396 hw_if->pre_xmit = xgbe_pre_xmit;
2397 hw_if->dev_read = xgbe_dev_read;
2398 hw_if->enable_int = xgbe_enable_int;
2399 hw_if->disable_int = xgbe_disable_int;
2400 hw_if->init = xgbe_init;
2401 hw_if->exit = xgbe_exit;
2403 /* Descriptor related Sequences have to be initialized here */
2404 hw_if->tx_desc_init = xgbe_tx_desc_init;
2405 hw_if->rx_desc_init = xgbe_rx_desc_init;
2406 hw_if->tx_desc_reset = xgbe_tx_desc_reset;
2407 hw_if->rx_desc_reset = xgbe_rx_desc_reset;
2408 hw_if->is_last_desc = xgbe_is_last_desc;
2409 hw_if->is_context_desc = xgbe_is_context_desc;
2412 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
2413 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
2415 /* For RX coalescing */
2416 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
2417 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
2418 hw_if->usec_to_riwt = xgbe_usec_to_riwt;
2419 hw_if->riwt_to_usec = xgbe_riwt_to_usec;
2421 /* For RX and TX threshold config */
2422 hw_if->config_rx_threshold = xgbe_config_rx_threshold;
2423 hw_if->config_tx_threshold = xgbe_config_tx_threshold;
2425 /* For RX and TX Store and Forward Mode config */
2426 hw_if->config_rsf_mode = xgbe_config_rsf_mode;
2427 hw_if->config_tsf_mode = xgbe_config_tsf_mode;
2429 /* For TX DMA Operating on Second Frame config */
2430 hw_if->config_osp_mode = xgbe_config_osp_mode;
2432 /* For RX and TX PBL config */
2433 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;
2434 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;
2435 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;
2436 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;
2437 hw_if->config_pblx8 = xgbe_config_pblx8;
2439 /* For MMC statistics support */
2440 hw_if->tx_mmc_int = xgbe_tx_mmc_int;
2441 hw_if->rx_mmc_int = xgbe_rx_mmc_int;
2442 hw_if->read_mmc_stats = xgbe_read_mmc_stats;
2444 /* For PTP config */
2445 hw_if->config_tstamp = xgbe_config_tstamp;
2446 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
2447 hw_if->set_tstamp_time = xgbe_set_tstamp_time;
2448 hw_if->get_tstamp_time = xgbe_get_tstamp_time;
2449 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
2451 DBGPR("<--xgbe_init_function_ptrs\n");