2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/platform_device.h>
118 #include <linux/spinlock.h>
119 #include <linux/tcp.h>
120 #include <linux/if_vlan.h>
121 #include <net/busy_poll.h>
122 #include <linux/clk.h>
123 #include <linux/if_ether.h>
124 #include <linux/net_tstamp.h>
125 #include <linux/phy.h>
128 #include "xgbe-common.h"
130 static int xgbe_one_poll(struct napi_struct *, int);
131 static int xgbe_all_poll(struct napi_struct *, int);
132 static void xgbe_set_rx_mode(struct net_device *);
134 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
136 struct xgbe_channel *channel_mem, *channel;
137 struct xgbe_ring *tx_ring, *rx_ring;
138 unsigned int count, i;
141 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
143 channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL);
147 tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring),
152 rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring),
157 for (i = 0, channel = channel_mem; i < count; i++, channel++) {
158 snprintf(channel->name, sizeof(channel->name), "channel-%d", i);
159 channel->pdata = pdata;
160 channel->queue_index = i;
161 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
164 if (pdata->per_channel_irq) {
165 /* Get the DMA interrupt (offset 1) */
166 ret = platform_get_irq(pdata->pdev, i + 1);
168 netdev_err(pdata->netdev,
169 "platform_get_irq %u failed\n",
174 channel->dma_irq = ret;
177 if (i < pdata->tx_ring_count) {
178 spin_lock_init(&tx_ring->lock);
179 channel->tx_ring = tx_ring++;
182 if (i < pdata->rx_ring_count) {
183 spin_lock_init(&rx_ring->lock);
184 channel->rx_ring = rx_ring++;
187 DBGPR(" %s: queue=%u, dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
188 channel->name, channel->queue_index, channel->dma_regs,
189 channel->dma_irq, channel->tx_ring, channel->rx_ring);
192 pdata->channel = channel_mem;
193 pdata->channel_count = count;
210 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
215 kfree(pdata->channel->rx_ring);
216 kfree(pdata->channel->tx_ring);
217 kfree(pdata->channel);
219 pdata->channel = NULL;
220 pdata->channel_count = 0;
223 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
225 return (ring->rdesc_count - (ring->cur - ring->dirty));
228 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
229 struct xgbe_ring *ring, unsigned int count)
231 struct xgbe_prv_data *pdata = channel->pdata;
233 if (count > xgbe_tx_avail_desc(ring)) {
234 DBGPR(" Tx queue stopped, not enough descriptors available\n");
235 netif_stop_subqueue(pdata->netdev, channel->queue_index);
236 ring->tx.queue_stopped = 1;
238 /* If we haven't notified the hardware because of xmit_more
239 * support, tell it now
241 if (ring->tx.xmit_more)
242 pdata->hw_if.tx_start_xmit(channel, ring);
244 return NETDEV_TX_BUSY;
250 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
252 unsigned int rx_buf_size;
254 if (mtu > XGMAC_JUMBO_PACKET_MTU) {
255 netdev_alert(netdev, "MTU exceeds maximum supported value\n");
259 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
260 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
262 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
263 ~(XGBE_RX_BUF_ALIGN - 1);
268 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
270 struct xgbe_hw_if *hw_if = &pdata->hw_if;
271 struct xgbe_channel *channel;
272 enum xgbe_int int_id;
275 channel = pdata->channel;
276 for (i = 0; i < pdata->channel_count; i++, channel++) {
277 if (channel->tx_ring && channel->rx_ring)
278 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
279 else if (channel->tx_ring)
280 int_id = XGMAC_INT_DMA_CH_SR_TI;
281 else if (channel->rx_ring)
282 int_id = XGMAC_INT_DMA_CH_SR_RI;
286 hw_if->enable_int(channel, int_id);
290 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
292 struct xgbe_hw_if *hw_if = &pdata->hw_if;
293 struct xgbe_channel *channel;
294 enum xgbe_int int_id;
297 channel = pdata->channel;
298 for (i = 0; i < pdata->channel_count; i++, channel++) {
299 if (channel->tx_ring && channel->rx_ring)
300 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
301 else if (channel->tx_ring)
302 int_id = XGMAC_INT_DMA_CH_SR_TI;
303 else if (channel->rx_ring)
304 int_id = XGMAC_INT_DMA_CH_SR_RI;
308 hw_if->disable_int(channel, int_id);
312 static irqreturn_t xgbe_isr(int irq, void *data)
314 struct xgbe_prv_data *pdata = data;
315 struct xgbe_hw_if *hw_if = &pdata->hw_if;
316 struct xgbe_channel *channel;
317 unsigned int dma_isr, dma_ch_isr;
318 unsigned int mac_isr, mac_tssr;
321 /* The DMA interrupt status register also reports MAC and MTL
322 * interrupts. So for polling mode, we just need to check for
323 * this register to be non-zero
325 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
329 DBGPR(" DMA_ISR = %08x\n", dma_isr);
331 for (i = 0; i < pdata->channel_count; i++) {
332 if (!(dma_isr & (1 << i)))
335 channel = pdata->channel + i;
337 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
338 DBGPR(" DMA_CH%u_ISR = %08x\n", i, dma_ch_isr);
340 /* If we get a TI or RI interrupt that means per channel DMA
341 * interrupts are not enabled, so we use the private data napi
342 * structure, not the per channel napi structure
344 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
345 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI)) {
346 if (napi_schedule_prep(&pdata->napi)) {
347 /* Disable Tx and Rx interrupts */
348 xgbe_disable_rx_tx_ints(pdata);
350 /* Turn on polling */
351 __napi_schedule(&pdata->napi);
355 /* Restart the device on a Fatal Bus Error */
356 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
357 schedule_work(&pdata->restart_work);
359 /* Clear all interrupt signals */
360 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
363 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
364 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
366 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
367 hw_if->tx_mmc_int(pdata);
369 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
370 hw_if->rx_mmc_int(pdata);
372 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
373 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
375 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
376 /* Read Tx Timestamp to clear interrupt */
378 hw_if->get_tx_tstamp(pdata);
379 schedule_work(&pdata->tx_tstamp_work);
384 DBGPR(" DMA_ISR = %08x\n", XGMAC_IOREAD(pdata, DMA_ISR));
390 static irqreturn_t xgbe_dma_isr(int irq, void *data)
392 struct xgbe_channel *channel = data;
394 /* Per channel DMA interrupts are enabled, so we use the per
395 * channel napi structure and not the private data napi structure
397 if (napi_schedule_prep(&channel->napi)) {
398 /* Disable Tx and Rx interrupts */
399 disable_irq_nosync(channel->dma_irq);
401 /* Turn on polling */
402 __napi_schedule(&channel->napi);
408 static enum hrtimer_restart xgbe_tx_timer(struct hrtimer *timer)
410 struct xgbe_channel *channel = container_of(timer,
413 struct xgbe_ring *ring = channel->tx_ring;
414 struct xgbe_prv_data *pdata = channel->pdata;
415 struct napi_struct *napi;
418 DBGPR("-->xgbe_tx_timer\n");
420 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
422 spin_lock_irqsave(&ring->lock, flags);
424 if (napi_schedule_prep(napi)) {
425 /* Disable Tx and Rx interrupts */
426 if (pdata->per_channel_irq)
427 disable_irq(channel->dma_irq);
429 xgbe_disable_rx_tx_ints(pdata);
431 /* Turn on polling */
432 __napi_schedule(napi);
435 channel->tx_timer_active = 0;
437 spin_unlock_irqrestore(&ring->lock, flags);
439 DBGPR("<--xgbe_tx_timer\n");
441 return HRTIMER_NORESTART;
444 static void xgbe_init_tx_timers(struct xgbe_prv_data *pdata)
446 struct xgbe_channel *channel;
449 DBGPR("-->xgbe_init_tx_timers\n");
451 channel = pdata->channel;
452 for (i = 0; i < pdata->channel_count; i++, channel++) {
453 if (!channel->tx_ring)
456 DBGPR(" %s adding tx timer\n", channel->name);
457 hrtimer_init(&channel->tx_timer, CLOCK_MONOTONIC,
459 channel->tx_timer.function = xgbe_tx_timer;
462 DBGPR("<--xgbe_init_tx_timers\n");
465 static void xgbe_stop_tx_timers(struct xgbe_prv_data *pdata)
467 struct xgbe_channel *channel;
470 DBGPR("-->xgbe_stop_tx_timers\n");
472 channel = pdata->channel;
473 for (i = 0; i < pdata->channel_count; i++, channel++) {
474 if (!channel->tx_ring)
477 DBGPR(" %s deleting tx timer\n", channel->name);
478 channel->tx_timer_active = 0;
479 hrtimer_cancel(&channel->tx_timer);
482 DBGPR("<--xgbe_stop_tx_timers\n");
485 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
487 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
488 struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
490 DBGPR("-->xgbe_get_all_hw_features\n");
492 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
493 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
494 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
496 memset(hw_feat, 0, sizeof(*hw_feat));
498 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
500 /* Hardware feature register 0 */
501 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
502 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
503 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
504 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
505 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
506 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
507 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
508 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
509 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
510 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
511 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
512 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
514 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
515 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
517 /* Hardware feature register 1 */
518 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
520 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
522 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
523 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
524 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
525 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
526 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
527 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
529 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
532 /* Hardware feature register 2 */
533 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
534 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
535 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
536 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
537 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
538 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
540 /* Translate the Hash Table size into actual number */
541 switch (hw_feat->hash_table_size) {
545 hw_feat->hash_table_size = 64;
548 hw_feat->hash_table_size = 128;
551 hw_feat->hash_table_size = 256;
555 /* The Queue and Channel counts are zero based so increment them
556 * to get the actual number
560 hw_feat->rx_ch_cnt++;
561 hw_feat->tx_ch_cnt++;
563 DBGPR("<--xgbe_get_all_hw_features\n");
566 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
568 struct xgbe_channel *channel;
571 if (pdata->per_channel_irq) {
572 channel = pdata->channel;
573 for (i = 0; i < pdata->channel_count; i++, channel++) {
575 netif_napi_add(pdata->netdev, &channel->napi,
576 xgbe_one_poll, NAPI_POLL_WEIGHT);
578 napi_enable(&channel->napi);
582 netif_napi_add(pdata->netdev, &pdata->napi,
583 xgbe_all_poll, NAPI_POLL_WEIGHT);
585 napi_enable(&pdata->napi);
589 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
591 struct xgbe_channel *channel;
594 if (pdata->per_channel_irq) {
595 channel = pdata->channel;
596 for (i = 0; i < pdata->channel_count; i++, channel++) {
597 napi_disable(&channel->napi);
600 netif_napi_del(&channel->napi);
603 napi_disable(&pdata->napi);
606 netif_napi_del(&pdata->napi);
610 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
612 struct xgbe_hw_if *hw_if = &pdata->hw_if;
614 DBGPR("-->xgbe_init_tx_coalesce\n");
616 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
617 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
619 hw_if->config_tx_coalesce(pdata);
621 DBGPR("<--xgbe_init_tx_coalesce\n");
624 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
626 struct xgbe_hw_if *hw_if = &pdata->hw_if;
628 DBGPR("-->xgbe_init_rx_coalesce\n");
630 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
631 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
633 hw_if->config_rx_coalesce(pdata);
635 DBGPR("<--xgbe_init_rx_coalesce\n");
638 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
640 struct xgbe_desc_if *desc_if = &pdata->desc_if;
641 struct xgbe_channel *channel;
642 struct xgbe_ring *ring;
643 struct xgbe_ring_data *rdata;
646 DBGPR("-->xgbe_free_tx_data\n");
648 channel = pdata->channel;
649 for (i = 0; i < pdata->channel_count; i++, channel++) {
650 ring = channel->tx_ring;
654 for (j = 0; j < ring->rdesc_count; j++) {
655 rdata = XGBE_GET_DESC_DATA(ring, j);
656 desc_if->unmap_rdata(pdata, rdata);
660 DBGPR("<--xgbe_free_tx_data\n");
663 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
665 struct xgbe_desc_if *desc_if = &pdata->desc_if;
666 struct xgbe_channel *channel;
667 struct xgbe_ring *ring;
668 struct xgbe_ring_data *rdata;
671 DBGPR("-->xgbe_free_rx_data\n");
673 channel = pdata->channel;
674 for (i = 0; i < pdata->channel_count; i++, channel++) {
675 ring = channel->rx_ring;
679 for (j = 0; j < ring->rdesc_count; j++) {
680 rdata = XGBE_GET_DESC_DATA(ring, j);
681 desc_if->unmap_rdata(pdata, rdata);
685 DBGPR("<--xgbe_free_rx_data\n");
688 static void xgbe_adjust_link(struct net_device *netdev)
690 struct xgbe_prv_data *pdata = netdev_priv(netdev);
691 struct xgbe_hw_if *hw_if = &pdata->hw_if;
692 struct phy_device *phydev = pdata->phydev;
699 /* Flow control support */
700 if (pdata->pause_autoneg) {
701 if (phydev->pause || phydev->asym_pause) {
710 if (pdata->tx_pause != pdata->phy_tx_pause) {
711 hw_if->config_tx_flow_control(pdata);
712 pdata->phy_tx_pause = pdata->tx_pause;
715 if (pdata->rx_pause != pdata->phy_rx_pause) {
716 hw_if->config_rx_flow_control(pdata);
717 pdata->phy_rx_pause = pdata->rx_pause;
721 if (phydev->speed != pdata->phy_speed) {
724 switch (phydev->speed) {
726 hw_if->set_xgmii_speed(pdata);
730 hw_if->set_gmii_2500_speed(pdata);
734 hw_if->set_gmii_speed(pdata);
737 pdata->phy_speed = phydev->speed;
740 if (phydev->link != pdata->phy_link) {
744 } else if (pdata->phy_link) {
747 pdata->phy_speed = SPEED_UNKNOWN;
751 phy_print_status(phydev);
754 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
756 struct net_device *netdev = pdata->netdev;
757 struct phy_device *phydev = pdata->phydev;
760 pdata->phy_link = -1;
761 pdata->phy_speed = SPEED_UNKNOWN;
762 pdata->phy_tx_pause = pdata->tx_pause;
763 pdata->phy_rx_pause = pdata->rx_pause;
765 ret = phy_connect_direct(netdev, phydev, &xgbe_adjust_link,
768 netdev_err(netdev, "phy_connect_direct failed\n");
772 if (!phydev->drv || (phydev->drv->phy_id == 0)) {
773 netdev_err(netdev, "phy_id not valid\n");
775 goto err_phy_connect;
777 DBGPR(" phy_connect_direct succeeded for PHY %s, link=%d\n",
778 dev_name(&phydev->dev), phydev->link);
783 phy_disconnect(phydev);
788 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
793 phy_disconnect(pdata->phydev);
796 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
798 struct xgbe_prv_data *pdata = netdev_priv(netdev);
799 struct xgbe_hw_if *hw_if = &pdata->hw_if;
802 DBGPR("-->xgbe_powerdown\n");
804 if (!netif_running(netdev) ||
805 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
806 netdev_alert(netdev, "Device is already powered down\n");
807 DBGPR("<--xgbe_powerdown\n");
811 phy_stop(pdata->phydev);
813 spin_lock_irqsave(&pdata->lock, flags);
815 if (caller == XGMAC_DRIVER_CONTEXT)
816 netif_device_detach(netdev);
818 netif_tx_stop_all_queues(netdev);
819 xgbe_napi_disable(pdata, 0);
821 /* Powerdown Tx/Rx */
822 hw_if->powerdown_tx(pdata);
823 hw_if->powerdown_rx(pdata);
825 pdata->power_down = 1;
827 spin_unlock_irqrestore(&pdata->lock, flags);
829 DBGPR("<--xgbe_powerdown\n");
834 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
836 struct xgbe_prv_data *pdata = netdev_priv(netdev);
837 struct xgbe_hw_if *hw_if = &pdata->hw_if;
840 DBGPR("-->xgbe_powerup\n");
842 if (!netif_running(netdev) ||
843 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
844 netdev_alert(netdev, "Device is already powered up\n");
845 DBGPR("<--xgbe_powerup\n");
849 spin_lock_irqsave(&pdata->lock, flags);
851 pdata->power_down = 0;
853 phy_start(pdata->phydev);
856 hw_if->powerup_tx(pdata);
857 hw_if->powerup_rx(pdata);
859 if (caller == XGMAC_DRIVER_CONTEXT)
860 netif_device_attach(netdev);
862 xgbe_napi_enable(pdata, 0);
863 netif_tx_start_all_queues(netdev);
865 spin_unlock_irqrestore(&pdata->lock, flags);
867 DBGPR("<--xgbe_powerup\n");
872 static int xgbe_start(struct xgbe_prv_data *pdata)
874 struct xgbe_hw_if *hw_if = &pdata->hw_if;
875 struct net_device *netdev = pdata->netdev;
877 DBGPR("-->xgbe_start\n");
879 xgbe_set_rx_mode(netdev);
883 phy_start(pdata->phydev);
885 hw_if->enable_tx(pdata);
886 hw_if->enable_rx(pdata);
888 xgbe_init_tx_timers(pdata);
890 xgbe_napi_enable(pdata, 1);
891 netif_tx_start_all_queues(netdev);
893 DBGPR("<--xgbe_start\n");
898 static void xgbe_stop(struct xgbe_prv_data *pdata)
900 struct xgbe_hw_if *hw_if = &pdata->hw_if;
901 struct xgbe_channel *channel;
902 struct net_device *netdev = pdata->netdev;
903 struct netdev_queue *txq;
906 DBGPR("-->xgbe_stop\n");
908 phy_stop(pdata->phydev);
910 netif_tx_stop_all_queues(netdev);
911 xgbe_napi_disable(pdata, 1);
913 xgbe_stop_tx_timers(pdata);
915 hw_if->disable_tx(pdata);
916 hw_if->disable_rx(pdata);
918 channel = pdata->channel;
919 for (i = 0; i < pdata->channel_count; i++, channel++) {
920 if (!channel->tx_ring)
923 txq = netdev_get_tx_queue(netdev, channel->queue_index);
924 netdev_tx_reset_queue(txq);
927 DBGPR("<--xgbe_stop\n");
930 static void xgbe_restart_dev(struct xgbe_prv_data *pdata, unsigned int reset)
932 struct xgbe_channel *channel;
933 struct xgbe_hw_if *hw_if = &pdata->hw_if;
936 DBGPR("-->xgbe_restart_dev\n");
938 /* If not running, "restart" will happen on open */
939 if (!netif_running(pdata->netdev))
943 synchronize_irq(pdata->dev_irq);
944 if (pdata->per_channel_irq) {
945 channel = pdata->channel;
946 for (i = 0; i < pdata->channel_count; i++, channel++)
947 synchronize_irq(channel->dma_irq);
950 xgbe_free_tx_data(pdata);
951 xgbe_free_rx_data(pdata);
953 /* Issue software reset to device if requested */
959 DBGPR("<--xgbe_restart_dev\n");
962 static void xgbe_restart(struct work_struct *work)
964 struct xgbe_prv_data *pdata = container_of(work,
965 struct xgbe_prv_data,
970 xgbe_restart_dev(pdata, 1);
975 static void xgbe_tx_tstamp(struct work_struct *work)
977 struct xgbe_prv_data *pdata = container_of(work,
978 struct xgbe_prv_data,
980 struct skb_shared_hwtstamps hwtstamps;
984 if (pdata->tx_tstamp) {
985 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
988 memset(&hwtstamps, 0, sizeof(hwtstamps));
989 hwtstamps.hwtstamp = ns_to_ktime(nsec);
990 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
993 dev_kfree_skb_any(pdata->tx_tstamp_skb);
995 spin_lock_irqsave(&pdata->tstamp_lock, flags);
996 pdata->tx_tstamp_skb = NULL;
997 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1000 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1001 struct ifreq *ifreq)
1003 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1004 sizeof(pdata->tstamp_config)))
1010 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1011 struct ifreq *ifreq)
1013 struct hwtstamp_config config;
1014 unsigned int mac_tscr;
1016 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1024 switch (config.tx_type) {
1025 case HWTSTAMP_TX_OFF:
1028 case HWTSTAMP_TX_ON:
1029 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1036 switch (config.rx_filter) {
1037 case HWTSTAMP_FILTER_NONE:
1040 case HWTSTAMP_FILTER_ALL:
1041 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1042 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1045 /* PTP v2, UDP, any kind of event packet */
1046 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1047 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1048 /* PTP v1, UDP, any kind of event packet */
1049 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1050 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1051 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1052 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1053 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1056 /* PTP v2, UDP, Sync packet */
1057 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1058 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1059 /* PTP v1, UDP, Sync packet */
1060 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1061 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1062 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1063 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1064 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1067 /* PTP v2, UDP, Delay_req packet */
1068 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1069 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1070 /* PTP v1, UDP, Delay_req packet */
1071 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1072 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1073 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1074 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1075 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1076 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1079 /* 802.AS1, Ethernet, any kind of event packet */
1080 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1081 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1082 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1083 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1086 /* 802.AS1, Ethernet, Sync packet */
1087 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1088 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1089 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1090 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1093 /* 802.AS1, Ethernet, Delay_req packet */
1094 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1095 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1096 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1097 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1098 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1101 /* PTP v2/802.AS1, any layer, any kind of event packet */
1102 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1103 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1104 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1105 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1106 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1107 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1108 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1111 /* PTP v2/802.AS1, any layer, Sync packet */
1112 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1113 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1114 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1115 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1116 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1117 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1118 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1121 /* PTP v2/802.AS1, any layer, Delay_req packet */
1122 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1123 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1124 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1125 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1126 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1127 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1128 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1129 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1136 pdata->hw_if.config_tstamp(pdata, mac_tscr);
1138 memcpy(&pdata->tstamp_config, &config, sizeof(config));
1143 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1144 struct sk_buff *skb,
1145 struct xgbe_packet_data *packet)
1147 unsigned long flags;
1149 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1150 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1151 if (pdata->tx_tstamp_skb) {
1152 /* Another timestamp in progress, ignore this one */
1153 XGMAC_SET_BITS(packet->attributes,
1154 TX_PACKET_ATTRIBUTES, PTP, 0);
1156 pdata->tx_tstamp_skb = skb_get(skb);
1157 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1159 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1162 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1163 skb_tx_timestamp(skb);
1166 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1168 if (vlan_tx_tag_present(skb))
1169 packet->vlan_ctag = vlan_tx_tag_get(skb);
1172 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1176 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1180 ret = skb_cow_head(skb, 0);
1184 packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1185 packet->tcp_header_len = tcp_hdrlen(skb);
1186 packet->tcp_payload_len = skb->len - packet->header_len;
1187 packet->mss = skb_shinfo(skb)->gso_size;
1188 DBGPR(" packet->header_len=%u\n", packet->header_len);
1189 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1190 packet->tcp_header_len, packet->tcp_payload_len);
1191 DBGPR(" packet->mss=%u\n", packet->mss);
1193 /* Update the number of packets that will ultimately be transmitted
1194 * along with the extra bytes for each extra packet
1196 packet->tx_packets = skb_shinfo(skb)->gso_segs;
1197 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1202 static int xgbe_is_tso(struct sk_buff *skb)
1204 if (skb->ip_summed != CHECKSUM_PARTIAL)
1207 if (!skb_is_gso(skb))
1210 DBGPR(" TSO packet to be processed\n");
1215 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1216 struct xgbe_ring *ring, struct sk_buff *skb,
1217 struct xgbe_packet_data *packet)
1219 struct skb_frag_struct *frag;
1220 unsigned int context_desc;
1227 packet->rdesc_count = 0;
1229 packet->tx_packets = 1;
1230 packet->tx_bytes = skb->len;
1232 if (xgbe_is_tso(skb)) {
1233 /* TSO requires an extra descriptor if mss is different */
1234 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1236 packet->rdesc_count++;
1239 /* TSO requires an extra descriptor for TSO header */
1240 packet->rdesc_count++;
1242 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1244 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1246 } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1247 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1250 if (vlan_tx_tag_present(skb)) {
1251 /* VLAN requires an extra descriptor if tag is different */
1252 if (vlan_tx_tag_get(skb) != ring->tx.cur_vlan_ctag)
1253 /* We can share with the TSO context descriptor */
1254 if (!context_desc) {
1256 packet->rdesc_count++;
1259 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1263 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1264 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1265 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1268 for (len = skb_headlen(skb); len;) {
1269 packet->rdesc_count++;
1270 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1273 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1274 frag = &skb_shinfo(skb)->frags[i];
1275 for (len = skb_frag_size(frag); len; ) {
1276 packet->rdesc_count++;
1277 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1282 static int xgbe_open(struct net_device *netdev)
1284 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1285 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1286 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1287 struct xgbe_channel *channel = NULL;
1291 DBGPR("-->xgbe_open\n");
1293 /* Initialize the phy */
1294 ret = xgbe_phy_init(pdata);
1298 /* Enable the clocks */
1299 ret = clk_prepare_enable(pdata->sysclk);
1301 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1305 ret = clk_prepare_enable(pdata->ptpclk);
1307 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1311 /* Calculate the Rx buffer size before allocating rings */
1312 ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1315 pdata->rx_buf_size = ret;
1317 /* Allocate the channel and ring structures */
1318 ret = xgbe_alloc_channels(pdata);
1322 /* Allocate the ring descriptors and buffers */
1323 ret = desc_if->alloc_ring_resources(pdata);
1327 /* Initialize the device restart and Tx timestamp work struct */
1328 INIT_WORK(&pdata->restart_work, xgbe_restart);
1329 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1331 /* Request interrupts */
1332 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
1333 netdev->name, pdata);
1335 netdev_alert(netdev, "error requesting irq %d\n",
1340 if (pdata->per_channel_irq) {
1341 channel = pdata->channel;
1342 for (i = 0; i < pdata->channel_count; i++, channel++) {
1343 snprintf(channel->dma_irq_name,
1344 sizeof(channel->dma_irq_name) - 1,
1345 "%s-TxRx-%u", netdev_name(netdev),
1346 channel->queue_index);
1348 ret = devm_request_irq(pdata->dev, channel->dma_irq,
1350 channel->dma_irq_name, channel);
1352 netdev_alert(netdev,
1353 "error requesting irq %d\n",
1360 ret = xgbe_start(pdata);
1364 DBGPR("<--xgbe_open\n");
1372 if (pdata->per_channel_irq) {
1373 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1374 for (i--, channel--; i < pdata->channel_count; i--, channel--)
1375 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1378 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1381 desc_if->free_ring_resources(pdata);
1384 xgbe_free_channels(pdata);
1387 clk_disable_unprepare(pdata->ptpclk);
1390 clk_disable_unprepare(pdata->sysclk);
1393 xgbe_phy_exit(pdata);
1398 static int xgbe_close(struct net_device *netdev)
1400 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1401 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1402 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1403 struct xgbe_channel *channel;
1406 DBGPR("-->xgbe_close\n");
1408 /* Stop the device */
1411 /* Issue software reset to device */
1414 /* Free the ring descriptors and buffers */
1415 desc_if->free_ring_resources(pdata);
1417 /* Release the interrupts */
1418 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1419 if (pdata->per_channel_irq) {
1420 channel = pdata->channel;
1421 for (i = 0; i < pdata->channel_count; i++, channel++)
1422 devm_free_irq(pdata->dev, channel->dma_irq, channel);
1425 /* Free the channel and ring structures */
1426 xgbe_free_channels(pdata);
1428 /* Disable the clocks */
1429 clk_disable_unprepare(pdata->ptpclk);
1430 clk_disable_unprepare(pdata->sysclk);
1432 /* Release the phy */
1433 xgbe_phy_exit(pdata);
1435 DBGPR("<--xgbe_close\n");
1440 static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1442 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1443 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1444 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1445 struct xgbe_channel *channel;
1446 struct xgbe_ring *ring;
1447 struct xgbe_packet_data *packet;
1448 struct netdev_queue *txq;
1449 unsigned long flags;
1452 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1454 channel = pdata->channel + skb->queue_mapping;
1455 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1456 ring = channel->tx_ring;
1457 packet = &ring->packet_data;
1461 spin_lock_irqsave(&ring->lock, flags);
1463 if (skb->len == 0) {
1464 netdev_err(netdev, "empty skb received from stack\n");
1465 dev_kfree_skb_any(skb);
1466 goto tx_netdev_return;
1469 /* Calculate preliminary packet info */
1470 memset(packet, 0, sizeof(*packet));
1471 xgbe_packet_info(pdata, ring, skb, packet);
1473 /* Check that there are enough descriptors available */
1474 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1476 goto tx_netdev_return;
1478 ret = xgbe_prep_tso(skb, packet);
1480 netdev_err(netdev, "error processing TSO packet\n");
1481 dev_kfree_skb_any(skb);
1482 goto tx_netdev_return;
1484 xgbe_prep_vlan(skb, packet);
1486 if (!desc_if->map_tx_skb(channel, skb)) {
1487 dev_kfree_skb_any(skb);
1488 goto tx_netdev_return;
1491 xgbe_prep_tx_tstamp(pdata, skb, packet);
1493 /* Report on the actual number of bytes (to be) sent */
1494 netdev_tx_sent_queue(txq, packet->tx_bytes);
1496 /* Configure required descriptor fields for transmission */
1497 hw_if->dev_xmit(channel);
1499 #ifdef XGMAC_ENABLE_TX_PKT_DUMP
1500 xgbe_print_pkt(netdev, skb, true);
1503 /* Stop the queue in advance if there may not be enough descriptors */
1504 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
1509 spin_unlock_irqrestore(&ring->lock, flags);
1511 DBGPR("<--xgbe_xmit\n");
1516 static void xgbe_set_rx_mode(struct net_device *netdev)
1518 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1519 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1520 unsigned int pr_mode, am_mode;
1522 DBGPR("-->xgbe_set_rx_mode\n");
1524 pr_mode = ((netdev->flags & IFF_PROMISC) != 0);
1525 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0);
1527 hw_if->set_promiscuous_mode(pdata, pr_mode);
1528 hw_if->set_all_multicast_mode(pdata, am_mode);
1530 hw_if->add_mac_addresses(pdata);
1532 DBGPR("<--xgbe_set_rx_mode\n");
1535 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
1537 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1538 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1539 struct sockaddr *saddr = addr;
1541 DBGPR("-->xgbe_set_mac_address\n");
1543 if (!is_valid_ether_addr(saddr->sa_data))
1544 return -EADDRNOTAVAIL;
1546 memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
1548 hw_if->set_mac_address(pdata, netdev->dev_addr);
1550 DBGPR("<--xgbe_set_mac_address\n");
1555 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
1557 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1562 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
1566 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
1576 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
1578 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1581 DBGPR("-->xgbe_change_mtu\n");
1583 ret = xgbe_calc_rx_buf_size(netdev, mtu);
1587 pdata->rx_buf_size = ret;
1590 xgbe_restart_dev(pdata, 0);
1592 DBGPR("<--xgbe_change_mtu\n");
1597 static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev,
1598 struct rtnl_link_stats64 *s)
1600 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1601 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
1603 DBGPR("-->%s\n", __func__);
1605 pdata->hw_if.read_mmc_stats(pdata);
1607 s->rx_packets = pstats->rxframecount_gb;
1608 s->rx_bytes = pstats->rxoctetcount_gb;
1609 s->rx_errors = pstats->rxframecount_gb -
1610 pstats->rxbroadcastframes_g -
1611 pstats->rxmulticastframes_g -
1612 pstats->rxunicastframes_g;
1613 s->multicast = pstats->rxmulticastframes_g;
1614 s->rx_length_errors = pstats->rxlengtherror;
1615 s->rx_crc_errors = pstats->rxcrcerror;
1616 s->rx_fifo_errors = pstats->rxfifooverflow;
1618 s->tx_packets = pstats->txframecount_gb;
1619 s->tx_bytes = pstats->txoctetcount_gb;
1620 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
1621 s->tx_dropped = netdev->stats.tx_dropped;
1623 DBGPR("<--%s\n", __func__);
1628 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1631 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1632 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1634 DBGPR("-->%s\n", __func__);
1636 set_bit(vid, pdata->active_vlans);
1637 hw_if->update_vlan_hash_table(pdata);
1639 DBGPR("<--%s\n", __func__);
1644 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1647 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1648 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1650 DBGPR("-->%s\n", __func__);
1652 clear_bit(vid, pdata->active_vlans);
1653 hw_if->update_vlan_hash_table(pdata);
1655 DBGPR("<--%s\n", __func__);
1660 #ifdef CONFIG_NET_POLL_CONTROLLER
1661 static void xgbe_poll_controller(struct net_device *netdev)
1663 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1664 struct xgbe_channel *channel;
1667 DBGPR("-->xgbe_poll_controller\n");
1669 if (pdata->per_channel_irq) {
1670 channel = pdata->channel;
1671 for (i = 0; i < pdata->channel_count; i++, channel++)
1672 xgbe_dma_isr(channel->dma_irq, channel);
1674 disable_irq(pdata->dev_irq);
1675 xgbe_isr(pdata->dev_irq, pdata);
1676 enable_irq(pdata->dev_irq);
1679 DBGPR("<--xgbe_poll_controller\n");
1681 #endif /* End CONFIG_NET_POLL_CONTROLLER */
1683 static int xgbe_setup_tc(struct net_device *netdev, u8 tc)
1685 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1686 unsigned int offset, queue;
1689 if (tc && (tc != pdata->hw_feat.tc_cnt))
1693 netdev_set_num_tc(netdev, tc);
1694 for (i = 0, queue = 0, offset = 0; i < tc; i++) {
1695 while ((queue < pdata->tx_q_count) &&
1696 (pdata->q2tc_map[queue] == i))
1699 DBGPR(" TC%u using TXq%u-%u\n", i, offset, queue - 1);
1700 netdev_set_tc_queue(netdev, i, queue - offset, offset);
1704 netdev_reset_tc(netdev);
1710 static int xgbe_set_features(struct net_device *netdev,
1711 netdev_features_t features)
1713 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1714 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1715 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
1718 rxhash = pdata->netdev_features & NETIF_F_RXHASH;
1719 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
1720 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
1721 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
1723 if ((features & NETIF_F_RXHASH) && !rxhash)
1724 ret = hw_if->enable_rss(pdata);
1725 else if (!(features & NETIF_F_RXHASH) && rxhash)
1726 ret = hw_if->disable_rss(pdata);
1730 if ((features & NETIF_F_RXCSUM) && !rxcsum)
1731 hw_if->enable_rx_csum(pdata);
1732 else if (!(features & NETIF_F_RXCSUM) && rxcsum)
1733 hw_if->disable_rx_csum(pdata);
1735 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
1736 hw_if->enable_rx_vlan_stripping(pdata);
1737 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
1738 hw_if->disable_rx_vlan_stripping(pdata);
1740 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
1741 hw_if->enable_rx_vlan_filtering(pdata);
1742 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
1743 hw_if->disable_rx_vlan_filtering(pdata);
1745 pdata->netdev_features = features;
1747 DBGPR("<--xgbe_set_features\n");
1752 static const struct net_device_ops xgbe_netdev_ops = {
1753 .ndo_open = xgbe_open,
1754 .ndo_stop = xgbe_close,
1755 .ndo_start_xmit = xgbe_xmit,
1756 .ndo_set_rx_mode = xgbe_set_rx_mode,
1757 .ndo_set_mac_address = xgbe_set_mac_address,
1758 .ndo_validate_addr = eth_validate_addr,
1759 .ndo_do_ioctl = xgbe_ioctl,
1760 .ndo_change_mtu = xgbe_change_mtu,
1761 .ndo_get_stats64 = xgbe_get_stats64,
1762 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid,
1763 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid,
1764 #ifdef CONFIG_NET_POLL_CONTROLLER
1765 .ndo_poll_controller = xgbe_poll_controller,
1767 .ndo_setup_tc = xgbe_setup_tc,
1768 .ndo_set_features = xgbe_set_features,
1771 struct net_device_ops *xgbe_get_netdev_ops(void)
1773 return (struct net_device_ops *)&xgbe_netdev_ops;
1776 static void xgbe_rx_refresh(struct xgbe_channel *channel)
1778 struct xgbe_prv_data *pdata = channel->pdata;
1779 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1780 struct xgbe_ring *ring = channel->rx_ring;
1781 struct xgbe_ring_data *rdata;
1783 desc_if->realloc_rx_buffer(channel);
1785 /* Update the Rx Tail Pointer Register with address of
1786 * the last cleaned entry */
1787 rdata = XGBE_GET_DESC_DATA(ring, ring->rx.realloc_index - 1);
1788 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1789 lower_32_bits(rdata->rdesc_dma));
1792 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
1793 struct xgbe_ring_data *rdata,
1796 struct net_device *netdev = pdata->netdev;
1797 struct sk_buff *skb;
1799 unsigned int copy_len;
1801 skb = netdev_alloc_skb_ip_align(netdev, rdata->rx.hdr.dma_len);
1805 packet = page_address(rdata->rx.hdr.pa.pages) +
1806 rdata->rx.hdr.pa.pages_offset;
1807 copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : *len;
1808 copy_len = min(rdata->rx.hdr.dma_len, copy_len);
1809 skb_copy_to_linear_data(skb, packet, copy_len);
1810 skb_put(skb, copy_len);
1817 static int xgbe_tx_poll(struct xgbe_channel *channel)
1819 struct xgbe_prv_data *pdata = channel->pdata;
1820 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1821 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1822 struct xgbe_ring *ring = channel->tx_ring;
1823 struct xgbe_ring_data *rdata;
1824 struct xgbe_ring_desc *rdesc;
1825 struct net_device *netdev = pdata->netdev;
1826 struct netdev_queue *txq;
1827 unsigned long flags;
1829 unsigned int tx_packets = 0, tx_bytes = 0;
1831 DBGPR("-->xgbe_tx_poll\n");
1833 /* Nothing to do if there isn't a Tx ring for this channel */
1837 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1839 spin_lock_irqsave(&ring->lock, flags);
1841 while ((processed < XGBE_TX_DESC_MAX_PROC) &&
1842 (ring->dirty != ring->cur)) {
1843 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1844 rdesc = rdata->rdesc;
1846 if (!hw_if->tx_complete(rdesc))
1849 /* Make sure descriptor fields are read after reading the OWN
1853 #ifdef XGMAC_ENABLE_TX_DESC_DUMP
1854 xgbe_dump_tx_desc(ring, ring->dirty, 1, 0);
1857 if (hw_if->is_last_desc(rdesc)) {
1858 tx_packets += rdata->tx.packets;
1859 tx_bytes += rdata->tx.bytes;
1862 /* Free the SKB and reset the descriptor for re-use */
1863 desc_if->unmap_rdata(pdata, rdata);
1864 hw_if->tx_desc_reset(rdata);
1873 netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
1875 if ((ring->tx.queue_stopped == 1) &&
1876 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
1877 ring->tx.queue_stopped = 0;
1878 netif_tx_wake_queue(txq);
1881 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
1884 spin_unlock_irqrestore(&ring->lock, flags);
1889 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
1891 struct xgbe_prv_data *pdata = channel->pdata;
1892 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1893 struct xgbe_ring *ring = channel->rx_ring;
1894 struct xgbe_ring_data *rdata;
1895 struct xgbe_packet_data *packet;
1896 struct net_device *netdev = pdata->netdev;
1897 struct napi_struct *napi;
1898 struct sk_buff *skb;
1899 struct skb_shared_hwtstamps *hwtstamps;
1900 unsigned int incomplete, error, context_next, context;
1901 unsigned int len, put_len, max_len;
1902 unsigned int received = 0;
1903 int packet_count = 0;
1905 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
1907 /* Nothing to do if there isn't a Rx ring for this channel */
1911 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
1913 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1914 packet = &ring->packet_data;
1915 while (packet_count < budget) {
1916 DBGPR(" cur = %d\n", ring->cur);
1918 /* First time in loop see if we need to restore state */
1919 if (!received && rdata->state_saved) {
1920 incomplete = rdata->state.incomplete;
1921 context_next = rdata->state.context_next;
1922 skb = rdata->state.skb;
1923 error = rdata->state.error;
1924 len = rdata->state.len;
1926 memset(packet, 0, sizeof(*packet));
1935 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1937 if (ring->dirty > (XGBE_RX_DESC_CNT >> 3))
1938 xgbe_rx_refresh(channel);
1940 if (hw_if->dev_read(channel))
1947 incomplete = XGMAC_GET_BITS(packet->attributes,
1948 RX_PACKET_ATTRIBUTES,
1950 context_next = XGMAC_GET_BITS(packet->attributes,
1951 RX_PACKET_ATTRIBUTES,
1953 context = XGMAC_GET_BITS(packet->attributes,
1954 RX_PACKET_ATTRIBUTES,
1957 /* Earlier error, just drain the remaining data */
1958 if ((incomplete || context_next) && error)
1961 if (error || packet->errors) {
1963 DBGPR("Error in received packet\n");
1969 put_len = rdata->rx.len - len;
1973 dma_sync_single_for_cpu(pdata->dev,
1975 rdata->rx.hdr.dma_len,
1978 skb = xgbe_create_skb(pdata, rdata, &put_len);
1986 dma_sync_single_for_cpu(pdata->dev,
1988 rdata->rx.buf.dma_len,
1991 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1992 rdata->rx.buf.pa.pages,
1993 rdata->rx.buf.pa.pages_offset,
1994 put_len, rdata->rx.buf.dma_len);
1995 rdata->rx.buf.pa.pages = NULL;
2000 if (incomplete || context_next)
2006 /* Be sure we don't exceed the configured MTU */
2007 max_len = netdev->mtu + ETH_HLEN;
2008 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2009 (skb->protocol == htons(ETH_P_8021Q)))
2010 max_len += VLAN_HLEN;
2012 if (skb->len > max_len) {
2013 DBGPR("packet length exceeds configured MTU\n");
2018 #ifdef XGMAC_ENABLE_RX_PKT_DUMP
2019 xgbe_print_pkt(netdev, skb, false);
2022 skb_checksum_none_assert(skb);
2023 if (XGMAC_GET_BITS(packet->attributes,
2024 RX_PACKET_ATTRIBUTES, CSUM_DONE))
2025 skb->ip_summed = CHECKSUM_UNNECESSARY;
2027 if (XGMAC_GET_BITS(packet->attributes,
2028 RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2029 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2032 if (XGMAC_GET_BITS(packet->attributes,
2033 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2036 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2038 hwtstamps = skb_hwtstamps(skb);
2039 hwtstamps->hwtstamp = ns_to_ktime(nsec);
2042 if (XGMAC_GET_BITS(packet->attributes,
2043 RX_PACKET_ATTRIBUTES, RSS_HASH))
2044 skb_set_hash(skb, packet->rss_hash,
2045 packet->rss_hash_type);
2048 skb->protocol = eth_type_trans(skb, netdev);
2049 skb_record_rx_queue(skb, channel->queue_index);
2050 skb_mark_napi_id(skb, napi);
2052 netdev->last_rx = jiffies;
2053 napi_gro_receive(napi, skb);
2059 /* Check if we need to save state before leaving */
2060 if (received && (incomplete || context_next)) {
2061 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2062 rdata->state_saved = 1;
2063 rdata->state.incomplete = incomplete;
2064 rdata->state.context_next = context_next;
2065 rdata->state.skb = skb;
2066 rdata->state.len = len;
2067 rdata->state.error = error;
2070 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2072 return packet_count;
2075 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2077 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2081 DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2083 /* Cleanup Tx ring first */
2084 xgbe_tx_poll(channel);
2086 /* Process Rx ring next */
2087 processed = xgbe_rx_poll(channel, budget);
2089 /* If we processed everything, we are done */
2090 if (processed < budget) {
2091 /* Turn off polling */
2092 napi_complete(napi);
2094 /* Enable Tx and Rx interrupts */
2095 enable_irq(channel->dma_irq);
2098 DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2103 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2105 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2107 struct xgbe_channel *channel;
2109 int processed, last_processed;
2112 DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2115 ring_budget = budget / pdata->rx_ring_count;
2117 last_processed = processed;
2119 channel = pdata->channel;
2120 for (i = 0; i < pdata->channel_count; i++, channel++) {
2121 /* Cleanup Tx ring first */
2122 xgbe_tx_poll(channel);
2124 /* Process Rx ring next */
2125 if (ring_budget > (budget - processed))
2126 ring_budget = budget - processed;
2127 processed += xgbe_rx_poll(channel, ring_budget);
2129 } while ((processed < budget) && (processed != last_processed));
2131 /* If we processed everything, we are done */
2132 if (processed < budget) {
2133 /* Turn off polling */
2134 napi_complete(napi);
2136 /* Enable Tx and Rx interrupts */
2137 xgbe_enable_rx_tx_ints(pdata);
2140 DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2145 void xgbe_dump_tx_desc(struct xgbe_ring *ring, unsigned int idx,
2146 unsigned int count, unsigned int flag)
2148 struct xgbe_ring_data *rdata;
2149 struct xgbe_ring_desc *rdesc;
2152 rdata = XGBE_GET_DESC_DATA(ring, idx);
2153 rdesc = rdata->rdesc;
2154 pr_alert("TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2155 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2156 le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2157 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2162 void xgbe_dump_rx_desc(struct xgbe_ring *ring, struct xgbe_ring_desc *desc,
2165 pr_alert("RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", idx,
2166 le32_to_cpu(desc->desc0), le32_to_cpu(desc->desc1),
2167 le32_to_cpu(desc->desc2), le32_to_cpu(desc->desc3));
2170 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2172 struct ethhdr *eth = (struct ethhdr *)skb->data;
2173 unsigned char *buf = skb->data;
2174 unsigned char buffer[128];
2177 netdev_alert(netdev, "\n************** SKB dump ****************\n");
2179 netdev_alert(netdev, "%s packet of %d bytes\n",
2180 (tx_rx ? "TX" : "RX"), skb->len);
2182 netdev_alert(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2183 netdev_alert(netdev, "Src MAC addr: %pM\n", eth->h_source);
2184 netdev_alert(netdev, "Protocol: 0x%04hx\n", ntohs(eth->h_proto));
2186 for (i = 0, j = 0; i < skb->len;) {
2187 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx",
2190 if ((i % 32) == 0) {
2191 netdev_alert(netdev, " 0x%04x: %s\n", i - 32, buffer);
2193 } else if ((i % 16) == 0) {
2196 } else if ((i % 4) == 0) {
2201 netdev_alert(netdev, " 0x%04x: %s\n", i - (i % 32), buffer);
2203 netdev_alert(netdev, "\n************** SKB dump ****************\n");