2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
120 #include <linux/dma-mapping.h>
121 #include <linux/netdevice.h>
122 #include <linux/workqueue.h>
123 #include <linux/phy.h>
124 #include <linux/if_vlan.h>
125 #include <linux/bitops.h>
126 #include <linux/ptp_clock_kernel.h>
127 #include <linux/clocksource.h>
128 #include <linux/net_tstamp.h>
129 #include <net/dcbnl.h>
131 #define XGBE_DRV_NAME "amd-xgbe"
132 #define XGBE_DRV_VERSION "1.0.0-a"
133 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
135 /* Descriptor related defines */
136 #define XGBE_TX_DESC_CNT 512
137 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
138 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
139 #define XGBE_RX_DESC_CNT 512
141 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
143 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
144 #define XGBE_RX_BUF_ALIGN 64
145 #define XGBE_SKB_ALLOC_SIZE 256
146 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
148 #define XGBE_MAX_DMA_CHANNELS 16
149 #define XGBE_MAX_QUEUES 16
150 #define XGBE_DMA_STOP_TIMEOUT 5
152 /* DMA cache settings - Outer sharable, write-back, write-allocate */
153 #define XGBE_DMA_OS_AXDOMAIN 0x2
154 #define XGBE_DMA_OS_ARCACHE 0xb
155 #define XGBE_DMA_OS_AWCACHE 0xf
157 /* DMA cache settings - System, no caches used */
158 #define XGBE_DMA_SYS_AXDOMAIN 0x3
159 #define XGBE_DMA_SYS_ARCACHE 0x0
160 #define XGBE_DMA_SYS_AWCACHE 0x0
162 #define XGBE_DMA_INTERRUPT_MASK 0x31c7
164 #define XGMAC_MIN_PACKET 60
165 #define XGMAC_STD_PACKET_MTU 1500
166 #define XGMAC_MAX_STD_PACKET 1518
167 #define XGMAC_JUMBO_PACKET_MTU 9000
168 #define XGMAC_MAX_JUMBO_PACKET 9018
170 /* MDIO bus phy name */
171 #define XGBE_PHY_NAME "amd_xgbe_phy"
174 /* Device-tree clock names */
175 #define XGBE_DMA_CLOCK "dma_clk"
176 #define XGBE_PTP_CLOCK "ptp_clk"
177 #define XGBE_DMA_IRQS "amd,per-channel-interrupt"
179 /* Timestamp support - values based on 50MHz PTP clock
182 #define XGBE_TSTAMP_SSINC 20
183 #define XGBE_TSTAMP_SNSINC 0
185 /* Driver PMT macros */
186 #define XGMAC_DRIVER_CONTEXT 1
187 #define XGMAC_IOCTL_CONTEXT 2
189 #define XGBE_FIFO_MAX 81920
190 #define XGBE_FIFO_SIZE_B(x) (x)
191 #define XGBE_FIFO_SIZE_KB(x) (x * 1024)
193 #define XGBE_TC_MIN_QUANTUM 10
195 /* Helper macro for descriptor handling
196 * Always use XGBE_GET_DESC_DATA to access the descriptor data
197 * since the index is free-running and needs to be and-ed
198 * with the descriptor count value of the ring to index to
199 * the proper descriptor data.
201 #define XGBE_GET_DESC_DATA(_ring, _idx) \
203 ((_idx) & ((_ring)->rdesc_count - 1)))
205 /* Default coalescing parameters */
206 #define XGMAC_INIT_DMA_TX_USECS 50
207 #define XGMAC_INIT_DMA_TX_FRAMES 25
209 #define XGMAC_MAX_DMA_RIWT 0xff
210 #define XGMAC_INIT_DMA_RX_USECS 30
211 #define XGMAC_INIT_DMA_RX_FRAMES 25
213 /* Flow control queue count */
214 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
216 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
217 #define XGBE_MAC_HASH_TABLE_SIZE 8
219 /* Receive Side Scaling */
220 #define XGBE_RSS_HASH_KEY_SIZE 40
221 #define XGBE_RSS_MAX_TABLE_SIZE 256
222 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0
223 #define XGBE_RSS_HASH_KEY_TYPE 1
225 struct xgbe_prv_data;
227 struct xgbe_packet_data {
228 unsigned int attributes;
232 unsigned int rdesc_count;
235 unsigned int header_len;
236 unsigned int tcp_header_len;
237 unsigned int tcp_payload_len;
240 unsigned short vlan_ctag;
245 enum pkt_hash_types rss_hash_type;
248 /* Common Rx and Tx descriptor mapping */
249 struct xgbe_ring_desc {
256 /* Page allocation related values */
257 struct xgbe_page_alloc {
259 unsigned int pages_len;
260 unsigned int pages_offset;
262 dma_addr_t pages_dma;
265 /* Ring entry buffer data */
266 struct xgbe_buffer_data {
267 struct xgbe_page_alloc pa;
268 struct xgbe_page_alloc pa_unmap;
271 unsigned int dma_len;
274 /* Tx-related ring data */
275 struct xgbe_tx_ring_data {
276 unsigned int tso_header; /* TSO header indicator */
279 /* Rx-related ring data */
280 struct xgbe_rx_ring_data {
281 struct xgbe_buffer_data hdr; /* Header locations */
282 struct xgbe_buffer_data buf; /* Payload locations */
284 unsigned short hdr_len; /* Length of received header */
285 unsigned short len; /* Length of received packet */
288 /* Structure used to hold information related to the descriptor
289 * and the packet associated with the descriptor (always use
290 * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
292 struct xgbe_ring_data {
293 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
294 dma_addr_t rdesc_dma; /* DMA address of descriptor */
296 struct sk_buff *skb; /* Virtual address of SKB */
297 dma_addr_t skb_dma; /* DMA address of SKB data */
298 unsigned int skb_dma_len; /* Length of SKB DMA area */
300 struct xgbe_tx_ring_data tx; /* Tx-related data */
301 struct xgbe_rx_ring_data rx; /* Rx-related data */
303 unsigned int interrupt; /* Interrupt indicator */
305 unsigned int mapped_as_page;
307 /* Incomplete receive save location. If the budget is exhausted
308 * or the last descriptor (last normal descriptor or a following
309 * context descriptor) has not been DMA'd yet the current state
310 * of the receive processing needs to be saved.
312 unsigned int state_saved;
314 unsigned int incomplete;
315 unsigned int context_next;
323 /* Ring lock - used just for TX rings at the moment */
326 /* Per packet related information */
327 struct xgbe_packet_data packet_data;
329 /* Virtual/DMA addresses and count of allocated descriptor memory */
330 struct xgbe_ring_desc *rdesc;
331 dma_addr_t rdesc_dma;
332 unsigned int rdesc_count;
334 /* Array of descriptor data corresponding the descriptor memory
335 * (always use the XGBE_GET_DESC_DATA macro to access this data)
337 struct xgbe_ring_data *rdata;
339 /* Page allocation for RX buffers */
340 struct xgbe_page_alloc rx_hdr_pa;
341 struct xgbe_page_alloc rx_buf_pa;
344 * cur - Tx: index of descriptor to be used for current transfer
345 * Rx: index of descriptor to check for packet availability
346 * dirty - Tx: index of descriptor to check for transfer complete
347 * Rx: count of descriptors in which a packet has been received
348 * (used with skb_realloc_index to refresh the ring)
353 /* Coalesce frame count used for interrupt bit setting */
354 unsigned int coalesce_count;
358 unsigned int queue_stopped;
359 unsigned short cur_mss;
360 unsigned short cur_vlan_ctag;
364 unsigned int realloc_index;
365 unsigned int realloc_threshold;
368 } ____cacheline_aligned;
370 /* Structure used to describe the descriptor rings associated with
373 struct xgbe_channel {
376 /* Address of private data area for device */
377 struct xgbe_prv_data *pdata;
379 /* Queue index and base address of queue's DMA registers */
380 unsigned int queue_index;
381 void __iomem *dma_regs;
383 /* Per channel interrupt irq number */
386 /* Netdev related settings */
387 struct napi_struct napi;
389 unsigned int saved_ier;
391 unsigned int tx_timer_active;
392 struct hrtimer tx_timer;
394 struct xgbe_ring *tx_ring;
395 struct xgbe_ring *rx_ring;
396 } ____cacheline_aligned;
399 XGMAC_INT_DMA_CH_SR_TI,
400 XGMAC_INT_DMA_CH_SR_TPS,
401 XGMAC_INT_DMA_CH_SR_TBU,
402 XGMAC_INT_DMA_CH_SR_RI,
403 XGMAC_INT_DMA_CH_SR_RBU,
404 XGMAC_INT_DMA_CH_SR_RPS,
405 XGMAC_INT_DMA_CH_SR_TI_RI,
406 XGMAC_INT_DMA_CH_SR_FBE,
410 enum xgbe_int_state {
411 XGMAC_INT_STATE_SAVE,
412 XGMAC_INT_STATE_RESTORE,
415 enum xgbe_mtl_fifo_size {
416 XGMAC_MTL_FIFO_SIZE_256 = 0x00,
417 XGMAC_MTL_FIFO_SIZE_512 = 0x01,
418 XGMAC_MTL_FIFO_SIZE_1K = 0x03,
419 XGMAC_MTL_FIFO_SIZE_2K = 0x07,
420 XGMAC_MTL_FIFO_SIZE_4K = 0x0f,
421 XGMAC_MTL_FIFO_SIZE_8K = 0x1f,
422 XGMAC_MTL_FIFO_SIZE_16K = 0x3f,
423 XGMAC_MTL_FIFO_SIZE_32K = 0x7f,
424 XGMAC_MTL_FIFO_SIZE_64K = 0xff,
425 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
426 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
429 struct xgbe_mmc_stats {
433 u64 txbroadcastframes_g;
434 u64 txmulticastframes_g;
436 u64 tx65to127octets_gb;
437 u64 tx128to255octets_gb;
438 u64 tx256to511octets_gb;
439 u64 tx512to1023octets_gb;
440 u64 tx1024tomaxoctets_gb;
441 u64 txunicastframes_gb;
442 u64 txmulticastframes_gb;
443 u64 txbroadcastframes_gb;
444 u64 txunderflowerror;
454 u64 rxbroadcastframes_g;
455 u64 rxmulticastframes_g;
462 u64 rx65to127octets_gb;
463 u64 rx128to255octets_gb;
464 u64 rx256to511octets_gb;
465 u64 rx512to1023octets_gb;
466 u64 rx1024tomaxoctets_gb;
467 u64 rxunicastframes_g;
469 u64 rxoutofrangetype;
477 int (*tx_complete)(struct xgbe_ring_desc *);
479 int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
480 int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
481 int (*add_mac_addresses)(struct xgbe_prv_data *);
482 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
484 int (*enable_rx_csum)(struct xgbe_prv_data *);
485 int (*disable_rx_csum)(struct xgbe_prv_data *);
487 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
488 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
489 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
490 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
491 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
493 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
494 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
495 int (*set_gmii_speed)(struct xgbe_prv_data *);
496 int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
497 int (*set_xgmii_speed)(struct xgbe_prv_data *);
499 void (*enable_tx)(struct xgbe_prv_data *);
500 void (*disable_tx)(struct xgbe_prv_data *);
501 void (*enable_rx)(struct xgbe_prv_data *);
502 void (*disable_rx)(struct xgbe_prv_data *);
504 void (*powerup_tx)(struct xgbe_prv_data *);
505 void (*powerdown_tx)(struct xgbe_prv_data *);
506 void (*powerup_rx)(struct xgbe_prv_data *);
507 void (*powerdown_rx)(struct xgbe_prv_data *);
509 int (*init)(struct xgbe_prv_data *);
510 int (*exit)(struct xgbe_prv_data *);
512 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
513 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
514 void (*dev_xmit)(struct xgbe_channel *);
515 int (*dev_read)(struct xgbe_channel *);
516 void (*tx_desc_init)(struct xgbe_channel *);
517 void (*rx_desc_init)(struct xgbe_channel *);
518 void (*rx_desc_reset)(struct xgbe_ring_data *);
519 void (*tx_desc_reset)(struct xgbe_ring_data *);
520 int (*is_last_desc)(struct xgbe_ring_desc *);
521 int (*is_context_desc)(struct xgbe_ring_desc *);
524 int (*config_tx_flow_control)(struct xgbe_prv_data *);
525 int (*config_rx_flow_control)(struct xgbe_prv_data *);
527 /* For RX coalescing */
528 int (*config_rx_coalesce)(struct xgbe_prv_data *);
529 int (*config_tx_coalesce)(struct xgbe_prv_data *);
530 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
531 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
533 /* For RX and TX threshold config */
534 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
535 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
537 /* For RX and TX Store and Forward Mode config */
538 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
539 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
541 /* For TX DMA Operate on Second Frame config */
542 int (*config_osp_mode)(struct xgbe_prv_data *);
544 /* For RX and TX PBL config */
545 int (*config_rx_pbl_val)(struct xgbe_prv_data *);
546 int (*get_rx_pbl_val)(struct xgbe_prv_data *);
547 int (*config_tx_pbl_val)(struct xgbe_prv_data *);
548 int (*get_tx_pbl_val)(struct xgbe_prv_data *);
549 int (*config_pblx8)(struct xgbe_prv_data *);
551 /* For MMC statistics */
552 void (*rx_mmc_int)(struct xgbe_prv_data *);
553 void (*tx_mmc_int)(struct xgbe_prv_data *);
554 void (*read_mmc_stats)(struct xgbe_prv_data *);
556 /* For Timestamp config */
557 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
558 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
559 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
561 u64 (*get_tstamp_time)(struct xgbe_prv_data *);
562 u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
564 /* For Data Center Bridging config */
565 void (*config_dcb_tc)(struct xgbe_prv_data *);
566 void (*config_dcb_pfc)(struct xgbe_prv_data *);
568 /* For Receive Side Scaling */
569 int (*enable_rss)(struct xgbe_prv_data *);
570 int (*disable_rss)(struct xgbe_prv_data *);
571 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
572 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
575 struct xgbe_desc_if {
576 int (*alloc_ring_resources)(struct xgbe_prv_data *);
577 void (*free_ring_resources)(struct xgbe_prv_data *);
578 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
579 void (*realloc_rx_buffer)(struct xgbe_channel *);
580 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
581 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
582 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
585 /* This structure contains flags that indicate what hardware features
586 * or configurations are present in the device.
588 struct xgbe_hw_features {
590 unsigned int version;
592 /* HW Feature Register0 */
593 unsigned int gmii; /* 1000 Mbps support */
594 unsigned int vlhash; /* VLAN Hash Filter */
595 unsigned int sma; /* SMA(MDIO) Interface */
596 unsigned int rwk; /* PMT remote wake-up packet */
597 unsigned int mgk; /* PMT magic packet */
598 unsigned int mmc; /* RMON module */
599 unsigned int aoe; /* ARP Offload */
600 unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */
601 unsigned int eee; /* Energy Efficient Ethernet */
602 unsigned int tx_coe; /* Tx Checksum Offload */
603 unsigned int rx_coe; /* Rx Checksum Offload */
604 unsigned int addn_mac; /* Additional MAC Addresses */
605 unsigned int ts_src; /* Timestamp Source */
606 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
608 /* HW Feature Register1 */
609 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
610 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
611 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
612 unsigned int dcb; /* DCB Feature */
613 unsigned int sph; /* Split Header Feature */
614 unsigned int tso; /* TCP Segmentation Offload */
615 unsigned int dma_debug; /* DMA Debug Registers */
616 unsigned int rss; /* Receive Side Scaling */
617 unsigned int tc_cnt; /* Number of Traffic Classes */
618 unsigned int hash_table_size; /* Hash Table Size */
619 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
621 /* HW Feature Register2 */
622 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
623 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
624 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
625 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
626 unsigned int pps_out_num; /* Number of PPS outputs */
627 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
630 struct xgbe_prv_data {
631 struct net_device *netdev;
632 struct platform_device *pdev;
635 /* XGMAC/XPCS related mmio registers */
636 void __iomem *xgmac_regs; /* XGMAC CSRs */
637 void __iomem *xpcs_regs; /* XPCS MMD registers */
639 /* Overall device lock */
642 /* XPCS indirect addressing mutex */
643 struct mutex xpcs_mutex;
645 /* RSS addressing mutex */
646 struct mutex rss_mutex;
649 unsigned int per_channel_irq;
651 struct xgbe_hw_if hw_if;
652 struct xgbe_desc_if desc_if;
654 /* AXI DMA settings */
655 unsigned int axdomain;
656 unsigned int arcache;
657 unsigned int awcache;
659 /* Rings for Tx/Rx on a DMA channel */
660 struct xgbe_channel *channel;
661 unsigned int channel_count;
662 unsigned int tx_ring_count;
663 unsigned int tx_desc_count;
664 unsigned int rx_ring_count;
665 unsigned int rx_desc_count;
667 unsigned int tx_q_count;
668 unsigned int rx_q_count;
670 /* Tx/Rx common settings */
674 unsigned int tx_sf_mode;
675 unsigned int tx_threshold;
677 unsigned int tx_osp_mode;
680 unsigned int rx_sf_mode;
681 unsigned int rx_threshold;
684 /* Tx coalescing settings */
685 unsigned int tx_usecs;
686 unsigned int tx_frames;
688 /* Rx coalescing settings */
689 unsigned int rx_riwt;
690 unsigned int rx_frames;
692 /* Current Rx buffer size */
693 unsigned int rx_buf_size;
695 /* Flow control settings */
696 unsigned int pause_autoneg;
697 unsigned int tx_pause;
698 unsigned int rx_pause;
700 /* Receive Side Scaling settings */
701 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
702 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
706 struct module *phy_module;
710 struct phy_device *phydev;
714 /* Current PHY settings */
715 phy_interface_t phy_mode;
718 unsigned int phy_tx_pause;
719 unsigned int phy_rx_pause;
721 /* Netdev related settings */
722 netdev_features_t netdev_features;
723 struct napi_struct napi;
724 struct xgbe_mmc_stats mmc_stats;
726 /* Filtering support */
727 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
733 /* Timestamp support */
734 spinlock_t tstamp_lock;
735 struct ptp_clock_info ptp_clock_info;
736 struct ptp_clock *ptp_clock;
737 struct hwtstamp_config tstamp_config;
738 struct cyclecounter tstamp_cc;
739 struct timecounter tstamp_tc;
740 unsigned int tstamp_addend;
741 struct work_struct tx_tstamp_work;
742 struct sk_buff *tx_tstamp_skb;
746 struct ieee_ets *ets;
747 struct ieee_pfc *pfc;
748 unsigned int q2tc_map[XGBE_MAX_QUEUES];
749 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
751 /* Hardware features of the device */
752 struct xgbe_hw_features hw_feat;
754 /* Device restart work structure */
755 struct work_struct restart_work;
757 /* Keeps track of power mode */
758 unsigned int power_down;
760 #ifdef CONFIG_DEBUG_FS
761 struct dentry *xgbe_debugfs;
763 unsigned int debugfs_xgmac_reg;
765 unsigned int debugfs_xpcs_mmd;
766 unsigned int debugfs_xpcs_reg;
770 /* Function prototypes*/
772 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
773 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
774 struct net_device_ops *xgbe_get_netdev_ops(void);
775 struct ethtool_ops *xgbe_get_ethtool_ops(void);
776 #ifdef CONFIG_AMD_XGBE_DCB
777 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
780 int xgbe_mdio_register(struct xgbe_prv_data *);
781 void xgbe_mdio_unregister(struct xgbe_prv_data *);
782 void xgbe_dump_phy_registers(struct xgbe_prv_data *);
783 void xgbe_ptp_register(struct xgbe_prv_data *);
784 void xgbe_ptp_unregister(struct xgbe_prv_data *);
785 void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
787 void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
789 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
790 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
791 int xgbe_powerup(struct net_device *, unsigned int);
792 int xgbe_powerdown(struct net_device *, unsigned int);
793 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
794 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
796 #ifdef CONFIG_DEBUG_FS
797 void xgbe_debugfs_init(struct xgbe_prv_data *);
798 void xgbe_debugfs_exit(struct xgbe_prv_data *);
800 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
801 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
802 #endif /* CONFIG_DEBUG_FS */
804 /* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
806 #define XGMAC_ENABLE_TX_DESC_DUMP
807 #define XGMAC_ENABLE_RX_DESC_DUMP
810 /* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
812 #define XGMAC_ENABLE_TX_PKT_DUMP
813 #define XGMAC_ENABLE_RX_PKT_DUMP
816 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
822 /* For debug prints */
824 #define DBGPR(x...) pr_alert(x)
825 #define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x)
827 #define DBGPR(x...) do { } while (0)
828 #define DBGPHY_REGS(x...) do { } while (0)
832 #define DBGPR_MDIO(x...) pr_alert(x)
834 #define DBGPR_MDIO(x...) do { } while (0)