2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
120 #include <linux/dma-mapping.h>
121 #include <linux/netdevice.h>
122 #include <linux/workqueue.h>
123 #include <linux/phy.h>
124 #include <linux/if_vlan.h>
125 #include <linux/bitops.h>
126 #include <linux/ptp_clock_kernel.h>
127 #include <linux/clocksource.h>
128 #include <linux/net_tstamp.h>
129 #include <net/dcbnl.h>
131 #define XGBE_DRV_NAME "amd-xgbe"
132 #define XGBE_DRV_VERSION "1.0.0-a"
133 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
135 /* Descriptor related defines */
136 #define XGBE_TX_DESC_CNT 512
137 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
138 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
139 #define XGBE_RX_DESC_CNT 512
141 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
143 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
144 #define XGBE_RX_BUF_ALIGN 64
145 #define XGBE_SKB_ALLOC_SIZE 256
146 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
148 #define XGBE_MAX_DMA_CHANNELS 16
149 #define XGBE_MAX_QUEUES 16
150 #define XGBE_DMA_STOP_TIMEOUT 5
152 /* DMA cache settings - Outer sharable, write-back, write-allocate */
153 #define XGBE_DMA_OS_AXDOMAIN 0x2
154 #define XGBE_DMA_OS_ARCACHE 0xb
155 #define XGBE_DMA_OS_AWCACHE 0xf
157 /* DMA cache settings - System, no caches used */
158 #define XGBE_DMA_SYS_AXDOMAIN 0x3
159 #define XGBE_DMA_SYS_ARCACHE 0x0
160 #define XGBE_DMA_SYS_AWCACHE 0x0
162 #define XGBE_DMA_INTERRUPT_MASK 0x31c7
164 #define XGMAC_MIN_PACKET 60
165 #define XGMAC_STD_PACKET_MTU 1500
166 #define XGMAC_MAX_STD_PACKET 1518
167 #define XGMAC_JUMBO_PACKET_MTU 9000
168 #define XGMAC_MAX_JUMBO_PACKET 9018
170 /* MDIO bus phy name */
171 #define XGBE_PHY_NAME "amd_xgbe_phy"
174 /* Device-tree clock names */
175 #define XGBE_DMA_CLOCK "dma_clk"
176 #define XGBE_PTP_CLOCK "ptp_clk"
177 #define XGBE_DMA_IRQS "amd,per-channel-interrupt"
179 /* Timestamp support - values based on 50MHz PTP clock
182 #define XGBE_TSTAMP_SSINC 20
183 #define XGBE_TSTAMP_SNSINC 0
185 /* Driver PMT macros */
186 #define XGMAC_DRIVER_CONTEXT 1
187 #define XGMAC_IOCTL_CONTEXT 2
189 #define XGBE_FIFO_MAX 81920
190 #define XGBE_FIFO_SIZE_B(x) (x)
191 #define XGBE_FIFO_SIZE_KB(x) (x * 1024)
193 #define XGBE_TC_MIN_QUANTUM 10
195 /* Helper macro for descriptor handling
196 * Always use XGBE_GET_DESC_DATA to access the descriptor data
197 * since the index is free-running and needs to be and-ed
198 * with the descriptor count value of the ring to index to
199 * the proper descriptor data.
201 #define XGBE_GET_DESC_DATA(_ring, _idx) \
203 ((_idx) & ((_ring)->rdesc_count - 1)))
205 /* Default coalescing parameters */
206 #define XGMAC_INIT_DMA_TX_USECS 50
207 #define XGMAC_INIT_DMA_TX_FRAMES 25
209 #define XGMAC_MAX_DMA_RIWT 0xff
210 #define XGMAC_INIT_DMA_RX_USECS 30
211 #define XGMAC_INIT_DMA_RX_FRAMES 25
213 /* Flow control queue count */
214 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
216 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
217 #define XGBE_MAC_HASH_TABLE_SIZE 8
219 /* Receive Side Scaling */
220 #define XGBE_RSS_HASH_KEY_SIZE 40
221 #define XGBE_RSS_MAX_TABLE_SIZE 256
222 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0
223 #define XGBE_RSS_HASH_KEY_TYPE 1
225 struct xgbe_prv_data;
227 struct xgbe_packet_data {
228 unsigned int attributes;
232 unsigned int rdesc_count;
235 unsigned int header_len;
236 unsigned int tcp_header_len;
237 unsigned int tcp_payload_len;
240 unsigned short vlan_ctag;
245 enum pkt_hash_types rss_hash_type;
247 unsigned int tx_packets;
248 unsigned int tx_bytes;
251 /* Common Rx and Tx descriptor mapping */
252 struct xgbe_ring_desc {
259 /* Page allocation related values */
260 struct xgbe_page_alloc {
262 unsigned int pages_len;
263 unsigned int pages_offset;
265 dma_addr_t pages_dma;
268 /* Ring entry buffer data */
269 struct xgbe_buffer_data {
270 struct xgbe_page_alloc pa;
271 struct xgbe_page_alloc pa_unmap;
274 unsigned int dma_len;
277 /* Tx-related ring data */
278 struct xgbe_tx_ring_data {
279 unsigned int tso_header; /* TSO header indicator */
280 unsigned int packets; /* BQL packet count */
281 unsigned int bytes; /* BQL byte count */
284 /* Rx-related ring data */
285 struct xgbe_rx_ring_data {
286 struct xgbe_buffer_data hdr; /* Header locations */
287 struct xgbe_buffer_data buf; /* Payload locations */
289 unsigned short hdr_len; /* Length of received header */
290 unsigned short len; /* Length of received packet */
293 /* Structure used to hold information related to the descriptor
294 * and the packet associated with the descriptor (always use
295 * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
297 struct xgbe_ring_data {
298 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
299 dma_addr_t rdesc_dma; /* DMA address of descriptor */
301 struct sk_buff *skb; /* Virtual address of SKB */
302 dma_addr_t skb_dma; /* DMA address of SKB data */
303 unsigned int skb_dma_len; /* Length of SKB DMA area */
305 struct xgbe_tx_ring_data tx; /* Tx-related data */
306 struct xgbe_rx_ring_data rx; /* Rx-related data */
308 unsigned int interrupt; /* Interrupt indicator */
310 unsigned int mapped_as_page;
312 /* Incomplete receive save location. If the budget is exhausted
313 * or the last descriptor (last normal descriptor or a following
314 * context descriptor) has not been DMA'd yet the current state
315 * of the receive processing needs to be saved.
317 unsigned int state_saved;
319 unsigned int incomplete;
320 unsigned int context_next;
328 /* Ring lock - used just for TX rings at the moment */
331 /* Per packet related information */
332 struct xgbe_packet_data packet_data;
334 /* Virtual/DMA addresses and count of allocated descriptor memory */
335 struct xgbe_ring_desc *rdesc;
336 dma_addr_t rdesc_dma;
337 unsigned int rdesc_count;
339 /* Array of descriptor data corresponding the descriptor memory
340 * (always use the XGBE_GET_DESC_DATA macro to access this data)
342 struct xgbe_ring_data *rdata;
344 /* Page allocation for RX buffers */
345 struct xgbe_page_alloc rx_hdr_pa;
346 struct xgbe_page_alloc rx_buf_pa;
349 * cur - Tx: index of descriptor to be used for current transfer
350 * Rx: index of descriptor to check for packet availability
351 * dirty - Tx: index of descriptor to check for transfer complete
352 * Rx: count of descriptors in which a packet has been received
353 * (used with skb_realloc_index to refresh the ring)
358 /* Coalesce frame count used for interrupt bit setting */
359 unsigned int coalesce_count;
363 unsigned int queue_stopped;
364 unsigned short cur_mss;
365 unsigned short cur_vlan_ctag;
369 unsigned int realloc_index;
370 unsigned int realloc_threshold;
373 } ____cacheline_aligned;
375 /* Structure used to describe the descriptor rings associated with
378 struct xgbe_channel {
381 /* Address of private data area for device */
382 struct xgbe_prv_data *pdata;
384 /* Queue index and base address of queue's DMA registers */
385 unsigned int queue_index;
386 void __iomem *dma_regs;
388 /* Per channel interrupt irq number */
391 /* Netdev related settings */
392 struct napi_struct napi;
394 unsigned int saved_ier;
396 unsigned int tx_timer_active;
397 struct hrtimer tx_timer;
399 struct xgbe_ring *tx_ring;
400 struct xgbe_ring *rx_ring;
401 } ____cacheline_aligned;
404 XGMAC_INT_DMA_CH_SR_TI,
405 XGMAC_INT_DMA_CH_SR_TPS,
406 XGMAC_INT_DMA_CH_SR_TBU,
407 XGMAC_INT_DMA_CH_SR_RI,
408 XGMAC_INT_DMA_CH_SR_RBU,
409 XGMAC_INT_DMA_CH_SR_RPS,
410 XGMAC_INT_DMA_CH_SR_TI_RI,
411 XGMAC_INT_DMA_CH_SR_FBE,
415 enum xgbe_int_state {
416 XGMAC_INT_STATE_SAVE,
417 XGMAC_INT_STATE_RESTORE,
420 enum xgbe_mtl_fifo_size {
421 XGMAC_MTL_FIFO_SIZE_256 = 0x00,
422 XGMAC_MTL_FIFO_SIZE_512 = 0x01,
423 XGMAC_MTL_FIFO_SIZE_1K = 0x03,
424 XGMAC_MTL_FIFO_SIZE_2K = 0x07,
425 XGMAC_MTL_FIFO_SIZE_4K = 0x0f,
426 XGMAC_MTL_FIFO_SIZE_8K = 0x1f,
427 XGMAC_MTL_FIFO_SIZE_16K = 0x3f,
428 XGMAC_MTL_FIFO_SIZE_32K = 0x7f,
429 XGMAC_MTL_FIFO_SIZE_64K = 0xff,
430 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
431 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
434 struct xgbe_mmc_stats {
438 u64 txbroadcastframes_g;
439 u64 txmulticastframes_g;
441 u64 tx65to127octets_gb;
442 u64 tx128to255octets_gb;
443 u64 tx256to511octets_gb;
444 u64 tx512to1023octets_gb;
445 u64 tx1024tomaxoctets_gb;
446 u64 txunicastframes_gb;
447 u64 txmulticastframes_gb;
448 u64 txbroadcastframes_gb;
449 u64 txunderflowerror;
459 u64 rxbroadcastframes_g;
460 u64 rxmulticastframes_g;
467 u64 rx65to127octets_gb;
468 u64 rx128to255octets_gb;
469 u64 rx256to511octets_gb;
470 u64 rx512to1023octets_gb;
471 u64 rx1024tomaxoctets_gb;
472 u64 rxunicastframes_g;
474 u64 rxoutofrangetype;
482 int (*tx_complete)(struct xgbe_ring_desc *);
484 int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
485 int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
486 int (*add_mac_addresses)(struct xgbe_prv_data *);
487 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
489 int (*enable_rx_csum)(struct xgbe_prv_data *);
490 int (*disable_rx_csum)(struct xgbe_prv_data *);
492 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
493 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
494 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
495 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
496 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
498 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
499 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
500 int (*set_gmii_speed)(struct xgbe_prv_data *);
501 int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
502 int (*set_xgmii_speed)(struct xgbe_prv_data *);
504 void (*enable_tx)(struct xgbe_prv_data *);
505 void (*disable_tx)(struct xgbe_prv_data *);
506 void (*enable_rx)(struct xgbe_prv_data *);
507 void (*disable_rx)(struct xgbe_prv_data *);
509 void (*powerup_tx)(struct xgbe_prv_data *);
510 void (*powerdown_tx)(struct xgbe_prv_data *);
511 void (*powerup_rx)(struct xgbe_prv_data *);
512 void (*powerdown_rx)(struct xgbe_prv_data *);
514 int (*init)(struct xgbe_prv_data *);
515 int (*exit)(struct xgbe_prv_data *);
517 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
518 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
519 void (*dev_xmit)(struct xgbe_channel *);
520 int (*dev_read)(struct xgbe_channel *);
521 void (*tx_desc_init)(struct xgbe_channel *);
522 void (*rx_desc_init)(struct xgbe_channel *);
523 void (*rx_desc_reset)(struct xgbe_ring_data *);
524 void (*tx_desc_reset)(struct xgbe_ring_data *);
525 int (*is_last_desc)(struct xgbe_ring_desc *);
526 int (*is_context_desc)(struct xgbe_ring_desc *);
529 int (*config_tx_flow_control)(struct xgbe_prv_data *);
530 int (*config_rx_flow_control)(struct xgbe_prv_data *);
532 /* For RX coalescing */
533 int (*config_rx_coalesce)(struct xgbe_prv_data *);
534 int (*config_tx_coalesce)(struct xgbe_prv_data *);
535 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
536 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
538 /* For RX and TX threshold config */
539 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
540 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
542 /* For RX and TX Store and Forward Mode config */
543 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
544 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
546 /* For TX DMA Operate on Second Frame config */
547 int (*config_osp_mode)(struct xgbe_prv_data *);
549 /* For RX and TX PBL config */
550 int (*config_rx_pbl_val)(struct xgbe_prv_data *);
551 int (*get_rx_pbl_val)(struct xgbe_prv_data *);
552 int (*config_tx_pbl_val)(struct xgbe_prv_data *);
553 int (*get_tx_pbl_val)(struct xgbe_prv_data *);
554 int (*config_pblx8)(struct xgbe_prv_data *);
556 /* For MMC statistics */
557 void (*rx_mmc_int)(struct xgbe_prv_data *);
558 void (*tx_mmc_int)(struct xgbe_prv_data *);
559 void (*read_mmc_stats)(struct xgbe_prv_data *);
561 /* For Timestamp config */
562 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
563 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
564 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
566 u64 (*get_tstamp_time)(struct xgbe_prv_data *);
567 u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
569 /* For Data Center Bridging config */
570 void (*config_dcb_tc)(struct xgbe_prv_data *);
571 void (*config_dcb_pfc)(struct xgbe_prv_data *);
573 /* For Receive Side Scaling */
574 int (*enable_rss)(struct xgbe_prv_data *);
575 int (*disable_rss)(struct xgbe_prv_data *);
576 int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
577 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
580 struct xgbe_desc_if {
581 int (*alloc_ring_resources)(struct xgbe_prv_data *);
582 void (*free_ring_resources)(struct xgbe_prv_data *);
583 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
584 void (*realloc_rx_buffer)(struct xgbe_channel *);
585 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
586 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
587 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
590 /* This structure contains flags that indicate what hardware features
591 * or configurations are present in the device.
593 struct xgbe_hw_features {
595 unsigned int version;
597 /* HW Feature Register0 */
598 unsigned int gmii; /* 1000 Mbps support */
599 unsigned int vlhash; /* VLAN Hash Filter */
600 unsigned int sma; /* SMA(MDIO) Interface */
601 unsigned int rwk; /* PMT remote wake-up packet */
602 unsigned int mgk; /* PMT magic packet */
603 unsigned int mmc; /* RMON module */
604 unsigned int aoe; /* ARP Offload */
605 unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */
606 unsigned int eee; /* Energy Efficient Ethernet */
607 unsigned int tx_coe; /* Tx Checksum Offload */
608 unsigned int rx_coe; /* Rx Checksum Offload */
609 unsigned int addn_mac; /* Additional MAC Addresses */
610 unsigned int ts_src; /* Timestamp Source */
611 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
613 /* HW Feature Register1 */
614 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
615 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
616 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
617 unsigned int dcb; /* DCB Feature */
618 unsigned int sph; /* Split Header Feature */
619 unsigned int tso; /* TCP Segmentation Offload */
620 unsigned int dma_debug; /* DMA Debug Registers */
621 unsigned int rss; /* Receive Side Scaling */
622 unsigned int tc_cnt; /* Number of Traffic Classes */
623 unsigned int hash_table_size; /* Hash Table Size */
624 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
626 /* HW Feature Register2 */
627 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
628 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
629 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
630 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
631 unsigned int pps_out_num; /* Number of PPS outputs */
632 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
635 struct xgbe_prv_data {
636 struct net_device *netdev;
637 struct platform_device *pdev;
640 /* XGMAC/XPCS related mmio registers */
641 void __iomem *xgmac_regs; /* XGMAC CSRs */
642 void __iomem *xpcs_regs; /* XPCS MMD registers */
644 /* Overall device lock */
647 /* XPCS indirect addressing mutex */
648 struct mutex xpcs_mutex;
650 /* RSS addressing mutex */
651 struct mutex rss_mutex;
654 unsigned int per_channel_irq;
656 struct xgbe_hw_if hw_if;
657 struct xgbe_desc_if desc_if;
659 /* AXI DMA settings */
660 unsigned int axdomain;
661 unsigned int arcache;
662 unsigned int awcache;
664 /* Rings for Tx/Rx on a DMA channel */
665 struct xgbe_channel *channel;
666 unsigned int channel_count;
667 unsigned int tx_ring_count;
668 unsigned int tx_desc_count;
669 unsigned int rx_ring_count;
670 unsigned int rx_desc_count;
672 unsigned int tx_q_count;
673 unsigned int rx_q_count;
675 /* Tx/Rx common settings */
679 unsigned int tx_sf_mode;
680 unsigned int tx_threshold;
682 unsigned int tx_osp_mode;
685 unsigned int rx_sf_mode;
686 unsigned int rx_threshold;
689 /* Tx coalescing settings */
690 unsigned int tx_usecs;
691 unsigned int tx_frames;
693 /* Rx coalescing settings */
694 unsigned int rx_riwt;
695 unsigned int rx_frames;
697 /* Current Rx buffer size */
698 unsigned int rx_buf_size;
700 /* Flow control settings */
701 unsigned int pause_autoneg;
702 unsigned int tx_pause;
703 unsigned int rx_pause;
705 /* Receive Side Scaling settings */
706 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
707 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
711 struct module *phy_module;
715 struct phy_device *phydev;
719 /* Current PHY settings */
720 phy_interface_t phy_mode;
723 unsigned int phy_tx_pause;
724 unsigned int phy_rx_pause;
726 /* Netdev related settings */
727 netdev_features_t netdev_features;
728 struct napi_struct napi;
729 struct xgbe_mmc_stats mmc_stats;
731 /* Filtering support */
732 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
738 /* Timestamp support */
739 spinlock_t tstamp_lock;
740 struct ptp_clock_info ptp_clock_info;
741 struct ptp_clock *ptp_clock;
742 struct hwtstamp_config tstamp_config;
743 struct cyclecounter tstamp_cc;
744 struct timecounter tstamp_tc;
745 unsigned int tstamp_addend;
746 struct work_struct tx_tstamp_work;
747 struct sk_buff *tx_tstamp_skb;
751 struct ieee_ets *ets;
752 struct ieee_pfc *pfc;
753 unsigned int q2tc_map[XGBE_MAX_QUEUES];
754 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
756 /* Hardware features of the device */
757 struct xgbe_hw_features hw_feat;
759 /* Device restart work structure */
760 struct work_struct restart_work;
762 /* Keeps track of power mode */
763 unsigned int power_down;
765 #ifdef CONFIG_DEBUG_FS
766 struct dentry *xgbe_debugfs;
768 unsigned int debugfs_xgmac_reg;
770 unsigned int debugfs_xpcs_mmd;
771 unsigned int debugfs_xpcs_reg;
775 /* Function prototypes*/
777 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
778 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
779 struct net_device_ops *xgbe_get_netdev_ops(void);
780 struct ethtool_ops *xgbe_get_ethtool_ops(void);
781 #ifdef CONFIG_AMD_XGBE_DCB
782 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
785 int xgbe_mdio_register(struct xgbe_prv_data *);
786 void xgbe_mdio_unregister(struct xgbe_prv_data *);
787 void xgbe_dump_phy_registers(struct xgbe_prv_data *);
788 void xgbe_ptp_register(struct xgbe_prv_data *);
789 void xgbe_ptp_unregister(struct xgbe_prv_data *);
790 void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
792 void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
794 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
795 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
796 int xgbe_powerup(struct net_device *, unsigned int);
797 int xgbe_powerdown(struct net_device *, unsigned int);
798 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
799 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
801 #ifdef CONFIG_DEBUG_FS
802 void xgbe_debugfs_init(struct xgbe_prv_data *);
803 void xgbe_debugfs_exit(struct xgbe_prv_data *);
805 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
806 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
807 #endif /* CONFIG_DEBUG_FS */
809 /* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
811 #define XGMAC_ENABLE_TX_DESC_DUMP
812 #define XGMAC_ENABLE_RX_DESC_DUMP
815 /* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
817 #define XGMAC_ENABLE_TX_PKT_DUMP
818 #define XGMAC_ENABLE_RX_PKT_DUMP
821 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
827 /* For debug prints */
829 #define DBGPR(x...) pr_alert(x)
830 #define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x)
832 #define DBGPR(x...) do { } while (0)
833 #define DBGPHY_REGS(x...) do { } while (0)
837 #define DBGPR_MDIO(x...) pr_alert(x)
839 #define DBGPR_MDIO(x...) do { } while (0)