2 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
4 * Registers and bits definitions of ARC EMAC
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/phy.h>
14 #include <linux/clk.h>
16 /* STATUS and ENABLE Register bit masks */
17 #define TXINT_MASK (1<<0) /* Transmit interrupt */
18 #define RXINT_MASK (1<<1) /* Receive interrupt */
19 #define ERR_MASK (1<<2) /* Error interrupt */
20 #define TXCH_MASK (1<<3) /* Transmit chaining error interrupt */
21 #define MSER_MASK (1<<4) /* Missed packet counter error */
22 #define RXCR_MASK (1<<8) /* RXCRCERR counter rolled over */
23 #define RXFR_MASK (1<<9) /* RXFRAMEERR counter rolled over */
24 #define RXFL_MASK (1<<10) /* RXOFLOWERR counter rolled over */
25 #define MDIO_MASK (1<<12) /* MDIO complete interrupt */
26 #define TXPL_MASK (1<<31) /* Force polling of BD by EMAC */
28 /* CONTROL Register bit masks */
29 #define EN_MASK (1<<0) /* VMAC enable */
30 #define TXRN_MASK (1<<3) /* TX enable */
31 #define RXRN_MASK (1<<4) /* RX enable */
32 #define DSBC_MASK (1<<8) /* Disable receive broadcast */
33 #define ENFL_MASK (1<<10) /* Enable Full-duplex */
34 #define PROM_MASK (1<<11) /* Promiscuous mode */
36 /* Buffer descriptor INFO bit masks */
37 #define OWN_MASK (1<<31) /* 0-CPU owns buffer, 1-EMAC owns buffer */
38 #define FIRST_MASK (1<<16) /* First buffer in chain */
39 #define LAST_MASK (1<<17) /* Last buffer in chain */
40 #define LEN_MASK 0x000007FF /* last 11 bits */
48 #define FOR_EMAC OWN_MASK
51 /* ARC EMAC register set combines entries for MAC and MDIO */
69 #define TX_TIMEOUT (400*HZ/1000) /* Transmission timeout */
71 #define ARC_EMAC_NAPI_WEIGHT 40 /* Workload for NAPI */
73 #define EMAC_BUFFER_SIZE 1536 /* EMAC buffer size */
76 * struct arc_emac_bd - EMAC buffer descriptor (BD).
78 * @info: Contains status information on the buffer itself.
79 * @data: 32-bit byte addressable pointer to the packet data.
86 /* Number of Rx/Tx BD's */
90 #define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
91 #define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
94 * struct buffer_state - Stores Rx/Tx buffer state.
95 * @sk_buff: Pointer to socket buffer.
96 * @addr: Start address of DMA-mapped memory region.
97 * @len: Length of DMA-mapped memory region.
101 DEFINE_DMA_UNMAP_ADDR(addr);
102 DEFINE_DMA_UNMAP_LEN(len);
106 * struct arc_emac_priv - Storage of EMAC's private information.
107 * @dev: Pointer to the current device.
108 * @phy_dev: Pointer to attached PHY device.
109 * @bus: Pointer to the current MII bus.
110 * @regs: Base address of EMAC memory-mapped control registers.
111 * @napi: Structure for NAPI.
112 * @rxbd: Pointer to Rx BD ring.
113 * @txbd: Pointer to Tx BD ring.
114 * @rxbd_dma: DMA handle for Rx BD ring.
115 * @txbd_dma: DMA handle for Tx BD ring.
116 * @rx_buff: Storage for Rx buffers states.
117 * @tx_buff: Storage for Tx buffers states.
118 * @txbd_curr: Index of Tx BD to use on the next "ndo_start_xmit".
119 * @txbd_dirty: Index of Tx BD to free on the next Tx interrupt.
120 * @last_rx_bd: Index of the last Rx BD we've got from EMAC.
121 * @link: PHY's last seen link state.
122 * @duplex: PHY's last set duplex mode.
123 * @speed: PHY's last set speed.
125 struct arc_emac_priv {
128 struct phy_device *phy_dev;
134 struct napi_struct napi;
136 struct arc_emac_bd *rxbd;
137 struct arc_emac_bd *txbd;
142 struct buffer_state rx_buff[RX_BD_NUM];
143 struct buffer_state tx_buff[TX_BD_NUM];
144 unsigned int txbd_curr;
145 unsigned int txbd_dirty;
147 unsigned int last_rx_bd;
155 * arc_reg_set - Sets EMAC register with provided value.
156 * @priv: Pointer to ARC EMAC private data structure.
157 * @reg: Register offset from base address.
158 * @value: Value to set in register.
160 static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
162 iowrite32(value, priv->regs + reg * sizeof(int));
166 * arc_reg_get - Gets value of specified EMAC register.
167 * @priv: Pointer to ARC EMAC private data structure.
168 * @reg: Register offset from base address.
170 * returns: Value of requested register.
172 static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
174 return ioread32(priv->regs + reg * sizeof(int));
178 * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
179 * @priv: Pointer to ARC EMAC private data structure.
180 * @reg: Register offset from base address.
181 * @mask: Mask to apply to specified register.
183 * This function reads initial register value, then applies provided mask
184 * to it and then writes register back.
186 static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
188 unsigned int value = arc_reg_get(priv, reg);
189 arc_reg_set(priv, reg, value | mask);
193 * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
194 * @priv: Pointer to ARC EMAC private data structure.
195 * @reg: Register offset from base address.
196 * @mask: Mask to apply to specified register.
198 * This function reads initial register value, then applies provided mask
199 * to it and then writes register back.
201 static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
203 unsigned int value = arc_reg_get(priv, reg);
204 arc_reg_set(priv, reg, value & ~mask);
207 int arc_mdio_probe(struct platform_device *pdev, struct arc_emac_priv *priv);
208 int arc_mdio_remove(struct arc_emac_priv *priv);
210 #endif /* ARC_EMAC_H */