1 /* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
7 * Copyright (C) 2006 Broadcom Corporation.
8 * Copyright (C) 2007 Michael Buesch <m@bues.ch>
10 * Distribute under GPL.
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/types.h>
19 #include <linux/netdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/mii.h>
22 #include <linux/if_ether.h>
23 #include <linux/if_vlan.h>
24 #include <linux/etherdevice.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/ssb/ssb.h>
31 #include <linux/slab.h>
33 #include <asm/uaccess.h>
40 #define DRV_MODULE_NAME "b44"
41 #define DRV_MODULE_VERSION "2.0"
42 #define DRV_DESCRIPTION "Broadcom 44xx/47xx 10/100 PCI ethernet driver"
44 #define B44_DEF_MSG_ENABLE \
54 /* length of time before we decide the hardware is borked,
55 * and dev->tx_timeout() should be called to fix the problem
57 #define B44_TX_TIMEOUT (5 * HZ)
59 /* hardware minimum and maximum for a single frame's data payload */
60 #define B44_MIN_MTU 60
61 #define B44_MAX_MTU 1500
63 #define B44_RX_RING_SIZE 512
64 #define B44_DEF_RX_RING_PENDING 200
65 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
67 #define B44_TX_RING_SIZE 512
68 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
69 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
72 #define TX_RING_GAP(BP) \
73 (B44_TX_RING_SIZE - (BP)->tx_pending)
74 #define TX_BUFFS_AVAIL(BP) \
75 (((BP)->tx_cons <= (BP)->tx_prod) ? \
76 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
77 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
78 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
80 #define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
81 #define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
83 /* minimum number of free TX descriptors required to wake up TX process */
84 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
86 /* b44 internal pattern match filter info */
87 #define B44_PATTERN_BASE 0x400
88 #define B44_PATTERN_SIZE 0x80
89 #define B44_PMASK_BASE 0x600
90 #define B44_PMASK_SIZE 0x10
91 #define B44_MAX_PATTERNS 16
92 #define B44_ETHIPV6UDP_HLEN 62
93 #define B44_ETHIPV4UDP_HLEN 42
95 MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
96 MODULE_DESCRIPTION(DRV_DESCRIPTION);
97 MODULE_LICENSE("GPL");
98 MODULE_VERSION(DRV_MODULE_VERSION);
100 static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
101 module_param(b44_debug, int, 0);
102 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
105 #ifdef CONFIG_B44_PCI
106 static DEFINE_PCI_DEVICE_TABLE(b44_pci_tbl) = {
107 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
109 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
110 { 0 } /* terminate list with empty entry */
112 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
114 static struct pci_driver b44_pci_driver = {
115 .name = DRV_MODULE_NAME,
116 .id_table = b44_pci_tbl,
118 #endif /* CONFIG_B44_PCI */
120 static const struct ssb_device_id b44_ssb_tbl[] = {
121 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
124 MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
126 static void b44_halt(struct b44 *);
127 static void b44_init_rings(struct b44 *);
129 #define B44_FULL_RESET 1
130 #define B44_FULL_RESET_SKIP_PHY 2
131 #define B44_PARTIAL_RESET 3
132 #define B44_CHIP_RESET_FULL 4
133 #define B44_CHIP_RESET_PARTIAL 5
135 static void b44_init_hw(struct b44 *, int);
137 static int dma_desc_sync_size;
140 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
141 #define _B44(x...) # x,
146 static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
148 unsigned long offset,
149 enum dma_data_direction dir)
151 dma_sync_single_for_device(sdev->dma_dev, dma_base + offset,
152 dma_desc_sync_size, dir);
155 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
157 unsigned long offset,
158 enum dma_data_direction dir)
160 dma_sync_single_for_cpu(sdev->dma_dev, dma_base + offset,
161 dma_desc_sync_size, dir);
164 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
166 return ssb_read32(bp->sdev, reg);
169 static inline void bw32(const struct b44 *bp,
170 unsigned long reg, unsigned long val)
172 ssb_write32(bp->sdev, reg, val);
175 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
176 u32 bit, unsigned long timeout, const int clear)
180 for (i = 0; i < timeout; i++) {
181 u32 val = br32(bp, reg);
183 if (clear && !(val & bit))
185 if (!clear && (val & bit))
191 netdev_err(bp->dev, "BUG! Timeout waiting for bit %08x of register %lx to %s\n",
192 bit, reg, clear ? "clear" : "set");
199 static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
203 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
204 (index << CAM_CTRL_INDEX_SHIFT)));
206 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
208 val = br32(bp, B44_CAM_DATA_LO);
210 data[2] = (val >> 24) & 0xFF;
211 data[3] = (val >> 16) & 0xFF;
212 data[4] = (val >> 8) & 0xFF;
213 data[5] = (val >> 0) & 0xFF;
215 val = br32(bp, B44_CAM_DATA_HI);
217 data[0] = (val >> 8) & 0xFF;
218 data[1] = (val >> 0) & 0xFF;
221 static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
225 val = ((u32) data[2]) << 24;
226 val |= ((u32) data[3]) << 16;
227 val |= ((u32) data[4]) << 8;
228 val |= ((u32) data[5]) << 0;
229 bw32(bp, B44_CAM_DATA_LO, val);
230 val = (CAM_DATA_HI_VALID |
231 (((u32) data[0]) << 8) |
232 (((u32) data[1]) << 0));
233 bw32(bp, B44_CAM_DATA_HI, val);
234 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
235 (index << CAM_CTRL_INDEX_SHIFT)));
236 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
239 static inline void __b44_disable_ints(struct b44 *bp)
241 bw32(bp, B44_IMASK, 0);
244 static void b44_disable_ints(struct b44 *bp)
246 __b44_disable_ints(bp);
248 /* Flush posted writes. */
252 static void b44_enable_ints(struct b44 *bp)
254 bw32(bp, B44_IMASK, bp->imask);
257 static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
261 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
262 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
263 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
264 (phy_addr << MDIO_DATA_PMD_SHIFT) |
265 (reg << MDIO_DATA_RA_SHIFT) |
266 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
267 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
268 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
273 static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
275 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
276 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
277 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
278 (phy_addr << MDIO_DATA_PMD_SHIFT) |
279 (reg << MDIO_DATA_RA_SHIFT) |
280 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
281 (val & MDIO_DATA_DATA)));
282 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
285 static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
287 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
290 return __b44_readphy(bp, bp->phy_addr, reg, val);
293 static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
295 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
298 return __b44_writephy(bp, bp->phy_addr, reg, val);
301 /* miilib interface */
302 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
305 struct b44 *bp = netdev_priv(dev);
306 int rc = __b44_readphy(bp, phy_id, location, &val);
312 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
315 struct b44 *bp = netdev_priv(dev);
316 __b44_writephy(bp, phy_id, location, val);
319 static int b44_phy_reset(struct b44 *bp)
324 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
326 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
330 err = b44_readphy(bp, MII_BMCR, &val);
332 if (val & BMCR_RESET) {
333 netdev_err(bp->dev, "PHY Reset would not complete\n");
341 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
345 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
346 bp->flags |= pause_flags;
348 val = br32(bp, B44_RXCONFIG);
349 if (pause_flags & B44_FLAG_RX_PAUSE)
350 val |= RXCONFIG_FLOW;
352 val &= ~RXCONFIG_FLOW;
353 bw32(bp, B44_RXCONFIG, val);
355 val = br32(bp, B44_MAC_FLOW);
356 if (pause_flags & B44_FLAG_TX_PAUSE)
357 val |= (MAC_FLOW_PAUSE_ENAB |
358 (0xc0 & MAC_FLOW_RX_HI_WATER));
360 val &= ~MAC_FLOW_PAUSE_ENAB;
361 bw32(bp, B44_MAC_FLOW, val);
364 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
368 /* The driver supports only rx pause by default because
369 the b44 mac tx pause mechanism generates excessive
371 Use ethtool to turn on b44 tx pause if necessary.
373 if ((local & ADVERTISE_PAUSE_CAP) &&
374 (local & ADVERTISE_PAUSE_ASYM)){
375 if ((remote & LPA_PAUSE_ASYM) &&
376 !(remote & LPA_PAUSE_CAP))
377 pause_enab |= B44_FLAG_RX_PAUSE;
380 __b44_set_flow_ctrl(bp, pause_enab);
383 #ifdef CONFIG_BCM47XX
384 #include <bcm47xx_nvram.h>
385 static void b44_wap54g10_workaround(struct b44 *bp)
392 * workaround for bad hardware design in Linksys WAP54G v1.0
393 * see https://dev.openwrt.org/ticket/146
394 * check and reset bit "isolate"
396 if (bcm47xx_nvram_getenv("boardnum", buf, sizeof(buf)) < 0)
398 if (simple_strtoul(buf, NULL, 0) == 2) {
399 err = __b44_readphy(bp, 0, MII_BMCR, &val);
402 if (!(val & BMCR_ISOLATE))
404 val &= ~BMCR_ISOLATE;
405 err = __b44_writephy(bp, 0, MII_BMCR, val);
411 pr_warning("PHY: cannot reset MII transceiver isolate bit\n");
414 static inline void b44_wap54g10_workaround(struct b44 *bp)
419 static int b44_setup_phy(struct b44 *bp)
424 b44_wap54g10_workaround(bp);
426 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
428 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
430 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
431 val & MII_ALEDCTRL_ALLMSK)) != 0)
433 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
435 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
436 val | MII_TLEDCTRL_ENABLE)) != 0)
439 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
440 u32 adv = ADVERTISE_CSMA;
442 if (bp->flags & B44_FLAG_ADV_10HALF)
443 adv |= ADVERTISE_10HALF;
444 if (bp->flags & B44_FLAG_ADV_10FULL)
445 adv |= ADVERTISE_10FULL;
446 if (bp->flags & B44_FLAG_ADV_100HALF)
447 adv |= ADVERTISE_100HALF;
448 if (bp->flags & B44_FLAG_ADV_100FULL)
449 adv |= ADVERTISE_100FULL;
451 if (bp->flags & B44_FLAG_PAUSE_AUTO)
452 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
454 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
456 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
457 BMCR_ANRESTART))) != 0)
462 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
464 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
465 if (bp->flags & B44_FLAG_100_BASE_T)
466 bmcr |= BMCR_SPEED100;
467 if (bp->flags & B44_FLAG_FULL_DUPLEX)
468 bmcr |= BMCR_FULLDPLX;
469 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
472 /* Since we will not be negotiating there is no safe way
473 * to determine if the link partner supports flow control
474 * or not. So just disable it completely in this case.
476 b44_set_flow_ctrl(bp, 0, 0);
483 static void b44_stats_update(struct b44 *bp)
488 val = &bp->hw_stats.tx_good_octets;
489 u64_stats_update_begin(&bp->hw_stats.syncp);
491 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
492 *val++ += br32(bp, reg);
498 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
499 *val++ += br32(bp, reg);
502 u64_stats_update_end(&bp->hw_stats.syncp);
505 static void b44_link_report(struct b44 *bp)
507 if (!netif_carrier_ok(bp->dev)) {
508 netdev_info(bp->dev, "Link is down\n");
510 netdev_info(bp->dev, "Link is up at %d Mbps, %s duplex\n",
511 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
512 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
514 netdev_info(bp->dev, "Flow control is %s for TX and %s for RX\n",
515 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
516 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
520 static void b44_check_phy(struct b44 *bp)
524 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
525 bp->flags |= B44_FLAG_100_BASE_T;
526 bp->flags |= B44_FLAG_FULL_DUPLEX;
527 if (!netif_carrier_ok(bp->dev)) {
528 u32 val = br32(bp, B44_TX_CTRL);
529 val |= TX_CTRL_DUPLEX;
530 bw32(bp, B44_TX_CTRL, val);
531 netif_carrier_on(bp->dev);
537 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
538 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
540 if (aux & MII_AUXCTRL_SPEED)
541 bp->flags |= B44_FLAG_100_BASE_T;
543 bp->flags &= ~B44_FLAG_100_BASE_T;
544 if (aux & MII_AUXCTRL_DUPLEX)
545 bp->flags |= B44_FLAG_FULL_DUPLEX;
547 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
549 if (!netif_carrier_ok(bp->dev) &&
550 (bmsr & BMSR_LSTATUS)) {
551 u32 val = br32(bp, B44_TX_CTRL);
552 u32 local_adv, remote_adv;
554 if (bp->flags & B44_FLAG_FULL_DUPLEX)
555 val |= TX_CTRL_DUPLEX;
557 val &= ~TX_CTRL_DUPLEX;
558 bw32(bp, B44_TX_CTRL, val);
560 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
561 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
562 !b44_readphy(bp, MII_LPA, &remote_adv))
563 b44_set_flow_ctrl(bp, local_adv, remote_adv);
566 netif_carrier_on(bp->dev);
568 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
570 netif_carrier_off(bp->dev);
574 if (bmsr & BMSR_RFAULT)
575 netdev_warn(bp->dev, "Remote fault detected in PHY\n");
577 netdev_warn(bp->dev, "Jabber detected in PHY\n");
581 static void b44_timer(unsigned long __opaque)
583 struct b44 *bp = (struct b44 *) __opaque;
585 spin_lock_irq(&bp->lock);
589 b44_stats_update(bp);
591 spin_unlock_irq(&bp->lock);
593 mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
596 static void b44_tx(struct b44 *bp)
600 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
601 cur /= sizeof(struct dma_desc);
603 /* XXX needs updating when NETIF_F_SG is supported */
604 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
605 struct ring_info *rp = &bp->tx_buffers[cons];
606 struct sk_buff *skb = rp->skb;
610 dma_unmap_single(bp->sdev->dma_dev,
615 dev_kfree_skb_irq(skb);
619 if (netif_queue_stopped(bp->dev) &&
620 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
621 netif_wake_queue(bp->dev);
623 bw32(bp, B44_GPTIMER, 0);
626 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
627 * before the DMA address you give it. So we allocate 30 more bytes
628 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
629 * point the chip at 30 bytes past where the rx_header will go.
631 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
634 struct ring_info *src_map, *map;
635 struct rx_header *rh;
643 src_map = &bp->rx_buffers[src_idx];
644 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
645 map = &bp->rx_buffers[dest_idx];
646 skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
650 mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
654 /* Hardware bug work-around, the chip is unable to do PCI DMA
655 to/from anything above 1GB :-( */
656 if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
657 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
659 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
660 dma_unmap_single(bp->sdev->dma_dev, mapping,
661 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
662 dev_kfree_skb_any(skb);
663 skb = alloc_skb(RX_PKT_BUF_SZ, GFP_ATOMIC | GFP_DMA);
666 mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
669 if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
670 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
671 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
672 dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
673 dev_kfree_skb_any(skb);
676 bp->force_copybreak = 1;
679 rh = (struct rx_header *) skb->data;
685 map->mapping = mapping;
690 ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
691 if (dest_idx == (B44_RX_RING_SIZE - 1))
692 ctrl |= DESC_CTRL_EOT;
694 dp = &bp->rx_ring[dest_idx];
695 dp->ctrl = cpu_to_le32(ctrl);
696 dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
698 if (bp->flags & B44_FLAG_RX_RING_HACK)
699 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
700 dest_idx * sizeof(*dp),
703 return RX_PKT_BUF_SZ;
706 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
708 struct dma_desc *src_desc, *dest_desc;
709 struct ring_info *src_map, *dest_map;
710 struct rx_header *rh;
714 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
715 dest_desc = &bp->rx_ring[dest_idx];
716 dest_map = &bp->rx_buffers[dest_idx];
717 src_desc = &bp->rx_ring[src_idx];
718 src_map = &bp->rx_buffers[src_idx];
720 dest_map->skb = src_map->skb;
721 rh = (struct rx_header *) src_map->skb->data;
724 dest_map->mapping = src_map->mapping;
726 if (bp->flags & B44_FLAG_RX_RING_HACK)
727 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
728 src_idx * sizeof(*src_desc),
731 ctrl = src_desc->ctrl;
732 if (dest_idx == (B44_RX_RING_SIZE - 1))
733 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
735 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
737 dest_desc->ctrl = ctrl;
738 dest_desc->addr = src_desc->addr;
742 if (bp->flags & B44_FLAG_RX_RING_HACK)
743 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
744 dest_idx * sizeof(*dest_desc),
747 dma_sync_single_for_device(bp->sdev->dma_dev, dest_map->mapping,
752 static int b44_rx(struct b44 *bp, int budget)
758 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
759 prod /= sizeof(struct dma_desc);
762 while (cons != prod && budget > 0) {
763 struct ring_info *rp = &bp->rx_buffers[cons];
764 struct sk_buff *skb = rp->skb;
765 dma_addr_t map = rp->mapping;
766 struct rx_header *rh;
769 dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
772 rh = (struct rx_header *) skb->data;
773 len = le16_to_cpu(rh->len);
774 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
775 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
777 b44_recycle_rx(bp, cons, bp->rx_prod);
779 bp->dev->stats.rx_dropped++;
789 len = le16_to_cpu(rh->len);
790 } while (len == 0 && i++ < 5);
798 if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
800 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
803 dma_unmap_single(bp->sdev->dma_dev, map,
804 skb_size, DMA_FROM_DEVICE);
805 /* Leave out rx_header */
806 skb_put(skb, len + RX_PKT_OFFSET);
807 skb_pull(skb, RX_PKT_OFFSET);
809 struct sk_buff *copy_skb;
811 b44_recycle_rx(bp, cons, bp->rx_prod);
812 copy_skb = netdev_alloc_skb_ip_align(bp->dev, len);
813 if (copy_skb == NULL)
814 goto drop_it_no_recycle;
816 skb_put(copy_skb, len);
817 /* DMA sync done above, copy just the actual packet */
818 skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
819 copy_skb->data, len);
822 skb_checksum_none_assert(skb);
823 skb->protocol = eth_type_trans(skb, bp->dev);
824 netif_receive_skb(skb);
828 bp->rx_prod = (bp->rx_prod + 1) &
829 (B44_RX_RING_SIZE - 1);
830 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
834 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
839 static int b44_poll(struct napi_struct *napi, int budget)
841 struct b44 *bp = container_of(napi, struct b44, napi);
845 spin_lock_irqsave(&bp->lock, flags);
847 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
848 /* spin_lock(&bp->tx_lock); */
850 /* spin_unlock(&bp->tx_lock); */
852 if (bp->istat & ISTAT_RFO) { /* fast recovery, in ~20msec */
853 bp->istat &= ~ISTAT_RFO;
854 b44_disable_ints(bp);
855 ssb_device_enable(bp->sdev, 0); /* resets ISTAT_RFO */
857 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
858 netif_wake_queue(bp->dev);
861 spin_unlock_irqrestore(&bp->lock, flags);
864 if (bp->istat & ISTAT_RX)
865 work_done += b44_rx(bp, budget);
867 if (bp->istat & ISTAT_ERRORS) {
868 spin_lock_irqsave(&bp->lock, flags);
871 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
872 netif_wake_queue(bp->dev);
873 spin_unlock_irqrestore(&bp->lock, flags);
877 if (work_done < budget) {
885 static irqreturn_t b44_interrupt(int irq, void *dev_id)
887 struct net_device *dev = dev_id;
888 struct b44 *bp = netdev_priv(dev);
892 spin_lock(&bp->lock);
894 istat = br32(bp, B44_ISTAT);
895 imask = br32(bp, B44_IMASK);
897 /* The interrupt mask register controls which interrupt bits
898 * will actually raise an interrupt to the CPU when set by hw/firmware,
899 * but doesn't mask off the bits.
905 if (unlikely(!netif_running(dev))) {
906 netdev_info(dev, "late interrupt\n");
910 if (napi_schedule_prep(&bp->napi)) {
911 /* NOTE: These writes are posted by the readback of
912 * the ISTAT register below.
915 __b44_disable_ints(bp);
916 __napi_schedule(&bp->napi);
920 bw32(bp, B44_ISTAT, istat);
923 spin_unlock(&bp->lock);
924 return IRQ_RETVAL(handled);
927 static void b44_tx_timeout(struct net_device *dev)
929 struct b44 *bp = netdev_priv(dev);
931 netdev_err(dev, "transmit timed out, resetting\n");
933 spin_lock_irq(&bp->lock);
937 b44_init_hw(bp, B44_FULL_RESET);
939 spin_unlock_irq(&bp->lock);
943 netif_wake_queue(dev);
946 static netdev_tx_t b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
948 struct b44 *bp = netdev_priv(dev);
949 int rc = NETDEV_TX_OK;
951 u32 len, entry, ctrl;
955 spin_lock_irqsave(&bp->lock, flags);
957 /* This is a hard error, log it. */
958 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
959 netif_stop_queue(dev);
960 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
964 mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
965 if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
966 struct sk_buff *bounce_skb;
968 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
969 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
970 dma_unmap_single(bp->sdev->dma_dev, mapping, len,
973 bounce_skb = alloc_skb(len, GFP_ATOMIC | GFP_DMA);
977 mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
979 if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
980 if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
981 dma_unmap_single(bp->sdev->dma_dev, mapping,
983 dev_kfree_skb_any(bounce_skb);
987 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
988 dev_kfree_skb_any(skb);
993 bp->tx_buffers[entry].skb = skb;
994 bp->tx_buffers[entry].mapping = mapping;
996 ctrl = (len & DESC_CTRL_LEN);
997 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
998 if (entry == (B44_TX_RING_SIZE - 1))
999 ctrl |= DESC_CTRL_EOT;
1001 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1002 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1004 if (bp->flags & B44_FLAG_TX_RING_HACK)
1005 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
1006 entry * sizeof(bp->tx_ring[0]),
1009 entry = NEXT_TX(entry);
1011 bp->tx_prod = entry;
1015 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1016 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1017 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1018 if (bp->flags & B44_FLAG_REORDER_BUG)
1019 br32(bp, B44_DMATX_PTR);
1021 if (TX_BUFFS_AVAIL(bp) < 1)
1022 netif_stop_queue(dev);
1025 spin_unlock_irqrestore(&bp->lock, flags);
1030 rc = NETDEV_TX_BUSY;
1034 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1036 struct b44 *bp = netdev_priv(dev);
1038 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1041 if (!netif_running(dev)) {
1042 /* We'll just catch it later when the
1049 spin_lock_irq(&bp->lock);
1053 b44_init_hw(bp, B44_FULL_RESET);
1054 spin_unlock_irq(&bp->lock);
1056 b44_enable_ints(bp);
1061 /* Free up pending packets in all rx/tx rings.
1063 * The chip has been shut down and the driver detached from
1064 * the networking, so no interrupts or new tx packets will
1065 * end up in the driver. bp->lock is not held and we are not
1066 * in an interrupt context and thus may sleep.
1068 static void b44_free_rings(struct b44 *bp)
1070 struct ring_info *rp;
1073 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1074 rp = &bp->rx_buffers[i];
1076 if (rp->skb == NULL)
1078 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
1080 dev_kfree_skb_any(rp->skb);
1084 /* XXX needs changes once NETIF_F_SG is set... */
1085 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1086 rp = &bp->tx_buffers[i];
1088 if (rp->skb == NULL)
1090 dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
1092 dev_kfree_skb_any(rp->skb);
1097 /* Initialize tx/rx rings for packet processing.
1099 * The chip has been shut down and the driver detached from
1100 * the networking, so no interrupts or new tx packets will
1101 * end up in the driver.
1103 static void b44_init_rings(struct b44 *bp)
1109 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1110 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1112 if (bp->flags & B44_FLAG_RX_RING_HACK)
1113 dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
1114 DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
1116 if (bp->flags & B44_FLAG_TX_RING_HACK)
1117 dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
1118 DMA_TABLE_BYTES, DMA_TO_DEVICE);
1120 for (i = 0; i < bp->rx_pending; i++) {
1121 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1127 * Must not be invoked with interrupt sources disabled and
1128 * the hardware shutdown down.
1130 static void b44_free_consistent(struct b44 *bp)
1132 kfree(bp->rx_buffers);
1133 bp->rx_buffers = NULL;
1134 kfree(bp->tx_buffers);
1135 bp->tx_buffers = NULL;
1137 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1138 dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
1139 DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
1142 dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
1143 bp->rx_ring, bp->rx_ring_dma);
1145 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1148 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1149 dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
1150 DMA_TABLE_BYTES, DMA_TO_DEVICE);
1153 dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
1154 bp->tx_ring, bp->tx_ring_dma);
1156 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1161 * Must not be invoked with interrupt sources disabled and
1162 * the hardware shutdown down. Can sleep.
1164 static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1168 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1169 bp->rx_buffers = kzalloc(size, gfp);
1170 if (!bp->rx_buffers)
1173 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1174 bp->tx_buffers = kzalloc(size, gfp);
1175 if (!bp->tx_buffers)
1178 size = DMA_TABLE_BYTES;
1179 bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
1180 &bp->rx_ring_dma, gfp);
1182 /* Allocation may have failed due to pci_alloc_consistent
1183 insisting on use of GFP_DMA, which is more restrictive
1184 than necessary... */
1185 struct dma_desc *rx_ring;
1186 dma_addr_t rx_ring_dma;
1188 rx_ring = kzalloc(size, gfp);
1192 rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
1196 if (dma_mapping_error(bp->sdev->dma_dev, rx_ring_dma) ||
1197 rx_ring_dma + size > DMA_BIT_MASK(30)) {
1202 bp->rx_ring = rx_ring;
1203 bp->rx_ring_dma = rx_ring_dma;
1204 bp->flags |= B44_FLAG_RX_RING_HACK;
1207 bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
1208 &bp->tx_ring_dma, gfp);
1210 /* Allocation may have failed due to ssb_dma_alloc_consistent
1211 insisting on use of GFP_DMA, which is more restrictive
1212 than necessary... */
1213 struct dma_desc *tx_ring;
1214 dma_addr_t tx_ring_dma;
1216 tx_ring = kzalloc(size, gfp);
1220 tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
1224 if (dma_mapping_error(bp->sdev->dma_dev, tx_ring_dma) ||
1225 tx_ring_dma + size > DMA_BIT_MASK(30)) {
1230 bp->tx_ring = tx_ring;
1231 bp->tx_ring_dma = tx_ring_dma;
1232 bp->flags |= B44_FLAG_TX_RING_HACK;
1238 b44_free_consistent(bp);
1242 /* bp->lock is held. */
1243 static void b44_clear_stats(struct b44 *bp)
1247 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1248 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1250 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1254 /* bp->lock is held. */
1255 static void b44_chip_reset(struct b44 *bp, int reset_kind)
1257 struct ssb_device *sdev = bp->sdev;
1260 was_enabled = ssb_device_is_enabled(bp->sdev);
1262 ssb_device_enable(bp->sdev, 0);
1263 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1266 bw32(bp, B44_RCV_LAZY, 0);
1267 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1268 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1269 bw32(bp, B44_DMATX_CTRL, 0);
1270 bp->tx_prod = bp->tx_cons = 0;
1271 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1272 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1275 bw32(bp, B44_DMARX_CTRL, 0);
1276 bp->rx_prod = bp->rx_cons = 0;
1279 b44_clear_stats(bp);
1282 * Don't enable PHY if we are doing a partial reset
1283 * we are probably going to power down
1285 if (reset_kind == B44_CHIP_RESET_PARTIAL)
1288 switch (sdev->bus->bustype) {
1289 case SSB_BUSTYPE_SSB:
1290 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1291 (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev->bus),
1293 & MDIO_CTRL_MAXF_MASK)));
1295 case SSB_BUSTYPE_PCI:
1296 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1297 (0x0d & MDIO_CTRL_MAXF_MASK)));
1299 case SSB_BUSTYPE_PCMCIA:
1300 case SSB_BUSTYPE_SDIO:
1301 WARN_ON(1); /* A device with this bus does not exist. */
1305 br32(bp, B44_MDIO_CTRL);
1307 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1308 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1309 br32(bp, B44_ENET_CTRL);
1310 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1312 u32 val = br32(bp, B44_DEVCTRL);
1314 if (val & DEVCTRL_EPR) {
1315 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1316 br32(bp, B44_DEVCTRL);
1319 bp->flags |= B44_FLAG_INTERNAL_PHY;
1323 /* bp->lock is held. */
1324 static void b44_halt(struct b44 *bp)
1326 b44_disable_ints(bp);
1329 /* power down PHY */
1330 netdev_info(bp->dev, "powering down PHY\n");
1331 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1332 /* now reset the chip, but without enabling the MAC&PHY
1333 * part of it. This has to be done _after_ we shut down the PHY */
1334 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1337 /* bp->lock is held. */
1338 static void __b44_set_mac_addr(struct b44 *bp)
1340 bw32(bp, B44_CAM_CTRL, 0);
1341 if (!(bp->dev->flags & IFF_PROMISC)) {
1344 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1345 val = br32(bp, B44_CAM_CTRL);
1346 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1350 static int b44_set_mac_addr(struct net_device *dev, void *p)
1352 struct b44 *bp = netdev_priv(dev);
1353 struct sockaddr *addr = p;
1356 if (netif_running(dev))
1359 if (!is_valid_ether_addr(addr->sa_data))
1362 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1364 spin_lock_irq(&bp->lock);
1366 val = br32(bp, B44_RXCONFIG);
1367 if (!(val & RXCONFIG_CAM_ABSENT))
1368 __b44_set_mac_addr(bp);
1370 spin_unlock_irq(&bp->lock);
1375 /* Called at device open time to get the chip ready for
1376 * packet processing. Invoked with bp->lock held.
1378 static void __b44_set_rx_mode(struct net_device *);
1379 static void b44_init_hw(struct b44 *bp, int reset_kind)
1383 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1384 if (reset_kind == B44_FULL_RESET) {
1389 /* Enable CRC32, set proper LED modes and power on PHY */
1390 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1391 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1393 /* This sets the MAC address too. */
1394 __b44_set_rx_mode(bp->dev);
1396 /* MTU + eth header + possible VLAN tag + struct rx_header */
1397 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1398 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1400 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1401 if (reset_kind == B44_PARTIAL_RESET) {
1402 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1403 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1405 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1406 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1407 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1408 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1409 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1411 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1412 bp->rx_prod = bp->rx_pending;
1414 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1417 val = br32(bp, B44_ENET_CTRL);
1418 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1421 static int b44_open(struct net_device *dev)
1423 struct b44 *bp = netdev_priv(dev);
1426 err = b44_alloc_consistent(bp, GFP_KERNEL);
1430 napi_enable(&bp->napi);
1433 b44_init_hw(bp, B44_FULL_RESET);
1437 err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
1438 if (unlikely(err < 0)) {
1439 napi_disable(&bp->napi);
1440 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1442 b44_free_consistent(bp);
1446 init_timer(&bp->timer);
1447 bp->timer.expires = jiffies + HZ;
1448 bp->timer.data = (unsigned long) bp;
1449 bp->timer.function = b44_timer;
1450 add_timer(&bp->timer);
1452 b44_enable_ints(bp);
1453 netif_start_queue(dev);
1458 #ifdef CONFIG_NET_POLL_CONTROLLER
1460 * Polling receive - used by netconsole and other diagnostic tools
1461 * to allow network i/o with interrupts disabled.
1463 static void b44_poll_controller(struct net_device *dev)
1465 disable_irq(dev->irq);
1466 b44_interrupt(dev->irq, dev);
1467 enable_irq(dev->irq);
1471 static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1474 u32 *pattern = (u32 *) pp;
1476 for (i = 0; i < bytes; i += sizeof(u32)) {
1477 bw32(bp, B44_FILT_ADDR, table_offset + i);
1478 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1482 static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1485 int k, j, len = offset;
1486 int ethaddr_bytes = ETH_ALEN;
1488 memset(ppattern + offset, 0xff, magicsync);
1489 for (j = 0; j < magicsync; j++)
1490 set_bit(len++, (unsigned long *) pmask);
1492 for (j = 0; j < B44_MAX_PATTERNS; j++) {
1493 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1494 ethaddr_bytes = ETH_ALEN;
1496 ethaddr_bytes = B44_PATTERN_SIZE - len;
1497 if (ethaddr_bytes <=0)
1499 for (k = 0; k< ethaddr_bytes; k++) {
1500 ppattern[offset + magicsync +
1501 (j * ETH_ALEN) + k] = macaddr[k];
1502 set_bit(len++, (unsigned long *) pmask);
1508 /* Setup magic packet patterns in the b44 WOL
1509 * pattern matching filter.
1511 static void b44_setup_pseudo_magicp(struct b44 *bp)
1515 int plen0, plen1, plen2;
1517 u8 pwol_mask[B44_PMASK_SIZE];
1519 pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
1523 /* Ipv4 magic packet pattern - pattern 0.*/
1524 memset(pwol_mask, 0, B44_PMASK_SIZE);
1525 plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1526 B44_ETHIPV4UDP_HLEN);
1528 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1529 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1531 /* Raw ethernet II magic packet pattern - pattern 1 */
1532 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1533 memset(pwol_mask, 0, B44_PMASK_SIZE);
1534 plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1537 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1538 B44_PATTERN_BASE + B44_PATTERN_SIZE);
1539 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1540 B44_PMASK_BASE + B44_PMASK_SIZE);
1542 /* Ipv6 magic packet pattern - pattern 2 */
1543 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1544 memset(pwol_mask, 0, B44_PMASK_SIZE);
1545 plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1546 B44_ETHIPV6UDP_HLEN);
1548 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1549 B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1550 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1551 B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1553 kfree(pwol_pattern);
1555 /* set these pattern's lengths: one less than each real length */
1556 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1557 bw32(bp, B44_WKUP_LEN, val);
1559 /* enable wakeup pattern matching */
1560 val = br32(bp, B44_DEVCTRL);
1561 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1565 #ifdef CONFIG_B44_PCI
1566 static void b44_setup_wol_pci(struct b44 *bp)
1570 if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1571 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1572 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1573 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1577 static inline void b44_setup_wol_pci(struct b44 *bp) { }
1578 #endif /* CONFIG_B44_PCI */
1580 static void b44_setup_wol(struct b44 *bp)
1584 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1586 if (bp->flags & B44_FLAG_B0_ANDLATER) {
1588 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1590 val = bp->dev->dev_addr[2] << 24 |
1591 bp->dev->dev_addr[3] << 16 |
1592 bp->dev->dev_addr[4] << 8 |
1593 bp->dev->dev_addr[5];
1594 bw32(bp, B44_ADDR_LO, val);
1596 val = bp->dev->dev_addr[0] << 8 |
1597 bp->dev->dev_addr[1];
1598 bw32(bp, B44_ADDR_HI, val);
1600 val = br32(bp, B44_DEVCTRL);
1601 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1604 b44_setup_pseudo_magicp(bp);
1606 b44_setup_wol_pci(bp);
1609 static int b44_close(struct net_device *dev)
1611 struct b44 *bp = netdev_priv(dev);
1613 netif_stop_queue(dev);
1615 napi_disable(&bp->napi);
1617 del_timer_sync(&bp->timer);
1619 spin_lock_irq(&bp->lock);
1623 netif_carrier_off(dev);
1625 spin_unlock_irq(&bp->lock);
1627 free_irq(dev->irq, dev);
1629 if (bp->flags & B44_FLAG_WOL_ENABLE) {
1630 b44_init_hw(bp, B44_PARTIAL_RESET);
1634 b44_free_consistent(bp);
1639 static struct rtnl_link_stats64 *b44_get_stats64(struct net_device *dev,
1640 struct rtnl_link_stats64 *nstat)
1642 struct b44 *bp = netdev_priv(dev);
1643 struct b44_hw_stats *hwstat = &bp->hw_stats;
1647 start = u64_stats_fetch_begin_bh(&hwstat->syncp);
1649 /* Convert HW stats into rtnl_link_stats64 stats. */
1650 nstat->rx_packets = hwstat->rx_pkts;
1651 nstat->tx_packets = hwstat->tx_pkts;
1652 nstat->rx_bytes = hwstat->rx_octets;
1653 nstat->tx_bytes = hwstat->tx_octets;
1654 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1655 hwstat->tx_oversize_pkts +
1656 hwstat->tx_underruns +
1657 hwstat->tx_excessive_cols +
1658 hwstat->tx_late_cols);
1659 nstat->multicast = hwstat->tx_multicast_pkts;
1660 nstat->collisions = hwstat->tx_total_cols;
1662 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1663 hwstat->rx_undersize);
1664 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1665 nstat->rx_frame_errors = hwstat->rx_align_errs;
1666 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1667 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1668 hwstat->rx_oversize_pkts +
1669 hwstat->rx_missed_pkts +
1670 hwstat->rx_crc_align_errs +
1671 hwstat->rx_undersize +
1672 hwstat->rx_crc_errs +
1673 hwstat->rx_align_errs +
1674 hwstat->rx_symbol_errs);
1676 nstat->tx_aborted_errors = hwstat->tx_underruns;
1678 /* Carrier lost counter seems to be broken for some devices */
1679 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1681 } while (u64_stats_fetch_retry_bh(&hwstat->syncp, start));
1686 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1688 struct netdev_hw_addr *ha;
1691 num_ents = min_t(int, netdev_mc_count(dev), B44_MCAST_TABLE_SIZE);
1693 netdev_for_each_mc_addr(ha, dev) {
1696 __b44_cam_write(bp, ha->addr, i++ + 1);
1701 static void __b44_set_rx_mode(struct net_device *dev)
1703 struct b44 *bp = netdev_priv(dev);
1706 val = br32(bp, B44_RXCONFIG);
1707 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1708 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1709 val |= RXCONFIG_PROMISC;
1710 bw32(bp, B44_RXCONFIG, val);
1712 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1715 __b44_set_mac_addr(bp);
1717 if ((dev->flags & IFF_ALLMULTI) ||
1718 (netdev_mc_count(dev) > B44_MCAST_TABLE_SIZE))
1719 val |= RXCONFIG_ALLMULTI;
1721 i = __b44_load_mcast(bp, dev);
1724 __b44_cam_write(bp, zero, i);
1726 bw32(bp, B44_RXCONFIG, val);
1727 val = br32(bp, B44_CAM_CTRL);
1728 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1732 static void b44_set_rx_mode(struct net_device *dev)
1734 struct b44 *bp = netdev_priv(dev);
1736 spin_lock_irq(&bp->lock);
1737 __b44_set_rx_mode(dev);
1738 spin_unlock_irq(&bp->lock);
1741 static u32 b44_get_msglevel(struct net_device *dev)
1743 struct b44 *bp = netdev_priv(dev);
1744 return bp->msg_enable;
1747 static void b44_set_msglevel(struct net_device *dev, u32 value)
1749 struct b44 *bp = netdev_priv(dev);
1750 bp->msg_enable = value;
1753 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1755 struct b44 *bp = netdev_priv(dev);
1756 struct ssb_bus *bus = bp->sdev->bus;
1758 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1759 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1760 switch (bus->bustype) {
1761 case SSB_BUSTYPE_PCI:
1762 strlcpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1764 case SSB_BUSTYPE_SSB:
1765 strlcpy(info->bus_info, "SSB", sizeof(info->bus_info));
1767 case SSB_BUSTYPE_PCMCIA:
1768 case SSB_BUSTYPE_SDIO:
1769 WARN_ON(1); /* A device with this bus does not exist. */
1774 static int b44_nway_reset(struct net_device *dev)
1776 struct b44 *bp = netdev_priv(dev);
1780 spin_lock_irq(&bp->lock);
1781 b44_readphy(bp, MII_BMCR, &bmcr);
1782 b44_readphy(bp, MII_BMCR, &bmcr);
1784 if (bmcr & BMCR_ANENABLE) {
1785 b44_writephy(bp, MII_BMCR,
1786 bmcr | BMCR_ANRESTART);
1789 spin_unlock_irq(&bp->lock);
1794 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1796 struct b44 *bp = netdev_priv(dev);
1798 cmd->supported = (SUPPORTED_Autoneg);
1799 cmd->supported |= (SUPPORTED_100baseT_Half |
1800 SUPPORTED_100baseT_Full |
1801 SUPPORTED_10baseT_Half |
1802 SUPPORTED_10baseT_Full |
1805 cmd->advertising = 0;
1806 if (bp->flags & B44_FLAG_ADV_10HALF)
1807 cmd->advertising |= ADVERTISED_10baseT_Half;
1808 if (bp->flags & B44_FLAG_ADV_10FULL)
1809 cmd->advertising |= ADVERTISED_10baseT_Full;
1810 if (bp->flags & B44_FLAG_ADV_100HALF)
1811 cmd->advertising |= ADVERTISED_100baseT_Half;
1812 if (bp->flags & B44_FLAG_ADV_100FULL)
1813 cmd->advertising |= ADVERTISED_100baseT_Full;
1814 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1815 ethtool_cmd_speed_set(cmd, ((bp->flags & B44_FLAG_100_BASE_T) ?
1816 SPEED_100 : SPEED_10));
1817 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1818 DUPLEX_FULL : DUPLEX_HALF;
1820 cmd->phy_address = bp->phy_addr;
1821 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1822 XCVR_INTERNAL : XCVR_EXTERNAL;
1823 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1824 AUTONEG_DISABLE : AUTONEG_ENABLE;
1825 if (cmd->autoneg == AUTONEG_ENABLE)
1826 cmd->advertising |= ADVERTISED_Autoneg;
1827 if (!netif_running(dev)){
1828 ethtool_cmd_speed_set(cmd, 0);
1836 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1838 struct b44 *bp = netdev_priv(dev);
1839 u32 speed = ethtool_cmd_speed(cmd);
1841 /* We do not support gigabit. */
1842 if (cmd->autoneg == AUTONEG_ENABLE) {
1843 if (cmd->advertising &
1844 (ADVERTISED_1000baseT_Half |
1845 ADVERTISED_1000baseT_Full))
1847 } else if ((speed != SPEED_100 &&
1848 speed != SPEED_10) ||
1849 (cmd->duplex != DUPLEX_HALF &&
1850 cmd->duplex != DUPLEX_FULL)) {
1854 spin_lock_irq(&bp->lock);
1856 if (cmd->autoneg == AUTONEG_ENABLE) {
1857 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1858 B44_FLAG_100_BASE_T |
1859 B44_FLAG_FULL_DUPLEX |
1860 B44_FLAG_ADV_10HALF |
1861 B44_FLAG_ADV_10FULL |
1862 B44_FLAG_ADV_100HALF |
1863 B44_FLAG_ADV_100FULL);
1864 if (cmd->advertising == 0) {
1865 bp->flags |= (B44_FLAG_ADV_10HALF |
1866 B44_FLAG_ADV_10FULL |
1867 B44_FLAG_ADV_100HALF |
1868 B44_FLAG_ADV_100FULL);
1870 if (cmd->advertising & ADVERTISED_10baseT_Half)
1871 bp->flags |= B44_FLAG_ADV_10HALF;
1872 if (cmd->advertising & ADVERTISED_10baseT_Full)
1873 bp->flags |= B44_FLAG_ADV_10FULL;
1874 if (cmd->advertising & ADVERTISED_100baseT_Half)
1875 bp->flags |= B44_FLAG_ADV_100HALF;
1876 if (cmd->advertising & ADVERTISED_100baseT_Full)
1877 bp->flags |= B44_FLAG_ADV_100FULL;
1880 bp->flags |= B44_FLAG_FORCE_LINK;
1881 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1882 if (speed == SPEED_100)
1883 bp->flags |= B44_FLAG_100_BASE_T;
1884 if (cmd->duplex == DUPLEX_FULL)
1885 bp->flags |= B44_FLAG_FULL_DUPLEX;
1888 if (netif_running(dev))
1891 spin_unlock_irq(&bp->lock);
1896 static void b44_get_ringparam(struct net_device *dev,
1897 struct ethtool_ringparam *ering)
1899 struct b44 *bp = netdev_priv(dev);
1901 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1902 ering->rx_pending = bp->rx_pending;
1904 /* XXX ethtool lacks a tx_max_pending, oops... */
1907 static int b44_set_ringparam(struct net_device *dev,
1908 struct ethtool_ringparam *ering)
1910 struct b44 *bp = netdev_priv(dev);
1912 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1913 (ering->rx_mini_pending != 0) ||
1914 (ering->rx_jumbo_pending != 0) ||
1915 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1918 spin_lock_irq(&bp->lock);
1920 bp->rx_pending = ering->rx_pending;
1921 bp->tx_pending = ering->tx_pending;
1925 b44_init_hw(bp, B44_FULL_RESET);
1926 netif_wake_queue(bp->dev);
1927 spin_unlock_irq(&bp->lock);
1929 b44_enable_ints(bp);
1934 static void b44_get_pauseparam(struct net_device *dev,
1935 struct ethtool_pauseparam *epause)
1937 struct b44 *bp = netdev_priv(dev);
1940 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1942 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1944 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1947 static int b44_set_pauseparam(struct net_device *dev,
1948 struct ethtool_pauseparam *epause)
1950 struct b44 *bp = netdev_priv(dev);
1952 spin_lock_irq(&bp->lock);
1953 if (epause->autoneg)
1954 bp->flags |= B44_FLAG_PAUSE_AUTO;
1956 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1957 if (epause->rx_pause)
1958 bp->flags |= B44_FLAG_RX_PAUSE;
1960 bp->flags &= ~B44_FLAG_RX_PAUSE;
1961 if (epause->tx_pause)
1962 bp->flags |= B44_FLAG_TX_PAUSE;
1964 bp->flags &= ~B44_FLAG_TX_PAUSE;
1965 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1968 b44_init_hw(bp, B44_FULL_RESET);
1970 __b44_set_flow_ctrl(bp, bp->flags);
1972 spin_unlock_irq(&bp->lock);
1974 b44_enable_ints(bp);
1979 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1983 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1988 static int b44_get_sset_count(struct net_device *dev, int sset)
1992 return ARRAY_SIZE(b44_gstrings);
1998 static void b44_get_ethtool_stats(struct net_device *dev,
1999 struct ethtool_stats *stats, u64 *data)
2001 struct b44 *bp = netdev_priv(dev);
2002 struct b44_hw_stats *hwstat = &bp->hw_stats;
2003 u64 *data_src, *data_dst;
2007 spin_lock_irq(&bp->lock);
2008 b44_stats_update(bp);
2009 spin_unlock_irq(&bp->lock);
2012 data_src = &hwstat->tx_good_octets;
2014 start = u64_stats_fetch_begin_bh(&hwstat->syncp);
2016 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2017 *data_dst++ = *data_src++;
2019 } while (u64_stats_fetch_retry_bh(&hwstat->syncp, start));
2022 static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2024 struct b44 *bp = netdev_priv(dev);
2026 wol->supported = WAKE_MAGIC;
2027 if (bp->flags & B44_FLAG_WOL_ENABLE)
2028 wol->wolopts = WAKE_MAGIC;
2031 memset(&wol->sopass, 0, sizeof(wol->sopass));
2034 static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2036 struct b44 *bp = netdev_priv(dev);
2038 spin_lock_irq(&bp->lock);
2039 if (wol->wolopts & WAKE_MAGIC)
2040 bp->flags |= B44_FLAG_WOL_ENABLE;
2042 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2043 spin_unlock_irq(&bp->lock);
2048 static const struct ethtool_ops b44_ethtool_ops = {
2049 .get_drvinfo = b44_get_drvinfo,
2050 .get_settings = b44_get_settings,
2051 .set_settings = b44_set_settings,
2052 .nway_reset = b44_nway_reset,
2053 .get_link = ethtool_op_get_link,
2054 .get_wol = b44_get_wol,
2055 .set_wol = b44_set_wol,
2056 .get_ringparam = b44_get_ringparam,
2057 .set_ringparam = b44_set_ringparam,
2058 .get_pauseparam = b44_get_pauseparam,
2059 .set_pauseparam = b44_set_pauseparam,
2060 .get_msglevel = b44_get_msglevel,
2061 .set_msglevel = b44_set_msglevel,
2062 .get_strings = b44_get_strings,
2063 .get_sset_count = b44_get_sset_count,
2064 .get_ethtool_stats = b44_get_ethtool_stats,
2067 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2069 struct mii_ioctl_data *data = if_mii(ifr);
2070 struct b44 *bp = netdev_priv(dev);
2073 if (!netif_running(dev))
2076 spin_lock_irq(&bp->lock);
2077 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2078 spin_unlock_irq(&bp->lock);
2083 static int b44_get_invariants(struct b44 *bp)
2085 struct ssb_device *sdev = bp->sdev;
2089 bp->dma_offset = ssb_dma_translation(sdev);
2091 if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2093 addr = sdev->bus->sprom.et1mac;
2094 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
2096 addr = sdev->bus->sprom.et0mac;
2097 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
2099 /* Some ROMs have buggy PHY addresses with the high
2100 * bits set (sign extension?). Truncate them to a
2101 * valid PHY address. */
2102 bp->phy_addr &= 0x1F;
2104 memcpy(bp->dev->dev_addr, addr, 6);
2106 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2107 pr_err("Invalid MAC address found in EEPROM\n");
2111 bp->imask = IMASK_DEF;
2113 /* XXX - really required?
2114 bp->flags |= B44_FLAG_BUGGY_TXPTR;
2117 if (bp->sdev->id.revision >= 7)
2118 bp->flags |= B44_FLAG_B0_ANDLATER;
2123 static const struct net_device_ops b44_netdev_ops = {
2124 .ndo_open = b44_open,
2125 .ndo_stop = b44_close,
2126 .ndo_start_xmit = b44_start_xmit,
2127 .ndo_get_stats64 = b44_get_stats64,
2128 .ndo_set_rx_mode = b44_set_rx_mode,
2129 .ndo_set_mac_address = b44_set_mac_addr,
2130 .ndo_validate_addr = eth_validate_addr,
2131 .ndo_do_ioctl = b44_ioctl,
2132 .ndo_tx_timeout = b44_tx_timeout,
2133 .ndo_change_mtu = b44_change_mtu,
2134 #ifdef CONFIG_NET_POLL_CONTROLLER
2135 .ndo_poll_controller = b44_poll_controller,
2139 static int b44_init_one(struct ssb_device *sdev,
2140 const struct ssb_device_id *ent)
2142 struct net_device *dev;
2148 pr_info_once("%s version %s\n", DRV_DESCRIPTION, DRV_MODULE_VERSION);
2150 dev = alloc_etherdev(sizeof(*bp));
2156 SET_NETDEV_DEV(dev, sdev->dev);
2158 /* No interesting netdevice features in this card... */
2161 bp = netdev_priv(dev);
2164 bp->force_copybreak = 0;
2166 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
2168 spin_lock_init(&bp->lock);
2170 bp->rx_pending = B44_DEF_RX_RING_PENDING;
2171 bp->tx_pending = B44_DEF_TX_RING_PENDING;
2173 dev->netdev_ops = &b44_netdev_ops;
2174 netif_napi_add(dev, &bp->napi, b44_poll, 64);
2175 dev->watchdog_timeo = B44_TX_TIMEOUT;
2176 dev->irq = sdev->irq;
2177 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2179 err = ssb_bus_powerup(sdev->bus, 0);
2182 "Failed to powerup the bus\n");
2183 goto err_out_free_dev;
2186 if (dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(30)) ||
2187 dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(30))) {
2189 "Required 30BIT DMA mask unsupported by the system\n");
2190 goto err_out_powerdown;
2193 err = b44_get_invariants(bp);
2196 "Problem fetching invariants of chip, aborting\n");
2197 goto err_out_powerdown;
2200 bp->mii_if.dev = dev;
2201 bp->mii_if.mdio_read = b44_mii_read;
2202 bp->mii_if.mdio_write = b44_mii_write;
2203 bp->mii_if.phy_id = bp->phy_addr;
2204 bp->mii_if.phy_id_mask = 0x1f;
2205 bp->mii_if.reg_num_mask = 0x1f;
2207 /* By default, advertise all speed/duplex settings. */
2208 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2209 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2211 /* By default, auto-negotiate PAUSE. */
2212 bp->flags |= B44_FLAG_PAUSE_AUTO;
2214 err = register_netdev(dev);
2216 dev_err(sdev->dev, "Cannot register net device, aborting\n");
2217 goto err_out_powerdown;
2220 netif_carrier_off(dev);
2222 ssb_set_drvdata(sdev, dev);
2224 /* Chip reset provides power to the b44 MAC & PCI cores, which
2225 * is necessary for MAC register access.
2227 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
2229 /* do a phy reset to test if there is an active phy */
2230 if (b44_phy_reset(bp) < 0)
2231 bp->phy_addr = B44_PHY_ADDR_NO_PHY;
2233 netdev_info(dev, "%s %pM\n", DRV_DESCRIPTION, dev->dev_addr);
2238 ssb_bus_may_powerdown(sdev->bus);
2247 static void b44_remove_one(struct ssb_device *sdev)
2249 struct net_device *dev = ssb_get_drvdata(sdev);
2251 unregister_netdev(dev);
2252 ssb_device_disable(sdev, 0);
2253 ssb_bus_may_powerdown(sdev->bus);
2255 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2256 ssb_set_drvdata(sdev, NULL);
2259 static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
2261 struct net_device *dev = ssb_get_drvdata(sdev);
2262 struct b44 *bp = netdev_priv(dev);
2264 if (!netif_running(dev))
2267 del_timer_sync(&bp->timer);
2269 spin_lock_irq(&bp->lock);
2272 netif_carrier_off(bp->dev);
2273 netif_device_detach(bp->dev);
2276 spin_unlock_irq(&bp->lock);
2278 free_irq(dev->irq, dev);
2279 if (bp->flags & B44_FLAG_WOL_ENABLE) {
2280 b44_init_hw(bp, B44_PARTIAL_RESET);
2284 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2288 static int b44_resume(struct ssb_device *sdev)
2290 struct net_device *dev = ssb_get_drvdata(sdev);
2291 struct b44 *bp = netdev_priv(dev);
2294 rc = ssb_bus_powerup(sdev->bus, 0);
2297 "Failed to powerup the bus\n");
2301 if (!netif_running(dev))
2304 spin_lock_irq(&bp->lock);
2306 b44_init_hw(bp, B44_FULL_RESET);
2307 spin_unlock_irq(&bp->lock);
2310 * As a shared interrupt, the handler can be called immediately. To be
2311 * able to check the interrupt status the hardware must already be
2312 * powered back on (b44_init_hw).
2314 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2316 netdev_err(dev, "request_irq failed\n");
2317 spin_lock_irq(&bp->lock);
2320 spin_unlock_irq(&bp->lock);
2324 netif_device_attach(bp->dev);
2326 b44_enable_ints(bp);
2327 netif_wake_queue(dev);
2329 mod_timer(&bp->timer, jiffies + 1);
2334 static struct ssb_driver b44_ssb_driver = {
2335 .name = DRV_MODULE_NAME,
2336 .id_table = b44_ssb_tbl,
2337 .probe = b44_init_one,
2338 .remove = b44_remove_one,
2339 .suspend = b44_suspend,
2340 .resume = b44_resume,
2343 static inline int __init b44_pci_init(void)
2346 #ifdef CONFIG_B44_PCI
2347 err = ssb_pcihost_register(&b44_pci_driver);
2352 static inline void b44_pci_exit(void)
2354 #ifdef CONFIG_B44_PCI
2355 ssb_pcihost_unregister(&b44_pci_driver);
2359 static int __init b44_init(void)
2361 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2364 /* Setup paramaters for syncing RX/TX DMA descriptors */
2365 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2367 err = b44_pci_init();
2370 err = ssb_driver_register(&b44_ssb_driver);
2376 static void __exit b44_cleanup(void)
2378 ssb_driver_unregister(&b44_ssb_driver);
2382 module_init(b44_init);
2383 module_exit(b44_cleanup);