drivers/net/ethernet/broadcom/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/clk.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/crc32.h>
  29 #include <linux/err.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/if_vlan.h>
  33
  34 #include <bcm63xx_dev_enet.h>
  35 #include "bcm63xx_enet.h"
  36
  37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  38 static char bcm_enet_driver_version[] = "1.0";
  39
  40 static int copybreak __read_mostly = 128;
  41 module_param(copybreak, int, 0);
  42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  43
  44 /* io memory shared between all devices */
  45 static void __iomem *bcm_enet_shared_base;
  46
  47 /*
  48  * io helpers to access mac registers
  49  */
  50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  51 {
  52         return bcm_readl(priv->base + off);
  53 }
  54
  55 static inline void enet_writel(struct bcm_enet_priv *priv,
  56                                u32 val, u32 off)
  57 {
  58         bcm_writel(val, priv->base + off);
  59 }
  60
  61 /*
  62  * io helpers to access shared registers
  63  */
  64 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
  65 {
  66         return bcm_readl(bcm_enet_shared_base + off);
  67 }
  68
  69 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
  70                                        u32 val, u32 off)
  71 {
  72         bcm_writel(val, bcm_enet_shared_base + off);
  73 }
  74
  75 /*
  76  * write given data into mii register and wait for transfer to end
  77  * with timeout (average measured transfer time is 25us)
  78  */
  79 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
  80 {
  81         int limit;
  82
  83         /* make sure mii interrupt status is cleared */
  84         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
  85
  86         enet_writel(priv, data, ENET_MIIDATA_REG);
  87         wmb();
  88
  89         /* busy wait on mii interrupt bit, with timeout */
  90         limit = 1000;
  91         do {
  92                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
  93                         break;
  94                 udelay(1);
  95         } while (limit-- > 0);
  96
  97         return (limit < 0) ? 1 : 0;
  98 }
  99
 100 /*
 101  * MII internal read callback
 102  */
 103 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 104                               int regnum)
 105 {
 106         u32 tmp, val;
 107
 108         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 109         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 110         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 111         tmp |= ENET_MIIDATA_OP_READ_MASK;
 112
 113         if (do_mdio_op(priv, tmp))
 114                 return -1;
 115
 116         val = enet_readl(priv, ENET_MIIDATA_REG);
 117         val &= 0xffff;
 118         return val;
 119 }
 120
 121 /*
 122  * MII internal write callback
 123  */
 124 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 125                                int regnum, u16 value)
 126 {
 127         u32 tmp;
 128
 129         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 130         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 131         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 132         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 133         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 134
 135         (void)do_mdio_op(priv, tmp);
 136         return 0;
 137 }
 138
 139 /*
 140  * MII read callback from phylib
 141  */
 142 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 143                                      int regnum)
 144 {
 145         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 146 }
 147
 148 /*
 149  * MII write callback from phylib
 150  */
 151 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 152                                       int regnum, u16 value)
 153 {
 154         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 155 }
 156
 157 /*
 158  * MII read callback from mii core
 159  */
 160 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 161                                   int regnum)
 162 {
 163         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 164 }
 165
 166 /*
 167  * MII write callback from mii core
 168  */
 169 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 170                                     int regnum, int value)
 171 {
 172         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 173 }
 174
 175 /*
 176  * refill rx queue
 177  */
 178 static int bcm_enet_refill_rx(struct net_device *dev)
 179 {
 180         struct bcm_enet_priv *priv;
 181
 182         priv = netdev_priv(dev);
 183
 184         while (priv->rx_desc_count < priv->rx_ring_size) {
 185                 struct bcm_enet_desc *desc;
 186                 struct sk_buff *skb;
 187                 dma_addr_t p;
 188                 int desc_idx;
 189                 u32 len_stat;
 190
 191                 desc_idx = priv->rx_dirty_desc;
 192                 desc = &priv->rx_desc_cpu[desc_idx];
 193
 194                 if (!priv->rx_skb[desc_idx]) {
 195                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 196                         if (!skb)
 197                                 break;
 198                         priv->rx_skb[desc_idx] = skb;
 199
 200                         p = dma_map_single(&priv->pdev->dev, skb->data,
 201                                            priv->rx_skb_size,
 202                                            DMA_FROM_DEVICE);
 203                         desc->address = p;
 204                 }
 205
 206                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 207                 len_stat |= DMADESC_OWNER_MASK;
 208                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 209                         len_stat |= DMADESC_WRAP_MASK;
 210                         priv->rx_dirty_desc = 0;
 211                 } else {
 212                         priv->rx_dirty_desc++;
 213                 }
 214                 wmb();
 215                 desc->len_stat = len_stat;
 216
 217                 priv->rx_desc_count++;
 218
 219                 /* tell dma engine we allocated one buffer */
 220                 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 221         }
 222
 223         /* If rx ring is still empty, set a timer to try allocating
 224          * again at a later time. */
 225         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 226                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 227                 priv->rx_timeout.expires = jiffies + HZ;
 228                 add_timer(&priv->rx_timeout);
 229         }
 230
 231         return 0;
 232 }
 233
 234 /*
 235  * timer callback to defer refill rx queue in case we're OOM
 236  */
 237 static void bcm_enet_refill_rx_timer(unsigned long data)
 238 {
 239         struct net_device *dev;
 240         struct bcm_enet_priv *priv;
 241
 242         dev = (struct net_device *)data;
 243         priv = netdev_priv(dev);
 244
 245         spin_lock(&priv->rx_lock);
 246         bcm_enet_refill_rx((struct net_device *)data);
 247         spin_unlock(&priv->rx_lock);
 248 }
 249
 250 /*
 251  * extract packet from rx queue
 252  */
 253 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 254 {
 255         struct bcm_enet_priv *priv;
 256         struct device *kdev;
 257         int processed;
 258
 259         priv = netdev_priv(dev);
 260         kdev = &priv->pdev->dev;
 261         processed = 0;
 262
 263         /* don't scan ring further than number of refilled
 264          * descriptor */
 265         if (budget > priv->rx_desc_count)
 266                 budget = priv->rx_desc_count;
 267
 268         do {
 269                 struct bcm_enet_desc *desc;
 270                 struct sk_buff *skb;
 271                 int desc_idx;
 272                 u32 len_stat;
 273                 unsigned int len;
 274
 275                 desc_idx = priv->rx_curr_desc;
 276                 desc = &priv->rx_desc_cpu[desc_idx];
 277
 278                 /* make sure we actually read the descriptor status at
 279                  * each loop */
 280                 rmb();
 281
 282                 len_stat = desc->len_stat;
 283
 284                 /* break if dma ownership belongs to hw */
 285                 if (len_stat & DMADESC_OWNER_MASK)
 286                         break;
 287
 288                 processed++;
 289                 priv->rx_curr_desc++;
 290                 if (priv->rx_curr_desc == priv->rx_ring_size)
 291                         priv->rx_curr_desc = 0;
 292                 priv->rx_desc_count--;
 293
 294                 /* if the packet does not have start of packet _and_
 295                  * end of packet flag set, then just recycle it */
 296                 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
 297                         dev->stats.rx_dropped++;
 298                         continue;
 299                 }
 300
 301                 /* recycle packet if it's marked as bad */
 302                 if (unlikely(len_stat & DMADESC_ERR_MASK)) {
 303                         dev->stats.rx_errors++;
 304
 305                         if (len_stat & DMADESC_OVSIZE_MASK)
 306                                 dev->stats.rx_length_errors++;
 307                         if (len_stat & DMADESC_CRC_MASK)
 308                                 dev->stats.rx_crc_errors++;
 309                         if (len_stat & DMADESC_UNDER_MASK)
 310                                 dev->stats.rx_frame_errors++;
 311                         if (len_stat & DMADESC_OV_MASK)
 312                                 dev->stats.rx_fifo_errors++;
 313                         continue;
 314                 }
 315
 316                 /* valid packet */
 317                 skb = priv->rx_skb[desc_idx];
 318                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 319                 /* don't include FCS */
 320                 len -= 4;
 321
 322                 if (len < copybreak) {
 323                         struct sk_buff *nskb;
 324
 325                         nskb = netdev_alloc_skb_ip_align(dev, len);
 326                         if (!nskb) {
 327                                 /* forget packet, just rearm desc */
 328                                 dev->stats.rx_dropped++;
 329                                 continue;
 330                         }
 331
 332                         dma_sync_single_for_cpu(kdev, desc->address,
 333                                                 len, DMA_FROM_DEVICE);
 334                         memcpy(nskb->data, skb->data, len);
 335                         dma_sync_single_for_device(kdev, desc->address,
 336                                                    len, DMA_FROM_DEVICE);
 337                         skb = nskb;
 338                 } else {
 339                         dma_unmap_single(&priv->pdev->dev, desc->address,
 340                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 341                         priv->rx_skb[desc_idx] = NULL;
 342                 }
 343
 344                 skb_put(skb, len);
 345                 skb->protocol = eth_type_trans(skb, dev);
 346                 dev->stats.rx_packets++;
 347                 dev->stats.rx_bytes += len;
 348                 netif_receive_skb(skb);
 349
 350         } while (--budget > 0);
 351
 352         if (processed || !priv->rx_desc_count) {
 353                 bcm_enet_refill_rx(dev);
 354
 355                 /* kick rx dma */
 356                 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
 357                                 ENETDMA_CHANCFG_REG(priv->rx_chan));
 358         }
 359
 360         return processed;
 361 }
 362
 363
 364 /*
 365  * try to or force reclaim of transmitted buffers
 366  */
 367 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 368 {
 369         struct bcm_enet_priv *priv;
 370         int released;
 371
 372         priv = netdev_priv(dev);
 373         released = 0;
 374
 375         while (priv->tx_desc_count < priv->tx_ring_size) {
 376                 struct bcm_enet_desc *desc;
 377                 struct sk_buff *skb;
 378
 379                 /* We run in a bh and fight against start_xmit, which
 380                  * is called with bh disabled  */
 381                 spin_lock(&priv->tx_lock);
 382
 383                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 384
 385                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 386                         spin_unlock(&priv->tx_lock);
 387                         break;
 388                 }
 389
 390                 /* ensure other field of the descriptor were not read
 391                  * before we checked ownership */
 392                 rmb();
 393
 394                 skb = priv->tx_skb[priv->tx_dirty_desc];
 395                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 396                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 397                                  DMA_TO_DEVICE);
 398
 399                 priv->tx_dirty_desc++;
 400                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 401                         priv->tx_dirty_desc = 0;
 402                 priv->tx_desc_count++;
 403
 404                 spin_unlock(&priv->tx_lock);
 405
 406                 if (desc->len_stat & DMADESC_UNDER_MASK)
 407                         dev->stats.tx_errors++;
 408
 409                 dev_kfree_skb(skb);
 410                 released++;
 411         }
 412
 413         if (netif_queue_stopped(dev) && released)
 414                 netif_wake_queue(dev);
 415
 416         return released;
 417 }
 418
 419 /*
 420  * poll func, called by network core
 421  */
 422 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 423 {
 424         struct bcm_enet_priv *priv;
 425         struct net_device *dev;
 426         int tx_work_done, rx_work_done;
 427
 428         priv = container_of(napi, struct bcm_enet_priv, napi);
 429         dev = priv->net_dev;
 430
 431         /* ack interrupts */
 432         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 433                         ENETDMA_IR_REG(priv->rx_chan));
 434         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 435                         ENETDMA_IR_REG(priv->tx_chan));
 436
 437         /* reclaim sent skb */
 438         tx_work_done = bcm_enet_tx_reclaim(dev, 0);
 439
 440         spin_lock(&priv->rx_lock);
 441         rx_work_done = bcm_enet_receive_queue(dev, budget);
 442         spin_unlock(&priv->rx_lock);
 443
 444         if (rx_work_done >= budget || tx_work_done > 0) {
 445                 /* rx/tx queue is not yet empty/clean */
 446                 return rx_work_done;
 447         }
 448
 449         /* no more packet in rx/tx queue, remove device from poll
 450          * queue */
 451         napi_complete(napi);
 452
 453         /* restore rx/tx interrupt */
 454         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 455                         ENETDMA_IRMASK_REG(priv->rx_chan));
 456         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 457                         ENETDMA_IRMASK_REG(priv->tx_chan));
 458
 459         return rx_work_done;
 460 }
 461
 462 /*
 463  * mac interrupt handler
 464  */
 465 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 466 {
 467         struct net_device *dev;
 468         struct bcm_enet_priv *priv;
 469         u32 stat;
 470
 471         dev = dev_id;
 472         priv = netdev_priv(dev);
 473
 474         stat = enet_readl(priv, ENET_IR_REG);
 475         if (!(stat & ENET_IR_MIB))
 476                 return IRQ_NONE;
 477
 478         /* clear & mask interrupt */
 479         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 480         enet_writel(priv, 0, ENET_IRMASK_REG);
 481
 482         /* read mib registers in workqueue */
 483         schedule_work(&priv->mib_update_task);
 484
 485         return IRQ_HANDLED;
 486 }
 487
 488 /*
 489  * rx/tx dma interrupt handler
 490  */
 491 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 492 {
 493         struct net_device *dev;
 494         struct bcm_enet_priv *priv;
 495
 496         dev = dev_id;
 497         priv = netdev_priv(dev);
 498
 499         /* mask rx/tx interrupts */
 500         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
 501         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
 502
 503         napi_schedule(&priv->napi);
 504
 505         return IRQ_HANDLED;
 506 }
 507
 508 /*
 509  * tx request callback
 510  */
 511 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 512 {
 513         struct bcm_enet_priv *priv;
 514         struct bcm_enet_desc *desc;
 515         u32 len_stat;
 516         int ret;
 517
 518         priv = netdev_priv(dev);
 519
 520         /* lock against tx reclaim */
 521         spin_lock(&priv->tx_lock);
 522
 523         /* make sure  the tx hw queue  is not full,  should not happen
 524          * since we stop queue before it's the case */
 525         if (unlikely(!priv->tx_desc_count)) {
 526                 netif_stop_queue(dev);
 527                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 528                         "available?\n");
 529                 ret = NETDEV_TX_BUSY;
 530                 goto out_unlock;
 531         }
 532
 533         /* point to the next available desc */
 534         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 535         priv->tx_skb[priv->tx_curr_desc] = skb;
 536
 537         /* fill descriptor */
 538         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 539                                        DMA_TO_DEVICE);
 540
 541         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 542         len_stat |= DMADESC_ESOP_MASK |
 543                 DMADESC_APPEND_CRC |
 544                 DMADESC_OWNER_MASK;
 545
 546         priv->tx_curr_desc++;
 547         if (priv->tx_curr_desc == priv->tx_ring_size) {
 548                 priv->tx_curr_desc = 0;
 549                 len_stat |= DMADESC_WRAP_MASK;
 550         }
 551         priv->tx_desc_count--;
 552
 553         /* dma might be already polling, make sure we update desc
 554          * fields in correct order */
 555         wmb();
 556         desc->len_stat = len_stat;
 557         wmb();
 558
 559         /* kick tx dma */
 560         enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
 561                         ENETDMA_CHANCFG_REG(priv->tx_chan));
 562
 563         /* stop queue if no more desc available */
 564         if (!priv->tx_desc_count)
 565                 netif_stop_queue(dev);
 566
 567         dev->stats.tx_bytes += skb->len;
 568         dev->stats.tx_packets++;
 569         ret = NETDEV_TX_OK;
 570
 571 out_unlock:
 572         spin_unlock(&priv->tx_lock);
 573         return ret;
 574 }
 575
 576 /*
 577  * Change the interface's mac address.
 578  */
 579 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 580 {
 581         struct bcm_enet_priv *priv;
 582         struct sockaddr *addr = p;
 583         u32 val;
 584
 585         priv = netdev_priv(dev);
 586         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 587
 588         /* use perfect match register 0 to store my mac address */
 589         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 590                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 591         enet_writel(priv, val, ENET_PML_REG(0));
 592
 593         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 594         val |= ENET_PMH_DATAVALID_MASK;
 595         enet_writel(priv, val, ENET_PMH_REG(0));
 596
 597         return 0;
 598 }
 599
 600 /*
 601  * Change rx mode (promiscuous/allmulti) and update multicast list
 602  */
 603 static void bcm_enet_set_multicast_list(struct net_device *dev)
 604 {
 605         struct bcm_enet_priv *priv;
 606         struct netdev_hw_addr *ha;
 607         u32 val;
 608         int i;
 609
 610         priv = netdev_priv(dev);
 611
 612         val = enet_readl(priv, ENET_RXCFG_REG);
 613
 614         if (dev->flags & IFF_PROMISC)
 615                 val |= ENET_RXCFG_PROMISC_MASK;
 616         else
 617                 val &= ~ENET_RXCFG_PROMISC_MASK;
 618
 619         /* only 3 perfect match registers left, first one is used for
 620          * own mac address */
 621         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 622                 val |= ENET_RXCFG_ALLMCAST_MASK;
 623         else
 624                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 625
 626         /* no need to set perfect match registers if we catch all
 627          * multicast */
 628         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 629                 enet_writel(priv, val, ENET_RXCFG_REG);
 630                 return;
 631         }
 632
 633         i = 0;
 634         netdev_for_each_mc_addr(ha, dev) {
 635                 u8 *dmi_addr;
 636                 u32 tmp;
 637
 638                 if (i == 3)
 639                         break;
 640                 /* update perfect match registers */
 641                 dmi_addr = ha->addr;
 642                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 643                         (dmi_addr[4] << 8) | dmi_addr[5];
 644                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 645
 646                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 647                 tmp |= ENET_PMH_DATAVALID_MASK;
 648                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 649         }
 650
 651         for (; i < 3; i++) {
 652                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 653                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 654         }
 655
 656         enet_writel(priv, val, ENET_RXCFG_REG);
 657 }
 658
 659 /*
 660  * set mac duplex parameters
 661  */
 662 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 663 {
 664         u32 val;
 665
 666         val = enet_readl(priv, ENET_TXCTL_REG);
 667         if (fullduplex)
 668                 val |= ENET_TXCTL_FD_MASK;
 669         else
 670                 val &= ~ENET_TXCTL_FD_MASK;
 671         enet_writel(priv, val, ENET_TXCTL_REG);
 672 }
 673
 674 /*
 675  * set mac flow control parameters
 676  */
 677 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 678 {
 679         u32 val;
 680
 681         /* rx flow control (pause frame handling) */
 682         val = enet_readl(priv, ENET_RXCFG_REG);
 683         if (rx_en)
 684                 val |= ENET_RXCFG_ENFLOW_MASK;
 685         else
 686                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 687         enet_writel(priv, val, ENET_RXCFG_REG);
 688
 689         /* tx flow control (pause frame generation) */
 690         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 691         if (tx_en)
 692                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 693         else
 694                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 695         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 696 }
 697
 698 /*
 699  * link changed callback (from phylib)
 700  */
 701 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 702 {
 703         struct bcm_enet_priv *priv;
 704         struct phy_device *phydev;
 705         int status_changed;
 706
 707         priv = netdev_priv(dev);
 708         phydev = priv->phydev;
 709         status_changed = 0;
 710
 711         if (priv->old_link != phydev->link) {
 712                 status_changed = 1;
 713                 priv->old_link = phydev->link;
 714         }
 715
 716         /* reflect duplex change in mac configuration */
 717         if (phydev->link && phydev->duplex != priv->old_duplex) {
 718                 bcm_enet_set_duplex(priv,
 719                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 720                 status_changed = 1;
 721                 priv->old_duplex = phydev->duplex;
 722         }
 723
 724         /* enable flow control if remote advertise it (trust phylib to
 725          * check that duplex is full */
 726         if (phydev->link && phydev->pause != priv->old_pause) {
 727                 int rx_pause_en, tx_pause_en;
 728
 729                 if (phydev->pause) {
 730                         /* pause was advertised by lpa and us */
 731                         rx_pause_en = 1;
 732                         tx_pause_en = 1;
 733                 } else if (!priv->pause_auto) {
 734                         /* pause setting overrided by user */
 735                         rx_pause_en = priv->pause_rx;
 736                         tx_pause_en = priv->pause_tx;
 737                 } else {
 738                         rx_pause_en = 0;
 739                         tx_pause_en = 0;
 740                 }
 741
 742                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 743                 status_changed = 1;
 744                 priv->old_pause = phydev->pause;
 745         }
 746
 747         if (status_changed) {
 748                 pr_info("%s: link %s", dev->name, phydev->link ?
 749                         "UP" : "DOWN");
 750                 if (phydev->link)
 751                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 752                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 753                                phydev->pause == 1 ? "rx&tx" : "off");
 754
 755                 pr_cont("\n");
 756         }
 757 }
 758
 759 /*
 760  * link changed callback (if phylib is not used)
 761  */
 762 static void bcm_enet_adjust_link(struct net_device *dev)
 763 {
 764         struct bcm_enet_priv *priv;
 765
 766         priv = netdev_priv(dev);
 767         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 768         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 769         netif_carrier_on(dev);
 770
 771         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 772                 dev->name,
 773                 priv->force_speed_100 ? 100 : 10,
 774                 priv->force_duplex_full ? "full" : "half",
 775                 priv->pause_rx ? "rx" : "off",
 776                 priv->pause_tx ? "tx" : "off");
 777 }
 778
 779 /*
 780  * open callback, allocate dma rings & buffers and start rx operation
 781  */
 782 static int bcm_enet_open(struct net_device *dev)
 783 {
 784         struct bcm_enet_priv *priv;
 785         struct sockaddr addr;
 786         struct device *kdev;
 787         struct phy_device *phydev;
 788         int i, ret;
 789         unsigned int size;
 790         char phy_id[MII_BUS_ID_SIZE + 3];
 791         void *p;
 792         u32 val;
 793
 794         priv = netdev_priv(dev);
 795         kdev = &priv->pdev->dev;
 796
 797         if (priv->has_phy) {
 798                 /* connect to PHY */
 799                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 800                          priv->mii_bus->id, priv->phy_id);
 801
 802                 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
 803                                      PHY_INTERFACE_MODE_MII);
 804
 805                 if (IS_ERR(phydev)) {
 806                         dev_err(kdev, "could not attach to PHY\n");
 807                         return PTR_ERR(phydev);
 808                 }
 809
 810                 /* mask with MAC supported features */
 811                 phydev->supported &= (SUPPORTED_10baseT_Half |
 812                                       SUPPORTED_10baseT_Full |
 813                                       SUPPORTED_100baseT_Half |
 814                                       SUPPORTED_100baseT_Full |
 815                                       SUPPORTED_Autoneg |
 816                                       SUPPORTED_Pause |
 817                                       SUPPORTED_MII);
 818                 phydev->advertising = phydev->supported;
 819
 820                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 821                         phydev->advertising |= SUPPORTED_Pause;
 822                 else
 823                         phydev->advertising &= ~SUPPORTED_Pause;
 824
 825                 dev_info(kdev, "attached PHY at address %d [%s]\n",
 826                          phydev->addr, phydev->drv->name);
 827
 828                 priv->old_link = 0;
 829                 priv->old_duplex = -1;
 830                 priv->old_pause = -1;
 831                 priv->phydev = phydev;
 832         }
 833
 834         /* mask all interrupts and request them */
 835         enet_writel(priv, 0, ENET_IRMASK_REG);
 836         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
 837         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
 838
 839         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 840         if (ret)
 841                 goto out_phy_disconnect;
 842
 843         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, IRQF_DISABLED,
 844                           dev->name, dev);
 845         if (ret)
 846                 goto out_freeirq;
 847
 848         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 849                           IRQF_DISABLED, dev->name, dev);
 850         if (ret)
 851                 goto out_freeirq_rx;
 852
 853         /* initialize perfect match registers */
 854         for (i = 0; i < 4; i++) {
 855                 enet_writel(priv, 0, ENET_PML_REG(i));
 856                 enet_writel(priv, 0, ENET_PMH_REG(i));
 857         }
 858
 859         /* write device mac address */
 860         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 861         bcm_enet_set_mac_address(dev, &addr);
 862
 863         /* allocate rx dma ring */
 864         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 865         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 866         if (!p) {
 867                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
 868                 ret = -ENOMEM;
 869                 goto out_freeirq_tx;
 870         }
 871
 872         memset(p, 0, size);
 873         priv->rx_desc_alloc_size = size;
 874         priv->rx_desc_cpu = p;
 875
 876         /* allocate tx dma ring */
 877         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 878         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 879         if (!p) {
 880                 dev_err(kdev, "cannot allocate tx ring\n");
 881                 ret = -ENOMEM;
 882                 goto out_free_rx_ring;
 883         }
 884
 885         memset(p, 0, size);
 886         priv->tx_desc_alloc_size = size;
 887         priv->tx_desc_cpu = p;
 888
 889         priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
 890                                GFP_KERNEL);
 891         if (!priv->tx_skb) {
 892                 ret = -ENOMEM;
 893                 goto out_free_tx_ring;
 894         }
 895
 896         priv->tx_desc_count = priv->tx_ring_size;
 897         priv->tx_dirty_desc = 0;
 898         priv->tx_curr_desc = 0;
 899         spin_lock_init(&priv->tx_lock);
 900
 901         /* init & fill rx ring with skbs */
 902         priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
 903                                GFP_KERNEL);
 904         if (!priv->rx_skb) {
 905                 ret = -ENOMEM;
 906                 goto out_free_tx_skb;
 907         }
 908
 909         priv->rx_desc_count = 0;
 910         priv->rx_dirty_desc = 0;
 911         priv->rx_curr_desc = 0;
 912
 913         /* initialize flow control buffer allocation */
 914         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 915                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
 916
 917         if (bcm_enet_refill_rx(dev)) {
 918                 dev_err(kdev, "cannot allocate rx skb queue\n");
 919                 ret = -ENOMEM;
 920                 goto out;
 921         }
 922
 923         /* write rx & tx ring addresses */
 924         enet_dma_writel(priv, priv->rx_desc_dma,
 925                         ENETDMA_RSTART_REG(priv->rx_chan));
 926         enet_dma_writel(priv, priv->tx_desc_dma,
 927                         ENETDMA_RSTART_REG(priv->tx_chan));
 928
 929         /* clear remaining state ram for rx & tx channel */
 930         enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
 931         enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
 932         enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
 933         enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
 934         enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
 935         enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
 936
 937         /* set max rx/tx length */
 938         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
 939         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
 940
 941         /* set dma maximum burst len */
 942         enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
 943                         ENETDMA_MAXBURST_REG(priv->rx_chan));
 944         enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
 945                         ENETDMA_MAXBURST_REG(priv->tx_chan));
 946
 947         /* set correct transmit fifo watermark */
 948         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
 949
 950         /* set flow control low/high threshold to 1/3 / 2/3 */
 951         val = priv->rx_ring_size / 3;
 952         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
 953         val = (priv->rx_ring_size * 2) / 3;
 954         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
 955
 956         /* all set, enable mac and interrupts, start dma engine and
 957          * kick rx dma channel */
 958         wmb();
 959         val = enet_readl(priv, ENET_CTL_REG);
 960         val |= ENET_CTL_ENABLE_MASK;
 961         enet_writel(priv, val, ENET_CTL_REG);
 962         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
 963         enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
 964                         ENETDMA_CHANCFG_REG(priv->rx_chan));
 965
 966         /* watch "mib counters about to overflow" interrupt */
 967         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 968         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
 969
 970         /* watch "packet transferred" interrupt in rx and tx */
 971         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 972                         ENETDMA_IR_REG(priv->rx_chan));
 973         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 974                         ENETDMA_IR_REG(priv->tx_chan));
 975
 976         /* make sure we enable napi before rx interrupt  */
 977         napi_enable(&priv->napi);
 978
 979         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 980                         ENETDMA_IRMASK_REG(priv->rx_chan));
 981         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 982                         ENETDMA_IRMASK_REG(priv->tx_chan));
 983
 984         if (priv->has_phy)
 985                 phy_start(priv->phydev);
 986         else
 987                 bcm_enet_adjust_link(dev);
 988
 989         netif_start_queue(dev);
 990         return 0;
 991
 992 out:
 993         for (i = 0; i < priv->rx_ring_size; i++) {
 994                 struct bcm_enet_desc *desc;
 995
 996                 if (!priv->rx_skb[i])
 997                         continue;
 998
 999                 desc = &priv->rx_desc_cpu[i];
1000                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1001                                  DMA_FROM_DEVICE);
1002                 kfree_skb(priv->rx_skb[i]);
1003         }
1004         kfree(priv->rx_skb);
1005
1006 out_free_tx_skb:
1007         kfree(priv->tx_skb);
1008
1009 out_free_tx_ring:
1010         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1011                           priv->tx_desc_cpu, priv->tx_desc_dma);
1012
1013 out_free_rx_ring:
1014         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1015                           priv->rx_desc_cpu, priv->rx_desc_dma);
1016
1017 out_freeirq_tx:
1018         free_irq(priv->irq_tx, dev);
1019
1020 out_freeirq_rx:
1021         free_irq(priv->irq_rx, dev);
1022
1023 out_freeirq:
1024         free_irq(dev->irq, dev);
1025
1026 out_phy_disconnect:
1027         phy_disconnect(priv->phydev);
1028
1029         return ret;
1030 }
1031
1032 /*
1033  * disable mac
1034  */
1035 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1036 {
1037         int limit;
1038         u32 val;
1039
1040         val = enet_readl(priv, ENET_CTL_REG);
1041         val |= ENET_CTL_DISABLE_MASK;
1042         enet_writel(priv, val, ENET_CTL_REG);
1043
1044         limit = 1000;
1045         do {
1046                 u32 val;
1047
1048                 val = enet_readl(priv, ENET_CTL_REG);
1049                 if (!(val & ENET_CTL_DISABLE_MASK))
1050                         break;
1051                 udelay(1);
1052         } while (limit--);
1053 }
1054
1055 /*
1056  * disable dma in given channel
1057  */
1058 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1059 {
1060         int limit;
1061
1062         enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
1063
1064         limit = 1000;
1065         do {
1066                 u32 val;
1067
1068                 val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
1069                 if (!(val & ENETDMA_CHANCFG_EN_MASK))
1070                         break;
1071                 udelay(1);
1072         } while (limit--);
1073 }
1074
1075 /*
1076  * stop callback
1077  */
1078 static int bcm_enet_stop(struct net_device *dev)
1079 {
1080         struct bcm_enet_priv *priv;
1081         struct device *kdev;
1082         int i;
1083
1084         priv = netdev_priv(dev);
1085         kdev = &priv->pdev->dev;
1086
1087         netif_stop_queue(dev);
1088         napi_disable(&priv->napi);
1089         if (priv->has_phy)
1090                 phy_stop(priv->phydev);
1091         del_timer_sync(&priv->rx_timeout);
1092
1093         /* mask all interrupts */
1094         enet_writel(priv, 0, ENET_IRMASK_REG);
1095         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
1096         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
1097
1098         /* make sure no mib update is scheduled */
1099         cancel_work_sync(&priv->mib_update_task);
1100
1101         /* disable dma & mac */
1102         bcm_enet_disable_dma(priv, priv->tx_chan);
1103         bcm_enet_disable_dma(priv, priv->rx_chan);
1104         bcm_enet_disable_mac(priv);
1105
1106         /* force reclaim of all tx buffers */
1107         bcm_enet_tx_reclaim(dev, 1);
1108
1109         /* free the rx skb ring */
1110         for (i = 0; i < priv->rx_ring_size; i++) {
1111                 struct bcm_enet_desc *desc;
1112
1113                 if (!priv->rx_skb[i])
1114                         continue;
1115
1116                 desc = &priv->rx_desc_cpu[i];
1117                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1118                                  DMA_FROM_DEVICE);
1119                 kfree_skb(priv->rx_skb[i]);
1120         }
1121
1122         /* free remaining allocated memory */
1123         kfree(priv->rx_skb);
1124         kfree(priv->tx_skb);
1125         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1126                           priv->rx_desc_cpu, priv->rx_desc_dma);
1127         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1128                           priv->tx_desc_cpu, priv->tx_desc_dma);
1129         free_irq(priv->irq_tx, dev);
1130         free_irq(priv->irq_rx, dev);
1131         free_irq(dev->irq, dev);
1132
1133         /* release phy */
1134         if (priv->has_phy) {
1135                 phy_disconnect(priv->phydev);
1136                 priv->phydev = NULL;
1137         }
1138
1139         return 0;
1140 }
1141
1142 /*
1143  * ethtool callbacks
1144  */
1145 struct bcm_enet_stats {
1146         char stat_string[ETH_GSTRING_LEN];
1147         int sizeof_stat;
1148         int stat_offset;
1149         int mib_reg;
1150 };
1151
1152 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1153                      offsetof(struct bcm_enet_priv, m)
1154 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m),          \
1155                      offsetof(struct net_device_stats, m)
1156
1157 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1158         { "rx_packets", DEV_STAT(rx_packets), -1 },
1159         { "tx_packets", DEV_STAT(tx_packets), -1 },
1160         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1161         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1162         { "rx_errors", DEV_STAT(rx_errors), -1 },
1163         { "tx_errors", DEV_STAT(tx_errors), -1 },
1164         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1165         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1166
1167         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1168         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1169         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1170         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1171         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1172         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1173         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1174         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1175         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1176         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1177         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1178         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1179         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1180         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1181         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1182         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1183         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1184         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1185         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1186         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1187         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1188
1189         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1190         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1191         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1192         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1193         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1194         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1195         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1196         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1197         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1198         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1199         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1200         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1201         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1202         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1203         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1204         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1205         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1206         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1207         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1208         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1209         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1210         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1211
1212 };
1213
1214 #define BCM_ENET_STATS_LEN      \
1215         (sizeof(bcm_enet_gstrings_stats) / sizeof(struct bcm_enet_stats))
1216
1217 static const u32 unused_mib_regs[] = {
1218         ETH_MIB_TX_ALL_OCTETS,
1219         ETH_MIB_TX_ALL_PKTS,
1220         ETH_MIB_RX_ALL_OCTETS,
1221         ETH_MIB_RX_ALL_PKTS,
1222 };
1223
1224
1225 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1226                                  struct ethtool_drvinfo *drvinfo)
1227 {
1228         strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1229         strlcpy(drvinfo->version, bcm_enet_driver_version,
1230                 sizeof(drvinfo->version));
1231         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1232         strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1233         drvinfo->n_stats = BCM_ENET_STATS_LEN;
1234 }
1235
1236 static int bcm_enet_get_sset_count(struct net_device *netdev,
1237                                         int string_set)
1238 {
1239         switch (string_set) {
1240         case ETH_SS_STATS:
1241                 return BCM_ENET_STATS_LEN;
1242         default:
1243                 return -EINVAL;
1244         }
1245 }
1246
1247 static void bcm_enet_get_strings(struct net_device *netdev,
1248                                  u32 stringset, u8 *data)
1249 {
1250         int i;
1251
1252         switch (stringset) {
1253         case ETH_SS_STATS:
1254                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1255                         memcpy(data + i * ETH_GSTRING_LEN,
1256                                bcm_enet_gstrings_stats[i].stat_string,
1257                                ETH_GSTRING_LEN);
1258                 }
1259                 break;
1260         }
1261 }
1262
1263 static void update_mib_counters(struct bcm_enet_priv *priv)
1264 {
1265         int i;
1266
1267         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1268                 const struct bcm_enet_stats *s;
1269                 u32 val;
1270                 char *p;
1271
1272                 s = &bcm_enet_gstrings_stats[i];
1273                 if (s->mib_reg == -1)
1274                         continue;
1275
1276                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1277                 p = (char *)priv + s->stat_offset;
1278
1279                 if (s->sizeof_stat == sizeof(u64))
1280                         *(u64 *)p += val;
1281                 else
1282                         *(u32 *)p += val;
1283         }
1284
1285         /* also empty unused mib counters to make sure mib counter
1286          * overflow interrupt is cleared */
1287         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1288                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1289 }
1290
1291 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1292 {
1293         struct bcm_enet_priv *priv;
1294
1295         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1296         mutex_lock(&priv->mib_update_lock);
1297         update_mib_counters(priv);
1298         mutex_unlock(&priv->mib_update_lock);
1299
1300         /* reenable mib interrupt */
1301         if (netif_running(priv->net_dev))
1302                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1303 }
1304
1305 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1306                                        struct ethtool_stats *stats,
1307                                        u64 *data)
1308 {
1309         struct bcm_enet_priv *priv;
1310         int i;
1311
1312         priv = netdev_priv(netdev);
1313
1314         mutex_lock(&priv->mib_update_lock);
1315         update_mib_counters(priv);
1316
1317         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1318                 const struct bcm_enet_stats *s;
1319                 char *p;
1320
1321                 s = &bcm_enet_gstrings_stats[i];
1322                 if (s->mib_reg == -1)
1323                         p = (char *)&netdev->stats;
1324                 else
1325                         p = (char *)priv;
1326                 p += s->stat_offset;
1327                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1328                         *(u64 *)p : *(u32 *)p;
1329         }
1330         mutex_unlock(&priv->mib_update_lock);
1331 }
1332
1333 static int bcm_enet_get_settings(struct net_device *dev,
1334                                  struct ethtool_cmd *cmd)
1335 {
1336         struct bcm_enet_priv *priv;
1337
1338         priv = netdev_priv(dev);
1339
1340         cmd->maxrxpkt = 0;
1341         cmd->maxtxpkt = 0;
1342
1343         if (priv->has_phy) {
1344                 if (!priv->phydev)
1345                         return -ENODEV;
1346                 return phy_ethtool_gset(priv->phydev, cmd);
1347         } else {
1348                 cmd->autoneg = 0;
1349                 ethtool_cmd_speed_set(cmd, ((priv->force_speed_100)
1350                                             ? SPEED_100 : SPEED_10));
1351                 cmd->duplex = (priv->force_duplex_full) ?
1352                         DUPLEX_FULL : DUPLEX_HALF;
1353                 cmd->supported = ADVERTISED_10baseT_Half  |
1354                         ADVERTISED_10baseT_Full |
1355                         ADVERTISED_100baseT_Half |
1356                         ADVERTISED_100baseT_Full;
1357                 cmd->advertising = 0;
1358                 cmd->port = PORT_MII;
1359                 cmd->transceiver = XCVR_EXTERNAL;
1360         }
1361         return 0;
1362 }
1363
1364 static int bcm_enet_set_settings(struct net_device *dev,
1365                                  struct ethtool_cmd *cmd)
1366 {
1367         struct bcm_enet_priv *priv;
1368
1369         priv = netdev_priv(dev);
1370         if (priv->has_phy) {
1371                 if (!priv->phydev)
1372                         return -ENODEV;
1373                 return phy_ethtool_sset(priv->phydev, cmd);
1374         } else {
1375
1376                 if (cmd->autoneg ||
1377                     (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) ||
1378                     cmd->port != PORT_MII)
1379                         return -EINVAL;
1380
1381                 priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0;
1382                 priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0;
1383
1384                 if (netif_running(dev))
1385                         bcm_enet_adjust_link(dev);
1386                 return 0;
1387         }
1388 }
1389
1390 static void bcm_enet_get_ringparam(struct net_device *dev,
1391                                    struct ethtool_ringparam *ering)
1392 {
1393         struct bcm_enet_priv *priv;
1394
1395         priv = netdev_priv(dev);
1396
1397         /* rx/tx ring is actually only limited by memory */
1398         ering->rx_max_pending = 8192;
1399         ering->tx_max_pending = 8192;
1400         ering->rx_pending = priv->rx_ring_size;
1401         ering->tx_pending = priv->tx_ring_size;
1402 }
1403
1404 static int bcm_enet_set_ringparam(struct net_device *dev,
1405                                   struct ethtool_ringparam *ering)
1406 {
1407         struct bcm_enet_priv *priv;
1408         int was_running;
1409
1410         priv = netdev_priv(dev);
1411
1412         was_running = 0;
1413         if (netif_running(dev)) {
1414                 bcm_enet_stop(dev);
1415                 was_running = 1;
1416         }
1417
1418         priv->rx_ring_size = ering->rx_pending;
1419         priv->tx_ring_size = ering->tx_pending;
1420
1421         if (was_running) {
1422                 int err;
1423
1424                 err = bcm_enet_open(dev);
1425                 if (err)
1426                         dev_close(dev);
1427                 else
1428                         bcm_enet_set_multicast_list(dev);
1429         }
1430         return 0;
1431 }
1432
1433 static void bcm_enet_get_pauseparam(struct net_device *dev,
1434                                     struct ethtool_pauseparam *ecmd)
1435 {
1436         struct bcm_enet_priv *priv;
1437
1438         priv = netdev_priv(dev);
1439         ecmd->autoneg = priv->pause_auto;
1440         ecmd->rx_pause = priv->pause_rx;
1441         ecmd->tx_pause = priv->pause_tx;
1442 }
1443
1444 static int bcm_enet_set_pauseparam(struct net_device *dev,
1445                                    struct ethtool_pauseparam *ecmd)
1446 {
1447         struct bcm_enet_priv *priv;
1448
1449         priv = netdev_priv(dev);
1450
1451         if (priv->has_phy) {
1452                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1453                         /* asymetric pause mode not supported,
1454                          * actually possible but integrated PHY has RO
1455                          * asym_pause bit */
1456                         return -EINVAL;
1457                 }
1458         } else {
1459                 /* no pause autoneg on direct mii connection */
1460                 if (ecmd->autoneg)
1461                         return -EINVAL;
1462         }
1463
1464         priv->pause_auto = ecmd->autoneg;
1465         priv->pause_rx = ecmd->rx_pause;
1466         priv->pause_tx = ecmd->tx_pause;
1467
1468         return 0;
1469 }
1470
1471 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1472         .get_strings            = bcm_enet_get_strings,
1473         .get_sset_count         = bcm_enet_get_sset_count,
1474         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1475         .get_settings           = bcm_enet_get_settings,
1476         .set_settings           = bcm_enet_set_settings,
1477         .get_drvinfo            = bcm_enet_get_drvinfo,
1478         .get_link               = ethtool_op_get_link,
1479         .get_ringparam          = bcm_enet_get_ringparam,
1480         .set_ringparam          = bcm_enet_set_ringparam,
1481         .get_pauseparam         = bcm_enet_get_pauseparam,
1482         .set_pauseparam         = bcm_enet_set_pauseparam,
1483 };
1484
1485 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1486 {
1487         struct bcm_enet_priv *priv;
1488
1489         priv = netdev_priv(dev);
1490         if (priv->has_phy) {
1491                 if (!priv->phydev)
1492                         return -ENODEV;
1493                 return phy_mii_ioctl(priv->phydev, rq, cmd);
1494         } else {
1495                 struct mii_if_info mii;
1496
1497                 mii.dev = dev;
1498                 mii.mdio_read = bcm_enet_mdio_read_mii;
1499                 mii.mdio_write = bcm_enet_mdio_write_mii;
1500                 mii.phy_id = 0;
1501                 mii.phy_id_mask = 0x3f;
1502                 mii.reg_num_mask = 0x1f;
1503                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1504         }
1505 }
1506
1507 /*
1508  * calculate actual hardware mtu
1509  */
1510 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1511 {
1512         int actual_mtu;
1513
1514         actual_mtu = mtu;
1515
1516         /* add ethernet header + vlan tag size */
1517         actual_mtu += VLAN_ETH_HLEN;
1518
1519         if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1520                 return -EINVAL;
1521
1522         /*
1523          * setup maximum size before we get overflow mark in
1524          * descriptor, note that this will not prevent reception of
1525          * big frames, they will be split into multiple buffers
1526          * anyway
1527          */
1528         priv->hw_mtu = actual_mtu;
1529
1530         /*
1531          * align rx buffer size to dma burst len, account FCS since
1532          * it's appended
1533          */
1534         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1535                                   BCMENET_DMA_MAXBURST * 4);
1536         return 0;
1537 }
1538
1539 /*
1540  * adjust mtu, can't be called while device is running
1541  */
1542 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1543 {
1544         int ret;
1545
1546         if (netif_running(dev))
1547                 return -EBUSY;
1548
1549         ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1550         if (ret)
1551                 return ret;
1552         dev->mtu = new_mtu;
1553         return 0;
1554 }
1555
1556 /*
1557  * preinit hardware to allow mii operation while device is down
1558  */
1559 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1560 {
1561         u32 val;
1562         int limit;
1563
1564         /* make sure mac is disabled */
1565         bcm_enet_disable_mac(priv);
1566
1567         /* soft reset mac */
1568         val = ENET_CTL_SRESET_MASK;
1569         enet_writel(priv, val, ENET_CTL_REG);
1570         wmb();
1571
1572         limit = 1000;
1573         do {
1574                 val = enet_readl(priv, ENET_CTL_REG);
1575                 if (!(val & ENET_CTL_SRESET_MASK))
1576                         break;
1577                 udelay(1);
1578         } while (limit--);
1579
1580         /* select correct mii interface */
1581         val = enet_readl(priv, ENET_CTL_REG);
1582         if (priv->use_external_mii)
1583                 val |= ENET_CTL_EPHYSEL_MASK;
1584         else
1585                 val &= ~ENET_CTL_EPHYSEL_MASK;
1586         enet_writel(priv, val, ENET_CTL_REG);
1587
1588         /* turn on mdc clock */
1589         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1590                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1591
1592         /* set mib counters to self-clear when read */
1593         val = enet_readl(priv, ENET_MIBCTL_REG);
1594         val |= ENET_MIBCTL_RDCLEAR_MASK;
1595         enet_writel(priv, val, ENET_MIBCTL_REG);
1596 }
1597
1598 static const struct net_device_ops bcm_enet_ops = {
1599         .ndo_open               = bcm_enet_open,
1600         .ndo_stop               = bcm_enet_stop,
1601         .ndo_start_xmit         = bcm_enet_start_xmit,
1602         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1603         .ndo_set_rx_mode        = bcm_enet_set_multicast_list,
1604         .ndo_do_ioctl           = bcm_enet_ioctl,
1605         .ndo_change_mtu         = bcm_enet_change_mtu,
1606 #ifdef CONFIG_NET_POLL_CONTROLLER
1607         .ndo_poll_controller = bcm_enet_netpoll,
1608 #endif
1609 };
1610
1611 /*
1612  * allocate netdevice, request register memory and register device.
1613  */
1614 static int bcm_enet_probe(struct platform_device *pdev)
1615 {
1616         struct bcm_enet_priv *priv;
1617         struct net_device *dev;
1618         struct bcm63xx_enet_platform_data *pd;
1619         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1620         struct mii_bus *bus;
1621         const char *clk_name;
1622         unsigned int iomem_size;
1623         int i, ret;
1624
1625         /* stop if shared driver failed, assume driver->probe will be
1626          * called in the same order we register devices (correct ?) */
1627         if (!bcm_enet_shared_base)
1628                 return -ENODEV;
1629
1630         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1631         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1632         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1633         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1634         if (!res_mem || !res_irq || !res_irq_rx || !res_irq_tx)
1635                 return -ENODEV;
1636
1637         ret = 0;
1638         dev = alloc_etherdev(sizeof(*priv));
1639         if (!dev)
1640                 return -ENOMEM;
1641         priv = netdev_priv(dev);
1642
1643         ret = compute_hw_mtu(priv, dev->mtu);
1644         if (ret)
1645                 goto out;
1646
1647         iomem_size = resource_size(res_mem);
1648         if (!request_mem_region(res_mem->start, iomem_size, "bcm63xx_enet")) {
1649                 ret = -EBUSY;
1650                 goto out;
1651         }
1652
1653         priv->base = ioremap(res_mem->start, iomem_size);
1654         if (priv->base == NULL) {
1655                 ret = -ENOMEM;
1656                 goto out_release_mem;
1657         }
1658         dev->irq = priv->irq = res_irq->start;
1659         priv->irq_rx = res_irq_rx->start;
1660         priv->irq_tx = res_irq_tx->start;
1661         priv->mac_id = pdev->id;
1662
1663         /* get rx & tx dma channel id for this mac */
1664         if (priv->mac_id == 0) {
1665                 priv->rx_chan = 0;
1666                 priv->tx_chan = 1;
1667                 clk_name = "enet0";
1668         } else {
1669                 priv->rx_chan = 2;
1670                 priv->tx_chan = 3;
1671                 clk_name = "enet1";
1672         }
1673
1674         priv->mac_clk = clk_get(&pdev->dev, clk_name);
1675         if (IS_ERR(priv->mac_clk)) {
1676                 ret = PTR_ERR(priv->mac_clk);
1677                 goto out_unmap;
1678         }
1679         clk_enable(priv->mac_clk);
1680
1681         /* initialize default and fetch platform data */
1682         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1683         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1684
1685         pd = pdev->dev.platform_data;
1686         if (pd) {
1687                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1688                 priv->has_phy = pd->has_phy;
1689                 priv->phy_id = pd->phy_id;
1690                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1691                 priv->phy_interrupt = pd->phy_interrupt;
1692                 priv->use_external_mii = !pd->use_internal_phy;
1693                 priv->pause_auto = pd->pause_auto;
1694                 priv->pause_rx = pd->pause_rx;
1695                 priv->pause_tx = pd->pause_tx;
1696                 priv->force_duplex_full = pd->force_duplex_full;
1697                 priv->force_speed_100 = pd->force_speed_100;
1698         }
1699
1700         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1701                 /* using internal PHY, enable clock */
1702                 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1703                 if (IS_ERR(priv->phy_clk)) {
1704                         ret = PTR_ERR(priv->phy_clk);
1705                         priv->phy_clk = NULL;
1706                         goto out_put_clk_mac;
1707                 }
1708                 clk_enable(priv->phy_clk);
1709         }
1710
1711         /* do minimal hardware init to be able to probe mii bus */
1712         bcm_enet_hw_preinit(priv);
1713
1714         /* MII bus registration */
1715         if (priv->has_phy) {
1716
1717                 priv->mii_bus = mdiobus_alloc();
1718                 if (!priv->mii_bus) {
1719                         ret = -ENOMEM;
1720                         goto out_uninit_hw;
1721                 }
1722
1723                 bus = priv->mii_bus;
1724                 bus->name = "bcm63xx_enet MII bus";
1725                 bus->parent = &pdev->dev;
1726                 bus->priv = priv;
1727                 bus->read = bcm_enet_mdio_read_phylib;
1728                 bus->write = bcm_enet_mdio_write_phylib;
1729                 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
1730
1731                 /* only probe bus where we think the PHY is, because
1732                  * the mdio read operation return 0 instead of 0xffff
1733                  * if a slave is not present on hw */
1734                 bus->phy_mask = ~(1 << priv->phy_id);
1735
1736                 bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1737                 if (!bus->irq) {
1738                         ret = -ENOMEM;
1739                         goto out_free_mdio;
1740                 }
1741
1742                 if (priv->has_phy_interrupt)
1743                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1744                 else
1745                         bus->irq[priv->phy_id] = PHY_POLL;
1746
1747                 ret = mdiobus_register(bus);
1748                 if (ret) {
1749                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1750                         goto out_free_mdio;
1751                 }
1752         } else {
1753
1754                 /* run platform code to initialize PHY device */
1755                 if (pd->mii_config &&
1756                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1757                                    bcm_enet_mdio_write_mii)) {
1758                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1759                         goto out_uninit_hw;
1760                 }
1761         }
1762
1763         spin_lock_init(&priv->rx_lock);
1764
1765         /* init rx timeout (used for oom) */
1766         init_timer(&priv->rx_timeout);
1767         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1768         priv->rx_timeout.data = (unsigned long)dev;
1769
1770         /* init the mib update lock&work */
1771         mutex_init(&priv->mib_update_lock);
1772         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1773
1774         /* zero mib counters */
1775         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1776                 enet_writel(priv, 0, ENET_MIB_REG(i));
1777
1778         /* register netdevice */
1779         dev->netdev_ops = &bcm_enet_ops;
1780         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1781
1782         SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops);
1783         SET_NETDEV_DEV(dev, &pdev->dev);
1784
1785         ret = register_netdev(dev);
1786         if (ret)
1787                 goto out_unregister_mdio;
1788
1789         netif_carrier_off(dev);
1790         platform_set_drvdata(pdev, dev);
1791         priv->pdev = pdev;
1792         priv->net_dev = dev;
1793
1794         return 0;
1795
1796 out_unregister_mdio:
1797         if (priv->mii_bus) {
1798                 mdiobus_unregister(priv->mii_bus);
1799                 kfree(priv->mii_bus->irq);
1800         }
1801
1802 out_free_mdio:
1803         if (priv->mii_bus)
1804                 mdiobus_free(priv->mii_bus);
1805
1806 out_uninit_hw:
1807         /* turn off mdc clock */
1808         enet_writel(priv, 0, ENET_MIISC_REG);
1809         if (priv->phy_clk) {
1810                 clk_disable(priv->phy_clk);
1811                 clk_put(priv->phy_clk);
1812         }
1813
1814 out_put_clk_mac:
1815         clk_disable(priv->mac_clk);
1816         clk_put(priv->mac_clk);
1817
1818 out_unmap:
1819         iounmap(priv->base);
1820
1821 out_release_mem:
1822         release_mem_region(res_mem->start, iomem_size);
1823 out:
1824         free_netdev(dev);
1825         return ret;
1826 }
1827
1828
1829 /*
1830  * exit func, stops hardware and unregisters netdevice
1831  */
1832 static int bcm_enet_remove(struct platform_device *pdev)
1833 {
1834         struct bcm_enet_priv *priv;
1835         struct net_device *dev;
1836         struct resource *res;
1837
1838         /* stop netdevice */
1839         dev = platform_get_drvdata(pdev);
1840         priv = netdev_priv(dev);
1841         unregister_netdev(dev);
1842
1843         /* turn off mdc clock */
1844         enet_writel(priv, 0, ENET_MIISC_REG);
1845
1846         if (priv->has_phy) {
1847                 mdiobus_unregister(priv->mii_bus);
1848                 kfree(priv->mii_bus->irq);
1849                 mdiobus_free(priv->mii_bus);
1850         } else {
1851                 struct bcm63xx_enet_platform_data *pd;
1852
1853                 pd = pdev->dev.platform_data;
1854                 if (pd && pd->mii_config)
1855                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1856                                        bcm_enet_mdio_write_mii);
1857         }
1858
1859         /* release device resources */
1860         iounmap(priv->base);
1861         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1862         release_mem_region(res->start, resource_size(res));
1863
1864         /* disable hw block clocks */
1865         if (priv->phy_clk) {
1866                 clk_disable(priv->phy_clk);
1867                 clk_put(priv->phy_clk);
1868         }
1869         clk_disable(priv->mac_clk);
1870         clk_put(priv->mac_clk);
1871
1872         platform_set_drvdata(pdev, NULL);
1873         free_netdev(dev);
1874         return 0;
1875 }
1876
1877 struct platform_driver bcm63xx_enet_driver = {
1878         .probe  = bcm_enet_probe,
1879         .remove = bcm_enet_remove,
1880         .driver = {
1881                 .name   = "bcm63xx_enet",
1882                 .owner  = THIS_MODULE,
1883         },
1884 };
1885
1886 /*
1887  * reserve & remap memory space shared between all macs
1888  */
1889 static int bcm_enet_shared_probe(struct platform_device *pdev)
1890 {
1891         struct resource *res;
1892         unsigned int iomem_size;
1893
1894         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1895         if (!res)
1896                 return -ENODEV;
1897
1898         iomem_size = resource_size(res);
1899         if (!request_mem_region(res->start, iomem_size, "bcm63xx_enet_dma"))
1900                 return -EBUSY;
1901
1902         bcm_enet_shared_base = ioremap(res->start, iomem_size);
1903         if (!bcm_enet_shared_base) {
1904                 release_mem_region(res->start, iomem_size);
1905                 return -ENOMEM;
1906         }
1907         return 0;
1908 }
1909
1910 static int bcm_enet_shared_remove(struct platform_device *pdev)
1911 {
1912         struct resource *res;
1913
1914         iounmap(bcm_enet_shared_base);
1915         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1916         release_mem_region(res->start, resource_size(res));
1917         return 0;
1918 }
1919
1920 /*
1921  * this "shared" driver is needed because both macs share a single
1922  * address space
1923  */
1924 struct platform_driver bcm63xx_enet_shared_driver = {
1925         .probe  = bcm_enet_shared_probe,
1926         .remove = bcm_enet_shared_remove,
1927         .driver = {
1928                 .name   = "bcm63xx_enet_shared",
1929                 .owner  = THIS_MODULE,
1930         },
1931 };
1932
1933 /*
1934  * entry point
1935  */
1936 static int __init bcm_enet_init(void)
1937 {
1938         int ret;
1939
1940         ret = platform_driver_register(&bcm63xx_enet_shared_driver);
1941         if (ret)
1942                 return ret;
1943
1944         ret = platform_driver_register(&bcm63xx_enet_driver);
1945         if (ret)
1946                 platform_driver_unregister(&bcm63xx_enet_shared_driver);
1947
1948         return ret;
1949 }
1950
1951 static void __exit bcm_enet_exit(void)
1952 {
1953         platform_driver_unregister(&bcm63xx_enet_driver);
1954         platform_driver_unregister(&bcm63xx_enet_shared_driver);
1955 }
1956
1957
1958 module_init(bcm_enet_init);
1959 module_exit(bcm_enet_exit);
1960
1961 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
1962 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
1963 MODULE_LICENSE("GPL");