2 * Driver for BCM963xx builtin Ethernet mac
4 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/etherdevice.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/ethtool.h>
28 #include <linux/crc32.h>
29 #include <linux/err.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/if_vlan.h>
34 #include <bcm63xx_dev_enet.h>
35 #include "bcm63xx_enet.h"
37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
38 static char bcm_enet_driver_version[] = "1.0";
40 static int copybreak __read_mostly = 128;
41 module_param(copybreak, int, 0);
42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
44 /* io memory shared between all devices */
45 static void __iomem *bcm_enet_shared_base;
48 * io helpers to access mac registers
50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
52 return bcm_readl(priv->base + off);
55 static inline void enet_writel(struct bcm_enet_priv *priv,
58 bcm_writel(val, priv->base + off);
62 * io helpers to access shared registers
64 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
66 return bcm_readl(bcm_enet_shared_base + off);
69 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
72 bcm_writel(val, bcm_enet_shared_base + off);
76 * write given data into mii register and wait for transfer to end
77 * with timeout (average measured transfer time is 25us)
79 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
83 /* make sure mii interrupt status is cleared */
84 enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
86 enet_writel(priv, data, ENET_MIIDATA_REG);
89 /* busy wait on mii interrupt bit, with timeout */
92 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
95 } while (limit-- > 0);
97 return (limit < 0) ? 1 : 0;
101 * MII internal read callback
103 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
108 tmp = regnum << ENET_MIIDATA_REG_SHIFT;
109 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
110 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
111 tmp |= ENET_MIIDATA_OP_READ_MASK;
113 if (do_mdio_op(priv, tmp))
116 val = enet_readl(priv, ENET_MIIDATA_REG);
122 * MII internal write callback
124 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
125 int regnum, u16 value)
129 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
130 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
131 tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
132 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
133 tmp |= ENET_MIIDATA_OP_WRITE_MASK;
135 (void)do_mdio_op(priv, tmp);
140 * MII read callback from phylib
142 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
145 return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
149 * MII write callback from phylib
151 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
152 int regnum, u16 value)
154 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
158 * MII read callback from mii core
160 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
163 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
167 * MII write callback from mii core
169 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
170 int regnum, int value)
172 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
178 static int bcm_enet_refill_rx(struct net_device *dev)
180 struct bcm_enet_priv *priv;
182 priv = netdev_priv(dev);
184 while (priv->rx_desc_count < priv->rx_ring_size) {
185 struct bcm_enet_desc *desc;
191 desc_idx = priv->rx_dirty_desc;
192 desc = &priv->rx_desc_cpu[desc_idx];
194 if (!priv->rx_skb[desc_idx]) {
195 skb = netdev_alloc_skb(dev, priv->rx_skb_size);
198 priv->rx_skb[desc_idx] = skb;
200 p = dma_map_single(&priv->pdev->dev, skb->data,
206 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
207 len_stat |= DMADESC_OWNER_MASK;
208 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
209 len_stat |= DMADESC_WRAP_MASK;
210 priv->rx_dirty_desc = 0;
212 priv->rx_dirty_desc++;
215 desc->len_stat = len_stat;
217 priv->rx_desc_count++;
219 /* tell dma engine we allocated one buffer */
220 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
223 /* If rx ring is still empty, set a timer to try allocating
224 * again at a later time. */
225 if (priv->rx_desc_count == 0 && netif_running(dev)) {
226 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
227 priv->rx_timeout.expires = jiffies + HZ;
228 add_timer(&priv->rx_timeout);
235 * timer callback to defer refill rx queue in case we're OOM
237 static void bcm_enet_refill_rx_timer(unsigned long data)
239 struct net_device *dev;
240 struct bcm_enet_priv *priv;
242 dev = (struct net_device *)data;
243 priv = netdev_priv(dev);
245 spin_lock(&priv->rx_lock);
246 bcm_enet_refill_rx((struct net_device *)data);
247 spin_unlock(&priv->rx_lock);
251 * extract packet from rx queue
253 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
255 struct bcm_enet_priv *priv;
259 priv = netdev_priv(dev);
260 kdev = &priv->pdev->dev;
263 /* don't scan ring further than number of refilled
265 if (budget > priv->rx_desc_count)
266 budget = priv->rx_desc_count;
269 struct bcm_enet_desc *desc;
275 desc_idx = priv->rx_curr_desc;
276 desc = &priv->rx_desc_cpu[desc_idx];
278 /* make sure we actually read the descriptor status at
282 len_stat = desc->len_stat;
284 /* break if dma ownership belongs to hw */
285 if (len_stat & DMADESC_OWNER_MASK)
289 priv->rx_curr_desc++;
290 if (priv->rx_curr_desc == priv->rx_ring_size)
291 priv->rx_curr_desc = 0;
292 priv->rx_desc_count--;
294 /* if the packet does not have start of packet _and_
295 * end of packet flag set, then just recycle it */
296 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
297 dev->stats.rx_dropped++;
301 /* recycle packet if it's marked as bad */
302 if (unlikely(len_stat & DMADESC_ERR_MASK)) {
303 dev->stats.rx_errors++;
305 if (len_stat & DMADESC_OVSIZE_MASK)
306 dev->stats.rx_length_errors++;
307 if (len_stat & DMADESC_CRC_MASK)
308 dev->stats.rx_crc_errors++;
309 if (len_stat & DMADESC_UNDER_MASK)
310 dev->stats.rx_frame_errors++;
311 if (len_stat & DMADESC_OV_MASK)
312 dev->stats.rx_fifo_errors++;
317 skb = priv->rx_skb[desc_idx];
318 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
319 /* don't include FCS */
322 if (len < copybreak) {
323 struct sk_buff *nskb;
325 nskb = netdev_alloc_skb_ip_align(dev, len);
327 /* forget packet, just rearm desc */
328 dev->stats.rx_dropped++;
332 dma_sync_single_for_cpu(kdev, desc->address,
333 len, DMA_FROM_DEVICE);
334 memcpy(nskb->data, skb->data, len);
335 dma_sync_single_for_device(kdev, desc->address,
336 len, DMA_FROM_DEVICE);
339 dma_unmap_single(&priv->pdev->dev, desc->address,
340 priv->rx_skb_size, DMA_FROM_DEVICE);
341 priv->rx_skb[desc_idx] = NULL;
345 skb->protocol = eth_type_trans(skb, dev);
346 dev->stats.rx_packets++;
347 dev->stats.rx_bytes += len;
348 netif_receive_skb(skb);
350 } while (--budget > 0);
352 if (processed || !priv->rx_desc_count) {
353 bcm_enet_refill_rx(dev);
356 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
357 ENETDMA_CHANCFG_REG(priv->rx_chan));
365 * try to or force reclaim of transmitted buffers
367 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
369 struct bcm_enet_priv *priv;
372 priv = netdev_priv(dev);
375 while (priv->tx_desc_count < priv->tx_ring_size) {
376 struct bcm_enet_desc *desc;
379 /* We run in a bh and fight against start_xmit, which
380 * is called with bh disabled */
381 spin_lock(&priv->tx_lock);
383 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
385 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
386 spin_unlock(&priv->tx_lock);
390 /* ensure other field of the descriptor were not read
391 * before we checked ownership */
394 skb = priv->tx_skb[priv->tx_dirty_desc];
395 priv->tx_skb[priv->tx_dirty_desc] = NULL;
396 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
399 priv->tx_dirty_desc++;
400 if (priv->tx_dirty_desc == priv->tx_ring_size)
401 priv->tx_dirty_desc = 0;
402 priv->tx_desc_count++;
404 spin_unlock(&priv->tx_lock);
406 if (desc->len_stat & DMADESC_UNDER_MASK)
407 dev->stats.tx_errors++;
413 if (netif_queue_stopped(dev) && released)
414 netif_wake_queue(dev);
420 * poll func, called by network core
422 static int bcm_enet_poll(struct napi_struct *napi, int budget)
424 struct bcm_enet_priv *priv;
425 struct net_device *dev;
426 int tx_work_done, rx_work_done;
428 priv = container_of(napi, struct bcm_enet_priv, napi);
432 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
433 ENETDMA_IR_REG(priv->rx_chan));
434 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
435 ENETDMA_IR_REG(priv->tx_chan));
437 /* reclaim sent skb */
438 tx_work_done = bcm_enet_tx_reclaim(dev, 0);
440 spin_lock(&priv->rx_lock);
441 rx_work_done = bcm_enet_receive_queue(dev, budget);
442 spin_unlock(&priv->rx_lock);
444 if (rx_work_done >= budget || tx_work_done > 0) {
445 /* rx/tx queue is not yet empty/clean */
449 /* no more packet in rx/tx queue, remove device from poll
453 /* restore rx/tx interrupt */
454 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
455 ENETDMA_IRMASK_REG(priv->rx_chan));
456 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
457 ENETDMA_IRMASK_REG(priv->tx_chan));
463 * mac interrupt handler
465 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
467 struct net_device *dev;
468 struct bcm_enet_priv *priv;
472 priv = netdev_priv(dev);
474 stat = enet_readl(priv, ENET_IR_REG);
475 if (!(stat & ENET_IR_MIB))
478 /* clear & mask interrupt */
479 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
480 enet_writel(priv, 0, ENET_IRMASK_REG);
482 /* read mib registers in workqueue */
483 schedule_work(&priv->mib_update_task);
489 * rx/tx dma interrupt handler
491 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
493 struct net_device *dev;
494 struct bcm_enet_priv *priv;
497 priv = netdev_priv(dev);
499 /* mask rx/tx interrupts */
500 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
501 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
503 napi_schedule(&priv->napi);
509 * tx request callback
511 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
513 struct bcm_enet_priv *priv;
514 struct bcm_enet_desc *desc;
518 priv = netdev_priv(dev);
520 /* lock against tx reclaim */
521 spin_lock(&priv->tx_lock);
523 /* make sure the tx hw queue is not full, should not happen
524 * since we stop queue before it's the case */
525 if (unlikely(!priv->tx_desc_count)) {
526 netif_stop_queue(dev);
527 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
529 ret = NETDEV_TX_BUSY;
533 /* point to the next available desc */
534 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
535 priv->tx_skb[priv->tx_curr_desc] = skb;
537 /* fill descriptor */
538 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
541 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
542 len_stat |= DMADESC_ESOP_MASK |
546 priv->tx_curr_desc++;
547 if (priv->tx_curr_desc == priv->tx_ring_size) {
548 priv->tx_curr_desc = 0;
549 len_stat |= DMADESC_WRAP_MASK;
551 priv->tx_desc_count--;
553 /* dma might be already polling, make sure we update desc
554 * fields in correct order */
556 desc->len_stat = len_stat;
560 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
561 ENETDMA_CHANCFG_REG(priv->tx_chan));
563 /* stop queue if no more desc available */
564 if (!priv->tx_desc_count)
565 netif_stop_queue(dev);
567 dev->stats.tx_bytes += skb->len;
568 dev->stats.tx_packets++;
572 spin_unlock(&priv->tx_lock);
577 * Change the interface's mac address.
579 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
581 struct bcm_enet_priv *priv;
582 struct sockaddr *addr = p;
585 priv = netdev_priv(dev);
586 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
588 /* use perfect match register 0 to store my mac address */
589 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
590 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
591 enet_writel(priv, val, ENET_PML_REG(0));
593 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
594 val |= ENET_PMH_DATAVALID_MASK;
595 enet_writel(priv, val, ENET_PMH_REG(0));
601 * Change rx mode (promiscuous/allmulti) and update multicast list
603 static void bcm_enet_set_multicast_list(struct net_device *dev)
605 struct bcm_enet_priv *priv;
606 struct netdev_hw_addr *ha;
610 priv = netdev_priv(dev);
612 val = enet_readl(priv, ENET_RXCFG_REG);
614 if (dev->flags & IFF_PROMISC)
615 val |= ENET_RXCFG_PROMISC_MASK;
617 val &= ~ENET_RXCFG_PROMISC_MASK;
619 /* only 3 perfect match registers left, first one is used for
621 if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
622 val |= ENET_RXCFG_ALLMCAST_MASK;
624 val &= ~ENET_RXCFG_ALLMCAST_MASK;
626 /* no need to set perfect match registers if we catch all
628 if (val & ENET_RXCFG_ALLMCAST_MASK) {
629 enet_writel(priv, val, ENET_RXCFG_REG);
634 netdev_for_each_mc_addr(ha, dev) {
640 /* update perfect match registers */
642 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
643 (dmi_addr[4] << 8) | dmi_addr[5];
644 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
646 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
647 tmp |= ENET_PMH_DATAVALID_MASK;
648 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
652 enet_writel(priv, 0, ENET_PML_REG(i + 1));
653 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
656 enet_writel(priv, val, ENET_RXCFG_REG);
660 * set mac duplex parameters
662 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
666 val = enet_readl(priv, ENET_TXCTL_REG);
668 val |= ENET_TXCTL_FD_MASK;
670 val &= ~ENET_TXCTL_FD_MASK;
671 enet_writel(priv, val, ENET_TXCTL_REG);
675 * set mac flow control parameters
677 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
681 /* rx flow control (pause frame handling) */
682 val = enet_readl(priv, ENET_RXCFG_REG);
684 val |= ENET_RXCFG_ENFLOW_MASK;
686 val &= ~ENET_RXCFG_ENFLOW_MASK;
687 enet_writel(priv, val, ENET_RXCFG_REG);
689 /* tx flow control (pause frame generation) */
690 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
692 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
694 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
695 enet_dma_writel(priv, val, ENETDMA_CFG_REG);
699 * link changed callback (from phylib)
701 static void bcm_enet_adjust_phy_link(struct net_device *dev)
703 struct bcm_enet_priv *priv;
704 struct phy_device *phydev;
707 priv = netdev_priv(dev);
708 phydev = priv->phydev;
711 if (priv->old_link != phydev->link) {
713 priv->old_link = phydev->link;
716 /* reflect duplex change in mac configuration */
717 if (phydev->link && phydev->duplex != priv->old_duplex) {
718 bcm_enet_set_duplex(priv,
719 (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
721 priv->old_duplex = phydev->duplex;
724 /* enable flow control if remote advertise it (trust phylib to
725 * check that duplex is full */
726 if (phydev->link && phydev->pause != priv->old_pause) {
727 int rx_pause_en, tx_pause_en;
730 /* pause was advertised by lpa and us */
733 } else if (!priv->pause_auto) {
734 /* pause setting overrided by user */
735 rx_pause_en = priv->pause_rx;
736 tx_pause_en = priv->pause_tx;
742 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
744 priv->old_pause = phydev->pause;
747 if (status_changed) {
748 pr_info("%s: link %s", dev->name, phydev->link ?
751 pr_cont(" - %d/%s - flow control %s", phydev->speed,
752 DUPLEX_FULL == phydev->duplex ? "full" : "half",
753 phydev->pause == 1 ? "rx&tx" : "off");
760 * link changed callback (if phylib is not used)
762 static void bcm_enet_adjust_link(struct net_device *dev)
764 struct bcm_enet_priv *priv;
766 priv = netdev_priv(dev);
767 bcm_enet_set_duplex(priv, priv->force_duplex_full);
768 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
769 netif_carrier_on(dev);
771 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
773 priv->force_speed_100 ? 100 : 10,
774 priv->force_duplex_full ? "full" : "half",
775 priv->pause_rx ? "rx" : "off",
776 priv->pause_tx ? "tx" : "off");
780 * open callback, allocate dma rings & buffers and start rx operation
782 static int bcm_enet_open(struct net_device *dev)
784 struct bcm_enet_priv *priv;
785 struct sockaddr addr;
787 struct phy_device *phydev;
790 char phy_id[MII_BUS_ID_SIZE + 3];
794 priv = netdev_priv(dev);
795 kdev = &priv->pdev->dev;
799 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
800 priv->mii_bus->id, priv->phy_id);
802 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
803 PHY_INTERFACE_MODE_MII);
805 if (IS_ERR(phydev)) {
806 dev_err(kdev, "could not attach to PHY\n");
807 return PTR_ERR(phydev);
810 /* mask with MAC supported features */
811 phydev->supported &= (SUPPORTED_10baseT_Half |
812 SUPPORTED_10baseT_Full |
813 SUPPORTED_100baseT_Half |
814 SUPPORTED_100baseT_Full |
818 phydev->advertising = phydev->supported;
820 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
821 phydev->advertising |= SUPPORTED_Pause;
823 phydev->advertising &= ~SUPPORTED_Pause;
825 dev_info(kdev, "attached PHY at address %d [%s]\n",
826 phydev->addr, phydev->drv->name);
829 priv->old_duplex = -1;
830 priv->old_pause = -1;
831 priv->phydev = phydev;
834 /* mask all interrupts and request them */
835 enet_writel(priv, 0, ENET_IRMASK_REG);
836 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
837 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
839 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
841 goto out_phy_disconnect;
843 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, IRQF_DISABLED,
848 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
849 IRQF_DISABLED, dev->name, dev);
853 /* initialize perfect match registers */
854 for (i = 0; i < 4; i++) {
855 enet_writel(priv, 0, ENET_PML_REG(i));
856 enet_writel(priv, 0, ENET_PMH_REG(i));
859 /* write device mac address */
860 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
861 bcm_enet_set_mac_address(dev, &addr);
863 /* allocate rx dma ring */
864 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
865 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
867 dev_err(kdev, "cannot allocate rx ring %u\n", size);
873 priv->rx_desc_alloc_size = size;
874 priv->rx_desc_cpu = p;
876 /* allocate tx dma ring */
877 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
878 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
880 dev_err(kdev, "cannot allocate tx ring\n");
882 goto out_free_rx_ring;
886 priv->tx_desc_alloc_size = size;
887 priv->tx_desc_cpu = p;
889 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
893 goto out_free_tx_ring;
896 priv->tx_desc_count = priv->tx_ring_size;
897 priv->tx_dirty_desc = 0;
898 priv->tx_curr_desc = 0;
899 spin_lock_init(&priv->tx_lock);
901 /* init & fill rx ring with skbs */
902 priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
906 goto out_free_tx_skb;
909 priv->rx_desc_count = 0;
910 priv->rx_dirty_desc = 0;
911 priv->rx_curr_desc = 0;
913 /* initialize flow control buffer allocation */
914 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
915 ENETDMA_BUFALLOC_REG(priv->rx_chan));
917 if (bcm_enet_refill_rx(dev)) {
918 dev_err(kdev, "cannot allocate rx skb queue\n");
923 /* write rx & tx ring addresses */
924 enet_dma_writel(priv, priv->rx_desc_dma,
925 ENETDMA_RSTART_REG(priv->rx_chan));
926 enet_dma_writel(priv, priv->tx_desc_dma,
927 ENETDMA_RSTART_REG(priv->tx_chan));
929 /* clear remaining state ram for rx & tx channel */
930 enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
931 enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
932 enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
933 enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
934 enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
935 enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
937 /* set max rx/tx length */
938 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
939 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
941 /* set dma maximum burst len */
942 enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
943 ENETDMA_MAXBURST_REG(priv->rx_chan));
944 enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
945 ENETDMA_MAXBURST_REG(priv->tx_chan));
947 /* set correct transmit fifo watermark */
948 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
950 /* set flow control low/high threshold to 1/3 / 2/3 */
951 val = priv->rx_ring_size / 3;
952 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
953 val = (priv->rx_ring_size * 2) / 3;
954 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
956 /* all set, enable mac and interrupts, start dma engine and
957 * kick rx dma channel */
959 val = enet_readl(priv, ENET_CTL_REG);
960 val |= ENET_CTL_ENABLE_MASK;
961 enet_writel(priv, val, ENET_CTL_REG);
962 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
963 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
964 ENETDMA_CHANCFG_REG(priv->rx_chan));
966 /* watch "mib counters about to overflow" interrupt */
967 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
968 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
970 /* watch "packet transferred" interrupt in rx and tx */
971 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
972 ENETDMA_IR_REG(priv->rx_chan));
973 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
974 ENETDMA_IR_REG(priv->tx_chan));
976 /* make sure we enable napi before rx interrupt */
977 napi_enable(&priv->napi);
979 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
980 ENETDMA_IRMASK_REG(priv->rx_chan));
981 enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
982 ENETDMA_IRMASK_REG(priv->tx_chan));
985 phy_start(priv->phydev);
987 bcm_enet_adjust_link(dev);
989 netif_start_queue(dev);
993 for (i = 0; i < priv->rx_ring_size; i++) {
994 struct bcm_enet_desc *desc;
996 if (!priv->rx_skb[i])
999 desc = &priv->rx_desc_cpu[i];
1000 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1002 kfree_skb(priv->rx_skb[i]);
1004 kfree(priv->rx_skb);
1007 kfree(priv->tx_skb);
1010 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1011 priv->tx_desc_cpu, priv->tx_desc_dma);
1014 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1015 priv->rx_desc_cpu, priv->rx_desc_dma);
1018 free_irq(priv->irq_tx, dev);
1021 free_irq(priv->irq_rx, dev);
1024 free_irq(dev->irq, dev);
1027 phy_disconnect(priv->phydev);
1035 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1040 val = enet_readl(priv, ENET_CTL_REG);
1041 val |= ENET_CTL_DISABLE_MASK;
1042 enet_writel(priv, val, ENET_CTL_REG);
1048 val = enet_readl(priv, ENET_CTL_REG);
1049 if (!(val & ENET_CTL_DISABLE_MASK))
1056 * disable dma in given channel
1058 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1062 enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
1068 val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
1069 if (!(val & ENETDMA_CHANCFG_EN_MASK))
1078 static int bcm_enet_stop(struct net_device *dev)
1080 struct bcm_enet_priv *priv;
1081 struct device *kdev;
1084 priv = netdev_priv(dev);
1085 kdev = &priv->pdev->dev;
1087 netif_stop_queue(dev);
1088 napi_disable(&priv->napi);
1090 phy_stop(priv->phydev);
1091 del_timer_sync(&priv->rx_timeout);
1093 /* mask all interrupts */
1094 enet_writel(priv, 0, ENET_IRMASK_REG);
1095 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
1096 enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
1098 /* make sure no mib update is scheduled */
1099 cancel_work_sync(&priv->mib_update_task);
1101 /* disable dma & mac */
1102 bcm_enet_disable_dma(priv, priv->tx_chan);
1103 bcm_enet_disable_dma(priv, priv->rx_chan);
1104 bcm_enet_disable_mac(priv);
1106 /* force reclaim of all tx buffers */
1107 bcm_enet_tx_reclaim(dev, 1);
1109 /* free the rx skb ring */
1110 for (i = 0; i < priv->rx_ring_size; i++) {
1111 struct bcm_enet_desc *desc;
1113 if (!priv->rx_skb[i])
1116 desc = &priv->rx_desc_cpu[i];
1117 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1119 kfree_skb(priv->rx_skb[i]);
1122 /* free remaining allocated memory */
1123 kfree(priv->rx_skb);
1124 kfree(priv->tx_skb);
1125 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1126 priv->rx_desc_cpu, priv->rx_desc_dma);
1127 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1128 priv->tx_desc_cpu, priv->tx_desc_dma);
1129 free_irq(priv->irq_tx, dev);
1130 free_irq(priv->irq_rx, dev);
1131 free_irq(dev->irq, dev);
1134 if (priv->has_phy) {
1135 phy_disconnect(priv->phydev);
1136 priv->phydev = NULL;
1145 struct bcm_enet_stats {
1146 char stat_string[ETH_GSTRING_LEN];
1152 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \
1153 offsetof(struct bcm_enet_priv, m)
1154 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \
1155 offsetof(struct net_device_stats, m)
1157 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1158 { "rx_packets", DEV_STAT(rx_packets), -1 },
1159 { "tx_packets", DEV_STAT(tx_packets), -1 },
1160 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1161 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1162 { "rx_errors", DEV_STAT(rx_errors), -1 },
1163 { "tx_errors", DEV_STAT(tx_errors), -1 },
1164 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1165 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1167 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1168 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1169 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1170 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1171 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1172 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1173 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1174 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1175 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1176 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1177 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1178 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1179 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1180 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1181 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1182 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1183 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1184 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1185 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1186 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1187 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1189 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1190 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1191 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1192 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1193 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1194 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1195 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1196 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1197 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1198 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1199 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1200 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1201 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1202 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1203 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1204 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1205 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1206 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1207 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1208 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1209 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1210 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1214 #define BCM_ENET_STATS_LEN \
1215 (sizeof(bcm_enet_gstrings_stats) / sizeof(struct bcm_enet_stats))
1217 static const u32 unused_mib_regs[] = {
1218 ETH_MIB_TX_ALL_OCTETS,
1219 ETH_MIB_TX_ALL_PKTS,
1220 ETH_MIB_RX_ALL_OCTETS,
1221 ETH_MIB_RX_ALL_PKTS,
1225 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1226 struct ethtool_drvinfo *drvinfo)
1228 strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1229 strlcpy(drvinfo->version, bcm_enet_driver_version,
1230 sizeof(drvinfo->version));
1231 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1232 strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1233 drvinfo->n_stats = BCM_ENET_STATS_LEN;
1236 static int bcm_enet_get_sset_count(struct net_device *netdev,
1239 switch (string_set) {
1241 return BCM_ENET_STATS_LEN;
1247 static void bcm_enet_get_strings(struct net_device *netdev,
1248 u32 stringset, u8 *data)
1252 switch (stringset) {
1254 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1255 memcpy(data + i * ETH_GSTRING_LEN,
1256 bcm_enet_gstrings_stats[i].stat_string,
1263 static void update_mib_counters(struct bcm_enet_priv *priv)
1267 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1268 const struct bcm_enet_stats *s;
1272 s = &bcm_enet_gstrings_stats[i];
1273 if (s->mib_reg == -1)
1276 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1277 p = (char *)priv + s->stat_offset;
1279 if (s->sizeof_stat == sizeof(u64))
1285 /* also empty unused mib counters to make sure mib counter
1286 * overflow interrupt is cleared */
1287 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1288 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1291 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1293 struct bcm_enet_priv *priv;
1295 priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1296 mutex_lock(&priv->mib_update_lock);
1297 update_mib_counters(priv);
1298 mutex_unlock(&priv->mib_update_lock);
1300 /* reenable mib interrupt */
1301 if (netif_running(priv->net_dev))
1302 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1305 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1306 struct ethtool_stats *stats,
1309 struct bcm_enet_priv *priv;
1312 priv = netdev_priv(netdev);
1314 mutex_lock(&priv->mib_update_lock);
1315 update_mib_counters(priv);
1317 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1318 const struct bcm_enet_stats *s;
1321 s = &bcm_enet_gstrings_stats[i];
1322 if (s->mib_reg == -1)
1323 p = (char *)&netdev->stats;
1326 p += s->stat_offset;
1327 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1328 *(u64 *)p : *(u32 *)p;
1330 mutex_unlock(&priv->mib_update_lock);
1333 static int bcm_enet_get_settings(struct net_device *dev,
1334 struct ethtool_cmd *cmd)
1336 struct bcm_enet_priv *priv;
1338 priv = netdev_priv(dev);
1343 if (priv->has_phy) {
1346 return phy_ethtool_gset(priv->phydev, cmd);
1349 ethtool_cmd_speed_set(cmd, ((priv->force_speed_100)
1350 ? SPEED_100 : SPEED_10));
1351 cmd->duplex = (priv->force_duplex_full) ?
1352 DUPLEX_FULL : DUPLEX_HALF;
1353 cmd->supported = ADVERTISED_10baseT_Half |
1354 ADVERTISED_10baseT_Full |
1355 ADVERTISED_100baseT_Half |
1356 ADVERTISED_100baseT_Full;
1357 cmd->advertising = 0;
1358 cmd->port = PORT_MII;
1359 cmd->transceiver = XCVR_EXTERNAL;
1364 static int bcm_enet_set_settings(struct net_device *dev,
1365 struct ethtool_cmd *cmd)
1367 struct bcm_enet_priv *priv;
1369 priv = netdev_priv(dev);
1370 if (priv->has_phy) {
1373 return phy_ethtool_sset(priv->phydev, cmd);
1377 (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) ||
1378 cmd->port != PORT_MII)
1381 priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0;
1382 priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0;
1384 if (netif_running(dev))
1385 bcm_enet_adjust_link(dev);
1390 static void bcm_enet_get_ringparam(struct net_device *dev,
1391 struct ethtool_ringparam *ering)
1393 struct bcm_enet_priv *priv;
1395 priv = netdev_priv(dev);
1397 /* rx/tx ring is actually only limited by memory */
1398 ering->rx_max_pending = 8192;
1399 ering->tx_max_pending = 8192;
1400 ering->rx_pending = priv->rx_ring_size;
1401 ering->tx_pending = priv->tx_ring_size;
1404 static int bcm_enet_set_ringparam(struct net_device *dev,
1405 struct ethtool_ringparam *ering)
1407 struct bcm_enet_priv *priv;
1410 priv = netdev_priv(dev);
1413 if (netif_running(dev)) {
1418 priv->rx_ring_size = ering->rx_pending;
1419 priv->tx_ring_size = ering->tx_pending;
1424 err = bcm_enet_open(dev);
1428 bcm_enet_set_multicast_list(dev);
1433 static void bcm_enet_get_pauseparam(struct net_device *dev,
1434 struct ethtool_pauseparam *ecmd)
1436 struct bcm_enet_priv *priv;
1438 priv = netdev_priv(dev);
1439 ecmd->autoneg = priv->pause_auto;
1440 ecmd->rx_pause = priv->pause_rx;
1441 ecmd->tx_pause = priv->pause_tx;
1444 static int bcm_enet_set_pauseparam(struct net_device *dev,
1445 struct ethtool_pauseparam *ecmd)
1447 struct bcm_enet_priv *priv;
1449 priv = netdev_priv(dev);
1451 if (priv->has_phy) {
1452 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1453 /* asymetric pause mode not supported,
1454 * actually possible but integrated PHY has RO
1459 /* no pause autoneg on direct mii connection */
1464 priv->pause_auto = ecmd->autoneg;
1465 priv->pause_rx = ecmd->rx_pause;
1466 priv->pause_tx = ecmd->tx_pause;
1471 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1472 .get_strings = bcm_enet_get_strings,
1473 .get_sset_count = bcm_enet_get_sset_count,
1474 .get_ethtool_stats = bcm_enet_get_ethtool_stats,
1475 .get_settings = bcm_enet_get_settings,
1476 .set_settings = bcm_enet_set_settings,
1477 .get_drvinfo = bcm_enet_get_drvinfo,
1478 .get_link = ethtool_op_get_link,
1479 .get_ringparam = bcm_enet_get_ringparam,
1480 .set_ringparam = bcm_enet_set_ringparam,
1481 .get_pauseparam = bcm_enet_get_pauseparam,
1482 .set_pauseparam = bcm_enet_set_pauseparam,
1485 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1487 struct bcm_enet_priv *priv;
1489 priv = netdev_priv(dev);
1490 if (priv->has_phy) {
1493 return phy_mii_ioctl(priv->phydev, rq, cmd);
1495 struct mii_if_info mii;
1498 mii.mdio_read = bcm_enet_mdio_read_mii;
1499 mii.mdio_write = bcm_enet_mdio_write_mii;
1501 mii.phy_id_mask = 0x3f;
1502 mii.reg_num_mask = 0x1f;
1503 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1508 * calculate actual hardware mtu
1510 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1516 /* add ethernet header + vlan tag size */
1517 actual_mtu += VLAN_ETH_HLEN;
1519 if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1523 * setup maximum size before we get overflow mark in
1524 * descriptor, note that this will not prevent reception of
1525 * big frames, they will be split into multiple buffers
1528 priv->hw_mtu = actual_mtu;
1531 * align rx buffer size to dma burst len, account FCS since
1534 priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1535 BCMENET_DMA_MAXBURST * 4);
1540 * adjust mtu, can't be called while device is running
1542 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1546 if (netif_running(dev))
1549 ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1557 * preinit hardware to allow mii operation while device is down
1559 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1564 /* make sure mac is disabled */
1565 bcm_enet_disable_mac(priv);
1567 /* soft reset mac */
1568 val = ENET_CTL_SRESET_MASK;
1569 enet_writel(priv, val, ENET_CTL_REG);
1574 val = enet_readl(priv, ENET_CTL_REG);
1575 if (!(val & ENET_CTL_SRESET_MASK))
1580 /* select correct mii interface */
1581 val = enet_readl(priv, ENET_CTL_REG);
1582 if (priv->use_external_mii)
1583 val |= ENET_CTL_EPHYSEL_MASK;
1585 val &= ~ENET_CTL_EPHYSEL_MASK;
1586 enet_writel(priv, val, ENET_CTL_REG);
1588 /* turn on mdc clock */
1589 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1590 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1592 /* set mib counters to self-clear when read */
1593 val = enet_readl(priv, ENET_MIBCTL_REG);
1594 val |= ENET_MIBCTL_RDCLEAR_MASK;
1595 enet_writel(priv, val, ENET_MIBCTL_REG);
1598 static const struct net_device_ops bcm_enet_ops = {
1599 .ndo_open = bcm_enet_open,
1600 .ndo_stop = bcm_enet_stop,
1601 .ndo_start_xmit = bcm_enet_start_xmit,
1602 .ndo_set_mac_address = bcm_enet_set_mac_address,
1603 .ndo_set_rx_mode = bcm_enet_set_multicast_list,
1604 .ndo_do_ioctl = bcm_enet_ioctl,
1605 .ndo_change_mtu = bcm_enet_change_mtu,
1606 #ifdef CONFIG_NET_POLL_CONTROLLER
1607 .ndo_poll_controller = bcm_enet_netpoll,
1612 * allocate netdevice, request register memory and register device.
1614 static int bcm_enet_probe(struct platform_device *pdev)
1616 struct bcm_enet_priv *priv;
1617 struct net_device *dev;
1618 struct bcm63xx_enet_platform_data *pd;
1619 struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1620 struct mii_bus *bus;
1621 const char *clk_name;
1622 unsigned int iomem_size;
1625 /* stop if shared driver failed, assume driver->probe will be
1626 * called in the same order we register devices (correct ?) */
1627 if (!bcm_enet_shared_base)
1630 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1631 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1632 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1633 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1634 if (!res_mem || !res_irq || !res_irq_rx || !res_irq_tx)
1638 dev = alloc_etherdev(sizeof(*priv));
1641 priv = netdev_priv(dev);
1643 ret = compute_hw_mtu(priv, dev->mtu);
1647 iomem_size = resource_size(res_mem);
1648 if (!request_mem_region(res_mem->start, iomem_size, "bcm63xx_enet")) {
1653 priv->base = ioremap(res_mem->start, iomem_size);
1654 if (priv->base == NULL) {
1656 goto out_release_mem;
1658 dev->irq = priv->irq = res_irq->start;
1659 priv->irq_rx = res_irq_rx->start;
1660 priv->irq_tx = res_irq_tx->start;
1661 priv->mac_id = pdev->id;
1663 /* get rx & tx dma channel id for this mac */
1664 if (priv->mac_id == 0) {
1674 priv->mac_clk = clk_get(&pdev->dev, clk_name);
1675 if (IS_ERR(priv->mac_clk)) {
1676 ret = PTR_ERR(priv->mac_clk);
1679 clk_enable(priv->mac_clk);
1681 /* initialize default and fetch platform data */
1682 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1683 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1685 pd = pdev->dev.platform_data;
1687 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1688 priv->has_phy = pd->has_phy;
1689 priv->phy_id = pd->phy_id;
1690 priv->has_phy_interrupt = pd->has_phy_interrupt;
1691 priv->phy_interrupt = pd->phy_interrupt;
1692 priv->use_external_mii = !pd->use_internal_phy;
1693 priv->pause_auto = pd->pause_auto;
1694 priv->pause_rx = pd->pause_rx;
1695 priv->pause_tx = pd->pause_tx;
1696 priv->force_duplex_full = pd->force_duplex_full;
1697 priv->force_speed_100 = pd->force_speed_100;
1700 if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1701 /* using internal PHY, enable clock */
1702 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1703 if (IS_ERR(priv->phy_clk)) {
1704 ret = PTR_ERR(priv->phy_clk);
1705 priv->phy_clk = NULL;
1706 goto out_put_clk_mac;
1708 clk_enable(priv->phy_clk);
1711 /* do minimal hardware init to be able to probe mii bus */
1712 bcm_enet_hw_preinit(priv);
1714 /* MII bus registration */
1715 if (priv->has_phy) {
1717 priv->mii_bus = mdiobus_alloc();
1718 if (!priv->mii_bus) {
1723 bus = priv->mii_bus;
1724 bus->name = "bcm63xx_enet MII bus";
1725 bus->parent = &pdev->dev;
1727 bus->read = bcm_enet_mdio_read_phylib;
1728 bus->write = bcm_enet_mdio_write_phylib;
1729 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
1731 /* only probe bus where we think the PHY is, because
1732 * the mdio read operation return 0 instead of 0xffff
1733 * if a slave is not present on hw */
1734 bus->phy_mask = ~(1 << priv->phy_id);
1736 bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1742 if (priv->has_phy_interrupt)
1743 bus->irq[priv->phy_id] = priv->phy_interrupt;
1745 bus->irq[priv->phy_id] = PHY_POLL;
1747 ret = mdiobus_register(bus);
1749 dev_err(&pdev->dev, "unable to register mdio bus\n");
1754 /* run platform code to initialize PHY device */
1755 if (pd->mii_config &&
1756 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1757 bcm_enet_mdio_write_mii)) {
1758 dev_err(&pdev->dev, "unable to configure mdio bus\n");
1763 spin_lock_init(&priv->rx_lock);
1765 /* init rx timeout (used for oom) */
1766 init_timer(&priv->rx_timeout);
1767 priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1768 priv->rx_timeout.data = (unsigned long)dev;
1770 /* init the mib update lock&work */
1771 mutex_init(&priv->mib_update_lock);
1772 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1774 /* zero mib counters */
1775 for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1776 enet_writel(priv, 0, ENET_MIB_REG(i));
1778 /* register netdevice */
1779 dev->netdev_ops = &bcm_enet_ops;
1780 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1782 SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops);
1783 SET_NETDEV_DEV(dev, &pdev->dev);
1785 ret = register_netdev(dev);
1787 goto out_unregister_mdio;
1789 netif_carrier_off(dev);
1790 platform_set_drvdata(pdev, dev);
1792 priv->net_dev = dev;
1796 out_unregister_mdio:
1797 if (priv->mii_bus) {
1798 mdiobus_unregister(priv->mii_bus);
1799 kfree(priv->mii_bus->irq);
1804 mdiobus_free(priv->mii_bus);
1807 /* turn off mdc clock */
1808 enet_writel(priv, 0, ENET_MIISC_REG);
1809 if (priv->phy_clk) {
1810 clk_disable(priv->phy_clk);
1811 clk_put(priv->phy_clk);
1815 clk_disable(priv->mac_clk);
1816 clk_put(priv->mac_clk);
1819 iounmap(priv->base);
1822 release_mem_region(res_mem->start, iomem_size);
1830 * exit func, stops hardware and unregisters netdevice
1832 static int bcm_enet_remove(struct platform_device *pdev)
1834 struct bcm_enet_priv *priv;
1835 struct net_device *dev;
1836 struct resource *res;
1838 /* stop netdevice */
1839 dev = platform_get_drvdata(pdev);
1840 priv = netdev_priv(dev);
1841 unregister_netdev(dev);
1843 /* turn off mdc clock */
1844 enet_writel(priv, 0, ENET_MIISC_REG);
1846 if (priv->has_phy) {
1847 mdiobus_unregister(priv->mii_bus);
1848 kfree(priv->mii_bus->irq);
1849 mdiobus_free(priv->mii_bus);
1851 struct bcm63xx_enet_platform_data *pd;
1853 pd = pdev->dev.platform_data;
1854 if (pd && pd->mii_config)
1855 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1856 bcm_enet_mdio_write_mii);
1859 /* release device resources */
1860 iounmap(priv->base);
1861 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1862 release_mem_region(res->start, resource_size(res));
1864 /* disable hw block clocks */
1865 if (priv->phy_clk) {
1866 clk_disable(priv->phy_clk);
1867 clk_put(priv->phy_clk);
1869 clk_disable(priv->mac_clk);
1870 clk_put(priv->mac_clk);
1872 platform_set_drvdata(pdev, NULL);
1877 struct platform_driver bcm63xx_enet_driver = {
1878 .probe = bcm_enet_probe,
1879 .remove = bcm_enet_remove,
1881 .name = "bcm63xx_enet",
1882 .owner = THIS_MODULE,
1887 * reserve & remap memory space shared between all macs
1889 static int bcm_enet_shared_probe(struct platform_device *pdev)
1891 struct resource *res;
1892 unsigned int iomem_size;
1894 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1898 iomem_size = resource_size(res);
1899 if (!request_mem_region(res->start, iomem_size, "bcm63xx_enet_dma"))
1902 bcm_enet_shared_base = ioremap(res->start, iomem_size);
1903 if (!bcm_enet_shared_base) {
1904 release_mem_region(res->start, iomem_size);
1910 static int bcm_enet_shared_remove(struct platform_device *pdev)
1912 struct resource *res;
1914 iounmap(bcm_enet_shared_base);
1915 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1916 release_mem_region(res->start, resource_size(res));
1921 * this "shared" driver is needed because both macs share a single
1924 struct platform_driver bcm63xx_enet_shared_driver = {
1925 .probe = bcm_enet_shared_probe,
1926 .remove = bcm_enet_shared_remove,
1928 .name = "bcm63xx_enet_shared",
1929 .owner = THIS_MODULE,
1936 static int __init bcm_enet_init(void)
1940 ret = platform_driver_register(&bcm63xx_enet_shared_driver);
1944 ret = platform_driver_register(&bcm63xx_enet_driver);
1946 platform_driver_unregister(&bcm63xx_enet_shared_driver);
1951 static void __exit bcm_enet_exit(void)
1953 platform_driver_unregister(&bcm63xx_enet_driver);
1954 platform_driver_unregister(&bcm63xx_enet_shared_driver);
1958 module_init(bcm_enet_init);
1959 module_exit(bcm_enet_exit);
1961 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
1962 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
1963 MODULE_LICENSE("GPL");