1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
16 #include <linux/netdevice.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/types.h>
20 /* compilation time flags */
22 /* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24 /* #define BNX2X_STOP_ON_ERROR */
26 #define DRV_MODULE_VERSION "1.72.51-0"
27 #define DRV_MODULE_RELDATE "2012/06/18"
28 #define BNX2X_BC_VER 0x040200
30 #if defined(CONFIG_DCB)
35 #include "bnx2x_hsi.h"
37 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
39 #include "../cnic_if.h"
43 #define BNX2X_MIN_MSIX_VEC_CNT 3
44 #define BNX2X_MSIX_VEC_FP_START 2
46 #define BNX2X_MIN_MSIX_VEC_CNT 2
47 #define BNX2X_MSIX_VEC_FP_START 1
50 #include <linux/mdio.h>
52 #include "bnx2x_reg.h"
53 #include "bnx2x_fw_defs.h"
54 #include "bnx2x_hsi.h"
55 #include "bnx2x_link.h"
57 #include "bnx2x_dcb.h"
58 #include "bnx2x_stats.h"
60 /* error/debug prints */
62 #define DRV_MODULE_NAME "bnx2x"
64 /* for messages that are currently off */
65 #define BNX2X_MSG_OFF 0x0
66 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
67 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
68 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
69 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
70 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
71 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
72 #define BNX2X_MSG_IOV 0x0800000
73 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
74 #define BNX2X_MSG_ETHTOOL 0x4000000
75 #define BNX2X_MSG_DCB 0x8000000
77 /* regular debug print */
78 #define DP(__mask, fmt, ...) \
80 if (unlikely(bp->msg_enable & (__mask))) \
81 pr_notice("[%s:%d(%s)]" fmt, \
83 bp->dev ? (bp->dev->name) : "?", \
87 #define DP_CONT(__mask, fmt, ...) \
89 if (unlikely(bp->msg_enable & (__mask))) \
90 pr_cont(fmt, ##__VA_ARGS__); \
93 /* errors debug print */
94 #define BNX2X_DBG_ERR(fmt, ...) \
96 if (unlikely(netif_msg_probe(bp))) \
97 pr_err("[%s:%d(%s)]" fmt, \
99 bp->dev ? (bp->dev->name) : "?", \
103 /* for errors (never masked) */
104 #define BNX2X_ERR(fmt, ...) \
106 pr_err("[%s:%d(%s)]" fmt, \
107 __func__, __LINE__, \
108 bp->dev ? (bp->dev->name) : "?", \
112 #define BNX2X_ERROR(fmt, ...) \
113 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
116 /* before we have a dev->name use dev_info() */
117 #define BNX2X_DEV_INFO(fmt, ...) \
119 if (unlikely(netif_msg_probe(bp))) \
120 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
123 #ifdef BNX2X_STOP_ON_ERROR
124 void bnx2x_int_disable(struct bnx2x *bp);
125 #define bnx2x_panic() \
128 BNX2X_ERR("driver assert\n"); \
129 bnx2x_int_disable(bp); \
130 bnx2x_panic_dump(bp); \
133 #define bnx2x_panic() \
136 BNX2X_ERR("driver assert\n"); \
137 bnx2x_panic_dump(bp); \
141 #define bnx2x_mc_addr(ha) ((ha)->addr)
142 #define bnx2x_uc_addr(ha) ((ha)->addr)
144 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
145 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
146 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
149 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
151 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
152 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
153 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
155 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
156 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
157 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
159 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
160 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
162 #define REG_RD_DMAE(bp, offset, valp, len32) \
164 bnx2x_read_dmae(bp, offset, len32);\
165 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
168 #define REG_WR_DMAE(bp, offset, valp, len32) \
170 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
171 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
175 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
176 REG_WR_DMAE(bp, offset, valp, len32)
178 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
180 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
181 bnx2x_write_big_buf_wb(bp, addr, len32); \
184 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
185 offsetof(struct shmem_region, field))
186 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
187 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
189 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
190 offsetof(struct shmem2_region, field))
191 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
192 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
193 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
194 offsetof(struct mf_cfg, field))
195 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
196 offsetof(struct mf2_cfg, field))
198 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
199 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
200 MF_CFG_ADDR(bp, field), (val))
201 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
203 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
204 (SHMEM2_RD((bp), size) > \
205 offsetof(struct shmem2_region, field)))
207 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
208 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
212 /* General SP events - stats query, cfc delete, etc */
213 #define HC_SP_INDEX_ETH_DEF_CONS 3
216 #define HC_SP_INDEX_EQ_CONS 7
218 /* FCoE L2 connection completions */
219 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
220 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
222 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
223 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
225 /* Special clients parameters */
229 #define BNX2X_FCOE_L2_RX_INDEX \
230 (&bp->def_status_blk->sp_sb.\
231 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
233 #define BNX2X_FCOE_L2_TX_INDEX \
234 (&bp->def_status_blk->sp_sb.\
235 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
239 * CLIDs below is a CLID for func 0, then the CLID for other
240 * functions will be calculated by the formula:
242 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
246 BNX2X_ISCSI_ETH_CL_ID_IDX,
247 BNX2X_FCOE_ETH_CL_ID_IDX,
248 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
251 #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\
254 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
256 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
258 /** Additional rings budgeting */
260 #define CNIC_PRESENT 1
261 #define FCOE_PRESENT 1
263 #define CNIC_PRESENT 0
264 #define FCOE_PRESENT 0
265 #endif /* BCM_CNIC */
266 #define NON_ETH_CONTEXT_USE (FCOE_PRESENT)
268 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
269 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
274 /* defines for multiple tx priority indices */
275 #define FIRST_TX_ONLY_COS_INDEX 1
276 #define FIRST_TX_COS_INDEX 0
278 /* rules for calculating the cids of tx-only connections */
279 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
280 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
281 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
283 /* fp index inside class of service range */
284 #define FP_COS_TO_TXQ(fp, cos, bp) \
285 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
287 /* Indexes for transmission queues array:
288 * txdata for RSS i CoS j is at location i + (j * num of RSS)
289 * txdata for FCoE (if exist) is at location max cos * num of RSS
290 * txdata for FWD (if exist) is one location after FCoE
291 * txdata for OOO (if exist) is one location after FWD
298 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
300 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
305 * This driver uses new build_skb() API :
306 * RX ring buffer contains pointer to kmalloc() data only,
307 * skb are built only after Hardware filled the frame.
311 DEFINE_DMA_UNMAP_ADDR(mapping);
318 /* Set on the first BD descriptor when there is a split BD */
319 #define BNX2X_TSO_SPLIT_BD (1<<0)
324 DEFINE_DMA_UNMAP_ADDR(mapping);
328 struct doorbell_set_prod data;
332 /* dropless fc FW/HW related params */
333 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
334 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
335 ETH_MAX_AGGREGATION_QUEUES_E1 :\
336 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
337 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
338 #define FW_PREFETCH_CNT 16
339 #define DROPLESS_FC_HEADROOM 100
342 #define BCM_PAGE_SHIFT 12
343 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
344 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
345 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
347 #define PAGES_PER_SGE_SHIFT 0
348 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
349 #define SGE_PAGE_SIZE PAGE_SIZE
350 #define SGE_PAGE_SHIFT PAGE_SHIFT
351 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
353 /* SGE ring related macros */
354 #define NUM_RX_SGE_PAGES 2
355 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
356 #define NEXT_PAGE_SGE_DESC_CNT 2
357 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
358 /* RX_SGE_CNT is promised to be a power of 2 */
359 #define RX_SGE_MASK (RX_SGE_CNT - 1)
360 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
361 #define MAX_RX_SGE (NUM_RX_SGE - 1)
362 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
363 (MAX_RX_SGE_CNT - 1)) ? \
364 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
366 #define RX_SGE(x) ((x) & MAX_RX_SGE)
369 * Number of required SGEs is the sum of two:
370 * 1. Number of possible opened aggregations (next packet for
371 * these aggregations will probably consume SGE immidiatelly)
372 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
373 * after placement on BD for new TPA aggregation)
375 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
377 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
378 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
379 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
381 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
382 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
383 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
385 /* Manipulate a bit vector defined as an array of u64 */
387 /* Number of bits in one sge_mask array element */
388 #define BIT_VEC64_ELEM_SZ 64
389 #define BIT_VEC64_ELEM_SHIFT 6
390 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
393 #define __BIT_VEC64_SET_BIT(el, bit) \
395 el = ((el) | ((u64)0x1 << (bit))); \
398 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
400 el = ((el) & (~((u64)0x1 << (bit)))); \
404 #define BIT_VEC64_SET_BIT(vec64, idx) \
405 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
406 (idx) & BIT_VEC64_ELEM_MASK)
408 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
409 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
410 (idx) & BIT_VEC64_ELEM_MASK)
412 #define BIT_VEC64_TEST_BIT(vec64, idx) \
413 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
414 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
416 /* Creates a bitmask of all ones in less significant bits.
417 idx - index of the most significant bit in the created mask */
418 #define BIT_VEC64_ONES_MASK(idx) \
419 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
420 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
422 /*******************************************************/
426 /* Number of u64 elements in SGE mask array */
427 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
428 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
429 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
431 union host_hc_status_block {
432 /* pointer to fp status block e1x */
433 struct host_hc_status_block_e1x *e1x_sb;
434 /* pointer to fp status block e2 */
435 struct host_hc_status_block_e2 *e2_sb;
438 struct bnx2x_agg_info {
440 * First aggregation buffer is a data buffer, the following - are pages.
441 * We will preallocate the data buffer for each aggregation when
442 * we open the interface and will replace the BD at the consumer
443 * with this one when we receive the TPA_START CQE in order to
444 * keep the Rx BD ring consistent.
446 struct sw_rx_bd first_buf;
448 #define BNX2X_TPA_START 1
449 #define BNX2X_TPA_STOP 2
450 #define BNX2X_TPA_ERROR 3
460 #define Q_STATS_OFFSET32(stat_name) \
461 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
463 struct bnx2x_fp_txdata {
465 struct sw_tx_bd *tx_buf_ring;
467 union eth_tx_bd_types *tx_desc_ring;
468 dma_addr_t tx_desc_mapping;
479 unsigned long tx_pkt;
484 struct bnx2x_fastpath *parent_fp;
488 enum bnx2x_tpa_mode_t {
493 struct bnx2x_fastpath {
494 struct bnx2x *bp; /* parent */
496 #define BNX2X_NAPI_WEIGHT 128
497 struct napi_struct napi;
498 union host_hc_status_block status_blk;
499 /* chip independed shortcuts into sb structure */
500 __le16 *sb_index_values;
501 __le16 *sb_running_index;
502 /* chip independed shortcut into rx_prods_offset memory */
503 u32 ustorm_rx_prods_offset;
507 dma_addr_t status_blk_mapping;
509 enum bnx2x_tpa_mode_t mode;
511 u8 max_cos; /* actual number of active tx coses */
512 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
514 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
515 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
517 struct eth_rx_bd *rx_desc_ring;
518 dma_addr_t rx_desc_mapping;
520 union eth_rx_cqe *rx_comp_ring;
521 dma_addr_t rx_comp_mapping;
524 struct eth_rx_sge *rx_sge_ring;
525 dma_addr_t rx_sge_mapping;
527 u64 sge_mask[RX_SGE_MASK_LEN];
533 u8 index; /* number in fp array */
534 u8 rx_queue; /* index for skb_record */
535 u8 cl_id; /* eth client id */
537 u8 fw_sb_id; /* status block number in FW */
538 u8 igu_sb_id; /* status block number in HW */
545 /* The last maximal completed SGE */
548 unsigned long rx_pkt,
552 struct bnx2x_agg_info *tpa_info;
554 #ifdef BNX2X_STOP_ON_ERROR
557 /* The size is calculated using the following:
558 sizeof name field from netdev structure +
560 4 (for the digits and to make it DWORD aligned) */
561 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
562 char name[FP_NAME_SIZE];
565 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
566 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
567 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
568 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
570 /* Use 2500 as a mini-jumbo MTU for FCoE */
571 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
573 #define FCOE_IDX_OFFSET 0
575 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
577 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
578 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
579 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
580 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
581 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
582 txdata_ptr[FIRST_TX_COS_INDEX] \
586 #define IS_ETH_FP(fp) (fp->index < \
587 BNX2X_NUM_ETH_QUEUES(fp->bp))
589 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX(fp->bp))
590 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
592 #define IS_FCOE_FP(fp) false
593 #define IS_FCOE_IDX(idx) false
598 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
599 #define RX_COPY_THRESH 92
601 #define NUM_TX_RINGS 16
602 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
603 #define NEXT_PAGE_TX_DESC_CNT 1
604 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
605 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
606 #define MAX_TX_BD (NUM_TX_BD - 1)
607 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
608 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
609 (MAX_TX_DESC_CNT - 1)) ? \
610 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
612 #define TX_BD(x) ((x) & MAX_TX_BD)
613 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
615 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
616 #define NUM_RX_RINGS 8
617 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
618 #define NEXT_PAGE_RX_DESC_CNT 2
619 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
620 #define RX_DESC_MASK (RX_DESC_CNT - 1)
621 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
622 #define MAX_RX_BD (NUM_RX_BD - 1)
623 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
625 /* dropless fc calculations for BDs
627 * Number of BDs should as number of buffers in BRB:
628 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
629 * "next" elements on each page
631 #define NUM_BD_REQ BRB_SIZE(bp)
632 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
634 #define BD_TH_LO(bp) (NUM_BD_REQ + \
635 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
637 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
639 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
641 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
642 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
643 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
644 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
645 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
646 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
649 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
650 (MAX_RX_DESC_CNT - 1)) ? \
651 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
653 #define RX_BD(x) ((x) & MAX_RX_BD)
656 * As long as CQE is X times bigger than BD entry we have to allocate X times
657 * more pages for CQ ring in order to keep it balanced with BD ring
659 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
660 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
661 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
662 #define NEXT_PAGE_RCQ_DESC_CNT 1
663 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
664 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
665 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
666 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
667 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
668 (MAX_RCQ_DESC_CNT - 1)) ? \
669 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
671 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
673 /* dropless fc calculations for RCQs
675 * Number of RCQs should be as number of buffers in BRB:
676 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
677 * "next" elements on each page
679 #define NUM_RCQ_REQ BRB_SIZE(bp)
680 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
682 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
683 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
685 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
688 /* This is needed for determining of last_max */
689 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
690 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
693 #define BNX2X_SWCID_SHIFT 17
694 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
696 /* used on a CID received from the HW */
697 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
698 #define CQE_CMD(x) (le32_to_cpu(x) >> \
699 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
701 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
702 le32_to_cpu((bd)->addr_lo))
703 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
705 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
706 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
707 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
708 #error "Min DB doorbell stride is 8"
710 #define DPM_TRIGER_TYPE 0x40
711 #define DOORBELL(bp, cid, val) \
713 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
718 /* TX CSUM helpers */
719 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
721 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
724 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
727 #define XMIT_CSUM_V4 0x1
728 #define XMIT_CSUM_V6 0x2
729 #define XMIT_CSUM_TCP 0x4
730 #define XMIT_GSO_V4 0x8
731 #define XMIT_GSO_V6 0x10
733 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
734 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
737 /* stuff added to make the code fit 80Col */
738 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
739 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
740 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
741 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
742 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
744 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
746 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
747 (((le16_to_cpu(flags) & \
748 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
749 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
750 == PRS_FLAG_OVERETH_IPV4)
751 #define BNX2X_RX_SUM_FIX(cqe) \
752 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
755 #define FP_USB_FUNC_OFF \
756 offsetof(struct cstorm_status_block_u, func)
757 #define FP_CSB_FUNC_OFF \
758 offsetof(struct cstorm_status_block_c, func)
760 #define HC_INDEX_ETH_RX_CQ_CONS 1
762 #define HC_INDEX_OOO_TX_CQ_CONS 4
764 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
766 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
768 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
770 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
772 #define BNX2X_RX_SB_INDEX \
773 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
775 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
777 #define BNX2X_TX_SB_INDEX_COS0 \
778 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
780 /* end of fast path */
784 struct bnx2x_common {
787 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
788 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
790 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
791 #define CHIP_NUM_57710 0x164e
792 #define CHIP_NUM_57711 0x164f
793 #define CHIP_NUM_57711E 0x1650
794 #define CHIP_NUM_57712 0x1662
795 #define CHIP_NUM_57712_MF 0x1663
796 #define CHIP_NUM_57713 0x1651
797 #define CHIP_NUM_57713E 0x1652
798 #define CHIP_NUM_57800 0x168a
799 #define CHIP_NUM_57800_MF 0x16a5
800 #define CHIP_NUM_57810 0x168e
801 #define CHIP_NUM_57810_MF 0x16ae
802 #define CHIP_NUM_57811 0x163d
803 #define CHIP_NUM_57811_MF 0x163e
804 #define CHIP_NUM_57840 0x168d
805 #define CHIP_NUM_57840_MF 0x16ab
806 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
807 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
808 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
809 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
810 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
811 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
812 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
813 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
814 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
815 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
816 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
817 #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840)
818 #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF)
819 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
821 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
822 CHIP_IS_57712_MF(bp))
823 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
824 CHIP_IS_57800_MF(bp) || \
825 CHIP_IS_57810(bp) || \
826 CHIP_IS_57810_MF(bp) || \
827 CHIP_IS_57811(bp) || \
828 CHIP_IS_57811_MF(bp) || \
829 CHIP_IS_57840(bp) || \
830 CHIP_IS_57840_MF(bp))
831 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
832 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
833 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
835 #define CHIP_REV_SHIFT 12
836 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
837 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
838 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
839 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
840 /* assume maximum 5 revisions */
841 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
842 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
843 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
844 !(CHIP_REV_VAL(bp) & 0x00001000))
845 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
846 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
847 (CHIP_REV_VAL(bp) & 0x00001000))
849 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
850 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
852 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
853 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
854 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
855 (CHIP_REV_SHIFT + 1)) \
857 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
860 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
861 (CHIP_REV(bp) == CHIP_REV_Bx))
862 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
863 (CHIP_REV(bp) == CHIP_REV_Ax))
866 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
867 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
868 #define BNX2X_NVRAM_PAGE_SIZE 256
880 #define INT_BLOCK_HC 0
881 #define INT_BLOCK_IGU 1
882 #define INT_BLOCK_MODE_NORMAL 0
883 #define INT_BLOCK_MODE_BW_COMP 2
884 #define CHIP_INT_MODE_IS_NBC(bp) \
885 (!CHIP_IS_E1x(bp) && \
886 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
887 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
890 #define CHIP_4_PORT_MODE 0x0
891 #define CHIP_2_PORT_MODE 0x1
892 #define CHIP_PORT_MODE_NONE 0x2
893 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
894 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
899 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
900 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
901 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
910 u32 link_config[LINK_CONFIG_SIZE];
912 u32 supported[LINK_CONFIG_SIZE];
913 /* link settings - missing defines */
914 #define SUPPORTED_2500baseX_Full (1 << 15)
916 u32 advertising[LINK_CONFIG_SIZE];
917 /* link settings - missing defines */
918 #define ADVERTISED_2500baseX_Full (1 << 15)
922 /* used to synchronize phy accesses */
923 struct mutex phy_mutex;
928 struct nig_stats old_nig_stats;
933 #define STATS_OFFSET32(stat_name) \
934 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
938 /* slow path work-queue */
939 extern struct workqueue_struct *bnx2x_wq;
941 #define BNX2X_MAX_NUM_OF_VFS 64
942 #define BNX2X_VF_ID_INVALID 0xFF
945 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
946 * control by the number of fast-path status blocks supported by the
947 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
948 * status block represents an independent interrupts context that can
949 * serve a regular L2 networking queue. However special L2 queues such
950 * as the FCoE queue do not require a FP-SB and other components like
951 * the CNIC may consume FP-SB reducing the number of possible L2 queues
953 * If the maximum number of FP-SB available is X then:
954 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
955 * regular L2 queues is Y=X-1
956 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
957 * c. If the FCoE L2 queue is supported the actual number of L2 queues
959 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
960 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
961 * FP interrupt context for the CNIC).
962 * e. The number of HW context (CID count) is always X or X+1 if FCoE
963 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
966 /* fast-path interrupt contexts E1x */
967 #define FP_SB_MAX_E1x 16
968 /* fast-path interrupt contexts E2 */
969 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
972 struct eth_context eth;
976 /* CDU host DB constants */
977 #define CDU_ILT_PAGE_SZ_HW 2
978 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
979 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
982 #define CNIC_ISCSI_CID_MAX 256
983 #define CNIC_FCOE_CID_MAX 2048
984 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
985 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
988 #define QM_ILT_PAGE_SZ_HW 0
989 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
990 #define QM_CID_ROUND 1024
993 /* TM (timers) host DB constants */
994 #define TM_ILT_PAGE_SZ_HW 0
995 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
996 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
997 #define TM_CONN_NUM 1024
998 #define TM_ILT_SZ (8 * TM_CONN_NUM)
999 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1001 /* SRC (Searcher) host DB constants */
1002 #define SRC_ILT_PAGE_SZ_HW 0
1003 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1004 #define SRC_HASH_BITS 10
1005 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1006 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1007 #define SRC_T2_SZ SRC_ILT_SZ
1008 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1012 #define MAX_DMAE_C 8
1014 /* DMA memory not used in fastpath */
1015 struct bnx2x_slowpath {
1017 struct mac_configuration_cmd e1x;
1018 struct eth_classify_rules_ramrod_data e2;
1023 struct tstorm_eth_mac_filter_config e1x;
1024 struct eth_filter_rules_ramrod_data e2;
1028 struct mac_configuration_cmd e1;
1029 struct eth_multicast_rules_ramrod_data e2;
1032 struct eth_rss_update_ramrod_data rss_rdata;
1034 /* Queue State related ramrods are always sent under rtnl_lock */
1036 struct client_init_ramrod_data init_data;
1037 struct client_update_ramrod_data update_data;
1041 struct function_start_data func_start;
1042 /* pfc configuration for DCBX ramrod */
1043 struct flow_control_configuration pfc_config;
1046 /* afex ramrod can not be a part of func_rdata union because these
1047 * events might arrive in parallel to other events from func_rdata.
1048 * Therefore, if they would have been defined in the same union,
1049 * data can get corrupted.
1051 struct afex_vif_list_ramrod_data func_afex_rdata;
1053 /* used by dmae command executer */
1054 struct dmae_command dmae[MAX_DMAE_C];
1057 union mac_stats mac_stats;
1058 struct nig_stats nig_stats;
1059 struct host_port_stats port_stats;
1060 struct host_func_stats func_stats;
1065 union drv_info_to_mcp drv_info_to_mcp;
1068 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1069 #define bnx2x_sp_mapping(bp, var) \
1070 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1073 /* attn group wiring */
1074 #define MAX_DYNAMIC_ATTN_GRPS 8
1089 union cdu_context *vcxt;
1090 dma_addr_t cxt_mapping;
1098 enum bnx2x_recovery_state {
1099 BNX2X_RECOVERY_DONE,
1100 BNX2X_RECOVERY_INIT,
1101 BNX2X_RECOVERY_WAIT,
1102 BNX2X_RECOVERY_FAILED,
1103 BNX2X_RECOVERY_NIC_LOADING
1107 * Event queue (EQ or event ring) MC hsi
1108 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1110 #define NUM_EQ_PAGES 1
1111 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1112 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1113 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1114 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1115 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1117 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1118 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1119 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1121 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1122 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1124 #define BNX2X_EQ_INDEX \
1125 (&bp->def_status_blk->sp_sb.\
1126 index_values[HC_SP_INDEX_EQ_CONS])
1128 /* This is a data that will be used to create a link report message.
1129 * We will keep the data used for the last link report in order
1130 * to prevent reporting the same link parameters twice.
1132 struct bnx2x_link_report_data {
1133 u16 line_speed; /* Effective line speed */
1134 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1138 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1139 BNX2X_LINK_REPORT_LINK_DOWN,
1140 BNX2X_LINK_REPORT_RX_FC_ON,
1141 BNX2X_LINK_REPORT_TX_FC_ON,
1145 BNX2X_PORT_QUERY_IDX,
1147 BNX2X_FCOE_QUERY_IDX,
1148 BNX2X_FIRST_QUEUE_QUERY_IDX,
1151 struct bnx2x_fw_stats_req {
1152 struct stats_query_header hdr;
1153 struct stats_query_entry query[FP_SB_MAX_E1x+
1154 BNX2X_FIRST_QUEUE_QUERY_IDX];
1157 struct bnx2x_fw_stats_data {
1158 struct stats_counter storm_counters;
1159 struct per_port_stats port;
1160 struct per_pf_stats pf;
1161 struct fcoe_statistics_params fcoe;
1162 struct per_queue_stats queue_stats[1];
1165 /* Public slow path states */
1167 BNX2X_SP_RTNL_SETUP_TC,
1168 BNX2X_SP_RTNL_TX_TIMEOUT,
1169 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1170 BNX2X_SP_RTNL_FAN_FAILURE,
1174 struct bnx2x_prev_path_list {
1178 struct list_head list;
1181 struct bnx2x_sp_objs {
1183 struct bnx2x_vlan_mac_obj mac_obj;
1185 /* Queue State object */
1186 struct bnx2x_queue_sp_obj q_obj;
1189 struct bnx2x_fp_stats {
1190 struct tstorm_per_queue_stats old_tclient;
1191 struct ustorm_per_queue_stats old_uclient;
1192 struct xstorm_per_queue_stats old_xclient;
1193 struct bnx2x_eth_q_stats eth_q_stats;
1194 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1198 /* Fields used in the tx and intr/napi performance paths
1199 * are grouped together in the beginning of the structure
1201 struct bnx2x_fastpath *fp;
1202 struct bnx2x_sp_objs *sp_objs;
1203 struct bnx2x_fp_stats *fp_stats;
1204 struct bnx2x_fp_txdata *bnx2x_txq;
1206 void __iomem *regview;
1207 void __iomem *doorbells;
1210 u8 pf_num; /* absolute PF number */
1211 u8 pfid; /* per-path PF number */
1212 int base_fw_ndsb; /**/
1213 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1214 #define BP_PORT(bp) (bp->pfid & 1)
1215 #define BP_FUNC(bp) (bp->pfid)
1216 #define BP_ABS_FUNC(bp) (bp->pf_num)
1217 #define BP_VN(bp) ((bp)->pfid >> 1)
1218 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1219 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1220 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1221 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1222 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1224 struct net_device *dev;
1225 struct pci_dev *pdev;
1227 const struct iro *iro_arr;
1228 #define IRO (bp->iro_arr)
1230 enum bnx2x_recovery_state recovery_state;
1232 struct msix_entry *msix_table;
1236 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1237 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1238 #define ETH_MIN_PACKET_SIZE 60
1239 #define ETH_MAX_PACKET_SIZE 1500
1240 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1241 /* TCP with Timestamp Option (32) + IPv6 (40) */
1242 #define ETH_MAX_TPA_HEADER_SIZE 72
1244 /* Max supported alignment is 256 (8 shift) */
1245 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1247 /* FW uses 2 Cache lines Alignment for start packet and size
1249 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1250 * at the end of skb->data, to avoid wasting a full cache line.
1251 * This reduces memory use (skb->truesize).
1253 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1255 #define BNX2X_FW_RX_ALIGN_END \
1256 max(1UL << BNX2X_RX_ALIGN_SHIFT, \
1257 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1259 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1261 struct host_sp_status_block *def_status_blk;
1262 #define DEF_SB_IGU_ID 16
1263 #define DEF_SB_ID HC_SP_SB_ID
1267 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1269 /* slow path ring */
1270 struct eth_spe *spq;
1271 dma_addr_t spq_mapping;
1273 struct eth_spe *spq_prod_bd;
1274 struct eth_spe *spq_last_bd;
1275 __le16 *dsb_sp_prod;
1276 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1277 /* used to synchronize spq accesses */
1278 spinlock_t spq_lock;
1281 union event_ring_elem *eq_ring;
1282 dma_addr_t eq_mapping;
1286 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1290 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1292 /* Counter for completed statistics ramrods */
1295 /* End of fields used in the performance code paths */
1301 #define PCIX_FLAG (1 << 0)
1302 #define PCI_32BIT_FLAG (1 << 1)
1303 #define ONE_PORT_FLAG (1 << 2)
1304 #define NO_WOL_FLAG (1 << 3)
1305 #define USING_DAC_FLAG (1 << 4)
1306 #define USING_MSIX_FLAG (1 << 5)
1307 #define USING_MSI_FLAG (1 << 6)
1308 #define DISABLE_MSI_FLAG (1 << 7)
1309 #define TPA_ENABLE_FLAG (1 << 8)
1310 #define NO_MCP_FLAG (1 << 9)
1312 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1313 #define GRO_ENABLE_FLAG (1 << 10)
1314 #define MF_FUNC_DIS (1 << 11)
1315 #define OWN_CNIC_IRQ (1 << 12)
1316 #define NO_ISCSI_OOO_FLAG (1 << 13)
1317 #define NO_ISCSI_FLAG (1 << 14)
1318 #define NO_FCOE_FLAG (1 << 15)
1319 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1320 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1321 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1323 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1324 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1325 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1330 struct delayed_work sp_task;
1331 struct delayed_work sp_rtnl_task;
1333 struct delayed_work period_task;
1334 struct timer_list timer;
1335 int current_interval;
1338 u16 fw_drv_pulse_wr_seq;
1341 struct link_params link_params;
1342 struct link_vars link_vars;
1344 struct bnx2x_link_report_data last_reported_link;
1346 struct mdio_if_info mdio;
1348 struct bnx2x_common common;
1349 struct bnx2x_port port;
1351 struct cmng_init cmng;
1353 u32 mf_config[E1HVN_MAX];
1355 u32 path_has_ovlan; /* E3 */
1358 #define IS_MF(bp) (bp->mf_mode != 0)
1359 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1360 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1361 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1367 u16 tx_quick_cons_trip_int;
1368 u16 tx_quick_cons_trip;
1372 u16 rx_quick_cons_trip_int;
1373 u16 rx_quick_cons_trip;
1376 /* Maximal coalescing timeout in us */
1377 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1382 #define BNX2X_STATE_CLOSED 0
1383 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1384 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1385 #define BNX2X_STATE_OPEN 0x3000
1386 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1387 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1389 #define BNX2X_STATE_DIAG 0xe000
1390 #define BNX2X_STATE_ERROR 0xf000
1392 #define BNX2X_MAX_PRIORITY 8
1393 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1394 #define BNX2X_MAX_COS 3
1395 #define BNX2X_MAX_TX_COS 2
1397 int num_napi_queues;
1401 #define BNX2X_RX_MODE_NONE 0
1402 #define BNX2X_RX_MODE_NORMAL 1
1403 #define BNX2X_RX_MODE_ALLMULTI 2
1404 #define BNX2X_RX_MODE_PROMISC 3
1405 #define BNX2X_MAX_MULTICAST 64
1411 dma_addr_t def_status_blk_mapping;
1413 struct bnx2x_slowpath *slowpath;
1414 dma_addr_t slowpath_mapping;
1416 /* Total number of FW statistics requests */
1420 * This is a memory buffer that will contain both statistics
1421 * ramrod request and data.
1424 dma_addr_t fw_stats_mapping;
1427 * FW statistics request shortcut (points at the
1428 * beginning of fw_stats buffer).
1430 struct bnx2x_fw_stats_req *fw_stats_req;
1431 dma_addr_t fw_stats_req_mapping;
1432 int fw_stats_req_sz;
1435 * FW statistics data shortcut (points at the begining of
1436 * fw_stats buffer + fw_stats_req_sz).
1438 struct bnx2x_fw_stats_data *fw_stats_data;
1439 dma_addr_t fw_stats_data_mapping;
1440 int fw_stats_data_sz;
1442 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1443 * context size we need 8 ILT entries.
1445 #define ILT_MAX_L2_LINES 8
1446 struct hw_context context[ILT_MAX_L2_LINES];
1448 struct bnx2x_ilt *ilt;
1449 #define BP_ILT(bp) ((bp)->ilt)
1450 #define ILT_MAX_LINES 256
1452 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1455 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT)
1458 * Maximum CID count that might be required by the bnx2x:
1459 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1461 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1462 + NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1463 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1464 + NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1465 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1474 #define BNX2X_CNIC_FLAG_MAC_SET 1
1476 dma_addr_t t2_mapping;
1477 struct cnic_ops __rcu *cnic_ops;
1480 struct cnic_eth_dev cnic_eth_dev;
1481 union host_hc_status_block cnic_sb;
1482 dma_addr_t cnic_sb_mapping;
1483 struct eth_spe *cnic_kwq;
1484 struct eth_spe *cnic_kwq_prod;
1485 struct eth_spe *cnic_kwq_cons;
1486 struct eth_spe *cnic_kwq_last;
1487 u16 cnic_kwq_pending;
1488 u16 cnic_spq_pending;
1489 u8 fip_mac[ETH_ALEN];
1490 struct mutex cnic_mutex;
1491 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1493 /* Start index of the "special" (CNIC related) L2 cleints */
1498 /* used to synchronize dmae accesses */
1499 spinlock_t dmae_lock;
1501 /* used to protect the FW mail box */
1502 struct mutex fw_mb_mutex;
1504 /* used to synchronize stats collecting */
1507 /* used for synchronization of concurrent threads statistics handling */
1508 spinlock_t stats_lock;
1510 /* used by dmae command loader */
1511 struct dmae_command stats_dmae;
1515 struct bnx2x_eth_stats eth_stats;
1516 struct host_func_stats func_stats;
1517 struct bnx2x_eth_stats_old eth_stats_old;
1518 struct bnx2x_net_stats_old net_stats_old;
1519 struct bnx2x_fw_port_stats_old fw_stats_old;
1522 struct z_stream_s *strm;
1524 dma_addr_t gunzip_mapping;
1526 #define FW_BUF_SIZE 0x8000
1527 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1528 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1529 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1531 struct raw_op *init_ops;
1532 /* Init blocks offsets inside init_ops */
1533 u16 *init_ops_offsets;
1534 /* Data blob - has 32 bit granularity */
1536 u32 init_mode_flags;
1537 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1538 /* Zipped PRAM blobs - raw data */
1539 const u8 *tsem_int_table_data;
1540 const u8 *tsem_pram_data;
1541 const u8 *usem_int_table_data;
1542 const u8 *usem_pram_data;
1543 const u8 *xsem_int_table_data;
1544 const u8 *xsem_pram_data;
1545 const u8 *csem_int_table_data;
1546 const u8 *csem_pram_data;
1547 #define INIT_OPS(bp) (bp->init_ops)
1548 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1549 #define INIT_DATA(bp) (bp->init_data)
1550 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1551 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1552 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1553 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1554 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1555 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1556 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1557 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1559 #define PHY_FW_VER_LEN 20
1561 const struct firmware *firmware;
1563 /* DCB support on/off */
1565 #define BNX2X_DCB_STATE_OFF 0
1566 #define BNX2X_DCB_STATE_ON 1
1568 /* DCBX engine mode */
1570 #define BNX2X_DCBX_ENABLED_OFF 0
1571 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1572 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1573 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1575 bool dcbx_mode_uset;
1577 struct bnx2x_config_dcbx_params dcbx_config_params;
1578 struct bnx2x_dcbx_port_params dcbx_port_params;
1581 /* CAM credit pools */
1582 struct bnx2x_credit_pool_obj macs_pool;
1584 /* RX_MODE object */
1585 struct bnx2x_rx_mode_obj rx_mode_obj;
1588 struct bnx2x_mcast_obj mcast_obj;
1590 /* RSS configuration object */
1591 struct bnx2x_rss_config_obj rss_conf_obj;
1593 /* Function State controlling object */
1594 struct bnx2x_func_sp_obj func_obj;
1596 unsigned long sp_state;
1598 /* operation indication for the sp_rtnl task */
1599 unsigned long sp_rtnl_state;
1601 /* DCBX Negotation results */
1602 struct dcbx_features dcbx_local_feat;
1606 struct dcbx_features dcbx_remote_feat;
1607 u32 dcbx_remote_flags;
1609 /* AFEX: store default vlan used */
1610 int afex_def_vlan_tag;
1611 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1614 /* multiple tx classes of service */
1617 /* priority to cos mapping */
1621 /* Tx queues may be less or equal to Rx queues */
1622 extern int num_queues;
1623 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1624 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE)
1625 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1626 NON_ETH_CONTEXT_USE)
1627 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1629 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1631 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1632 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1634 #define RSS_IPV4_CAP_MASK \
1635 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1637 #define RSS_IPV4_TCP_CAP_MASK \
1638 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1640 #define RSS_IPV6_CAP_MASK \
1641 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1643 #define RSS_IPV6_TCP_CAP_MASK \
1644 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1646 /* func init flags */
1647 #define FUNC_FLG_RSS 0x0001
1648 #define FUNC_FLG_STATS 0x0002
1649 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1650 #define FUNC_FLG_TPA 0x0008
1651 #define FUNC_FLG_SPQ 0x0010
1652 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1655 struct bnx2x_func_init_params {
1657 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1658 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1661 u16 func_id; /* abs fid */
1663 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1666 #define for_each_eth_queue(bp, var) \
1667 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1669 #define for_each_nondefault_eth_queue(bp, var) \
1670 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1672 #define for_each_queue(bp, var) \
1673 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1674 if (skip_queue(bp, var)) \
1678 /* Skip forwarding FP */
1679 #define for_each_rx_queue(bp, var) \
1680 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1681 if (skip_rx_queue(bp, var)) \
1685 #define for_each_napi_rx_queue(bp, var) \
1686 for ((var) = 0; (var) < bp->num_napi_queues; (var)++)
1689 #define for_each_tx_queue(bp, var) \
1690 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1691 if (skip_tx_queue(bp, var)) \
1695 #define for_each_nondefault_queue(bp, var) \
1696 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1697 if (skip_queue(bp, var)) \
1701 #define for_each_cos_in_tx_queue(fp, var) \
1702 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1705 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1707 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1710 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1712 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1714 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1720 * bnx2x_set_mac_one - configure a single MAC address
1722 * @bp: driver handle
1723 * @mac: MAC to configure
1724 * @obj: MAC object handle
1725 * @set: if 'true' add a new MAC, otherwise - delete
1726 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1727 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1729 * Configures one MAC according to provided parameters or continues the
1730 * execution of previously scheduled commands if RAMROD_CONT is set in
1733 * Returns zero if operation has successfully completed, a positive value if the
1734 * operation has been successfully scheduled and a negative - if a requested
1735 * operations has failed.
1737 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1738 struct bnx2x_vlan_mac_obj *obj, bool set,
1739 int mac_type, unsigned long *ramrod_flags);
1741 * Deletes all MACs configured for the specific MAC object.
1743 * @param bp Function driver instance
1744 * @param mac_obj MAC object to cleanup
1746 * @return zero if all MACs were cleaned
1750 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1752 * @bp: driver handle
1753 * @mac_obj: MAC object handle
1754 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1755 * @wait_for_comp: if 'true' block until completion
1757 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1759 * Returns zero if operation has successfully completed, a positive value if the
1760 * operation has been successfully scheduled and a negative - if a requested
1761 * operations has failed.
1763 int bnx2x_del_all_macs(struct bnx2x *bp,
1764 struct bnx2x_vlan_mac_obj *mac_obj,
1765 int mac_type, bool wait_for_comp);
1767 /* Init Function API */
1768 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1769 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1770 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1771 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1772 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1773 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1777 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1778 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1780 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1781 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1782 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1783 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1784 bool with_comp, u8 comp_type);
1787 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1788 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1789 u32 data_hi, u32 data_lo, int cmd_type);
1790 void bnx2x_update_coalesce(struct bnx2x *bp);
1791 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1793 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1799 val = REG_RD(bp, reg);
1800 if (val == expected)
1810 #define BNX2X_ILT_ZALLOC(x, y, size) \
1812 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1814 memset(x, 0, size); \
1817 #define BNX2X_ILT_FREE(x, y, size) \
1820 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1826 #define ILOG2(x) (ilog2((x)))
1828 #define ILT_NUM_PAGE_ENTRIES (3072)
1829 /* In 57710/11 we use whole table since we have 8 func
1830 * In 57712 we have only 4 func, but use same size per func, then only half of
1833 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1835 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1837 * the phys address is shifted right 12 bits and has an added
1838 * 1=valid bit added to the 53rd bit
1839 * then since this is a wide register(TM)
1840 * we split it into two 32 bit writes
1842 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1843 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1845 /* load/unload mode */
1846 #define LOAD_NORMAL 0
1849 #define LOAD_LOOPBACK_EXT 3
1850 #define UNLOAD_NORMAL 0
1851 #define UNLOAD_CLOSE 1
1852 #define UNLOAD_RECOVERY 2
1855 /* DMAE command defines */
1856 #define DMAE_TIMEOUT -1
1857 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1858 #define DMAE_NOT_RDY -3
1859 #define DMAE_PCI_ERR_FLAG 0x80000000
1861 #define DMAE_SRC_PCI 0
1862 #define DMAE_SRC_GRC 1
1864 #define DMAE_DST_NONE 0
1865 #define DMAE_DST_PCI 1
1866 #define DMAE_DST_GRC 2
1868 #define DMAE_COMP_PCI 0
1869 #define DMAE_COMP_GRC 1
1871 /* E2 and onward - PCI error handling in the completion */
1873 #define DMAE_COMP_REGULAR 0
1874 #define DMAE_COM_SET_ERR 1
1876 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1877 DMAE_COMMAND_SRC_SHIFT)
1878 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1879 DMAE_COMMAND_SRC_SHIFT)
1881 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1882 DMAE_COMMAND_DST_SHIFT)
1883 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1884 DMAE_COMMAND_DST_SHIFT)
1886 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1887 DMAE_COMMAND_C_DST_SHIFT)
1888 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1889 DMAE_COMMAND_C_DST_SHIFT)
1891 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1893 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1894 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1895 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1896 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1898 #define DMAE_CMD_PORT_0 0
1899 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1901 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1902 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1903 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1905 #define DMAE_SRC_PF 0
1906 #define DMAE_SRC_VF 1
1908 #define DMAE_DST_PF 0
1909 #define DMAE_DST_VF 1
1911 #define DMAE_C_SRC 0
1912 #define DMAE_C_DST 1
1914 #define DMAE_LEN32_RD_MAX 0x80
1915 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1917 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1920 #define MAX_DMAE_C_PER_PORT 8
1921 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1923 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1926 /* PCIE link and speed */
1927 #define PCICFG_LINK_WIDTH 0x1f00000
1928 #define PCICFG_LINK_WIDTH_SHIFT 20
1929 #define PCICFG_LINK_SPEED 0xf0000
1930 #define PCICFG_LINK_SPEED_SHIFT 16
1932 #define BNX2X_NUM_TESTS_SF 7
1933 #define BNX2X_NUM_TESTS_MF 3
1934 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
1937 #define BNX2X_PHY_LOOPBACK 0
1938 #define BNX2X_MAC_LOOPBACK 1
1939 #define BNX2X_EXT_LOOPBACK 2
1940 #define BNX2X_PHY_LOOPBACK_FAILED 1
1941 #define BNX2X_MAC_LOOPBACK_FAILED 2
1942 #define BNX2X_EXT_LOOPBACK_FAILED 3
1943 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1944 BNX2X_PHY_LOOPBACK_FAILED)
1947 #define STROM_ASSERT_ARRAY_SIZE 50
1950 /* must be used on a CID before placing it on a HW ring */
1951 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1952 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
1955 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1956 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1960 #define MAX_SPQ_PENDING 8
1962 /* CMNG constants, as derived from system spec calculations */
1963 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
1964 #define DEF_MIN_RATE 100
1965 /* resolution of the rate shaping timer - 400 usec */
1966 #define RS_PERIODIC_TIMEOUT_USEC 400
1967 /* number of bytes in single QM arbitration cycle -
1968 * coefficient for calculating the fairness timer */
1969 #define QM_ARB_BYTES 160000
1970 /* resolution of Min algorithm 1:100 */
1972 /* how many bytes above threshold for the minimal credit of Min algorithm*/
1973 #define MIN_ABOVE_THRESH 32768
1974 /* Fairness algorithm integration time coefficient -
1975 * for calculating the actual Tfair */
1976 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
1977 /* Memory of fairness algorithm . 2 cycles */
1981 #define ATTN_NIG_FOR_FUNC (1L << 8)
1982 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1983 #define GPIO_2_FUNC (1L << 10)
1984 #define GPIO_3_FUNC (1L << 11)
1985 #define GPIO_4_FUNC (1L << 12)
1986 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1987 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1988 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1989 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1990 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1991 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1993 #define ATTN_HARD_WIRED_MASK 0xff00
1994 #define ATTENTION_ID 4
1997 /* stuff added to make the code fit 80Col */
1999 #define BNX2X_PMF_LINK_ASSERT \
2000 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2002 #define BNX2X_MC_ASSERT_BITS \
2003 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2004 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2005 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2006 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2008 #define BNX2X_MCP_ASSERT \
2009 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2011 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2012 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2013 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2014 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2015 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2016 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2017 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2019 #define HW_INTERRUT_ASSERT_SET_0 \
2020 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2021 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2022 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2023 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2024 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2025 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2026 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2027 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2028 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2029 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2030 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2031 #define HW_INTERRUT_ASSERT_SET_1 \
2032 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2033 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2034 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2035 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2036 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2037 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2038 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2039 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2040 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2041 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2042 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2043 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2044 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2045 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2046 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2047 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2048 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2049 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2050 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2051 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2052 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2053 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2054 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2055 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2056 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2057 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2058 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2059 #define HW_INTERRUT_ASSERT_SET_2 \
2060 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2061 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2062 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2063 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2064 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2065 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2066 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2067 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2068 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2069 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2070 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2071 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2072 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2074 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2075 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2076 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2077 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2079 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2080 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2082 #define MULTI_MASK 0x7f
2085 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2086 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2087 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2088 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2090 #define DEF_USB_IGU_INDEX_OFF \
2091 offsetof(struct cstorm_def_status_block_u, igu_index)
2092 #define DEF_CSB_IGU_INDEX_OFF \
2093 offsetof(struct cstorm_def_status_block_c, igu_index)
2094 #define DEF_XSB_IGU_INDEX_OFF \
2095 offsetof(struct xstorm_def_status_block, igu_index)
2096 #define DEF_TSB_IGU_INDEX_OFF \
2097 offsetof(struct tstorm_def_status_block, igu_index)
2099 #define DEF_USB_SEGMENT_OFF \
2100 offsetof(struct cstorm_def_status_block_u, segment)
2101 #define DEF_CSB_SEGMENT_OFF \
2102 offsetof(struct cstorm_def_status_block_c, segment)
2103 #define DEF_XSB_SEGMENT_OFF \
2104 offsetof(struct xstorm_def_status_block, segment)
2105 #define DEF_TSB_SEGMENT_OFF \
2106 offsetof(struct tstorm_def_status_block, segment)
2108 #define BNX2X_SP_DSB_INDEX \
2109 (&bp->def_status_blk->sp_sb.\
2110 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2112 #define SET_FLAG(value, mask, flag) \
2114 (value) &= ~(mask);\
2115 (value) |= ((flag) << (mask##_SHIFT));\
2118 #define GET_FLAG(value, mask) \
2119 (((value) & (mask)) >> (mask##_SHIFT))
2121 #define GET_FIELD(value, fname) \
2122 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2124 #define CAM_IS_INVALID(x) \
2125 (GET_FLAG(x.flags, \
2126 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2127 (T_ETH_MAC_COMMAND_INVALIDATE))
2129 /* Number of u32 elements in MC hash array */
2130 #define MC_HASH_SIZE 8
2131 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2132 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2135 #ifndef PXP2_REG_PXP2_INT_STS
2136 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2139 #ifndef ETH_MAX_RX_CLIENTS_E2
2140 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2143 #define BNX2X_VPD_LEN 128
2144 #define VENDOR_ID_LEN 4
2146 /* Congestion management fairness mode */
2147 #define CMNG_FNS_NONE 0
2148 #define CMNG_FNS_MINMAX 1
2150 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2151 #define HC_SEG_ACCESS_ATTN 4
2152 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2154 static const u32 dmae_reg_go_c[] = {
2155 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2156 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2157 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2158 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2161 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2162 void bnx2x_notify_link_changed(struct bnx2x *bp);
2165 #define BNX2X_MF_SD_PROTOCOL(bp) \
2166 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2169 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2170 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2172 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2173 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2175 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2176 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2178 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \
2179 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2181 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
2182 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2183 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2184 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2186 #define IS_MF_FCOE_AFEX(bp) false
2190 #endif /* bnx2x.h */