1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
17 #include <linux/pci.h>
18 #include <linux/netdevice.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/types.h>
21 #include <linux/pci_regs.h>
23 /* compilation time flags */
25 /* define this to make the driver freeze on error to allow getting debug info
26 * (you will need to reboot afterwards) */
27 /* #define BNX2X_STOP_ON_ERROR */
29 #define DRV_MODULE_VERSION "1.78.01-0"
30 #define DRV_MODULE_RELDATE "2012/10/30"
31 #define BNX2X_BC_VER 0x040200
33 #if defined(CONFIG_DCB)
38 #include "bnx2x_hsi.h"
40 #include "../cnic_if.h"
43 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
45 #include <linux/mdio.h>
47 #include "bnx2x_reg.h"
48 #include "bnx2x_fw_defs.h"
49 #include "bnx2x_mfw_req.h"
50 #include "bnx2x_link.h"
52 #include "bnx2x_dcb.h"
53 #include "bnx2x_stats.h"
54 #include "bnx2x_vfpf.h"
62 /* error/debug prints */
64 #define DRV_MODULE_NAME "bnx2x"
66 /* for messages that are currently off */
67 #define BNX2X_MSG_OFF 0x0
68 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
69 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
70 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
71 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
72 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
73 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
74 #define BNX2X_MSG_IOV 0x0800000
75 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
76 #define BNX2X_MSG_ETHTOOL 0x4000000
77 #define BNX2X_MSG_DCB 0x8000000
79 /* regular debug print */
80 #define DP(__mask, fmt, ...) \
82 if (unlikely(bp->msg_enable & (__mask))) \
83 pr_notice("[%s:%d(%s)]" fmt, \
85 bp->dev ? (bp->dev->name) : "?", \
89 #define DP_CONT(__mask, fmt, ...) \
91 if (unlikely(bp->msg_enable & (__mask))) \
92 pr_cont(fmt, ##__VA_ARGS__); \
95 /* errors debug print */
96 #define BNX2X_DBG_ERR(fmt, ...) \
98 if (unlikely(netif_msg_probe(bp))) \
99 pr_err("[%s:%d(%s)]" fmt, \
100 __func__, __LINE__, \
101 bp->dev ? (bp->dev->name) : "?", \
105 /* for errors (never masked) */
106 #define BNX2X_ERR(fmt, ...) \
108 pr_err("[%s:%d(%s)]" fmt, \
109 __func__, __LINE__, \
110 bp->dev ? (bp->dev->name) : "?", \
114 #define BNX2X_ERROR(fmt, ...) \
115 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
118 /* before we have a dev->name use dev_info() */
119 #define BNX2X_DEV_INFO(fmt, ...) \
121 if (unlikely(netif_msg_probe(bp))) \
122 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
125 #ifdef BNX2X_STOP_ON_ERROR
126 #define bnx2x_panic() \
129 BNX2X_ERR("driver assert\n"); \
130 bnx2x_panic_dump(bp, true); \
133 #define bnx2x_panic() \
136 BNX2X_ERR("driver assert\n"); \
137 bnx2x_panic_dump(bp, false); \
141 #define bnx2x_mc_addr(ha) ((ha)->addr)
142 #define bnx2x_uc_addr(ha) ((ha)->addr)
144 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
145 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
146 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
149 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
151 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
152 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
153 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
155 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
156 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
157 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
159 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
160 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
162 #define REG_RD_DMAE(bp, offset, valp, len32) \
164 bnx2x_read_dmae(bp, offset, len32);\
165 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
168 #define REG_WR_DMAE(bp, offset, valp, len32) \
170 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
171 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
175 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
176 REG_WR_DMAE(bp, offset, valp, len32)
178 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
180 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
181 bnx2x_write_big_buf_wb(bp, addr, len32); \
184 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
185 offsetof(struct shmem_region, field))
186 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
187 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
189 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
190 offsetof(struct shmem2_region, field))
191 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
192 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
193 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
194 offsetof(struct mf_cfg, field))
195 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
196 offsetof(struct mf2_cfg, field))
198 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
199 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
200 MF_CFG_ADDR(bp, field), (val))
201 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
203 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
204 (SHMEM2_RD((bp), size) > \
205 offsetof(struct shmem2_region, field)))
207 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
208 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
212 /* General SP events - stats query, cfc delete, etc */
213 #define HC_SP_INDEX_ETH_DEF_CONS 3
216 #define HC_SP_INDEX_EQ_CONS 7
218 /* FCoE L2 connection completions */
219 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
220 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
222 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
223 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
225 /* Special clients parameters */
229 #define BNX2X_FCOE_L2_RX_INDEX \
230 (&bp->def_status_blk->sp_sb.\
231 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
233 #define BNX2X_FCOE_L2_TX_INDEX \
234 (&bp->def_status_blk->sp_sb.\
235 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
239 * CLIDs below is a CLID for func 0, then the CLID for other
240 * functions will be calculated by the formula:
242 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
246 BNX2X_ISCSI_ETH_CL_ID_IDX,
247 BNX2X_FCOE_ETH_CL_ID_IDX,
248 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
251 #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\
254 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
256 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
258 #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
259 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
260 #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
261 #define FCOE_INIT(bp) ((bp)->fcoe_init)
263 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
264 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
269 /* defines for multiple tx priority indices */
270 #define FIRST_TX_ONLY_COS_INDEX 1
271 #define FIRST_TX_COS_INDEX 0
273 /* rules for calculating the cids of tx-only connections */
274 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
275 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
276 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
278 /* fp index inside class of service range */
279 #define FP_COS_TO_TXQ(fp, cos, bp) \
280 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
282 /* Indexes for transmission queues array:
283 * txdata for RSS i CoS j is at location i + (j * num of RSS)
284 * txdata for FCoE (if exist) is at location max cos * num of RSS
285 * txdata for FWD (if exist) is one location after FCoE
286 * txdata for OOO (if exist) is one location after FWD
293 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
294 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
298 * This driver uses new build_skb() API :
299 * RX ring buffer contains pointer to kmalloc() data only,
300 * skb are built only after Hardware filled the frame.
304 DEFINE_DMA_UNMAP_ADDR(mapping);
311 /* Set on the first BD descriptor when there is a split BD */
312 #define BNX2X_TSO_SPLIT_BD (1<<0)
317 DEFINE_DMA_UNMAP_ADDR(mapping);
321 struct doorbell_set_prod data;
325 /* dropless fc FW/HW related params */
326 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
327 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
328 ETH_MAX_AGGREGATION_QUEUES_E1 :\
329 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
330 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
331 #define FW_PREFETCH_CNT 16
332 #define DROPLESS_FC_HEADROOM 100
335 #define BCM_PAGE_SHIFT 12
336 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
337 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
338 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
340 #define PAGES_PER_SGE_SHIFT 0
341 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
342 #define SGE_PAGE_SIZE PAGE_SIZE
343 #define SGE_PAGE_SHIFT PAGE_SHIFT
344 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
345 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
346 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
349 /* SGE ring related macros */
350 #define NUM_RX_SGE_PAGES 2
351 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
352 #define NEXT_PAGE_SGE_DESC_CNT 2
353 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
354 /* RX_SGE_CNT is promised to be a power of 2 */
355 #define RX_SGE_MASK (RX_SGE_CNT - 1)
356 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
357 #define MAX_RX_SGE (NUM_RX_SGE - 1)
358 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
359 (MAX_RX_SGE_CNT - 1)) ? \
360 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
362 #define RX_SGE(x) ((x) & MAX_RX_SGE)
365 * Number of required SGEs is the sum of two:
366 * 1. Number of possible opened aggregations (next packet for
367 * these aggregations will probably consume SGE immidiatelly)
368 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
369 * after placement on BD for new TPA aggregation)
371 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
373 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
374 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
375 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
377 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
378 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
379 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
381 /* Manipulate a bit vector defined as an array of u64 */
383 /* Number of bits in one sge_mask array element */
384 #define BIT_VEC64_ELEM_SZ 64
385 #define BIT_VEC64_ELEM_SHIFT 6
386 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
389 #define __BIT_VEC64_SET_BIT(el, bit) \
391 el = ((el) | ((u64)0x1 << (bit))); \
394 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
396 el = ((el) & (~((u64)0x1 << (bit)))); \
400 #define BIT_VEC64_SET_BIT(vec64, idx) \
401 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
402 (idx) & BIT_VEC64_ELEM_MASK)
404 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
405 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
406 (idx) & BIT_VEC64_ELEM_MASK)
408 #define BIT_VEC64_TEST_BIT(vec64, idx) \
409 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
410 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
412 /* Creates a bitmask of all ones in less significant bits.
413 idx - index of the most significant bit in the created mask */
414 #define BIT_VEC64_ONES_MASK(idx) \
415 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
416 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
418 /*******************************************************/
422 /* Number of u64 elements in SGE mask array */
423 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
424 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
425 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
427 union host_hc_status_block {
428 /* pointer to fp status block e1x */
429 struct host_hc_status_block_e1x *e1x_sb;
430 /* pointer to fp status block e2 */
431 struct host_hc_status_block_e2 *e2_sb;
434 struct bnx2x_agg_info {
436 * First aggregation buffer is a data buffer, the following - are pages.
437 * We will preallocate the data buffer for each aggregation when
438 * we open the interface and will replace the BD at the consumer
439 * with this one when we receive the TPA_START CQE in order to
440 * keep the Rx BD ring consistent.
442 struct sw_rx_bd first_buf;
444 #define BNX2X_TPA_START 1
445 #define BNX2X_TPA_STOP 2
446 #define BNX2X_TPA_ERROR 3
457 #define Q_STATS_OFFSET32(stat_name) \
458 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
460 struct bnx2x_fp_txdata {
462 struct sw_tx_bd *tx_buf_ring;
464 union eth_tx_bd_types *tx_desc_ring;
465 dma_addr_t tx_desc_mapping;
476 unsigned long tx_pkt;
481 struct bnx2x_fastpath *parent_fp;
485 enum bnx2x_tpa_mode_t {
490 struct bnx2x_fastpath {
491 struct bnx2x *bp; /* parent */
493 #define BNX2X_NAPI_WEIGHT 128
494 struct napi_struct napi;
495 union host_hc_status_block status_blk;
496 /* chip independed shortcuts into sb structure */
497 __le16 *sb_index_values;
498 __le16 *sb_running_index;
499 /* chip independed shortcut into rx_prods_offset memory */
500 u32 ustorm_rx_prods_offset;
503 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
504 dma_addr_t status_blk_mapping;
506 enum bnx2x_tpa_mode_t mode;
508 u8 max_cos; /* actual number of active tx coses */
509 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
511 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
512 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
514 struct eth_rx_bd *rx_desc_ring;
515 dma_addr_t rx_desc_mapping;
517 union eth_rx_cqe *rx_comp_ring;
518 dma_addr_t rx_comp_mapping;
521 struct eth_rx_sge *rx_sge_ring;
522 dma_addr_t rx_sge_mapping;
524 u64 sge_mask[RX_SGE_MASK_LEN];
530 u8 index; /* number in fp array */
531 u8 rx_queue; /* index for skb_record */
532 u8 cl_id; /* eth client id */
534 u8 fw_sb_id; /* status block number in FW */
535 u8 igu_sb_id; /* status block number in HW */
542 /* The last maximal completed SGE */
545 unsigned long rx_pkt,
549 struct bnx2x_agg_info *tpa_info;
551 #ifdef BNX2X_STOP_ON_ERROR
554 /* The size is calculated using the following:
555 sizeof name field from netdev structure +
557 4 (for the digits and to make it DWORD aligned) */
558 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
559 char name[FP_NAME_SIZE];
562 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
563 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
564 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
565 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
567 /* Use 2500 as a mini-jumbo MTU for FCoE */
568 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
570 #define FCOE_IDX_OFFSET 0
572 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
574 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
575 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
576 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
577 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
578 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
579 txdata_ptr[FIRST_TX_COS_INDEX] \
583 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
584 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
585 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
589 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
590 #define RX_COPY_THRESH 92
592 #define NUM_TX_RINGS 16
593 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
594 #define NEXT_PAGE_TX_DESC_CNT 1
595 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
596 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
597 #define MAX_TX_BD (NUM_TX_BD - 1)
598 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
599 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
600 (MAX_TX_DESC_CNT - 1)) ? \
601 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
603 #define TX_BD(x) ((x) & MAX_TX_BD)
604 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
606 /* number of NEXT_PAGE descriptors may be required during placement */
607 #define NEXT_CNT_PER_TX_PKT(bds) \
608 (((bds) + MAX_TX_DESC_CNT - 1) / \
609 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
610 /* max BDs per tx packet w/o next_pages:
611 * START_BD - describes packed
612 * START_BD(splitted) - includes unpaged data segment for GSO
613 * PARSING_BD - for TSO and CSUM data
614 * Frag BDs - decribes pages for frags
616 #define BDS_PER_TX_PKT 3
617 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
618 /* max BDs per tx packet including next pages */
619 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
620 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
622 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
623 #define NUM_RX_RINGS 8
624 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
625 #define NEXT_PAGE_RX_DESC_CNT 2
626 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
627 #define RX_DESC_MASK (RX_DESC_CNT - 1)
628 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
629 #define MAX_RX_BD (NUM_RX_BD - 1)
630 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
632 /* dropless fc calculations for BDs
634 * Number of BDs should as number of buffers in BRB:
635 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
636 * "next" elements on each page
638 #define NUM_BD_REQ BRB_SIZE(bp)
639 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
641 #define BD_TH_LO(bp) (NUM_BD_REQ + \
642 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
644 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
646 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
648 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
649 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
650 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
651 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
652 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
653 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
656 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
657 (MAX_RX_DESC_CNT - 1)) ? \
658 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
660 #define RX_BD(x) ((x) & MAX_RX_BD)
663 * As long as CQE is X times bigger than BD entry we have to allocate X times
664 * more pages for CQ ring in order to keep it balanced with BD ring
666 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
667 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
668 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
669 #define NEXT_PAGE_RCQ_DESC_CNT 1
670 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
671 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
672 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
673 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
674 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
675 (MAX_RCQ_DESC_CNT - 1)) ? \
676 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
678 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
680 /* dropless fc calculations for RCQs
682 * Number of RCQs should be as number of buffers in BRB:
683 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
684 * "next" elements on each page
686 #define NUM_RCQ_REQ BRB_SIZE(bp)
687 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
689 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
690 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
692 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
695 /* This is needed for determining of last_max */
696 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
697 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
700 #define BNX2X_SWCID_SHIFT 17
701 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
703 /* used on a CID received from the HW */
704 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
705 #define CQE_CMD(x) (le32_to_cpu(x) >> \
706 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
708 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
709 le32_to_cpu((bd)->addr_lo))
710 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
712 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
713 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
714 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
715 #error "Min DB doorbell stride is 8"
717 #define DPM_TRIGER_TYPE 0x40
718 #define DOORBELL(bp, cid, val) \
720 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
725 /* TX CSUM helpers */
726 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
728 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
731 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
734 #define XMIT_CSUM_V4 0x1
735 #define XMIT_CSUM_V6 0x2
736 #define XMIT_CSUM_TCP 0x4
737 #define XMIT_GSO_V4 0x8
738 #define XMIT_GSO_V6 0x10
740 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
741 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
744 /* stuff added to make the code fit 80Col */
745 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
746 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
747 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
748 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
749 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
751 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
753 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
754 (((le16_to_cpu(flags) & \
755 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
756 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
757 == PRS_FLAG_OVERETH_IPV4)
758 #define BNX2X_RX_SUM_FIX(cqe) \
759 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
762 #define FP_USB_FUNC_OFF \
763 offsetof(struct cstorm_status_block_u, func)
764 #define FP_CSB_FUNC_OFF \
765 offsetof(struct cstorm_status_block_c, func)
767 #define HC_INDEX_ETH_RX_CQ_CONS 1
769 #define HC_INDEX_OOO_TX_CQ_CONS 4
771 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
773 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
775 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
777 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
779 #define BNX2X_RX_SB_INDEX \
780 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
782 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
784 #define BNX2X_TX_SB_INDEX_COS0 \
785 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
787 /* end of fast path */
791 struct bnx2x_common {
794 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
795 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
797 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
798 #define CHIP_NUM_57710 0x164e
799 #define CHIP_NUM_57711 0x164f
800 #define CHIP_NUM_57711E 0x1650
801 #define CHIP_NUM_57712 0x1662
802 #define CHIP_NUM_57712_MF 0x1663
803 #define CHIP_NUM_57712_VF 0x166f
804 #define CHIP_NUM_57713 0x1651
805 #define CHIP_NUM_57713E 0x1652
806 #define CHIP_NUM_57800 0x168a
807 #define CHIP_NUM_57800_MF 0x16a5
808 #define CHIP_NUM_57800_VF 0x16a9
809 #define CHIP_NUM_57810 0x168e
810 #define CHIP_NUM_57810_MF 0x16ae
811 #define CHIP_NUM_57810_VF 0x16af
812 #define CHIP_NUM_57811 0x163d
813 #define CHIP_NUM_57811_MF 0x163e
814 #define CHIP_NUM_57811_VF 0x163f
815 #define CHIP_NUM_57840_OBSOLETE 0x168d
816 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
817 #define CHIP_NUM_57840_4_10 0x16a1
818 #define CHIP_NUM_57840_2_20 0x16a2
819 #define CHIP_NUM_57840_MF 0x16a4
820 #define CHIP_NUM_57840_VF 0x16ad
821 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
822 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
823 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
824 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
825 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
826 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
827 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
828 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
829 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
830 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
831 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
832 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
833 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
834 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
835 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
836 #define CHIP_IS_57840(bp) \
837 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
838 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
839 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
840 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
841 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
842 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
843 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
845 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
846 CHIP_IS_57712_MF(bp))
847 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
848 CHIP_IS_57800_MF(bp) || \
849 CHIP_IS_57810(bp) || \
850 CHIP_IS_57810_MF(bp) || \
851 CHIP_IS_57810_VF(bp) || \
852 CHIP_IS_57811(bp) || \
853 CHIP_IS_57811_MF(bp) || \
854 CHIP_IS_57811_VF(bp) || \
855 CHIP_IS_57840(bp) || \
856 CHIP_IS_57840_MF(bp) || \
857 CHIP_IS_57840_VF(bp))
858 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
859 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
860 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
862 #define CHIP_REV_SHIFT 12
863 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
864 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
865 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
866 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
867 /* assume maximum 5 revisions */
868 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
869 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
870 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
871 !(CHIP_REV_VAL(bp) & 0x00001000))
872 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
873 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
874 (CHIP_REV_VAL(bp) & 0x00001000))
876 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
877 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
879 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
880 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
881 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
882 (CHIP_REV_SHIFT + 1)) \
884 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
887 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
888 (CHIP_REV(bp) == CHIP_REV_Bx))
889 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
890 (CHIP_REV(bp) == CHIP_REV_Ax))
891 /* This define is used in two main places:
892 * 1. In the early stages of nic_load, to know if to configrue Parser / Searcher
893 * to nic-only mode or to offload mode. Offload mode is configured if either the
894 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
895 * registered for this port (which means that the user wants storage services).
896 * 2. During cnic-related load, to know if offload mode is already configured in
897 * the HW or needs to be configrued.
898 * Since the transition from nic-mode to offload-mode in HW causes traffic
899 * coruption, nic-mode is configured only in ports on which storage services
900 * where never requested.
902 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
905 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
906 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
907 #define BNX2X_NVRAM_PAGE_SIZE 256
919 #define INT_BLOCK_HC 0
920 #define INT_BLOCK_IGU 1
921 #define INT_BLOCK_MODE_NORMAL 0
922 #define INT_BLOCK_MODE_BW_COMP 2
923 #define CHIP_INT_MODE_IS_NBC(bp) \
924 (!CHIP_IS_E1x(bp) && \
925 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
926 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
929 #define CHIP_4_PORT_MODE 0x0
930 #define CHIP_2_PORT_MODE 0x1
931 #define CHIP_PORT_MODE_NONE 0x2
932 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
933 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
938 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
939 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
940 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
942 #define MAX_IGU_ATTN_ACK_TO 100
950 u32 link_config[LINK_CONFIG_SIZE];
952 u32 supported[LINK_CONFIG_SIZE];
953 /* link settings - missing defines */
954 #define SUPPORTED_2500baseX_Full (1 << 15)
956 u32 advertising[LINK_CONFIG_SIZE];
957 /* link settings - missing defines */
958 #define ADVERTISED_2500baseX_Full (1 << 15)
962 /* used to synchronize phy accesses */
963 struct mutex phy_mutex;
967 struct nig_stats old_nig_stats;
972 #define STATS_OFFSET32(stat_name) \
973 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
977 /* slow path work-queue */
978 extern struct workqueue_struct *bnx2x_wq;
980 #define BNX2X_MAX_NUM_OF_VFS 64
981 #define BNX2X_VF_CID_WND 0
982 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
983 #define BNX2X_CLIENTS_PER_VF 1
984 #define BNX2X_FIRST_VF_CID 256
985 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
986 #define BNX2X_VF_ID_INVALID 0xFF
989 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
990 * control by the number of fast-path status blocks supported by the
991 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
992 * status block represents an independent interrupts context that can
993 * serve a regular L2 networking queue. However special L2 queues such
994 * as the FCoE queue do not require a FP-SB and other components like
995 * the CNIC may consume FP-SB reducing the number of possible L2 queues
997 * If the maximum number of FP-SB available is X then:
998 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
999 * regular L2 queues is Y=X-1
1000 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1001 * c. If the FCoE L2 queue is supported the actual number of L2 queues
1003 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1004 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
1005 * FP interrupt context for the CNIC).
1006 * e. The number of HW context (CID count) is always X or X+1 if FCoE
1007 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
1010 /* fast-path interrupt contexts E1x */
1011 #define FP_SB_MAX_E1x 16
1012 /* fast-path interrupt contexts E2 */
1013 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
1016 struct eth_context eth;
1020 /* CDU host DB constants */
1021 #define CDU_ILT_PAGE_SZ_HW 2
1022 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1023 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1025 #define CNIC_ISCSI_CID_MAX 256
1026 #define CNIC_FCOE_CID_MAX 2048
1027 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1028 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1030 #define QM_ILT_PAGE_SZ_HW 0
1031 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1032 #define QM_CID_ROUND 1024
1034 /* TM (timers) host DB constants */
1035 #define TM_ILT_PAGE_SZ_HW 0
1036 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1037 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
1038 #define TM_CONN_NUM 1024
1039 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1040 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1042 /* SRC (Searcher) host DB constants */
1043 #define SRC_ILT_PAGE_SZ_HW 0
1044 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1045 #define SRC_HASH_BITS 10
1046 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1047 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1048 #define SRC_T2_SZ SRC_ILT_SZ
1049 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1051 #define MAX_DMAE_C 8
1053 /* DMA memory not used in fastpath */
1054 struct bnx2x_slowpath {
1056 struct mac_configuration_cmd e1x;
1057 struct eth_classify_rules_ramrod_data e2;
1062 struct tstorm_eth_mac_filter_config e1x;
1063 struct eth_filter_rules_ramrod_data e2;
1067 struct mac_configuration_cmd e1;
1068 struct eth_multicast_rules_ramrod_data e2;
1071 struct eth_rss_update_ramrod_data rss_rdata;
1073 /* Queue State related ramrods are always sent under rtnl_lock */
1075 struct client_init_ramrod_data init_data;
1076 struct client_update_ramrod_data update_data;
1080 struct function_start_data func_start;
1081 /* pfc configuration for DCBX ramrod */
1082 struct flow_control_configuration pfc_config;
1085 /* afex ramrod can not be a part of func_rdata union because these
1086 * events might arrive in parallel to other events from func_rdata.
1087 * Therefore, if they would have been defined in the same union,
1088 * data can get corrupted.
1090 struct afex_vif_list_ramrod_data func_afex_rdata;
1092 /* used by dmae command executer */
1093 struct dmae_command dmae[MAX_DMAE_C];
1096 union mac_stats mac_stats;
1097 struct nig_stats nig_stats;
1098 struct host_port_stats port_stats;
1099 struct host_func_stats func_stats;
1104 union drv_info_to_mcp drv_info_to_mcp;
1107 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1108 #define bnx2x_sp_mapping(bp, var) \
1109 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1112 /* attn group wiring */
1113 #define MAX_DYNAMIC_ATTN_GRPS 8
1128 union cdu_context *vcxt;
1129 dma_addr_t cxt_mapping;
1138 enum bnx2x_recovery_state {
1139 BNX2X_RECOVERY_DONE,
1140 BNX2X_RECOVERY_INIT,
1141 BNX2X_RECOVERY_WAIT,
1142 BNX2X_RECOVERY_FAILED,
1143 BNX2X_RECOVERY_NIC_LOADING
1147 * Event queue (EQ or event ring) MC hsi
1148 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1150 #define NUM_EQ_PAGES 1
1151 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1152 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1153 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1154 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1155 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1157 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1158 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1159 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1161 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1162 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1164 #define BNX2X_EQ_INDEX \
1165 (&bp->def_status_blk->sp_sb.\
1166 index_values[HC_SP_INDEX_EQ_CONS])
1168 /* This is a data that will be used to create a link report message.
1169 * We will keep the data used for the last link report in order
1170 * to prevent reporting the same link parameters twice.
1172 struct bnx2x_link_report_data {
1173 u16 line_speed; /* Effective line speed */
1174 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1178 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1179 BNX2X_LINK_REPORT_LINK_DOWN,
1180 BNX2X_LINK_REPORT_RX_FC_ON,
1181 BNX2X_LINK_REPORT_TX_FC_ON,
1185 BNX2X_PORT_QUERY_IDX,
1187 BNX2X_FCOE_QUERY_IDX,
1188 BNX2X_FIRST_QUEUE_QUERY_IDX,
1191 struct bnx2x_fw_stats_req {
1192 struct stats_query_header hdr;
1193 struct stats_query_entry query[FP_SB_MAX_E1x+
1194 BNX2X_FIRST_QUEUE_QUERY_IDX];
1197 struct bnx2x_fw_stats_data {
1198 struct stats_counter storm_counters;
1199 struct per_port_stats port;
1200 struct per_pf_stats pf;
1201 struct fcoe_statistics_params fcoe;
1202 struct per_queue_stats queue_stats[1];
1205 /* Public slow path states */
1207 BNX2X_SP_RTNL_SETUP_TC,
1208 BNX2X_SP_RTNL_TX_TIMEOUT,
1209 BNX2X_SP_RTNL_FAN_FAILURE,
1210 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1211 BNX2X_SP_RTNL_ENABLE_SRIOV,
1212 BNX2X_SP_RTNL_VFPF_MCAST,
1213 BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
1217 struct bnx2x_prev_path_list {
1221 struct list_head list;
1225 struct bnx2x_sp_objs {
1227 struct bnx2x_vlan_mac_obj mac_obj;
1229 /* Queue State object */
1230 struct bnx2x_queue_sp_obj q_obj;
1233 struct bnx2x_fp_stats {
1234 struct tstorm_per_queue_stats old_tclient;
1235 struct ustorm_per_queue_stats old_uclient;
1236 struct xstorm_per_queue_stats old_xclient;
1237 struct bnx2x_eth_q_stats eth_q_stats;
1238 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1242 /* Fields used in the tx and intr/napi performance paths
1243 * are grouped together in the beginning of the structure
1245 struct bnx2x_fastpath *fp;
1246 struct bnx2x_sp_objs *sp_objs;
1247 struct bnx2x_fp_stats *fp_stats;
1248 struct bnx2x_fp_txdata *bnx2x_txq;
1249 void __iomem *regview;
1250 void __iomem *doorbells;
1253 u8 pf_num; /* absolute PF number */
1254 u8 pfid; /* per-path PF number */
1255 int base_fw_ndsb; /**/
1256 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1257 #define BP_PORT(bp) (bp->pfid & 1)
1258 #define BP_FUNC(bp) (bp->pfid)
1259 #define BP_ABS_FUNC(bp) (bp->pf_num)
1260 #define BP_VN(bp) ((bp)->pfid >> 1)
1261 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1262 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1263 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1264 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1265 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1267 #ifdef CONFIG_BNX2X_SRIOV
1268 /* vf pf channel mailbox contains request and response buffers */
1269 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1270 dma_addr_t vf2pf_mbox_mapping;
1272 /* we set aside a copy of the acquire response */
1273 struct pfvf_acquire_resp_tlv acquire_resp;
1275 /* bulletin board for messages from pf to vf */
1276 union pf_vf_bulletin *pf2vf_bulletin;
1277 dma_addr_t pf2vf_bulletin_mapping;
1279 struct pf_vf_bulletin_content old_bulletin;
1280 #endif /* CONFIG_BNX2X_SRIOV */
1282 struct net_device *dev;
1283 struct pci_dev *pdev;
1285 const struct iro *iro_arr;
1286 #define IRO (bp->iro_arr)
1288 enum bnx2x_recovery_state recovery_state;
1290 struct msix_entry *msix_table;
1294 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1295 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1296 #define ETH_MIN_PACKET_SIZE 60
1297 #define ETH_MAX_PACKET_SIZE 1500
1298 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1299 /* TCP with Timestamp Option (32) + IPv6 (40) */
1300 #define ETH_MAX_TPA_HEADER_SIZE 72
1302 /* Max supported alignment is 256 (8 shift) */
1303 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1305 /* FW uses 2 Cache lines Alignment for start packet and size
1307 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1308 * at the end of skb->data, to avoid wasting a full cache line.
1309 * This reduces memory use (skb->truesize).
1311 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1313 #define BNX2X_FW_RX_ALIGN_END \
1314 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1315 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1317 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1319 struct host_sp_status_block *def_status_blk;
1320 #define DEF_SB_IGU_ID 16
1321 #define DEF_SB_ID HC_SP_SB_ID
1325 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1327 /* slow path ring */
1328 struct eth_spe *spq;
1329 dma_addr_t spq_mapping;
1331 struct eth_spe *spq_prod_bd;
1332 struct eth_spe *spq_last_bd;
1333 __le16 *dsb_sp_prod;
1334 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1335 /* used to synchronize spq accesses */
1336 spinlock_t spq_lock;
1339 union event_ring_elem *eq_ring;
1340 dma_addr_t eq_mapping;
1344 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1348 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1350 /* Counter for completed statistics ramrods */
1353 /* End of fields used in the performance code paths */
1359 #define PCIX_FLAG (1 << 0)
1360 #define PCI_32BIT_FLAG (1 << 1)
1361 #define ONE_PORT_FLAG (1 << 2)
1362 #define NO_WOL_FLAG (1 << 3)
1363 #define USING_DAC_FLAG (1 << 4)
1364 #define USING_MSIX_FLAG (1 << 5)
1365 #define USING_MSI_FLAG (1 << 6)
1366 #define DISABLE_MSI_FLAG (1 << 7)
1367 #define TPA_ENABLE_FLAG (1 << 8)
1368 #define NO_MCP_FLAG (1 << 9)
1369 #define GRO_ENABLE_FLAG (1 << 10)
1370 #define MF_FUNC_DIS (1 << 11)
1371 #define OWN_CNIC_IRQ (1 << 12)
1372 #define NO_ISCSI_OOO_FLAG (1 << 13)
1373 #define NO_ISCSI_FLAG (1 << 14)
1374 #define NO_FCOE_FLAG (1 << 15)
1375 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1376 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1377 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1378 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1379 #define IS_VF_FLAG (1 << 22)
1381 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
1383 #ifdef CONFIG_BNX2X_SRIOV
1384 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1385 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
1387 #define IS_VF(bp) false
1388 #define IS_PF(bp) true
1391 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1392 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1393 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1398 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1400 /* Flag that indicates that we can start looking for FCoE L2 queue
1401 * completions in the default status block.
1408 struct delayed_work sp_task;
1409 atomic_t interrupt_occurred;
1410 struct delayed_work sp_rtnl_task;
1412 struct delayed_work period_task;
1413 struct timer_list timer;
1414 int current_interval;
1417 u16 fw_drv_pulse_wr_seq;
1420 struct link_params link_params;
1421 struct link_vars link_vars;
1423 struct bnx2x_link_report_data last_reported_link;
1425 struct mdio_if_info mdio;
1427 struct bnx2x_common common;
1428 struct bnx2x_port port;
1430 struct cmng_init cmng;
1432 u32 mf_config[E1HVN_MAX];
1434 u32 path_has_ovlan; /* E3 */
1437 #define IS_MF(bp) (bp->mf_mode != 0)
1438 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1439 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1440 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1446 u16 tx_quick_cons_trip_int;
1447 u16 tx_quick_cons_trip;
1451 u16 rx_quick_cons_trip_int;
1452 u16 rx_quick_cons_trip;
1455 /* Maximal coalescing timeout in us */
1456 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1461 #define BNX2X_STATE_CLOSED 0
1462 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1463 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1464 #define BNX2X_STATE_OPEN 0x3000
1465 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1466 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1468 #define BNX2X_STATE_DIAG 0xe000
1469 #define BNX2X_STATE_ERROR 0xf000
1471 #define BNX2X_MAX_PRIORITY 8
1472 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1473 #define BNX2X_MAX_COS 3
1474 #define BNX2X_MAX_TX_COS 2
1476 uint num_ethernet_queues;
1477 uint num_cnic_queues;
1478 int num_napi_queues;
1482 #define BNX2X_RX_MODE_NONE 0
1483 #define BNX2X_RX_MODE_NORMAL 1
1484 #define BNX2X_RX_MODE_ALLMULTI 2
1485 #define BNX2X_RX_MODE_PROMISC 3
1486 #define BNX2X_MAX_MULTICAST 64
1491 u8 min_msix_vec_cnt;
1494 dma_addr_t def_status_blk_mapping;
1496 struct bnx2x_slowpath *slowpath;
1497 dma_addr_t slowpath_mapping;
1499 /* Total number of FW statistics requests */
1503 * This is a memory buffer that will contain both statistics
1504 * ramrod request and data.
1507 dma_addr_t fw_stats_mapping;
1510 * FW statistics request shortcut (points at the
1511 * beginning of fw_stats buffer).
1513 struct bnx2x_fw_stats_req *fw_stats_req;
1514 dma_addr_t fw_stats_req_mapping;
1515 int fw_stats_req_sz;
1518 * FW statistics data shortcut (points at the beginning of
1519 * fw_stats buffer + fw_stats_req_sz).
1521 struct bnx2x_fw_stats_data *fw_stats_data;
1522 dma_addr_t fw_stats_data_mapping;
1523 int fw_stats_data_sz;
1525 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1526 * context size we need 8 ILT entries.
1528 #define ILT_MAX_L2_LINES 8
1529 struct hw_context context[ILT_MAX_L2_LINES];
1531 struct bnx2x_ilt *ilt;
1532 #define BP_ILT(bp) ((bp)->ilt)
1533 #define ILT_MAX_LINES 256
1535 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1538 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1541 * Maximum CID count that might be required by the bnx2x:
1542 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1544 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1545 + 2 * CNIC_SUPPORT(bp))
1546 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1547 + 2 * CNIC_SUPPORT(bp))
1548 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1556 dma_addr_t t2_mapping;
1557 struct cnic_ops __rcu *cnic_ops;
1560 struct cnic_eth_dev cnic_eth_dev;
1561 union host_hc_status_block cnic_sb;
1562 dma_addr_t cnic_sb_mapping;
1563 struct eth_spe *cnic_kwq;
1564 struct eth_spe *cnic_kwq_prod;
1565 struct eth_spe *cnic_kwq_cons;
1566 struct eth_spe *cnic_kwq_last;
1567 u16 cnic_kwq_pending;
1568 u16 cnic_spq_pending;
1569 u8 fip_mac[ETH_ALEN];
1570 struct mutex cnic_mutex;
1571 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1573 /* Start index of the "special" (CNIC related) L2 cleints */
1577 /* used to synchronize dmae accesses */
1578 spinlock_t dmae_lock;
1580 /* used to protect the FW mail box */
1581 struct mutex fw_mb_mutex;
1583 /* used to synchronize stats collecting */
1586 /* used for synchronization of concurrent threads statistics handling */
1587 spinlock_t stats_lock;
1589 /* used by dmae command loader */
1590 struct dmae_command stats_dmae;
1594 struct bnx2x_eth_stats eth_stats;
1595 struct host_func_stats func_stats;
1596 struct bnx2x_eth_stats_old eth_stats_old;
1597 struct bnx2x_net_stats_old net_stats_old;
1598 struct bnx2x_fw_port_stats_old fw_stats_old;
1601 struct z_stream_s *strm;
1603 dma_addr_t gunzip_mapping;
1605 #define FW_BUF_SIZE 0x8000
1606 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1607 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1608 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1610 struct raw_op *init_ops;
1611 /* Init blocks offsets inside init_ops */
1612 u16 *init_ops_offsets;
1613 /* Data blob - has 32 bit granularity */
1615 u32 init_mode_flags;
1616 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1617 /* Zipped PRAM blobs - raw data */
1618 const u8 *tsem_int_table_data;
1619 const u8 *tsem_pram_data;
1620 const u8 *usem_int_table_data;
1621 const u8 *usem_pram_data;
1622 const u8 *xsem_int_table_data;
1623 const u8 *xsem_pram_data;
1624 const u8 *csem_int_table_data;
1625 const u8 *csem_pram_data;
1626 #define INIT_OPS(bp) (bp->init_ops)
1627 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1628 #define INIT_DATA(bp) (bp->init_data)
1629 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1630 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1631 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1632 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1633 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1634 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1635 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1636 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1638 #define PHY_FW_VER_LEN 20
1640 const struct firmware *firmware;
1642 struct bnx2x_vfdb *vfdb;
1643 #define IS_SRIOV(bp) ((bp)->vfdb)
1645 /* DCB support on/off */
1647 #define BNX2X_DCB_STATE_OFF 0
1648 #define BNX2X_DCB_STATE_ON 1
1650 /* DCBX engine mode */
1652 #define BNX2X_DCBX_ENABLED_OFF 0
1653 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1654 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1655 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1657 bool dcbx_mode_uset;
1659 struct bnx2x_config_dcbx_params dcbx_config_params;
1660 struct bnx2x_dcbx_port_params dcbx_port_params;
1663 /* CAM credit pools */
1665 /* used only in sriov */
1666 struct bnx2x_credit_pool_obj vlans_pool;
1668 struct bnx2x_credit_pool_obj macs_pool;
1670 /* RX_MODE object */
1671 struct bnx2x_rx_mode_obj rx_mode_obj;
1674 struct bnx2x_mcast_obj mcast_obj;
1676 /* RSS configuration object */
1677 struct bnx2x_rss_config_obj rss_conf_obj;
1679 /* Function State controlling object */
1680 struct bnx2x_func_sp_obj func_obj;
1682 unsigned long sp_state;
1684 /* operation indication for the sp_rtnl task */
1685 unsigned long sp_rtnl_state;
1687 /* DCBX Negotation results */
1688 struct dcbx_features dcbx_local_feat;
1692 struct dcbx_features dcbx_remote_feat;
1693 u32 dcbx_remote_flags;
1695 /* AFEX: store default vlan used */
1696 int afex_def_vlan_tag;
1697 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1700 /* multiple tx classes of service */
1703 /* priority to cos mapping */
1705 u32 dump_preset_idx;
1708 /* Tx queues may be less or equal to Rx queues */
1709 extern int num_queues;
1710 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1711 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1712 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1713 (bp)->num_cnic_queues)
1714 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1716 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1718 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1719 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1721 #define RSS_IPV4_CAP_MASK \
1722 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1724 #define RSS_IPV4_TCP_CAP_MASK \
1725 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1727 #define RSS_IPV6_CAP_MASK \
1728 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1730 #define RSS_IPV6_TCP_CAP_MASK \
1731 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1733 /* func init flags */
1734 #define FUNC_FLG_RSS 0x0001
1735 #define FUNC_FLG_STATS 0x0002
1736 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1737 #define FUNC_FLG_TPA 0x0008
1738 #define FUNC_FLG_SPQ 0x0010
1739 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1742 struct bnx2x_func_init_params {
1744 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1745 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1748 u16 func_id; /* abs fid */
1750 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1753 #define for_each_cnic_queue(bp, var) \
1754 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1756 if (skip_queue(bp, var)) \
1760 #define for_each_eth_queue(bp, var) \
1761 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1763 #define for_each_nondefault_eth_queue(bp, var) \
1764 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1766 #define for_each_queue(bp, var) \
1767 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1768 if (skip_queue(bp, var)) \
1772 /* Skip forwarding FP */
1773 #define for_each_valid_rx_queue(bp, var) \
1775 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1776 BNX2X_NUM_ETH_QUEUES(bp)); \
1778 if (skip_rx_queue(bp, var)) \
1782 #define for_each_rx_queue_cnic(bp, var) \
1783 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1785 if (skip_rx_queue(bp, var)) \
1789 #define for_each_rx_queue(bp, var) \
1790 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1791 if (skip_rx_queue(bp, var)) \
1796 #define for_each_valid_tx_queue(bp, var) \
1798 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1799 BNX2X_NUM_ETH_QUEUES(bp)); \
1801 if (skip_tx_queue(bp, var)) \
1805 #define for_each_tx_queue_cnic(bp, var) \
1806 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1808 if (skip_tx_queue(bp, var)) \
1812 #define for_each_tx_queue(bp, var) \
1813 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1814 if (skip_tx_queue(bp, var)) \
1818 #define for_each_nondefault_queue(bp, var) \
1819 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1820 if (skip_queue(bp, var)) \
1824 #define for_each_cos_in_tx_queue(fp, var) \
1825 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1828 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1830 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1833 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1835 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1837 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1843 * bnx2x_set_mac_one - configure a single MAC address
1845 * @bp: driver handle
1846 * @mac: MAC to configure
1847 * @obj: MAC object handle
1848 * @set: if 'true' add a new MAC, otherwise - delete
1849 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1850 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1852 * Configures one MAC according to provided parameters or continues the
1853 * execution of previously scheduled commands if RAMROD_CONT is set in
1856 * Returns zero if operation has successfully completed, a positive value if the
1857 * operation has been successfully scheduled and a negative - if a requested
1858 * operations has failed.
1860 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1861 struct bnx2x_vlan_mac_obj *obj, bool set,
1862 int mac_type, unsigned long *ramrod_flags);
1864 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1866 * @bp: driver handle
1867 * @mac_obj: MAC object handle
1868 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1869 * @wait_for_comp: if 'true' block until completion
1871 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1873 * Returns zero if operation has successfully completed, a positive value if the
1874 * operation has been successfully scheduled and a negative - if a requested
1875 * operations has failed.
1877 int bnx2x_del_all_macs(struct bnx2x *bp,
1878 struct bnx2x_vlan_mac_obj *mac_obj,
1879 int mac_type, bool wait_for_comp);
1881 /* Init Function API */
1882 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1883 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
1884 u8 vf_valid, int fw_sb_id, int igu_sb_id);
1885 u32 bnx2x_get_pretend_reg(struct bnx2x *bp);
1886 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1887 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1888 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1889 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1890 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1892 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
1895 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1896 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1898 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1899 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1900 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1901 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1902 bool with_comp, u8 comp_type);
1904 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
1905 u8 src_type, u8 dst_type);
1906 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae);
1907 void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl);
1909 /* FLR related routines */
1910 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
1911 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
1912 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
1913 u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
1914 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1915 char *msg, u32 poll_cnt);
1917 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1918 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1919 u32 data_hi, u32 data_lo, int cmd_type);
1920 void bnx2x_update_coalesce(struct bnx2x *bp);
1921 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1923 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1929 val = REG_RD(bp, reg);
1930 if (val == expected)
1940 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
1943 #define BNX2X_ILT_ZALLOC(x, y, size) \
1945 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1947 memset(x, 0, size); \
1950 #define BNX2X_ILT_FREE(x, y, size) \
1953 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1959 #define ILOG2(x) (ilog2((x)))
1961 #define ILT_NUM_PAGE_ENTRIES (3072)
1962 /* In 57710/11 we use whole table since we have 8 func
1963 * In 57712 we have only 4 func, but use same size per func, then only half of
1966 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1968 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1970 * the phys address is shifted right 12 bits and has an added
1971 * 1=valid bit added to the 53rd bit
1972 * then since this is a wide register(TM)
1973 * we split it into two 32 bit writes
1975 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1976 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1978 /* load/unload mode */
1979 #define LOAD_NORMAL 0
1982 #define LOAD_LOOPBACK_EXT 3
1983 #define UNLOAD_NORMAL 0
1984 #define UNLOAD_CLOSE 1
1985 #define UNLOAD_RECOVERY 2
1988 /* DMAE command defines */
1989 #define DMAE_TIMEOUT -1
1990 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1991 #define DMAE_NOT_RDY -3
1992 #define DMAE_PCI_ERR_FLAG 0x80000000
1994 #define DMAE_SRC_PCI 0
1995 #define DMAE_SRC_GRC 1
1997 #define DMAE_DST_NONE 0
1998 #define DMAE_DST_PCI 1
1999 #define DMAE_DST_GRC 2
2001 #define DMAE_COMP_PCI 0
2002 #define DMAE_COMP_GRC 1
2004 /* E2 and onward - PCI error handling in the completion */
2006 #define DMAE_COMP_REGULAR 0
2007 #define DMAE_COM_SET_ERR 1
2009 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
2010 DMAE_COMMAND_SRC_SHIFT)
2011 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
2012 DMAE_COMMAND_SRC_SHIFT)
2014 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
2015 DMAE_COMMAND_DST_SHIFT)
2016 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
2017 DMAE_COMMAND_DST_SHIFT)
2019 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
2020 DMAE_COMMAND_C_DST_SHIFT)
2021 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
2022 DMAE_COMMAND_C_DST_SHIFT)
2024 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
2026 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2027 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2028 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2029 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2031 #define DMAE_CMD_PORT_0 0
2032 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2034 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
2035 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
2036 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
2038 #define DMAE_SRC_PF 0
2039 #define DMAE_SRC_VF 1
2041 #define DMAE_DST_PF 0
2042 #define DMAE_DST_VF 1
2044 #define DMAE_C_SRC 0
2045 #define DMAE_C_DST 1
2047 #define DMAE_LEN32_RD_MAX 0x80
2048 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2050 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
2053 #define MAX_DMAE_C_PER_PORT 8
2054 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2056 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2059 /* PCIE link and speed */
2060 #define PCICFG_LINK_WIDTH 0x1f00000
2061 #define PCICFG_LINK_WIDTH_SHIFT 20
2062 #define PCICFG_LINK_SPEED 0xf0000
2063 #define PCICFG_LINK_SPEED_SHIFT 16
2065 #define BNX2X_NUM_TESTS_SF 7
2066 #define BNX2X_NUM_TESTS_MF 3
2067 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2070 #define BNX2X_PHY_LOOPBACK 0
2071 #define BNX2X_MAC_LOOPBACK 1
2072 #define BNX2X_EXT_LOOPBACK 2
2073 #define BNX2X_PHY_LOOPBACK_FAILED 1
2074 #define BNX2X_MAC_LOOPBACK_FAILED 2
2075 #define BNX2X_EXT_LOOPBACK_FAILED 3
2076 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2077 BNX2X_PHY_LOOPBACK_FAILED)
2080 #define STROM_ASSERT_ARRAY_SIZE 50
2083 /* must be used on a CID before placing it on a HW ring */
2084 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
2085 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2088 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2089 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2093 #define MAX_SPQ_PENDING 8
2095 /* CMNG constants, as derived from system spec calculations */
2096 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2097 #define DEF_MIN_RATE 100
2098 /* resolution of the rate shaping timer - 400 usec */
2099 #define RS_PERIODIC_TIMEOUT_USEC 400
2100 /* number of bytes in single QM arbitration cycle -
2101 * coefficient for calculating the fairness timer */
2102 #define QM_ARB_BYTES 160000
2103 /* resolution of Min algorithm 1:100 */
2105 /* how many bytes above threshold for the minimal credit of Min algorithm*/
2106 #define MIN_ABOVE_THRESH 32768
2107 /* Fairness algorithm integration time coefficient -
2108 * for calculating the actual Tfair */
2109 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2110 /* Memory of fairness algorithm . 2 cycles */
2114 #define ATTN_NIG_FOR_FUNC (1L << 8)
2115 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2116 #define GPIO_2_FUNC (1L << 10)
2117 #define GPIO_3_FUNC (1L << 11)
2118 #define GPIO_4_FUNC (1L << 12)
2119 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2120 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2121 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2122 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2123 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2124 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2126 #define ATTN_HARD_WIRED_MASK 0xff00
2127 #define ATTENTION_ID 4
2130 /* stuff added to make the code fit 80Col */
2132 #define BNX2X_PMF_LINK_ASSERT \
2133 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2135 #define BNX2X_MC_ASSERT_BITS \
2136 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2137 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2138 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2139 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2141 #define BNX2X_MCP_ASSERT \
2142 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2144 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2145 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2146 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2147 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2148 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2149 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2150 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2152 #define HW_INTERRUT_ASSERT_SET_0 \
2153 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2154 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2155 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2156 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2157 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2158 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2159 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2160 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2161 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2162 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2163 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2164 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2165 #define HW_INTERRUT_ASSERT_SET_1 \
2166 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2167 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2168 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2169 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2170 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2171 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2172 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2173 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2174 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2175 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2176 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2177 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2178 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2179 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2180 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2181 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2182 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2183 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2184 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2185 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2186 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2187 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2188 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2189 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2190 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2191 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2192 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2193 #define HW_INTERRUT_ASSERT_SET_2 \
2194 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2195 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2196 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2197 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2198 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2199 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2200 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2201 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2202 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2203 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2204 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2205 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2206 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2208 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2209 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2210 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2211 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2213 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2214 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2216 #define MULTI_MASK 0x7f
2219 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2220 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2221 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2222 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2224 #define DEF_USB_IGU_INDEX_OFF \
2225 offsetof(struct cstorm_def_status_block_u, igu_index)
2226 #define DEF_CSB_IGU_INDEX_OFF \
2227 offsetof(struct cstorm_def_status_block_c, igu_index)
2228 #define DEF_XSB_IGU_INDEX_OFF \
2229 offsetof(struct xstorm_def_status_block, igu_index)
2230 #define DEF_TSB_IGU_INDEX_OFF \
2231 offsetof(struct tstorm_def_status_block, igu_index)
2233 #define DEF_USB_SEGMENT_OFF \
2234 offsetof(struct cstorm_def_status_block_u, segment)
2235 #define DEF_CSB_SEGMENT_OFF \
2236 offsetof(struct cstorm_def_status_block_c, segment)
2237 #define DEF_XSB_SEGMENT_OFF \
2238 offsetof(struct xstorm_def_status_block, segment)
2239 #define DEF_TSB_SEGMENT_OFF \
2240 offsetof(struct tstorm_def_status_block, segment)
2242 #define BNX2X_SP_DSB_INDEX \
2243 (&bp->def_status_blk->sp_sb.\
2244 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2246 #define SET_FLAG(value, mask, flag) \
2248 (value) &= ~(mask);\
2249 (value) |= ((flag) << (mask##_SHIFT));\
2252 #define GET_FLAG(value, mask) \
2253 (((value) & (mask)) >> (mask##_SHIFT))
2255 #define GET_FIELD(value, fname) \
2256 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2258 #define CAM_IS_INVALID(x) \
2259 (GET_FLAG(x.flags, \
2260 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2261 (T_ETH_MAC_COMMAND_INVALIDATE))
2263 /* Number of u32 elements in MC hash array */
2264 #define MC_HASH_SIZE 8
2265 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2266 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2269 #ifndef PXP2_REG_PXP2_INT_STS
2270 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2273 #ifndef ETH_MAX_RX_CLIENTS_E2
2274 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2277 #define BNX2X_VPD_LEN 128
2278 #define VENDOR_ID_LEN 4
2280 #define VF_ACQUIRE_THRESH 3
2281 #define VF_ACQUIRE_MAC_FILTERS 1
2282 #define VF_ACQUIRE_MC_FILTERS 10
2284 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2285 (!((me_reg) & ME_REG_VF_ERR)))
2286 int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code);
2287 /* Congestion management fairness mode */
2288 #define CMNG_FNS_NONE 0
2289 #define CMNG_FNS_MINMAX 1
2291 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2292 #define HC_SEG_ACCESS_ATTN 4
2293 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2295 static const u32 dmae_reg_go_c[] = {
2296 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2297 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2298 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2299 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2302 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2303 void bnx2x_notify_link_changed(struct bnx2x *bp);
2306 #define BNX2X_MF_SD_PROTOCOL(bp) \
2307 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2309 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2310 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2312 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2313 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2315 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2316 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2318 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \
2319 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2321 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
2322 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2323 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2324 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2333 #endif /* bnx2x.h */