1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
17 #include <linux/pci.h>
18 #include <linux/netdevice.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/types.h>
21 #include <linux/pci_regs.h>
23 /* compilation time flags */
25 /* define this to make the driver freeze on error to allow getting debug info
26 * (you will need to reboot afterwards) */
27 /* #define BNX2X_STOP_ON_ERROR */
29 #define DRV_MODULE_VERSION "1.78.17-0"
30 #define DRV_MODULE_RELDATE "2013/04/11"
31 #define BNX2X_BC_VER 0x040200
33 #if defined(CONFIG_DCB)
37 #include "bnx2x_hsi.h"
39 #include "../cnic_if.h"
41 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
43 #include <linux/mdio.h>
45 #include "bnx2x_reg.h"
46 #include "bnx2x_fw_defs.h"
47 #include "bnx2x_mfw_req.h"
48 #include "bnx2x_link.h"
50 #include "bnx2x_dcb.h"
51 #include "bnx2x_stats.h"
52 #include "bnx2x_vfpf.h"
60 /* error/debug prints */
62 #define DRV_MODULE_NAME "bnx2x"
64 /* for messages that are currently off */
65 #define BNX2X_MSG_OFF 0x0
66 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
67 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
68 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
69 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
70 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
71 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
72 #define BNX2X_MSG_IOV 0x0800000
73 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
74 #define BNX2X_MSG_ETHTOOL 0x4000000
75 #define BNX2X_MSG_DCB 0x8000000
77 /* regular debug print */
78 #define DP(__mask, fmt, ...) \
80 if (unlikely(bp->msg_enable & (__mask))) \
81 pr_notice("[%s:%d(%s)]" fmt, \
83 bp->dev ? (bp->dev->name) : "?", \
87 #define DP_CONT(__mask, fmt, ...) \
89 if (unlikely(bp->msg_enable & (__mask))) \
90 pr_cont(fmt, ##__VA_ARGS__); \
93 /* errors debug print */
94 #define BNX2X_DBG_ERR(fmt, ...) \
96 if (unlikely(netif_msg_probe(bp))) \
97 pr_err("[%s:%d(%s)]" fmt, \
99 bp->dev ? (bp->dev->name) : "?", \
103 /* for errors (never masked) */
104 #define BNX2X_ERR(fmt, ...) \
106 pr_err("[%s:%d(%s)]" fmt, \
107 __func__, __LINE__, \
108 bp->dev ? (bp->dev->name) : "?", \
112 #define BNX2X_ERROR(fmt, ...) \
113 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
115 /* before we have a dev->name use dev_info() */
116 #define BNX2X_DEV_INFO(fmt, ...) \
118 if (unlikely(netif_msg_probe(bp))) \
119 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
123 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
124 #ifdef BNX2X_STOP_ON_ERROR
125 #define bnx2x_panic() \
128 BNX2X_ERR("driver assert\n"); \
129 bnx2x_panic_dump(bp, true); \
132 #define bnx2x_panic() \
135 BNX2X_ERR("driver assert\n"); \
136 bnx2x_panic_dump(bp, false); \
140 #define bnx2x_mc_addr(ha) ((ha)->addr)
141 #define bnx2x_uc_addr(ha) ((ha)->addr)
143 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff))
144 #define U64_HI(x) ((u32)(((u64)(x)) >> 32))
145 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
147 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
149 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
150 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
151 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
153 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
154 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
155 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
157 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
158 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
160 #define REG_RD_DMAE(bp, offset, valp, len32) \
162 bnx2x_read_dmae(bp, offset, len32);\
163 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
166 #define REG_WR_DMAE(bp, offset, valp, len32) \
168 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
169 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
173 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
174 REG_WR_DMAE(bp, offset, valp, len32)
176 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
178 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
179 bnx2x_write_big_buf_wb(bp, addr, len32); \
182 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
183 offsetof(struct shmem_region, field))
184 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
185 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
187 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
188 offsetof(struct shmem2_region, field))
189 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
190 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
191 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
192 offsetof(struct mf_cfg, field))
193 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
194 offsetof(struct mf2_cfg, field))
196 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
197 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
198 MF_CFG_ADDR(bp, field), (val))
199 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
201 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
202 (SHMEM2_RD((bp), size) > \
203 offsetof(struct shmem2_region, field)))
205 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
206 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
210 /* General SP events - stats query, cfc delete, etc */
211 #define HC_SP_INDEX_ETH_DEF_CONS 3
214 #define HC_SP_INDEX_EQ_CONS 7
216 /* FCoE L2 connection completions */
217 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
218 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
220 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
221 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
223 /* Special clients parameters */
227 #define BNX2X_FCOE_L2_RX_INDEX \
228 (&bp->def_status_blk->sp_sb.\
229 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
231 #define BNX2X_FCOE_L2_TX_INDEX \
232 (&bp->def_status_blk->sp_sb.\
233 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
237 * CLIDs below is a CLID for func 0, then the CLID for other
238 * functions will be calculated by the formula:
240 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
244 BNX2X_ISCSI_ETH_CL_ID_IDX,
245 BNX2X_FCOE_ETH_CL_ID_IDX,
246 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
249 #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\
252 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
254 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
256 #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
257 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
258 #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
259 #define FCOE_INIT(bp) ((bp)->fcoe_init)
261 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
262 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
267 /* defines for multiple tx priority indices */
268 #define FIRST_TX_ONLY_COS_INDEX 1
269 #define FIRST_TX_COS_INDEX 0
271 /* rules for calculating the cids of tx-only connections */
272 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
273 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
274 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
276 /* fp index inside class of service range */
277 #define FP_COS_TO_TXQ(fp, cos, bp) \
278 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
280 /* Indexes for transmission queues array:
281 * txdata for RSS i CoS j is at location i + (j * num of RSS)
282 * txdata for FCoE (if exist) is at location max cos * num of RSS
283 * txdata for FWD (if exist) is one location after FCoE
284 * txdata for OOO (if exist) is one location after FWD
291 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
292 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
296 * This driver uses new build_skb() API :
297 * RX ring buffer contains pointer to kmalloc() data only,
298 * skb are built only after Hardware filled the frame.
302 DEFINE_DMA_UNMAP_ADDR(mapping);
309 /* Set on the first BD descriptor when there is a split BD */
310 #define BNX2X_TSO_SPLIT_BD (1<<0)
315 DEFINE_DMA_UNMAP_ADDR(mapping);
319 struct doorbell_set_prod data;
323 /* dropless fc FW/HW related params */
324 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
325 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
326 ETH_MAX_AGGREGATION_QUEUES_E1 :\
327 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
328 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
329 #define FW_PREFETCH_CNT 16
330 #define DROPLESS_FC_HEADROOM 100
333 #define BCM_PAGE_SHIFT 12
334 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
335 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
336 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
338 #define PAGES_PER_SGE_SHIFT 0
339 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
340 #define SGE_PAGE_SIZE PAGE_SIZE
341 #define SGE_PAGE_SHIFT PAGE_SHIFT
342 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
343 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
344 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
347 /* SGE ring related macros */
348 #define NUM_RX_SGE_PAGES 2
349 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
350 #define NEXT_PAGE_SGE_DESC_CNT 2
351 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
352 /* RX_SGE_CNT is promised to be a power of 2 */
353 #define RX_SGE_MASK (RX_SGE_CNT - 1)
354 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
355 #define MAX_RX_SGE (NUM_RX_SGE - 1)
356 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
357 (MAX_RX_SGE_CNT - 1)) ? \
358 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
360 #define RX_SGE(x) ((x) & MAX_RX_SGE)
363 * Number of required SGEs is the sum of two:
364 * 1. Number of possible opened aggregations (next packet for
365 * these aggregations will probably consume SGE immediately)
366 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
367 * after placement on BD for new TPA aggregation)
369 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
371 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
372 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
373 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
375 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
376 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
377 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
379 /* Manipulate a bit vector defined as an array of u64 */
381 /* Number of bits in one sge_mask array element */
382 #define BIT_VEC64_ELEM_SZ 64
383 #define BIT_VEC64_ELEM_SHIFT 6
384 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
386 #define __BIT_VEC64_SET_BIT(el, bit) \
388 el = ((el) | ((u64)0x1 << (bit))); \
391 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
393 el = ((el) & (~((u64)0x1 << (bit)))); \
396 #define BIT_VEC64_SET_BIT(vec64, idx) \
397 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
398 (idx) & BIT_VEC64_ELEM_MASK)
400 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
401 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
402 (idx) & BIT_VEC64_ELEM_MASK)
404 #define BIT_VEC64_TEST_BIT(vec64, idx) \
405 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
406 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
408 /* Creates a bitmask of all ones in less significant bits.
409 idx - index of the most significant bit in the created mask */
410 #define BIT_VEC64_ONES_MASK(idx) \
411 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
412 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
414 /*******************************************************/
416 /* Number of u64 elements in SGE mask array */
417 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
418 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
419 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
421 union host_hc_status_block {
422 /* pointer to fp status block e1x */
423 struct host_hc_status_block_e1x *e1x_sb;
424 /* pointer to fp status block e2 */
425 struct host_hc_status_block_e2 *e2_sb;
428 struct bnx2x_agg_info {
430 * First aggregation buffer is a data buffer, the following - are pages.
431 * We will preallocate the data buffer for each aggregation when
432 * we open the interface and will replace the BD at the consumer
433 * with this one when we receive the TPA_START CQE in order to
434 * keep the Rx BD ring consistent.
436 struct sw_rx_bd first_buf;
438 #define BNX2X_TPA_START 1
439 #define BNX2X_TPA_STOP 2
440 #define BNX2X_TPA_ERROR 3
451 #define Q_STATS_OFFSET32(stat_name) \
452 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
454 struct bnx2x_fp_txdata {
456 struct sw_tx_bd *tx_buf_ring;
458 union eth_tx_bd_types *tx_desc_ring;
459 dma_addr_t tx_desc_mapping;
470 unsigned long tx_pkt;
475 struct bnx2x_fastpath *parent_fp;
479 enum bnx2x_tpa_mode_t {
484 struct bnx2x_fastpath {
485 struct bnx2x *bp; /* parent */
487 struct napi_struct napi;
488 union host_hc_status_block status_blk;
489 /* chip independent shortcuts into sb structure */
490 __le16 *sb_index_values;
491 __le16 *sb_running_index;
492 /* chip independent shortcut into rx_prods_offset memory */
493 u32 ustorm_rx_prods_offset;
496 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
497 dma_addr_t status_blk_mapping;
499 enum bnx2x_tpa_mode_t mode;
501 u8 max_cos; /* actual number of active tx coses */
502 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
504 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
505 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
507 struct eth_rx_bd *rx_desc_ring;
508 dma_addr_t rx_desc_mapping;
510 union eth_rx_cqe *rx_comp_ring;
511 dma_addr_t rx_comp_mapping;
514 struct eth_rx_sge *rx_sge_ring;
515 dma_addr_t rx_sge_mapping;
517 u64 sge_mask[RX_SGE_MASK_LEN];
523 u8 index; /* number in fp array */
524 u8 rx_queue; /* index for skb_record */
525 u8 cl_id; /* eth client id */
527 u8 fw_sb_id; /* status block number in FW */
528 u8 igu_sb_id; /* status block number in HW */
535 /* The last maximal completed SGE */
538 unsigned long rx_pkt,
542 struct bnx2x_agg_info *tpa_info;
544 #ifdef BNX2X_STOP_ON_ERROR
547 /* The size is calculated using the following:
548 sizeof name field from netdev structure +
550 4 (for the digits and to make it DWORD aligned) */
551 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
552 char name[FP_NAME_SIZE];
555 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
556 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
557 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
558 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
560 /* Use 2500 as a mini-jumbo MTU for FCoE */
561 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
563 #define FCOE_IDX_OFFSET 0
565 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
567 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
568 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
569 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
570 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
571 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
572 txdata_ptr[FIRST_TX_COS_INDEX] \
575 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
576 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
577 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
580 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
581 #define RX_COPY_THRESH 92
583 #define NUM_TX_RINGS 16
584 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
585 #define NEXT_PAGE_TX_DESC_CNT 1
586 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
587 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
588 #define MAX_TX_BD (NUM_TX_BD - 1)
589 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
590 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
591 (MAX_TX_DESC_CNT - 1)) ? \
592 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
594 #define TX_BD(x) ((x) & MAX_TX_BD)
595 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
597 /* number of NEXT_PAGE descriptors may be required during placement */
598 #define NEXT_CNT_PER_TX_PKT(bds) \
599 (((bds) + MAX_TX_DESC_CNT - 1) / \
600 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
601 /* max BDs per tx packet w/o next_pages:
602 * START_BD - describes packed
603 * START_BD(splitted) - includes unpaged data segment for GSO
604 * PARSING_BD - for TSO and CSUM data
605 * PARSING_BD2 - for encapsulation data
606 * Frag BDs - describes pages for frags
608 #define BDS_PER_TX_PKT 4
609 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
610 /* max BDs per tx packet including next pages */
611 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
612 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
614 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
615 #define NUM_RX_RINGS 8
616 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
617 #define NEXT_PAGE_RX_DESC_CNT 2
618 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
619 #define RX_DESC_MASK (RX_DESC_CNT - 1)
620 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
621 #define MAX_RX_BD (NUM_RX_BD - 1)
622 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
624 /* dropless fc calculations for BDs
626 * Number of BDs should as number of buffers in BRB:
627 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
628 * "next" elements on each page
630 #define NUM_BD_REQ BRB_SIZE(bp)
631 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
633 #define BD_TH_LO(bp) (NUM_BD_REQ + \
634 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
636 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
638 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
640 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
641 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
642 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
643 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
644 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
645 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
648 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
649 (MAX_RX_DESC_CNT - 1)) ? \
650 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
652 #define RX_BD(x) ((x) & MAX_RX_BD)
655 * As long as CQE is X times bigger than BD entry we have to allocate X times
656 * more pages for CQ ring in order to keep it balanced with BD ring
658 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
659 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
660 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
661 #define NEXT_PAGE_RCQ_DESC_CNT 1
662 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
663 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
664 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
665 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
666 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
667 (MAX_RCQ_DESC_CNT - 1)) ? \
668 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
670 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
672 /* dropless fc calculations for RCQs
674 * Number of RCQs should be as number of buffers in BRB:
675 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
676 * "next" elements on each page
678 #define NUM_RCQ_REQ BRB_SIZE(bp)
679 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
681 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
682 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
684 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
686 /* This is needed for determining of last_max */
687 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
688 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
690 #define BNX2X_SWCID_SHIFT 17
691 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
693 /* used on a CID received from the HW */
694 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
695 #define CQE_CMD(x) (le32_to_cpu(x) >> \
696 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
698 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
699 le32_to_cpu((bd)->addr_lo))
700 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
702 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
703 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
704 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
705 #error "Min DB doorbell stride is 8"
707 #define DPM_TRIGER_TYPE 0x40
708 #define DOORBELL(bp, cid, val) \
710 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
714 /* TX CSUM helpers */
715 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
717 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
720 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
723 #define XMIT_CSUM_V4 (1 << 0)
724 #define XMIT_CSUM_V6 (1 << 1)
725 #define XMIT_CSUM_TCP (1 << 2)
726 #define XMIT_GSO_V4 (1 << 3)
727 #define XMIT_GSO_V6 (1 << 4)
728 #define XMIT_CSUM_ENC_V4 (1 << 5)
729 #define XMIT_CSUM_ENC_V6 (1 << 6)
730 #define XMIT_GSO_ENC_V4 (1 << 7)
731 #define XMIT_GSO_ENC_V6 (1 << 8)
733 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
734 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
736 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
737 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
739 /* stuff added to make the code fit 80Col */
740 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
741 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
742 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
743 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
744 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
746 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
748 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
749 (((le16_to_cpu(flags) & \
750 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
751 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
752 == PRS_FLAG_OVERETH_IPV4)
753 #define BNX2X_RX_SUM_FIX(cqe) \
754 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
756 #define FP_USB_FUNC_OFF \
757 offsetof(struct cstorm_status_block_u, func)
758 #define FP_CSB_FUNC_OFF \
759 offsetof(struct cstorm_status_block_c, func)
761 #define HC_INDEX_ETH_RX_CQ_CONS 1
763 #define HC_INDEX_OOO_TX_CQ_CONS 4
765 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
767 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
769 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
771 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
773 #define BNX2X_RX_SB_INDEX \
774 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
776 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
778 #define BNX2X_TX_SB_INDEX_COS0 \
779 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
781 /* end of fast path */
785 struct bnx2x_common {
788 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
789 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
791 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
792 #define CHIP_NUM_57710 0x164e
793 #define CHIP_NUM_57711 0x164f
794 #define CHIP_NUM_57711E 0x1650
795 #define CHIP_NUM_57712 0x1662
796 #define CHIP_NUM_57712_MF 0x1663
797 #define CHIP_NUM_57712_VF 0x166f
798 #define CHIP_NUM_57713 0x1651
799 #define CHIP_NUM_57713E 0x1652
800 #define CHIP_NUM_57800 0x168a
801 #define CHIP_NUM_57800_MF 0x16a5
802 #define CHIP_NUM_57800_VF 0x16a9
803 #define CHIP_NUM_57810 0x168e
804 #define CHIP_NUM_57810_MF 0x16ae
805 #define CHIP_NUM_57810_VF 0x16af
806 #define CHIP_NUM_57811 0x163d
807 #define CHIP_NUM_57811_MF 0x163e
808 #define CHIP_NUM_57811_VF 0x163f
809 #define CHIP_NUM_57840_OBSOLETE 0x168d
810 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
811 #define CHIP_NUM_57840_4_10 0x16a1
812 #define CHIP_NUM_57840_2_20 0x16a2
813 #define CHIP_NUM_57840_MF 0x16a4
814 #define CHIP_NUM_57840_VF 0x16ad
815 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
816 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
817 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
818 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
819 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
820 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
821 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
822 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
823 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
824 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
825 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
826 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
827 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
828 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
829 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
830 #define CHIP_IS_57840(bp) \
831 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
832 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
833 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
834 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
835 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
836 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
837 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
839 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \
840 CHIP_IS_57811_MF(bp) || \
841 CHIP_IS_57811_VF(bp))
842 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
843 CHIP_IS_57712_MF(bp) || \
844 CHIP_IS_57712_VF(bp))
845 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
846 CHIP_IS_57800_MF(bp) || \
847 CHIP_IS_57800_VF(bp) || \
848 CHIP_IS_57810(bp) || \
849 CHIP_IS_57810_MF(bp) || \
850 CHIP_IS_57810_VF(bp) || \
851 CHIP_IS_57811xx(bp) || \
852 CHIP_IS_57840(bp) || \
853 CHIP_IS_57840_MF(bp) || \
854 CHIP_IS_57840_VF(bp))
855 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
856 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
857 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
859 #define CHIP_REV_SHIFT 12
860 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
861 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
862 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
863 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
864 /* assume maximum 5 revisions */
865 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
866 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
867 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
868 !(CHIP_REV_VAL(bp) & 0x00001000))
869 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
870 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
871 (CHIP_REV_VAL(bp) & 0x00001000))
873 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
874 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
876 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
877 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
878 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
879 (CHIP_REV_SHIFT + 1)) \
881 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
884 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
885 (CHIP_REV(bp) == CHIP_REV_Bx))
886 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
887 (CHIP_REV(bp) == CHIP_REV_Ax))
888 /* This define is used in two main places:
889 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher
890 * to nic-only mode or to offload mode. Offload mode is configured if either the
891 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
892 * registered for this port (which means that the user wants storage services).
893 * 2. During cnic-related load, to know if offload mode is already configured in
894 * the HW or needs to be configured.
895 * Since the transition from nic-mode to offload-mode in HW causes traffic
896 * corruption, nic-mode is configured only in ports on which storage services
897 * where never requested.
899 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
902 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
903 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
904 #define BNX2X_NVRAM_PAGE_SIZE 256
916 #define INT_BLOCK_HC 0
917 #define INT_BLOCK_IGU 1
918 #define INT_BLOCK_MODE_NORMAL 0
919 #define INT_BLOCK_MODE_BW_COMP 2
920 #define CHIP_INT_MODE_IS_NBC(bp) \
921 (!CHIP_IS_E1x(bp) && \
922 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
923 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
926 #define CHIP_4_PORT_MODE 0x0
927 #define CHIP_2_PORT_MODE 0x1
928 #define CHIP_PORT_MODE_NONE 0x2
929 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
930 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
935 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
936 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
937 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
939 #define MAX_IGU_ATTN_ACK_TO 100
947 u32 link_config[LINK_CONFIG_SIZE];
949 u32 supported[LINK_CONFIG_SIZE];
950 /* link settings - missing defines */
951 #define SUPPORTED_2500baseX_Full (1 << 15)
953 u32 advertising[LINK_CONFIG_SIZE];
954 /* link settings - missing defines */
955 #define ADVERTISED_2500baseX_Full (1 << 15)
959 /* used to synchronize phy accesses */
960 struct mutex phy_mutex;
964 struct nig_stats old_nig_stats;
969 #define STATS_OFFSET32(stat_name) \
970 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
974 /* slow path work-queue */
975 extern struct workqueue_struct *bnx2x_wq;
977 #define BNX2X_MAX_NUM_OF_VFS 64
978 #define BNX2X_VF_CID_WND 0
979 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
980 #define BNX2X_CLIENTS_PER_VF 1
981 #define BNX2X_FIRST_VF_CID 256
982 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
983 #define BNX2X_VF_ID_INVALID 0xFF
986 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
987 * control by the number of fast-path status blocks supported by the
988 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
989 * status block represents an independent interrupts context that can
990 * serve a regular L2 networking queue. However special L2 queues such
991 * as the FCoE queue do not require a FP-SB and other components like
992 * the CNIC may consume FP-SB reducing the number of possible L2 queues
994 * If the maximum number of FP-SB available is X then:
995 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
996 * regular L2 queues is Y=X-1
997 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
998 * c. If the FCoE L2 queue is supported the actual number of L2 queues
1000 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1001 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
1002 * FP interrupt context for the CNIC).
1003 * e. The number of HW context (CID count) is always X or X+1 if FCoE
1004 * L2 queue is supported. The cid for the FCoE L2 queue is always X.
1007 /* fast-path interrupt contexts E1x */
1008 #define FP_SB_MAX_E1x 16
1009 /* fast-path interrupt contexts E2 */
1010 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
1013 struct eth_context eth;
1017 /* CDU host DB constants */
1018 #define CDU_ILT_PAGE_SZ_HW 2
1019 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1020 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1022 #define CNIC_ISCSI_CID_MAX 256
1023 #define CNIC_FCOE_CID_MAX 2048
1024 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1025 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1027 #define QM_ILT_PAGE_SZ_HW 0
1028 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1029 #define QM_CID_ROUND 1024
1031 /* TM (timers) host DB constants */
1032 #define TM_ILT_PAGE_SZ_HW 0
1033 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1034 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
1035 #define TM_CONN_NUM 1024
1036 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1037 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1039 /* SRC (Searcher) host DB constants */
1040 #define SRC_ILT_PAGE_SZ_HW 0
1041 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1042 #define SRC_HASH_BITS 10
1043 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1044 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1045 #define SRC_T2_SZ SRC_ILT_SZ
1046 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1048 #define MAX_DMAE_C 8
1050 /* DMA memory not used in fastpath */
1051 struct bnx2x_slowpath {
1053 struct mac_configuration_cmd e1x;
1054 struct eth_classify_rules_ramrod_data e2;
1058 struct tstorm_eth_mac_filter_config e1x;
1059 struct eth_filter_rules_ramrod_data e2;
1063 struct mac_configuration_cmd e1;
1064 struct eth_multicast_rules_ramrod_data e2;
1067 struct eth_rss_update_ramrod_data rss_rdata;
1069 /* Queue State related ramrods are always sent under rtnl_lock */
1071 struct client_init_ramrod_data init_data;
1072 struct client_update_ramrod_data update_data;
1076 struct function_start_data func_start;
1077 /* pfc configuration for DCBX ramrod */
1078 struct flow_control_configuration pfc_config;
1081 /* afex ramrod can not be a part of func_rdata union because these
1082 * events might arrive in parallel to other events from func_rdata.
1083 * Therefore, if they would have been defined in the same union,
1084 * data can get corrupted.
1086 struct afex_vif_list_ramrod_data func_afex_rdata;
1088 /* used by dmae command executer */
1089 struct dmae_command dmae[MAX_DMAE_C];
1092 union mac_stats mac_stats;
1093 struct nig_stats nig_stats;
1094 struct host_port_stats port_stats;
1095 struct host_func_stats func_stats;
1100 union drv_info_to_mcp drv_info_to_mcp;
1103 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1104 #define bnx2x_sp_mapping(bp, var) \
1105 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1107 /* attn group wiring */
1108 #define MAX_DYNAMIC_ATTN_GRPS 8
1123 union cdu_context *vcxt;
1124 dma_addr_t cxt_mapping;
1133 enum bnx2x_recovery_state {
1134 BNX2X_RECOVERY_DONE,
1135 BNX2X_RECOVERY_INIT,
1136 BNX2X_RECOVERY_WAIT,
1137 BNX2X_RECOVERY_FAILED,
1138 BNX2X_RECOVERY_NIC_LOADING
1142 * Event queue (EQ or event ring) MC hsi
1143 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1145 #define NUM_EQ_PAGES 1
1146 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1147 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1148 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1149 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1150 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1152 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1153 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1154 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1156 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1157 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1159 #define BNX2X_EQ_INDEX \
1160 (&bp->def_status_blk->sp_sb.\
1161 index_values[HC_SP_INDEX_EQ_CONS])
1163 /* This is a data that will be used to create a link report message.
1164 * We will keep the data used for the last link report in order
1165 * to prevent reporting the same link parameters twice.
1167 struct bnx2x_link_report_data {
1168 u16 line_speed; /* Effective line speed */
1169 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1173 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1174 BNX2X_LINK_REPORT_LINK_DOWN,
1175 BNX2X_LINK_REPORT_RX_FC_ON,
1176 BNX2X_LINK_REPORT_TX_FC_ON,
1180 BNX2X_PORT_QUERY_IDX,
1182 BNX2X_FCOE_QUERY_IDX,
1183 BNX2X_FIRST_QUEUE_QUERY_IDX,
1186 struct bnx2x_fw_stats_req {
1187 struct stats_query_header hdr;
1188 struct stats_query_entry query[FP_SB_MAX_E1x+
1189 BNX2X_FIRST_QUEUE_QUERY_IDX];
1192 struct bnx2x_fw_stats_data {
1193 struct stats_counter storm_counters;
1194 struct per_port_stats port;
1195 struct per_pf_stats pf;
1196 struct fcoe_statistics_params fcoe;
1197 struct per_queue_stats queue_stats[1];
1200 /* Public slow path states */
1202 BNX2X_SP_RTNL_SETUP_TC,
1203 BNX2X_SP_RTNL_TX_TIMEOUT,
1204 BNX2X_SP_RTNL_FAN_FAILURE,
1205 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1206 BNX2X_SP_RTNL_ENABLE_SRIOV,
1207 BNX2X_SP_RTNL_VFPF_MCAST,
1208 BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
1209 BNX2X_SP_RTNL_HYPERVISOR_VLAN,
1212 struct bnx2x_prev_path_list {
1213 struct list_head list;
1221 struct bnx2x_sp_objs {
1223 struct bnx2x_vlan_mac_obj mac_obj;
1225 /* Queue State object */
1226 struct bnx2x_queue_sp_obj q_obj;
1229 struct bnx2x_fp_stats {
1230 struct tstorm_per_queue_stats old_tclient;
1231 struct ustorm_per_queue_stats old_uclient;
1232 struct xstorm_per_queue_stats old_xclient;
1233 struct bnx2x_eth_q_stats eth_q_stats;
1234 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1238 /* Fields used in the tx and intr/napi performance paths
1239 * are grouped together in the beginning of the structure
1241 struct bnx2x_fastpath *fp;
1242 struct bnx2x_sp_objs *sp_objs;
1243 struct bnx2x_fp_stats *fp_stats;
1244 struct bnx2x_fp_txdata *bnx2x_txq;
1245 void __iomem *regview;
1246 void __iomem *doorbells;
1249 u8 pf_num; /* absolute PF number */
1250 u8 pfid; /* per-path PF number */
1251 int base_fw_ndsb; /**/
1252 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1253 #define BP_PORT(bp) (bp->pfid & 1)
1254 #define BP_FUNC(bp) (bp->pfid)
1255 #define BP_ABS_FUNC(bp) (bp->pf_num)
1256 #define BP_VN(bp) ((bp)->pfid >> 1)
1257 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1258 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1259 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1260 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1261 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1263 #ifdef CONFIG_BNX2X_SRIOV
1264 /* protects vf2pf mailbox from simultaneous access */
1265 struct mutex vf2pf_mutex;
1266 /* vf pf channel mailbox contains request and response buffers */
1267 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1268 dma_addr_t vf2pf_mbox_mapping;
1270 /* we set aside a copy of the acquire response */
1271 struct pfvf_acquire_resp_tlv acquire_resp;
1273 /* bulletin board for messages from pf to vf */
1274 union pf_vf_bulletin *pf2vf_bulletin;
1275 dma_addr_t pf2vf_bulletin_mapping;
1277 struct pf_vf_bulletin_content old_bulletin;
1279 u16 requested_nr_virtfn;
1280 #endif /* CONFIG_BNX2X_SRIOV */
1282 struct net_device *dev;
1283 struct pci_dev *pdev;
1285 const struct iro *iro_arr;
1286 #define IRO (bp->iro_arr)
1288 enum bnx2x_recovery_state recovery_state;
1290 struct msix_entry *msix_table;
1294 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1295 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1296 #define ETH_MIN_PACKET_SIZE 60
1297 #define ETH_MAX_PACKET_SIZE 1500
1298 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1299 /* TCP with Timestamp Option (32) + IPv6 (40) */
1300 #define ETH_MAX_TPA_HEADER_SIZE 72
1302 /* Max supported alignment is 256 (8 shift) */
1303 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1305 /* FW uses 2 Cache lines Alignment for start packet and size
1307 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1308 * at the end of skb->data, to avoid wasting a full cache line.
1309 * This reduces memory use (skb->truesize).
1311 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1313 #define BNX2X_FW_RX_ALIGN_END \
1314 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1315 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1317 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1319 struct host_sp_status_block *def_status_blk;
1320 #define DEF_SB_IGU_ID 16
1321 #define DEF_SB_ID HC_SP_SB_ID
1325 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1327 /* slow path ring */
1328 struct eth_spe *spq;
1329 dma_addr_t spq_mapping;
1331 struct eth_spe *spq_prod_bd;
1332 struct eth_spe *spq_last_bd;
1333 __le16 *dsb_sp_prod;
1334 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1335 /* used to synchronize spq accesses */
1336 spinlock_t spq_lock;
1339 union event_ring_elem *eq_ring;
1340 dma_addr_t eq_mapping;
1344 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1346 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1348 /* Counter for completed statistics ramrods */
1351 /* End of fields used in the performance code paths */
1357 #define PCIX_FLAG (1 << 0)
1358 #define PCI_32BIT_FLAG (1 << 1)
1359 #define ONE_PORT_FLAG (1 << 2)
1360 #define NO_WOL_FLAG (1 << 3)
1361 #define USING_DAC_FLAG (1 << 4)
1362 #define USING_MSIX_FLAG (1 << 5)
1363 #define USING_MSI_FLAG (1 << 6)
1364 #define DISABLE_MSI_FLAG (1 << 7)
1365 #define TPA_ENABLE_FLAG (1 << 8)
1366 #define NO_MCP_FLAG (1 << 9)
1367 #define GRO_ENABLE_FLAG (1 << 10)
1368 #define MF_FUNC_DIS (1 << 11)
1369 #define OWN_CNIC_IRQ (1 << 12)
1370 #define NO_ISCSI_OOO_FLAG (1 << 13)
1371 #define NO_ISCSI_FLAG (1 << 14)
1372 #define NO_FCOE_FLAG (1 << 15)
1373 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1374 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1375 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1376 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1377 #define IS_VF_FLAG (1 << 22)
1379 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
1381 #ifdef CONFIG_BNX2X_SRIOV
1382 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1383 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
1385 #define IS_VF(bp) false
1386 #define IS_PF(bp) true
1389 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1390 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1391 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1396 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1398 /* Flag that indicates that we can start looking for FCoE L2 queue
1399 * completions in the default status block.
1406 struct delayed_work sp_task;
1407 atomic_t interrupt_occurred;
1408 struct delayed_work sp_rtnl_task;
1410 struct delayed_work period_task;
1411 struct timer_list timer;
1412 int current_interval;
1415 u16 fw_drv_pulse_wr_seq;
1418 struct link_params link_params;
1419 struct link_vars link_vars;
1421 struct bnx2x_link_report_data last_reported_link;
1423 struct mdio_if_info mdio;
1425 struct bnx2x_common common;
1426 struct bnx2x_port port;
1428 struct cmng_init cmng;
1430 u32 mf_config[E1HVN_MAX];
1432 u32 path_has_ovlan; /* E3 */
1435 #define IS_MF(bp) (bp->mf_mode != 0)
1436 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1437 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1438 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1444 u16 tx_quick_cons_trip_int;
1445 u16 tx_quick_cons_trip;
1449 u16 rx_quick_cons_trip_int;
1450 u16 rx_quick_cons_trip;
1453 /* Maximal coalescing timeout in us */
1454 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1459 #define BNX2X_STATE_CLOSED 0
1460 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1461 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1462 #define BNX2X_STATE_OPEN 0x3000
1463 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1464 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1466 #define BNX2X_STATE_DIAG 0xe000
1467 #define BNX2X_STATE_ERROR 0xf000
1469 #define BNX2X_MAX_PRIORITY 8
1470 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1471 #define BNX2X_MAX_COS 3
1472 #define BNX2X_MAX_TX_COS 2
1474 uint num_ethernet_queues;
1475 uint num_cnic_queues;
1476 int num_napi_queues;
1480 #define BNX2X_RX_MODE_NONE 0
1481 #define BNX2X_RX_MODE_NORMAL 1
1482 #define BNX2X_RX_MODE_ALLMULTI 2
1483 #define BNX2X_RX_MODE_PROMISC 3
1484 #define BNX2X_MAX_MULTICAST 64
1489 u8 min_msix_vec_cnt;
1492 dma_addr_t def_status_blk_mapping;
1494 struct bnx2x_slowpath *slowpath;
1495 dma_addr_t slowpath_mapping;
1497 /* Total number of FW statistics requests */
1501 * This is a memory buffer that will contain both statistics
1502 * ramrod request and data.
1505 dma_addr_t fw_stats_mapping;
1508 * FW statistics request shortcut (points at the
1509 * beginning of fw_stats buffer).
1511 struct bnx2x_fw_stats_req *fw_stats_req;
1512 dma_addr_t fw_stats_req_mapping;
1513 int fw_stats_req_sz;
1516 * FW statistics data shortcut (points at the beginning of
1517 * fw_stats buffer + fw_stats_req_sz).
1519 struct bnx2x_fw_stats_data *fw_stats_data;
1520 dma_addr_t fw_stats_data_mapping;
1521 int fw_stats_data_sz;
1523 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1524 * context size we need 8 ILT entries.
1526 #define ILT_MAX_L2_LINES 8
1527 struct hw_context context[ILT_MAX_L2_LINES];
1529 struct bnx2x_ilt *ilt;
1530 #define BP_ILT(bp) ((bp)->ilt)
1531 #define ILT_MAX_LINES 256
1533 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1536 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1539 * Maximum CID count that might be required by the bnx2x:
1540 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1542 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1543 + 2 * CNIC_SUPPORT(bp))
1544 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1545 + 2 * CNIC_SUPPORT(bp))
1546 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1554 dma_addr_t t2_mapping;
1555 struct cnic_ops __rcu *cnic_ops;
1558 struct cnic_eth_dev cnic_eth_dev;
1559 union host_hc_status_block cnic_sb;
1560 dma_addr_t cnic_sb_mapping;
1561 struct eth_spe *cnic_kwq;
1562 struct eth_spe *cnic_kwq_prod;
1563 struct eth_spe *cnic_kwq_cons;
1564 struct eth_spe *cnic_kwq_last;
1565 u16 cnic_kwq_pending;
1566 u16 cnic_spq_pending;
1567 u8 fip_mac[ETH_ALEN];
1568 struct mutex cnic_mutex;
1569 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1571 /* Start index of the "special" (CNIC related) L2 clients */
1575 /* used to synchronize dmae accesses */
1576 spinlock_t dmae_lock;
1578 /* used to protect the FW mail box */
1579 struct mutex fw_mb_mutex;
1581 /* used to synchronize stats collecting */
1584 /* used for synchronization of concurrent threads statistics handling */
1585 spinlock_t stats_lock;
1587 /* used by dmae command loader */
1588 struct dmae_command stats_dmae;
1592 struct bnx2x_eth_stats eth_stats;
1593 struct host_func_stats func_stats;
1594 struct bnx2x_eth_stats_old eth_stats_old;
1595 struct bnx2x_net_stats_old net_stats_old;
1596 struct bnx2x_fw_port_stats_old fw_stats_old;
1599 struct z_stream_s *strm;
1601 dma_addr_t gunzip_mapping;
1603 #define FW_BUF_SIZE 0x8000
1604 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1605 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1606 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1608 struct raw_op *init_ops;
1609 /* Init blocks offsets inside init_ops */
1610 u16 *init_ops_offsets;
1611 /* Data blob - has 32 bit granularity */
1613 u32 init_mode_flags;
1614 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1615 /* Zipped PRAM blobs - raw data */
1616 const u8 *tsem_int_table_data;
1617 const u8 *tsem_pram_data;
1618 const u8 *usem_int_table_data;
1619 const u8 *usem_pram_data;
1620 const u8 *xsem_int_table_data;
1621 const u8 *xsem_pram_data;
1622 const u8 *csem_int_table_data;
1623 const u8 *csem_pram_data;
1624 #define INIT_OPS(bp) (bp->init_ops)
1625 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1626 #define INIT_DATA(bp) (bp->init_data)
1627 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1628 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1629 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1630 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1631 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1632 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1633 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1634 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1636 #define PHY_FW_VER_LEN 20
1638 const struct firmware *firmware;
1640 struct bnx2x_vfdb *vfdb;
1641 #define IS_SRIOV(bp) ((bp)->vfdb)
1643 /* DCB support on/off */
1645 #define BNX2X_DCB_STATE_OFF 0
1646 #define BNX2X_DCB_STATE_ON 1
1648 /* DCBX engine mode */
1650 #define BNX2X_DCBX_ENABLED_OFF 0
1651 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1652 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1653 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1655 bool dcbx_mode_uset;
1657 struct bnx2x_config_dcbx_params dcbx_config_params;
1658 struct bnx2x_dcbx_port_params dcbx_port_params;
1661 /* CAM credit pools */
1663 /* used only in sriov */
1664 struct bnx2x_credit_pool_obj vlans_pool;
1666 struct bnx2x_credit_pool_obj macs_pool;
1668 /* RX_MODE object */
1669 struct bnx2x_rx_mode_obj rx_mode_obj;
1672 struct bnx2x_mcast_obj mcast_obj;
1674 /* RSS configuration object */
1675 struct bnx2x_rss_config_obj rss_conf_obj;
1677 /* Function State controlling object */
1678 struct bnx2x_func_sp_obj func_obj;
1680 unsigned long sp_state;
1682 /* operation indication for the sp_rtnl task */
1683 unsigned long sp_rtnl_state;
1685 /* DCBX Negotiation results */
1686 struct dcbx_features dcbx_local_feat;
1690 struct dcbx_features dcbx_remote_feat;
1691 u32 dcbx_remote_flags;
1693 /* AFEX: store default vlan used */
1694 int afex_def_vlan_tag;
1695 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1698 /* multiple tx classes of service */
1701 /* priority to cos mapping */
1705 u32 dump_preset_idx;
1708 /* Tx queues may be less or equal to Rx queues */
1709 extern int num_queues;
1710 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1711 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1712 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1713 (bp)->num_cnic_queues)
1714 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1716 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1718 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1719 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1721 #define RSS_IPV4_CAP_MASK \
1722 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1724 #define RSS_IPV4_TCP_CAP_MASK \
1725 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1727 #define RSS_IPV6_CAP_MASK \
1728 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1730 #define RSS_IPV6_TCP_CAP_MASK \
1731 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1733 /* func init flags */
1734 #define FUNC_FLG_RSS 0x0001
1735 #define FUNC_FLG_STATS 0x0002
1736 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1737 #define FUNC_FLG_TPA 0x0008
1738 #define FUNC_FLG_SPQ 0x0010
1739 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1741 struct bnx2x_func_init_params {
1743 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1744 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1747 u16 func_id; /* abs fid */
1749 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1752 #define for_each_cnic_queue(bp, var) \
1753 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1755 if (skip_queue(bp, var)) \
1759 #define for_each_eth_queue(bp, var) \
1760 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1762 #define for_each_nondefault_eth_queue(bp, var) \
1763 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1765 #define for_each_queue(bp, var) \
1766 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1767 if (skip_queue(bp, var)) \
1771 /* Skip forwarding FP */
1772 #define for_each_valid_rx_queue(bp, var) \
1774 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1775 BNX2X_NUM_ETH_QUEUES(bp)); \
1777 if (skip_rx_queue(bp, var)) \
1781 #define for_each_rx_queue_cnic(bp, var) \
1782 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1784 if (skip_rx_queue(bp, var)) \
1788 #define for_each_rx_queue(bp, var) \
1789 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1790 if (skip_rx_queue(bp, var)) \
1795 #define for_each_valid_tx_queue(bp, var) \
1797 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1798 BNX2X_NUM_ETH_QUEUES(bp)); \
1800 if (skip_tx_queue(bp, var)) \
1804 #define for_each_tx_queue_cnic(bp, var) \
1805 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1807 if (skip_tx_queue(bp, var)) \
1811 #define for_each_tx_queue(bp, var) \
1812 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1813 if (skip_tx_queue(bp, var)) \
1817 #define for_each_nondefault_queue(bp, var) \
1818 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1819 if (skip_queue(bp, var)) \
1823 #define for_each_cos_in_tx_queue(fp, var) \
1824 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1827 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1829 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1832 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1834 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1836 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1839 * bnx2x_set_mac_one - configure a single MAC address
1841 * @bp: driver handle
1842 * @mac: MAC to configure
1843 * @obj: MAC object handle
1844 * @set: if 'true' add a new MAC, otherwise - delete
1845 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1846 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1848 * Configures one MAC according to provided parameters or continues the
1849 * execution of previously scheduled commands if RAMROD_CONT is set in
1852 * Returns zero if operation has successfully completed, a positive value if the
1853 * operation has been successfully scheduled and a negative - if a requested
1854 * operations has failed.
1856 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1857 struct bnx2x_vlan_mac_obj *obj, bool set,
1858 int mac_type, unsigned long *ramrod_flags);
1860 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1862 * @bp: driver handle
1863 * @mac_obj: MAC object handle
1864 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1865 * @wait_for_comp: if 'true' block until completion
1867 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1869 * Returns zero if operation has successfully completed, a positive value if the
1870 * operation has been successfully scheduled and a negative - if a requested
1871 * operations has failed.
1873 int bnx2x_del_all_macs(struct bnx2x *bp,
1874 struct bnx2x_vlan_mac_obj *mac_obj,
1875 int mac_type, bool wait_for_comp);
1877 /* Init Function API */
1878 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1879 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
1880 u8 vf_valid, int fw_sb_id, int igu_sb_id);
1881 u32 bnx2x_get_pretend_reg(struct bnx2x *bp);
1882 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1883 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1884 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1885 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1886 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1888 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
1891 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1892 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1894 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1895 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1896 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1897 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1898 bool with_comp, u8 comp_type);
1900 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
1901 u8 src_type, u8 dst_type);
1902 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae);
1904 /* FLR related routines */
1905 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
1906 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
1907 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
1908 u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
1909 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1910 char *msg, u32 poll_cnt);
1912 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1913 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1914 u32 data_hi, u32 data_lo, int cmd_type);
1915 void bnx2x_update_coalesce(struct bnx2x *bp);
1916 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1918 bool bnx2x_port_after_undi(struct bnx2x *bp);
1920 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1926 val = REG_RD(bp, reg);
1927 if (val == expected)
1937 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
1940 #define BNX2X_ILT_ZALLOC(x, y, size) \
1941 x = dma_alloc_coherent(&bp->pdev->dev, size, y, \
1942 GFP_KERNEL | __GFP_ZERO)
1944 #define BNX2X_ILT_FREE(x, y, size) \
1947 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1953 #define ILOG2(x) (ilog2((x)))
1955 #define ILT_NUM_PAGE_ENTRIES (3072)
1956 /* In 57710/11 we use whole table since we have 8 func
1957 * In 57712 we have only 4 func, but use same size per func, then only half of
1960 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1962 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1964 * the phys address is shifted right 12 bits and has an added
1965 * 1=valid bit added to the 53rd bit
1966 * then since this is a wide register(TM)
1967 * we split it into two 32 bit writes
1969 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1970 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1972 /* load/unload mode */
1973 #define LOAD_NORMAL 0
1976 #define LOAD_LOOPBACK_EXT 3
1977 #define UNLOAD_NORMAL 0
1978 #define UNLOAD_CLOSE 1
1979 #define UNLOAD_RECOVERY 2
1981 /* DMAE command defines */
1982 #define DMAE_TIMEOUT -1
1983 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1984 #define DMAE_NOT_RDY -3
1985 #define DMAE_PCI_ERR_FLAG 0x80000000
1987 #define DMAE_SRC_PCI 0
1988 #define DMAE_SRC_GRC 1
1990 #define DMAE_DST_NONE 0
1991 #define DMAE_DST_PCI 1
1992 #define DMAE_DST_GRC 2
1994 #define DMAE_COMP_PCI 0
1995 #define DMAE_COMP_GRC 1
1997 /* E2 and onward - PCI error handling in the completion */
1999 #define DMAE_COMP_REGULAR 0
2000 #define DMAE_COM_SET_ERR 1
2002 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
2003 DMAE_COMMAND_SRC_SHIFT)
2004 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
2005 DMAE_COMMAND_SRC_SHIFT)
2007 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
2008 DMAE_COMMAND_DST_SHIFT)
2009 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
2010 DMAE_COMMAND_DST_SHIFT)
2012 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
2013 DMAE_COMMAND_C_DST_SHIFT)
2014 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
2015 DMAE_COMMAND_C_DST_SHIFT)
2017 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
2019 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2020 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2021 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2022 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2024 #define DMAE_CMD_PORT_0 0
2025 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2027 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
2028 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
2029 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
2031 #define DMAE_SRC_PF 0
2032 #define DMAE_SRC_VF 1
2034 #define DMAE_DST_PF 0
2035 #define DMAE_DST_VF 1
2037 #define DMAE_C_SRC 0
2038 #define DMAE_C_DST 1
2040 #define DMAE_LEN32_RD_MAX 0x80
2041 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2043 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
2047 #define MAX_DMAE_C_PER_PORT 8
2048 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2050 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2053 /* PCIE link and speed */
2054 #define PCICFG_LINK_WIDTH 0x1f00000
2055 #define PCICFG_LINK_WIDTH_SHIFT 20
2056 #define PCICFG_LINK_SPEED 0xf0000
2057 #define PCICFG_LINK_SPEED_SHIFT 16
2059 #define BNX2X_NUM_TESTS_SF 7
2060 #define BNX2X_NUM_TESTS_MF 3
2061 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2064 #define BNX2X_PHY_LOOPBACK 0
2065 #define BNX2X_MAC_LOOPBACK 1
2066 #define BNX2X_EXT_LOOPBACK 2
2067 #define BNX2X_PHY_LOOPBACK_FAILED 1
2068 #define BNX2X_MAC_LOOPBACK_FAILED 2
2069 #define BNX2X_EXT_LOOPBACK_FAILED 3
2070 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2071 BNX2X_PHY_LOOPBACK_FAILED)
2073 #define STROM_ASSERT_ARRAY_SIZE 50
2075 /* must be used on a CID before placing it on a HW ring */
2076 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
2077 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2080 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2081 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2084 #define MAX_SPQ_PENDING 8
2086 /* CMNG constants, as derived from system spec calculations */
2087 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2088 #define DEF_MIN_RATE 100
2089 /* resolution of the rate shaping timer - 400 usec */
2090 #define RS_PERIODIC_TIMEOUT_USEC 400
2091 /* number of bytes in single QM arbitration cycle -
2092 * coefficient for calculating the fairness timer */
2093 #define QM_ARB_BYTES 160000
2094 /* resolution of Min algorithm 1:100 */
2096 /* how many bytes above threshold for the minimal credit of Min algorithm*/
2097 #define MIN_ABOVE_THRESH 32768
2098 /* Fairness algorithm integration time coefficient -
2099 * for calculating the actual Tfair */
2100 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2101 /* Memory of fairness algorithm . 2 cycles */
2104 #define ATTN_NIG_FOR_FUNC (1L << 8)
2105 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2106 #define GPIO_2_FUNC (1L << 10)
2107 #define GPIO_3_FUNC (1L << 11)
2108 #define GPIO_4_FUNC (1L << 12)
2109 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2110 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2111 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2112 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2113 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2114 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2116 #define ATTN_HARD_WIRED_MASK 0xff00
2117 #define ATTENTION_ID 4
2119 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \
2120 IS_MF_FCOE_AFEX(bp))
2122 /* stuff added to make the code fit 80Col */
2124 #define BNX2X_PMF_LINK_ASSERT \
2125 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2127 #define BNX2X_MC_ASSERT_BITS \
2128 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2129 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2130 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2131 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2133 #define BNX2X_MCP_ASSERT \
2134 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2136 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2137 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2138 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2139 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2140 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2141 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2142 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2144 #define HW_INTERRUT_ASSERT_SET_0 \
2145 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2146 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2147 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2148 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2149 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2150 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2151 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2152 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2153 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2154 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2155 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2156 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2157 #define HW_INTERRUT_ASSERT_SET_1 \
2158 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2159 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2160 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2161 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2162 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2163 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2164 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2165 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2166 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2167 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2168 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2169 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2170 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2171 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2172 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2173 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2174 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2175 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2176 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2177 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2178 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2179 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2180 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2181 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2182 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2183 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2184 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2185 #define HW_INTERRUT_ASSERT_SET_2 \
2186 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2187 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2188 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2189 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2190 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2191 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2192 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2193 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2194 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2195 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2196 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2197 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2198 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2200 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2201 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2202 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2203 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2205 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2206 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2208 #define MULTI_MASK 0x7f
2210 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2211 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2212 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2213 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2215 #define DEF_USB_IGU_INDEX_OFF \
2216 offsetof(struct cstorm_def_status_block_u, igu_index)
2217 #define DEF_CSB_IGU_INDEX_OFF \
2218 offsetof(struct cstorm_def_status_block_c, igu_index)
2219 #define DEF_XSB_IGU_INDEX_OFF \
2220 offsetof(struct xstorm_def_status_block, igu_index)
2221 #define DEF_TSB_IGU_INDEX_OFF \
2222 offsetof(struct tstorm_def_status_block, igu_index)
2224 #define DEF_USB_SEGMENT_OFF \
2225 offsetof(struct cstorm_def_status_block_u, segment)
2226 #define DEF_CSB_SEGMENT_OFF \
2227 offsetof(struct cstorm_def_status_block_c, segment)
2228 #define DEF_XSB_SEGMENT_OFF \
2229 offsetof(struct xstorm_def_status_block, segment)
2230 #define DEF_TSB_SEGMENT_OFF \
2231 offsetof(struct tstorm_def_status_block, segment)
2233 #define BNX2X_SP_DSB_INDEX \
2234 (&bp->def_status_blk->sp_sb.\
2235 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2237 #define CAM_IS_INVALID(x) \
2238 (GET_FLAG(x.flags, \
2239 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2240 (T_ETH_MAC_COMMAND_INVALIDATE))
2242 /* Number of u32 elements in MC hash array */
2243 #define MC_HASH_SIZE 8
2244 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2245 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2247 #ifndef PXP2_REG_PXP2_INT_STS
2248 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2251 #ifndef ETH_MAX_RX_CLIENTS_E2
2252 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2255 #define BNX2X_VPD_LEN 128
2256 #define VENDOR_ID_LEN 4
2258 #define VF_ACQUIRE_THRESH 3
2259 #define VF_ACQUIRE_MAC_FILTERS 1
2260 #define VF_ACQUIRE_MC_FILTERS 10
2262 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2263 (!((me_reg) & ME_REG_VF_ERR)))
2264 int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code);
2265 /* Congestion management fairness mode */
2266 #define CMNG_FNS_NONE 0
2267 #define CMNG_FNS_MINMAX 1
2269 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2270 #define HC_SEG_ACCESS_ATTN 4
2271 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2273 static const u32 dmae_reg_go_c[] = {
2274 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2275 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2276 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2277 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2280 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2281 void bnx2x_notify_link_changed(struct bnx2x *bp);
2283 #define BNX2X_MF_SD_PROTOCOL(bp) \
2284 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2286 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2287 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2289 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2290 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2292 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2293 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2295 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \
2296 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2298 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
2299 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2300 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2301 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2303 #define SET_FLAG(value, mask, flag) \
2305 (value) &= ~(mask);\
2306 (value) |= ((flag) << (mask##_SHIFT));\
2309 #define GET_FLAG(value, mask) \
2310 (((value) & (mask)) >> (mask##_SHIFT))
2312 #define GET_FIELD(value, fname) \
2313 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2322 enum bnx2x_pci_bus_speed {
2323 BNX2X_PCI_LINK_SPEED_2500 = 2500,
2324 BNX2X_PCI_LINK_SPEED_5000 = 5000,
2325 BNX2X_PCI_LINK_SPEED_8000 = 8000
2327 #endif /* bnx2x.h */