1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
16 #include <linux/netdevice.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/types.h>
20 /* compilation time flags */
22 /* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24 /* #define BNX2X_STOP_ON_ERROR */
26 #define DRV_MODULE_VERSION "1.78.00-0"
27 #define DRV_MODULE_RELDATE "2012/09/27"
28 #define BNX2X_BC_VER 0x040200
30 #if defined(CONFIG_DCB)
35 #include "bnx2x_hsi.h"
37 #include "../cnic_if.h"
40 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
42 #include <linux/mdio.h>
44 #include "bnx2x_reg.h"
45 #include "bnx2x_fw_defs.h"
46 #include "bnx2x_mfw_req.h"
47 #include "bnx2x_link.h"
49 #include "bnx2x_dcb.h"
50 #include "bnx2x_stats.h"
52 /* error/debug prints */
54 #define DRV_MODULE_NAME "bnx2x"
56 /* for messages that are currently off */
57 #define BNX2X_MSG_OFF 0x0
58 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
59 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
60 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
61 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
62 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
63 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
64 #define BNX2X_MSG_IOV 0x0800000
65 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
66 #define BNX2X_MSG_ETHTOOL 0x4000000
67 #define BNX2X_MSG_DCB 0x8000000
69 /* regular debug print */
70 #define DP(__mask, fmt, ...) \
72 if (unlikely(bp->msg_enable & (__mask))) \
73 pr_notice("[%s:%d(%s)]" fmt, \
75 bp->dev ? (bp->dev->name) : "?", \
79 #define DP_CONT(__mask, fmt, ...) \
81 if (unlikely(bp->msg_enable & (__mask))) \
82 pr_cont(fmt, ##__VA_ARGS__); \
85 /* errors debug print */
86 #define BNX2X_DBG_ERR(fmt, ...) \
88 if (unlikely(netif_msg_probe(bp))) \
89 pr_err("[%s:%d(%s)]" fmt, \
91 bp->dev ? (bp->dev->name) : "?", \
95 /* for errors (never masked) */
96 #define BNX2X_ERR(fmt, ...) \
98 pr_err("[%s:%d(%s)]" fmt, \
100 bp->dev ? (bp->dev->name) : "?", \
104 #define BNX2X_ERROR(fmt, ...) \
105 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
108 /* before we have a dev->name use dev_info() */
109 #define BNX2X_DEV_INFO(fmt, ...) \
111 if (unlikely(netif_msg_probe(bp))) \
112 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
115 #ifdef BNX2X_STOP_ON_ERROR
116 void bnx2x_int_disable(struct bnx2x *bp);
117 #define bnx2x_panic() \
120 BNX2X_ERR("driver assert\n"); \
121 bnx2x_int_disable(bp); \
122 bnx2x_panic_dump(bp); \
125 #define bnx2x_panic() \
128 BNX2X_ERR("driver assert\n"); \
129 bnx2x_panic_dump(bp); \
133 #define bnx2x_mc_addr(ha) ((ha)->addr)
134 #define bnx2x_uc_addr(ha) ((ha)->addr)
136 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
137 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
138 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
141 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
143 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
144 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
145 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
147 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
148 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
149 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
151 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
152 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
154 #define REG_RD_DMAE(bp, offset, valp, len32) \
156 bnx2x_read_dmae(bp, offset, len32);\
157 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
160 #define REG_WR_DMAE(bp, offset, valp, len32) \
162 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
163 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
167 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
168 REG_WR_DMAE(bp, offset, valp, len32)
170 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
172 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
173 bnx2x_write_big_buf_wb(bp, addr, len32); \
176 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
177 offsetof(struct shmem_region, field))
178 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
179 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
181 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
182 offsetof(struct shmem2_region, field))
183 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
184 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
185 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
186 offsetof(struct mf_cfg, field))
187 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
188 offsetof(struct mf2_cfg, field))
190 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
191 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
192 MF_CFG_ADDR(bp, field), (val))
193 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
195 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
196 (SHMEM2_RD((bp), size) > \
197 offsetof(struct shmem2_region, field)))
199 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
200 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
204 /* General SP events - stats query, cfc delete, etc */
205 #define HC_SP_INDEX_ETH_DEF_CONS 3
208 #define HC_SP_INDEX_EQ_CONS 7
210 /* FCoE L2 connection completions */
211 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
212 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
214 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
215 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
217 /* Special clients parameters */
221 #define BNX2X_FCOE_L2_RX_INDEX \
222 (&bp->def_status_blk->sp_sb.\
223 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
225 #define BNX2X_FCOE_L2_TX_INDEX \
226 (&bp->def_status_blk->sp_sb.\
227 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
231 * CLIDs below is a CLID for func 0, then the CLID for other
232 * functions will be calculated by the formula:
234 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
238 BNX2X_ISCSI_ETH_CL_ID_IDX,
239 BNX2X_FCOE_ETH_CL_ID_IDX,
240 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
243 #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\
246 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
248 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
250 #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
251 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
252 #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
253 #define FCOE_INIT(bp) ((bp)->fcoe_init)
255 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
256 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
261 /* defines for multiple tx priority indices */
262 #define FIRST_TX_ONLY_COS_INDEX 1
263 #define FIRST_TX_COS_INDEX 0
265 /* rules for calculating the cids of tx-only connections */
266 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
267 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
268 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
270 /* fp index inside class of service range */
271 #define FP_COS_TO_TXQ(fp, cos, bp) \
272 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
274 /* Indexes for transmission queues array:
275 * txdata for RSS i CoS j is at location i + (j * num of RSS)
276 * txdata for FCoE (if exist) is at location max cos * num of RSS
277 * txdata for FWD (if exist) is one location after FCoE
278 * txdata for OOO (if exist) is one location after FWD
285 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
286 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
290 * This driver uses new build_skb() API :
291 * RX ring buffer contains pointer to kmalloc() data only,
292 * skb are built only after Hardware filled the frame.
296 DEFINE_DMA_UNMAP_ADDR(mapping);
303 /* Set on the first BD descriptor when there is a split BD */
304 #define BNX2X_TSO_SPLIT_BD (1<<0)
309 DEFINE_DMA_UNMAP_ADDR(mapping);
313 struct doorbell_set_prod data;
317 /* dropless fc FW/HW related params */
318 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
319 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
320 ETH_MAX_AGGREGATION_QUEUES_E1 :\
321 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
322 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
323 #define FW_PREFETCH_CNT 16
324 #define DROPLESS_FC_HEADROOM 100
327 #define BCM_PAGE_SHIFT 12
328 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
329 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
330 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
332 #define PAGES_PER_SGE_SHIFT 0
333 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
334 #define SGE_PAGE_SIZE PAGE_SIZE
335 #define SGE_PAGE_SHIFT PAGE_SHIFT
336 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
338 /* SGE ring related macros */
339 #define NUM_RX_SGE_PAGES 2
340 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
341 #define NEXT_PAGE_SGE_DESC_CNT 2
342 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
343 /* RX_SGE_CNT is promised to be a power of 2 */
344 #define RX_SGE_MASK (RX_SGE_CNT - 1)
345 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
346 #define MAX_RX_SGE (NUM_RX_SGE - 1)
347 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
348 (MAX_RX_SGE_CNT - 1)) ? \
349 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
351 #define RX_SGE(x) ((x) & MAX_RX_SGE)
354 * Number of required SGEs is the sum of two:
355 * 1. Number of possible opened aggregations (next packet for
356 * these aggregations will probably consume SGE immidiatelly)
357 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
358 * after placement on BD for new TPA aggregation)
360 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
362 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
363 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
364 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
366 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
367 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
368 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
370 /* Manipulate a bit vector defined as an array of u64 */
372 /* Number of bits in one sge_mask array element */
373 #define BIT_VEC64_ELEM_SZ 64
374 #define BIT_VEC64_ELEM_SHIFT 6
375 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
378 #define __BIT_VEC64_SET_BIT(el, bit) \
380 el = ((el) | ((u64)0x1 << (bit))); \
383 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
385 el = ((el) & (~((u64)0x1 << (bit)))); \
389 #define BIT_VEC64_SET_BIT(vec64, idx) \
390 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
391 (idx) & BIT_VEC64_ELEM_MASK)
393 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
394 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
395 (idx) & BIT_VEC64_ELEM_MASK)
397 #define BIT_VEC64_TEST_BIT(vec64, idx) \
398 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
399 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
401 /* Creates a bitmask of all ones in less significant bits.
402 idx - index of the most significant bit in the created mask */
403 #define BIT_VEC64_ONES_MASK(idx) \
404 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
405 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
407 /*******************************************************/
411 /* Number of u64 elements in SGE mask array */
412 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
413 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
414 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
416 union host_hc_status_block {
417 /* pointer to fp status block e1x */
418 struct host_hc_status_block_e1x *e1x_sb;
419 /* pointer to fp status block e2 */
420 struct host_hc_status_block_e2 *e2_sb;
423 struct bnx2x_agg_info {
425 * First aggregation buffer is a data buffer, the following - are pages.
426 * We will preallocate the data buffer for each aggregation when
427 * we open the interface and will replace the BD at the consumer
428 * with this one when we receive the TPA_START CQE in order to
429 * keep the Rx BD ring consistent.
431 struct sw_rx_bd first_buf;
433 #define BNX2X_TPA_START 1
434 #define BNX2X_TPA_STOP 2
435 #define BNX2X_TPA_ERROR 3
446 #define Q_STATS_OFFSET32(stat_name) \
447 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
449 struct bnx2x_fp_txdata {
451 struct sw_tx_bd *tx_buf_ring;
453 union eth_tx_bd_types *tx_desc_ring;
454 dma_addr_t tx_desc_mapping;
465 unsigned long tx_pkt;
470 struct bnx2x_fastpath *parent_fp;
474 enum bnx2x_tpa_mode_t {
479 struct bnx2x_fastpath {
480 struct bnx2x *bp; /* parent */
482 #define BNX2X_NAPI_WEIGHT 128
483 struct napi_struct napi;
484 union host_hc_status_block status_blk;
485 /* chip independed shortcuts into sb structure */
486 __le16 *sb_index_values;
487 __le16 *sb_running_index;
488 /* chip independed shortcut into rx_prods_offset memory */
489 u32 ustorm_rx_prods_offset;
492 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
493 dma_addr_t status_blk_mapping;
495 enum bnx2x_tpa_mode_t mode;
497 u8 max_cos; /* actual number of active tx coses */
498 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
500 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
501 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
503 struct eth_rx_bd *rx_desc_ring;
504 dma_addr_t rx_desc_mapping;
506 union eth_rx_cqe *rx_comp_ring;
507 dma_addr_t rx_comp_mapping;
510 struct eth_rx_sge *rx_sge_ring;
511 dma_addr_t rx_sge_mapping;
513 u64 sge_mask[RX_SGE_MASK_LEN];
519 u8 index; /* number in fp array */
520 u8 rx_queue; /* index for skb_record */
521 u8 cl_id; /* eth client id */
523 u8 fw_sb_id; /* status block number in FW */
524 u8 igu_sb_id; /* status block number in HW */
531 /* The last maximal completed SGE */
534 unsigned long rx_pkt,
538 struct bnx2x_agg_info *tpa_info;
540 #ifdef BNX2X_STOP_ON_ERROR
543 /* The size is calculated using the following:
544 sizeof name field from netdev structure +
546 4 (for the digits and to make it DWORD aligned) */
547 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
548 char name[FP_NAME_SIZE];
551 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
552 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
553 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
554 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
556 /* Use 2500 as a mini-jumbo MTU for FCoE */
557 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
559 #define FCOE_IDX_OFFSET 0
561 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
563 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
564 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
565 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
566 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
567 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
568 txdata_ptr[FIRST_TX_COS_INDEX] \
572 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
573 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
574 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
578 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
579 #define RX_COPY_THRESH 92
581 #define NUM_TX_RINGS 16
582 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
583 #define NEXT_PAGE_TX_DESC_CNT 1
584 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
585 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
586 #define MAX_TX_BD (NUM_TX_BD - 1)
587 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
588 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
589 (MAX_TX_DESC_CNT - 1)) ? \
590 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
592 #define TX_BD(x) ((x) & MAX_TX_BD)
593 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
595 /* number of NEXT_PAGE descriptors may be required during placement */
596 #define NEXT_CNT_PER_TX_PKT(bds) \
597 (((bds) + MAX_TX_DESC_CNT - 1) / \
598 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
599 /* max BDs per tx packet w/o next_pages:
600 * START_BD - describes packed
601 * START_BD(splitted) - includes unpaged data segment for GSO
602 * PARSING_BD - for TSO and CSUM data
603 * Frag BDs - decribes pages for frags
605 #define BDS_PER_TX_PKT 3
606 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
607 /* max BDs per tx packet including next pages */
608 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
609 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
611 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
612 #define NUM_RX_RINGS 8
613 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
614 #define NEXT_PAGE_RX_DESC_CNT 2
615 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
616 #define RX_DESC_MASK (RX_DESC_CNT - 1)
617 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
618 #define MAX_RX_BD (NUM_RX_BD - 1)
619 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
621 /* dropless fc calculations for BDs
623 * Number of BDs should as number of buffers in BRB:
624 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
625 * "next" elements on each page
627 #define NUM_BD_REQ BRB_SIZE(bp)
628 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
630 #define BD_TH_LO(bp) (NUM_BD_REQ + \
631 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
633 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
635 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
637 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
638 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
639 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
640 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
641 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
642 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
645 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
646 (MAX_RX_DESC_CNT - 1)) ? \
647 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
649 #define RX_BD(x) ((x) & MAX_RX_BD)
652 * As long as CQE is X times bigger than BD entry we have to allocate X times
653 * more pages for CQ ring in order to keep it balanced with BD ring
655 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
656 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
657 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
658 #define NEXT_PAGE_RCQ_DESC_CNT 1
659 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
660 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
661 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
662 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
663 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
664 (MAX_RCQ_DESC_CNT - 1)) ? \
665 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
667 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
669 /* dropless fc calculations for RCQs
671 * Number of RCQs should be as number of buffers in BRB:
672 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
673 * "next" elements on each page
675 #define NUM_RCQ_REQ BRB_SIZE(bp)
676 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
678 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
679 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
681 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
684 /* This is needed for determining of last_max */
685 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
686 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
689 #define BNX2X_SWCID_SHIFT 17
690 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
692 /* used on a CID received from the HW */
693 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
694 #define CQE_CMD(x) (le32_to_cpu(x) >> \
695 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
697 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
698 le32_to_cpu((bd)->addr_lo))
699 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
701 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
702 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
703 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
704 #error "Min DB doorbell stride is 8"
706 #define DPM_TRIGER_TYPE 0x40
707 #define DOORBELL(bp, cid, val) \
709 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
714 /* TX CSUM helpers */
715 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
717 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
720 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
723 #define XMIT_CSUM_V4 0x1
724 #define XMIT_CSUM_V6 0x2
725 #define XMIT_CSUM_TCP 0x4
726 #define XMIT_GSO_V4 0x8
727 #define XMIT_GSO_V6 0x10
729 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
730 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
733 /* stuff added to make the code fit 80Col */
734 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
735 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
736 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
737 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
738 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
740 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
742 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
743 (((le16_to_cpu(flags) & \
744 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
745 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
746 == PRS_FLAG_OVERETH_IPV4)
747 #define BNX2X_RX_SUM_FIX(cqe) \
748 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
751 #define FP_USB_FUNC_OFF \
752 offsetof(struct cstorm_status_block_u, func)
753 #define FP_CSB_FUNC_OFF \
754 offsetof(struct cstorm_status_block_c, func)
756 #define HC_INDEX_ETH_RX_CQ_CONS 1
758 #define HC_INDEX_OOO_TX_CQ_CONS 4
760 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
762 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
764 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
766 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
768 #define BNX2X_RX_SB_INDEX \
769 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
771 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
773 #define BNX2X_TX_SB_INDEX_COS0 \
774 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
776 /* end of fast path */
780 struct bnx2x_common {
783 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
784 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
786 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
787 #define CHIP_NUM_57710 0x164e
788 #define CHIP_NUM_57711 0x164f
789 #define CHIP_NUM_57711E 0x1650
790 #define CHIP_NUM_57712 0x1662
791 #define CHIP_NUM_57712_MF 0x1663
792 #define CHIP_NUM_57713 0x1651
793 #define CHIP_NUM_57713E 0x1652
794 #define CHIP_NUM_57800 0x168a
795 #define CHIP_NUM_57800_MF 0x16a5
796 #define CHIP_NUM_57810 0x168e
797 #define CHIP_NUM_57810_MF 0x16ae
798 #define CHIP_NUM_57811 0x163d
799 #define CHIP_NUM_57811_MF 0x163e
800 #define CHIP_NUM_57840_OBSOLETE 0x168d
801 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
802 #define CHIP_NUM_57840_4_10 0x16a1
803 #define CHIP_NUM_57840_2_20 0x16a2
804 #define CHIP_NUM_57840_MF 0x16a4
805 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
806 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
807 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
808 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
809 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
810 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
811 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
812 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
813 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
814 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
815 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
816 #define CHIP_IS_57840(bp) \
817 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
818 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
819 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
820 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
821 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
822 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
824 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
825 CHIP_IS_57712_MF(bp))
826 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
827 CHIP_IS_57800_MF(bp) || \
828 CHIP_IS_57810(bp) || \
829 CHIP_IS_57810_MF(bp) || \
830 CHIP_IS_57811(bp) || \
831 CHIP_IS_57811_MF(bp) || \
832 CHIP_IS_57840(bp) || \
833 CHIP_IS_57840_MF(bp))
834 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
835 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
836 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
838 #define CHIP_REV_SHIFT 12
839 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
840 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
841 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
842 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
843 /* assume maximum 5 revisions */
844 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
845 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
846 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
847 !(CHIP_REV_VAL(bp) & 0x00001000))
848 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
849 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
850 (CHIP_REV_VAL(bp) & 0x00001000))
852 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
853 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
855 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
856 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
857 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
858 (CHIP_REV_SHIFT + 1)) \
860 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
863 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
864 (CHIP_REV(bp) == CHIP_REV_Bx))
865 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
866 (CHIP_REV(bp) == CHIP_REV_Ax))
867 /* This define is used in two main places:
868 * 1. In the early stages of nic_load, to know if to configrue Parser / Searcher
869 * to nic-only mode or to offload mode. Offload mode is configured if either the
870 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
871 * registered for this port (which means that the user wants storage services).
872 * 2. During cnic-related load, to know if offload mode is already configured in
873 * the HW or needs to be configrued.
874 * Since the transition from nic-mode to offload-mode in HW causes traffic
875 * coruption, nic-mode is configured only in ports on which storage services
876 * where never requested.
878 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
881 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
882 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
883 #define BNX2X_NVRAM_PAGE_SIZE 256
895 #define INT_BLOCK_HC 0
896 #define INT_BLOCK_IGU 1
897 #define INT_BLOCK_MODE_NORMAL 0
898 #define INT_BLOCK_MODE_BW_COMP 2
899 #define CHIP_INT_MODE_IS_NBC(bp) \
900 (!CHIP_IS_E1x(bp) && \
901 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
902 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
905 #define CHIP_4_PORT_MODE 0x0
906 #define CHIP_2_PORT_MODE 0x1
907 #define CHIP_PORT_MODE_NONE 0x2
908 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
909 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
914 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
915 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
916 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
918 #define MAX_IGU_ATTN_ACK_TO 100
926 u32 link_config[LINK_CONFIG_SIZE];
928 u32 supported[LINK_CONFIG_SIZE];
929 /* link settings - missing defines */
930 #define SUPPORTED_2500baseX_Full (1 << 15)
932 u32 advertising[LINK_CONFIG_SIZE];
933 /* link settings - missing defines */
934 #define ADVERTISED_2500baseX_Full (1 << 15)
938 /* used to synchronize phy accesses */
939 struct mutex phy_mutex;
943 struct nig_stats old_nig_stats;
948 #define STATS_OFFSET32(stat_name) \
949 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
953 /* slow path work-queue */
954 extern struct workqueue_struct *bnx2x_wq;
956 #define BNX2X_MAX_NUM_OF_VFS 64
957 #define BNX2X_VF_ID_INVALID 0xFF
960 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
961 * control by the number of fast-path status blocks supported by the
962 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
963 * status block represents an independent interrupts context that can
964 * serve a regular L2 networking queue. However special L2 queues such
965 * as the FCoE queue do not require a FP-SB and other components like
966 * the CNIC may consume FP-SB reducing the number of possible L2 queues
968 * If the maximum number of FP-SB available is X then:
969 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
970 * regular L2 queues is Y=X-1
971 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
972 * c. If the FCoE L2 queue is supported the actual number of L2 queues
974 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
975 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
976 * FP interrupt context for the CNIC).
977 * e. The number of HW context (CID count) is always X or X+1 if FCoE
978 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
981 /* fast-path interrupt contexts E1x */
982 #define FP_SB_MAX_E1x 16
983 /* fast-path interrupt contexts E2 */
984 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
987 struct eth_context eth;
991 /* CDU host DB constants */
992 #define CDU_ILT_PAGE_SZ_HW 2
993 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
994 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
996 #define CNIC_ISCSI_CID_MAX 256
997 #define CNIC_FCOE_CID_MAX 2048
998 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
999 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1001 #define QM_ILT_PAGE_SZ_HW 0
1002 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1003 #define QM_CID_ROUND 1024
1005 /* TM (timers) host DB constants */
1006 #define TM_ILT_PAGE_SZ_HW 0
1007 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1008 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
1009 #define TM_CONN_NUM 1024
1010 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1011 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1013 /* SRC (Searcher) host DB constants */
1014 #define SRC_ILT_PAGE_SZ_HW 0
1015 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1016 #define SRC_HASH_BITS 10
1017 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1018 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1019 #define SRC_T2_SZ SRC_ILT_SZ
1020 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1022 #define MAX_DMAE_C 8
1024 /* DMA memory not used in fastpath */
1025 struct bnx2x_slowpath {
1027 struct mac_configuration_cmd e1x;
1028 struct eth_classify_rules_ramrod_data e2;
1033 struct tstorm_eth_mac_filter_config e1x;
1034 struct eth_filter_rules_ramrod_data e2;
1038 struct mac_configuration_cmd e1;
1039 struct eth_multicast_rules_ramrod_data e2;
1042 struct eth_rss_update_ramrod_data rss_rdata;
1044 /* Queue State related ramrods are always sent under rtnl_lock */
1046 struct client_init_ramrod_data init_data;
1047 struct client_update_ramrod_data update_data;
1051 struct function_start_data func_start;
1052 /* pfc configuration for DCBX ramrod */
1053 struct flow_control_configuration pfc_config;
1056 /* afex ramrod can not be a part of func_rdata union because these
1057 * events might arrive in parallel to other events from func_rdata.
1058 * Therefore, if they would have been defined in the same union,
1059 * data can get corrupted.
1061 struct afex_vif_list_ramrod_data func_afex_rdata;
1063 /* used by dmae command executer */
1064 struct dmae_command dmae[MAX_DMAE_C];
1067 union mac_stats mac_stats;
1068 struct nig_stats nig_stats;
1069 struct host_port_stats port_stats;
1070 struct host_func_stats func_stats;
1075 union drv_info_to_mcp drv_info_to_mcp;
1078 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1079 #define bnx2x_sp_mapping(bp, var) \
1080 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1083 /* attn group wiring */
1084 #define MAX_DYNAMIC_ATTN_GRPS 8
1099 union cdu_context *vcxt;
1100 dma_addr_t cxt_mapping;
1108 enum bnx2x_recovery_state {
1109 BNX2X_RECOVERY_DONE,
1110 BNX2X_RECOVERY_INIT,
1111 BNX2X_RECOVERY_WAIT,
1112 BNX2X_RECOVERY_FAILED,
1113 BNX2X_RECOVERY_NIC_LOADING
1117 * Event queue (EQ or event ring) MC hsi
1118 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1120 #define NUM_EQ_PAGES 1
1121 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1122 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1123 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1124 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1125 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1127 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1128 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1129 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1131 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1132 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1134 #define BNX2X_EQ_INDEX \
1135 (&bp->def_status_blk->sp_sb.\
1136 index_values[HC_SP_INDEX_EQ_CONS])
1138 /* This is a data that will be used to create a link report message.
1139 * We will keep the data used for the last link report in order
1140 * to prevent reporting the same link parameters twice.
1142 struct bnx2x_link_report_data {
1143 u16 line_speed; /* Effective line speed */
1144 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1148 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1149 BNX2X_LINK_REPORT_LINK_DOWN,
1150 BNX2X_LINK_REPORT_RX_FC_ON,
1151 BNX2X_LINK_REPORT_TX_FC_ON,
1155 BNX2X_PORT_QUERY_IDX,
1157 BNX2X_FCOE_QUERY_IDX,
1158 BNX2X_FIRST_QUEUE_QUERY_IDX,
1161 struct bnx2x_fw_stats_req {
1162 struct stats_query_header hdr;
1163 struct stats_query_entry query[FP_SB_MAX_E1x+
1164 BNX2X_FIRST_QUEUE_QUERY_IDX];
1167 struct bnx2x_fw_stats_data {
1168 struct stats_counter storm_counters;
1169 struct per_port_stats port;
1170 struct per_pf_stats pf;
1171 struct fcoe_statistics_params fcoe;
1172 struct per_queue_stats queue_stats[1];
1175 /* Public slow path states */
1177 BNX2X_SP_RTNL_SETUP_TC,
1178 BNX2X_SP_RTNL_TX_TIMEOUT,
1179 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1180 BNX2X_SP_RTNL_FAN_FAILURE,
1184 struct bnx2x_prev_path_list {
1188 struct list_head list;
1192 struct bnx2x_sp_objs {
1194 struct bnx2x_vlan_mac_obj mac_obj;
1196 /* Queue State object */
1197 struct bnx2x_queue_sp_obj q_obj;
1200 struct bnx2x_fp_stats {
1201 struct tstorm_per_queue_stats old_tclient;
1202 struct ustorm_per_queue_stats old_uclient;
1203 struct xstorm_per_queue_stats old_xclient;
1204 struct bnx2x_eth_q_stats eth_q_stats;
1205 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1209 /* Fields used in the tx and intr/napi performance paths
1210 * are grouped together in the beginning of the structure
1212 struct bnx2x_fastpath *fp;
1213 struct bnx2x_sp_objs *sp_objs;
1214 struct bnx2x_fp_stats *fp_stats;
1215 struct bnx2x_fp_txdata *bnx2x_txq;
1216 void __iomem *regview;
1217 void __iomem *doorbells;
1220 u8 pf_num; /* absolute PF number */
1221 u8 pfid; /* per-path PF number */
1222 int base_fw_ndsb; /**/
1223 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1224 #define BP_PORT(bp) (bp->pfid & 1)
1225 #define BP_FUNC(bp) (bp->pfid)
1226 #define BP_ABS_FUNC(bp) (bp->pf_num)
1227 #define BP_VN(bp) ((bp)->pfid >> 1)
1228 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1229 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1230 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1231 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1232 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1234 struct net_device *dev;
1235 struct pci_dev *pdev;
1237 const struct iro *iro_arr;
1238 #define IRO (bp->iro_arr)
1240 enum bnx2x_recovery_state recovery_state;
1242 struct msix_entry *msix_table;
1246 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1247 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1248 #define ETH_MIN_PACKET_SIZE 60
1249 #define ETH_MAX_PACKET_SIZE 1500
1250 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1251 /* TCP with Timestamp Option (32) + IPv6 (40) */
1252 #define ETH_MAX_TPA_HEADER_SIZE 72
1254 /* Max supported alignment is 256 (8 shift) */
1255 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1257 /* FW uses 2 Cache lines Alignment for start packet and size
1259 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1260 * at the end of skb->data, to avoid wasting a full cache line.
1261 * This reduces memory use (skb->truesize).
1263 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1265 #define BNX2X_FW_RX_ALIGN_END \
1266 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1267 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1269 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1271 struct host_sp_status_block *def_status_blk;
1272 #define DEF_SB_IGU_ID 16
1273 #define DEF_SB_ID HC_SP_SB_ID
1277 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1279 /* slow path ring */
1280 struct eth_spe *spq;
1281 dma_addr_t spq_mapping;
1283 struct eth_spe *spq_prod_bd;
1284 struct eth_spe *spq_last_bd;
1285 __le16 *dsb_sp_prod;
1286 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1287 /* used to synchronize spq accesses */
1288 spinlock_t spq_lock;
1291 union event_ring_elem *eq_ring;
1292 dma_addr_t eq_mapping;
1296 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1300 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1302 /* Counter for completed statistics ramrods */
1305 /* End of fields used in the performance code paths */
1311 #define PCIX_FLAG (1 << 0)
1312 #define PCI_32BIT_FLAG (1 << 1)
1313 #define ONE_PORT_FLAG (1 << 2)
1314 #define NO_WOL_FLAG (1 << 3)
1315 #define USING_DAC_FLAG (1 << 4)
1316 #define USING_MSIX_FLAG (1 << 5)
1317 #define USING_MSI_FLAG (1 << 6)
1318 #define DISABLE_MSI_FLAG (1 << 7)
1319 #define TPA_ENABLE_FLAG (1 << 8)
1320 #define NO_MCP_FLAG (1 << 9)
1322 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1323 #define GRO_ENABLE_FLAG (1 << 10)
1324 #define MF_FUNC_DIS (1 << 11)
1325 #define OWN_CNIC_IRQ (1 << 12)
1326 #define NO_ISCSI_OOO_FLAG (1 << 13)
1327 #define NO_ISCSI_FLAG (1 << 14)
1328 #define NO_FCOE_FLAG (1 << 15)
1329 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1330 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1331 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1332 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1334 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1335 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1336 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1341 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1343 /* Flag that indicates that we can start looking for FCoE L2 queue
1344 * completions in the default status block.
1351 struct delayed_work sp_task;
1352 struct delayed_work sp_rtnl_task;
1354 struct delayed_work period_task;
1355 struct timer_list timer;
1356 int current_interval;
1359 u16 fw_drv_pulse_wr_seq;
1362 struct link_params link_params;
1363 struct link_vars link_vars;
1365 struct bnx2x_link_report_data last_reported_link;
1367 struct mdio_if_info mdio;
1369 struct bnx2x_common common;
1370 struct bnx2x_port port;
1372 struct cmng_init cmng;
1374 u32 mf_config[E1HVN_MAX];
1376 u32 path_has_ovlan; /* E3 */
1379 #define IS_MF(bp) (bp->mf_mode != 0)
1380 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1381 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1382 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1388 u16 tx_quick_cons_trip_int;
1389 u16 tx_quick_cons_trip;
1393 u16 rx_quick_cons_trip_int;
1394 u16 rx_quick_cons_trip;
1397 /* Maximal coalescing timeout in us */
1398 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1403 #define BNX2X_STATE_CLOSED 0
1404 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1405 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1406 #define BNX2X_STATE_OPEN 0x3000
1407 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1408 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1410 #define BNX2X_STATE_DIAG 0xe000
1411 #define BNX2X_STATE_ERROR 0xf000
1413 #define BNX2X_MAX_PRIORITY 8
1414 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1415 #define BNX2X_MAX_COS 3
1416 #define BNX2X_MAX_TX_COS 2
1418 uint num_ethernet_queues;
1419 uint num_cnic_queues;
1420 int num_napi_queues;
1424 #define BNX2X_RX_MODE_NONE 0
1425 #define BNX2X_RX_MODE_NORMAL 1
1426 #define BNX2X_RX_MODE_ALLMULTI 2
1427 #define BNX2X_RX_MODE_PROMISC 3
1428 #define BNX2X_MAX_MULTICAST 64
1433 u8 min_msix_vec_cnt;
1435 dma_addr_t def_status_blk_mapping;
1437 struct bnx2x_slowpath *slowpath;
1438 dma_addr_t slowpath_mapping;
1440 /* Total number of FW statistics requests */
1444 * This is a memory buffer that will contain both statistics
1445 * ramrod request and data.
1448 dma_addr_t fw_stats_mapping;
1451 * FW statistics request shortcut (points at the
1452 * beginning of fw_stats buffer).
1454 struct bnx2x_fw_stats_req *fw_stats_req;
1455 dma_addr_t fw_stats_req_mapping;
1456 int fw_stats_req_sz;
1459 * FW statistics data shortcut (points at the beginning of
1460 * fw_stats buffer + fw_stats_req_sz).
1462 struct bnx2x_fw_stats_data *fw_stats_data;
1463 dma_addr_t fw_stats_data_mapping;
1464 int fw_stats_data_sz;
1466 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1467 * context size we need 8 ILT entries.
1469 #define ILT_MAX_L2_LINES 8
1470 struct hw_context context[ILT_MAX_L2_LINES];
1472 struct bnx2x_ilt *ilt;
1473 #define BP_ILT(bp) ((bp)->ilt)
1474 #define ILT_MAX_LINES 256
1476 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1479 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1482 * Maximum CID count that might be required by the bnx2x:
1483 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1485 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1486 + 2 * CNIC_SUPPORT(bp))
1487 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1488 + 2 * CNIC_SUPPORT(bp))
1489 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1497 dma_addr_t t2_mapping;
1498 struct cnic_ops __rcu *cnic_ops;
1501 struct cnic_eth_dev cnic_eth_dev;
1502 union host_hc_status_block cnic_sb;
1503 dma_addr_t cnic_sb_mapping;
1504 struct eth_spe *cnic_kwq;
1505 struct eth_spe *cnic_kwq_prod;
1506 struct eth_spe *cnic_kwq_cons;
1507 struct eth_spe *cnic_kwq_last;
1508 u16 cnic_kwq_pending;
1509 u16 cnic_spq_pending;
1510 u8 fip_mac[ETH_ALEN];
1511 struct mutex cnic_mutex;
1512 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1514 /* Start index of the "special" (CNIC related) L2 cleints */
1518 /* used to synchronize dmae accesses */
1519 spinlock_t dmae_lock;
1521 /* used to protect the FW mail box */
1522 struct mutex fw_mb_mutex;
1524 /* used to synchronize stats collecting */
1527 /* used for synchronization of concurrent threads statistics handling */
1528 spinlock_t stats_lock;
1530 /* used by dmae command loader */
1531 struct dmae_command stats_dmae;
1535 struct bnx2x_eth_stats eth_stats;
1536 struct host_func_stats func_stats;
1537 struct bnx2x_eth_stats_old eth_stats_old;
1538 struct bnx2x_net_stats_old net_stats_old;
1539 struct bnx2x_fw_port_stats_old fw_stats_old;
1542 struct z_stream_s *strm;
1544 dma_addr_t gunzip_mapping;
1546 #define FW_BUF_SIZE 0x8000
1547 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1548 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1549 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1551 struct raw_op *init_ops;
1552 /* Init blocks offsets inside init_ops */
1553 u16 *init_ops_offsets;
1554 /* Data blob - has 32 bit granularity */
1556 u32 init_mode_flags;
1557 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1558 /* Zipped PRAM blobs - raw data */
1559 const u8 *tsem_int_table_data;
1560 const u8 *tsem_pram_data;
1561 const u8 *usem_int_table_data;
1562 const u8 *usem_pram_data;
1563 const u8 *xsem_int_table_data;
1564 const u8 *xsem_pram_data;
1565 const u8 *csem_int_table_data;
1566 const u8 *csem_pram_data;
1567 #define INIT_OPS(bp) (bp->init_ops)
1568 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1569 #define INIT_DATA(bp) (bp->init_data)
1570 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1571 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1572 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1573 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1574 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1575 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1576 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1577 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1579 #define PHY_FW_VER_LEN 20
1581 const struct firmware *firmware;
1583 /* DCB support on/off */
1585 #define BNX2X_DCB_STATE_OFF 0
1586 #define BNX2X_DCB_STATE_ON 1
1588 /* DCBX engine mode */
1590 #define BNX2X_DCBX_ENABLED_OFF 0
1591 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1592 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1593 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1595 bool dcbx_mode_uset;
1597 struct bnx2x_config_dcbx_params dcbx_config_params;
1598 struct bnx2x_dcbx_port_params dcbx_port_params;
1601 /* CAM credit pools */
1602 struct bnx2x_credit_pool_obj macs_pool;
1604 /* RX_MODE object */
1605 struct bnx2x_rx_mode_obj rx_mode_obj;
1608 struct bnx2x_mcast_obj mcast_obj;
1610 /* RSS configuration object */
1611 struct bnx2x_rss_config_obj rss_conf_obj;
1613 /* Function State controlling object */
1614 struct bnx2x_func_sp_obj func_obj;
1616 unsigned long sp_state;
1618 /* operation indication for the sp_rtnl task */
1619 unsigned long sp_rtnl_state;
1621 /* DCBX Negotation results */
1622 struct dcbx_features dcbx_local_feat;
1626 struct dcbx_features dcbx_remote_feat;
1627 u32 dcbx_remote_flags;
1629 /* AFEX: store default vlan used */
1630 int afex_def_vlan_tag;
1631 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1634 /* multiple tx classes of service */
1637 /* priority to cos mapping */
1641 /* Tx queues may be less or equal to Rx queues */
1642 extern int num_queues;
1643 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1644 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1645 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1646 (bp)->num_cnic_queues)
1647 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1649 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1651 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1652 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1654 #define RSS_IPV4_CAP_MASK \
1655 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1657 #define RSS_IPV4_TCP_CAP_MASK \
1658 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1660 #define RSS_IPV6_CAP_MASK \
1661 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1663 #define RSS_IPV6_TCP_CAP_MASK \
1664 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1666 /* func init flags */
1667 #define FUNC_FLG_RSS 0x0001
1668 #define FUNC_FLG_STATS 0x0002
1669 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1670 #define FUNC_FLG_TPA 0x0008
1671 #define FUNC_FLG_SPQ 0x0010
1672 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1675 struct bnx2x_func_init_params {
1677 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1678 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1681 u16 func_id; /* abs fid */
1683 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1686 #define for_each_cnic_queue(bp, var) \
1687 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1689 if (skip_queue(bp, var)) \
1693 #define for_each_eth_queue(bp, var) \
1694 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1696 #define for_each_nondefault_eth_queue(bp, var) \
1697 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1699 #define for_each_queue(bp, var) \
1700 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1701 if (skip_queue(bp, var)) \
1705 /* Skip forwarding FP */
1706 #define for_each_valid_rx_queue(bp, var) \
1708 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1709 BNX2X_NUM_ETH_QUEUES(bp)); \
1711 if (skip_rx_queue(bp, var)) \
1715 #define for_each_rx_queue_cnic(bp, var) \
1716 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1718 if (skip_rx_queue(bp, var)) \
1722 #define for_each_rx_queue(bp, var) \
1723 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1724 if (skip_rx_queue(bp, var)) \
1729 #define for_each_valid_tx_queue(bp, var) \
1731 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1732 BNX2X_NUM_ETH_QUEUES(bp)); \
1734 if (skip_tx_queue(bp, var)) \
1738 #define for_each_tx_queue_cnic(bp, var) \
1739 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1741 if (skip_tx_queue(bp, var)) \
1745 #define for_each_tx_queue(bp, var) \
1746 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1747 if (skip_tx_queue(bp, var)) \
1751 #define for_each_nondefault_queue(bp, var) \
1752 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1753 if (skip_queue(bp, var)) \
1757 #define for_each_cos_in_tx_queue(fp, var) \
1758 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1761 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1763 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1766 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1768 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1770 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1776 * bnx2x_set_mac_one - configure a single MAC address
1778 * @bp: driver handle
1779 * @mac: MAC to configure
1780 * @obj: MAC object handle
1781 * @set: if 'true' add a new MAC, otherwise - delete
1782 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1783 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1785 * Configures one MAC according to provided parameters or continues the
1786 * execution of previously scheduled commands if RAMROD_CONT is set in
1789 * Returns zero if operation has successfully completed, a positive value if the
1790 * operation has been successfully scheduled and a negative - if a requested
1791 * operations has failed.
1793 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1794 struct bnx2x_vlan_mac_obj *obj, bool set,
1795 int mac_type, unsigned long *ramrod_flags);
1797 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1799 * @bp: driver handle
1800 * @mac_obj: MAC object handle
1801 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1802 * @wait_for_comp: if 'true' block until completion
1804 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1806 * Returns zero if operation has successfully completed, a positive value if the
1807 * operation has been successfully scheduled and a negative - if a requested
1808 * operations has failed.
1810 int bnx2x_del_all_macs(struct bnx2x *bp,
1811 struct bnx2x_vlan_mac_obj *mac_obj,
1812 int mac_type, bool wait_for_comp);
1814 /* Init Function API */
1815 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1816 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1817 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1818 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1819 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1820 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1824 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1825 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1827 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1828 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1829 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1830 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1831 bool with_comp, u8 comp_type);
1834 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1835 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1836 u32 data_hi, u32 data_lo, int cmd_type);
1837 void bnx2x_update_coalesce(struct bnx2x *bp);
1838 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1840 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1846 val = REG_RD(bp, reg);
1847 if (val == expected)
1857 #define BNX2X_ILT_ZALLOC(x, y, size) \
1859 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1861 memset(x, 0, size); \
1864 #define BNX2X_ILT_FREE(x, y, size) \
1867 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1873 #define ILOG2(x) (ilog2((x)))
1875 #define ILT_NUM_PAGE_ENTRIES (3072)
1876 /* In 57710/11 we use whole table since we have 8 func
1877 * In 57712 we have only 4 func, but use same size per func, then only half of
1880 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1882 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1884 * the phys address is shifted right 12 bits and has an added
1885 * 1=valid bit added to the 53rd bit
1886 * then since this is a wide register(TM)
1887 * we split it into two 32 bit writes
1889 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1890 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1892 /* load/unload mode */
1893 #define LOAD_NORMAL 0
1896 #define LOAD_LOOPBACK_EXT 3
1897 #define UNLOAD_NORMAL 0
1898 #define UNLOAD_CLOSE 1
1899 #define UNLOAD_RECOVERY 2
1902 /* DMAE command defines */
1903 #define DMAE_TIMEOUT -1
1904 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1905 #define DMAE_NOT_RDY -3
1906 #define DMAE_PCI_ERR_FLAG 0x80000000
1908 #define DMAE_SRC_PCI 0
1909 #define DMAE_SRC_GRC 1
1911 #define DMAE_DST_NONE 0
1912 #define DMAE_DST_PCI 1
1913 #define DMAE_DST_GRC 2
1915 #define DMAE_COMP_PCI 0
1916 #define DMAE_COMP_GRC 1
1918 /* E2 and onward - PCI error handling in the completion */
1920 #define DMAE_COMP_REGULAR 0
1921 #define DMAE_COM_SET_ERR 1
1923 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1924 DMAE_COMMAND_SRC_SHIFT)
1925 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1926 DMAE_COMMAND_SRC_SHIFT)
1928 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1929 DMAE_COMMAND_DST_SHIFT)
1930 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1931 DMAE_COMMAND_DST_SHIFT)
1933 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1934 DMAE_COMMAND_C_DST_SHIFT)
1935 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1936 DMAE_COMMAND_C_DST_SHIFT)
1938 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1940 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1941 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1942 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1943 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1945 #define DMAE_CMD_PORT_0 0
1946 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1948 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1949 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1950 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1952 #define DMAE_SRC_PF 0
1953 #define DMAE_SRC_VF 1
1955 #define DMAE_DST_PF 0
1956 #define DMAE_DST_VF 1
1958 #define DMAE_C_SRC 0
1959 #define DMAE_C_DST 1
1961 #define DMAE_LEN32_RD_MAX 0x80
1962 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1964 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1967 #define MAX_DMAE_C_PER_PORT 8
1968 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1970 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1973 /* PCIE link and speed */
1974 #define PCICFG_LINK_WIDTH 0x1f00000
1975 #define PCICFG_LINK_WIDTH_SHIFT 20
1976 #define PCICFG_LINK_SPEED 0xf0000
1977 #define PCICFG_LINK_SPEED_SHIFT 16
1979 #define BNX2X_NUM_TESTS_SF 7
1980 #define BNX2X_NUM_TESTS_MF 3
1981 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
1984 #define BNX2X_PHY_LOOPBACK 0
1985 #define BNX2X_MAC_LOOPBACK 1
1986 #define BNX2X_EXT_LOOPBACK 2
1987 #define BNX2X_PHY_LOOPBACK_FAILED 1
1988 #define BNX2X_MAC_LOOPBACK_FAILED 2
1989 #define BNX2X_EXT_LOOPBACK_FAILED 3
1990 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1991 BNX2X_PHY_LOOPBACK_FAILED)
1994 #define STROM_ASSERT_ARRAY_SIZE 50
1997 /* must be used on a CID before placing it on a HW ring */
1998 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1999 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2002 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2003 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2007 #define MAX_SPQ_PENDING 8
2009 /* CMNG constants, as derived from system spec calculations */
2010 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2011 #define DEF_MIN_RATE 100
2012 /* resolution of the rate shaping timer - 400 usec */
2013 #define RS_PERIODIC_TIMEOUT_USEC 400
2014 /* number of bytes in single QM arbitration cycle -
2015 * coefficient for calculating the fairness timer */
2016 #define QM_ARB_BYTES 160000
2017 /* resolution of Min algorithm 1:100 */
2019 /* how many bytes above threshold for the minimal credit of Min algorithm*/
2020 #define MIN_ABOVE_THRESH 32768
2021 /* Fairness algorithm integration time coefficient -
2022 * for calculating the actual Tfair */
2023 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2024 /* Memory of fairness algorithm . 2 cycles */
2028 #define ATTN_NIG_FOR_FUNC (1L << 8)
2029 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2030 #define GPIO_2_FUNC (1L << 10)
2031 #define GPIO_3_FUNC (1L << 11)
2032 #define GPIO_4_FUNC (1L << 12)
2033 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2034 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2035 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2036 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2037 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2038 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2040 #define ATTN_HARD_WIRED_MASK 0xff00
2041 #define ATTENTION_ID 4
2044 /* stuff added to make the code fit 80Col */
2046 #define BNX2X_PMF_LINK_ASSERT \
2047 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2049 #define BNX2X_MC_ASSERT_BITS \
2050 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2051 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2052 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2053 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2055 #define BNX2X_MCP_ASSERT \
2056 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2058 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2059 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2060 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2061 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2062 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2063 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2064 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2066 #define HW_INTERRUT_ASSERT_SET_0 \
2067 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2068 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2069 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2070 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2071 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2072 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2073 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2074 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2075 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2076 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2077 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2078 #define HW_INTERRUT_ASSERT_SET_1 \
2079 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2080 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2081 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2082 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2083 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2084 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2085 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2086 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2087 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2088 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2089 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2090 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2091 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2092 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2093 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2094 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2095 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2096 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2097 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2098 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2099 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2100 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2101 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2102 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2103 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2104 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2105 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2106 #define HW_INTERRUT_ASSERT_SET_2 \
2107 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2108 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2109 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2110 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2111 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2112 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2113 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2114 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2115 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2116 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2117 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2118 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2119 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2121 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2122 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2123 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2124 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2126 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2127 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2129 #define MULTI_MASK 0x7f
2132 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2133 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2134 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2135 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2137 #define DEF_USB_IGU_INDEX_OFF \
2138 offsetof(struct cstorm_def_status_block_u, igu_index)
2139 #define DEF_CSB_IGU_INDEX_OFF \
2140 offsetof(struct cstorm_def_status_block_c, igu_index)
2141 #define DEF_XSB_IGU_INDEX_OFF \
2142 offsetof(struct xstorm_def_status_block, igu_index)
2143 #define DEF_TSB_IGU_INDEX_OFF \
2144 offsetof(struct tstorm_def_status_block, igu_index)
2146 #define DEF_USB_SEGMENT_OFF \
2147 offsetof(struct cstorm_def_status_block_u, segment)
2148 #define DEF_CSB_SEGMENT_OFF \
2149 offsetof(struct cstorm_def_status_block_c, segment)
2150 #define DEF_XSB_SEGMENT_OFF \
2151 offsetof(struct xstorm_def_status_block, segment)
2152 #define DEF_TSB_SEGMENT_OFF \
2153 offsetof(struct tstorm_def_status_block, segment)
2155 #define BNX2X_SP_DSB_INDEX \
2156 (&bp->def_status_blk->sp_sb.\
2157 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2159 #define SET_FLAG(value, mask, flag) \
2161 (value) &= ~(mask);\
2162 (value) |= ((flag) << (mask##_SHIFT));\
2165 #define GET_FLAG(value, mask) \
2166 (((value) & (mask)) >> (mask##_SHIFT))
2168 #define GET_FIELD(value, fname) \
2169 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2171 #define CAM_IS_INVALID(x) \
2172 (GET_FLAG(x.flags, \
2173 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2174 (T_ETH_MAC_COMMAND_INVALIDATE))
2176 /* Number of u32 elements in MC hash array */
2177 #define MC_HASH_SIZE 8
2178 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2179 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2182 #ifndef PXP2_REG_PXP2_INT_STS
2183 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2186 #ifndef ETH_MAX_RX_CLIENTS_E2
2187 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2190 #define BNX2X_VPD_LEN 128
2191 #define VENDOR_ID_LEN 4
2193 /* Congestion management fairness mode */
2194 #define CMNG_FNS_NONE 0
2195 #define CMNG_FNS_MINMAX 1
2197 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2198 #define HC_SEG_ACCESS_ATTN 4
2199 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2201 static const u32 dmae_reg_go_c[] = {
2202 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2203 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2204 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2205 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2208 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2209 void bnx2x_notify_link_changed(struct bnx2x *bp);
2212 #define BNX2X_MF_SD_PROTOCOL(bp) \
2213 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2215 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2216 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2218 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2219 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2221 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2222 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2224 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \
2225 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2227 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
2228 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2229 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2230 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2239 #endif /* bnx2x.h */