1 /* bnx2x_cmn.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
20 #include <linux/types.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
28 /* This is used as a replacement for an MCP if it's not present */
29 extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */
31 extern int num_queues;
33 /************************ Macros ********************************/
34 #define BNX2X_PCI_FREE(x, y, size) \
37 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
43 #define BNX2X_FREE(x) \
51 #define BNX2X_PCI_ALLOC(x, y, size) \
53 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
56 memset((void *)x, 0, size); \
59 #define BNX2X_ALLOC(x, size) \
61 x = kzalloc(size, GFP_KERNEL); \
66 /*********************** Interfaces ****************************
67 * Functions that need to be implemented by each driver version
72 * bnx2x_send_unload_req - request unload mode from the MCP.
75 * @unload_mode: requested function's unload mode
77 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
79 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
82 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
86 void bnx2x_send_unload_done(struct bnx2x *bp);
89 * bnx2x_config_rss_pf - configure RSS parameters in a PF.
92 * @rss_obj RSS object to use
93 * @ind_table: indirection table to configure
94 * @config_hash: re-configure RSS hash keys configuration
96 int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
100 * bnx2x__init_func_obj - init function object
104 * Initializes the Function Object with the appropriate
105 * parameters which include a function slow path driver
108 void bnx2x__init_func_obj(struct bnx2x *bp);
111 * bnx2x_setup_queue - setup eth queue.
114 * @fp: pointer to the fastpath structure
118 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
122 * bnx2x_setup_leading - bring up a leading eth queue.
126 int bnx2x_setup_leading(struct bnx2x *bp);
129 * bnx2x_fw_command - send the MCP a request
133 * @param: request's parameter
135 * block until there is a reply
137 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
140 * bnx2x_initial_phy_init - initialize link parameters structure variables.
143 * @load_mode: current mode
145 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
148 * bnx2x_link_set - configure hw according to link parameters structure.
152 void bnx2x_link_set(struct bnx2x *bp);
155 * bnx2x_link_test - query link status.
160 * Returns 0 if link is UP.
162 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
165 * bnx2x_drv_pulse - write driver pulse to shmem
169 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox
172 void bnx2x_drv_pulse(struct bnx2x *bp);
175 * bnx2x_igu_ack_sb - update IGU with current SB value
179 * @segment: SB segment
182 * @update: is HW update required
184 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
185 u16 index, u8 op, u8 update);
187 /* Disable transactions from chip to host */
188 void bnx2x_pf_disable(struct bnx2x *bp);
191 * bnx2x__link_status_update - handles link status change.
195 void bnx2x__link_status_update(struct bnx2x *bp);
198 * bnx2x_link_report - report link status to upper layer.
202 void bnx2x_link_report(struct bnx2x *bp);
204 /* None-atomic version of bnx2x_link_report() */
205 void __bnx2x_link_report(struct bnx2x *bp);
208 * bnx2x_get_mf_speed - calculate MF speed.
212 * Takes into account current linespeed and MF configuration.
214 u16 bnx2x_get_mf_speed(struct bnx2x *bp);
217 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
220 * @dev_instance: private instance
222 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
225 * bnx2x_interrupt - non MSI-X interrupt handler
228 * @dev_instance: private instance
230 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
234 * bnx2x_cnic_notify - send command to cnic driver
239 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
242 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information
246 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
250 * bnx2x_int_enable - enable HW interrupts.
254 void bnx2x_int_enable(struct bnx2x *bp);
257 * bnx2x_int_disable_sync - disable interrupts.
260 * @disable_hw: true, disable HW interrupts.
262 * This function ensures that there are no
263 * ISRs or SP DPCs (sp_task) are running after it returns.
265 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
268 * bnx2x_nic_init - init driver internals.
271 * @load_code: COMMON, PORT or FUNCTION
278 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
281 * bnx2x_alloc_mem - allocate driver's memory.
285 int bnx2x_alloc_mem(struct bnx2x *bp);
288 * bnx2x_free_mem - release driver's memory.
292 void bnx2x_free_mem(struct bnx2x *bp);
295 * bnx2x_set_num_queues - set number of queues according to mode.
299 void bnx2x_set_num_queues(struct bnx2x *bp);
302 * bnx2x_chip_cleanup - cleanup chip internals.
305 * @unload_mode: COMMON, PORT, FUNCTION
307 * - Cleanup MAC configuration.
311 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
314 * bnx2x_acquire_hw_lock - acquire HW lock.
317 * @resource: resource bit which was locked
319 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
322 * bnx2x_release_hw_lock - release HW lock.
325 * @resource: resource bit which was locked
327 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
330 * bnx2x_release_leader_lock - release recovery leader lock
334 int bnx2x_release_leader_lock(struct bnx2x *bp);
337 * bnx2x_set_eth_mac - configure eth MAC address in the HW
342 * Configures according to the value in netdev->dev_addr.
344 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set);
347 * bnx2x_set_rx_mode - set MAC filtering configurations.
351 * called with netif_tx_lock from dev_mcast.c
352 * If bp->state is OPEN, should be called with
353 * netif_addr_lock_bh()
355 void bnx2x_set_rx_mode(struct net_device *dev);
358 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW.
362 * If bp->state is OPEN, should be called with
363 * netif_addr_lock_bh().
365 void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
368 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue.
372 * @rx_mode_flags: rx mode configuration
373 * @rx_accept_flags: rx accept configuration
374 * @tx_accept_flags: tx accept configuration (tx switch)
375 * @ramrod_flags: ramrod configuration
377 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
378 unsigned long rx_mode_flags,
379 unsigned long rx_accept_flags,
380 unsigned long tx_accept_flags,
381 unsigned long ramrod_flags);
383 /* Parity errors related */
384 void bnx2x_set_pf_load(struct bnx2x *bp);
385 bool bnx2x_clear_pf_load(struct bnx2x *bp);
386 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
387 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
388 void bnx2x_set_reset_in_progress(struct bnx2x *bp);
389 void bnx2x_set_reset_global(struct bnx2x *bp);
390 void bnx2x_disable_close_the_gate(struct bnx2x *bp);
393 * bnx2x_sp_event - handle ramrods completion.
395 * @fp: fastpath handle for the event
396 * @rr_cqe: eth_rx_cqe
398 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
401 * bnx2x_ilt_set_info - prepare ILT configurations.
405 void bnx2x_ilt_set_info(struct bnx2x *bp);
408 * bnx2x_dcbx_init - initialize dcbx protocol.
412 void bnx2x_dcbx_init(struct bnx2x *bp);
415 * bnx2x_set_power_state - set power state to the requested value.
418 * @state: required state D0 or D3hot
420 * Currently only D0 and D3hot are supported.
422 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
425 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW.
430 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
432 void bnx2x_panic_dump(struct bnx2x *bp);
434 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
436 /* validate currect fw is loaded */
437 bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err);
439 /* dev_close main block */
440 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
442 /* dev_open main block */
443 int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
445 /* hard_xmit callback */
446 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
448 /* setup_tc callback */
449 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc);
451 /* select_queue callback */
452 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
455 int bnx2x_reload_if_running(struct net_device *dev);
457 int bnx2x_change_mac_addr(struct net_device *dev, void *p);
459 /* NAPI poll Rx part */
460 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
462 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
463 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod);
465 /* NAPI poll Tx part */
466 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata);
468 /* suspend/resume callbacks */
469 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
470 int bnx2x_resume(struct pci_dev *pdev);
472 /* Release IRQ vectors */
473 void bnx2x_free_irq(struct bnx2x *bp);
475 void bnx2x_free_fp_mem(struct bnx2x *bp);
476 int bnx2x_alloc_fp_mem(struct bnx2x *bp);
477 void bnx2x_init_rx_rings(struct bnx2x *bp);
478 void bnx2x_free_skbs(struct bnx2x *bp);
479 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
480 void bnx2x_netif_start(struct bnx2x *bp);
483 * bnx2x_enable_msix - set msix configuration.
487 * fills msix_table, requests vectors, updates num_queues
488 * according to number of available vectors.
490 int __devinit bnx2x_enable_msix(struct bnx2x *bp);
493 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly
497 int bnx2x_enable_msi(struct bnx2x *bp);
500 * bnx2x_poll - NAPI callback
502 * @napi: napi structure
506 int bnx2x_poll(struct napi_struct *napi, int budget);
509 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure
513 int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp);
516 * bnx2x_free_mem_bp - release memories outsize main driver structure
520 void bnx2x_free_mem_bp(struct bnx2x *bp);
523 * bnx2x_change_mtu - change mtu netdev callback
526 * @new_mtu: requested mtu
529 int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
531 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
533 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port
536 * @wwn: output buffer
537 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port)
540 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type);
543 netdev_features_t bnx2x_fix_features(struct net_device *dev,
544 netdev_features_t features);
545 int bnx2x_set_features(struct net_device *dev, netdev_features_t features);
548 * bnx2x_tx_timeout - tx timeout netdev callback
552 void bnx2x_tx_timeout(struct net_device *dev);
554 /*********************** Inlines **********************************/
555 /*********************** Fast path ********************************/
556 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
558 barrier(); /* status block is written to by the chip */
559 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
562 static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp,
563 struct bnx2x_fastpath *fp, u16 bd_prod,
564 u16 rx_comp_prod, u16 rx_sge_prod, u32 start)
566 struct ustorm_eth_rx_producers rx_prods = {0};
569 /* Update producers */
570 rx_prods.bd_prod = bd_prod;
571 rx_prods.cqe_prod = rx_comp_prod;
572 rx_prods.sge_prod = rx_sge_prod;
575 * Make sure that the BD and SGE data is updated before updating the
576 * producers since FW might read the BD/SGE right after the producer
578 * This is only applicable for weak-ordered memory model archs such
579 * as IA-64. The following barrier is also mandatory since FW will
580 * assumes BDs must have buffers.
584 for (i = 0; i < sizeof(rx_prods)/4; i++)
585 REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]);
587 mmiowb(); /* keep prod updates ordered */
589 DP(NETIF_MSG_RX_STATUS,
590 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
591 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
594 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
595 u8 segment, u16 index, u8 op,
596 u8 update, u32 igu_addr)
598 struct igu_regular cmd_data = {0};
600 cmd_data.sb_id_and_flags =
601 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
602 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
603 (update << IGU_REGULAR_BUPDATE_SHIFT) |
604 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
606 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
607 cmd_data.sb_id_and_flags, igu_addr);
608 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
610 /* Make sure that ACK is written */
615 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
616 u8 storm, u16 index, u8 op, u8 update)
618 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
619 COMMAND_REG_INT_ACK);
620 struct igu_ack_register igu_ack;
622 igu_ack.status_block_index = index;
623 igu_ack.sb_id_and_flags =
624 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
625 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
626 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
627 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
629 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
631 /* Make sure that ACK is written */
636 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
637 u16 index, u8 op, u8 update)
639 if (bp->common.int_block == INT_BLOCK_HC)
640 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
644 if (CHIP_INT_MODE_IS_BC(bp))
646 else if (igu_sb_id != bp->igu_dsb_id)
647 segment = IGU_SEG_ACCESS_DEF;
648 else if (storm == ATTENTION_ID)
649 segment = IGU_SEG_ACCESS_ATTN;
651 segment = IGU_SEG_ACCESS_DEF;
652 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
656 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
658 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
659 COMMAND_REG_SIMD_MASK);
660 u32 result = REG_RD(bp, hc_addr);
666 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
668 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
669 u32 result = REG_RD(bp, igu_addr);
671 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
678 static inline u16 bnx2x_ack_int(struct bnx2x *bp)
681 if (bp->common.int_block == INT_BLOCK_HC)
682 return bnx2x_hc_ack_int(bp);
684 return bnx2x_igu_ack_int(bp);
687 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata)
689 /* Tell compiler that consumer and producer can change */
691 return txdata->tx_pkt_prod != txdata->tx_pkt_cons;
694 static inline u16 bnx2x_tx_avail(struct bnx2x *bp,
695 struct bnx2x_fp_txdata *txdata)
701 prod = txdata->tx_bd_prod;
702 cons = txdata->tx_bd_cons;
704 /* NUM_TX_RINGS = number of "next-page" entries
705 It will be used as a threshold */
706 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
708 #ifdef BNX2X_STOP_ON_ERROR
710 WARN_ON(used > bp->tx_ring_size);
711 WARN_ON((bp->tx_ring_size - used) > MAX_TX_AVAIL);
714 return (s16)(bp->tx_ring_size) - used;
717 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
721 /* Tell compiler that status block fields can change */
723 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
724 return hw_cons != txdata->tx_pkt_cons;
727 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
730 for_each_cos_in_tx_queue(fp, cos)
731 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
736 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
740 /* Tell compiler that status block fields can change */
742 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
743 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
745 return (fp->rx_comp_cons != rx_cons_sb);
749 * bnx2x_tx_disable - disables tx from stack point of view
753 static inline void bnx2x_tx_disable(struct bnx2x *bp)
755 netif_tx_disable(bp->dev);
756 netif_carrier_off(bp->dev);
759 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
760 struct bnx2x_fastpath *fp, u16 index)
762 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
763 struct page *page = sw_buf->page;
764 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
766 /* Skip "next page" elements */
770 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
771 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
772 __free_pages(page, PAGES_PER_SGE_SHIFT);
779 static inline void bnx2x_add_all_napi(struct bnx2x *bp)
783 /* Add NAPI objects */
784 for_each_rx_queue(bp, i)
785 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
786 bnx2x_poll, BNX2X_NAPI_WEIGHT);
789 static inline void bnx2x_del_all_napi(struct bnx2x *bp)
793 for_each_rx_queue(bp, i)
794 netif_napi_del(&bnx2x_fp(bp, i, napi));
797 static inline void bnx2x_disable_msi(struct bnx2x *bp)
799 if (bp->flags & USING_MSIX_FLAG) {
800 pci_disable_msix(bp->pdev);
801 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG);
802 } else if (bp->flags & USING_MSI_FLAG) {
803 pci_disable_msi(bp->pdev);
804 bp->flags &= ~USING_MSI_FLAG;
808 static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
811 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
812 min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp));
815 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
819 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
820 int idx = RX_SGE_CNT * i - 1;
822 for (j = 0; j < 2; j++) {
823 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
829 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
831 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
832 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
834 /* Clear the two last indices in the page to 1:
835 these are the indices that correspond to the "next" element,
836 hence will never be indicated and should be removed from
838 bnx2x_clear_sge_mask_next_elems(fp);
841 /* note that we are not allocating a new buffer,
842 * we are just moving one from cons to prod
843 * we are not creating a new mapping,
844 * so there is no need to check for dma_mapping_error().
846 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp,
849 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
850 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
851 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
852 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
854 dma_unmap_addr_set(prod_rx_buf, mapping,
855 dma_unmap_addr(cons_rx_buf, mapping));
856 prod_rx_buf->data = cons_rx_buf->data;
860 /************************* Init ******************************************/
862 /* returns func by VN for current port */
863 static inline int func_by_vn(struct bnx2x *bp, int vn)
865 return 2 * vn + BP_PORT(bp);
868 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash)
870 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash);
874 * bnx2x_func_start - init function
878 * Must be called before sending CLIENT_SETUP for the first client.
880 static inline int bnx2x_func_start(struct bnx2x *bp)
882 struct bnx2x_func_state_params func_params = {NULL};
883 struct bnx2x_func_start_params *start_params =
884 &func_params.params.start;
886 /* Prepare parameters for function state transitions */
887 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
889 func_params.f_obj = &bp->func_obj;
890 func_params.cmd = BNX2X_F_CMD_START;
892 /* Function parameters */
893 start_params->mf_mode = bp->mf_mode;
894 start_params->sd_vlan_tag = bp->mf_ov;
896 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
897 start_params->network_cos_mode = STATIC_COS;
898 else /* CHIP_IS_E1X */
899 start_params->network_cos_mode = FW_WRR;
901 return bnx2x_func_state_change(bp, &func_params);
906 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format
908 * @fw_hi: pointer to upper part
909 * @fw_mid: pointer to middle part
910 * @fw_lo: pointer to lower part
911 * @mac: pointer to MAC address
913 static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo,
916 ((u8 *)fw_hi)[0] = mac[1];
917 ((u8 *)fw_hi)[1] = mac[0];
918 ((u8 *)fw_mid)[0] = mac[3];
919 ((u8 *)fw_mid)[1] = mac[2];
920 ((u8 *)fw_lo)[0] = mac[5];
921 ((u8 *)fw_lo)[1] = mac[4];
924 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
925 struct bnx2x_fastpath *fp, int last)
932 for (i = 0; i < last; i++)
933 bnx2x_free_rx_sge(bp, fp, i);
936 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
940 for (i = 1; i <= NUM_RX_RINGS; i++) {
941 struct eth_rx_bd *rx_bd;
943 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
945 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
946 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
948 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
949 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
953 /* Statistics ID are global per chip/path, while Client IDs for E1x are per
956 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp)
958 struct bnx2x *bp = fp->bp;
959 if (!CHIP_IS_E1x(bp)) {
961 /* there are special statistics counters for FCoE 136..140 */
963 return bp->cnic_base_cl_id + (bp->pf_num >> 1);
967 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x;
970 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp,
971 bnx2x_obj_type obj_type)
973 struct bnx2x *bp = fp->bp;
975 /* Configure classification DBs */
976 bnx2x_init_mac_obj(bp, &fp->mac_obj, fp->cl_id, fp->cid,
977 BP_FUNC(bp), bnx2x_sp(bp, mac_rdata),
978 bnx2x_sp_mapping(bp, mac_rdata),
979 BNX2X_FILTER_MAC_PENDING,
980 &bp->sp_state, obj_type,
985 * bnx2x_get_path_func_num - get number of active functions
989 * Calculates the number of active (not hidden) functions on the
992 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp)
996 /* 57710 has only one function per-port */
1000 /* Calculate a number of functions enabled on the current
1003 if (CHIP_REV_IS_SLOW(bp)) {
1009 for (i = 0; i < E1H_FUNC_MAX / 2; i++) {
1012 func_mf_config[BP_PORT(bp) + 2 * i].
1015 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1);
1024 static inline void bnx2x_init_bp_objs(struct bnx2x *bp)
1026 /* RX_MODE controlling object */
1027 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj);
1029 /* multicast configuration controlling object */
1030 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid,
1031 BP_FUNC(bp), BP_FUNC(bp),
1032 bnx2x_sp(bp, mcast_rdata),
1033 bnx2x_sp_mapping(bp, mcast_rdata),
1034 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state,
1037 /* Setup CAM credit pools */
1038 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp),
1039 bnx2x_get_path_func_num(bp));
1041 /* RSS configuration object */
1042 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id,
1043 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp),
1044 bnx2x_sp(bp, rss_rdata),
1045 bnx2x_sp_mapping(bp, rss_rdata),
1046 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state,
1050 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
1052 if (CHIP_IS_E1x(fp->bp))
1053 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
1058 static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
1060 struct bnx2x *bp = fp->bp;
1062 if (!CHIP_IS_E1x(bp))
1063 return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
1065 return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
1068 static inline void bnx2x_init_txdata(struct bnx2x *bp,
1069 struct bnx2x_fp_txdata *txdata, u32 cid,
1070 int txq_index, __le16 *tx_cons_sb,
1071 struct bnx2x_fastpath *fp)
1074 txdata->txq_index = txq_index;
1075 txdata->tx_cons_sb = tx_cons_sb;
1076 txdata->parent_fp = fp;
1078 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n",
1079 txdata->cid, txdata->txq_index);
1083 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx)
1085 return bp->cnic_base_cl_id + cl_idx +
1086 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
1089 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
1092 /* the 'first' id is allocated for the cnic */
1093 return bp->base_fw_ndsb;
1096 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
1098 return bp->igu_base_sb;
1102 static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
1104 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
1105 unsigned long q_type = 0;
1107 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
1108 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
1109 BNX2X_FCOE_ETH_CL_ID_IDX);
1110 /** Current BNX2X_FCOE_ETH_CID deffinition implies not more than
1111 * 16 ETH clients per function when CNIC is enabled!
1115 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID;
1116 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
1117 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
1118 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
1119 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
1120 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
1123 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
1125 /* qZone id equals to FW (per path) client id */
1126 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
1128 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
1129 bnx2x_rx_ustorm_prods_offset(fp);
1131 /* Configure Queue State object */
1132 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
1133 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
1135 /* No multi-CoS for FCoE L2 client */
1136 BUG_ON(fp->max_cos != 1);
1138 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, &fp->cid, 1,
1139 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
1140 bnx2x_sp_mapping(bp, q_rdata), q_type);
1143 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
1144 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
1149 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
1150 struct bnx2x_fp_txdata *txdata)
1154 while (bnx2x_has_tx_work_unload(txdata)) {
1156 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1157 txdata->txq_index, txdata->tx_pkt_prod,
1158 txdata->tx_pkt_cons);
1159 #ifdef BNX2X_STOP_ON_ERROR
1167 usleep_range(1000, 1000);
1173 int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1175 static inline void __storm_memset_struct(struct bnx2x *bp,
1176 u32 addr, size_t size, u32 *data)
1179 for (i = 0; i < size/4; i++)
1180 REG_WR(bp, addr + (i * 4), data[i]);
1184 * bnx2x_wait_sp_comp - wait for the outstanding SP commands.
1186 * @bp: driver handle
1187 * @mask: bits that need to be cleared
1189 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
1191 int tout = 5000; /* Wait for 5 secs tops */
1195 netif_addr_lock_bh(bp->dev);
1196 if (!(bp->sp_state & mask)) {
1197 netif_addr_unlock_bh(bp->dev);
1200 netif_addr_unlock_bh(bp->dev);
1202 usleep_range(1000, 1000);
1207 netif_addr_lock_bh(bp->dev);
1208 if (bp->sp_state & mask) {
1209 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n",
1210 bp->sp_state, mask);
1211 netif_addr_unlock_bh(bp->dev);
1214 netif_addr_unlock_bh(bp->dev);
1220 * bnx2x_set_ctx_validation - set CDU context validation values
1222 * @bp: driver handle
1223 * @cxt: context of the connection on the host memory
1224 * @cid: SW CID of the connection to be configured
1226 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
1229 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
1230 u8 sb_index, u8 disable, u16 usec);
1231 void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1232 void bnx2x_release_phy_lock(struct bnx2x *bp);
1235 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration.
1237 * @bp: driver handle
1238 * @mf_cfg: MF configuration
1241 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
1243 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1244 FUNC_MF_CFG_MAX_BW_SHIFT;
1246 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
1247 "Max BW configured to 0 - using 100 instead\n");
1253 /* checks if HW supports GRO for given MTU */
1254 static inline bool bnx2x_mtu_allows_gro(int mtu)
1256 /* gro frags per page */
1257 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE);
1260 * 1. number of frags should not grow above MAX_SKB_FRAGS
1261 * 2. frag must fit the page
1263 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS;
1267 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info.
1269 * @bp: driver handle
1272 void bnx2x_get_iscsi_info(struct bnx2x *bp);
1276 * bnx2x_link_sync_notify - send notification to other functions.
1278 * @bp: driver handle
1281 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
1286 /* Set the attention towards other drivers on the same port */
1287 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
1288 if (vn == BP_VN(bp))
1291 func = func_by_vn(bp, vn);
1292 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
1293 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
1298 * bnx2x_update_drv_flags - update flags in shmem
1300 * @bp: driver handle
1301 * @flags: flags to update
1302 * @set: set or clear
1305 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set)
1307 if (SHMEM2_HAS(bp, drv_flags)) {
1309 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1310 drv_flags = SHMEM2_RD(bp, drv_flags);
1313 SET_FLAGS(drv_flags, flags);
1315 RESET_FLAGS(drv_flags, flags);
1317 SHMEM2_WR(bp, drv_flags, drv_flags);
1318 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags);
1319 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1323 static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr)
1325 if (is_valid_ether_addr(addr))
1328 if (is_zero_ether_addr(addr) &&
1329 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)))
1335 #endif /* BNX2X_CMN_H */