1 /* bnx2x_cmn.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
20 #include <linux/types.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
27 #include "bnx2x_sriov.h"
29 /* This is used as a replacement for an MCP if it's not present */
30 extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */
32 extern int num_queues;
35 /************************ Macros ********************************/
36 #define BNX2X_PCI_FREE(x, y, size) \
39 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
45 #define BNX2X_FREE(x) \
53 #define BNX2X_PCI_ALLOC(x, y, size) \
55 x = dma_alloc_coherent(&bp->pdev->dev, size, y, \
56 GFP_KERNEL | __GFP_ZERO); \
61 #define BNX2X_ALLOC(x, size) \
63 x = kzalloc(size, GFP_KERNEL); \
68 /*********************** Interfaces ****************************
69 * Functions that need to be implemented by each driver version
74 * bnx2x_send_unload_req - request unload mode from the MCP.
77 * @unload_mode: requested function's unload mode
79 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
81 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
84 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
87 * @keep_link: true iff link should be kept up
89 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link);
92 * bnx2x_config_rss_pf - configure RSS parameters in a PF.
95 * @rss_obj: RSS object to use
96 * @ind_table: indirection table to configure
97 * @config_hash: re-configure RSS hash keys configuration
99 int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
103 * bnx2x__init_func_obj - init function object
107 * Initializes the Function Object with the appropriate
108 * parameters which include a function slow path driver
111 void bnx2x__init_func_obj(struct bnx2x *bp);
114 * bnx2x_setup_queue - setup eth queue.
117 * @fp: pointer to the fastpath structure
121 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
125 * bnx2x_setup_leading - bring up a leading eth queue.
129 int bnx2x_setup_leading(struct bnx2x *bp);
132 * bnx2x_fw_command - send the MCP a request
136 * @param: request's parameter
138 * block until there is a reply
140 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
143 * bnx2x_initial_phy_init - initialize link parameters structure variables.
146 * @load_mode: current mode
148 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
151 * bnx2x_link_set - configure hw according to link parameters structure.
155 void bnx2x_link_set(struct bnx2x *bp);
158 * bnx2x_force_link_reset - Forces link reset, and put the PHY
163 void bnx2x_force_link_reset(struct bnx2x *bp);
166 * bnx2x_link_test - query link status.
171 * Returns 0 if link is UP.
173 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
176 * bnx2x_drv_pulse - write driver pulse to shmem
180 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox
183 void bnx2x_drv_pulse(struct bnx2x *bp);
186 * bnx2x_igu_ack_sb - update IGU with current SB value
190 * @segment: SB segment
193 * @update: is HW update required
195 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
196 u16 index, u8 op, u8 update);
198 /* Disable transactions from chip to host */
199 void bnx2x_pf_disable(struct bnx2x *bp);
200 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
203 * bnx2x__link_status_update - handles link status change.
207 void bnx2x__link_status_update(struct bnx2x *bp);
210 * bnx2x_link_report - report link status to upper layer.
214 void bnx2x_link_report(struct bnx2x *bp);
216 /* None-atomic version of bnx2x_link_report() */
217 void __bnx2x_link_report(struct bnx2x *bp);
220 * bnx2x_get_mf_speed - calculate MF speed.
224 * Takes into account current linespeed and MF configuration.
226 u16 bnx2x_get_mf_speed(struct bnx2x *bp);
229 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
232 * @dev_instance: private instance
234 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
237 * bnx2x_interrupt - non MSI-X interrupt handler
240 * @dev_instance: private instance
242 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
245 * bnx2x_cnic_notify - send command to cnic driver
250 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
253 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information
257 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
260 * bnx2x_setup_cnic_info - provides cnic with updated info
264 void bnx2x_setup_cnic_info(struct bnx2x *bp);
267 * bnx2x_int_enable - enable HW interrupts.
271 void bnx2x_int_enable(struct bnx2x *bp);
274 * bnx2x_int_disable_sync - disable interrupts.
277 * @disable_hw: true, disable HW interrupts.
279 * This function ensures that there are no
280 * ISRs or SP DPCs (sp_task) are running after it returns.
282 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
285 * bnx2x_nic_init_cnic - init driver internals for cnic.
288 * @load_code: COMMON, PORT or FUNCTION
295 void bnx2x_nic_init_cnic(struct bnx2x *bp);
298 * bnx2x_nic_init - init driver internals.
307 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
309 * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic.
313 int bnx2x_alloc_mem_cnic(struct bnx2x *bp);
315 * bnx2x_alloc_mem - allocate driver's memory.
319 int bnx2x_alloc_mem(struct bnx2x *bp);
322 * bnx2x_free_mem_cnic - release driver's memory for cnic.
326 void bnx2x_free_mem_cnic(struct bnx2x *bp);
328 * bnx2x_free_mem - release driver's memory.
332 void bnx2x_free_mem(struct bnx2x *bp);
335 * bnx2x_set_num_queues - set number of queues according to mode.
339 void bnx2x_set_num_queues(struct bnx2x *bp);
342 * bnx2x_chip_cleanup - cleanup chip internals.
345 * @unload_mode: COMMON, PORT, FUNCTION
346 * @keep_link: true iff link should be kept up.
348 * - Cleanup MAC configuration.
352 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link);
355 * bnx2x_acquire_hw_lock - acquire HW lock.
358 * @resource: resource bit which was locked
360 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
363 * bnx2x_release_hw_lock - release HW lock.
366 * @resource: resource bit which was locked
368 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
371 * bnx2x_release_leader_lock - release recovery leader lock
375 int bnx2x_release_leader_lock(struct bnx2x *bp);
378 * bnx2x_set_eth_mac - configure eth MAC address in the HW
383 * Configures according to the value in netdev->dev_addr.
385 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set);
388 * bnx2x_set_rx_mode - set MAC filtering configurations.
392 * called with netif_tx_lock from dev_mcast.c
393 * If bp->state is OPEN, should be called with
394 * netif_addr_lock_bh()
396 void bnx2x_set_rx_mode(struct net_device *dev);
399 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW.
403 * If bp->state is OPEN, should be called with
404 * netif_addr_lock_bh().
406 int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
409 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue.
413 * @rx_mode_flags: rx mode configuration
414 * @rx_accept_flags: rx accept configuration
415 * @tx_accept_flags: tx accept configuration (tx switch)
416 * @ramrod_flags: ramrod configuration
418 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
419 unsigned long rx_mode_flags,
420 unsigned long rx_accept_flags,
421 unsigned long tx_accept_flags,
422 unsigned long ramrod_flags);
424 /* Parity errors related */
425 void bnx2x_set_pf_load(struct bnx2x *bp);
426 bool bnx2x_clear_pf_load(struct bnx2x *bp);
427 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
428 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
429 void bnx2x_set_reset_in_progress(struct bnx2x *bp);
430 void bnx2x_set_reset_global(struct bnx2x *bp);
431 void bnx2x_disable_close_the_gate(struct bnx2x *bp);
432 int bnx2x_init_hw_func_cnic(struct bnx2x *bp);
435 * bnx2x_sp_event - handle ramrods completion.
437 * @fp: fastpath handle for the event
438 * @rr_cqe: eth_rx_cqe
440 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
443 * bnx2x_ilt_set_info - prepare ILT configurations.
447 void bnx2x_ilt_set_info(struct bnx2x *bp);
450 * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC
455 void bnx2x_ilt_set_info_cnic(struct bnx2x *bp);
458 * bnx2x_dcbx_init - initialize dcbx protocol.
462 void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem);
465 * bnx2x_set_power_state - set power state to the requested value.
468 * @state: required state D0 or D3hot
470 * Currently only D0 and D3hot are supported.
472 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
475 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW.
480 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
482 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
484 /* validate currect fw is loaded */
485 bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err);
487 /* dev_close main block */
488 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link);
490 /* dev_open main block */
491 int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
493 /* hard_xmit callback */
494 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
496 /* setup_tc callback */
497 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc);
499 int bnx2x_get_vf_config(struct net_device *dev, int vf,
500 struct ifla_vf_info *ivi);
501 int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac);
502 int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos);
504 /* select_queue callback */
505 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
507 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
508 struct bnx2x_fastpath *fp,
509 u16 bd_prod, u16 rx_comp_prod,
512 struct ustorm_eth_rx_producers rx_prods = {0};
515 /* Update producers */
516 rx_prods.bd_prod = bd_prod;
517 rx_prods.cqe_prod = rx_comp_prod;
518 rx_prods.sge_prod = rx_sge_prod;
520 /* Make sure that the BD and SGE data is updated before updating the
521 * producers since FW might read the BD/SGE right after the producer
523 * This is only applicable for weak-ordered memory model archs such
524 * as IA-64. The following barrier is also mandatory since FW will
525 * assumes BDs must have buffers.
529 for (i = 0; i < sizeof(rx_prods)/4; i++)
530 REG_WR(bp, fp->ustorm_rx_prods_offset + i*4,
531 ((u32 *)&rx_prods)[i]);
533 mmiowb(); /* keep prod updates ordered */
535 DP(NETIF_MSG_RX_STATUS,
536 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
537 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
541 int bnx2x_reload_if_running(struct net_device *dev);
543 int bnx2x_change_mac_addr(struct net_device *dev, void *p);
545 /* NAPI poll Rx part */
546 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
548 /* NAPI poll Tx part */
549 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata);
551 /* suspend/resume callbacks */
552 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
553 int bnx2x_resume(struct pci_dev *pdev);
555 /* Release IRQ vectors */
556 void bnx2x_free_irq(struct bnx2x *bp);
558 void bnx2x_free_fp_mem_cnic(struct bnx2x *bp);
559 void bnx2x_free_fp_mem(struct bnx2x *bp);
560 int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp);
561 int bnx2x_alloc_fp_mem(struct bnx2x *bp);
562 void bnx2x_init_rx_rings(struct bnx2x *bp);
563 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp);
564 void bnx2x_free_skbs_cnic(struct bnx2x *bp);
565 void bnx2x_free_skbs(struct bnx2x *bp);
566 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
567 void bnx2x_netif_start(struct bnx2x *bp);
568 int bnx2x_load_cnic(struct bnx2x *bp);
571 * bnx2x_enable_msix - set msix configuration.
575 * fills msix_table, requests vectors, updates num_queues
576 * according to number of available vectors.
578 int bnx2x_enable_msix(struct bnx2x *bp);
581 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly
585 int bnx2x_enable_msi(struct bnx2x *bp);
588 * bnx2x_poll - NAPI callback
590 * @napi: napi structure
594 int bnx2x_poll(struct napi_struct *napi, int budget);
597 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure
601 int bnx2x_alloc_mem_bp(struct bnx2x *bp);
604 * bnx2x_free_mem_bp - release memories outsize main driver structure
608 void bnx2x_free_mem_bp(struct bnx2x *bp);
611 * bnx2x_change_mtu - change mtu netdev callback
614 * @new_mtu: requested mtu
617 int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
619 #ifdef NETDEV_FCOE_WWNN
621 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port
624 * @wwn: output buffer
625 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port)
628 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type);
631 netdev_features_t bnx2x_fix_features(struct net_device *dev,
632 netdev_features_t features);
633 int bnx2x_set_features(struct net_device *dev, netdev_features_t features);
636 * bnx2x_tx_timeout - tx timeout netdev callback
640 void bnx2x_tx_timeout(struct net_device *dev);
642 /*********************** Inlines **********************************/
643 /*********************** Fast path ********************************/
644 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
646 barrier(); /* status block is written to by the chip */
647 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
650 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
651 u8 segment, u16 index, u8 op,
652 u8 update, u32 igu_addr)
654 struct igu_regular cmd_data = {0};
656 cmd_data.sb_id_and_flags =
657 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
658 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
659 (update << IGU_REGULAR_BUPDATE_SHIFT) |
660 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
662 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
663 cmd_data.sb_id_and_flags, igu_addr);
664 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
666 /* Make sure that ACK is written */
671 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
672 u8 storm, u16 index, u8 op, u8 update)
674 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
675 COMMAND_REG_INT_ACK);
676 struct igu_ack_register igu_ack;
678 igu_ack.status_block_index = index;
679 igu_ack.sb_id_and_flags =
680 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
681 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
682 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
683 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
685 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
687 /* Make sure that ACK is written */
692 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
693 u16 index, u8 op, u8 update)
695 if (bp->common.int_block == INT_BLOCK_HC)
696 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
700 if (CHIP_INT_MODE_IS_BC(bp))
702 else if (igu_sb_id != bp->igu_dsb_id)
703 segment = IGU_SEG_ACCESS_DEF;
704 else if (storm == ATTENTION_ID)
705 segment = IGU_SEG_ACCESS_ATTN;
707 segment = IGU_SEG_ACCESS_DEF;
708 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
712 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
714 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
715 COMMAND_REG_SIMD_MASK);
716 u32 result = REG_RD(bp, hc_addr);
722 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
724 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
725 u32 result = REG_RD(bp, igu_addr);
727 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
734 static inline u16 bnx2x_ack_int(struct bnx2x *bp)
737 if (bp->common.int_block == INT_BLOCK_HC)
738 return bnx2x_hc_ack_int(bp);
740 return bnx2x_igu_ack_int(bp);
743 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata)
745 /* Tell compiler that consumer and producer can change */
747 return txdata->tx_pkt_prod != txdata->tx_pkt_cons;
750 static inline u16 bnx2x_tx_avail(struct bnx2x *bp,
751 struct bnx2x_fp_txdata *txdata)
757 prod = txdata->tx_bd_prod;
758 cons = txdata->tx_bd_cons;
760 used = SUB_S16(prod, cons);
762 #ifdef BNX2X_STOP_ON_ERROR
764 WARN_ON(used > txdata->tx_ring_size);
765 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL);
768 return (s16)(txdata->tx_ring_size) - used;
771 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
775 /* Tell compiler that status block fields can change */
777 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
778 return hw_cons != txdata->tx_pkt_cons;
781 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
784 for_each_cos_in_tx_queue(fp, cos)
785 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
790 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
794 /* Tell compiler that status block fields can change */
796 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
797 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
799 return (fp->rx_comp_cons != rx_cons_sb);
803 * bnx2x_tx_disable - disables tx from stack point of view
807 static inline void bnx2x_tx_disable(struct bnx2x *bp)
809 netif_tx_disable(bp->dev);
810 netif_carrier_off(bp->dev);
813 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
814 struct bnx2x_fastpath *fp, u16 index)
816 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
817 struct page *page = sw_buf->page;
818 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
820 /* Skip "next page" elements */
824 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
825 SGE_PAGES, DMA_FROM_DEVICE);
826 __free_pages(page, PAGES_PER_SGE_SHIFT);
833 static inline void bnx2x_add_all_napi_cnic(struct bnx2x *bp)
837 /* Add NAPI objects */
838 for_each_rx_queue_cnic(bp, i)
839 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
840 bnx2x_poll, NAPI_POLL_WEIGHT);
843 static inline void bnx2x_add_all_napi(struct bnx2x *bp)
847 /* Add NAPI objects */
848 for_each_eth_queue(bp, i)
849 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
850 bnx2x_poll, NAPI_POLL_WEIGHT);
853 static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp)
857 for_each_rx_queue_cnic(bp, i)
858 netif_napi_del(&bnx2x_fp(bp, i, napi));
861 static inline void bnx2x_del_all_napi(struct bnx2x *bp)
865 for_each_eth_queue(bp, i)
866 netif_napi_del(&bnx2x_fp(bp, i, napi));
869 int bnx2x_set_int_mode(struct bnx2x *bp);
871 static inline void bnx2x_disable_msi(struct bnx2x *bp)
873 if (bp->flags & USING_MSIX_FLAG) {
874 pci_disable_msix(bp->pdev);
875 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG);
876 } else if (bp->flags & USING_MSI_FLAG) {
877 pci_disable_msi(bp->pdev);
878 bp->flags &= ~USING_MSI_FLAG;
882 static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
885 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
886 min_t(int, netif_get_num_default_rss_queues(),
887 BNX2X_MAX_QUEUES(bp));
890 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
894 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
895 int idx = RX_SGE_CNT * i - 1;
897 for (j = 0; j < 2; j++) {
898 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
904 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
906 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
907 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
909 /* Clear the two last indices in the page to 1:
910 these are the indices that correspond to the "next" element,
911 hence will never be indicated and should be removed from
913 bnx2x_clear_sge_mask_next_elems(fp);
916 /* note that we are not allocating a new buffer,
917 * we are just moving one from cons to prod
918 * we are not creating a new mapping,
919 * so there is no need to check for dma_mapping_error().
921 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp,
924 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
925 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
926 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
927 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
929 dma_unmap_addr_set(prod_rx_buf, mapping,
930 dma_unmap_addr(cons_rx_buf, mapping));
931 prod_rx_buf->data = cons_rx_buf->data;
935 /************************* Init ******************************************/
937 /* returns func by VN for current port */
938 static inline int func_by_vn(struct bnx2x *bp, int vn)
940 return 2 * vn + BP_PORT(bp);
943 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash)
945 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash);
949 * bnx2x_func_start - init function
953 * Must be called before sending CLIENT_SETUP for the first client.
955 static inline int bnx2x_func_start(struct bnx2x *bp)
957 struct bnx2x_func_state_params func_params = {NULL};
958 struct bnx2x_func_start_params *start_params =
959 &func_params.params.start;
961 /* Prepare parameters for function state transitions */
962 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
964 func_params.f_obj = &bp->func_obj;
965 func_params.cmd = BNX2X_F_CMD_START;
967 /* Function parameters */
968 start_params->mf_mode = bp->mf_mode;
969 start_params->sd_vlan_tag = bp->mf_ov;
971 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
972 start_params->network_cos_mode = STATIC_COS;
973 else /* CHIP_IS_E1X */
974 start_params->network_cos_mode = FW_WRR;
976 return bnx2x_func_state_change(bp, &func_params);
980 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format
982 * @fw_hi: pointer to upper part
983 * @fw_mid: pointer to middle part
984 * @fw_lo: pointer to lower part
985 * @mac: pointer to MAC address
987 static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
988 __le16 *fw_lo, u8 *mac)
990 ((u8 *)fw_hi)[0] = mac[1];
991 ((u8 *)fw_hi)[1] = mac[0];
992 ((u8 *)fw_mid)[0] = mac[3];
993 ((u8 *)fw_mid)[1] = mac[2];
994 ((u8 *)fw_lo)[0] = mac[5];
995 ((u8 *)fw_lo)[1] = mac[4];
998 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
999 struct bnx2x_fastpath *fp, int last)
1003 if (fp->disable_tpa)
1006 for (i = 0; i < last; i++)
1007 bnx2x_free_rx_sge(bp, fp, i);
1010 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
1014 for (i = 1; i <= NUM_RX_RINGS; i++) {
1015 struct eth_rx_bd *rx_bd;
1017 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
1019 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
1020 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1022 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
1023 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
1027 /* Statistics ID are global per chip/path, while Client IDs for E1x are per
1030 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp)
1032 struct bnx2x *bp = fp->bp;
1033 if (!CHIP_IS_E1x(bp)) {
1034 /* there are special statistics counters for FCoE 136..140 */
1036 return bp->cnic_base_cl_id + (bp->pf_num >> 1);
1039 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x;
1042 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp,
1043 bnx2x_obj_type obj_type)
1045 struct bnx2x *bp = fp->bp;
1047 /* Configure classification DBs */
1048 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id,
1049 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata),
1050 bnx2x_sp_mapping(bp, mac_rdata),
1051 BNX2X_FILTER_MAC_PENDING,
1052 &bp->sp_state, obj_type,
1057 * bnx2x_get_path_func_num - get number of active functions
1059 * @bp: driver handle
1061 * Calculates the number of active (not hidden) functions on the
1064 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp)
1068 /* 57710 has only one function per-port */
1072 /* Calculate a number of functions enabled on the current
1075 if (CHIP_REV_IS_SLOW(bp)) {
1081 for (i = 0; i < E1H_FUNC_MAX / 2; i++) {
1084 func_mf_config[BP_PORT(bp) + 2 * i].
1087 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1);
1096 static inline void bnx2x_init_bp_objs(struct bnx2x *bp)
1098 /* RX_MODE controlling object */
1099 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj);
1101 /* multicast configuration controlling object */
1102 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid,
1103 BP_FUNC(bp), BP_FUNC(bp),
1104 bnx2x_sp(bp, mcast_rdata),
1105 bnx2x_sp_mapping(bp, mcast_rdata),
1106 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state,
1109 /* Setup CAM credit pools */
1110 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp),
1111 bnx2x_get_path_func_num(bp));
1113 bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1,
1114 bnx2x_get_path_func_num(bp));
1116 /* RSS configuration object */
1117 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id,
1118 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp),
1119 bnx2x_sp(bp, rss_rdata),
1120 bnx2x_sp_mapping(bp, rss_rdata),
1121 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state,
1125 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
1127 if (CHIP_IS_E1x(fp->bp))
1128 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
1133 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
1135 static inline void bnx2x_init_txdata(struct bnx2x *bp,
1136 struct bnx2x_fp_txdata *txdata, u32 cid,
1137 int txq_index, __le16 *tx_cons_sb,
1138 struct bnx2x_fastpath *fp)
1141 txdata->txq_index = txq_index;
1142 txdata->tx_cons_sb = tx_cons_sb;
1143 txdata->parent_fp = fp;
1144 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size;
1146 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n",
1147 txdata->cid, txdata->txq_index);
1150 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx)
1152 return bp->cnic_base_cl_id + cl_idx +
1153 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
1156 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
1159 /* the 'first' id is allocated for the cnic */
1160 return bp->base_fw_ndsb;
1163 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
1165 return bp->igu_base_sb;
1169 static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
1171 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
1172 unsigned long q_type = 0;
1174 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
1175 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
1176 BNX2X_FCOE_ETH_CL_ID_IDX);
1177 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
1178 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
1179 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
1180 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
1181 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
1182 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
1185 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
1187 /* qZone id equals to FW (per path) client id */
1188 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
1190 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
1191 bnx2x_rx_ustorm_prods_offset(fp);
1193 /* Configure Queue State object */
1194 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
1195 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
1197 /* No multi-CoS for FCoE L2 client */
1198 BUG_ON(fp->max_cos != 1);
1200 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
1201 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
1202 bnx2x_sp_mapping(bp, q_rdata), q_type);
1205 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
1206 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
1210 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
1211 struct bnx2x_fp_txdata *txdata)
1215 while (bnx2x_has_tx_work_unload(txdata)) {
1217 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1218 txdata->txq_index, txdata->tx_pkt_prod,
1219 txdata->tx_pkt_cons);
1220 #ifdef BNX2X_STOP_ON_ERROR
1228 usleep_range(1000, 2000);
1234 int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1236 static inline void __storm_memset_struct(struct bnx2x *bp,
1237 u32 addr, size_t size, u32 *data)
1240 for (i = 0; i < size/4; i++)
1241 REG_WR(bp, addr + (i * 4), data[i]);
1245 * bnx2x_wait_sp_comp - wait for the outstanding SP commands.
1247 * @bp: driver handle
1248 * @mask: bits that need to be cleared
1250 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
1252 int tout = 5000; /* Wait for 5 secs tops */
1256 netif_addr_lock_bh(bp->dev);
1257 if (!(bp->sp_state & mask)) {
1258 netif_addr_unlock_bh(bp->dev);
1261 netif_addr_unlock_bh(bp->dev);
1263 usleep_range(1000, 2000);
1268 netif_addr_lock_bh(bp->dev);
1269 if (bp->sp_state & mask) {
1270 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n",
1271 bp->sp_state, mask);
1272 netif_addr_unlock_bh(bp->dev);
1275 netif_addr_unlock_bh(bp->dev);
1281 * bnx2x_set_ctx_validation - set CDU context validation values
1283 * @bp: driver handle
1284 * @cxt: context of the connection on the host memory
1285 * @cid: SW CID of the connection to be configured
1287 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
1290 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
1291 u8 sb_index, u8 disable, u16 usec);
1292 void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1293 void bnx2x_release_phy_lock(struct bnx2x *bp);
1296 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration.
1298 * @bp: driver handle
1299 * @mf_cfg: MF configuration
1302 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
1304 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1305 FUNC_MF_CFG_MAX_BW_SHIFT;
1307 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
1308 "Max BW configured to 0 - using 100 instead\n");
1314 /* checks if HW supports GRO for given MTU */
1315 static inline bool bnx2x_mtu_allows_gro(int mtu)
1317 /* gro frags per page */
1318 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE);
1321 * 1. number of frags should not grow above MAX_SKB_FRAGS
1322 * 2. frag must fit the page
1324 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS;
1328 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info.
1330 * @bp: driver handle
1333 void bnx2x_get_iscsi_info(struct bnx2x *bp);
1336 * bnx2x_link_sync_notify - send notification to other functions.
1338 * @bp: driver handle
1341 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
1346 /* Set the attention towards other drivers on the same port */
1347 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
1348 if (vn == BP_VN(bp))
1351 func = func_by_vn(bp, vn);
1352 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
1353 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
1358 * bnx2x_update_drv_flags - update flags in shmem
1360 * @bp: driver handle
1361 * @flags: flags to update
1362 * @set: set or clear
1365 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set)
1367 if (SHMEM2_HAS(bp, drv_flags)) {
1369 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1370 drv_flags = SHMEM2_RD(bp, drv_flags);
1373 SET_FLAGS(drv_flags, flags);
1375 RESET_FLAGS(drv_flags, flags);
1377 SHMEM2_WR(bp, drv_flags, drv_flags);
1378 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags);
1379 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1383 static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr)
1385 if (is_valid_ether_addr(addr) ||
1386 (is_zero_ether_addr(addr) &&
1387 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))))
1394 * bnx2x_fill_fw_str - Fill buffer with FW version string
1396 * @bp: driver handle
1397 * @buf: character buffer to fill with the fw name
1398 * @buf_len: length of the above buffer
1401 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len);
1402 #endif /* BNX2X_CMN_H */