drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/ethtool.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/types.h>
  23 #include <linux/sched.h>
  24 #include <linux/crc32.h>
  25 #include "bnx2x.h"
  26 #include "bnx2x_cmn.h"
  27 #include "bnx2x_dump.h"
  28 #include "bnx2x_init.h"
  29
  30 /* Note: in the format strings below %s is replaced by the queue-name which is
  31  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  32  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  33  */
  34 #define MAX_QUEUE_NAME_LEN      4
  35 static const struct {
  36         long offset;
  37         int size;
  38         char string[ETH_GSTRING_LEN];
  39 } bnx2x_q_stats_arr[] = {
  40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  41         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  42                                                 8, "[%s]: rx_ucast_packets" },
  43         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  44                                                 8, "[%s]: rx_mcast_packets" },
  45         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  46                                                 8, "[%s]: rx_bcast_packets" },
  47         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  48         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  49                                          4, "[%s]: rx_phy_ip_err_discards"},
  50         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  51                                          4, "[%s]: rx_skb_alloc_discard" },
  52         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  53
  54         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  56                                                 8, "[%s]: tx_ucast_packets" },
  57         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  58                                                 8, "[%s]: tx_mcast_packets" },
  59         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  60                                                 8, "[%s]: tx_bcast_packets" },
  61         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  62                                                 8, "[%s]: tpa_aggregations" },
  63         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  64                                         8, "[%s]: tpa_aggregated_frames"},
  65         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
  66         { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
  67                                         4, "[%s]: driver_filtered_tx_pkt" }
  68 };
  69
  70 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  71
  72 static const struct {
  73         long offset;
  74         int size;
  75         u32 flags;
  76 #define STATS_FLAGS_PORT                1
  77 #define STATS_FLAGS_FUNC                2
  78 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  79         char string[ETH_GSTRING_LEN];
  80 } bnx2x_stats_arr[] = {
  81 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  82                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  83         { STATS_OFFSET32(error_bytes_received_hi),
  84                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  85         { STATS_OFFSET32(total_unicast_packets_received_hi),
  86                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  87         { STATS_OFFSET32(total_multicast_packets_received_hi),
  88                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  89         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  90                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  91         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  92                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  93         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  94                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  95         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  96                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  97         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  98                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  99 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
 100                                 8, STATS_FLAGS_PORT, "rx_fragments" },
 101         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 102                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 103         { STATS_OFFSET32(no_buff_discard_hi),
 104                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 105         { STATS_OFFSET32(mac_filter_discard),
 106                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 107         { STATS_OFFSET32(mf_tag_discard),
 108                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 109         { STATS_OFFSET32(pfc_frames_received_hi),
 110                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
 111         { STATS_OFFSET32(pfc_frames_sent_hi),
 112                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
 113         { STATS_OFFSET32(brb_drop_hi),
 114                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 115         { STATS_OFFSET32(brb_truncate_hi),
 116                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 117         { STATS_OFFSET32(pause_frames_received_hi),
 118                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 119         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 120                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 121         { STATS_OFFSET32(nig_timer_max),
 122                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 123 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 124                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 125         { STATS_OFFSET32(rx_skb_alloc_failed),
 126                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 127         { STATS_OFFSET32(hw_csum_err),
 128                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 129
 130         { STATS_OFFSET32(total_bytes_transmitted_hi),
 131                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 132         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 133                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 134         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 135                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 136         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 137                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 138         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 139                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 140         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 141                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 142         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 143                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 145                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 146         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 147                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 148         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 149                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 150         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 151                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 152         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 153                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 154         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 155                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 156         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 157                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 158         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 159                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 160         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 161                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 162         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 163                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 165                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 166         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 167                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 168         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 169                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 170         { STATS_OFFSET32(pause_frames_sent_hi),
 171                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 172         { STATS_OFFSET32(total_tpa_aggregations_hi),
 173                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 174         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 175                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 176         { STATS_OFFSET32(total_tpa_bytes_hi),
 177                         8, STATS_FLAGS_FUNC, "tpa_bytes"},
 178         { STATS_OFFSET32(recoverable_error),
 179                         4, STATS_FLAGS_FUNC, "recoverable_errors" },
 180         { STATS_OFFSET32(unrecoverable_error),
 181                         4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
 182         { STATS_OFFSET32(driver_filtered_tx_pkt),
 183                         4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
 184         { STATS_OFFSET32(eee_tx_lpi),
 185                         4, STATS_FLAGS_PORT, "Tx LPI entry count"}
 186 };
 187
 188 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 189
 190 static int bnx2x_get_port_type(struct bnx2x *bp)
 191 {
 192         int port_type;
 193         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 194         switch (bp->link_params.phy[phy_idx].media_type) {
 195         case ETH_PHY_SFPP_10G_FIBER:
 196         case ETH_PHY_SFP_1G_FIBER:
 197         case ETH_PHY_XFP_FIBER:
 198         case ETH_PHY_KR:
 199         case ETH_PHY_CX4:
 200                 port_type = PORT_FIBRE;
 201                 break;
 202         case ETH_PHY_DA_TWINAX:
 203                 port_type = PORT_DA;
 204                 break;
 205         case ETH_PHY_BASE_T:
 206                 port_type = PORT_TP;
 207                 break;
 208         case ETH_PHY_NOT_PRESENT:
 209                 port_type = PORT_NONE;
 210                 break;
 211         case ETH_PHY_UNSPECIFIED:
 212         default:
 213                 port_type = PORT_OTHER;
 214                 break;
 215         }
 216         return port_type;
 217 }
 218
 219 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 220 {
 221         struct bnx2x *bp = netdev_priv(dev);
 222         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 223
 224         /* Dual Media boards present all available port types */
 225         cmd->supported = bp->port.supported[cfg_idx] |
 226                 (bp->port.supported[cfg_idx ^ 1] &
 227                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 228         cmd->advertising = bp->port.advertising[cfg_idx];
 229         if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
 230             ETH_PHY_SFP_1G_FIBER) {
 231                 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
 232                 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
 233         }
 234
 235         if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
 236             !(bp->flags & MF_FUNC_DIS)) {
 237                         cmd->duplex = bp->link_vars.duplex;
 238
 239                 if (IS_MF(bp) && !BP_NOMCP(bp))
 240                         ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 241                 else
 242                         ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 243         } else {
 244                 cmd->duplex = DUPLEX_UNKNOWN;
 245                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 246         }
 247
 248         cmd->port = bnx2x_get_port_type(bp);
 249
 250         cmd->phy_address = bp->mdio.prtad;
 251         cmd->transceiver = XCVR_INTERNAL;
 252
 253         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 254                 cmd->autoneg = AUTONEG_ENABLE;
 255         else
 256                 cmd->autoneg = AUTONEG_DISABLE;
 257
 258         /* Publish LP advertised speeds and FC */
 259         if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
 260                 u32 status = bp->link_vars.link_status;
 261
 262                 cmd->lp_advertising |= ADVERTISED_Autoneg;
 263                 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
 264                         cmd->lp_advertising |= ADVERTISED_Pause;
 265                 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 266                         cmd->lp_advertising |= ADVERTISED_Asym_Pause;
 267
 268                 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
 269                         cmd->lp_advertising |= ADVERTISED_10baseT_Half;
 270                 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
 271                         cmd->lp_advertising |= ADVERTISED_10baseT_Full;
 272                 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
 273                         cmd->lp_advertising |= ADVERTISED_100baseT_Half;
 274                 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
 275                         cmd->lp_advertising |= ADVERTISED_100baseT_Full;
 276                 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
 277                         cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
 278                 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
 279                         cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
 280                 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
 281                         cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
 282                 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
 283                         cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
 284         }
 285
 286         cmd->maxtxpkt = 0;
 287         cmd->maxrxpkt = 0;
 288
 289         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 290            "  supported 0x%x  advertising 0x%x  speed %u\n"
 291            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 292            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 293            cmd->cmd, cmd->supported, cmd->advertising,
 294            ethtool_cmd_speed(cmd),
 295            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 296            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 297
 298         return 0;
 299 }
 300
 301 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 302 {
 303         struct bnx2x *bp = netdev_priv(dev);
 304         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 305         u32 speed, phy_idx;
 306
 307         if (IS_MF_SD(bp))
 308                 return 0;
 309
 310         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 311            "  supported 0x%x  advertising 0x%x  speed %u\n"
 312            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 313            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 314            cmd->cmd, cmd->supported, cmd->advertising,
 315            ethtool_cmd_speed(cmd),
 316            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 317            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 318
 319         speed = ethtool_cmd_speed(cmd);
 320
 321         /* If recieved a request for an unknown duplex, assume full*/
 322         if (cmd->duplex == DUPLEX_UNKNOWN)
 323                 cmd->duplex = DUPLEX_FULL;
 324
 325         if (IS_MF_SI(bp)) {
 326                 u32 part;
 327                 u32 line_speed = bp->link_vars.line_speed;
 328
 329                 /* use 10G if no link detected */
 330                 if (!line_speed)
 331                         line_speed = 10000;
 332
 333                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 334                         DP(BNX2X_MSG_ETHTOOL,
 335                            "To set speed BC %X or higher is required, please upgrade BC\n",
 336                            REQ_BC_VER_4_SET_MF_BW);
 337                         return -EINVAL;
 338                 }
 339
 340                 part = (speed * 100) / line_speed;
 341
 342                 if (line_speed < speed || !part) {
 343                         DP(BNX2X_MSG_ETHTOOL,
 344                            "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
 345                         return -EINVAL;
 346                 }
 347
 348                 if (bp->state != BNX2X_STATE_OPEN)
 349                         /* store value for following "load" */
 350                         bp->pending_max = part;
 351                 else
 352                         bnx2x_update_max_mf_config(bp, part);
 353
 354                 return 0;
 355         }
 356
 357         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 358         old_multi_phy_config = bp->link_params.multi_phy_config;
 359         switch (cmd->port) {
 360         case PORT_TP:
 361                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 362                         break; /* no port change */
 363
 364                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 365                       bp->port.supported[1] & SUPPORTED_TP)) {
 366                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 367                         return -EINVAL;
 368                 }
 369                 bp->link_params.multi_phy_config &=
 370                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 371                 if (bp->link_params.multi_phy_config &
 372                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 373                         bp->link_params.multi_phy_config |=
 374                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 375                 else
 376                         bp->link_params.multi_phy_config |=
 377                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 378                 break;
 379         case PORT_FIBRE:
 380         case PORT_DA:
 381                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 382                         break; /* no port change */
 383
 384                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 385                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 386                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 387                         return -EINVAL;
 388                 }
 389                 bp->link_params.multi_phy_config &=
 390                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 391                 if (bp->link_params.multi_phy_config &
 392                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 393                         bp->link_params.multi_phy_config |=
 394                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 395                 else
 396                         bp->link_params.multi_phy_config |=
 397                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 398                 break;
 399         default:
 400                 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 401                 return -EINVAL;
 402         }
 403         /* Save new config in case command complete successully */
 404         new_multi_phy_config = bp->link_params.multi_phy_config;
 405         /* Get the new cfg_idx */
 406         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 407         /* Restore old config in case command failed */
 408         bp->link_params.multi_phy_config = old_multi_phy_config;
 409         DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 410
 411         if (cmd->autoneg == AUTONEG_ENABLE) {
 412                 u32 an_supported_speed = bp->port.supported[cfg_idx];
 413                 if (bp->link_params.phy[EXT_PHY1].type ==
 414                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 415                         an_supported_speed |= (SUPPORTED_100baseT_Half |
 416                                                SUPPORTED_100baseT_Full);
 417                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 418                         DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
 419                         return -EINVAL;
 420                 }
 421
 422                 /* advertise the requested speed and duplex if supported */
 423                 if (cmd->advertising & ~an_supported_speed) {
 424                         DP(BNX2X_MSG_ETHTOOL,
 425                            "Advertisement parameters are not supported\n");
 426                         return -EINVAL;
 427                 }
 428
 429                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 430                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 431                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 432                                          cmd->advertising);
 433                 if (cmd->advertising) {
 434
 435                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 436                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 437                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 438                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 439                         }
 440                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 441                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 442                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 443
 444                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 445                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 446                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 447
 448                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 449                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 450                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 451                         }
 452                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 453                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 454                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 455                         }
 456                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 457                                                 ADVERTISED_1000baseKX_Full))
 458                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 459                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 460
 461                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 462                                                 ADVERTISED_10000baseKX4_Full |
 463                                                 ADVERTISED_10000baseKR_Full))
 464                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 465                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 466                 }
 467         } else { /* forced speed */
 468                 /* advertise the requested speed and duplex if supported */
 469                 switch (speed) {
 470                 case SPEED_10:
 471                         if (cmd->duplex == DUPLEX_FULL) {
 472                                 if (!(bp->port.supported[cfg_idx] &
 473                                       SUPPORTED_10baseT_Full)) {
 474                                         DP(BNX2X_MSG_ETHTOOL,
 475                                            "10M full not supported\n");
 476                                         return -EINVAL;
 477                                 }
 478
 479                                 advertising = (ADVERTISED_10baseT_Full |
 480                                                ADVERTISED_TP);
 481                         } else {
 482                                 if (!(bp->port.supported[cfg_idx] &
 483                                       SUPPORTED_10baseT_Half)) {
 484                                         DP(BNX2X_MSG_ETHTOOL,
 485                                            "10M half not supported\n");
 486                                         return -EINVAL;
 487                                 }
 488
 489                                 advertising = (ADVERTISED_10baseT_Half |
 490                                                ADVERTISED_TP);
 491                         }
 492                         break;
 493
 494                 case SPEED_100:
 495                         if (cmd->duplex == DUPLEX_FULL) {
 496                                 if (!(bp->port.supported[cfg_idx] &
 497                                                 SUPPORTED_100baseT_Full)) {
 498                                         DP(BNX2X_MSG_ETHTOOL,
 499                                            "100M full not supported\n");
 500                                         return -EINVAL;
 501                                 }
 502
 503                                 advertising = (ADVERTISED_100baseT_Full |
 504                                                ADVERTISED_TP);
 505                         } else {
 506                                 if (!(bp->port.supported[cfg_idx] &
 507                                                 SUPPORTED_100baseT_Half)) {
 508                                         DP(BNX2X_MSG_ETHTOOL,
 509                                            "100M half not supported\n");
 510                                         return -EINVAL;
 511                                 }
 512
 513                                 advertising = (ADVERTISED_100baseT_Half |
 514                                                ADVERTISED_TP);
 515                         }
 516                         break;
 517
 518                 case SPEED_1000:
 519                         if (cmd->duplex != DUPLEX_FULL) {
 520                                 DP(BNX2X_MSG_ETHTOOL,
 521                                    "1G half not supported\n");
 522                                 return -EINVAL;
 523                         }
 524
 525                         if (!(bp->port.supported[cfg_idx] &
 526                               SUPPORTED_1000baseT_Full)) {
 527                                 DP(BNX2X_MSG_ETHTOOL,
 528                                    "1G full not supported\n");
 529                                 return -EINVAL;
 530                         }
 531
 532                         advertising = (ADVERTISED_1000baseT_Full |
 533                                        ADVERTISED_TP);
 534                         break;
 535
 536                 case SPEED_2500:
 537                         if (cmd->duplex != DUPLEX_FULL) {
 538                                 DP(BNX2X_MSG_ETHTOOL,
 539                                    "2.5G half not supported\n");
 540                                 return -EINVAL;
 541                         }
 542
 543                         if (!(bp->port.supported[cfg_idx]
 544                               & SUPPORTED_2500baseX_Full)) {
 545                                 DP(BNX2X_MSG_ETHTOOL,
 546                                    "2.5G full not supported\n");
 547                                 return -EINVAL;
 548                         }
 549
 550                         advertising = (ADVERTISED_2500baseX_Full |
 551                                        ADVERTISED_TP);
 552                         break;
 553
 554                 case SPEED_10000:
 555                         if (cmd->duplex != DUPLEX_FULL) {
 556                                 DP(BNX2X_MSG_ETHTOOL,
 557                                    "10G half not supported\n");
 558                                 return -EINVAL;
 559                         }
 560                         phy_idx = bnx2x_get_cur_phy_idx(bp);
 561                         if (!(bp->port.supported[cfg_idx]
 562                               & SUPPORTED_10000baseT_Full) ||
 563                             (bp->link_params.phy[phy_idx].media_type ==
 564                              ETH_PHY_SFP_1G_FIBER)) {
 565                                 DP(BNX2X_MSG_ETHTOOL,
 566                                    "10G full not supported\n");
 567                                 return -EINVAL;
 568                         }
 569
 570                         advertising = (ADVERTISED_10000baseT_Full |
 571                                        ADVERTISED_FIBRE);
 572                         break;
 573
 574                 default:
 575                         DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
 576                         return -EINVAL;
 577                 }
 578
 579                 bp->link_params.req_line_speed[cfg_idx] = speed;
 580                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 581                 bp->port.advertising[cfg_idx] = advertising;
 582         }
 583
 584         DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
 585            "  req_duplex %d  advertising 0x%x\n",
 586            bp->link_params.req_line_speed[cfg_idx],
 587            bp->link_params.req_duplex[cfg_idx],
 588            bp->port.advertising[cfg_idx]);
 589
 590         /* Set new config */
 591         bp->link_params.multi_phy_config = new_multi_phy_config;
 592         if (netif_running(dev)) {
 593                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 594                 bnx2x_link_set(bp);
 595         }
 596
 597         return 0;
 598 }
 599
 600 #define DUMP_ALL_PRESETS                0x1FFF
 601 #define DUMP_MAX_PRESETS                13
 602
 603 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
 604 {
 605         if (CHIP_IS_E1(bp))
 606                 return dump_num_registers[0][preset-1];
 607         else if (CHIP_IS_E1H(bp))
 608                 return dump_num_registers[1][preset-1];
 609         else if (CHIP_IS_E2(bp))
 610                 return dump_num_registers[2][preset-1];
 611         else if (CHIP_IS_E3A0(bp))
 612                 return dump_num_registers[3][preset-1];
 613         else if (CHIP_IS_E3B0(bp))
 614                 return dump_num_registers[4][preset-1];
 615         else
 616                 return 0;
 617 }
 618
 619 static int __bnx2x_get_regs_len(struct bnx2x *bp)
 620 {
 621         u32 preset_idx;
 622         int regdump_len = 0;
 623
 624         /* Calculate the total preset regs length */
 625         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
 626                 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
 627
 628         return regdump_len;
 629 }
 630
 631 static int bnx2x_get_regs_len(struct net_device *dev)
 632 {
 633         struct bnx2x *bp = netdev_priv(dev);
 634         int regdump_len = 0;
 635
 636         regdump_len = __bnx2x_get_regs_len(bp);
 637         regdump_len *= 4;
 638         regdump_len += sizeof(struct dump_header);
 639
 640         return regdump_len;
 641 }
 642
 643 #define IS_E1_REG(chips)        ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
 644 #define IS_E1H_REG(chips)       ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
 645 #define IS_E2_REG(chips)        ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
 646 #define IS_E3A0_REG(chips)      ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
 647 #define IS_E3B0_REG(chips)      ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
 648
 649 #define IS_REG_IN_PRESET(presets, idx)  \
 650                 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
 651
 652 /******* Paged registers info selectors ********/
 653 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 654 {
 655         if (CHIP_IS_E2(bp))
 656                 return page_vals_e2;
 657         else if (CHIP_IS_E3(bp))
 658                 return page_vals_e3;
 659         else
 660                 return NULL;
 661 }
 662
 663 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 664 {
 665         if (CHIP_IS_E2(bp))
 666                 return PAGE_MODE_VALUES_E2;
 667         else if (CHIP_IS_E3(bp))
 668                 return PAGE_MODE_VALUES_E3;
 669         else
 670                 return 0;
 671 }
 672
 673 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 674 {
 675         if (CHIP_IS_E2(bp))
 676                 return page_write_regs_e2;
 677         else if (CHIP_IS_E3(bp))
 678                 return page_write_regs_e3;
 679         else
 680                 return NULL;
 681 }
 682
 683 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 684 {
 685         if (CHIP_IS_E2(bp))
 686                 return PAGE_WRITE_REGS_E2;
 687         else if (CHIP_IS_E3(bp))
 688                 return PAGE_WRITE_REGS_E3;
 689         else
 690                 return 0;
 691 }
 692
 693 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 694 {
 695         if (CHIP_IS_E2(bp))
 696                 return page_read_regs_e2;
 697         else if (CHIP_IS_E3(bp))
 698                 return page_read_regs_e3;
 699         else
 700                 return NULL;
 701 }
 702
 703 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 704 {
 705         if (CHIP_IS_E2(bp))
 706                 return PAGE_READ_REGS_E2;
 707         else if (CHIP_IS_E3(bp))
 708                 return PAGE_READ_REGS_E3;
 709         else
 710                 return 0;
 711 }
 712
 713 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
 714                                        const struct reg_addr *reg_info)
 715 {
 716         if (CHIP_IS_E1(bp))
 717                 return IS_E1_REG(reg_info->chips);
 718         else if (CHIP_IS_E1H(bp))
 719                 return IS_E1H_REG(reg_info->chips);
 720         else if (CHIP_IS_E2(bp))
 721                 return IS_E2_REG(reg_info->chips);
 722         else if (CHIP_IS_E3A0(bp))
 723                 return IS_E3A0_REG(reg_info->chips);
 724         else if (CHIP_IS_E3B0(bp))
 725                 return IS_E3B0_REG(reg_info->chips);
 726         else
 727                 return false;
 728 }
 729
 730
 731 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
 732         const struct wreg_addr *wreg_info)
 733 {
 734         if (CHIP_IS_E1(bp))
 735                 return IS_E1_REG(wreg_info->chips);
 736         else if (CHIP_IS_E1H(bp))
 737                 return IS_E1H_REG(wreg_info->chips);
 738         else if (CHIP_IS_E2(bp))
 739                 return IS_E2_REG(wreg_info->chips);
 740         else if (CHIP_IS_E3A0(bp))
 741                 return IS_E3A0_REG(wreg_info->chips);
 742         else if (CHIP_IS_E3B0(bp))
 743                 return IS_E3B0_REG(wreg_info->chips);
 744         else
 745                 return false;
 746 }
 747
 748 /**
 749  * bnx2x_read_pages_regs - read "paged" registers
 750  *
 751  * @bp          device handle
 752  * @p           output buffer
 753  *
 754  * Reads "paged" memories: memories that may only be read by
 755  * first writing to a specific address ("write address") and
 756  * then reading from a specific address ("read address"). There
 757  * may be more than one write address per "page" and more than
 758  * one read address per write address.
 759  */
 760 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
 761 {
 762         u32 i, j, k, n;
 763
 764         /* addresses of the paged registers */
 765         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 766         /* number of paged registers */
 767         int num_pages = __bnx2x_get_page_reg_num(bp);
 768         /* write addresses */
 769         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 770         /* number of write addresses */
 771         int write_num = __bnx2x_get_page_write_num(bp);
 772         /* read addresses info */
 773         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 774         /* number of read addresses */
 775         int read_num = __bnx2x_get_page_read_num(bp);
 776         u32 addr, size;
 777
 778         for (i = 0; i < num_pages; i++) {
 779                 for (j = 0; j < write_num; j++) {
 780                         REG_WR(bp, write_addr[j], page_addr[i]);
 781
 782                         for (k = 0; k < read_num; k++) {
 783                                 if (IS_REG_IN_PRESET(read_addr[k].presets,
 784                                                      preset)) {
 785                                         size = read_addr[k].size;
 786                                         for (n = 0; n < size; n++) {
 787                                                 addr = read_addr[k].addr + n*4;
 788                                                 *p++ = REG_RD(bp, addr);
 789                                         }
 790                                 }
 791                         }
 792                 }
 793         }
 794 }
 795
 796 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
 797 {
 798         u32 i, j, addr;
 799         const struct wreg_addr *wreg_addr_p = NULL;
 800
 801         if (CHIP_IS_E1(bp))
 802                 wreg_addr_p = &wreg_addr_e1;
 803         else if (CHIP_IS_E1H(bp))
 804                 wreg_addr_p = &wreg_addr_e1h;
 805         else if (CHIP_IS_E2(bp))
 806                 wreg_addr_p = &wreg_addr_e2;
 807         else if (CHIP_IS_E3A0(bp))
 808                 wreg_addr_p = &wreg_addr_e3;
 809         else if (CHIP_IS_E3B0(bp))
 810                 wreg_addr_p = &wreg_addr_e3b0;
 811
 812         /* Read the idle_chk registers */
 813         for (i = 0; i < IDLE_REGS_COUNT; i++) {
 814                 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
 815                     IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
 816                         for (j = 0; j < idle_reg_addrs[i].size; j++)
 817                                 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
 818                 }
 819         }
 820
 821         /* Read the regular registers */
 822         for (i = 0; i < REGS_COUNT; i++) {
 823                 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
 824                     IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
 825                         for (j = 0; j < reg_addrs[i].size; j++)
 826                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 827                 }
 828         }
 829
 830         /* Read the CAM registers */
 831         if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
 832             IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
 833                 for (i = 0; i < wreg_addr_p->size; i++) {
 834                         *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
 835
 836                         /* In case of wreg_addr register, read additional
 837                            registers from read_regs array
 838                         */
 839                         for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
 840                                 addr = *(wreg_addr_p->read_regs);
 841                                 *p++ = REG_RD(bp, addr + j*4);
 842                         }
 843                 }
 844         }
 845
 846         /* Paged registers are supported in E2 & E3 only */
 847         if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
 848                 /* Read "paged" registes */
 849                 bnx2x_read_pages_regs(bp, p, preset);
 850         }
 851
 852         return 0;
 853 }
 854
 855 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 856 {
 857         u32 preset_idx;
 858
 859         /* Read all registers, by reading all preset registers */
 860         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
 861                 /* Skip presets with IOR */
 862                 if ((preset_idx == 2) ||
 863                     (preset_idx == 5) ||
 864                     (preset_idx == 8) ||
 865                     (preset_idx == 11))
 866                         continue;
 867                 __bnx2x_get_preset_regs(bp, p, preset_idx);
 868                 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
 869         }
 870 }
 871
 872 static void bnx2x_get_regs(struct net_device *dev,
 873                            struct ethtool_regs *regs, void *_p)
 874 {
 875         u32 *p = _p;
 876         struct bnx2x *bp = netdev_priv(dev);
 877         struct dump_header dump_hdr = {0};
 878
 879         regs->version = 2;
 880         memset(p, 0, regs->len);
 881
 882         if (!netif_running(bp->dev))
 883                 return;
 884
 885         /* Disable parity attentions as long as following dump may
 886          * cause false alarms by reading never written registers. We
 887          * will re-enable parity attentions right after the dump.
 888          */
 889
 890         /* Disable parity on path 0 */
 891         bnx2x_pretend_func(bp, 0);
 892         bnx2x_disable_blocks_parity(bp);
 893
 894         /* Disable parity on path 1 */
 895         bnx2x_pretend_func(bp, 1);
 896         bnx2x_disable_blocks_parity(bp);
 897
 898         /* Return to current function */
 899         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
 900
 901         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
 902         dump_hdr.preset = DUMP_ALL_PRESETS;
 903         dump_hdr.version = BNX2X_DUMP_VERSION;
 904
 905         /* dump_meta_data presents OR of CHIP and PATH. */
 906         if (CHIP_IS_E1(bp)) {
 907                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
 908         } else if (CHIP_IS_E1H(bp)) {
 909                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
 910         } else if (CHIP_IS_E2(bp)) {
 911                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
 912                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 913         } else if (CHIP_IS_E3A0(bp)) {
 914                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
 915                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 916         } else if (CHIP_IS_E3B0(bp)) {
 917                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
 918                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 919         }
 920
 921         memcpy(p, &dump_hdr, sizeof(struct dump_header));
 922         p += dump_hdr.header_size + 1;
 923
 924         /* Actually read the registers */
 925         __bnx2x_get_regs(bp, p);
 926
 927         /* Re-enable parity attentions on path 0 */
 928         bnx2x_pretend_func(bp, 0);
 929         bnx2x_clear_blocks_parity(bp);
 930         bnx2x_enable_blocks_parity(bp);
 931
 932         /* Re-enable parity attentions on path 1 */
 933         bnx2x_pretend_func(bp, 1);
 934         bnx2x_clear_blocks_parity(bp);
 935         bnx2x_enable_blocks_parity(bp);
 936
 937         /* Return to current function */
 938         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
 939 }
 940
 941 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
 942 {
 943         struct bnx2x *bp = netdev_priv(dev);
 944         int regdump_len = 0;
 945
 946         regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
 947         regdump_len *= 4;
 948         regdump_len += sizeof(struct dump_header);
 949
 950         return regdump_len;
 951 }
 952
 953 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
 954 {
 955         struct bnx2x *bp = netdev_priv(dev);
 956
 957         /* Use the ethtool_dump "flag" field as the dump preset index */
 958         bp->dump_preset_idx = val->flag;
 959         return 0;
 960 }
 961
 962 static int bnx2x_get_dump_flag(struct net_device *dev,
 963                                struct ethtool_dump *dump)
 964 {
 965         struct bnx2x *bp = netdev_priv(dev);
 966
 967         /* Calculate the requested preset idx length */
 968         dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
 969         DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
 970            bp->dump_preset_idx, dump->len);
 971
 972         dump->flag = ETHTOOL_GET_DUMP_DATA;
 973         return 0;
 974 }
 975
 976 static int bnx2x_get_dump_data(struct net_device *dev,
 977                                struct ethtool_dump *dump,
 978                                void *buffer)
 979 {
 980         u32 *p = buffer;
 981         struct bnx2x *bp = netdev_priv(dev);
 982         struct dump_header dump_hdr = {0};
 983
 984         memset(p, 0, dump->len);
 985
 986         /* Disable parity attentions as long as following dump may
 987          * cause false alarms by reading never written registers. We
 988          * will re-enable parity attentions right after the dump.
 989          */
 990
 991         /* Disable parity on path 0 */
 992         bnx2x_pretend_func(bp, 0);
 993         bnx2x_disable_blocks_parity(bp);
 994
 995         /* Disable parity on path 1 */
 996         bnx2x_pretend_func(bp, 1);
 997         bnx2x_disable_blocks_parity(bp);
 998
 999         /* Return to current function */
1000         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1001
1002         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1003         dump_hdr.preset = bp->dump_preset_idx;
1004         dump_hdr.version = BNX2X_DUMP_VERSION;
1005
1006         DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1007
1008         /* dump_meta_data presents OR of CHIP and PATH. */
1009         if (CHIP_IS_E1(bp)) {
1010                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1011         } else if (CHIP_IS_E1H(bp)) {
1012                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1013         } else if (CHIP_IS_E2(bp)) {
1014                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1015                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1016         } else if (CHIP_IS_E3A0(bp)) {
1017                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1018                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1019         } else if (CHIP_IS_E3B0(bp)) {
1020                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1021                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1022         }
1023
1024         memcpy(p, &dump_hdr, sizeof(struct dump_header));
1025         p += dump_hdr.header_size + 1;
1026
1027         /* Actually read the registers */
1028         __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1029
1030         /* Re-enable parity attentions on path 0 */
1031         bnx2x_pretend_func(bp, 0);
1032         bnx2x_clear_blocks_parity(bp);
1033         bnx2x_enable_blocks_parity(bp);
1034
1035         /* Re-enable parity attentions on path 1 */
1036         bnx2x_pretend_func(bp, 1);
1037         bnx2x_clear_blocks_parity(bp);
1038         bnx2x_enable_blocks_parity(bp);
1039
1040         /* Return to current function */
1041         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1042
1043         return 0;
1044 }
1045
1046 static void bnx2x_get_drvinfo(struct net_device *dev,
1047                               struct ethtool_drvinfo *info)
1048 {
1049         struct bnx2x *bp = netdev_priv(dev);
1050
1051         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1052         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1053
1054         bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1055
1056         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1057         info->n_stats = BNX2X_NUM_STATS;
1058         info->testinfo_len = BNX2X_NUM_TESTS(bp);
1059         info->eedump_len = bp->common.flash_size;
1060         info->regdump_len = bnx2x_get_regs_len(dev);
1061 }
1062
1063 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1064 {
1065         struct bnx2x *bp = netdev_priv(dev);
1066
1067         if (bp->flags & NO_WOL_FLAG) {
1068                 wol->supported = 0;
1069                 wol->wolopts = 0;
1070         } else {
1071                 wol->supported = WAKE_MAGIC;
1072                 if (bp->wol)
1073                         wol->wolopts = WAKE_MAGIC;
1074                 else
1075                         wol->wolopts = 0;
1076         }
1077         memset(&wol->sopass, 0, sizeof(wol->sopass));
1078 }
1079
1080 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1081 {
1082         struct bnx2x *bp = netdev_priv(dev);
1083
1084         if (wol->wolopts & ~WAKE_MAGIC) {
1085                 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
1086                 return -EINVAL;
1087         }
1088
1089         if (wol->wolopts & WAKE_MAGIC) {
1090                 if (bp->flags & NO_WOL_FLAG) {
1091                         DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
1092                         return -EINVAL;
1093                 }
1094                 bp->wol = 1;
1095         } else
1096                 bp->wol = 0;
1097
1098         return 0;
1099 }
1100
1101 static u32 bnx2x_get_msglevel(struct net_device *dev)
1102 {
1103         struct bnx2x *bp = netdev_priv(dev);
1104
1105         return bp->msg_enable;
1106 }
1107
1108 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1109 {
1110         struct bnx2x *bp = netdev_priv(dev);
1111
1112         if (capable(CAP_NET_ADMIN)) {
1113                 /* dump MCP trace */
1114                 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1115                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
1116                 bp->msg_enable = level;
1117         }
1118 }
1119
1120 static int bnx2x_nway_reset(struct net_device *dev)
1121 {
1122         struct bnx2x *bp = netdev_priv(dev);
1123
1124         if (!bp->port.pmf)
1125                 return 0;
1126
1127         if (netif_running(dev)) {
1128                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1129                 bnx2x_force_link_reset(bp);
1130                 bnx2x_link_set(bp);
1131         }
1132
1133         return 0;
1134 }
1135
1136 static u32 bnx2x_get_link(struct net_device *dev)
1137 {
1138         struct bnx2x *bp = netdev_priv(dev);
1139
1140         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1141                 return 0;
1142
1143         return bp->link_vars.link_up;
1144 }
1145
1146 static int bnx2x_get_eeprom_len(struct net_device *dev)
1147 {
1148         struct bnx2x *bp = netdev_priv(dev);
1149
1150         return bp->common.flash_size;
1151 }
1152
1153 /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
1154  * we done things the other way around, if two pfs from the same port would
1155  * attempt to access nvram at the same time, we could run into a scenario such
1156  * as:
1157  * pf A takes the port lock.
1158  * pf B succeeds in taking the same lock since they are from the same port.
1159  * pf A takes the per pf misc lock. Performs eeprom access.
1160  * pf A finishes. Unlocks the per pf misc lock.
1161  * Pf B takes the lock and proceeds to perform it's own access.
1162  * pf A unlocks the per port lock, while pf B is still working (!).
1163  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1164  * acess corrupted by pf B).*
1165  */
1166 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1167 {
1168         int port = BP_PORT(bp);
1169         int count, i;
1170         u32 val;
1171
1172         /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1173         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1174
1175         /* adjust timeout for emulation/FPGA */
1176         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1177         if (CHIP_REV_IS_SLOW(bp))
1178                 count *= 100;
1179
1180         /* request access to nvram interface */
1181         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1182                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1183
1184         for (i = 0; i < count*10; i++) {
1185                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1186                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1187                         break;
1188
1189                 udelay(5);
1190         }
1191
1192         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1193                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1194                    "cannot get access to nvram interface\n");
1195                 return -EBUSY;
1196         }
1197
1198         return 0;
1199 }
1200
1201 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1202 {
1203         int port = BP_PORT(bp);
1204         int count, i;
1205         u32 val;
1206
1207         /* adjust timeout for emulation/FPGA */
1208         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1209         if (CHIP_REV_IS_SLOW(bp))
1210                 count *= 100;
1211
1212         /* relinquish nvram interface */
1213         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1214                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1215
1216         for (i = 0; i < count*10; i++) {
1217                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1218                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1219                         break;
1220
1221                 udelay(5);
1222         }
1223
1224         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1225                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1226                    "cannot free access to nvram interface\n");
1227                 return -EBUSY;
1228         }
1229
1230         /* release HW lock: protect against other PFs in PF Direct Assignment */
1231         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1232         return 0;
1233 }
1234
1235 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1236 {
1237         u32 val;
1238
1239         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1240
1241         /* enable both bits, even on read */
1242         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1243                (val | MCPR_NVM_ACCESS_ENABLE_EN |
1244                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
1245 }
1246
1247 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1248 {
1249         u32 val;
1250
1251         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1252
1253         /* disable both bits, even after read */
1254         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1255                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1256                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1257 }
1258
1259 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1260                                   u32 cmd_flags)
1261 {
1262         int count, i, rc;
1263         u32 val;
1264
1265         /* build the command word */
1266         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1267
1268         /* need to clear DONE bit separately */
1269         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1270
1271         /* address of the NVRAM to read from */
1272         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1273                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1274
1275         /* issue a read command */
1276         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1277
1278         /* adjust timeout for emulation/FPGA */
1279         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1280         if (CHIP_REV_IS_SLOW(bp))
1281                 count *= 100;
1282
1283         /* wait for completion */
1284         *ret_val = 0;
1285         rc = -EBUSY;
1286         for (i = 0; i < count; i++) {
1287                 udelay(5);
1288                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1289
1290                 if (val & MCPR_NVM_COMMAND_DONE) {
1291                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1292                         /* we read nvram data in cpu order
1293                          * but ethtool sees it as an array of bytes
1294                          * converting to big-endian will do the work
1295                          */
1296                         *ret_val = cpu_to_be32(val);
1297                         rc = 0;
1298                         break;
1299                 }
1300         }
1301         if (rc == -EBUSY)
1302                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1303                    "nvram read timeout expired\n");
1304         return rc;
1305 }
1306
1307 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1308                             int buf_size)
1309 {
1310         int rc;
1311         u32 cmd_flags;
1312         __be32 val;
1313
1314         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1315                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1316                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1317                    offset, buf_size);
1318                 return -EINVAL;
1319         }
1320
1321         if (offset + buf_size > bp->common.flash_size) {
1322                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1323                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1324                    offset, buf_size, bp->common.flash_size);
1325                 return -EINVAL;
1326         }
1327
1328         /* request access to nvram interface */
1329         rc = bnx2x_acquire_nvram_lock(bp);
1330         if (rc)
1331                 return rc;
1332
1333         /* enable access to nvram interface */
1334         bnx2x_enable_nvram_access(bp);
1335
1336         /* read the first word(s) */
1337         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1338         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1339                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1340                 memcpy(ret_buf, &val, 4);
1341
1342                 /* advance to the next dword */
1343                 offset += sizeof(u32);
1344                 ret_buf += sizeof(u32);
1345                 buf_size -= sizeof(u32);
1346                 cmd_flags = 0;
1347         }
1348
1349         if (rc == 0) {
1350                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1351                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1352                 memcpy(ret_buf, &val, 4);
1353         }
1354
1355         /* disable access to nvram interface */
1356         bnx2x_disable_nvram_access(bp);
1357         bnx2x_release_nvram_lock(bp);
1358
1359         return rc;
1360 }
1361
1362 static int bnx2x_get_eeprom(struct net_device *dev,
1363                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1364 {
1365         struct bnx2x *bp = netdev_priv(dev);
1366         int rc;
1367
1368         if (!netif_running(dev)) {
1369                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1370                    "cannot access eeprom when the interface is down\n");
1371                 return -EAGAIN;
1372         }
1373
1374         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1375            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1376            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1377            eeprom->len, eeprom->len);
1378
1379         /* parameters already validated in ethtool_get_eeprom */
1380
1381         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1382
1383         return rc;
1384 }
1385
1386 static int bnx2x_get_module_eeprom(struct net_device *dev,
1387                                    struct ethtool_eeprom *ee,
1388                                    u8 *data)
1389 {
1390         struct bnx2x *bp = netdev_priv(dev);
1391         int rc = 0, phy_idx;
1392         u8 *user_data = data;
1393         int remaining_len = ee->len, xfer_size;
1394         unsigned int page_off = ee->offset;
1395
1396         if (!netif_running(dev)) {
1397                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1398                    "cannot access eeprom when the interface is down\n");
1399                 return -EAGAIN;
1400         }
1401
1402         phy_idx = bnx2x_get_cur_phy_idx(bp);
1403         bnx2x_acquire_phy_lock(bp);
1404         while (!rc && remaining_len > 0) {
1405                 xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ?
1406                         SFP_EEPROM_PAGE_SIZE : remaining_len;
1407                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1408                                                   &bp->link_params,
1409                                                   page_off,
1410                                                   xfer_size,
1411                                                   user_data);
1412                 remaining_len -= xfer_size;
1413                 user_data += xfer_size;
1414                 page_off += xfer_size;
1415         }
1416
1417         bnx2x_release_phy_lock(bp);
1418         return rc;
1419 }
1420
1421 static int bnx2x_get_module_info(struct net_device *dev,
1422                                  struct ethtool_modinfo *modinfo)
1423 {
1424         struct bnx2x *bp = netdev_priv(dev);
1425         int phy_idx;
1426         if (!netif_running(dev)) {
1427                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1428                    "cannot access eeprom when the interface is down\n");
1429                 return -EAGAIN;
1430         }
1431
1432         phy_idx = bnx2x_get_cur_phy_idx(bp);
1433         switch (bp->link_params.phy[phy_idx].media_type) {
1434         case ETH_PHY_SFPP_10G_FIBER:
1435         case ETH_PHY_SFP_1G_FIBER:
1436         case ETH_PHY_DA_TWINAX:
1437                 modinfo->type = ETH_MODULE_SFF_8079;
1438                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1439                 return 0;
1440         default:
1441                 return -EOPNOTSUPP;
1442         }
1443 }
1444
1445 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1446                                    u32 cmd_flags)
1447 {
1448         int count, i, rc;
1449
1450         /* build the command word */
1451         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1452
1453         /* need to clear DONE bit separately */
1454         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1455
1456         /* write the data */
1457         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1458
1459         /* address of the NVRAM to write to */
1460         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1461                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1462
1463         /* issue the write command */
1464         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1465
1466         /* adjust timeout for emulation/FPGA */
1467         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1468         if (CHIP_REV_IS_SLOW(bp))
1469                 count *= 100;
1470
1471         /* wait for completion */
1472         rc = -EBUSY;
1473         for (i = 0; i < count; i++) {
1474                 udelay(5);
1475                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1476                 if (val & MCPR_NVM_COMMAND_DONE) {
1477                         rc = 0;
1478                         break;
1479                 }
1480         }
1481
1482         if (rc == -EBUSY)
1483                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1484                    "nvram write timeout expired\n");
1485         return rc;
1486 }
1487
1488 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1489
1490 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1491                               int buf_size)
1492 {
1493         int rc;
1494         u32 cmd_flags;
1495         u32 align_offset;
1496         __be32 val;
1497
1498         if (offset + buf_size > bp->common.flash_size) {
1499                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1500                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1501                    offset, buf_size, bp->common.flash_size);
1502                 return -EINVAL;
1503         }
1504
1505         /* request access to nvram interface */
1506         rc = bnx2x_acquire_nvram_lock(bp);
1507         if (rc)
1508                 return rc;
1509
1510         /* enable access to nvram interface */
1511         bnx2x_enable_nvram_access(bp);
1512
1513         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1514         align_offset = (offset & ~0x03);
1515         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1516
1517         if (rc == 0) {
1518                 val &= ~(0xff << BYTE_OFFSET(offset));
1519                 val |= (*data_buf << BYTE_OFFSET(offset));
1520
1521                 /* nvram data is returned as an array of bytes
1522                  * convert it back to cpu order
1523                  */
1524                 val = be32_to_cpu(val);
1525
1526                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1527                                              cmd_flags);
1528         }
1529
1530         /* disable access to nvram interface */
1531         bnx2x_disable_nvram_access(bp);
1532         bnx2x_release_nvram_lock(bp);
1533
1534         return rc;
1535 }
1536
1537 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1538                              int buf_size)
1539 {
1540         int rc;
1541         u32 cmd_flags;
1542         u32 val;
1543         u32 written_so_far;
1544
1545         if (buf_size == 1)      /* ethtool */
1546                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1547
1548         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1549                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1550                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1551                    offset, buf_size);
1552                 return -EINVAL;
1553         }
1554
1555         if (offset + buf_size > bp->common.flash_size) {
1556                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1557                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1558                    offset, buf_size, bp->common.flash_size);
1559                 return -EINVAL;
1560         }
1561
1562         /* request access to nvram interface */
1563         rc = bnx2x_acquire_nvram_lock(bp);
1564         if (rc)
1565                 return rc;
1566
1567         /* enable access to nvram interface */
1568         bnx2x_enable_nvram_access(bp);
1569
1570         written_so_far = 0;
1571         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1572         while ((written_so_far < buf_size) && (rc == 0)) {
1573                 if (written_so_far == (buf_size - sizeof(u32)))
1574                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1575                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1576                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1577                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1578                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1579
1580                 memcpy(&val, data_buf, 4);
1581
1582                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1583
1584                 /* advance to the next dword */
1585                 offset += sizeof(u32);
1586                 data_buf += sizeof(u32);
1587                 written_so_far += sizeof(u32);
1588                 cmd_flags = 0;
1589         }
1590
1591         /* disable access to nvram interface */
1592         bnx2x_disable_nvram_access(bp);
1593         bnx2x_release_nvram_lock(bp);
1594
1595         return rc;
1596 }
1597
1598 static int bnx2x_set_eeprom(struct net_device *dev,
1599                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1600 {
1601         struct bnx2x *bp = netdev_priv(dev);
1602         int port = BP_PORT(bp);
1603         int rc = 0;
1604         u32 ext_phy_config;
1605         if (!netif_running(dev)) {
1606                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1607                    "cannot access eeprom when the interface is down\n");
1608                 return -EAGAIN;
1609         }
1610
1611         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1612            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1613            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1614            eeprom->len, eeprom->len);
1615
1616         /* parameters already validated in ethtool_set_eeprom */
1617
1618         /* PHY eeprom can be accessed only by the PMF */
1619         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1620             !bp->port.pmf) {
1621                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1622                    "wrong magic or interface is not pmf\n");
1623                 return -EINVAL;
1624         }
1625
1626         ext_phy_config =
1627                 SHMEM_RD(bp,
1628                          dev_info.port_hw_config[port].external_phy_config);
1629
1630         if (eeprom->magic == 0x50485950) {
1631                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1632                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1633
1634                 bnx2x_acquire_phy_lock(bp);
1635                 rc |= bnx2x_link_reset(&bp->link_params,
1636                                        &bp->link_vars, 0);
1637                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1638                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1639                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1640                                        MISC_REGISTERS_GPIO_HIGH, port);
1641                 bnx2x_release_phy_lock(bp);
1642                 bnx2x_link_report(bp);
1643
1644         } else if (eeprom->magic == 0x50485952) {
1645                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1646                 if (bp->state == BNX2X_STATE_OPEN) {
1647                         bnx2x_acquire_phy_lock(bp);
1648                         rc |= bnx2x_link_reset(&bp->link_params,
1649                                                &bp->link_vars, 1);
1650
1651                         rc |= bnx2x_phy_init(&bp->link_params,
1652                                              &bp->link_vars);
1653                         bnx2x_release_phy_lock(bp);
1654                         bnx2x_calc_fc_adv(bp);
1655                 }
1656         } else if (eeprom->magic == 0x53985943) {
1657                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1658                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1659                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1660
1661                         /* DSP Remove Download Mode */
1662                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1663                                        MISC_REGISTERS_GPIO_LOW, port);
1664
1665                         bnx2x_acquire_phy_lock(bp);
1666
1667                         bnx2x_sfx7101_sp_sw_reset(bp,
1668                                                 &bp->link_params.phy[EXT_PHY1]);
1669
1670                         /* wait 0.5 sec to allow it to run */
1671                         msleep(500);
1672                         bnx2x_ext_phy_hw_reset(bp, port);
1673                         msleep(500);
1674                         bnx2x_release_phy_lock(bp);
1675                 }
1676         } else
1677                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1678
1679         return rc;
1680 }
1681
1682 static int bnx2x_get_coalesce(struct net_device *dev,
1683                               struct ethtool_coalesce *coal)
1684 {
1685         struct bnx2x *bp = netdev_priv(dev);
1686
1687         memset(coal, 0, sizeof(struct ethtool_coalesce));
1688
1689         coal->rx_coalesce_usecs = bp->rx_ticks;
1690         coal->tx_coalesce_usecs = bp->tx_ticks;
1691
1692         return 0;
1693 }
1694
1695 static int bnx2x_set_coalesce(struct net_device *dev,
1696                               struct ethtool_coalesce *coal)
1697 {
1698         struct bnx2x *bp = netdev_priv(dev);
1699
1700         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1701         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1702                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1703
1704         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1705         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1706                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1707
1708         if (netif_running(dev))
1709                 bnx2x_update_coalesce(bp);
1710
1711         return 0;
1712 }
1713
1714 static void bnx2x_get_ringparam(struct net_device *dev,
1715                                 struct ethtool_ringparam *ering)
1716 {
1717         struct bnx2x *bp = netdev_priv(dev);
1718
1719         ering->rx_max_pending = MAX_RX_AVAIL;
1720
1721         if (bp->rx_ring_size)
1722                 ering->rx_pending = bp->rx_ring_size;
1723         else
1724                 ering->rx_pending = MAX_RX_AVAIL;
1725
1726         ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1727         ering->tx_pending = bp->tx_ring_size;
1728 }
1729
1730 static int bnx2x_set_ringparam(struct net_device *dev,
1731                                struct ethtool_ringparam *ering)
1732 {
1733         struct bnx2x *bp = netdev_priv(dev);
1734
1735         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1736                 DP(BNX2X_MSG_ETHTOOL,
1737                    "Handling parity error recovery. Try again later\n");
1738                 return -EAGAIN;
1739         }
1740
1741         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1742             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1743                                                     MIN_RX_SIZE_TPA)) ||
1744             (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
1745             (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1746                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1747                 return -EINVAL;
1748         }
1749
1750         bp->rx_ring_size = ering->rx_pending;
1751         bp->tx_ring_size = ering->tx_pending;
1752
1753         return bnx2x_reload_if_running(dev);
1754 }
1755
1756 static void bnx2x_get_pauseparam(struct net_device *dev,
1757                                  struct ethtool_pauseparam *epause)
1758 {
1759         struct bnx2x *bp = netdev_priv(dev);
1760         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1761         int cfg_reg;
1762
1763         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1764                            BNX2X_FLOW_CTRL_AUTO);
1765
1766         if (!epause->autoneg)
1767                 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1768         else
1769                 cfg_reg = bp->link_params.req_fc_auto_adv;
1770
1771         epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1772                             BNX2X_FLOW_CTRL_RX);
1773         epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1774                             BNX2X_FLOW_CTRL_TX);
1775
1776         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1777            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1778            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1779 }
1780
1781 static int bnx2x_set_pauseparam(struct net_device *dev,
1782                                 struct ethtool_pauseparam *epause)
1783 {
1784         struct bnx2x *bp = netdev_priv(dev);
1785         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1786         if (IS_MF(bp))
1787                 return 0;
1788
1789         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1790            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1791            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1792
1793         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1794
1795         if (epause->rx_pause)
1796                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1797
1798         if (epause->tx_pause)
1799                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1800
1801         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1802                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1803
1804         if (epause->autoneg) {
1805                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1806                         DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1807                         return -EINVAL;
1808                 }
1809
1810                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1811                         bp->link_params.req_flow_ctrl[cfg_idx] =
1812                                 BNX2X_FLOW_CTRL_AUTO;
1813                 }
1814                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE;
1815                 if (epause->rx_pause)
1816                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1817
1818                 if (epause->tx_pause)
1819                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1820         }
1821
1822         DP(BNX2X_MSG_ETHTOOL,
1823            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1824
1825         if (netif_running(dev)) {
1826                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1827                 bnx2x_link_set(bp);
1828         }
1829
1830         return 0;
1831 }
1832
1833 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1834         "register_test (offline)    ",
1835         "memory_test (offline)      ",
1836         "int_loopback_test (offline)",
1837         "ext_loopback_test (offline)",
1838         "nvram_test (online)        ",
1839         "interrupt_test (online)    ",
1840         "link_test (online)         "
1841 };
1842
1843 static u32 bnx2x_eee_to_adv(u32 eee_adv)
1844 {
1845         u32 modes = 0;
1846
1847         if (eee_adv & SHMEM_EEE_100M_ADV)
1848                 modes |= ADVERTISED_100baseT_Full;
1849         if (eee_adv & SHMEM_EEE_1G_ADV)
1850                 modes |= ADVERTISED_1000baseT_Full;
1851         if (eee_adv & SHMEM_EEE_10G_ADV)
1852                 modes |= ADVERTISED_10000baseT_Full;
1853
1854         return modes;
1855 }
1856
1857 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1858 {
1859         u32 eee_adv = 0;
1860         if (modes & ADVERTISED_100baseT_Full)
1861                 eee_adv |= SHMEM_EEE_100M_ADV;
1862         if (modes & ADVERTISED_1000baseT_Full)
1863                 eee_adv |= SHMEM_EEE_1G_ADV;
1864         if (modes & ADVERTISED_10000baseT_Full)
1865                 eee_adv |= SHMEM_EEE_10G_ADV;
1866
1867         return eee_adv << shift;
1868 }
1869
1870 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1871 {
1872         struct bnx2x *bp = netdev_priv(dev);
1873         u32 eee_cfg;
1874
1875         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1876                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1877                 return -EOPNOTSUPP;
1878         }
1879
1880         eee_cfg = bp->link_vars.eee_status;
1881
1882         edata->supported =
1883                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1884                                  SHMEM_EEE_SUPPORTED_SHIFT);
1885
1886         edata->advertised =
1887                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1888                                  SHMEM_EEE_ADV_STATUS_SHIFT);
1889         edata->lp_advertised =
1890                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1891                                  SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1892
1893         /* SHMEM value is in 16u units --> Convert to 1u units. */
1894         edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1895
1896         edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
1897         edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
1898         edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1899
1900         return 0;
1901 }
1902
1903 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1904 {
1905         struct bnx2x *bp = netdev_priv(dev);
1906         u32 eee_cfg;
1907         u32 advertised;
1908
1909         if (IS_MF(bp))
1910                 return 0;
1911
1912         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1913                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1914                 return -EOPNOTSUPP;
1915         }
1916
1917         eee_cfg = bp->link_vars.eee_status;
1918
1919         if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1920                 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1921                 return -EOPNOTSUPP;
1922         }
1923
1924         advertised = bnx2x_adv_to_eee(edata->advertised,
1925                                       SHMEM_EEE_ADV_STATUS_SHIFT);
1926         if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1927                 DP(BNX2X_MSG_ETHTOOL,
1928                    "Direct manipulation of EEE advertisement is not supported\n");
1929                 return -EINVAL;
1930         }
1931
1932         if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1933                 DP(BNX2X_MSG_ETHTOOL,
1934                    "Maximal Tx Lpi timer supported is %x(u)\n",
1935                    EEE_MODE_TIMER_MASK);
1936                 return -EINVAL;
1937         }
1938         if (edata->tx_lpi_enabled &&
1939             (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1940                 DP(BNX2X_MSG_ETHTOOL,
1941                    "Minimal Tx Lpi timer supported is %d(u)\n",
1942                    EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1943                 return -EINVAL;
1944         }
1945
1946         /* All is well; Apply changes*/
1947         if (edata->eee_enabled)
1948                 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1949         else
1950                 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1951
1952         if (edata->tx_lpi_enabled)
1953                 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1954         else
1955                 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1956
1957         bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1958         bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1959                                     EEE_MODE_TIMER_MASK) |
1960                                     EEE_MODE_OVERRIDE_NVRAM |
1961                                     EEE_MODE_OUTPUT_TIME;
1962
1963         /* Restart link to propogate changes */
1964         if (netif_running(dev)) {
1965                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1966                 bnx2x_force_link_reset(bp);
1967                 bnx2x_link_set(bp);
1968         }
1969
1970         return 0;
1971 }
1972
1973
1974 enum {
1975         BNX2X_CHIP_E1_OFST = 0,
1976         BNX2X_CHIP_E1H_OFST,
1977         BNX2X_CHIP_E2_OFST,
1978         BNX2X_CHIP_E3_OFST,
1979         BNX2X_CHIP_E3B0_OFST,
1980         BNX2X_CHIP_MAX_OFST
1981 };
1982
1983 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
1984 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
1985 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
1986 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
1987 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
1988
1989 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1990 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1991
1992 static int bnx2x_test_registers(struct bnx2x *bp)
1993 {
1994         int idx, i, rc = -ENODEV;
1995         u32 wr_val = 0, hw;
1996         int port = BP_PORT(bp);
1997         static const struct {
1998                 u32 hw;
1999                 u32 offset0;
2000                 u32 offset1;
2001                 u32 mask;
2002         } reg_tbl[] = {
2003 /* 0 */         { BNX2X_CHIP_MASK_ALL,
2004                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2005                 { BNX2X_CHIP_MASK_ALL,
2006                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
2007                 { BNX2X_CHIP_MASK_E1X,
2008                         HC_REG_AGG_INT_0,               4, 0x000003ff },
2009                 { BNX2X_CHIP_MASK_ALL,
2010                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
2011                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2012                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
2013                 { BNX2X_CHIP_MASK_E3B0,
2014                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
2015                 { BNX2X_CHIP_MASK_ALL,
2016                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
2017                 { BNX2X_CHIP_MASK_ALL,
2018                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
2019                 { BNX2X_CHIP_MASK_ALL,
2020                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2021                 { BNX2X_CHIP_MASK_ALL,
2022                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
2023 /* 10 */        { BNX2X_CHIP_MASK_ALL,
2024                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2025                 { BNX2X_CHIP_MASK_ALL,
2026                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
2027                 { BNX2X_CHIP_MASK_ALL,
2028                         QM_REG_CONNNUM_0,               4, 0x000fffff },
2029                 { BNX2X_CHIP_MASK_ALL,
2030                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
2031                 { BNX2X_CHIP_MASK_ALL,
2032                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
2033                 { BNX2X_CHIP_MASK_ALL,
2034                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
2035                 { BNX2X_CHIP_MASK_ALL,
2036                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2037                 { BNX2X_CHIP_MASK_ALL,
2038                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
2039                 { BNX2X_CHIP_MASK_ALL,
2040                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
2041                 { BNX2X_CHIP_MASK_ALL,
2042                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
2043 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2044                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
2045                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2046                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
2047                 { BNX2X_CHIP_MASK_ALL,
2048                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
2049                 { BNX2X_CHIP_MASK_ALL,
2050                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
2051                 { BNX2X_CHIP_MASK_ALL,
2052                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
2053                 { BNX2X_CHIP_MASK_ALL,
2054                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
2055                 { BNX2X_CHIP_MASK_ALL,
2056                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
2057                 { BNX2X_CHIP_MASK_ALL,
2058                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
2059                 { BNX2X_CHIP_MASK_ALL,
2060                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
2061                 { BNX2X_CHIP_MASK_ALL,
2062                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
2063 /* 30 */        { BNX2X_CHIP_MASK_ALL,
2064                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
2065                 { BNX2X_CHIP_MASK_ALL,
2066                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
2067                 { BNX2X_CHIP_MASK_ALL,
2068                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2069                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2070                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
2071                 { BNX2X_CHIP_MASK_ALL,
2072                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2073                 { BNX2X_CHIP_MASK_ALL,
2074                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2075                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2076                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2077                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2078                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
2079
2080                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2081         };
2082
2083         if (!netif_running(bp->dev)) {
2084                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2085                    "cannot access eeprom when the interface is down\n");
2086                 return rc;
2087         }
2088
2089         if (CHIP_IS_E1(bp))
2090                 hw = BNX2X_CHIP_MASK_E1;
2091         else if (CHIP_IS_E1H(bp))
2092                 hw = BNX2X_CHIP_MASK_E1H;
2093         else if (CHIP_IS_E2(bp))
2094                 hw = BNX2X_CHIP_MASK_E2;
2095         else if (CHIP_IS_E3B0(bp))
2096                 hw = BNX2X_CHIP_MASK_E3B0;
2097         else /* e3 A0 */
2098                 hw = BNX2X_CHIP_MASK_E3;
2099
2100         /* Repeat the test twice:
2101          * First by writing 0x00000000, second by writing 0xffffffff
2102          */
2103         for (idx = 0; idx < 2; idx++) {
2104
2105                 switch (idx) {
2106                 case 0:
2107                         wr_val = 0;
2108                         break;
2109                 case 1:
2110                         wr_val = 0xffffffff;
2111                         break;
2112                 }
2113
2114                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2115                         u32 offset, mask, save_val, val;
2116                         if (!(hw & reg_tbl[i].hw))
2117                                 continue;
2118
2119                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2120                         mask = reg_tbl[i].mask;
2121
2122                         save_val = REG_RD(bp, offset);
2123
2124                         REG_WR(bp, offset, wr_val & mask);
2125
2126                         val = REG_RD(bp, offset);
2127
2128                         /* Restore the original register's value */
2129                         REG_WR(bp, offset, save_val);
2130
2131                         /* verify value is as expected */
2132                         if ((val & mask) != (wr_val & mask)) {
2133                                 DP(BNX2X_MSG_ETHTOOL,
2134                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2135                                    offset, val, wr_val, mask);
2136                                 goto test_reg_exit;
2137                         }
2138                 }
2139         }
2140
2141         rc = 0;
2142
2143 test_reg_exit:
2144         return rc;
2145 }
2146
2147 static int bnx2x_test_memory(struct bnx2x *bp)
2148 {
2149         int i, j, rc = -ENODEV;
2150         u32 val, index;
2151         static const struct {
2152                 u32 offset;
2153                 int size;
2154         } mem_tbl[] = {
2155                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2156                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2157                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2158                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2159                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2160                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2161                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2162
2163                 { 0xffffffff, 0 }
2164         };
2165
2166         static const struct {
2167                 char *name;
2168                 u32 offset;
2169                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2170         } prty_tbl[] = {
2171                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2172                         {0x3ffc0, 0,   0, 0} },
2173                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2174                         {0x2,     0x2, 0, 0} },
2175                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2176                         {0,       0,   0, 0} },
2177                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2178                         {0x3ffc0, 0,   0, 0} },
2179                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2180                         {0x3ffc0, 0,   0, 0} },
2181                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2182                         {0x3ffc1, 0,   0, 0} },
2183
2184                 { NULL, 0xffffffff, {0, 0, 0, 0} }
2185         };
2186
2187         if (!netif_running(bp->dev)) {
2188                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2189                    "cannot access eeprom when the interface is down\n");
2190                 return rc;
2191         }
2192
2193         if (CHIP_IS_E1(bp))
2194                 index = BNX2X_CHIP_E1_OFST;
2195         else if (CHIP_IS_E1H(bp))
2196                 index = BNX2X_CHIP_E1H_OFST;
2197         else if (CHIP_IS_E2(bp))
2198                 index = BNX2X_CHIP_E2_OFST;
2199         else /* e3 */
2200                 index = BNX2X_CHIP_E3_OFST;
2201
2202         /* pre-Check the parity status */
2203         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2204                 val = REG_RD(bp, prty_tbl[i].offset);
2205                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2206                         DP(BNX2X_MSG_ETHTOOL,
2207                            "%s is 0x%x\n", prty_tbl[i].name, val);
2208                         goto test_mem_exit;
2209                 }
2210         }
2211
2212         /* Go through all the memories */
2213         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2214                 for (j = 0; j < mem_tbl[i].size; j++)
2215                         REG_RD(bp, mem_tbl[i].offset + j*4);
2216
2217         /* Check the parity status */
2218         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2219                 val = REG_RD(bp, prty_tbl[i].offset);
2220                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2221                         DP(BNX2X_MSG_ETHTOOL,
2222                            "%s is 0x%x\n", prty_tbl[i].name, val);
2223                         goto test_mem_exit;
2224                 }
2225         }
2226
2227         rc = 0;
2228
2229 test_mem_exit:
2230         return rc;
2231 }
2232
2233 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2234 {
2235         int cnt = 1400;
2236
2237         if (link_up) {
2238                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2239                         msleep(20);
2240
2241                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2242                         DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2243
2244                 cnt = 1400;
2245                 while (!bp->link_vars.link_up && cnt--)
2246                         msleep(20);
2247
2248                 if (cnt <= 0 && !bp->link_vars.link_up)
2249                         DP(BNX2X_MSG_ETHTOOL,
2250                            "Timeout waiting for link init\n");
2251         }
2252 }
2253
2254 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2255 {
2256         unsigned int pkt_size, num_pkts, i;
2257         struct sk_buff *skb;
2258         unsigned char *packet;
2259         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2260         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2261         struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2262         u16 tx_start_idx, tx_idx;
2263         u16 rx_start_idx, rx_idx;
2264         u16 pkt_prod, bd_prod;
2265         struct sw_tx_bd *tx_buf;
2266         struct eth_tx_start_bd *tx_start_bd;
2267         dma_addr_t mapping;
2268         union eth_rx_cqe *cqe;
2269         u8 cqe_fp_flags, cqe_fp_type;
2270         struct sw_rx_bd *rx_buf;
2271         u16 len;
2272         int rc = -ENODEV;
2273         u8 *data;
2274         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2275                                                        txdata->txq_index);
2276
2277         /* check the loopback mode */
2278         switch (loopback_mode) {
2279         case BNX2X_PHY_LOOPBACK:
2280                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2281                         DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2282                         return -EINVAL;
2283                 }
2284                 break;
2285         case BNX2X_MAC_LOOPBACK:
2286                 if (CHIP_IS_E3(bp)) {
2287                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2288                         if (bp->port.supported[cfg_idx] &
2289                             (SUPPORTED_10000baseT_Full |
2290                              SUPPORTED_20000baseMLD2_Full |
2291                              SUPPORTED_20000baseKR2_Full))
2292                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2293                         else
2294                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2295                 } else
2296                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
2297
2298                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2299                 break;
2300         case BNX2X_EXT_LOOPBACK:
2301                 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2302                         DP(BNX2X_MSG_ETHTOOL,
2303                            "Can't configure external loopback\n");
2304                         return -EINVAL;
2305                 }
2306                 break;
2307         default:
2308                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2309                 return -EINVAL;
2310         }
2311
2312         /* prepare the loopback packet */
2313         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2314                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2315         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2316         if (!skb) {
2317                 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2318                 rc = -ENOMEM;
2319                 goto test_loopback_exit;
2320         }
2321         packet = skb_put(skb, pkt_size);
2322         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2323         memset(packet + ETH_ALEN, 0, ETH_ALEN);
2324         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2325         for (i = ETH_HLEN; i < pkt_size; i++)
2326                 packet[i] = (unsigned char) (i & 0xff);
2327         mapping = dma_map_single(&bp->pdev->dev, skb->data,
2328                                  skb_headlen(skb), DMA_TO_DEVICE);
2329         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2330                 rc = -ENOMEM;
2331                 dev_kfree_skb(skb);
2332                 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2333                 goto test_loopback_exit;
2334         }
2335
2336         /* send the loopback packet */
2337         num_pkts = 0;
2338         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2339         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2340
2341         netdev_tx_sent_queue(txq, skb->len);
2342
2343         pkt_prod = txdata->tx_pkt_prod++;
2344         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2345         tx_buf->first_bd = txdata->tx_bd_prod;
2346         tx_buf->skb = skb;
2347         tx_buf->flags = 0;
2348
2349         bd_prod = TX_BD(txdata->tx_bd_prod);
2350         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2351         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2352         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2353         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2354         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2355         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2356         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2357         SET_FLAG(tx_start_bd->general_data,
2358                  ETH_TX_START_BD_HDR_NBDS,
2359                  1);
2360         SET_FLAG(tx_start_bd->general_data,
2361                  ETH_TX_START_BD_PARSE_NBDS,
2362                  0);
2363
2364         /* turn on parsing and get a BD */
2365         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2366
2367         if (CHIP_IS_E1x(bp)) {
2368                 u16 global_data = 0;
2369                 struct eth_tx_parse_bd_e1x  *pbd_e1x =
2370                         &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2371                 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2372                 SET_FLAG(global_data,
2373                          ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2374                 pbd_e1x->global_data = cpu_to_le16(global_data);
2375         } else {
2376                 u32 parsing_data = 0;
2377                 struct eth_tx_parse_bd_e2  *pbd_e2 =
2378                         &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2379                 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2380                 SET_FLAG(parsing_data,
2381                          ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2382                 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2383         }
2384         wmb();
2385
2386         txdata->tx_db.data.prod += 2;
2387         barrier();
2388         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2389
2390         mmiowb();
2391         barrier();
2392
2393         num_pkts++;
2394         txdata->tx_bd_prod += 2; /* start + pbd */
2395
2396         udelay(100);
2397
2398         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2399         if (tx_idx != tx_start_idx + num_pkts)
2400                 goto test_loopback_exit;
2401
2402         /* Unlike HC IGU won't generate an interrupt for status block
2403          * updates that have been performed while interrupts were
2404          * disabled.
2405          */
2406         if (bp->common.int_block == INT_BLOCK_IGU) {
2407                 /* Disable local BHes to prevent a dead-lock situation between
2408                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
2409                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
2410                  */
2411                 local_bh_disable();
2412                 bnx2x_tx_int(bp, txdata);
2413                 local_bh_enable();
2414         }
2415
2416         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2417         if (rx_idx != rx_start_idx + num_pkts)
2418                 goto test_loopback_exit;
2419
2420         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2421         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2422         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2423         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2424                 goto test_loopback_rx_exit;
2425
2426         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2427         if (len != pkt_size)
2428                 goto test_loopback_rx_exit;
2429
2430         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2431         dma_sync_single_for_cpu(&bp->pdev->dev,
2432                                    dma_unmap_addr(rx_buf, mapping),
2433                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2434         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2435         for (i = ETH_HLEN; i < pkt_size; i++)
2436                 if (*(data + i) != (unsigned char) (i & 0xff))
2437                         goto test_loopback_rx_exit;
2438
2439         rc = 0;
2440
2441 test_loopback_rx_exit:
2442
2443         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2444         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2445         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2446         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2447
2448         /* Update producers */
2449         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2450                              fp_rx->rx_sge_prod);
2451
2452 test_loopback_exit:
2453         bp->link_params.loopback_mode = LOOPBACK_NONE;
2454
2455         return rc;
2456 }
2457
2458 static int bnx2x_test_loopback(struct bnx2x *bp)
2459 {
2460         int rc = 0, res;
2461
2462         if (BP_NOMCP(bp))
2463                 return rc;
2464
2465         if (!netif_running(bp->dev))
2466                 return BNX2X_LOOPBACK_FAILED;
2467
2468         bnx2x_netif_stop(bp, 1);
2469         bnx2x_acquire_phy_lock(bp);
2470
2471         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2472         if (res) {
2473                 DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2474                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2475         }
2476
2477         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2478         if (res) {
2479                 DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2480                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2481         }
2482
2483         bnx2x_release_phy_lock(bp);
2484         bnx2x_netif_start(bp);
2485
2486         return rc;
2487 }
2488
2489 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2490 {
2491         int rc;
2492         u8 is_serdes =
2493                 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2494
2495         if (BP_NOMCP(bp))
2496                 return -ENODEV;
2497
2498         if (!netif_running(bp->dev))
2499                 return BNX2X_EXT_LOOPBACK_FAILED;
2500
2501         bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2502         rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2503         if (rc) {
2504                 DP(BNX2X_MSG_ETHTOOL,
2505                    "Can't perform self-test, nic_load (for external lb) failed\n");
2506                 return -ENODEV;
2507         }
2508         bnx2x_wait_for_link(bp, 1, is_serdes);
2509
2510         bnx2x_netif_stop(bp, 1);
2511
2512         rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2513         if (rc)
2514                 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2515
2516         bnx2x_netif_start(bp);
2517
2518         return rc;
2519 }
2520
2521 #define CRC32_RESIDUAL                  0xdebb20e3
2522
2523 static int bnx2x_test_nvram(struct bnx2x *bp)
2524 {
2525         static const struct {
2526                 int offset;
2527                 int size;
2528         } nvram_tbl[] = {
2529                 {     0,  0x14 }, /* bootstrap */
2530                 {  0x14,  0xec }, /* dir */
2531                 { 0x100, 0x350 }, /* manuf_info */
2532                 { 0x450,  0xf0 }, /* feature_info */
2533                 { 0x640,  0x64 }, /* upgrade_key_info */
2534                 { 0x708,  0x70 }, /* manuf_key_info */
2535                 {     0,     0 }
2536         };
2537         __be32 *buf;
2538         u8 *data;
2539         int i, rc;
2540         u32 magic, crc;
2541
2542         if (BP_NOMCP(bp))
2543                 return 0;
2544
2545         buf = kmalloc(0x350, GFP_KERNEL);
2546         if (!buf) {
2547                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2548                 rc = -ENOMEM;
2549                 goto test_nvram_exit;
2550         }
2551         data = (u8 *)buf;
2552
2553         rc = bnx2x_nvram_read(bp, 0, data, 4);
2554         if (rc) {
2555                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2556                    "magic value read (rc %d)\n", rc);
2557                 goto test_nvram_exit;
2558         }
2559
2560         magic = be32_to_cpu(buf[0]);
2561         if (magic != 0x669955aa) {
2562                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2563                    "wrong magic value (0x%08x)\n", magic);
2564                 rc = -ENODEV;
2565                 goto test_nvram_exit;
2566         }
2567
2568         for (i = 0; nvram_tbl[i].size; i++) {
2569
2570                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2571                                       nvram_tbl[i].size);
2572                 if (rc) {
2573                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2574                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2575                         goto test_nvram_exit;
2576                 }
2577
2578                 crc = ether_crc_le(nvram_tbl[i].size, data);
2579                 if (crc != CRC32_RESIDUAL) {
2580                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2581                            "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
2582                         rc = -ENODEV;
2583                         goto test_nvram_exit;
2584                 }
2585         }
2586
2587 test_nvram_exit:
2588         kfree(buf);
2589         return rc;
2590 }
2591
2592 /* Send an EMPTY ramrod on the first queue */
2593 static int bnx2x_test_intr(struct bnx2x *bp)
2594 {
2595         struct bnx2x_queue_state_params params = {NULL};
2596
2597         if (!netif_running(bp->dev)) {
2598                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2599                    "cannot access eeprom when the interface is down\n");
2600                 return -ENODEV;
2601         }
2602
2603         params.q_obj = &bp->sp_objs->q_obj;
2604         params.cmd = BNX2X_Q_CMD_EMPTY;
2605
2606         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2607
2608         return bnx2x_queue_state_change(bp, &params);
2609 }
2610
2611 static void bnx2x_self_test(struct net_device *dev,
2612                             struct ethtool_test *etest, u64 *buf)
2613 {
2614         struct bnx2x *bp = netdev_priv(dev);
2615         u8 is_serdes, link_up;
2616         int rc, cnt = 0;
2617
2618         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2619                 netdev_err(bp->dev,
2620                            "Handling parity error recovery. Try again later\n");
2621                 etest->flags |= ETH_TEST_FL_FAILED;
2622                 return;
2623         }
2624         DP(BNX2X_MSG_ETHTOOL,
2625            "Self-test command parameters: offline = %d, external_lb = %d\n",
2626            (etest->flags & ETH_TEST_FL_OFFLINE),
2627            (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2628
2629         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2630
2631         if (!netif_running(dev)) {
2632                 DP(BNX2X_MSG_ETHTOOL,
2633                    "Can't perform self-test when interface is down\n");
2634                 return;
2635         }
2636
2637         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2638         link_up = bp->link_vars.link_up;
2639         /* offline tests are not supported in MF mode */
2640         if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2641                 int port = BP_PORT(bp);
2642                 u32 val;
2643
2644                 /* save current value of input enable for TX port IF */
2645                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2646                 /* disable input for TX port IF */
2647                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2648
2649                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2650                 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2651                 if (rc) {
2652                         etest->flags |= ETH_TEST_FL_FAILED;
2653                         DP(BNX2X_MSG_ETHTOOL,
2654                            "Can't perform self-test, nic_load (for offline) failed\n");
2655                         return;
2656                 }
2657
2658                 /* wait until link state is restored */
2659                 bnx2x_wait_for_link(bp, 1, is_serdes);
2660
2661                 if (bnx2x_test_registers(bp) != 0) {
2662                         buf[0] = 1;
2663                         etest->flags |= ETH_TEST_FL_FAILED;
2664                 }
2665                 if (bnx2x_test_memory(bp) != 0) {
2666                         buf[1] = 1;
2667                         etest->flags |= ETH_TEST_FL_FAILED;
2668                 }
2669
2670                 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
2671                 if (buf[2] != 0)
2672                         etest->flags |= ETH_TEST_FL_FAILED;
2673
2674                 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2675                         buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2676                         if (buf[3] != 0)
2677                                 etest->flags |= ETH_TEST_FL_FAILED;
2678                         etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2679                 }
2680
2681                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2682
2683                 /* restore input for TX port IF */
2684                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2685                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2686                 if (rc) {
2687                         etest->flags |= ETH_TEST_FL_FAILED;
2688                         DP(BNX2X_MSG_ETHTOOL,
2689                            "Can't perform self-test, nic_load (for online) failed\n");
2690                         return;
2691                 }
2692                 /* wait until link state is restored */
2693                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2694         }
2695         if (bnx2x_test_nvram(bp) != 0) {
2696                 if (!IS_MF(bp))
2697                         buf[4] = 1;
2698                 else
2699                         buf[0] = 1;
2700                 etest->flags |= ETH_TEST_FL_FAILED;
2701         }
2702         if (bnx2x_test_intr(bp) != 0) {
2703                 if (!IS_MF(bp))
2704                         buf[5] = 1;
2705                 else
2706                         buf[1] = 1;
2707                 etest->flags |= ETH_TEST_FL_FAILED;
2708         }
2709
2710         if (link_up) {
2711                 cnt = 100;
2712                 while (bnx2x_link_test(bp, is_serdes) && --cnt)
2713                         msleep(20);
2714         }
2715
2716         if (!cnt) {
2717                 if (!IS_MF(bp))
2718                         buf[6] = 1;
2719                 else
2720                         buf[2] = 1;
2721                 etest->flags |= ETH_TEST_FL_FAILED;
2722         }
2723 }
2724
2725 #define IS_PORT_STAT(i) \
2726         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2727 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2728 #define IS_MF_MODE_STAT(bp) \
2729                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2730
2731 /* ethtool statistics are displayed for all regular ethernet queues and the
2732  * fcoe L2 queue if not disabled
2733  */
2734 static int bnx2x_num_stat_queues(struct bnx2x *bp)
2735 {
2736         return BNX2X_NUM_ETH_QUEUES(bp);
2737 }
2738
2739 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2740 {
2741         struct bnx2x *bp = netdev_priv(dev);
2742         int i, num_stats;
2743
2744         switch (stringset) {
2745         case ETH_SS_STATS:
2746                 if (is_multi(bp)) {
2747                         num_stats = bnx2x_num_stat_queues(bp) *
2748                                                 BNX2X_NUM_Q_STATS;
2749                 } else
2750                         num_stats = 0;
2751                 if (IS_MF_MODE_STAT(bp)) {
2752                         for (i = 0; i < BNX2X_NUM_STATS; i++)
2753                                 if (IS_FUNC_STAT(i))
2754                                         num_stats++;
2755                 } else
2756                         num_stats += BNX2X_NUM_STATS;
2757
2758                 return num_stats;
2759
2760         case ETH_SS_TEST:
2761                 return BNX2X_NUM_TESTS(bp);
2762
2763         default:
2764                 return -EINVAL;
2765         }
2766 }
2767
2768 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2769 {
2770         struct bnx2x *bp = netdev_priv(dev);
2771         int i, j, k, start;
2772         char queue_name[MAX_QUEUE_NAME_LEN+1];
2773
2774         switch (stringset) {
2775         case ETH_SS_STATS:
2776                 k = 0;
2777                 if (is_multi(bp)) {
2778                         for_each_eth_queue(bp, i) {
2779                                 memset(queue_name, 0, sizeof(queue_name));
2780                                 sprintf(queue_name, "%d", i);
2781                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2782                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2783                                                 ETH_GSTRING_LEN,
2784                                                 bnx2x_q_stats_arr[j].string,
2785                                                 queue_name);
2786                                 k += BNX2X_NUM_Q_STATS;
2787                         }
2788                 }
2789
2790
2791                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2792                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2793                                 continue;
2794                         strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2795                                    bnx2x_stats_arr[i].string);
2796                         j++;
2797                 }
2798
2799                 break;
2800
2801         case ETH_SS_TEST:
2802                 /* First 4 tests cannot be done in MF mode */
2803                 if (!IS_MF(bp))
2804                         start = 0;
2805                 else
2806                         start = 4;
2807                 memcpy(buf, bnx2x_tests_str_arr + start,
2808                        ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
2809         }
2810 }
2811
2812 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2813                                     struct ethtool_stats *stats, u64 *buf)
2814 {
2815         struct bnx2x *bp = netdev_priv(dev);
2816         u32 *hw_stats, *offset;
2817         int i, j, k = 0;
2818
2819         if (is_multi(bp)) {
2820                 for_each_eth_queue(bp, i) {
2821                         hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
2822                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2823                                 if (bnx2x_q_stats_arr[j].size == 0) {
2824                                         /* skip this counter */
2825                                         buf[k + j] = 0;
2826                                         continue;
2827                                 }
2828                                 offset = (hw_stats +
2829                                           bnx2x_q_stats_arr[j].offset);
2830                                 if (bnx2x_q_stats_arr[j].size == 4) {
2831                                         /* 4-byte counter */
2832                                         buf[k + j] = (u64) *offset;
2833                                         continue;
2834                                 }
2835                                 /* 8-byte counter */
2836                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2837                         }
2838                         k += BNX2X_NUM_Q_STATS;
2839                 }
2840         }
2841
2842         hw_stats = (u32 *)&bp->eth_stats;
2843         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2844                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2845                         continue;
2846                 if (bnx2x_stats_arr[i].size == 0) {
2847                         /* skip this counter */
2848                         buf[k + j] = 0;
2849                         j++;
2850                         continue;
2851                 }
2852                 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2853                 if (bnx2x_stats_arr[i].size == 4) {
2854                         /* 4-byte counter */
2855                         buf[k + j] = (u64) *offset;
2856                         j++;
2857                         continue;
2858                 }
2859                 /* 8-byte counter */
2860                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2861                 j++;
2862         }
2863 }
2864
2865 static int bnx2x_set_phys_id(struct net_device *dev,
2866                              enum ethtool_phys_id_state state)
2867 {
2868         struct bnx2x *bp = netdev_priv(dev);
2869
2870         if (!netif_running(dev)) {
2871                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2872                    "cannot access eeprom when the interface is down\n");
2873                 return -EAGAIN;
2874         }
2875
2876         if (!bp->port.pmf) {
2877                 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
2878                 return -EOPNOTSUPP;
2879         }
2880
2881         switch (state) {
2882         case ETHTOOL_ID_ACTIVE:
2883                 return 1;       /* cycle on/off once per second */
2884
2885         case ETHTOOL_ID_ON:
2886                 bnx2x_acquire_phy_lock(bp);
2887                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2888                               LED_MODE_ON, SPEED_1000);
2889                 bnx2x_release_phy_lock(bp);
2890                 break;
2891
2892         case ETHTOOL_ID_OFF:
2893                 bnx2x_acquire_phy_lock(bp);
2894                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2895                               LED_MODE_FRONT_PANEL_OFF, 0);
2896                 bnx2x_release_phy_lock(bp);
2897                 break;
2898
2899         case ETHTOOL_ID_INACTIVE:
2900                 bnx2x_acquire_phy_lock(bp);
2901                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2902                               LED_MODE_OPER,
2903                               bp->link_vars.line_speed);
2904                 bnx2x_release_phy_lock(bp);
2905         }
2906
2907         return 0;
2908 }
2909
2910 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2911 {
2912
2913         switch (info->flow_type) {
2914         case TCP_V4_FLOW:
2915         case TCP_V6_FLOW:
2916                 info->data = RXH_IP_SRC | RXH_IP_DST |
2917                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2918                 break;
2919         case UDP_V4_FLOW:
2920                 if (bp->rss_conf_obj.udp_rss_v4)
2921                         info->data = RXH_IP_SRC | RXH_IP_DST |
2922                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
2923                 else
2924                         info->data = RXH_IP_SRC | RXH_IP_DST;
2925                 break;
2926         case UDP_V6_FLOW:
2927                 if (bp->rss_conf_obj.udp_rss_v6)
2928                         info->data = RXH_IP_SRC | RXH_IP_DST |
2929                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
2930                 else
2931                         info->data = RXH_IP_SRC | RXH_IP_DST;
2932                 break;
2933         case IPV4_FLOW:
2934         case IPV6_FLOW:
2935                 info->data = RXH_IP_SRC | RXH_IP_DST;
2936                 break;
2937         default:
2938                 info->data = 0;
2939                 break;
2940         }
2941
2942         return 0;
2943 }
2944
2945 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2946                            u32 *rules __always_unused)
2947 {
2948         struct bnx2x *bp = netdev_priv(dev);
2949
2950         switch (info->cmd) {
2951         case ETHTOOL_GRXRINGS:
2952                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2953                 return 0;
2954         case ETHTOOL_GRXFH:
2955                 return bnx2x_get_rss_flags(bp, info);
2956         default:
2957                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2958                 return -EOPNOTSUPP;
2959         }
2960 }
2961
2962 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2963 {
2964         int udp_rss_requested;
2965
2966         DP(BNX2X_MSG_ETHTOOL,
2967            "Set rss flags command parameters: flow type = %d, data = %llu\n",
2968            info->flow_type, info->data);
2969
2970         switch (info->flow_type) {
2971         case TCP_V4_FLOW:
2972         case TCP_V6_FLOW:
2973                 /* For TCP only 4-tupple hash is supported */
2974                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
2975                                   RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2976                         DP(BNX2X_MSG_ETHTOOL,
2977                            "Command parameters not supported\n");
2978                         return -EINVAL;
2979                 } else {
2980                         return 0;
2981                 }
2982
2983         case UDP_V4_FLOW:
2984         case UDP_V6_FLOW:
2985                 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
2986                 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2987                                  RXH_L4_B_0_1 | RXH_L4_B_2_3))
2988                         udp_rss_requested = 1;
2989                 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
2990                         udp_rss_requested = 0;
2991                 else
2992                         return -EINVAL;
2993                 if ((info->flow_type == UDP_V4_FLOW) &&
2994                     (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
2995                         bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
2996                         DP(BNX2X_MSG_ETHTOOL,
2997                            "rss re-configured, UDP 4-tupple %s\n",
2998                            udp_rss_requested ? "enabled" : "disabled");
2999                         return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
3000                 } else if ((info->flow_type == UDP_V6_FLOW) &&
3001                            (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3002                         bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3003                         DP(BNX2X_MSG_ETHTOOL,
3004                            "rss re-configured, UDP 4-tupple %s\n",
3005                            udp_rss_requested ? "enabled" : "disabled");
3006                         return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
3007                 } else {
3008                         return 0;
3009                 }
3010         case IPV4_FLOW:
3011         case IPV6_FLOW:
3012                 /* For IP only 2-tupple hash is supported */
3013                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3014                         DP(BNX2X_MSG_ETHTOOL,
3015                            "Command parameters not supported\n");
3016                         return -EINVAL;
3017                 } else {
3018                         return 0;
3019                 }
3020         case SCTP_V4_FLOW:
3021         case AH_ESP_V4_FLOW:
3022         case AH_V4_FLOW:
3023         case ESP_V4_FLOW:
3024         case SCTP_V6_FLOW:
3025         case AH_ESP_V6_FLOW:
3026         case AH_V6_FLOW:
3027         case ESP_V6_FLOW:
3028         case IP_USER_FLOW:
3029         case ETHER_FLOW:
3030                 /* RSS is not supported for these protocols */
3031                 if (info->data) {
3032                         DP(BNX2X_MSG_ETHTOOL,
3033                            "Command parameters not supported\n");
3034                         return -EINVAL;
3035                 } else {
3036                         return 0;
3037                 }
3038         default:
3039                 return -EINVAL;
3040         }
3041 }
3042
3043 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3044 {
3045         struct bnx2x *bp = netdev_priv(dev);
3046
3047         switch (info->cmd) {
3048         case ETHTOOL_SRXFH:
3049                 return bnx2x_set_rss_flags(bp, info);
3050         default:
3051                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3052                 return -EOPNOTSUPP;
3053         }
3054 }
3055
3056 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3057 {
3058         return T_ETH_INDIRECTION_TABLE_SIZE;
3059 }
3060
3061 static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
3062 {
3063         struct bnx2x *bp = netdev_priv(dev);
3064         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3065         size_t i;
3066
3067         /* Get the current configuration of the RSS indirection table */
3068         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3069
3070         /*
3071          * We can't use a memcpy() as an internal storage of an
3072          * indirection table is a u8 array while indir->ring_index
3073          * points to an array of u32.
3074          *
3075          * Indirection table contains the FW Client IDs, so we need to
3076          * align the returned table to the Client ID of the leading RSS
3077          * queue.
3078          */
3079         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3080                 indir[i] = ind_table[i] - bp->fp->cl_id;
3081
3082         return 0;
3083 }
3084
3085 static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
3086 {
3087         struct bnx2x *bp = netdev_priv(dev);
3088         size_t i;
3089
3090         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3091                 /*
3092                  * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
3093                  * as an internal storage of an indirection table is a u8 array
3094                  * while indir->ring_index points to an array of u32.
3095                  *
3096                  * Indirection table contains the FW Client IDs, so we need to
3097                  * align the received table to the Client ID of the leading RSS
3098                  * queue
3099                  */
3100                 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3101         }
3102
3103         return bnx2x_config_rss_eth(bp, false);
3104 }
3105
3106 /**
3107  * bnx2x_get_channels - gets the number of RSS queues.
3108  *
3109  * @dev:                net device
3110  * @channels:           returns the number of max / current queues
3111  */
3112 static void bnx2x_get_channels(struct net_device *dev,
3113                                struct ethtool_channels *channels)
3114 {
3115         struct bnx2x *bp = netdev_priv(dev);
3116
3117         channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3118         channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3119 }
3120
3121 /**
3122  * bnx2x_change_num_queues - change the number of RSS queues.
3123  *
3124  * @bp:                 bnx2x private structure
3125  *
3126  * Re-configure interrupt mode to get the new number of MSI-X
3127  * vectors and re-add NAPI objects.
3128  */
3129 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3130 {
3131         bnx2x_disable_msi(bp);
3132         bp->num_ethernet_queues = num_rss;
3133         bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3134         BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3135         bnx2x_set_int_mode(bp);
3136 }
3137
3138 /**
3139  * bnx2x_set_channels - sets the number of RSS queues.
3140  *
3141  * @dev:                net device
3142  * @channels:           includes the number of queues requested
3143  */
3144 static int bnx2x_set_channels(struct net_device *dev,
3145                               struct ethtool_channels *channels)
3146 {
3147         struct bnx2x *bp = netdev_priv(dev);
3148
3149
3150         DP(BNX2X_MSG_ETHTOOL,
3151            "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3152            channels->rx_count, channels->tx_count, channels->other_count,
3153            channels->combined_count);
3154
3155         /* We don't support separate rx / tx channels.
3156          * We don't allow setting 'other' channels.
3157          */
3158         if (channels->rx_count || channels->tx_count || channels->other_count
3159             || (channels->combined_count == 0) ||
3160             (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3161                 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3162                 return -EINVAL;
3163         }
3164
3165         /* Check if there was a change in the active parameters */
3166         if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3167                 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3168                 return 0;
3169         }
3170
3171         /* Set the requested number of queues in bp context.
3172          * Note that the actual number of queues created during load may be
3173          * less than requested if memory is low.
3174          */
3175         if (unlikely(!netif_running(dev))) {
3176                 bnx2x_change_num_queues(bp, channels->combined_count);
3177                 return 0;
3178         }
3179         bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3180         bnx2x_change_num_queues(bp, channels->combined_count);
3181         return bnx2x_nic_load(bp, LOAD_NORMAL);
3182 }
3183
3184 static const struct ethtool_ops bnx2x_ethtool_ops = {
3185         .get_settings           = bnx2x_get_settings,
3186         .set_settings           = bnx2x_set_settings,
3187         .get_drvinfo            = bnx2x_get_drvinfo,
3188         .get_regs_len           = bnx2x_get_regs_len,
3189         .get_regs               = bnx2x_get_regs,
3190         .get_dump_flag          = bnx2x_get_dump_flag,
3191         .get_dump_data          = bnx2x_get_dump_data,
3192         .set_dump               = bnx2x_set_dump,
3193         .get_wol                = bnx2x_get_wol,
3194         .set_wol                = bnx2x_set_wol,
3195         .get_msglevel           = bnx2x_get_msglevel,
3196         .set_msglevel           = bnx2x_set_msglevel,
3197         .nway_reset             = bnx2x_nway_reset,
3198         .get_link               = bnx2x_get_link,
3199         .get_eeprom_len         = bnx2x_get_eeprom_len,
3200         .get_eeprom             = bnx2x_get_eeprom,
3201         .set_eeprom             = bnx2x_set_eeprom,
3202         .get_coalesce           = bnx2x_get_coalesce,
3203         .set_coalesce           = bnx2x_set_coalesce,
3204         .get_ringparam          = bnx2x_get_ringparam,
3205         .set_ringparam          = bnx2x_set_ringparam,
3206         .get_pauseparam         = bnx2x_get_pauseparam,
3207         .set_pauseparam         = bnx2x_set_pauseparam,
3208         .self_test              = bnx2x_self_test,
3209         .get_sset_count         = bnx2x_get_sset_count,
3210         .get_strings            = bnx2x_get_strings,
3211         .set_phys_id            = bnx2x_set_phys_id,
3212         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3213         .get_rxnfc              = bnx2x_get_rxnfc,
3214         .set_rxnfc              = bnx2x_set_rxnfc,
3215         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3216         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
3217         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
3218         .get_channels           = bnx2x_get_channels,
3219         .set_channels           = bnx2x_set_channels,
3220         .get_module_info        = bnx2x_get_module_info,
3221         .get_module_eeprom      = bnx2x_get_module_eeprom,
3222         .get_eee                = bnx2x_get_eee,
3223         .set_eee                = bnx2x_set_eee,
3224         .get_ts_info            = ethtool_op_get_ts_info,
3225 };
3226
3227 void bnx2x_set_ethtool_ops(struct net_device *netdev)
3228 {
3229         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
3230 }