drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2012 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/ethtool.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/types.h>
  23 #include <linux/sched.h>
  24 #include <linux/crc32.h>
  25 #include "bnx2x.h"
  26 #include "bnx2x_cmn.h"
  27 #include "bnx2x_dump.h"
  28 #include "bnx2x_init.h"
  29
  30 /* Note: in the format strings below %s is replaced by the queue-name which is
  31  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  32  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  33  */
  34 #define MAX_QUEUE_NAME_LEN      4
  35 static const struct {
  36         long offset;
  37         int size;
  38         char string[ETH_GSTRING_LEN];
  39 } bnx2x_q_stats_arr[] = {
  40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  41         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  42                                                 8, "[%s]: rx_ucast_packets" },
  43         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  44                                                 8, "[%s]: rx_mcast_packets" },
  45         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  46                                                 8, "[%s]: rx_bcast_packets" },
  47         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  48         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  49                                          4, "[%s]: rx_phy_ip_err_discards"},
  50         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  51                                          4, "[%s]: rx_skb_alloc_discard" },
  52         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  53
  54         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  56                                                 8, "[%s]: tx_ucast_packets" },
  57         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  58                                                 8, "[%s]: tx_mcast_packets" },
  59         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  60                                                 8, "[%s]: tx_bcast_packets" },
  61         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  62                                                 8, "[%s]: tpa_aggregations" },
  63         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  64                                         8, "[%s]: tpa_aggregated_frames"},
  65         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
  66 };
  67
  68 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  69
  70 static const struct {
  71         long offset;
  72         int size;
  73         u32 flags;
  74 #define STATS_FLAGS_PORT                1
  75 #define STATS_FLAGS_FUNC                2
  76 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  77         char string[ETH_GSTRING_LEN];
  78 } bnx2x_stats_arr[] = {
  79 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  80                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  81         { STATS_OFFSET32(error_bytes_received_hi),
  82                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  83         { STATS_OFFSET32(total_unicast_packets_received_hi),
  84                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  85         { STATS_OFFSET32(total_multicast_packets_received_hi),
  86                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  87         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  88                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  89         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  90                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  91         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  92                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  93         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  94                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  95         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  96                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  97 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
  98                                 8, STATS_FLAGS_PORT, "rx_fragments" },
  99         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 100                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 101         { STATS_OFFSET32(no_buff_discard_hi),
 102                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 103         { STATS_OFFSET32(mac_filter_discard),
 104                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 105         { STATS_OFFSET32(mf_tag_discard),
 106                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 107         { STATS_OFFSET32(pfc_frames_received_hi),
 108                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
 109         { STATS_OFFSET32(pfc_frames_sent_hi),
 110                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
 111         { STATS_OFFSET32(brb_drop_hi),
 112                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 113         { STATS_OFFSET32(brb_truncate_hi),
 114                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 115         { STATS_OFFSET32(pause_frames_received_hi),
 116                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 117         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 118                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 119         { STATS_OFFSET32(nig_timer_max),
 120                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 121 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 122                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 123         { STATS_OFFSET32(rx_skb_alloc_failed),
 124                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 125         { STATS_OFFSET32(hw_csum_err),
 126                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 127
 128         { STATS_OFFSET32(total_bytes_transmitted_hi),
 129                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 130         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 131                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 132         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 133                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 134         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 135                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 136         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 137                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 138         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 139                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 140         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 141                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 142 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 143                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 144         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 145                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 146         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 147                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 148         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 149                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 150         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 151                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 152         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 153                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 154         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 155                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 156         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 157                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 158         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 159                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 160         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 161                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 162 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 163                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 164         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 165                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 166         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 167                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 168         { STATS_OFFSET32(pause_frames_sent_hi),
 169                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 170         { STATS_OFFSET32(total_tpa_aggregations_hi),
 171                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 172         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 173                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 174         { STATS_OFFSET32(total_tpa_bytes_hi),
 175                         8, STATS_FLAGS_FUNC, "tpa_bytes"},
 176         { STATS_OFFSET32(recoverable_error),
 177                         4, STATS_FLAGS_FUNC, "recoverable_errors" },
 178         { STATS_OFFSET32(unrecoverable_error),
 179                         4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
 180         { STATS_OFFSET32(eee_tx_lpi),
 181                         4, STATS_FLAGS_PORT, "Tx LPI entry count"}
 182 };
 183
 184 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 185 static int bnx2x_get_port_type(struct bnx2x *bp)
 186 {
 187         int port_type;
 188         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 189         switch (bp->link_params.phy[phy_idx].media_type) {
 190         case ETH_PHY_SFP_FIBER:
 191         case ETH_PHY_XFP_FIBER:
 192         case ETH_PHY_KR:
 193         case ETH_PHY_CX4:
 194                 port_type = PORT_FIBRE;
 195                 break;
 196         case ETH_PHY_DA_TWINAX:
 197                 port_type = PORT_DA;
 198                 break;
 199         case ETH_PHY_BASE_T:
 200                 port_type = PORT_TP;
 201                 break;
 202         case ETH_PHY_NOT_PRESENT:
 203                 port_type = PORT_NONE;
 204                 break;
 205         case ETH_PHY_UNSPECIFIED:
 206         default:
 207                 port_type = PORT_OTHER;
 208                 break;
 209         }
 210         return port_type;
 211 }
 212
 213 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 214 {
 215         struct bnx2x *bp = netdev_priv(dev);
 216         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 217
 218         /* Dual Media boards present all available port types */
 219         cmd->supported = bp->port.supported[cfg_idx] |
 220                 (bp->port.supported[cfg_idx ^ 1] &
 221                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 222         cmd->advertising = bp->port.advertising[cfg_idx];
 223
 224         if ((bp->state == BNX2X_STATE_OPEN) && (bp->link_vars.link_up)) {
 225                 if (!(bp->flags & MF_FUNC_DIS)) {
 226                         ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 227                         cmd->duplex = bp->link_vars.duplex;
 228                 } else {
 229                         ethtool_cmd_speed_set(
 230                                 cmd, bp->link_params.req_line_speed[cfg_idx]);
 231                         cmd->duplex = bp->link_params.req_duplex[cfg_idx];
 232                 }
 233
 234                 if (IS_MF(bp) && !BP_NOMCP(bp))
 235                         ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 236         } else {
 237                 cmd->duplex = DUPLEX_UNKNOWN;
 238                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 239         }
 240
 241         cmd->port = bnx2x_get_port_type(bp);
 242
 243         cmd->phy_address = bp->mdio.prtad;
 244         cmd->transceiver = XCVR_INTERNAL;
 245
 246         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 247                 cmd->autoneg = AUTONEG_ENABLE;
 248         else
 249                 cmd->autoneg = AUTONEG_DISABLE;
 250
 251         /* Publish LP advertised speeds and FC */
 252         if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
 253                 u32 status = bp->link_vars.link_status;
 254
 255                 cmd->lp_advertising |= ADVERTISED_Autoneg;
 256                 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
 257                         cmd->lp_advertising |= ADVERTISED_Pause;
 258                 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 259                         cmd->lp_advertising |= ADVERTISED_Asym_Pause;
 260
 261                 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
 262                         cmd->lp_advertising |= ADVERTISED_10baseT_Half;
 263                 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
 264                         cmd->lp_advertising |= ADVERTISED_10baseT_Full;
 265                 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
 266                         cmd->lp_advertising |= ADVERTISED_100baseT_Half;
 267                 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
 268                         cmd->lp_advertising |= ADVERTISED_100baseT_Full;
 269                 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
 270                         cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
 271                 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
 272                         cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
 273                 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
 274                         cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
 275                 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
 276                         cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
 277         }
 278
 279         cmd->maxtxpkt = 0;
 280         cmd->maxrxpkt = 0;
 281
 282         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 283            "  supported 0x%x  advertising 0x%x  speed %u\n"
 284            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 285            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 286            cmd->cmd, cmd->supported, cmd->advertising,
 287            ethtool_cmd_speed(cmd),
 288            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 289            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 290
 291         return 0;
 292 }
 293
 294 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 295 {
 296         struct bnx2x *bp = netdev_priv(dev);
 297         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 298         u32 speed;
 299
 300         if (IS_MF_SD(bp))
 301                 return 0;
 302
 303         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 304            "  supported 0x%x  advertising 0x%x  speed %u\n"
 305            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 306            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 307            cmd->cmd, cmd->supported, cmd->advertising,
 308            ethtool_cmd_speed(cmd),
 309            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 310            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 311
 312         speed = ethtool_cmd_speed(cmd);
 313
 314         /* If recieved a request for an unknown duplex, assume full*/
 315         if (cmd->duplex == DUPLEX_UNKNOWN)
 316                 cmd->duplex = DUPLEX_FULL;
 317
 318         if (IS_MF_SI(bp)) {
 319                 u32 part;
 320                 u32 line_speed = bp->link_vars.line_speed;
 321
 322                 /* use 10G if no link detected */
 323                 if (!line_speed)
 324                         line_speed = 10000;
 325
 326                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 327                         DP(BNX2X_MSG_ETHTOOL,
 328                            "To set speed BC %X or higher is required, please upgrade BC\n",
 329                            REQ_BC_VER_4_SET_MF_BW);
 330                         return -EINVAL;
 331                 }
 332
 333                 part = (speed * 100) / line_speed;
 334
 335                 if (line_speed < speed || !part) {
 336                         DP(BNX2X_MSG_ETHTOOL,
 337                            "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
 338                         return -EINVAL;
 339                 }
 340
 341                 if (bp->state != BNX2X_STATE_OPEN)
 342                         /* store value for following "load" */
 343                         bp->pending_max = part;
 344                 else
 345                         bnx2x_update_max_mf_config(bp, part);
 346
 347                 return 0;
 348         }
 349
 350         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 351         old_multi_phy_config = bp->link_params.multi_phy_config;
 352         switch (cmd->port) {
 353         case PORT_TP:
 354                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 355                         break; /* no port change */
 356
 357                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 358                       bp->port.supported[1] & SUPPORTED_TP)) {
 359                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 360                         return -EINVAL;
 361                 }
 362                 bp->link_params.multi_phy_config &=
 363                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 364                 if (bp->link_params.multi_phy_config &
 365                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 366                         bp->link_params.multi_phy_config |=
 367                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 368                 else
 369                         bp->link_params.multi_phy_config |=
 370                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 371                 break;
 372         case PORT_FIBRE:
 373         case PORT_DA:
 374                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 375                         break; /* no port change */
 376
 377                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 378                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 379                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 380                         return -EINVAL;
 381                 }
 382                 bp->link_params.multi_phy_config &=
 383                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 384                 if (bp->link_params.multi_phy_config &
 385                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 386                         bp->link_params.multi_phy_config |=
 387                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 388                 else
 389                         bp->link_params.multi_phy_config |=
 390                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 391                 break;
 392         default:
 393                 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 394                 return -EINVAL;
 395         }
 396         /* Save new config in case command complete successully */
 397         new_multi_phy_config = bp->link_params.multi_phy_config;
 398         /* Get the new cfg_idx */
 399         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 400         /* Restore old config in case command failed */
 401         bp->link_params.multi_phy_config = old_multi_phy_config;
 402         DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 403
 404         if (cmd->autoneg == AUTONEG_ENABLE) {
 405                 u32 an_supported_speed = bp->port.supported[cfg_idx];
 406                 if (bp->link_params.phy[EXT_PHY1].type ==
 407                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 408                         an_supported_speed |= (SUPPORTED_100baseT_Half |
 409                                                SUPPORTED_100baseT_Full);
 410                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 411                         DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
 412                         return -EINVAL;
 413                 }
 414
 415                 /* advertise the requested speed and duplex if supported */
 416                 if (cmd->advertising & ~an_supported_speed) {
 417                         DP(BNX2X_MSG_ETHTOOL,
 418                            "Advertisement parameters are not supported\n");
 419                         return -EINVAL;
 420                 }
 421
 422                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 423                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 424                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 425                                          cmd->advertising);
 426                 if (cmd->advertising) {
 427
 428                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 429                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 430                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 431                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 432                         }
 433                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 434                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 435                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 436
 437                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 438                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 439                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 440
 441                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 442                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 443                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 444                         }
 445                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 446                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 447                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 448                         }
 449                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 450                                                 ADVERTISED_1000baseKX_Full))
 451                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 452                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 453
 454                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 455                                                 ADVERTISED_10000baseKX4_Full |
 456                                                 ADVERTISED_10000baseKR_Full))
 457                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 458                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 459                 }
 460         } else { /* forced speed */
 461                 /* advertise the requested speed and duplex if supported */
 462                 switch (speed) {
 463                 case SPEED_10:
 464                         if (cmd->duplex == DUPLEX_FULL) {
 465                                 if (!(bp->port.supported[cfg_idx] &
 466                                       SUPPORTED_10baseT_Full)) {
 467                                         DP(BNX2X_MSG_ETHTOOL,
 468                                            "10M full not supported\n");
 469                                         return -EINVAL;
 470                                 }
 471
 472                                 advertising = (ADVERTISED_10baseT_Full |
 473                                                ADVERTISED_TP);
 474                         } else {
 475                                 if (!(bp->port.supported[cfg_idx] &
 476                                       SUPPORTED_10baseT_Half)) {
 477                                         DP(BNX2X_MSG_ETHTOOL,
 478                                            "10M half not supported\n");
 479                                         return -EINVAL;
 480                                 }
 481
 482                                 advertising = (ADVERTISED_10baseT_Half |
 483                                                ADVERTISED_TP);
 484                         }
 485                         break;
 486
 487                 case SPEED_100:
 488                         if (cmd->duplex == DUPLEX_FULL) {
 489                                 if (!(bp->port.supported[cfg_idx] &
 490                                                 SUPPORTED_100baseT_Full)) {
 491                                         DP(BNX2X_MSG_ETHTOOL,
 492                                            "100M full not supported\n");
 493                                         return -EINVAL;
 494                                 }
 495
 496                                 advertising = (ADVERTISED_100baseT_Full |
 497                                                ADVERTISED_TP);
 498                         } else {
 499                                 if (!(bp->port.supported[cfg_idx] &
 500                                                 SUPPORTED_100baseT_Half)) {
 501                                         DP(BNX2X_MSG_ETHTOOL,
 502                                            "100M half not supported\n");
 503                                         return -EINVAL;
 504                                 }
 505
 506                                 advertising = (ADVERTISED_100baseT_Half |
 507                                                ADVERTISED_TP);
 508                         }
 509                         break;
 510
 511                 case SPEED_1000:
 512                         if (cmd->duplex != DUPLEX_FULL) {
 513                                 DP(BNX2X_MSG_ETHTOOL,
 514                                    "1G half not supported\n");
 515                                 return -EINVAL;
 516                         }
 517
 518                         if (!(bp->port.supported[cfg_idx] &
 519                               SUPPORTED_1000baseT_Full)) {
 520                                 DP(BNX2X_MSG_ETHTOOL,
 521                                    "1G full not supported\n");
 522                                 return -EINVAL;
 523                         }
 524
 525                         advertising = (ADVERTISED_1000baseT_Full |
 526                                        ADVERTISED_TP);
 527                         break;
 528
 529                 case SPEED_2500:
 530                         if (cmd->duplex != DUPLEX_FULL) {
 531                                 DP(BNX2X_MSG_ETHTOOL,
 532                                    "2.5G half not supported\n");
 533                                 return -EINVAL;
 534                         }
 535
 536                         if (!(bp->port.supported[cfg_idx]
 537                               & SUPPORTED_2500baseX_Full)) {
 538                                 DP(BNX2X_MSG_ETHTOOL,
 539                                    "2.5G full not supported\n");
 540                                 return -EINVAL;
 541                         }
 542
 543                         advertising = (ADVERTISED_2500baseX_Full |
 544                                        ADVERTISED_TP);
 545                         break;
 546
 547                 case SPEED_10000:
 548                         if (cmd->duplex != DUPLEX_FULL) {
 549                                 DP(BNX2X_MSG_ETHTOOL,
 550                                    "10G half not supported\n");
 551                                 return -EINVAL;
 552                         }
 553
 554                         if (!(bp->port.supported[cfg_idx]
 555                               & SUPPORTED_10000baseT_Full)) {
 556                                 DP(BNX2X_MSG_ETHTOOL,
 557                                    "10G full not supported\n");
 558                                 return -EINVAL;
 559                         }
 560
 561                         advertising = (ADVERTISED_10000baseT_Full |
 562                                        ADVERTISED_FIBRE);
 563                         break;
 564
 565                 default:
 566                         DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
 567                         return -EINVAL;
 568                 }
 569
 570                 bp->link_params.req_line_speed[cfg_idx] = speed;
 571                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 572                 bp->port.advertising[cfg_idx] = advertising;
 573         }
 574
 575         DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
 576            "  req_duplex %d  advertising 0x%x\n",
 577            bp->link_params.req_line_speed[cfg_idx],
 578            bp->link_params.req_duplex[cfg_idx],
 579            bp->port.advertising[cfg_idx]);
 580
 581         /* Set new config */
 582         bp->link_params.multi_phy_config = new_multi_phy_config;
 583         if (netif_running(dev)) {
 584                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 585                 bnx2x_link_set(bp);
 586         }
 587
 588         return 0;
 589 }
 590
 591 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
 592 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
 593 #define IS_E2_ONLINE(info)      (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
 594 #define IS_E3_ONLINE(info)      (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
 595 #define IS_E3B0_ONLINE(info)    (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
 596
 597 static bool bnx2x_is_reg_online(struct bnx2x *bp,
 598                                 const struct reg_addr *reg_info)
 599 {
 600         if (CHIP_IS_E1(bp))
 601                 return IS_E1_ONLINE(reg_info->info);
 602         else if (CHIP_IS_E1H(bp))
 603                 return IS_E1H_ONLINE(reg_info->info);
 604         else if (CHIP_IS_E2(bp))
 605                 return IS_E2_ONLINE(reg_info->info);
 606         else if (CHIP_IS_E3A0(bp))
 607                 return IS_E3_ONLINE(reg_info->info);
 608         else if (CHIP_IS_E3B0(bp))
 609                 return IS_E3B0_ONLINE(reg_info->info);
 610         else
 611                 return false;
 612 }
 613
 614 /******* Paged registers info selectors ********/
 615 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 616 {
 617         if (CHIP_IS_E2(bp))
 618                 return page_vals_e2;
 619         else if (CHIP_IS_E3(bp))
 620                 return page_vals_e3;
 621         else
 622                 return NULL;
 623 }
 624
 625 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 626 {
 627         if (CHIP_IS_E2(bp))
 628                 return PAGE_MODE_VALUES_E2;
 629         else if (CHIP_IS_E3(bp))
 630                 return PAGE_MODE_VALUES_E3;
 631         else
 632                 return 0;
 633 }
 634
 635 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 636 {
 637         if (CHIP_IS_E2(bp))
 638                 return page_write_regs_e2;
 639         else if (CHIP_IS_E3(bp))
 640                 return page_write_regs_e3;
 641         else
 642                 return NULL;
 643 }
 644
 645 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 646 {
 647         if (CHIP_IS_E2(bp))
 648                 return PAGE_WRITE_REGS_E2;
 649         else if (CHIP_IS_E3(bp))
 650                 return PAGE_WRITE_REGS_E3;
 651         else
 652                 return 0;
 653 }
 654
 655 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 656 {
 657         if (CHIP_IS_E2(bp))
 658                 return page_read_regs_e2;
 659         else if (CHIP_IS_E3(bp))
 660                 return page_read_regs_e3;
 661         else
 662                 return NULL;
 663 }
 664
 665 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 666 {
 667         if (CHIP_IS_E2(bp))
 668                 return PAGE_READ_REGS_E2;
 669         else if (CHIP_IS_E3(bp))
 670                 return PAGE_READ_REGS_E3;
 671         else
 672                 return 0;
 673 }
 674
 675 static int __bnx2x_get_regs_len(struct bnx2x *bp)
 676 {
 677         int num_pages = __bnx2x_get_page_reg_num(bp);
 678         int page_write_num = __bnx2x_get_page_write_num(bp);
 679         const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
 680         int page_read_num = __bnx2x_get_page_read_num(bp);
 681         int regdump_len = 0;
 682         int i, j, k;
 683
 684         for (i = 0; i < REGS_COUNT; i++)
 685                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 686                         regdump_len += reg_addrs[i].size;
 687
 688         for (i = 0; i < num_pages; i++)
 689                 for (j = 0; j < page_write_num; j++)
 690                         for (k = 0; k < page_read_num; k++)
 691                                 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
 692                                         regdump_len += page_read_addr[k].size;
 693
 694         return regdump_len;
 695 }
 696
 697 static int bnx2x_get_regs_len(struct net_device *dev)
 698 {
 699         struct bnx2x *bp = netdev_priv(dev);
 700         int regdump_len = 0;
 701
 702         regdump_len = __bnx2x_get_regs_len(bp);
 703         regdump_len *= 4;
 704         regdump_len += sizeof(struct dump_hdr);
 705
 706         return regdump_len;
 707 }
 708
 709 /**
 710  * bnx2x_read_pages_regs - read "paged" registers
 711  *
 712  * @bp          device handle
 713  * @p           output buffer
 714  *
 715  * Reads "paged" memories: memories that may only be read by first writing to a
 716  * specific address ("write address") and then reading from a specific address
 717  * ("read address"). There may be more than one write address per "page" and
 718  * more than one read address per write address.
 719  */
 720 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
 721 {
 722         u32 i, j, k, n;
 723         /* addresses of the paged registers */
 724         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 725         /* number of paged registers */
 726         int num_pages = __bnx2x_get_page_reg_num(bp);
 727         /* write addresses */
 728         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 729         /* number of write addresses */
 730         int write_num = __bnx2x_get_page_write_num(bp);
 731         /* read addresses info */
 732         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 733         /* number of read addresses */
 734         int read_num = __bnx2x_get_page_read_num(bp);
 735
 736         for (i = 0; i < num_pages; i++) {
 737                 for (j = 0; j < write_num; j++) {
 738                         REG_WR(bp, write_addr[j], page_addr[i]);
 739                         for (k = 0; k < read_num; k++)
 740                                 if (bnx2x_is_reg_online(bp, &read_addr[k]))
 741                                         for (n = 0; n <
 742                                               read_addr[k].size; n++)
 743                                                 *p++ = REG_RD(bp,
 744                                                        read_addr[k].addr + n*4);
 745                 }
 746         }
 747 }
 748
 749 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 750 {
 751         u32 i, j;
 752
 753         /* Read the regular registers */
 754         for (i = 0; i < REGS_COUNT; i++)
 755                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 756                         for (j = 0; j < reg_addrs[i].size; j++)
 757                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 758
 759         /* Read "paged" registes */
 760         bnx2x_read_pages_regs(bp, p);
 761 }
 762
 763 static void bnx2x_get_regs(struct net_device *dev,
 764                            struct ethtool_regs *regs, void *_p)
 765 {
 766         u32 *p = _p;
 767         struct bnx2x *bp = netdev_priv(dev);
 768         struct dump_hdr dump_hdr = {0};
 769
 770         regs->version = 0;
 771         memset(p, 0, regs->len);
 772
 773         if (!netif_running(bp->dev))
 774                 return;
 775
 776         /* Disable parity attentions as long as following dump may
 777          * cause false alarms by reading never written registers. We
 778          * will re-enable parity attentions right after the dump.
 779          */
 780         bnx2x_disable_blocks_parity(bp);
 781
 782         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
 783         dump_hdr.dump_sign = dump_sign_all;
 784         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
 785         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
 786         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
 787         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
 788
 789         if (CHIP_IS_E1(bp))
 790                 dump_hdr.info = RI_E1_ONLINE;
 791         else if (CHIP_IS_E1H(bp))
 792                 dump_hdr.info = RI_E1H_ONLINE;
 793         else if (!CHIP_IS_E1x(bp))
 794                 dump_hdr.info = RI_E2_ONLINE |
 795                 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
 796
 797         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
 798         p += dump_hdr.hdr_size + 1;
 799
 800         /* Actually read the registers */
 801         __bnx2x_get_regs(bp, p);
 802
 803         /* Re-enable parity attentions */
 804         bnx2x_clear_blocks_parity(bp);
 805         bnx2x_enable_blocks_parity(bp);
 806 }
 807
 808 static void bnx2x_get_drvinfo(struct net_device *dev,
 809                               struct ethtool_drvinfo *info)
 810 {
 811         struct bnx2x *bp = netdev_priv(dev);
 812         u8 phy_fw_ver[PHY_FW_VER_LEN];
 813
 814         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
 815         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
 816
 817         phy_fw_ver[0] = '\0';
 818         bnx2x_get_ext_phy_fw_version(&bp->link_params,
 819                                      phy_fw_ver, PHY_FW_VER_LEN);
 820         strlcpy(info->fw_version, bp->fw_ver, sizeof(info->fw_version));
 821         snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
 822                  "bc %d.%d.%d%s%s",
 823                  (bp->common.bc_ver & 0xff0000) >> 16,
 824                  (bp->common.bc_ver & 0xff00) >> 8,
 825                  (bp->common.bc_ver & 0xff),
 826                  ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
 827         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
 828         info->n_stats = BNX2X_NUM_STATS;
 829         info->testinfo_len = BNX2X_NUM_TESTS(bp);
 830         info->eedump_len = bp->common.flash_size;
 831         info->regdump_len = bnx2x_get_regs_len(dev);
 832 }
 833
 834 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 835 {
 836         struct bnx2x *bp = netdev_priv(dev);
 837
 838         if (bp->flags & NO_WOL_FLAG) {
 839                 wol->supported = 0;
 840                 wol->wolopts = 0;
 841         } else {
 842                 wol->supported = WAKE_MAGIC;
 843                 if (bp->wol)
 844                         wol->wolopts = WAKE_MAGIC;
 845                 else
 846                         wol->wolopts = 0;
 847         }
 848         memset(&wol->sopass, 0, sizeof(wol->sopass));
 849 }
 850
 851 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 852 {
 853         struct bnx2x *bp = netdev_priv(dev);
 854
 855         if (wol->wolopts & ~WAKE_MAGIC) {
 856                 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
 857                 return -EINVAL;
 858         }
 859
 860         if (wol->wolopts & WAKE_MAGIC) {
 861                 if (bp->flags & NO_WOL_FLAG) {
 862                         DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
 863                         return -EINVAL;
 864                 }
 865                 bp->wol = 1;
 866         } else
 867                 bp->wol = 0;
 868
 869         return 0;
 870 }
 871
 872 static u32 bnx2x_get_msglevel(struct net_device *dev)
 873 {
 874         struct bnx2x *bp = netdev_priv(dev);
 875
 876         return bp->msg_enable;
 877 }
 878
 879 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
 880 {
 881         struct bnx2x *bp = netdev_priv(dev);
 882
 883         if (capable(CAP_NET_ADMIN)) {
 884                 /* dump MCP trace */
 885                 if (level & BNX2X_MSG_MCP)
 886                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
 887                 bp->msg_enable = level;
 888         }
 889 }
 890
 891 static int bnx2x_nway_reset(struct net_device *dev)
 892 {
 893         struct bnx2x *bp = netdev_priv(dev);
 894
 895         if (!bp->port.pmf)
 896                 return 0;
 897
 898         if (netif_running(dev)) {
 899                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 900                 bnx2x_link_set(bp);
 901         }
 902
 903         return 0;
 904 }
 905
 906 static u32 bnx2x_get_link(struct net_device *dev)
 907 {
 908         struct bnx2x *bp = netdev_priv(dev);
 909
 910         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
 911                 return 0;
 912
 913         return bp->link_vars.link_up;
 914 }
 915
 916 static int bnx2x_get_eeprom_len(struct net_device *dev)
 917 {
 918         struct bnx2x *bp = netdev_priv(dev);
 919
 920         return bp->common.flash_size;
 921 }
 922
 923 /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
 924  * we done things the other way around, if two pfs from the same port would
 925  * attempt to access nvram at the same time, we could run into a scenario such
 926  * as:
 927  * pf A takes the port lock.
 928  * pf B succeeds in taking the same lock since they are from the same port.
 929  * pf A takes the per pf misc lock. Performs eeprom access.
 930  * pf A finishes. Unlocks the per pf misc lock.
 931  * Pf B takes the lock and proceeds to perform it's own access.
 932  * pf A unlocks the per port lock, while pf B is still working (!).
 933  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
 934  * acess corrupted by pf B).*
 935  */
 936 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 937 {
 938         int port = BP_PORT(bp);
 939         int count, i;
 940         u32 val;
 941
 942         /* acquire HW lock: protect against other PFs in PF Direct Assignment */
 943         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
 944
 945         /* adjust timeout for emulation/FPGA */
 946         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 947         if (CHIP_REV_IS_SLOW(bp))
 948                 count *= 100;
 949
 950         /* request access to nvram interface */
 951         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 952                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
 953
 954         for (i = 0; i < count*10; i++) {
 955                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 956                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
 957                         break;
 958
 959                 udelay(5);
 960         }
 961
 962         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
 963                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
 964                    "cannot get access to nvram interface\n");
 965                 return -EBUSY;
 966         }
 967
 968         return 0;
 969 }
 970
 971 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 972 {
 973         int port = BP_PORT(bp);
 974         int count, i;
 975         u32 val;
 976
 977         /* adjust timeout for emulation/FPGA */
 978         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 979         if (CHIP_REV_IS_SLOW(bp))
 980                 count *= 100;
 981
 982         /* relinquish nvram interface */
 983         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 984                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
 985
 986         for (i = 0; i < count*10; i++) {
 987                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 988                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
 989                         break;
 990
 991                 udelay(5);
 992         }
 993
 994         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
 995                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
 996                    "cannot free access to nvram interface\n");
 997                 return -EBUSY;
 998         }
 999
1000         /* release HW lock: protect against other PFs in PF Direct Assignment */
1001         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1002         return 0;
1003 }
1004
1005 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1006 {
1007         u32 val;
1008
1009         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1010
1011         /* enable both bits, even on read */
1012         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1013                (val | MCPR_NVM_ACCESS_ENABLE_EN |
1014                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
1015 }
1016
1017 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1018 {
1019         u32 val;
1020
1021         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1022
1023         /* disable both bits, even after read */
1024         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1025                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1026                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1027 }
1028
1029 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1030                                   u32 cmd_flags)
1031 {
1032         int count, i, rc;
1033         u32 val;
1034
1035         /* build the command word */
1036         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1037
1038         /* need to clear DONE bit separately */
1039         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1040
1041         /* address of the NVRAM to read from */
1042         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1043                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1044
1045         /* issue a read command */
1046         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1047
1048         /* adjust timeout for emulation/FPGA */
1049         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1050         if (CHIP_REV_IS_SLOW(bp))
1051                 count *= 100;
1052
1053         /* wait for completion */
1054         *ret_val = 0;
1055         rc = -EBUSY;
1056         for (i = 0; i < count; i++) {
1057                 udelay(5);
1058                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1059
1060                 if (val & MCPR_NVM_COMMAND_DONE) {
1061                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1062                         /* we read nvram data in cpu order
1063                          * but ethtool sees it as an array of bytes
1064                          * converting to big-endian will do the work */
1065                         *ret_val = cpu_to_be32(val);
1066                         rc = 0;
1067                         break;
1068                 }
1069         }
1070         if (rc == -EBUSY)
1071                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1072                    "nvram read timeout expired\n");
1073         return rc;
1074 }
1075
1076 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1077                             int buf_size)
1078 {
1079         int rc;
1080         u32 cmd_flags;
1081         __be32 val;
1082
1083         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1084                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1085                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1086                    offset, buf_size);
1087                 return -EINVAL;
1088         }
1089
1090         if (offset + buf_size > bp->common.flash_size) {
1091                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1092                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1093                    offset, buf_size, bp->common.flash_size);
1094                 return -EINVAL;
1095         }
1096
1097         /* request access to nvram interface */
1098         rc = bnx2x_acquire_nvram_lock(bp);
1099         if (rc)
1100                 return rc;
1101
1102         /* enable access to nvram interface */
1103         bnx2x_enable_nvram_access(bp);
1104
1105         /* read the first word(s) */
1106         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1107         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1108                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1109                 memcpy(ret_buf, &val, 4);
1110
1111                 /* advance to the next dword */
1112                 offset += sizeof(u32);
1113                 ret_buf += sizeof(u32);
1114                 buf_size -= sizeof(u32);
1115                 cmd_flags = 0;
1116         }
1117
1118         if (rc == 0) {
1119                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1120                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1121                 memcpy(ret_buf, &val, 4);
1122         }
1123
1124         /* disable access to nvram interface */
1125         bnx2x_disable_nvram_access(bp);
1126         bnx2x_release_nvram_lock(bp);
1127
1128         return rc;
1129 }
1130
1131 static int bnx2x_get_eeprom(struct net_device *dev,
1132                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1133 {
1134         struct bnx2x *bp = netdev_priv(dev);
1135         int rc;
1136
1137         if (!netif_running(dev)) {
1138                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1139                    "cannot access eeprom when the interface is down\n");
1140                 return -EAGAIN;
1141         }
1142
1143         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1144            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1145            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1146            eeprom->len, eeprom->len);
1147
1148         /* parameters already validated in ethtool_get_eeprom */
1149
1150         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1151
1152         return rc;
1153 }
1154
1155 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1156                                    u32 cmd_flags)
1157 {
1158         int count, i, rc;
1159
1160         /* build the command word */
1161         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1162
1163         /* need to clear DONE bit separately */
1164         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1165
1166         /* write the data */
1167         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1168
1169         /* address of the NVRAM to write to */
1170         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1171                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1172
1173         /* issue the write command */
1174         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1175
1176         /* adjust timeout for emulation/FPGA */
1177         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1178         if (CHIP_REV_IS_SLOW(bp))
1179                 count *= 100;
1180
1181         /* wait for completion */
1182         rc = -EBUSY;
1183         for (i = 0; i < count; i++) {
1184                 udelay(5);
1185                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1186                 if (val & MCPR_NVM_COMMAND_DONE) {
1187                         rc = 0;
1188                         break;
1189                 }
1190         }
1191
1192         if (rc == -EBUSY)
1193                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1194                    "nvram write timeout expired\n");
1195         return rc;
1196 }
1197
1198 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1199
1200 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1201                               int buf_size)
1202 {
1203         int rc;
1204         u32 cmd_flags;
1205         u32 align_offset;
1206         __be32 val;
1207
1208         if (offset + buf_size > bp->common.flash_size) {
1209                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1210                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1211                    offset, buf_size, bp->common.flash_size);
1212                 return -EINVAL;
1213         }
1214
1215         /* request access to nvram interface */
1216         rc = bnx2x_acquire_nvram_lock(bp);
1217         if (rc)
1218                 return rc;
1219
1220         /* enable access to nvram interface */
1221         bnx2x_enable_nvram_access(bp);
1222
1223         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1224         align_offset = (offset & ~0x03);
1225         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1226
1227         if (rc == 0) {
1228                 val &= ~(0xff << BYTE_OFFSET(offset));
1229                 val |= (*data_buf << BYTE_OFFSET(offset));
1230
1231                 /* nvram data is returned as an array of bytes
1232                  * convert it back to cpu order */
1233                 val = be32_to_cpu(val);
1234
1235                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1236                                              cmd_flags);
1237         }
1238
1239         /* disable access to nvram interface */
1240         bnx2x_disable_nvram_access(bp);
1241         bnx2x_release_nvram_lock(bp);
1242
1243         return rc;
1244 }
1245
1246 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1247                              int buf_size)
1248 {
1249         int rc;
1250         u32 cmd_flags;
1251         u32 val;
1252         u32 written_so_far;
1253
1254         if (buf_size == 1)      /* ethtool */
1255                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1256
1257         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1258                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1259                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1260                    offset, buf_size);
1261                 return -EINVAL;
1262         }
1263
1264         if (offset + buf_size > bp->common.flash_size) {
1265                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1266                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1267                    offset, buf_size, bp->common.flash_size);
1268                 return -EINVAL;
1269         }
1270
1271         /* request access to nvram interface */
1272         rc = bnx2x_acquire_nvram_lock(bp);
1273         if (rc)
1274                 return rc;
1275
1276         /* enable access to nvram interface */
1277         bnx2x_enable_nvram_access(bp);
1278
1279         written_so_far = 0;
1280         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1281         while ((written_so_far < buf_size) && (rc == 0)) {
1282                 if (written_so_far == (buf_size - sizeof(u32)))
1283                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1284                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1285                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1286                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1287                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1288
1289                 memcpy(&val, data_buf, 4);
1290
1291                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1292
1293                 /* advance to the next dword */
1294                 offset += sizeof(u32);
1295                 data_buf += sizeof(u32);
1296                 written_so_far += sizeof(u32);
1297                 cmd_flags = 0;
1298         }
1299
1300         /* disable access to nvram interface */
1301         bnx2x_disable_nvram_access(bp);
1302         bnx2x_release_nvram_lock(bp);
1303
1304         return rc;
1305 }
1306
1307 static int bnx2x_set_eeprom(struct net_device *dev,
1308                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1309 {
1310         struct bnx2x *bp = netdev_priv(dev);
1311         int port = BP_PORT(bp);
1312         int rc = 0;
1313         u32 ext_phy_config;
1314         if (!netif_running(dev)) {
1315                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1316                    "cannot access eeprom when the interface is down\n");
1317                 return -EAGAIN;
1318         }
1319
1320         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1321            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1322            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1323            eeprom->len, eeprom->len);
1324
1325         /* parameters already validated in ethtool_set_eeprom */
1326
1327         /* PHY eeprom can be accessed only by the PMF */
1328         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1329             !bp->port.pmf) {
1330                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1331                    "wrong magic or interface is not pmf\n");
1332                 return -EINVAL;
1333         }
1334
1335         ext_phy_config =
1336                 SHMEM_RD(bp,
1337                          dev_info.port_hw_config[port].external_phy_config);
1338
1339         if (eeprom->magic == 0x50485950) {
1340                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1341                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1342
1343                 bnx2x_acquire_phy_lock(bp);
1344                 rc |= bnx2x_link_reset(&bp->link_params,
1345                                        &bp->link_vars, 0);
1346                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1347                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1348                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1349                                        MISC_REGISTERS_GPIO_HIGH, port);
1350                 bnx2x_release_phy_lock(bp);
1351                 bnx2x_link_report(bp);
1352
1353         } else if (eeprom->magic == 0x50485952) {
1354                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1355                 if (bp->state == BNX2X_STATE_OPEN) {
1356                         bnx2x_acquire_phy_lock(bp);
1357                         rc |= bnx2x_link_reset(&bp->link_params,
1358                                                &bp->link_vars, 1);
1359
1360                         rc |= bnx2x_phy_init(&bp->link_params,
1361                                              &bp->link_vars);
1362                         bnx2x_release_phy_lock(bp);
1363                         bnx2x_calc_fc_adv(bp);
1364                 }
1365         } else if (eeprom->magic == 0x53985943) {
1366                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1367                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1368                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1369
1370                         /* DSP Remove Download Mode */
1371                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1372                                        MISC_REGISTERS_GPIO_LOW, port);
1373
1374                         bnx2x_acquire_phy_lock(bp);
1375
1376                         bnx2x_sfx7101_sp_sw_reset(bp,
1377                                                 &bp->link_params.phy[EXT_PHY1]);
1378
1379                         /* wait 0.5 sec to allow it to run */
1380                         msleep(500);
1381                         bnx2x_ext_phy_hw_reset(bp, port);
1382                         msleep(500);
1383                         bnx2x_release_phy_lock(bp);
1384                 }
1385         } else
1386                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1387
1388         return rc;
1389 }
1390
1391 static int bnx2x_get_coalesce(struct net_device *dev,
1392                               struct ethtool_coalesce *coal)
1393 {
1394         struct bnx2x *bp = netdev_priv(dev);
1395
1396         memset(coal, 0, sizeof(struct ethtool_coalesce));
1397
1398         coal->rx_coalesce_usecs = bp->rx_ticks;
1399         coal->tx_coalesce_usecs = bp->tx_ticks;
1400
1401         return 0;
1402 }
1403
1404 static int bnx2x_set_coalesce(struct net_device *dev,
1405                               struct ethtool_coalesce *coal)
1406 {
1407         struct bnx2x *bp = netdev_priv(dev);
1408
1409         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1410         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1411                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1412
1413         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1414         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1415                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1416
1417         if (netif_running(dev))
1418                 bnx2x_update_coalesce(bp);
1419
1420         return 0;
1421 }
1422
1423 static void bnx2x_get_ringparam(struct net_device *dev,
1424                                 struct ethtool_ringparam *ering)
1425 {
1426         struct bnx2x *bp = netdev_priv(dev);
1427
1428         ering->rx_max_pending = MAX_RX_AVAIL;
1429
1430         if (bp->rx_ring_size)
1431                 ering->rx_pending = bp->rx_ring_size;
1432         else
1433                 ering->rx_pending = MAX_RX_AVAIL;
1434
1435         ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1436         ering->tx_pending = bp->tx_ring_size;
1437 }
1438
1439 static int bnx2x_set_ringparam(struct net_device *dev,
1440                                struct ethtool_ringparam *ering)
1441 {
1442         struct bnx2x *bp = netdev_priv(dev);
1443
1444         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1445                 DP(BNX2X_MSG_ETHTOOL,
1446                    "Handling parity error recovery. Try again later\n");
1447                 return -EAGAIN;
1448         }
1449
1450         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1451             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1452                                                     MIN_RX_SIZE_TPA)) ||
1453             (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
1454             (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1455                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1456                 return -EINVAL;
1457         }
1458
1459         bp->rx_ring_size = ering->rx_pending;
1460         bp->tx_ring_size = ering->tx_pending;
1461
1462         return bnx2x_reload_if_running(dev);
1463 }
1464
1465 static void bnx2x_get_pauseparam(struct net_device *dev,
1466                                  struct ethtool_pauseparam *epause)
1467 {
1468         struct bnx2x *bp = netdev_priv(dev);
1469         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1470         int cfg_reg;
1471
1472         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1473                            BNX2X_FLOW_CTRL_AUTO);
1474
1475         if (!epause->autoneg)
1476                 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1477         else
1478                 cfg_reg = bp->link_params.req_fc_auto_adv;
1479
1480         epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1481                             BNX2X_FLOW_CTRL_RX);
1482         epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1483                             BNX2X_FLOW_CTRL_TX);
1484
1485         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1486            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1487            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1488 }
1489
1490 static int bnx2x_set_pauseparam(struct net_device *dev,
1491                                 struct ethtool_pauseparam *epause)
1492 {
1493         struct bnx2x *bp = netdev_priv(dev);
1494         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1495         if (IS_MF(bp))
1496                 return 0;
1497
1498         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1499            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1500            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1501
1502         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1503
1504         if (epause->rx_pause)
1505                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1506
1507         if (epause->tx_pause)
1508                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1509
1510         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1511                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1512
1513         if (epause->autoneg) {
1514                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1515                         DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1516                         return -EINVAL;
1517                 }
1518
1519                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1520                         bp->link_params.req_flow_ctrl[cfg_idx] =
1521                                 BNX2X_FLOW_CTRL_AUTO;
1522                 }
1523         }
1524
1525         DP(BNX2X_MSG_ETHTOOL,
1526            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1527
1528         if (netif_running(dev)) {
1529                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1530                 bnx2x_link_set(bp);
1531         }
1532
1533         return 0;
1534 }
1535
1536 char *bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF] = {
1537         "register_test (offline)    ",
1538         "memory_test (offline)      ",
1539         "int_loopback_test (offline)",
1540         "ext_loopback_test (offline)",
1541         "nvram_test (online)        ",
1542         "interrupt_test (online)    ",
1543         "link_test (online)         "
1544 };
1545
1546 static u32 bnx2x_eee_to_adv(u32 eee_adv)
1547 {
1548         u32 modes = 0;
1549
1550         if (eee_adv & SHMEM_EEE_100M_ADV)
1551                 modes |= ADVERTISED_100baseT_Full;
1552         if (eee_adv & SHMEM_EEE_1G_ADV)
1553                 modes |= ADVERTISED_1000baseT_Full;
1554         if (eee_adv & SHMEM_EEE_10G_ADV)
1555                 modes |= ADVERTISED_10000baseT_Full;
1556
1557         return modes;
1558 }
1559
1560 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1561 {
1562         u32 eee_adv = 0;
1563         if (modes & ADVERTISED_100baseT_Full)
1564                 eee_adv |= SHMEM_EEE_100M_ADV;
1565         if (modes & ADVERTISED_1000baseT_Full)
1566                 eee_adv |= SHMEM_EEE_1G_ADV;
1567         if (modes & ADVERTISED_10000baseT_Full)
1568                 eee_adv |= SHMEM_EEE_10G_ADV;
1569
1570         return eee_adv << shift;
1571 }
1572
1573 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1574 {
1575         struct bnx2x *bp = netdev_priv(dev);
1576         u32 eee_cfg;
1577
1578         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1579                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1580                 return -EOPNOTSUPP;
1581         }
1582
1583         eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
1584
1585         edata->supported =
1586                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1587                                  SHMEM_EEE_SUPPORTED_SHIFT);
1588
1589         edata->advertised =
1590                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1591                                  SHMEM_EEE_ADV_STATUS_SHIFT);
1592         edata->lp_advertised =
1593                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1594                                  SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1595
1596         /* SHMEM value is in 16u units --> Convert to 1u units. */
1597         edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1598
1599         edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
1600         edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
1601         edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1602
1603         return 0;
1604 }
1605
1606 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1607 {
1608         struct bnx2x *bp = netdev_priv(dev);
1609         u32 eee_cfg;
1610         u32 advertised;
1611
1612         if (IS_MF(bp))
1613                 return 0;
1614
1615         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1616                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1617                 return -EOPNOTSUPP;
1618         }
1619
1620         eee_cfg = SHMEM2_RD(bp, eee_status[BP_PORT(bp)]);
1621
1622         if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1623                 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1624                 return -EOPNOTSUPP;
1625         }
1626
1627         advertised = bnx2x_adv_to_eee(edata->advertised,
1628                                       SHMEM_EEE_ADV_STATUS_SHIFT);
1629         if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1630                 DP(BNX2X_MSG_ETHTOOL,
1631                    "Direct manipulation of EEE advertisment is not supported\n");
1632                 return -EINVAL;
1633         }
1634
1635         if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1636                 DP(BNX2X_MSG_ETHTOOL,
1637                    "Maximal Tx Lpi timer supported is %x(u)\n",
1638                    EEE_MODE_TIMER_MASK);
1639                 return -EINVAL;
1640         }
1641         if (edata->tx_lpi_enabled &&
1642             (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1643                 DP(BNX2X_MSG_ETHTOOL,
1644                    "Minimal Tx Lpi timer supported is %d(u)\n",
1645                    EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1646                 return -EINVAL;
1647         }
1648
1649         /* All is well; Apply changes*/
1650         if (edata->eee_enabled)
1651                 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1652         else
1653                 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1654
1655         if (edata->tx_lpi_enabled)
1656                 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1657         else
1658                 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1659
1660         bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1661         bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1662                                     EEE_MODE_TIMER_MASK) |
1663                                     EEE_MODE_OVERRIDE_NVRAM |
1664                                     EEE_MODE_OUTPUT_TIME;
1665
1666         /* Restart link to propogate changes */
1667         if (netif_running(dev)) {
1668                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1669                 bnx2x_link_set(bp);
1670         }
1671
1672         return 0;
1673 }
1674
1675
1676 enum {
1677         BNX2X_CHIP_E1_OFST = 0,
1678         BNX2X_CHIP_E1H_OFST,
1679         BNX2X_CHIP_E2_OFST,
1680         BNX2X_CHIP_E3_OFST,
1681         BNX2X_CHIP_E3B0_OFST,
1682         BNX2X_CHIP_MAX_OFST
1683 };
1684
1685 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
1686 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
1687 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
1688 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
1689 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
1690
1691 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1692 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1693
1694 static int bnx2x_test_registers(struct bnx2x *bp)
1695 {
1696         int idx, i, rc = -ENODEV;
1697         u32 wr_val = 0, hw;
1698         int port = BP_PORT(bp);
1699         static const struct {
1700                 u32 hw;
1701                 u32 offset0;
1702                 u32 offset1;
1703                 u32 mask;
1704         } reg_tbl[] = {
1705 /* 0 */         { BNX2X_CHIP_MASK_ALL,
1706                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1707                 { BNX2X_CHIP_MASK_ALL,
1708                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
1709                 { BNX2X_CHIP_MASK_E1X,
1710                         HC_REG_AGG_INT_0,               4, 0x000003ff },
1711                 { BNX2X_CHIP_MASK_ALL,
1712                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
1713                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1714                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
1715                 { BNX2X_CHIP_MASK_E3B0,
1716                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
1717                 { BNX2X_CHIP_MASK_ALL,
1718                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
1719                 { BNX2X_CHIP_MASK_ALL,
1720                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
1721                 { BNX2X_CHIP_MASK_ALL,
1722                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1723                 { BNX2X_CHIP_MASK_ALL,
1724                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
1725 /* 10 */        { BNX2X_CHIP_MASK_ALL,
1726                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1727                 { BNX2X_CHIP_MASK_ALL,
1728                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
1729                 { BNX2X_CHIP_MASK_ALL,
1730                         QM_REG_CONNNUM_0,               4, 0x000fffff },
1731                 { BNX2X_CHIP_MASK_ALL,
1732                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
1733                 { BNX2X_CHIP_MASK_ALL,
1734                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
1735                 { BNX2X_CHIP_MASK_ALL,
1736                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
1737                 { BNX2X_CHIP_MASK_ALL,
1738                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1739                 { BNX2X_CHIP_MASK_ALL,
1740                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
1741                 { BNX2X_CHIP_MASK_ALL,
1742                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
1743                 { BNX2X_CHIP_MASK_ALL,
1744                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
1745 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1746                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
1747                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1748                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
1749                 { BNX2X_CHIP_MASK_ALL,
1750                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
1751                 { BNX2X_CHIP_MASK_ALL,
1752                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
1753                 { BNX2X_CHIP_MASK_ALL,
1754                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
1755                 { BNX2X_CHIP_MASK_ALL,
1756                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
1757                 { BNX2X_CHIP_MASK_ALL,
1758                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
1759                 { BNX2X_CHIP_MASK_ALL,
1760                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
1761                 { BNX2X_CHIP_MASK_ALL,
1762                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
1763                 { BNX2X_CHIP_MASK_ALL,
1764                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
1765 /* 30 */        { BNX2X_CHIP_MASK_ALL,
1766                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
1767                 { BNX2X_CHIP_MASK_ALL,
1768                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
1769                 { BNX2X_CHIP_MASK_ALL,
1770                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1771                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1772                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
1773                 { BNX2X_CHIP_MASK_ALL,
1774                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1775                 { BNX2X_CHIP_MASK_ALL,
1776                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1777                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1778                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1779                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1780                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
1781
1782                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
1783         };
1784
1785         if (!netif_running(bp->dev)) {
1786                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1787                    "cannot access eeprom when the interface is down\n");
1788                 return rc;
1789         }
1790
1791         if (CHIP_IS_E1(bp))
1792                 hw = BNX2X_CHIP_MASK_E1;
1793         else if (CHIP_IS_E1H(bp))
1794                 hw = BNX2X_CHIP_MASK_E1H;
1795         else if (CHIP_IS_E2(bp))
1796                 hw = BNX2X_CHIP_MASK_E2;
1797         else if (CHIP_IS_E3B0(bp))
1798                 hw = BNX2X_CHIP_MASK_E3B0;
1799         else /* e3 A0 */
1800                 hw = BNX2X_CHIP_MASK_E3;
1801
1802         /* Repeat the test twice:
1803            First by writing 0x00000000, second by writing 0xffffffff */
1804         for (idx = 0; idx < 2; idx++) {
1805
1806                 switch (idx) {
1807                 case 0:
1808                         wr_val = 0;
1809                         break;
1810                 case 1:
1811                         wr_val = 0xffffffff;
1812                         break;
1813                 }
1814
1815                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1816                         u32 offset, mask, save_val, val;
1817                         if (!(hw & reg_tbl[i].hw))
1818                                 continue;
1819
1820                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1821                         mask = reg_tbl[i].mask;
1822
1823                         save_val = REG_RD(bp, offset);
1824
1825                         REG_WR(bp, offset, wr_val & mask);
1826
1827                         val = REG_RD(bp, offset);
1828
1829                         /* Restore the original register's value */
1830                         REG_WR(bp, offset, save_val);
1831
1832                         /* verify value is as expected */
1833                         if ((val & mask) != (wr_val & mask)) {
1834                                 DP(BNX2X_MSG_ETHTOOL,
1835                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1836                                    offset, val, wr_val, mask);
1837                                 goto test_reg_exit;
1838                         }
1839                 }
1840         }
1841
1842         rc = 0;
1843
1844 test_reg_exit:
1845         return rc;
1846 }
1847
1848 static int bnx2x_test_memory(struct bnx2x *bp)
1849 {
1850         int i, j, rc = -ENODEV;
1851         u32 val, index;
1852         static const struct {
1853                 u32 offset;
1854                 int size;
1855         } mem_tbl[] = {
1856                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
1857                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1858                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
1859                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
1860                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
1861                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
1862                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
1863
1864                 { 0xffffffff, 0 }
1865         };
1866
1867         static const struct {
1868                 char *name;
1869                 u32 offset;
1870                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
1871         } prty_tbl[] = {
1872                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
1873                         {0x3ffc0, 0,   0, 0} },
1874                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
1875                         {0x2,     0x2, 0, 0} },
1876                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1877                         {0,       0,   0, 0} },
1878                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
1879                         {0x3ffc0, 0,   0, 0} },
1880                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
1881                         {0x3ffc0, 0,   0, 0} },
1882                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
1883                         {0x3ffc1, 0,   0, 0} },
1884
1885                 { NULL, 0xffffffff, {0, 0, 0, 0} }
1886         };
1887
1888         if (!netif_running(bp->dev)) {
1889                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1890                    "cannot access eeprom when the interface is down\n");
1891                 return rc;
1892         }
1893
1894         if (CHIP_IS_E1(bp))
1895                 index = BNX2X_CHIP_E1_OFST;
1896         else if (CHIP_IS_E1H(bp))
1897                 index = BNX2X_CHIP_E1H_OFST;
1898         else if (CHIP_IS_E2(bp))
1899                 index = BNX2X_CHIP_E2_OFST;
1900         else /* e3 */
1901                 index = BNX2X_CHIP_E3_OFST;
1902
1903         /* pre-Check the parity status */
1904         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1905                 val = REG_RD(bp, prty_tbl[i].offset);
1906                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1907                         DP(BNX2X_MSG_ETHTOOL,
1908                            "%s is 0x%x\n", prty_tbl[i].name, val);
1909                         goto test_mem_exit;
1910                 }
1911         }
1912
1913         /* Go through all the memories */
1914         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1915                 for (j = 0; j < mem_tbl[i].size; j++)
1916                         REG_RD(bp, mem_tbl[i].offset + j*4);
1917
1918         /* Check the parity status */
1919         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1920                 val = REG_RD(bp, prty_tbl[i].offset);
1921                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1922                         DP(BNX2X_MSG_ETHTOOL,
1923                            "%s is 0x%x\n", prty_tbl[i].name, val);
1924                         goto test_mem_exit;
1925                 }
1926         }
1927
1928         rc = 0;
1929
1930 test_mem_exit:
1931         return rc;
1932 }
1933
1934 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1935 {
1936         int cnt = 1400;
1937
1938         if (link_up) {
1939                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1940                         msleep(20);
1941
1942                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
1943                         DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
1944
1945                 cnt = 1400;
1946                 while (!bp->link_vars.link_up && cnt--)
1947                         msleep(20);
1948
1949                 if (cnt <= 0 && !bp->link_vars.link_up)
1950                         DP(BNX2X_MSG_ETHTOOL,
1951                            "Timeout waiting for link init\n");
1952         }
1953 }
1954
1955 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
1956 {
1957         unsigned int pkt_size, num_pkts, i;
1958         struct sk_buff *skb;
1959         unsigned char *packet;
1960         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1961         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1962         struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
1963         u16 tx_start_idx, tx_idx;
1964         u16 rx_start_idx, rx_idx;
1965         u16 pkt_prod, bd_prod;
1966         struct sw_tx_bd *tx_buf;
1967         struct eth_tx_start_bd *tx_start_bd;
1968         struct eth_tx_parse_bd_e1x  *pbd_e1x = NULL;
1969         struct eth_tx_parse_bd_e2  *pbd_e2 = NULL;
1970         dma_addr_t mapping;
1971         union eth_rx_cqe *cqe;
1972         u8 cqe_fp_flags, cqe_fp_type;
1973         struct sw_rx_bd *rx_buf;
1974         u16 len;
1975         int rc = -ENODEV;
1976         u8 *data;
1977         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
1978                                                        txdata->txq_index);
1979
1980         /* check the loopback mode */
1981         switch (loopback_mode) {
1982         case BNX2X_PHY_LOOPBACK:
1983                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
1984                         DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
1985                         return -EINVAL;
1986                 }
1987                 break;
1988         case BNX2X_MAC_LOOPBACK:
1989                 if (CHIP_IS_E3(bp)) {
1990                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1991                         if (bp->port.supported[cfg_idx] &
1992                             (SUPPORTED_10000baseT_Full |
1993                              SUPPORTED_20000baseMLD2_Full |
1994                              SUPPORTED_20000baseKR2_Full))
1995                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
1996                         else
1997                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
1998                 } else
1999                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
2000
2001                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2002                 break;
2003         case BNX2X_EXT_LOOPBACK:
2004                 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2005                         DP(BNX2X_MSG_ETHTOOL,
2006                            "Can't configure external loopback\n");
2007                         return -EINVAL;
2008                 }
2009                 break;
2010         default:
2011                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2012                 return -EINVAL;
2013         }
2014
2015         /* prepare the loopback packet */
2016         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2017                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2018         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2019         if (!skb) {
2020                 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2021                 rc = -ENOMEM;
2022                 goto test_loopback_exit;
2023         }
2024         packet = skb_put(skb, pkt_size);
2025         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2026         memset(packet + ETH_ALEN, 0, ETH_ALEN);
2027         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2028         for (i = ETH_HLEN; i < pkt_size; i++)
2029                 packet[i] = (unsigned char) (i & 0xff);
2030         mapping = dma_map_single(&bp->pdev->dev, skb->data,
2031                                  skb_headlen(skb), DMA_TO_DEVICE);
2032         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2033                 rc = -ENOMEM;
2034                 dev_kfree_skb(skb);
2035                 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2036                 goto test_loopback_exit;
2037         }
2038
2039         /* send the loopback packet */
2040         num_pkts = 0;
2041         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2042         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2043
2044         netdev_tx_sent_queue(txq, skb->len);
2045
2046         pkt_prod = txdata->tx_pkt_prod++;
2047         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2048         tx_buf->first_bd = txdata->tx_bd_prod;
2049         tx_buf->skb = skb;
2050         tx_buf->flags = 0;
2051
2052         bd_prod = TX_BD(txdata->tx_bd_prod);
2053         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2054         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2055         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2056         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2057         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2058         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2059         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2060         SET_FLAG(tx_start_bd->general_data,
2061                  ETH_TX_START_BD_ETH_ADDR_TYPE,
2062                  UNICAST_ADDRESS);
2063         SET_FLAG(tx_start_bd->general_data,
2064                  ETH_TX_START_BD_HDR_NBDS,
2065                  1);
2066
2067         /* turn on parsing and get a BD */
2068         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2069
2070         pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2071         pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2072
2073         memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2074         memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2075
2076         wmb();
2077
2078         txdata->tx_db.data.prod += 2;
2079         barrier();
2080         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2081
2082         mmiowb();
2083         barrier();
2084
2085         num_pkts++;
2086         txdata->tx_bd_prod += 2; /* start + pbd */
2087
2088         udelay(100);
2089
2090         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2091         if (tx_idx != tx_start_idx + num_pkts)
2092                 goto test_loopback_exit;
2093
2094         /* Unlike HC IGU won't generate an interrupt for status block
2095          * updates that have been performed while interrupts were
2096          * disabled.
2097          */
2098         if (bp->common.int_block == INT_BLOCK_IGU) {
2099                 /* Disable local BHes to prevent a dead-lock situation between
2100                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
2101                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
2102                  */
2103                 local_bh_disable();
2104                 bnx2x_tx_int(bp, txdata);
2105                 local_bh_enable();
2106         }
2107
2108         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2109         if (rx_idx != rx_start_idx + num_pkts)
2110                 goto test_loopback_exit;
2111
2112         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2113         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2114         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2115         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2116                 goto test_loopback_rx_exit;
2117
2118         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2119         if (len != pkt_size)
2120                 goto test_loopback_rx_exit;
2121
2122         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2123         dma_sync_single_for_cpu(&bp->pdev->dev,
2124                                    dma_unmap_addr(rx_buf, mapping),
2125                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2126         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2127         for (i = ETH_HLEN; i < pkt_size; i++)
2128                 if (*(data + i) != (unsigned char) (i & 0xff))
2129                         goto test_loopback_rx_exit;
2130
2131         rc = 0;
2132
2133 test_loopback_rx_exit:
2134
2135         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2136         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2137         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2138         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2139
2140         /* Update producers */
2141         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2142                              fp_rx->rx_sge_prod);
2143
2144 test_loopback_exit:
2145         bp->link_params.loopback_mode = LOOPBACK_NONE;
2146
2147         return rc;
2148 }
2149
2150 static int bnx2x_test_loopback(struct bnx2x *bp)
2151 {
2152         int rc = 0, res;
2153
2154         if (BP_NOMCP(bp))
2155                 return rc;
2156
2157         if (!netif_running(bp->dev))
2158                 return BNX2X_LOOPBACK_FAILED;
2159
2160         bnx2x_netif_stop(bp, 1);
2161         bnx2x_acquire_phy_lock(bp);
2162
2163         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2164         if (res) {
2165                 DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2166                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2167         }
2168
2169         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2170         if (res) {
2171                 DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2172                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2173         }
2174
2175         bnx2x_release_phy_lock(bp);
2176         bnx2x_netif_start(bp);
2177
2178         return rc;
2179 }
2180
2181 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2182 {
2183         int rc;
2184         u8 is_serdes =
2185                 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2186
2187         if (BP_NOMCP(bp))
2188                 return -ENODEV;
2189
2190         if (!netif_running(bp->dev))
2191                 return BNX2X_EXT_LOOPBACK_FAILED;
2192
2193         bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2194         rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2195         if (rc) {
2196                 DP(BNX2X_MSG_ETHTOOL,
2197                    "Can't perform self-test, nic_load (for external lb) failed\n");
2198                 return -ENODEV;
2199         }
2200         bnx2x_wait_for_link(bp, 1, is_serdes);
2201
2202         bnx2x_netif_stop(bp, 1);
2203
2204         rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2205         if (rc)
2206                 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2207
2208         bnx2x_netif_start(bp);
2209
2210         return rc;
2211 }
2212
2213 #define CRC32_RESIDUAL                  0xdebb20e3
2214
2215 static int bnx2x_test_nvram(struct bnx2x *bp)
2216 {
2217         static const struct {
2218                 int offset;
2219                 int size;
2220         } nvram_tbl[] = {
2221                 {     0,  0x14 }, /* bootstrap */
2222                 {  0x14,  0xec }, /* dir */
2223                 { 0x100, 0x350 }, /* manuf_info */
2224                 { 0x450,  0xf0 }, /* feature_info */
2225                 { 0x640,  0x64 }, /* upgrade_key_info */
2226                 { 0x708,  0x70 }, /* manuf_key_info */
2227                 {     0,     0 }
2228         };
2229         __be32 *buf;
2230         u8 *data;
2231         int i, rc;
2232         u32 magic, crc;
2233
2234         if (BP_NOMCP(bp))
2235                 return 0;
2236
2237         buf = kmalloc(0x350, GFP_KERNEL);
2238         if (!buf) {
2239                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2240                 rc = -ENOMEM;
2241                 goto test_nvram_exit;
2242         }
2243         data = (u8 *)buf;
2244
2245         rc = bnx2x_nvram_read(bp, 0, data, 4);
2246         if (rc) {
2247                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2248                    "magic value read (rc %d)\n", rc);
2249                 goto test_nvram_exit;
2250         }
2251
2252         magic = be32_to_cpu(buf[0]);
2253         if (magic != 0x669955aa) {
2254                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2255                    "wrong magic value (0x%08x)\n", magic);
2256                 rc = -ENODEV;
2257                 goto test_nvram_exit;
2258         }
2259
2260         for (i = 0; nvram_tbl[i].size; i++) {
2261
2262                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2263                                       nvram_tbl[i].size);
2264                 if (rc) {
2265                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2266                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2267                         goto test_nvram_exit;
2268                 }
2269
2270                 crc = ether_crc_le(nvram_tbl[i].size, data);
2271                 if (crc != CRC32_RESIDUAL) {
2272                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2273                            "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
2274                         rc = -ENODEV;
2275                         goto test_nvram_exit;
2276                 }
2277         }
2278
2279 test_nvram_exit:
2280         kfree(buf);
2281         return rc;
2282 }
2283
2284 /* Send an EMPTY ramrod on the first queue */
2285 static int bnx2x_test_intr(struct bnx2x *bp)
2286 {
2287         struct bnx2x_queue_state_params params = {NULL};
2288
2289         if (!netif_running(bp->dev)) {
2290                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2291                    "cannot access eeprom when the interface is down\n");
2292                 return -ENODEV;
2293         }
2294
2295         params.q_obj = &bp->fp->q_obj;
2296         params.cmd = BNX2X_Q_CMD_EMPTY;
2297
2298         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2299
2300         return bnx2x_queue_state_change(bp, &params);
2301 }
2302
2303 static void bnx2x_self_test(struct net_device *dev,
2304                             struct ethtool_test *etest, u64 *buf)
2305 {
2306         struct bnx2x *bp = netdev_priv(dev);
2307         u8 is_serdes;
2308         int rc;
2309
2310         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2311                 netdev_err(bp->dev,
2312                            "Handling parity error recovery. Try again later\n");
2313                 etest->flags |= ETH_TEST_FL_FAILED;
2314                 return;
2315         }
2316         DP(BNX2X_MSG_ETHTOOL,
2317            "Self-test command parameters: offline = %d, external_lb = %d\n",
2318            (etest->flags & ETH_TEST_FL_OFFLINE),
2319            (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2320
2321         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2322
2323         if (!netif_running(dev)) {
2324                 DP(BNX2X_MSG_ETHTOOL,
2325                    "Can't perform self-test when interface is down\n");
2326                 return;
2327         }
2328
2329         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2330
2331         /* offline tests are not supported in MF mode */
2332         if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2333                 int port = BP_PORT(bp);
2334                 u32 val;
2335                 u8 link_up;
2336
2337                 /* save current value of input enable for TX port IF */
2338                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2339                 /* disable input for TX port IF */
2340                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2341
2342                 link_up = bp->link_vars.link_up;
2343
2344                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2345                 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2346                 if (rc) {
2347                         etest->flags |= ETH_TEST_FL_FAILED;
2348                         DP(BNX2X_MSG_ETHTOOL,
2349                            "Can't perform self-test, nic_load (for offline) failed\n");
2350                         return;
2351                 }
2352
2353                 /* wait until link state is restored */
2354                 bnx2x_wait_for_link(bp, 1, is_serdes);
2355
2356                 if (bnx2x_test_registers(bp) != 0) {
2357                         buf[0] = 1;
2358                         etest->flags |= ETH_TEST_FL_FAILED;
2359                 }
2360                 if (bnx2x_test_memory(bp) != 0) {
2361                         buf[1] = 1;
2362                         etest->flags |= ETH_TEST_FL_FAILED;
2363                 }
2364
2365                 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
2366                 if (buf[2] != 0)
2367                         etest->flags |= ETH_TEST_FL_FAILED;
2368
2369                 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2370                         buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2371                         if (buf[3] != 0)
2372                                 etest->flags |= ETH_TEST_FL_FAILED;
2373                         etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2374                 }
2375
2376                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2377
2378                 /* restore input for TX port IF */
2379                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2380                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2381                 if (rc) {
2382                         etest->flags |= ETH_TEST_FL_FAILED;
2383                         DP(BNX2X_MSG_ETHTOOL,
2384                            "Can't perform self-test, nic_load (for online) failed\n");
2385                         return;
2386                 }
2387                 /* wait until link state is restored */
2388                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2389         }
2390         if (bnx2x_test_nvram(bp) != 0) {
2391                 if (!IS_MF(bp))
2392                         buf[4] = 1;
2393                 else
2394                         buf[0] = 1;
2395                 etest->flags |= ETH_TEST_FL_FAILED;
2396         }
2397         if (bnx2x_test_intr(bp) != 0) {
2398                 if (!IS_MF(bp))
2399                         buf[5] = 1;
2400                 else
2401                         buf[1] = 1;
2402                 etest->flags |= ETH_TEST_FL_FAILED;
2403         }
2404
2405         if (bnx2x_link_test(bp, is_serdes) != 0) {
2406                 if (!IS_MF(bp))
2407                         buf[6] = 1;
2408                 else
2409                         buf[2] = 1;
2410                 etest->flags |= ETH_TEST_FL_FAILED;
2411         }
2412
2413 #ifdef BNX2X_EXTRA_DEBUG
2414         bnx2x_panic_dump(bp);
2415 #endif
2416 }
2417
2418 #define IS_PORT_STAT(i) \
2419         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2420 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2421 #define IS_MF_MODE_STAT(bp) \
2422                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2423
2424 /* ethtool statistics are displayed for all regular ethernet queues and the
2425  * fcoe L2 queue if not disabled
2426  */
2427 static int bnx2x_num_stat_queues(struct bnx2x *bp)
2428 {
2429         return BNX2X_NUM_ETH_QUEUES(bp);
2430 }
2431
2432 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2433 {
2434         struct bnx2x *bp = netdev_priv(dev);
2435         int i, num_stats;
2436
2437         switch (stringset) {
2438         case ETH_SS_STATS:
2439                 if (is_multi(bp)) {
2440                         num_stats = bnx2x_num_stat_queues(bp) *
2441                                                 BNX2X_NUM_Q_STATS;
2442                 } else
2443                         num_stats = 0;
2444                 if (IS_MF_MODE_STAT(bp)) {
2445                         for (i = 0; i < BNX2X_NUM_STATS; i++)
2446                                 if (IS_FUNC_STAT(i))
2447                                         num_stats++;
2448                 } else
2449                         num_stats += BNX2X_NUM_STATS;
2450
2451                 return num_stats;
2452
2453         case ETH_SS_TEST:
2454                 return BNX2X_NUM_TESTS(bp);
2455
2456         default:
2457                 return -EINVAL;
2458         }
2459 }
2460
2461 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2462 {
2463         struct bnx2x *bp = netdev_priv(dev);
2464         int i, j, k, offset, start;
2465         char queue_name[MAX_QUEUE_NAME_LEN+1];
2466
2467         switch (stringset) {
2468         case ETH_SS_STATS:
2469                 k = 0;
2470                 if (is_multi(bp)) {
2471                         for_each_eth_queue(bp, i) {
2472                                 memset(queue_name, 0, sizeof(queue_name));
2473                                 sprintf(queue_name, "%d", i);
2474                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2475                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2476                                                 ETH_GSTRING_LEN,
2477                                                 bnx2x_q_stats_arr[j].string,
2478                                                 queue_name);
2479                                 k += BNX2X_NUM_Q_STATS;
2480                         }
2481                 }
2482
2483
2484                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2485                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2486                                 continue;
2487                         strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2488                                    bnx2x_stats_arr[i].string);
2489                         j++;
2490                 }
2491
2492                 break;
2493
2494         case ETH_SS_TEST:
2495                 /* First 4 tests cannot be done in MF mode */
2496                 if (!IS_MF(bp))
2497                         start = 0;
2498                 else
2499                         start = 4;
2500                 for (i = 0, j = start; j < (start + BNX2X_NUM_TESTS(bp));
2501                      i++, j++) {
2502                         offset = sprintf(buf+32*i, "%s",
2503                                          bnx2x_tests_str_arr[j]);
2504                         *(buf+offset) = '\0';
2505                 }
2506                 break;
2507         }
2508 }
2509
2510 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2511                                     struct ethtool_stats *stats, u64 *buf)
2512 {
2513         struct bnx2x *bp = netdev_priv(dev);
2514         u32 *hw_stats, *offset;
2515         int i, j, k = 0;
2516
2517         if (is_multi(bp)) {
2518                 for_each_eth_queue(bp, i) {
2519                         hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2520                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2521                                 if (bnx2x_q_stats_arr[j].size == 0) {
2522                                         /* skip this counter */
2523                                         buf[k + j] = 0;
2524                                         continue;
2525                                 }
2526                                 offset = (hw_stats +
2527                                           bnx2x_q_stats_arr[j].offset);
2528                                 if (bnx2x_q_stats_arr[j].size == 4) {
2529                                         /* 4-byte counter */
2530                                         buf[k + j] = (u64) *offset;
2531                                         continue;
2532                                 }
2533                                 /* 8-byte counter */
2534                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2535                         }
2536                         k += BNX2X_NUM_Q_STATS;
2537                 }
2538         }
2539
2540         hw_stats = (u32 *)&bp->eth_stats;
2541         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2542                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2543                         continue;
2544                 if (bnx2x_stats_arr[i].size == 0) {
2545                         /* skip this counter */
2546                         buf[k + j] = 0;
2547                         j++;
2548                         continue;
2549                 }
2550                 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2551                 if (bnx2x_stats_arr[i].size == 4) {
2552                         /* 4-byte counter */
2553                         buf[k + j] = (u64) *offset;
2554                         j++;
2555                         continue;
2556                 }
2557                 /* 8-byte counter */
2558                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2559                 j++;
2560         }
2561 }
2562
2563 static int bnx2x_set_phys_id(struct net_device *dev,
2564                              enum ethtool_phys_id_state state)
2565 {
2566         struct bnx2x *bp = netdev_priv(dev);
2567
2568         if (!netif_running(dev)) {
2569                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2570                    "cannot access eeprom when the interface is down\n");
2571                 return -EAGAIN;
2572         }
2573
2574         if (!bp->port.pmf) {
2575                 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
2576                 return -EOPNOTSUPP;
2577         }
2578
2579         switch (state) {
2580         case ETHTOOL_ID_ACTIVE:
2581                 return 1;       /* cycle on/off once per second */
2582
2583         case ETHTOOL_ID_ON:
2584                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2585                               LED_MODE_ON, SPEED_1000);
2586                 break;
2587
2588         case ETHTOOL_ID_OFF:
2589                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2590                               LED_MODE_FRONT_PANEL_OFF, 0);
2591
2592                 break;
2593
2594         case ETHTOOL_ID_INACTIVE:
2595                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2596                               LED_MODE_OPER,
2597                               bp->link_vars.line_speed);
2598         }
2599
2600         return 0;
2601 }
2602
2603 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2604                            u32 *rules __always_unused)
2605 {
2606         struct bnx2x *bp = netdev_priv(dev);
2607
2608         switch (info->cmd) {
2609         case ETHTOOL_GRXRINGS:
2610                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2611                 return 0;
2612
2613         default:
2614                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2615                 return -EOPNOTSUPP;
2616         }
2617 }
2618
2619 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
2620 {
2621         return T_ETH_INDIRECTION_TABLE_SIZE;
2622 }
2623
2624 static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
2625 {
2626         struct bnx2x *bp = netdev_priv(dev);
2627         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2628         size_t i;
2629
2630         /* Get the current configuration of the RSS indirection table */
2631         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2632
2633         /*
2634          * We can't use a memcpy() as an internal storage of an
2635          * indirection table is a u8 array while indir->ring_index
2636          * points to an array of u32.
2637          *
2638          * Indirection table contains the FW Client IDs, so we need to
2639          * align the returned table to the Client ID of the leading RSS
2640          * queue.
2641          */
2642         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
2643                 indir[i] = ind_table[i] - bp->fp->cl_id;
2644
2645         return 0;
2646 }
2647
2648 static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
2649 {
2650         struct bnx2x *bp = netdev_priv(dev);
2651         size_t i;
2652         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2653
2654         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2655                 /*
2656                  * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2657                  * as an internal storage of an indirection table is a u8 array
2658                  * while indir->ring_index points to an array of u32.
2659                  *
2660                  * Indirection table contains the FW Client IDs, so we need to
2661                  * align the received table to the Client ID of the leading RSS
2662                  * queue
2663                  */
2664                 ind_table[i] = indir[i] + bp->fp->cl_id;
2665         }
2666
2667         return bnx2x_config_rss_eth(bp, ind_table, false);
2668 }
2669
2670 static const struct ethtool_ops bnx2x_ethtool_ops = {
2671         .get_settings           = bnx2x_get_settings,
2672         .set_settings           = bnx2x_set_settings,
2673         .get_drvinfo            = bnx2x_get_drvinfo,
2674         .get_regs_len           = bnx2x_get_regs_len,
2675         .get_regs               = bnx2x_get_regs,
2676         .get_wol                = bnx2x_get_wol,
2677         .set_wol                = bnx2x_set_wol,
2678         .get_msglevel           = bnx2x_get_msglevel,
2679         .set_msglevel           = bnx2x_set_msglevel,
2680         .nway_reset             = bnx2x_nway_reset,
2681         .get_link               = bnx2x_get_link,
2682         .get_eeprom_len         = bnx2x_get_eeprom_len,
2683         .get_eeprom             = bnx2x_get_eeprom,
2684         .set_eeprom             = bnx2x_set_eeprom,
2685         .get_coalesce           = bnx2x_get_coalesce,
2686         .set_coalesce           = bnx2x_set_coalesce,
2687         .get_ringparam          = bnx2x_get_ringparam,
2688         .set_ringparam          = bnx2x_set_ringparam,
2689         .get_pauseparam         = bnx2x_get_pauseparam,
2690         .set_pauseparam         = bnx2x_set_pauseparam,
2691         .self_test              = bnx2x_self_test,
2692         .get_sset_count         = bnx2x_get_sset_count,
2693         .get_strings            = bnx2x_get_strings,
2694         .set_phys_id            = bnx2x_set_phys_id,
2695         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
2696         .get_rxnfc              = bnx2x_get_rxnfc,
2697         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
2698         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
2699         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
2700         .get_eee                = bnx2x_get_eee,
2701         .set_eee                = bnx2x_set_eee,
2702 };
2703
2704 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2705 {
2706         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2707 }