1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/ethtool.h>
21 #include <linux/netdevice.h>
22 #include <linux/types.h>
23 #include <linux/sched.h>
24 #include <linux/crc32.h>
26 #include "bnx2x_cmn.h"
27 #include "bnx2x_dump.h"
28 #include "bnx2x_init.h"
30 /* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
34 #define MAX_QUEUE_NAME_LEN 4
38 char string[ETH_GSTRING_LEN];
39 } bnx2x_q_stats_arr[] = {
40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
67 4, "[%s]: driver_filtered_tx_pkt" }
70 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
76 #define STATS_FLAGS_PORT 1
77 #define STATS_FLAGS_FUNC 2
78 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
79 char string[ETH_GSTRING_LEN];
80 } bnx2x_stats_arr[] = {
81 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_bytes" },
83 { STATS_OFFSET32(error_bytes_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
85 { STATS_OFFSET32(total_unicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
87 { STATS_OFFSET32(total_multicast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
89 { STATS_OFFSET32(total_broadcast_packets_received_hi),
90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
92 8, STATS_FLAGS_PORT, "rx_crc_errors" },
93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
94 8, STATS_FLAGS_PORT, "rx_align_errors" },
95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
98 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
99 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
100 8, STATS_FLAGS_PORT, "rx_fragments" },
101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
102 8, STATS_FLAGS_PORT, "rx_jabbers" },
103 { STATS_OFFSET32(no_buff_discard_hi),
104 8, STATS_FLAGS_BOTH, "rx_discards" },
105 { STATS_OFFSET32(mac_filter_discard),
106 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
107 { STATS_OFFSET32(mf_tag_discard),
108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
109 { STATS_OFFSET32(pfc_frames_received_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_received" },
111 { STATS_OFFSET32(pfc_frames_sent_hi),
112 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
113 { STATS_OFFSET32(brb_drop_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_discard" },
115 { STATS_OFFSET32(brb_truncate_hi),
116 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
117 { STATS_OFFSET32(pause_frames_received_hi),
118 8, STATS_FLAGS_PORT, "rx_pause_frames" },
119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
121 { STATS_OFFSET32(nig_timer_max),
122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
123 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
125 { STATS_OFFSET32(rx_skb_alloc_failed),
126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
127 { STATS_OFFSET32(hw_csum_err),
128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, STATS_FLAGS_PORT, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, STATS_FLAGS_PORT, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, STATS_FLAGS_PORT, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, STATS_FLAGS_PORT, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
171 8, STATS_FLAGS_PORT, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
177 8, STATS_FLAGS_FUNC, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, STATS_FLAGS_FUNC, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
184 { STATS_OFFSET32(eee_tx_lpi),
185 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
188 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
190 static int bnx2x_get_port_type(struct bnx2x *bp)
193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 switch (bp->link_params.phy[phy_idx].media_type) {
195 case ETH_PHY_SFPP_10G_FIBER:
196 case ETH_PHY_SFP_1G_FIBER:
197 case ETH_PHY_XFP_FIBER:
200 port_type = PORT_FIBRE;
202 case ETH_PHY_DA_TWINAX:
208 case ETH_PHY_NOT_PRESENT:
209 port_type = PORT_NONE;
211 case ETH_PHY_UNSPECIFIED:
213 port_type = PORT_OTHER;
219 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
221 struct bnx2x *bp = netdev_priv(dev);
222 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
224 /* Dual Media boards present all available port types */
225 cmd->supported = bp->port.supported[cfg_idx] |
226 (bp->port.supported[cfg_idx ^ 1] &
227 (SUPPORTED_TP | SUPPORTED_FIBRE));
228 cmd->advertising = bp->port.advertising[cfg_idx];
229 if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
230 ETH_PHY_SFP_1G_FIBER) {
231 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
232 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
235 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
236 !(bp->flags & MF_FUNC_DIS)) {
237 cmd->duplex = bp->link_vars.duplex;
239 if (IS_MF(bp) && !BP_NOMCP(bp))
240 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
242 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
244 cmd->duplex = DUPLEX_UNKNOWN;
245 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
248 cmd->port = bnx2x_get_port_type(bp);
250 cmd->phy_address = bp->mdio.prtad;
251 cmd->transceiver = XCVR_INTERNAL;
253 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
254 cmd->autoneg = AUTONEG_ENABLE;
256 cmd->autoneg = AUTONEG_DISABLE;
258 /* Publish LP advertised speeds and FC */
259 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
260 u32 status = bp->link_vars.link_status;
262 cmd->lp_advertising |= ADVERTISED_Autoneg;
263 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
264 cmd->lp_advertising |= ADVERTISED_Pause;
265 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
266 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
268 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
269 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
270 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
271 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
272 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
273 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
274 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
275 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
276 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
277 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
278 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
279 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
280 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
281 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
282 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
283 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
284 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
285 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
291 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
292 " supported 0x%x advertising 0x%x speed %u\n"
293 " duplex %d port %d phy_address %d transceiver %d\n"
294 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
295 cmd->cmd, cmd->supported, cmd->advertising,
296 ethtool_cmd_speed(cmd),
297 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
298 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
303 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
305 struct bnx2x *bp = netdev_priv(dev);
306 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
312 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
313 " supported 0x%x advertising 0x%x speed %u\n"
314 " duplex %d port %d phy_address %d transceiver %d\n"
315 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
316 cmd->cmd, cmd->supported, cmd->advertising,
317 ethtool_cmd_speed(cmd),
318 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
319 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
321 speed = ethtool_cmd_speed(cmd);
323 /* If recieved a request for an unknown duplex, assume full*/
324 if (cmd->duplex == DUPLEX_UNKNOWN)
325 cmd->duplex = DUPLEX_FULL;
329 u32 line_speed = bp->link_vars.line_speed;
331 /* use 10G if no link detected */
335 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
336 DP(BNX2X_MSG_ETHTOOL,
337 "To set speed BC %X or higher is required, please upgrade BC\n",
338 REQ_BC_VER_4_SET_MF_BW);
342 part = (speed * 100) / line_speed;
344 if (line_speed < speed || !part) {
345 DP(BNX2X_MSG_ETHTOOL,
346 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
350 if (bp->state != BNX2X_STATE_OPEN)
351 /* store value for following "load" */
352 bp->pending_max = part;
354 bnx2x_update_max_mf_config(bp, part);
359 cfg_idx = bnx2x_get_link_cfg_idx(bp);
360 old_multi_phy_config = bp->link_params.multi_phy_config;
363 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
364 break; /* no port change */
366 if (!(bp->port.supported[0] & SUPPORTED_TP ||
367 bp->port.supported[1] & SUPPORTED_TP)) {
368 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
371 bp->link_params.multi_phy_config &=
372 ~PORT_HW_CFG_PHY_SELECTION_MASK;
373 if (bp->link_params.multi_phy_config &
374 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
375 bp->link_params.multi_phy_config |=
376 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
378 bp->link_params.multi_phy_config |=
379 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
383 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
384 break; /* no port change */
386 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
387 bp->port.supported[1] & SUPPORTED_FIBRE)) {
388 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
391 bp->link_params.multi_phy_config &=
392 ~PORT_HW_CFG_PHY_SELECTION_MASK;
393 if (bp->link_params.multi_phy_config &
394 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
395 bp->link_params.multi_phy_config |=
396 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
398 bp->link_params.multi_phy_config |=
399 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
402 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
405 /* Save new config in case command complete successfully */
406 new_multi_phy_config = bp->link_params.multi_phy_config;
407 /* Get the new cfg_idx */
408 cfg_idx = bnx2x_get_link_cfg_idx(bp);
409 /* Restore old config in case command failed */
410 bp->link_params.multi_phy_config = old_multi_phy_config;
411 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
413 if (cmd->autoneg == AUTONEG_ENABLE) {
414 u32 an_supported_speed = bp->port.supported[cfg_idx];
415 if (bp->link_params.phy[EXT_PHY1].type ==
416 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
417 an_supported_speed |= (SUPPORTED_100baseT_Half |
418 SUPPORTED_100baseT_Full);
419 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
420 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
424 /* advertise the requested speed and duplex if supported */
425 if (cmd->advertising & ~an_supported_speed) {
426 DP(BNX2X_MSG_ETHTOOL,
427 "Advertisement parameters are not supported\n");
431 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
432 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
433 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
435 if (cmd->advertising) {
437 bp->link_params.speed_cap_mask[cfg_idx] = 0;
438 if (cmd->advertising & ADVERTISED_10baseT_Half) {
439 bp->link_params.speed_cap_mask[cfg_idx] |=
440 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
442 if (cmd->advertising & ADVERTISED_10baseT_Full)
443 bp->link_params.speed_cap_mask[cfg_idx] |=
444 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
446 if (cmd->advertising & ADVERTISED_100baseT_Full)
447 bp->link_params.speed_cap_mask[cfg_idx] |=
448 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
450 if (cmd->advertising & ADVERTISED_100baseT_Half) {
451 bp->link_params.speed_cap_mask[cfg_idx] |=
452 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
454 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
455 bp->link_params.speed_cap_mask[cfg_idx] |=
456 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
458 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
459 ADVERTISED_1000baseKX_Full))
460 bp->link_params.speed_cap_mask[cfg_idx] |=
461 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
463 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
464 ADVERTISED_10000baseKX4_Full |
465 ADVERTISED_10000baseKR_Full))
466 bp->link_params.speed_cap_mask[cfg_idx] |=
467 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
469 if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
470 bp->link_params.speed_cap_mask[cfg_idx] |=
471 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
473 } else { /* forced speed */
474 /* advertise the requested speed and duplex if supported */
477 if (cmd->duplex == DUPLEX_FULL) {
478 if (!(bp->port.supported[cfg_idx] &
479 SUPPORTED_10baseT_Full)) {
480 DP(BNX2X_MSG_ETHTOOL,
481 "10M full not supported\n");
485 advertising = (ADVERTISED_10baseT_Full |
488 if (!(bp->port.supported[cfg_idx] &
489 SUPPORTED_10baseT_Half)) {
490 DP(BNX2X_MSG_ETHTOOL,
491 "10M half not supported\n");
495 advertising = (ADVERTISED_10baseT_Half |
501 if (cmd->duplex == DUPLEX_FULL) {
502 if (!(bp->port.supported[cfg_idx] &
503 SUPPORTED_100baseT_Full)) {
504 DP(BNX2X_MSG_ETHTOOL,
505 "100M full not supported\n");
509 advertising = (ADVERTISED_100baseT_Full |
512 if (!(bp->port.supported[cfg_idx] &
513 SUPPORTED_100baseT_Half)) {
514 DP(BNX2X_MSG_ETHTOOL,
515 "100M half not supported\n");
519 advertising = (ADVERTISED_100baseT_Half |
525 if (cmd->duplex != DUPLEX_FULL) {
526 DP(BNX2X_MSG_ETHTOOL,
527 "1G half not supported\n");
531 if (!(bp->port.supported[cfg_idx] &
532 SUPPORTED_1000baseT_Full)) {
533 DP(BNX2X_MSG_ETHTOOL,
534 "1G full not supported\n");
538 advertising = (ADVERTISED_1000baseT_Full |
543 if (cmd->duplex != DUPLEX_FULL) {
544 DP(BNX2X_MSG_ETHTOOL,
545 "2.5G half not supported\n");
549 if (!(bp->port.supported[cfg_idx]
550 & SUPPORTED_2500baseX_Full)) {
551 DP(BNX2X_MSG_ETHTOOL,
552 "2.5G full not supported\n");
556 advertising = (ADVERTISED_2500baseX_Full |
561 if (cmd->duplex != DUPLEX_FULL) {
562 DP(BNX2X_MSG_ETHTOOL,
563 "10G half not supported\n");
566 phy_idx = bnx2x_get_cur_phy_idx(bp);
567 if (!(bp->port.supported[cfg_idx]
568 & SUPPORTED_10000baseT_Full) ||
569 (bp->link_params.phy[phy_idx].media_type ==
570 ETH_PHY_SFP_1G_FIBER)) {
571 DP(BNX2X_MSG_ETHTOOL,
572 "10G full not supported\n");
576 advertising = (ADVERTISED_10000baseT_Full |
581 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
585 bp->link_params.req_line_speed[cfg_idx] = speed;
586 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
587 bp->port.advertising[cfg_idx] = advertising;
590 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
591 " req_duplex %d advertising 0x%x\n",
592 bp->link_params.req_line_speed[cfg_idx],
593 bp->link_params.req_duplex[cfg_idx],
594 bp->port.advertising[cfg_idx]);
597 bp->link_params.multi_phy_config = new_multi_phy_config;
598 if (netif_running(dev)) {
599 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
606 #define DUMP_ALL_PRESETS 0x1FFF
607 #define DUMP_MAX_PRESETS 13
609 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
612 return dump_num_registers[0][preset-1];
613 else if (CHIP_IS_E1H(bp))
614 return dump_num_registers[1][preset-1];
615 else if (CHIP_IS_E2(bp))
616 return dump_num_registers[2][preset-1];
617 else if (CHIP_IS_E3A0(bp))
618 return dump_num_registers[3][preset-1];
619 else if (CHIP_IS_E3B0(bp))
620 return dump_num_registers[4][preset-1];
625 static int __bnx2x_get_regs_len(struct bnx2x *bp)
630 /* Calculate the total preset regs length */
631 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
632 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
637 static int bnx2x_get_regs_len(struct net_device *dev)
639 struct bnx2x *bp = netdev_priv(dev);
642 regdump_len = __bnx2x_get_regs_len(bp);
644 regdump_len += sizeof(struct dump_header);
649 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
650 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
651 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
652 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
653 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
655 #define IS_REG_IN_PRESET(presets, idx) \
656 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
658 /******* Paged registers info selectors ********/
659 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
663 else if (CHIP_IS_E3(bp))
669 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
672 return PAGE_MODE_VALUES_E2;
673 else if (CHIP_IS_E3(bp))
674 return PAGE_MODE_VALUES_E3;
679 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
682 return page_write_regs_e2;
683 else if (CHIP_IS_E3(bp))
684 return page_write_regs_e3;
689 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
692 return PAGE_WRITE_REGS_E2;
693 else if (CHIP_IS_E3(bp))
694 return PAGE_WRITE_REGS_E3;
699 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
702 return page_read_regs_e2;
703 else if (CHIP_IS_E3(bp))
704 return page_read_regs_e3;
709 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
712 return PAGE_READ_REGS_E2;
713 else if (CHIP_IS_E3(bp))
714 return PAGE_READ_REGS_E3;
719 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
720 const struct reg_addr *reg_info)
723 return IS_E1_REG(reg_info->chips);
724 else if (CHIP_IS_E1H(bp))
725 return IS_E1H_REG(reg_info->chips);
726 else if (CHIP_IS_E2(bp))
727 return IS_E2_REG(reg_info->chips);
728 else if (CHIP_IS_E3A0(bp))
729 return IS_E3A0_REG(reg_info->chips);
730 else if (CHIP_IS_E3B0(bp))
731 return IS_E3B0_REG(reg_info->chips);
737 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
738 const struct wreg_addr *wreg_info)
741 return IS_E1_REG(wreg_info->chips);
742 else if (CHIP_IS_E1H(bp))
743 return IS_E1H_REG(wreg_info->chips);
744 else if (CHIP_IS_E2(bp))
745 return IS_E2_REG(wreg_info->chips);
746 else if (CHIP_IS_E3A0(bp))
747 return IS_E3A0_REG(wreg_info->chips);
748 else if (CHIP_IS_E3B0(bp))
749 return IS_E3B0_REG(wreg_info->chips);
755 * bnx2x_read_pages_regs - read "paged" registers
760 * Reads "paged" memories: memories that may only be read by first writing to a
761 * specific address ("write address") and then reading from a specific address
762 * ("read address"). There may be more than one write address per "page" and
763 * more than one read address per write address.
765 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
769 /* addresses of the paged registers */
770 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
771 /* number of paged registers */
772 int num_pages = __bnx2x_get_page_reg_num(bp);
773 /* write addresses */
774 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
775 /* number of write addresses */
776 int write_num = __bnx2x_get_page_write_num(bp);
777 /* read addresses info */
778 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
779 /* number of read addresses */
780 int read_num = __bnx2x_get_page_read_num(bp);
783 for (i = 0; i < num_pages; i++) {
784 for (j = 0; j < write_num; j++) {
785 REG_WR(bp, write_addr[j], page_addr[i]);
787 for (k = 0; k < read_num; k++) {
788 if (IS_REG_IN_PRESET(read_addr[k].presets,
790 size = read_addr[k].size;
791 for (n = 0; n < size; n++) {
792 addr = read_addr[k].addr + n*4;
793 *p++ = REG_RD(bp, addr);
801 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
804 const struct wreg_addr *wreg_addr_p = NULL;
807 wreg_addr_p = &wreg_addr_e1;
808 else if (CHIP_IS_E1H(bp))
809 wreg_addr_p = &wreg_addr_e1h;
810 else if (CHIP_IS_E2(bp))
811 wreg_addr_p = &wreg_addr_e2;
812 else if (CHIP_IS_E3A0(bp))
813 wreg_addr_p = &wreg_addr_e3;
814 else if (CHIP_IS_E3B0(bp))
815 wreg_addr_p = &wreg_addr_e3b0;
817 /* Read the idle_chk registers */
818 for (i = 0; i < IDLE_REGS_COUNT; i++) {
819 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
820 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
821 for (j = 0; j < idle_reg_addrs[i].size; j++)
822 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
826 /* Read the regular registers */
827 for (i = 0; i < REGS_COUNT; i++) {
828 if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) &&
829 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
830 for (j = 0; j < reg_addrs[i].size; j++)
831 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
835 /* Read the CAM registers */
836 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
837 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
838 for (i = 0; i < wreg_addr_p->size; i++) {
839 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
841 /* In case of wreg_addr register, read additional
842 registers from read_regs array
844 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
845 addr = *(wreg_addr_p->read_regs);
846 *p++ = REG_RD(bp, addr + j*4);
851 /* Paged registers are supported in E2 & E3 only */
852 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
853 /* Read "paged" registes */
854 bnx2x_read_pages_regs(bp, p, preset);
860 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
864 /* Read all registers, by reading all preset registers */
865 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
866 /* Skip presets with IOR */
867 if ((preset_idx == 2) ||
872 __bnx2x_get_preset_regs(bp, p, preset_idx);
873 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
877 static void bnx2x_get_regs(struct net_device *dev,
878 struct ethtool_regs *regs, void *_p)
881 struct bnx2x *bp = netdev_priv(dev);
882 struct dump_header dump_hdr = {0};
885 memset(p, 0, regs->len);
887 if (!netif_running(bp->dev))
890 /* Disable parity attentions as long as following dump may
891 * cause false alarms by reading never written registers. We
892 * will re-enable parity attentions right after the dump.
895 /* Disable parity on path 0 */
896 bnx2x_pretend_func(bp, 0);
897 bnx2x_disable_blocks_parity(bp);
899 /* Disable parity on path 1 */
900 bnx2x_pretend_func(bp, 1);
901 bnx2x_disable_blocks_parity(bp);
903 /* Return to current function */
904 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
906 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
907 dump_hdr.preset = DUMP_ALL_PRESETS;
908 dump_hdr.version = BNX2X_DUMP_VERSION;
910 /* dump_meta_data presents OR of CHIP and PATH. */
911 if (CHIP_IS_E1(bp)) {
912 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
913 } else if (CHIP_IS_E1H(bp)) {
914 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
915 } else if (CHIP_IS_E2(bp)) {
916 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
917 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
918 } else if (CHIP_IS_E3A0(bp)) {
919 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
920 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
921 } else if (CHIP_IS_E3B0(bp)) {
922 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
923 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
926 memcpy(p, &dump_hdr, sizeof(struct dump_header));
927 p += dump_hdr.header_size + 1;
929 /* Actually read the registers */
930 __bnx2x_get_regs(bp, p);
932 /* Re-enable parity attentions on path 0 */
933 bnx2x_pretend_func(bp, 0);
934 bnx2x_clear_blocks_parity(bp);
935 bnx2x_enable_blocks_parity(bp);
937 /* Re-enable parity attentions on path 1 */
938 bnx2x_pretend_func(bp, 1);
939 bnx2x_clear_blocks_parity(bp);
940 bnx2x_enable_blocks_parity(bp);
942 /* Return to current function */
943 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
946 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
948 struct bnx2x *bp = netdev_priv(dev);
951 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
953 regdump_len += sizeof(struct dump_header);
958 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
960 struct bnx2x *bp = netdev_priv(dev);
962 /* Use the ethtool_dump "flag" field as the dump preset index */
963 bp->dump_preset_idx = val->flag;
967 static int bnx2x_get_dump_flag(struct net_device *dev,
968 struct ethtool_dump *dump)
970 struct bnx2x *bp = netdev_priv(dev);
972 /* Calculate the requested preset idx length */
973 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
974 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
975 bp->dump_preset_idx, dump->len);
977 dump->flag = ETHTOOL_GET_DUMP_DATA;
981 static int bnx2x_get_dump_data(struct net_device *dev,
982 struct ethtool_dump *dump,
986 struct bnx2x *bp = netdev_priv(dev);
987 struct dump_header dump_hdr = {0};
989 memset(p, 0, dump->len);
991 /* Disable parity attentions as long as following dump may
992 * cause false alarms by reading never written registers. We
993 * will re-enable parity attentions right after the dump.
996 /* Disable parity on path 0 */
997 bnx2x_pretend_func(bp, 0);
998 bnx2x_disable_blocks_parity(bp);
1000 /* Disable parity on path 1 */
1001 bnx2x_pretend_func(bp, 1);
1002 bnx2x_disable_blocks_parity(bp);
1004 /* Return to current function */
1005 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1007 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1008 dump_hdr.preset = bp->dump_preset_idx;
1009 dump_hdr.version = BNX2X_DUMP_VERSION;
1011 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1013 /* dump_meta_data presents OR of CHIP and PATH. */
1014 if (CHIP_IS_E1(bp)) {
1015 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1016 } else if (CHIP_IS_E1H(bp)) {
1017 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1018 } else if (CHIP_IS_E2(bp)) {
1019 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1020 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1021 } else if (CHIP_IS_E3A0(bp)) {
1022 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1023 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1024 } else if (CHIP_IS_E3B0(bp)) {
1025 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1026 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1029 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1030 p += dump_hdr.header_size + 1;
1032 /* Actually read the registers */
1033 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1035 /* Re-enable parity attentions on path 0 */
1036 bnx2x_pretend_func(bp, 0);
1037 bnx2x_clear_blocks_parity(bp);
1038 bnx2x_enable_blocks_parity(bp);
1040 /* Re-enable parity attentions on path 1 */
1041 bnx2x_pretend_func(bp, 1);
1042 bnx2x_clear_blocks_parity(bp);
1043 bnx2x_enable_blocks_parity(bp);
1045 /* Return to current function */
1046 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1051 static void bnx2x_get_drvinfo(struct net_device *dev,
1052 struct ethtool_drvinfo *info)
1054 struct bnx2x *bp = netdev_priv(dev);
1056 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1057 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1059 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1061 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1062 info->n_stats = BNX2X_NUM_STATS;
1063 info->testinfo_len = BNX2X_NUM_TESTS(bp);
1064 info->eedump_len = bp->common.flash_size;
1065 info->regdump_len = bnx2x_get_regs_len(dev);
1068 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1070 struct bnx2x *bp = netdev_priv(dev);
1072 if (bp->flags & NO_WOL_FLAG) {
1076 wol->supported = WAKE_MAGIC;
1078 wol->wolopts = WAKE_MAGIC;
1082 memset(&wol->sopass, 0, sizeof(wol->sopass));
1085 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1087 struct bnx2x *bp = netdev_priv(dev);
1089 if (wol->wolopts & ~WAKE_MAGIC) {
1090 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1094 if (wol->wolopts & WAKE_MAGIC) {
1095 if (bp->flags & NO_WOL_FLAG) {
1096 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1106 static u32 bnx2x_get_msglevel(struct net_device *dev)
1108 struct bnx2x *bp = netdev_priv(dev);
1110 return bp->msg_enable;
1113 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1115 struct bnx2x *bp = netdev_priv(dev);
1117 if (capable(CAP_NET_ADMIN)) {
1118 /* dump MCP trace */
1119 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1120 bnx2x_fw_dump_lvl(bp, KERN_INFO);
1121 bp->msg_enable = level;
1125 static int bnx2x_nway_reset(struct net_device *dev)
1127 struct bnx2x *bp = netdev_priv(dev);
1132 if (netif_running(dev)) {
1133 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1134 bnx2x_force_link_reset(bp);
1141 static u32 bnx2x_get_link(struct net_device *dev)
1143 struct bnx2x *bp = netdev_priv(dev);
1145 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1148 return bp->link_vars.link_up;
1151 static int bnx2x_get_eeprom_len(struct net_device *dev)
1153 struct bnx2x *bp = netdev_priv(dev);
1155 return bp->common.flash_size;
1158 /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
1159 * we done things the other way around, if two pfs from the same port would
1160 * attempt to access nvram at the same time, we could run into a scenario such
1162 * pf A takes the port lock.
1163 * pf B succeeds in taking the same lock since they are from the same port.
1164 * pf A takes the per pf misc lock. Performs eeprom access.
1165 * pf A finishes. Unlocks the per pf misc lock.
1166 * Pf B takes the lock and proceeds to perform it's own access.
1167 * pf A unlocks the per port lock, while pf B is still working (!).
1168 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1169 * access corrupted by pf B)
1171 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1173 int port = BP_PORT(bp);
1177 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1178 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1180 /* adjust timeout for emulation/FPGA */
1181 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1182 if (CHIP_REV_IS_SLOW(bp))
1185 /* request access to nvram interface */
1186 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1187 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1189 for (i = 0; i < count*10; i++) {
1190 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1191 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1197 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1198 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1199 "cannot get access to nvram interface\n");
1206 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1208 int port = BP_PORT(bp);
1212 /* adjust timeout for emulation/FPGA */
1213 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1214 if (CHIP_REV_IS_SLOW(bp))
1217 /* relinquish nvram interface */
1218 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1219 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1221 for (i = 0; i < count*10; i++) {
1222 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1223 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1229 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1230 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1231 "cannot free access to nvram interface\n");
1235 /* release HW lock: protect against other PFs in PF Direct Assignment */
1236 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1240 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1244 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1246 /* enable both bits, even on read */
1247 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1248 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1249 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1252 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1256 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1258 /* disable both bits, even after read */
1259 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1260 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1261 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1264 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1270 /* build the command word */
1271 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1273 /* need to clear DONE bit separately */
1274 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1276 /* address of the NVRAM to read from */
1277 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1278 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1280 /* issue a read command */
1281 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1283 /* adjust timeout for emulation/FPGA */
1284 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1285 if (CHIP_REV_IS_SLOW(bp))
1288 /* wait for completion */
1291 for (i = 0; i < count; i++) {
1293 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1295 if (val & MCPR_NVM_COMMAND_DONE) {
1296 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1297 /* we read nvram data in cpu order
1298 * but ethtool sees it as an array of bytes
1299 * converting to big-endian will do the work
1301 *ret_val = cpu_to_be32(val);
1307 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1308 "nvram read timeout expired\n");
1312 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1319 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1320 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1321 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1326 if (offset + buf_size > bp->common.flash_size) {
1327 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1328 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1329 offset, buf_size, bp->common.flash_size);
1333 /* request access to nvram interface */
1334 rc = bnx2x_acquire_nvram_lock(bp);
1338 /* enable access to nvram interface */
1339 bnx2x_enable_nvram_access(bp);
1341 /* read the first word(s) */
1342 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1343 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1344 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1345 memcpy(ret_buf, &val, 4);
1347 /* advance to the next dword */
1348 offset += sizeof(u32);
1349 ret_buf += sizeof(u32);
1350 buf_size -= sizeof(u32);
1355 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1356 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1357 memcpy(ret_buf, &val, 4);
1360 /* disable access to nvram interface */
1361 bnx2x_disable_nvram_access(bp);
1362 bnx2x_release_nvram_lock(bp);
1367 static int bnx2x_get_eeprom(struct net_device *dev,
1368 struct ethtool_eeprom *eeprom, u8 *eebuf)
1370 struct bnx2x *bp = netdev_priv(dev);
1373 if (!netif_running(dev)) {
1374 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1375 "cannot access eeprom when the interface is down\n");
1379 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1380 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1381 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1382 eeprom->len, eeprom->len);
1384 /* parameters already validated in ethtool_get_eeprom */
1386 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1391 static int bnx2x_get_module_eeprom(struct net_device *dev,
1392 struct ethtool_eeprom *ee,
1395 struct bnx2x *bp = netdev_priv(dev);
1396 int rc = 0, phy_idx;
1397 u8 *user_data = data;
1398 int remaining_len = ee->len, xfer_size;
1399 unsigned int page_off = ee->offset;
1401 if (!netif_running(dev)) {
1402 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1403 "cannot access eeprom when the interface is down\n");
1407 phy_idx = bnx2x_get_cur_phy_idx(bp);
1408 bnx2x_acquire_phy_lock(bp);
1409 while (!rc && remaining_len > 0) {
1410 xfer_size = (remaining_len > SFP_EEPROM_PAGE_SIZE) ?
1411 SFP_EEPROM_PAGE_SIZE : remaining_len;
1412 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1417 remaining_len -= xfer_size;
1418 user_data += xfer_size;
1419 page_off += xfer_size;
1422 bnx2x_release_phy_lock(bp);
1426 static int bnx2x_get_module_info(struct net_device *dev,
1427 struct ethtool_modinfo *modinfo)
1429 struct bnx2x *bp = netdev_priv(dev);
1431 if (!netif_running(dev)) {
1432 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1433 "cannot access eeprom when the interface is down\n");
1437 phy_idx = bnx2x_get_cur_phy_idx(bp);
1438 switch (bp->link_params.phy[phy_idx].media_type) {
1439 case ETH_PHY_SFPP_10G_FIBER:
1440 case ETH_PHY_SFP_1G_FIBER:
1441 case ETH_PHY_DA_TWINAX:
1442 modinfo->type = ETH_MODULE_SFF_8079;
1443 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1450 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1455 /* build the command word */
1456 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1458 /* need to clear DONE bit separately */
1459 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1461 /* write the data */
1462 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1464 /* address of the NVRAM to write to */
1465 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1466 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1468 /* issue the write command */
1469 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1471 /* adjust timeout for emulation/FPGA */
1472 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1473 if (CHIP_REV_IS_SLOW(bp))
1476 /* wait for completion */
1478 for (i = 0; i < count; i++) {
1480 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1481 if (val & MCPR_NVM_COMMAND_DONE) {
1488 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1489 "nvram write timeout expired\n");
1493 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1495 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1503 if (offset + buf_size > bp->common.flash_size) {
1504 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1505 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1506 offset, buf_size, bp->common.flash_size);
1510 /* request access to nvram interface */
1511 rc = bnx2x_acquire_nvram_lock(bp);
1515 /* enable access to nvram interface */
1516 bnx2x_enable_nvram_access(bp);
1518 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1519 align_offset = (offset & ~0x03);
1520 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1523 val &= ~(0xff << BYTE_OFFSET(offset));
1524 val |= (*data_buf << BYTE_OFFSET(offset));
1526 /* nvram data is returned as an array of bytes
1527 * convert it back to cpu order
1529 val = be32_to_cpu(val);
1531 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1535 /* disable access to nvram interface */
1536 bnx2x_disable_nvram_access(bp);
1537 bnx2x_release_nvram_lock(bp);
1542 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1550 if (buf_size == 1) /* ethtool */
1551 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1553 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1554 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1555 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1560 if (offset + buf_size > bp->common.flash_size) {
1561 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1562 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1563 offset, buf_size, bp->common.flash_size);
1567 /* request access to nvram interface */
1568 rc = bnx2x_acquire_nvram_lock(bp);
1572 /* enable access to nvram interface */
1573 bnx2x_enable_nvram_access(bp);
1576 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1577 while ((written_so_far < buf_size) && (rc == 0)) {
1578 if (written_so_far == (buf_size - sizeof(u32)))
1579 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1580 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1581 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1582 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1583 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1585 memcpy(&val, data_buf, 4);
1587 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1589 /* advance to the next dword */
1590 offset += sizeof(u32);
1591 data_buf += sizeof(u32);
1592 written_so_far += sizeof(u32);
1596 /* disable access to nvram interface */
1597 bnx2x_disable_nvram_access(bp);
1598 bnx2x_release_nvram_lock(bp);
1603 static int bnx2x_set_eeprom(struct net_device *dev,
1604 struct ethtool_eeprom *eeprom, u8 *eebuf)
1606 struct bnx2x *bp = netdev_priv(dev);
1607 int port = BP_PORT(bp);
1610 if (!netif_running(dev)) {
1611 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1612 "cannot access eeprom when the interface is down\n");
1616 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1617 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1618 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1619 eeprom->len, eeprom->len);
1621 /* parameters already validated in ethtool_set_eeprom */
1623 /* PHY eeprom can be accessed only by the PMF */
1624 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1626 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1627 "wrong magic or interface is not pmf\n");
1633 dev_info.port_hw_config[port].external_phy_config);
1635 if (eeprom->magic == 0x50485950) {
1636 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1637 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1639 bnx2x_acquire_phy_lock(bp);
1640 rc |= bnx2x_link_reset(&bp->link_params,
1642 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1643 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1644 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1645 MISC_REGISTERS_GPIO_HIGH, port);
1646 bnx2x_release_phy_lock(bp);
1647 bnx2x_link_report(bp);
1649 } else if (eeprom->magic == 0x50485952) {
1650 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1651 if (bp->state == BNX2X_STATE_OPEN) {
1652 bnx2x_acquire_phy_lock(bp);
1653 rc |= bnx2x_link_reset(&bp->link_params,
1656 rc |= bnx2x_phy_init(&bp->link_params,
1658 bnx2x_release_phy_lock(bp);
1659 bnx2x_calc_fc_adv(bp);
1661 } else if (eeprom->magic == 0x53985943) {
1662 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1663 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1664 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1666 /* DSP Remove Download Mode */
1667 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1668 MISC_REGISTERS_GPIO_LOW, port);
1670 bnx2x_acquire_phy_lock(bp);
1672 bnx2x_sfx7101_sp_sw_reset(bp,
1673 &bp->link_params.phy[EXT_PHY1]);
1675 /* wait 0.5 sec to allow it to run */
1677 bnx2x_ext_phy_hw_reset(bp, port);
1679 bnx2x_release_phy_lock(bp);
1682 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1687 static int bnx2x_get_coalesce(struct net_device *dev,
1688 struct ethtool_coalesce *coal)
1690 struct bnx2x *bp = netdev_priv(dev);
1692 memset(coal, 0, sizeof(struct ethtool_coalesce));
1694 coal->rx_coalesce_usecs = bp->rx_ticks;
1695 coal->tx_coalesce_usecs = bp->tx_ticks;
1700 static int bnx2x_set_coalesce(struct net_device *dev,
1701 struct ethtool_coalesce *coal)
1703 struct bnx2x *bp = netdev_priv(dev);
1705 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1706 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1707 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1709 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1710 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1711 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1713 if (netif_running(dev))
1714 bnx2x_update_coalesce(bp);
1719 static void bnx2x_get_ringparam(struct net_device *dev,
1720 struct ethtool_ringparam *ering)
1722 struct bnx2x *bp = netdev_priv(dev);
1724 ering->rx_max_pending = MAX_RX_AVAIL;
1726 if (bp->rx_ring_size)
1727 ering->rx_pending = bp->rx_ring_size;
1729 ering->rx_pending = MAX_RX_AVAIL;
1731 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1732 ering->tx_pending = bp->tx_ring_size;
1735 static int bnx2x_set_ringparam(struct net_device *dev,
1736 struct ethtool_ringparam *ering)
1738 struct bnx2x *bp = netdev_priv(dev);
1740 DP(BNX2X_MSG_ETHTOOL,
1741 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1742 ering->rx_pending, ering->tx_pending);
1744 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1745 DP(BNX2X_MSG_ETHTOOL,
1746 "Handling parity error recovery. Try again later\n");
1750 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1751 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1752 MIN_RX_SIZE_TPA)) ||
1753 (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
1754 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1755 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1759 bp->rx_ring_size = ering->rx_pending;
1760 bp->tx_ring_size = ering->tx_pending;
1762 return bnx2x_reload_if_running(dev);
1765 static void bnx2x_get_pauseparam(struct net_device *dev,
1766 struct ethtool_pauseparam *epause)
1768 struct bnx2x *bp = netdev_priv(dev);
1769 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1772 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1773 BNX2X_FLOW_CTRL_AUTO);
1775 if (!epause->autoneg)
1776 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1778 cfg_reg = bp->link_params.req_fc_auto_adv;
1780 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1781 BNX2X_FLOW_CTRL_RX);
1782 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1783 BNX2X_FLOW_CTRL_TX);
1785 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1786 " autoneg %d rx_pause %d tx_pause %d\n",
1787 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1790 static int bnx2x_set_pauseparam(struct net_device *dev,
1791 struct ethtool_pauseparam *epause)
1793 struct bnx2x *bp = netdev_priv(dev);
1794 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1798 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1799 " autoneg %d rx_pause %d tx_pause %d\n",
1800 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1802 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1804 if (epause->rx_pause)
1805 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1807 if (epause->tx_pause)
1808 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1810 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1811 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1813 if (epause->autoneg) {
1814 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1815 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1819 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1820 bp->link_params.req_flow_ctrl[cfg_idx] =
1821 BNX2X_FLOW_CTRL_AUTO;
1823 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_NONE;
1824 if (epause->rx_pause)
1825 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1827 if (epause->tx_pause)
1828 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1831 DP(BNX2X_MSG_ETHTOOL,
1832 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1834 if (netif_running(dev)) {
1835 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1842 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1843 "register_test (offline) ",
1844 "memory_test (offline) ",
1845 "int_loopback_test (offline)",
1846 "ext_loopback_test (offline)",
1847 "nvram_test (online) ",
1848 "interrupt_test (online) ",
1849 "link_test (online) "
1852 static u32 bnx2x_eee_to_adv(u32 eee_adv)
1856 if (eee_adv & SHMEM_EEE_100M_ADV)
1857 modes |= ADVERTISED_100baseT_Full;
1858 if (eee_adv & SHMEM_EEE_1G_ADV)
1859 modes |= ADVERTISED_1000baseT_Full;
1860 if (eee_adv & SHMEM_EEE_10G_ADV)
1861 modes |= ADVERTISED_10000baseT_Full;
1866 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1869 if (modes & ADVERTISED_100baseT_Full)
1870 eee_adv |= SHMEM_EEE_100M_ADV;
1871 if (modes & ADVERTISED_1000baseT_Full)
1872 eee_adv |= SHMEM_EEE_1G_ADV;
1873 if (modes & ADVERTISED_10000baseT_Full)
1874 eee_adv |= SHMEM_EEE_10G_ADV;
1876 return eee_adv << shift;
1879 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1881 struct bnx2x *bp = netdev_priv(dev);
1884 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1885 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1889 eee_cfg = bp->link_vars.eee_status;
1892 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1893 SHMEM_EEE_SUPPORTED_SHIFT);
1896 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1897 SHMEM_EEE_ADV_STATUS_SHIFT);
1898 edata->lp_advertised =
1899 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1900 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1902 /* SHMEM value is in 16u units --> Convert to 1u units. */
1903 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1905 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
1906 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
1907 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1912 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1914 struct bnx2x *bp = netdev_priv(dev);
1921 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1922 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1926 eee_cfg = bp->link_vars.eee_status;
1928 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
1929 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
1933 advertised = bnx2x_adv_to_eee(edata->advertised,
1934 SHMEM_EEE_ADV_STATUS_SHIFT);
1935 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
1936 DP(BNX2X_MSG_ETHTOOL,
1937 "Direct manipulation of EEE advertisement is not supported\n");
1941 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
1942 DP(BNX2X_MSG_ETHTOOL,
1943 "Maximal Tx Lpi timer supported is %x(u)\n",
1944 EEE_MODE_TIMER_MASK);
1947 if (edata->tx_lpi_enabled &&
1948 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
1949 DP(BNX2X_MSG_ETHTOOL,
1950 "Minimal Tx Lpi timer supported is %d(u)\n",
1951 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
1955 /* All is well; Apply changes*/
1956 if (edata->eee_enabled)
1957 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
1959 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
1961 if (edata->tx_lpi_enabled)
1962 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
1964 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
1966 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
1967 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
1968 EEE_MODE_TIMER_MASK) |
1969 EEE_MODE_OVERRIDE_NVRAM |
1970 EEE_MODE_OUTPUT_TIME;
1972 /* Restart link to propogate changes */
1973 if (netif_running(dev)) {
1974 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1975 bnx2x_force_link_reset(bp);
1983 BNX2X_CHIP_E1_OFST = 0,
1984 BNX2X_CHIP_E1H_OFST,
1987 BNX2X_CHIP_E3B0_OFST,
1991 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1992 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1993 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1994 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1995 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1997 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1998 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2000 static int bnx2x_test_registers(struct bnx2x *bp)
2002 int idx, i, rc = -ENODEV;
2004 int port = BP_PORT(bp);
2005 static const struct {
2011 /* 0 */ { BNX2X_CHIP_MASK_ALL,
2012 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2013 { BNX2X_CHIP_MASK_ALL,
2014 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2015 { BNX2X_CHIP_MASK_E1X,
2016 HC_REG_AGG_INT_0, 4, 0x000003ff },
2017 { BNX2X_CHIP_MASK_ALL,
2018 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2019 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2020 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2021 { BNX2X_CHIP_MASK_E3B0,
2022 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2023 { BNX2X_CHIP_MASK_ALL,
2024 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2025 { BNX2X_CHIP_MASK_ALL,
2026 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2027 { BNX2X_CHIP_MASK_ALL,
2028 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2029 { BNX2X_CHIP_MASK_ALL,
2030 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2031 /* 10 */ { BNX2X_CHIP_MASK_ALL,
2032 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2033 { BNX2X_CHIP_MASK_ALL,
2034 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2035 { BNX2X_CHIP_MASK_ALL,
2036 QM_REG_CONNNUM_0, 4, 0x000fffff },
2037 { BNX2X_CHIP_MASK_ALL,
2038 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2039 { BNX2X_CHIP_MASK_ALL,
2040 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2041 { BNX2X_CHIP_MASK_ALL,
2042 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2043 { BNX2X_CHIP_MASK_ALL,
2044 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2045 { BNX2X_CHIP_MASK_ALL,
2046 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2047 { BNX2X_CHIP_MASK_ALL,
2048 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2049 { BNX2X_CHIP_MASK_ALL,
2050 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2051 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2052 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2053 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2054 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2055 { BNX2X_CHIP_MASK_ALL,
2056 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2057 { BNX2X_CHIP_MASK_ALL,
2058 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2059 { BNX2X_CHIP_MASK_ALL,
2060 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2061 { BNX2X_CHIP_MASK_ALL,
2062 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2063 { BNX2X_CHIP_MASK_ALL,
2064 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2065 { BNX2X_CHIP_MASK_ALL,
2066 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2067 { BNX2X_CHIP_MASK_ALL,
2068 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2069 { BNX2X_CHIP_MASK_ALL,
2070 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2071 /* 30 */ { BNX2X_CHIP_MASK_ALL,
2072 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2073 { BNX2X_CHIP_MASK_ALL,
2074 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2075 { BNX2X_CHIP_MASK_ALL,
2076 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2077 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2078 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2079 { BNX2X_CHIP_MASK_ALL,
2080 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2081 { BNX2X_CHIP_MASK_ALL,
2082 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2083 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2084 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2085 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2086 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2088 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2091 if (!netif_running(bp->dev)) {
2092 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2093 "cannot access eeprom when the interface is down\n");
2098 hw = BNX2X_CHIP_MASK_E1;
2099 else if (CHIP_IS_E1H(bp))
2100 hw = BNX2X_CHIP_MASK_E1H;
2101 else if (CHIP_IS_E2(bp))
2102 hw = BNX2X_CHIP_MASK_E2;
2103 else if (CHIP_IS_E3B0(bp))
2104 hw = BNX2X_CHIP_MASK_E3B0;
2106 hw = BNX2X_CHIP_MASK_E3;
2108 /* Repeat the test twice:
2109 * First by writing 0x00000000, second by writing 0xffffffff
2111 for (idx = 0; idx < 2; idx++) {
2118 wr_val = 0xffffffff;
2122 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2123 u32 offset, mask, save_val, val;
2124 if (!(hw & reg_tbl[i].hw))
2127 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2128 mask = reg_tbl[i].mask;
2130 save_val = REG_RD(bp, offset);
2132 REG_WR(bp, offset, wr_val & mask);
2134 val = REG_RD(bp, offset);
2136 /* Restore the original register's value */
2137 REG_WR(bp, offset, save_val);
2139 /* verify value is as expected */
2140 if ((val & mask) != (wr_val & mask)) {
2141 DP(BNX2X_MSG_ETHTOOL,
2142 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2143 offset, val, wr_val, mask);
2155 static int bnx2x_test_memory(struct bnx2x *bp)
2157 int i, j, rc = -ENODEV;
2159 static const struct {
2163 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2164 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2165 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2166 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2167 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2168 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2169 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2174 static const struct {
2177 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2179 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2180 {0x3ffc0, 0, 0, 0} },
2181 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2183 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2185 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2186 {0x3ffc0, 0, 0, 0} },
2187 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2188 {0x3ffc0, 0, 0, 0} },
2189 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2190 {0x3ffc1, 0, 0, 0} },
2192 { NULL, 0xffffffff, {0, 0, 0, 0} }
2195 if (!netif_running(bp->dev)) {
2196 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2197 "cannot access eeprom when the interface is down\n");
2202 index = BNX2X_CHIP_E1_OFST;
2203 else if (CHIP_IS_E1H(bp))
2204 index = BNX2X_CHIP_E1H_OFST;
2205 else if (CHIP_IS_E2(bp))
2206 index = BNX2X_CHIP_E2_OFST;
2208 index = BNX2X_CHIP_E3_OFST;
2210 /* pre-Check the parity status */
2211 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2212 val = REG_RD(bp, prty_tbl[i].offset);
2213 if (val & ~(prty_tbl[i].hw_mask[index])) {
2214 DP(BNX2X_MSG_ETHTOOL,
2215 "%s is 0x%x\n", prty_tbl[i].name, val);
2220 /* Go through all the memories */
2221 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2222 for (j = 0; j < mem_tbl[i].size; j++)
2223 REG_RD(bp, mem_tbl[i].offset + j*4);
2225 /* Check the parity status */
2226 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2227 val = REG_RD(bp, prty_tbl[i].offset);
2228 if (val & ~(prty_tbl[i].hw_mask[index])) {
2229 DP(BNX2X_MSG_ETHTOOL,
2230 "%s is 0x%x\n", prty_tbl[i].name, val);
2241 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2246 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2249 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2250 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2253 while (!bp->link_vars.link_up && cnt--)
2256 if (cnt <= 0 && !bp->link_vars.link_up)
2257 DP(BNX2X_MSG_ETHTOOL,
2258 "Timeout waiting for link init\n");
2262 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2264 unsigned int pkt_size, num_pkts, i;
2265 struct sk_buff *skb;
2266 unsigned char *packet;
2267 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2268 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2269 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2270 u16 tx_start_idx, tx_idx;
2271 u16 rx_start_idx, rx_idx;
2272 u16 pkt_prod, bd_prod;
2273 struct sw_tx_bd *tx_buf;
2274 struct eth_tx_start_bd *tx_start_bd;
2276 union eth_rx_cqe *cqe;
2277 u8 cqe_fp_flags, cqe_fp_type;
2278 struct sw_rx_bd *rx_buf;
2282 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2285 /* check the loopback mode */
2286 switch (loopback_mode) {
2287 case BNX2X_PHY_LOOPBACK:
2288 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2289 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2293 case BNX2X_MAC_LOOPBACK:
2294 if (CHIP_IS_E3(bp)) {
2295 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2296 if (bp->port.supported[cfg_idx] &
2297 (SUPPORTED_10000baseT_Full |
2298 SUPPORTED_20000baseMLD2_Full |
2299 SUPPORTED_20000baseKR2_Full))
2300 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2302 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2304 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2306 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2308 case BNX2X_EXT_LOOPBACK:
2309 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2310 DP(BNX2X_MSG_ETHTOOL,
2311 "Can't configure external loopback\n");
2316 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2320 /* prepare the loopback packet */
2321 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2322 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2323 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2325 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2327 goto test_loopback_exit;
2329 packet = skb_put(skb, pkt_size);
2330 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2331 memset(packet + ETH_ALEN, 0, ETH_ALEN);
2332 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2333 for (i = ETH_HLEN; i < pkt_size; i++)
2334 packet[i] = (unsigned char) (i & 0xff);
2335 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2336 skb_headlen(skb), DMA_TO_DEVICE);
2337 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2340 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2341 goto test_loopback_exit;
2344 /* send the loopback packet */
2346 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2347 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2349 netdev_tx_sent_queue(txq, skb->len);
2351 pkt_prod = txdata->tx_pkt_prod++;
2352 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2353 tx_buf->first_bd = txdata->tx_bd_prod;
2357 bd_prod = TX_BD(txdata->tx_bd_prod);
2358 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2359 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2360 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2361 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2362 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2363 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2364 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2365 SET_FLAG(tx_start_bd->general_data,
2366 ETH_TX_START_BD_HDR_NBDS,
2368 SET_FLAG(tx_start_bd->general_data,
2369 ETH_TX_START_BD_PARSE_NBDS,
2372 /* turn on parsing and get a BD */
2373 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2375 if (CHIP_IS_E1x(bp)) {
2376 u16 global_data = 0;
2377 struct eth_tx_parse_bd_e1x *pbd_e1x =
2378 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2379 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2380 SET_FLAG(global_data,
2381 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2382 pbd_e1x->global_data = cpu_to_le16(global_data);
2384 u32 parsing_data = 0;
2385 struct eth_tx_parse_bd_e2 *pbd_e2 =
2386 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2387 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2388 SET_FLAG(parsing_data,
2389 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2390 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2394 txdata->tx_db.data.prod += 2;
2396 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2402 txdata->tx_bd_prod += 2; /* start + pbd */
2406 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2407 if (tx_idx != tx_start_idx + num_pkts)
2408 goto test_loopback_exit;
2410 /* Unlike HC IGU won't generate an interrupt for status block
2411 * updates that have been performed while interrupts were
2414 if (bp->common.int_block == INT_BLOCK_IGU) {
2415 /* Disable local BHes to prevent a dead-lock situation between
2416 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2417 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2420 bnx2x_tx_int(bp, txdata);
2424 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2425 if (rx_idx != rx_start_idx + num_pkts)
2426 goto test_loopback_exit;
2428 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2429 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2430 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2431 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2432 goto test_loopback_rx_exit;
2434 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2435 if (len != pkt_size)
2436 goto test_loopback_rx_exit;
2438 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2439 dma_sync_single_for_cpu(&bp->pdev->dev,
2440 dma_unmap_addr(rx_buf, mapping),
2441 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2442 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2443 for (i = ETH_HLEN; i < pkt_size; i++)
2444 if (*(data + i) != (unsigned char) (i & 0xff))
2445 goto test_loopback_rx_exit;
2449 test_loopback_rx_exit:
2451 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2452 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2453 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2454 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2456 /* Update producers */
2457 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2458 fp_rx->rx_sge_prod);
2461 bp->link_params.loopback_mode = LOOPBACK_NONE;
2466 static int bnx2x_test_loopback(struct bnx2x *bp)
2473 if (!netif_running(bp->dev))
2474 return BNX2X_LOOPBACK_FAILED;
2476 bnx2x_netif_stop(bp, 1);
2477 bnx2x_acquire_phy_lock(bp);
2479 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2481 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
2482 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2485 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2487 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
2488 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2491 bnx2x_release_phy_lock(bp);
2492 bnx2x_netif_start(bp);
2497 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2501 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2506 if (!netif_running(bp->dev))
2507 return BNX2X_EXT_LOOPBACK_FAILED;
2509 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2510 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2512 DP(BNX2X_MSG_ETHTOOL,
2513 "Can't perform self-test, nic_load (for external lb) failed\n");
2516 bnx2x_wait_for_link(bp, 1, is_serdes);
2518 bnx2x_netif_stop(bp, 1);
2520 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2522 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2524 bnx2x_netif_start(bp);
2529 #define CRC32_RESIDUAL 0xdebb20e3
2531 static int bnx2x_test_nvram(struct bnx2x *bp)
2533 static const struct {
2537 { 0, 0x14 }, /* bootstrap */
2538 { 0x14, 0xec }, /* dir */
2539 { 0x100, 0x350 }, /* manuf_info */
2540 { 0x450, 0xf0 }, /* feature_info */
2541 { 0x640, 0x64 }, /* upgrade_key_info */
2542 { 0x708, 0x70 }, /* manuf_key_info */
2553 buf = kmalloc(0x350, GFP_KERNEL);
2555 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2557 goto test_nvram_exit;
2561 rc = bnx2x_nvram_read(bp, 0, data, 4);
2563 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2564 "magic value read (rc %d)\n", rc);
2565 goto test_nvram_exit;
2568 magic = be32_to_cpu(buf[0]);
2569 if (magic != 0x669955aa) {
2570 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2571 "wrong magic value (0x%08x)\n", magic);
2573 goto test_nvram_exit;
2576 for (i = 0; nvram_tbl[i].size; i++) {
2578 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2581 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2582 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2583 goto test_nvram_exit;
2586 crc = ether_crc_le(nvram_tbl[i].size, data);
2587 if (crc != CRC32_RESIDUAL) {
2588 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2589 "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
2591 goto test_nvram_exit;
2600 /* Send an EMPTY ramrod on the first queue */
2601 static int bnx2x_test_intr(struct bnx2x *bp)
2603 struct bnx2x_queue_state_params params = {NULL};
2605 if (!netif_running(bp->dev)) {
2606 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2607 "cannot access eeprom when the interface is down\n");
2611 params.q_obj = &bp->sp_objs->q_obj;
2612 params.cmd = BNX2X_Q_CMD_EMPTY;
2614 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
2616 return bnx2x_queue_state_change(bp, ¶ms);
2619 static void bnx2x_self_test(struct net_device *dev,
2620 struct ethtool_test *etest, u64 *buf)
2622 struct bnx2x *bp = netdev_priv(dev);
2623 u8 is_serdes, link_up;
2626 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2628 "Handling parity error recovery. Try again later\n");
2629 etest->flags |= ETH_TEST_FL_FAILED;
2633 DP(BNX2X_MSG_ETHTOOL,
2634 "Self-test command parameters: offline = %d, external_lb = %d\n",
2635 (etest->flags & ETH_TEST_FL_OFFLINE),
2636 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2638 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2640 if (!netif_running(dev)) {
2641 DP(BNX2X_MSG_ETHTOOL,
2642 "Can't perform self-test when interface is down\n");
2646 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2647 link_up = bp->link_vars.link_up;
2648 /* offline tests are not supported in MF mode */
2649 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2650 int port = BP_PORT(bp);
2653 /* save current value of input enable for TX port IF */
2654 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2655 /* disable input for TX port IF */
2656 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2658 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2659 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2661 etest->flags |= ETH_TEST_FL_FAILED;
2662 DP(BNX2X_MSG_ETHTOOL,
2663 "Can't perform self-test, nic_load (for offline) failed\n");
2667 /* wait until link state is restored */
2668 bnx2x_wait_for_link(bp, 1, is_serdes);
2670 if (bnx2x_test_registers(bp) != 0) {
2672 etest->flags |= ETH_TEST_FL_FAILED;
2674 if (bnx2x_test_memory(bp) != 0) {
2676 etest->flags |= ETH_TEST_FL_FAILED;
2679 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
2681 etest->flags |= ETH_TEST_FL_FAILED;
2683 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2684 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2686 etest->flags |= ETH_TEST_FL_FAILED;
2687 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2690 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2692 /* restore input for TX port IF */
2693 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2694 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2696 etest->flags |= ETH_TEST_FL_FAILED;
2697 DP(BNX2X_MSG_ETHTOOL,
2698 "Can't perform self-test, nic_load (for online) failed\n");
2701 /* wait until link state is restored */
2702 bnx2x_wait_for_link(bp, link_up, is_serdes);
2704 if (bnx2x_test_nvram(bp) != 0) {
2709 etest->flags |= ETH_TEST_FL_FAILED;
2711 if (bnx2x_test_intr(bp) != 0) {
2716 etest->flags |= ETH_TEST_FL_FAILED;
2721 while (bnx2x_link_test(bp, is_serdes) && --cnt)
2730 etest->flags |= ETH_TEST_FL_FAILED;
2734 #define IS_PORT_STAT(i) \
2735 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2736 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2737 #define IS_MF_MODE_STAT(bp) \
2738 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2740 /* ethtool statistics are displayed for all regular ethernet queues and the
2741 * fcoe L2 queue if not disabled
2743 static int bnx2x_num_stat_queues(struct bnx2x *bp)
2745 return BNX2X_NUM_ETH_QUEUES(bp);
2748 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2750 struct bnx2x *bp = netdev_priv(dev);
2753 switch (stringset) {
2756 num_stats = bnx2x_num_stat_queues(bp) *
2760 if (IS_MF_MODE_STAT(bp)) {
2761 for (i = 0; i < BNX2X_NUM_STATS; i++)
2762 if (IS_FUNC_STAT(i))
2765 num_stats += BNX2X_NUM_STATS;
2770 return BNX2X_NUM_TESTS(bp);
2777 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2779 struct bnx2x *bp = netdev_priv(dev);
2781 char queue_name[MAX_QUEUE_NAME_LEN+1];
2783 switch (stringset) {
2787 for_each_eth_queue(bp, i) {
2788 memset(queue_name, 0, sizeof(queue_name));
2789 sprintf(queue_name, "%d", i);
2790 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2791 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2793 bnx2x_q_stats_arr[j].string,
2795 k += BNX2X_NUM_Q_STATS;
2800 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2801 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2803 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2804 bnx2x_stats_arr[i].string);
2811 /* First 4 tests cannot be done in MF mode */
2816 memcpy(buf, bnx2x_tests_str_arr + start,
2817 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
2821 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2822 struct ethtool_stats *stats, u64 *buf)
2824 struct bnx2x *bp = netdev_priv(dev);
2825 u32 *hw_stats, *offset;
2829 for_each_eth_queue(bp, i) {
2830 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
2831 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2832 if (bnx2x_q_stats_arr[j].size == 0) {
2833 /* skip this counter */
2837 offset = (hw_stats +
2838 bnx2x_q_stats_arr[j].offset);
2839 if (bnx2x_q_stats_arr[j].size == 4) {
2840 /* 4-byte counter */
2841 buf[k + j] = (u64) *offset;
2844 /* 8-byte counter */
2845 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2847 k += BNX2X_NUM_Q_STATS;
2851 hw_stats = (u32 *)&bp->eth_stats;
2852 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2853 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2855 if (bnx2x_stats_arr[i].size == 0) {
2856 /* skip this counter */
2861 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2862 if (bnx2x_stats_arr[i].size == 4) {
2863 /* 4-byte counter */
2864 buf[k + j] = (u64) *offset;
2868 /* 8-byte counter */
2869 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2874 static int bnx2x_set_phys_id(struct net_device *dev,
2875 enum ethtool_phys_id_state state)
2877 struct bnx2x *bp = netdev_priv(dev);
2879 if (!netif_running(dev)) {
2880 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2881 "cannot access eeprom when the interface is down\n");
2885 if (!bp->port.pmf) {
2886 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
2891 case ETHTOOL_ID_ACTIVE:
2892 return 1; /* cycle on/off once per second */
2895 bnx2x_acquire_phy_lock(bp);
2896 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2897 LED_MODE_ON, SPEED_1000);
2898 bnx2x_release_phy_lock(bp);
2901 case ETHTOOL_ID_OFF:
2902 bnx2x_acquire_phy_lock(bp);
2903 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2904 LED_MODE_FRONT_PANEL_OFF, 0);
2905 bnx2x_release_phy_lock(bp);
2908 case ETHTOOL_ID_INACTIVE:
2909 bnx2x_acquire_phy_lock(bp);
2910 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2912 bp->link_vars.line_speed);
2913 bnx2x_release_phy_lock(bp);
2919 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2922 switch (info->flow_type) {
2925 info->data = RXH_IP_SRC | RXH_IP_DST |
2926 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2929 if (bp->rss_conf_obj.udp_rss_v4)
2930 info->data = RXH_IP_SRC | RXH_IP_DST |
2931 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2933 info->data = RXH_IP_SRC | RXH_IP_DST;
2936 if (bp->rss_conf_obj.udp_rss_v6)
2937 info->data = RXH_IP_SRC | RXH_IP_DST |
2938 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2940 info->data = RXH_IP_SRC | RXH_IP_DST;
2944 info->data = RXH_IP_SRC | RXH_IP_DST;
2954 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2955 u32 *rules __always_unused)
2957 struct bnx2x *bp = netdev_priv(dev);
2959 switch (info->cmd) {
2960 case ETHTOOL_GRXRINGS:
2961 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2964 return bnx2x_get_rss_flags(bp, info);
2966 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2971 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
2973 int udp_rss_requested;
2975 DP(BNX2X_MSG_ETHTOOL,
2976 "Set rss flags command parameters: flow type = %d, data = %llu\n",
2977 info->flow_type, info->data);
2979 switch (info->flow_type) {
2982 /* For TCP only 4-tupple hash is supported */
2983 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
2984 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2985 DP(BNX2X_MSG_ETHTOOL,
2986 "Command parameters not supported\n");
2993 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
2994 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
2995 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2996 udp_rss_requested = 1;
2997 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
2998 udp_rss_requested = 0;
3001 if ((info->flow_type == UDP_V4_FLOW) &&
3002 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3003 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3004 DP(BNX2X_MSG_ETHTOOL,
3005 "rss re-configured, UDP 4-tupple %s\n",
3006 udp_rss_requested ? "enabled" : "disabled");
3007 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
3008 } else if ((info->flow_type == UDP_V6_FLOW) &&
3009 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3010 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3011 DP(BNX2X_MSG_ETHTOOL,
3012 "rss re-configured, UDP 4-tupple %s\n",
3013 udp_rss_requested ? "enabled" : "disabled");
3014 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
3020 /* For IP only 2-tupple hash is supported */
3021 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3022 DP(BNX2X_MSG_ETHTOOL,
3023 "Command parameters not supported\n");
3029 case AH_ESP_V4_FLOW:
3033 case AH_ESP_V6_FLOW:
3038 /* RSS is not supported for these protocols */
3040 DP(BNX2X_MSG_ETHTOOL,
3041 "Command parameters not supported\n");
3051 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3053 struct bnx2x *bp = netdev_priv(dev);
3055 switch (info->cmd) {
3057 return bnx2x_set_rss_flags(bp, info);
3059 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3064 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3066 return T_ETH_INDIRECTION_TABLE_SIZE;
3069 static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
3071 struct bnx2x *bp = netdev_priv(dev);
3072 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3075 /* Get the current configuration of the RSS indirection table */
3076 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3079 * We can't use a memcpy() as an internal storage of an
3080 * indirection table is a u8 array while indir->ring_index
3081 * points to an array of u32.
3083 * Indirection table contains the FW Client IDs, so we need to
3084 * align the returned table to the Client ID of the leading RSS
3087 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3088 indir[i] = ind_table[i] - bp->fp->cl_id;
3093 static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
3095 struct bnx2x *bp = netdev_priv(dev);
3098 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3100 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
3101 * as an internal storage of an indirection table is a u8 array
3102 * while indir->ring_index points to an array of u32.
3104 * Indirection table contains the FW Client IDs, so we need to
3105 * align the received table to the Client ID of the leading RSS
3108 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3111 return bnx2x_config_rss_eth(bp, false);
3115 * bnx2x_get_channels - gets the number of RSS queues.
3118 * @channels: returns the number of max / current queues
3120 static void bnx2x_get_channels(struct net_device *dev,
3121 struct ethtool_channels *channels)
3123 struct bnx2x *bp = netdev_priv(dev);
3125 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3126 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3130 * bnx2x_change_num_queues - change the number of RSS queues.
3132 * @bp: bnx2x private structure
3134 * Re-configure interrupt mode to get the new number of MSI-X
3135 * vectors and re-add NAPI objects.
3137 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3139 bnx2x_disable_msi(bp);
3140 bp->num_ethernet_queues = num_rss;
3141 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3142 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3143 bnx2x_set_int_mode(bp);
3147 * bnx2x_set_channels - sets the number of RSS queues.
3150 * @channels: includes the number of queues requested
3152 static int bnx2x_set_channels(struct net_device *dev,
3153 struct ethtool_channels *channels)
3155 struct bnx2x *bp = netdev_priv(dev);
3158 DP(BNX2X_MSG_ETHTOOL,
3159 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3160 channels->rx_count, channels->tx_count, channels->other_count,
3161 channels->combined_count);
3163 /* We don't support separate rx / tx channels.
3164 * We don't allow setting 'other' channels.
3166 if (channels->rx_count || channels->tx_count || channels->other_count
3167 || (channels->combined_count == 0) ||
3168 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3169 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3173 /* Check if there was a change in the active parameters */
3174 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3175 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3179 /* Set the requested number of queues in bp context.
3180 * Note that the actual number of queues created during load may be
3181 * less than requested if memory is low.
3183 if (unlikely(!netif_running(dev))) {
3184 bnx2x_change_num_queues(bp, channels->combined_count);
3187 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3188 bnx2x_change_num_queues(bp, channels->combined_count);
3189 return bnx2x_nic_load(bp, LOAD_NORMAL);
3192 static const struct ethtool_ops bnx2x_ethtool_ops = {
3193 .get_settings = bnx2x_get_settings,
3194 .set_settings = bnx2x_set_settings,
3195 .get_drvinfo = bnx2x_get_drvinfo,
3196 .get_regs_len = bnx2x_get_regs_len,
3197 .get_regs = bnx2x_get_regs,
3198 .get_dump_flag = bnx2x_get_dump_flag,
3199 .get_dump_data = bnx2x_get_dump_data,
3200 .set_dump = bnx2x_set_dump,
3201 .get_wol = bnx2x_get_wol,
3202 .set_wol = bnx2x_set_wol,
3203 .get_msglevel = bnx2x_get_msglevel,
3204 .set_msglevel = bnx2x_set_msglevel,
3205 .nway_reset = bnx2x_nway_reset,
3206 .get_link = bnx2x_get_link,
3207 .get_eeprom_len = bnx2x_get_eeprom_len,
3208 .get_eeprom = bnx2x_get_eeprom,
3209 .set_eeprom = bnx2x_set_eeprom,
3210 .get_coalesce = bnx2x_get_coalesce,
3211 .set_coalesce = bnx2x_set_coalesce,
3212 .get_ringparam = bnx2x_get_ringparam,
3213 .set_ringparam = bnx2x_set_ringparam,
3214 .get_pauseparam = bnx2x_get_pauseparam,
3215 .set_pauseparam = bnx2x_set_pauseparam,
3216 .self_test = bnx2x_self_test,
3217 .get_sset_count = bnx2x_get_sset_count,
3218 .get_strings = bnx2x_get_strings,
3219 .set_phys_id = bnx2x_set_phys_id,
3220 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3221 .get_rxnfc = bnx2x_get_rxnfc,
3222 .set_rxnfc = bnx2x_set_rxnfc,
3223 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3224 .get_rxfh_indir = bnx2x_get_rxfh_indir,
3225 .set_rxfh_indir = bnx2x_set_rxfh_indir,
3226 .get_channels = bnx2x_get_channels,
3227 .set_channels = bnx2x_set_channels,
3228 .get_module_info = bnx2x_get_module_info,
3229 .get_module_eeprom = bnx2x_get_module_eeprom,
3230 .get_eee = bnx2x_get_eee,
3231 .set_eee = bnx2x_set_eee,
3232 .get_ts_info = ethtool_op_get_ts_info,
3235 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3236 .get_settings = bnx2x_get_settings,
3237 .set_settings = bnx2x_set_settings,
3238 .get_drvinfo = bnx2x_get_drvinfo,
3239 .get_msglevel = bnx2x_get_msglevel,
3240 .set_msglevel = bnx2x_set_msglevel,
3241 .get_link = bnx2x_get_link,
3242 .get_coalesce = bnx2x_get_coalesce,
3243 .get_ringparam = bnx2x_get_ringparam,
3244 .set_ringparam = bnx2x_set_ringparam,
3245 .get_sset_count = bnx2x_get_sset_count,
3246 .get_strings = bnx2x_get_strings,
3247 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3248 .get_rxnfc = bnx2x_get_rxnfc,
3249 .set_rxnfc = bnx2x_set_rxnfc,
3250 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3251 .get_rxfh_indir = bnx2x_get_rxfh_indir,
3252 .set_rxfh_indir = bnx2x_set_rxfh_indir,
3253 .get_channels = bnx2x_get_channels,
3254 .set_channels = bnx2x_set_channels,
3257 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3260 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
3262 SET_ETHTOOL_OPS(netdev, &bnx2x_vf_ethtool_ops);