1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
12 #include "bnx2x_fw_defs.h"
13 #include "bnx2x_mfw_req.h"
15 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
37 /****************************************************************************
38 * Shared HW configuration *
39 ****************************************************************************/
40 #define PIN_CFG_NA 0x00000000
41 #define PIN_CFG_GPIO0_P0 0x00000001
42 #define PIN_CFG_GPIO1_P0 0x00000002
43 #define PIN_CFG_GPIO2_P0 0x00000003
44 #define PIN_CFG_GPIO3_P0 0x00000004
45 #define PIN_CFG_GPIO0_P1 0x00000005
46 #define PIN_CFG_GPIO1_P1 0x00000006
47 #define PIN_CFG_GPIO2_P1 0x00000007
48 #define PIN_CFG_GPIO3_P1 0x00000008
49 #define PIN_CFG_EPIO0 0x00000009
50 #define PIN_CFG_EPIO1 0x0000000a
51 #define PIN_CFG_EPIO2 0x0000000b
52 #define PIN_CFG_EPIO3 0x0000000c
53 #define PIN_CFG_EPIO4 0x0000000d
54 #define PIN_CFG_EPIO5 0x0000000e
55 #define PIN_CFG_EPIO6 0x0000000f
56 #define PIN_CFG_EPIO7 0x00000010
57 #define PIN_CFG_EPIO8 0x00000011
58 #define PIN_CFG_EPIO9 0x00000012
59 #define PIN_CFG_EPIO10 0x00000013
60 #define PIN_CFG_EPIO11 0x00000014
61 #define PIN_CFG_EPIO12 0x00000015
62 #define PIN_CFG_EPIO13 0x00000016
63 #define PIN_CFG_EPIO14 0x00000017
64 #define PIN_CFG_EPIO15 0x00000018
65 #define PIN_CFG_EPIO16 0x00000019
66 #define PIN_CFG_EPIO17 0x0000001a
67 #define PIN_CFG_EPIO18 0x0000001b
68 #define PIN_CFG_EPIO19 0x0000001c
69 #define PIN_CFG_EPIO20 0x0000001d
70 #define PIN_CFG_EPIO21 0x0000001e
71 #define PIN_CFG_EPIO22 0x0000001f
72 #define PIN_CFG_EPIO23 0x00000020
73 #define PIN_CFG_EPIO24 0x00000021
74 #define PIN_CFG_EPIO25 0x00000022
75 #define PIN_CFG_EPIO26 0x00000023
76 #define PIN_CFG_EPIO27 0x00000024
77 #define PIN_CFG_EPIO28 0x00000025
78 #define PIN_CFG_EPIO29 0x00000026
79 #define PIN_CFG_EPIO30 0x00000027
80 #define PIN_CFG_EPIO31 0x00000028
83 #define EPIO_CFG_NA 0x00000000
84 #define EPIO_CFG_EPIO0 0x00000001
85 #define EPIO_CFG_EPIO1 0x00000002
86 #define EPIO_CFG_EPIO2 0x00000003
87 #define EPIO_CFG_EPIO3 0x00000004
88 #define EPIO_CFG_EPIO4 0x00000005
89 #define EPIO_CFG_EPIO5 0x00000006
90 #define EPIO_CFG_EPIO6 0x00000007
91 #define EPIO_CFG_EPIO7 0x00000008
92 #define EPIO_CFG_EPIO8 0x00000009
93 #define EPIO_CFG_EPIO9 0x0000000a
94 #define EPIO_CFG_EPIO10 0x0000000b
95 #define EPIO_CFG_EPIO11 0x0000000c
96 #define EPIO_CFG_EPIO12 0x0000000d
97 #define EPIO_CFG_EPIO13 0x0000000e
98 #define EPIO_CFG_EPIO14 0x0000000f
99 #define EPIO_CFG_EPIO15 0x00000010
100 #define EPIO_CFG_EPIO16 0x00000011
101 #define EPIO_CFG_EPIO17 0x00000012
102 #define EPIO_CFG_EPIO18 0x00000013
103 #define EPIO_CFG_EPIO19 0x00000014
104 #define EPIO_CFG_EPIO20 0x00000015
105 #define EPIO_CFG_EPIO21 0x00000016
106 #define EPIO_CFG_EPIO22 0x00000017
107 #define EPIO_CFG_EPIO23 0x00000018
108 #define EPIO_CFG_EPIO24 0x00000019
109 #define EPIO_CFG_EPIO25 0x0000001a
110 #define EPIO_CFG_EPIO26 0x0000001b
111 #define EPIO_CFG_EPIO27 0x0000001c
112 #define EPIO_CFG_EPIO28 0x0000001d
113 #define EPIO_CFG_EPIO29 0x0000001e
114 #define EPIO_CFG_EPIO30 0x0000001f
115 #define EPIO_CFG_EPIO31 0x00000020
118 struct shared_hw_cfg { /* NVRAM Offset */
119 /* Up to 16 bytes of NULL-terminated string */
120 u8 part_num[16]; /* 0x104 */
122 u32 config; /* 0x114 */
123 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
124 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
125 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
126 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
127 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
129 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
131 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
133 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
134 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
136 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
137 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
138 /* Whatever MFW found in NVM
139 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
140 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
141 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
142 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
143 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
144 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
145 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
146 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
147 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
148 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
149 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
150 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
151 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
152 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
154 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
155 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
156 #define SHARED_HW_CFG_LED_MAC1 0x00000000
157 #define SHARED_HW_CFG_LED_PHY1 0x00010000
158 #define SHARED_HW_CFG_LED_PHY2 0x00020000
159 #define SHARED_HW_CFG_LED_PHY3 0x00030000
160 #define SHARED_HW_CFG_LED_MAC2 0x00040000
161 #define SHARED_HW_CFG_LED_PHY4 0x00050000
162 #define SHARED_HW_CFG_LED_PHY5 0x00060000
163 #define SHARED_HW_CFG_LED_PHY6 0x00070000
164 #define SHARED_HW_CFG_LED_MAC3 0x00080000
165 #define SHARED_HW_CFG_LED_PHY7 0x00090000
166 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
167 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
168 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
169 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
170 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
173 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
174 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
175 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
176 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
177 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
178 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
179 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
180 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
182 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
183 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
184 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
186 #define SHARED_HW_CFG_ATC_MASK 0x80000000
187 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
188 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
190 u32 config2; /* 0x118 */
191 /* one time auto detect grace period (in sec) */
192 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
193 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
195 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
196 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
198 /* The default value for the core clock is 250MHz and it is
199 achieved by setting the clock change to 4 */
200 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
201 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
203 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
204 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
205 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
207 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
209 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000
210 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
211 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
213 /* Output low when PERST is asserted */
214 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
215 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
216 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
218 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
219 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
220 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
221 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
222 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
225 /* The fan failure mechanism is usually related to the PHY type
226 since the power consumption of the board is determined by the PHY.
227 Currently, fan is required for most designs with SFX7101, BCM8727
228 and BCM8481. If a fan is not required for a board which uses one
229 of those PHYs, this field should be set to "Disabled". If a fan is
230 required for a different PHY type, this option should be set to
231 "Enabled". The fan failure indication is expected on SPIO5 */
232 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
233 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
234 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
235 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
236 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
238 /* ASPM Power Management support */
239 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
240 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
241 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
242 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
243 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
244 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
246 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
247 tl_control_0 (register 0x2800) */
248 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
249 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
250 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
252 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000
253 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000
254 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000
256 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000
257 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000
258 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000
260 /* Set the MDC/MDIO access for the first external phy */
261 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
262 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
263 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
264 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
269 /* Set the MDC/MDIO access for the second external phy */
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
279 u32 power_dissipated; /* 0x11c */
280 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
281 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
282 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
283 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
284 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
285 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
287 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
288 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
290 u32 ump_nc_si_config; /* 0x120 */
291 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
292 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
293 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
294 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
298 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
299 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
301 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
302 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
303 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
304 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
306 u32 board; /* 0x124 */
307 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
308 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
309 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
310 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
311 /* Use the PIN_CFG_XXX defines on top */
312 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
313 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
315 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
316 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
318 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
319 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
321 u32 wc_lane_config; /* 0x128 */
322 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
323 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
324 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
325 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
326 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
333 /* TX lane Polarity swap */
334 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
335 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
336 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
337 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
338 /* TX lane Polarity swap */
339 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
340 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
341 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
342 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
344 /* Selects the port layout of the board */
345 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
346 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
347 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
348 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
356 /****************************************************************************
357 * Port HW configuration *
358 ****************************************************************************/
359 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
362 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
363 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
366 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
367 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
369 u32 power_dissipated;
370 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
371 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
372 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
373 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
374 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
375 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
376 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
377 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
380 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
381 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
382 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
383 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
384 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
385 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
386 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
387 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
390 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
391 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
394 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
397 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
401 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
402 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
404 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
405 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
408 /* Default values: 2P-64, 4P-32 */
409 u32 pf_config; /* 0x158 */
410 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F
411 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0
413 /* Default values: 17 */
414 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00
415 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8
417 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000
418 #define PORT_HW_CFG_FLR_ENABLED 0x00010000
420 u32 vf_config; /* 0x15C */
421 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F
422 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0
424 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
425 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
427 u32 mf_pci_id; /* 0x160 */
428 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
429 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
431 /* Controls the TX laser of the SFP+ module */
432 u32 sfp_ctrl; /* 0x164 */
433 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
434 #define PORT_HW_CFG_TX_LASER_SHIFT 0
435 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
436 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
437 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
438 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
439 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
441 /* Controls the fault module LED of the SFP+ */
442 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
443 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
444 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
445 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
447 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
448 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
450 /* The output pin TX_DIS that controls the TX laser of the SFP+
451 module. Use the PIN_CFG_XXX defines on top */
452 u32 e3_sfp_ctrl; /* 0x168 */
453 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
454 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
456 /* The output pin for SFPP_TYPE which turns on the Fault module LED */
457 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
458 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
460 /* The input pin MOD_ABS that indicates whether SFP+ module is
461 present or not. Use the PIN_CFG_XXX defines on top */
462 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
463 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
465 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+
466 module. Use the PIN_CFG_XXX defines on top */
467 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
468 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
471 * The input pin which signals module transmit fault. Use the
472 * PIN_CFG_XXX defines on top
474 u32 e3_cmn_pin_cfg; /* 0x16C */
475 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
476 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
478 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
480 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
481 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
484 * The output pin which powers down the PHY. Use the PIN_CFG_XXX
487 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
488 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
490 /* The output pin values BSC_SEL which selects the I2C for this port
492 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
493 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
497 * The input pin I_FAULT which indicate over-current has occurred.
498 * Use the PIN_CFG_XXX defines on top
500 u32 e3_cmn_pin_cfg1; /* 0x170 */
501 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
502 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
504 /* pause on host ring */
505 u32 generic_features; /* 0x174 */
506 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001
507 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0
508 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000
509 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001
511 u32 reserved0[6]; /* 0x178 */
513 u32 aeu_int_mask; /* 0x190 */
515 u32 media_type; /* 0x194 */
516 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
517 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
519 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
520 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
522 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
523 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
525 /* 4 times 16 bits for all 4 lanes. In case external PHY is present
526 (not direct mode), those values will not take effect on the 4 XGXS
527 lanes. For some external PHYs (such as 8706 and 8726) the values
528 will be used to configure the external PHY in those cases, not
529 all 4 values are needed. */
530 u16 xgxs_config_rx[4]; /* 0x198 */
531 u16 xgxs_config_tx[4]; /* 0x1A0 */
533 /* For storing FCOE mac on shared memory */
534 u32 fcoe_fip_mac_upper;
535 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
536 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
537 u32 fcoe_fip_mac_lower;
539 u32 fcoe_wwn_port_name_upper;
540 u32 fcoe_wwn_port_name_lower;
542 u32 fcoe_wwn_node_name_upper;
543 u32 fcoe_wwn_node_name_lower;
545 u32 Reserved1[49]; /* 0x1C0 */
547 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
549 u32 xgbt_phy_cfg; /* 0x284 */
550 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
551 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
553 u32 default_cfg; /* 0x288 */
554 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
555 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
556 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
557 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
558 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
559 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
561 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
562 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
563 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
564 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
565 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
566 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
568 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
569 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
570 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
571 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
572 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
573 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
575 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
576 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
577 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
578 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
579 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
580 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
582 /* When KR link is required to be set to force which is not
583 KR-compliant, this parameter determine what is the trigger for it.
584 When GPIO is selected, low input will force the speed. Currently
585 default speed is 1G. In the future, it may be widen to select the
586 forced speed in with another parameter. Note when force-1G is
587 enabled, it override option 56: Link Speed option. */
588 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
589 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
590 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
591 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
592 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
593 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
594 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
595 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
596 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
597 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
598 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
599 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
600 /* Enable to determine with which GPIO to reset the external phy */
601 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
602 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
603 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
604 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
605 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
606 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
607 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
608 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
609 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
610 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
611 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
613 /* Enable BAM on KR */
614 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
615 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
616 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
617 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
619 /* Enable Common Mode Sense */
620 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
621 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
622 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
623 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
625 /* Determine the Serdes electrical interface */
626 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
627 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
628 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
629 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
630 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
631 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
632 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
633 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
636 u32 speed_capability_mask2; /* 0x28C */
637 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
638 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
639 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
643 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
644 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
649 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
650 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
651 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
652 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
653 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
654 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
655 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
656 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
657 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
660 /* In the case where two media types (e.g. copper and fiber) are
661 present and electrically active at the same time, PHY Selection
662 will determine which of the two PHYs will be designated as the
663 Active PHY and used for a connection to the network. */
664 u32 multi_phy_config; /* 0x290 */
665 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
666 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
667 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
668 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
669 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
670 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
671 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
673 /* When enabled, all second phy nvram parameters will be swapped
674 with the first phy parameters */
675 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
676 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
677 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
678 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
681 /* Address of the second external phy */
682 u32 external_phy_config2; /* 0x294 */
683 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
684 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
686 /* The second XGXS external PHY type */
687 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
688 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
700 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
701 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
702 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
703 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
704 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
705 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
706 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100
707 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
708 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
711 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
712 8706, 8726 and 8727) not all 4 values are needed. */
713 u16 xgxs_config2_rx[4]; /* 0x296 */
714 u16 xgxs_config2_tx[4]; /* 0x2A0 */
717 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
718 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
720 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
722 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
724 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
726 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
727 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
728 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
729 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
730 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
731 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
732 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
734 /* Indicate whether to swap the external phy polarity */
735 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
736 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
737 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
740 u32 external_phy_config;
741 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
742 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
744 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
757 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
759 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
760 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
761 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
762 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
763 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100
764 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
765 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
766 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
768 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
769 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
771 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
772 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
773 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
774 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
775 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
776 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
778 u32 speed_capability_mask;
779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
780 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
781 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
782 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
783 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
784 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
785 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
786 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
787 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
788 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
789 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
792 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
793 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
794 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
795 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
796 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
797 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
798 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
799 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
800 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
801 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
803 /* A place to hold the original MAC address as a backup */
804 u32 backup_mac_upper; /* 0x2B4 */
805 u32 backup_mac_lower; /* 0x2B8 */
810 /****************************************************************************
811 * Shared Feature configuration *
812 ****************************************************************************/
813 struct shared_feat_cfg { /* NVRAM Offset */
815 u32 config; /* 0x450 */
816 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
818 /* Use NVRAM values instead of HW default values */
819 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
821 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
823 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
826 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
827 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
828 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
830 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
831 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
833 /* Override the OTP back to single function mode. When using GPIO,
834 high means only SF, 0 is according to CLP configuration */
835 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
836 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
837 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
838 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
839 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
840 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
841 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
843 /* The interval in seconds between sending LLDP packets. Set to zero
844 to disable the feature */
845 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000
846 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
848 /* The assigned device type ID for LLDP usage */
849 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000
850 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
855 /****************************************************************************
856 * Port Feature configuration *
857 ****************************************************************************/
858 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
861 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
862 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
863 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
864 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
865 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
866 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
867 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
868 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
869 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
870 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
871 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
872 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
873 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
874 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
875 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
876 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
877 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
878 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
879 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
880 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
881 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
882 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
883 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
884 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
885 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
886 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
887 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
888 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
889 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
890 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
891 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
892 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
893 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
894 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
895 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
896 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
898 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
899 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
900 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
902 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00
903 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400
904 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
906 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
907 #define PORT_FEATURE_EN_SIZE_SHIFT 24
908 #define PORT_FEATURE_WOL_ENABLED 0x01000000
909 #define PORT_FEATURE_MBA_ENABLED 0x02000000
910 #define PORT_FEATURE_MFW_ENABLED 0x04000000
912 /* Advertise expansion ROM even if MBA is disabled */
913 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
914 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
915 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
917 /* Check the optic vendor via i2c against a list of approved modules
918 in a separate nvram image */
919 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000
920 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
921 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
923 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
925 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
926 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
929 /* Default is used when driver sets to "auto" mode */
930 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
931 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
932 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
933 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
934 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
935 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
936 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
937 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
938 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
941 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
942 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
943 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
944 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
945 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
946 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
947 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
948 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
950 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
951 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
953 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
954 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
955 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
956 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
957 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
958 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
959 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
960 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
961 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
962 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
963 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
964 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
965 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
966 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
967 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
968 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
969 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
970 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
971 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
972 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
973 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
974 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
975 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
976 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
977 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
978 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
979 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
980 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
981 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
982 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
983 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
984 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
985 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
986 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
987 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
988 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
989 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
990 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
991 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
992 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
993 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
994 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
995 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000
997 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001
998 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
999 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
1002 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
1003 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
1004 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
1007 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
1008 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
1009 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
1010 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
1011 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
1014 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1015 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1018 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f
1019 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1020 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1021 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1022 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1023 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1024 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1025 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1026 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1027 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1028 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1029 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1030 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1031 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1032 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1033 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1034 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1035 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1037 u32 link_config; /* Used as HW defaults for the driver */
1038 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1039 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1040 /* (forced) low speed switch (< 10G) */
1041 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1042 /* (forced) high speed switch (>= 10G) */
1043 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1044 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1045 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1047 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
1048 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1049 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1050 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1051 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1052 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1053 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1054 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1055 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1056 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1057 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1059 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1060 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1061 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1062 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1063 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1064 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1065 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1067 /* The default for MCP link configuration,
1068 uses the same defines as link_config */
1069 u32 mfw_wol_link_cfg;
1071 /* The default for the driver of the second external phy,
1072 uses the same defines as link_config */
1073 u32 link_config2; /* 0x47C */
1075 /* The default for MCP of the second external phy,
1076 uses the same defines as link_config */
1077 u32 mfw_wol_link_cfg2; /* 0x480 */
1080 /* EEE power saving mode */
1081 u32 eee_power_mode; /* 0x484 */
1082 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF
1083 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
1084 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000
1085 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001
1086 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002
1087 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
1090 u32 Reserved2[16]; /* 0x488 */
1094 /****************************************************************************
1095 * Device Information *
1096 ****************************************************************************/
1097 struct shm_dev_info { /* size */
1099 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
1101 struct shared_hw_cfg shared_hw_config; /* 40 */
1103 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
1105 struct shared_feat_cfg shared_feature_config; /* 4 */
1107 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
1112 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1113 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1124 #define E1_FUNC_MAX 2
1125 #define E1H_FUNC_MAX 8
1126 #define E2_FUNC_MAX 4 /* per path */
1135 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */
1136 /* This value (in milliseconds) determines the frequency of the driver
1137 * issuing the PULSE message code. The firmware monitors this periodic
1138 * pulse to determine when to switch to an OS-absent mode. */
1139 #define DRV_PULSE_PERIOD_MS 250
1141 /* This value (in milliseconds) determines how long the driver should
1142 * wait for an acknowledgement from the firmware before timing out. Once
1143 * the firmware has timed out, the driver will assume there is no firmware
1144 * running and there won't be any firmware-driver synchronization during a
1146 #define FW_ACK_TIME_OUT_MS 5000
1148 #define FW_ACK_POLL_TIME_MS 1
1150 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1152 #define MFW_TRACE_SIGNATURE 0x54524342
1154 /****************************************************************************
1155 * Driver <-> FW Mailbox *
1156 ****************************************************************************/
1157 struct drv_port_mb {
1160 /* Driver should update this field on any link change event */
1162 #define LINK_STATUS_NONE (0<<0)
1163 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1164 #define LINK_STATUS_LINK_UP 0x00000001
1165 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1166 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1167 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1168 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1169 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1170 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1171 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1172 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1173 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1174 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1175 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1176 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1177 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1178 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1179 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1180 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1181 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1183 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1184 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1186 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1187 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1188 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1190 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1191 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1192 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1193 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1194 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1195 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1196 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1198 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1199 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1201 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1202 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1204 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1205 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1206 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1207 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1208 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1210 #define LINK_STATUS_SERDES_LINK 0x00100000
1212 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1213 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1214 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1215 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1217 #define LINK_STATUS_PFC_ENABLED 0x20000000
1219 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1220 #define LINK_STATUS_SFP_TX_FAULT 0x80000000
1226 /* MCP firmware does not use this field */
1227 u32 ext_phy_fw_version;
1232 struct drv_func_mb {
1235 #define DRV_MSG_CODE_MASK 0xffff0000
1236 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1237 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1238 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1239 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1240 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1241 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1242 #define DRV_MSG_CODE_DCC_OK 0x30000000
1243 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1244 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1245 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1246 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1247 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1248 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1249 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1250 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1252 * The optic module verification command requires bootcode
1253 * v5.0.6 or later, te specific optic module verification command
1254 * requires bootcode v5.2.12 or later
1256 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1257 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1258 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1259 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1260 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
1261 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
1262 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1263 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201
1264 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1265 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209
1267 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1268 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1269 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401
1271 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1273 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
1274 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
1275 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
1276 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
1277 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
1279 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1280 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1282 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000
1284 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1285 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1286 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1288 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1290 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1291 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1293 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1294 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1295 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1296 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1298 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1301 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1302 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1304 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002
1306 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a
1308 #define FW_MSG_CODE_MASK 0xffff0000
1309 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1310 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1311 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1312 /* Load common chip is supported from bc 6.0.0 */
1313 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1314 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1316 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1317 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1318 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1319 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1320 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1321 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1322 #define FW_MSG_CODE_DCC_DONE 0x30100000
1323 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1324 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1325 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1326 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1327 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1328 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1329 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1330 #define FW_MSG_CODE_NO_KEY 0x80f00000
1331 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1332 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1333 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1334 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1335 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1336 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1337 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1338 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1339 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1340 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1341 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
1343 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
1344 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
1345 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
1346 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
1347 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
1349 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1350 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1352 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000
1354 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1355 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1357 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1359 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1360 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1361 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1362 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1364 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1369 #define DRV_PULSE_SEQ_MASK 0x00007fff
1370 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1372 * The system time is in the format of
1373 * (year-2001)*12*32 + month*32 + day.
1375 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1377 * Indicate to the firmware not to go into the
1378 * OS-absent when it is not getting driver pulse.
1379 * This is used for debugging as well for PXE(MBA).
1383 #define MCP_PULSE_SEQ_MASK 0x00007fff
1384 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1385 /* Indicates to the driver not to assert due to lack
1386 * of MCP response */
1387 #define MCP_EVENT_MASK 0xffff0000
1388 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1390 u32 iscsi_boot_signature;
1391 u32 iscsi_boot_block_offset;
1394 #define DRV_STATUS_PMF 0x00000001
1395 #define DRV_STATUS_VF_DISABLED 0x00000002
1396 #define DRV_STATUS_SET_MF_BW 0x00000004
1397 #define DRV_STATUS_LINK_EVENT 0x00000008
1399 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1400 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1401 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1402 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1403 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1404 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1405 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1407 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1408 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1409 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
1410 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
1411 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
1412 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
1413 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
1415 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1417 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000
1420 #define VIRT_MAC_SIGN_MASK 0xffff0000
1421 #define VIRT_MAC_SIGNATURE 0x564d0000
1427 /****************************************************************************
1428 * Management firmware state *
1429 ****************************************************************************/
1430 /* Allocate 440 bytes for management firmware */
1431 #define MGMTFW_STATE_WORD_SIZE 110
1433 struct mgmtfw_state {
1434 u32 opaque[MGMTFW_STATE_WORD_SIZE];
1438 /****************************************************************************
1439 * Multi-Function configuration *
1440 ****************************************************************************/
1441 struct shared_mf_cfg {
1444 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1446 #define SHARED_MF_CLP_EXIT 0x00000001
1448 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1452 struct port_mf_cfg {
1454 u32 dynamic_cfg; /* device control channel */
1455 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1456 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1457 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1463 struct func_mf_cfg {
1467 /* function 0 of each port cannot be hidden */
1468 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1470 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1471 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1472 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1473 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1474 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1475 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1476 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1478 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1479 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1482 /* 0 - low priority, 3 - high priority */
1483 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1484 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1485 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1488 /* value range - 0..100, increments in 100Mbps */
1489 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1490 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1491 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1492 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1493 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1494 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1496 u32 mac_upper; /* MAC */
1497 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1498 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1499 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1501 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1503 u32 e1hov_tag; /* VNI */
1504 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1505 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1506 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1508 /* afex default VLAN ID - 12 bits */
1509 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
1510 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16
1513 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
1514 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
1515 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
1516 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8
1517 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
1518 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
1519 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16
1524 enum mf_cfg_afex_vlan_mode {
1525 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1526 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1527 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1530 /* This structure is not applicable and should not be accessed on 57711 */
1531 struct func_ext_cfg {
1533 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F
1534 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1535 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1536 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1537 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1538 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1539 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080
1541 u32 iscsi_mac_addr_upper;
1542 u32 iscsi_mac_addr_lower;
1544 u32 fcoe_mac_addr_upper;
1545 u32 fcoe_mac_addr_lower;
1547 u32 fcoe_wwn_port_name_upper;
1548 u32 fcoe_wwn_port_name_lower;
1550 u32 fcoe_wwn_node_name_upper;
1551 u32 fcoe_wwn_node_name_lower;
1554 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1555 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1556 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1557 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1558 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1559 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
1564 struct shared_mf_cfg shared_mf_config; /* 0x4 */
1566 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX];
1567 /* for all chips, there are 8 mf functions */
1568 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1570 * Extended configuration per function - this array does not exist and
1571 * should not be accessed on 57711
1573 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1576 /****************************************************************************
1577 * Shared Memory Region *
1578 ****************************************************************************/
1579 struct shmem_region { /* SharedMem Offset (size) */
1581 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
1582 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1583 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1585 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1586 #define SHR_MEM_VALIDITY_MB 0x00200000
1587 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1588 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1589 /* One licensing bit should be set */
1590 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1591 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1592 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1593 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1595 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1596 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1597 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1598 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1599 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1600 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1602 struct shm_dev_info dev_info; /* 0x8 (0x438) */
1604 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1606 /* FW information (for internal FW use) */
1607 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
1608 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
1610 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
1613 /* This is a variable length array */
1614 /* the number of function depends on the chip type */
1615 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1617 /* the number of function depends on the chip type */
1618 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1621 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1623 /****************************************************************************
1624 * Shared Memory 2 Region *
1625 ****************************************************************************/
1626 /* The fw_flr_ack is actually built in the following way: */
1628 /* 64 bit: VF ack */
1629 /* 8 bit: ios_dis_ack */
1630 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1631 /* u32. The fw must have the VF right after the PF since this is how it */
1632 /* access arrays(it expects always the VF to reside after the PF, and that */
1633 /* makes the calculation much easier for it. ) */
1634 /* In order to answer both limitations, and keep the struct small, the code */
1635 /* will abuse the structure defined here to achieve the actual partition */
1637 /****************************************************************************/
1647 struct fw_flr_ack ack;
1650 struct eee_remote_vals {
1655 /**** SUPPORT FOR SHMEM ARRRAYS ***
1656 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1657 * define arrays with storage types smaller then unsigned dwords.
1658 * The macros below add generic support for SHMEM arrays with numeric elements
1659 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1660 * array with individual bit-filed elements accessed using shifts and masks.
1664 /* eb is the bitwidth of a single element */
1665 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1666 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1668 /* the bit-position macro allows the used to flip the order of the arrays
1669 * elements on a per byte or word boundary.
1671 * example: an array with 8 entries each 4 bit wide. This array will fit into
1672 * a single dword. The diagrmas below show the array order of the nibbles.
1674 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1677 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1680 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1683 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
1686 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1689 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
1692 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1693 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1694 (((i)%((fb)/(eb))) * (eb)))
1696 #define SHMEM_ARRAY_GET(a, i, eb, fb) \
1697 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1698 SHMEM_ARRAY_MASK(eb))
1700 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1702 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1703 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1704 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1705 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1709 /****START OF DCBX STRUCTURES DECLARATIONS****/
1710 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1711 #define DCBX_PRI_PG_BITWIDTH 4
1712 #define DCBX_PRI_PG_FBITS 8
1713 #define DCBX_PRI_PG_GET(a, i) \
1714 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1715 #define DCBX_PRI_PG_SET(a, i, val) \
1716 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1717 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1718 #define DCBX_BW_PG_BITWIDTH 8
1719 #define DCBX_PG_BW_GET(a, i) \
1720 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1721 #define DCBX_PG_BW_SET(a, i, val) \
1722 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1723 #define DCBX_STRICT_PRI_PG 15
1724 #define DCBX_MAX_APP_PROTOCOL 16
1725 #define FCOE_APP_IDX 0
1726 #define ISCSI_APP_IDX 1
1727 #define PREDEFINED_APP_IDX_MAX 2
1730 /* Big/Little endian have the same representation. */
1731 struct dcbx_ets_feature {
1733 * For Admin MIB - is this feature supported by the
1734 * driver | For Local MIB - should this feature be enabled.
1741 /* Driver structure in LE */
1742 struct dcbx_pfc_feature {
1745 #define DCBX_PFC_PRI_0 0x01
1746 #define DCBX_PFC_PRI_1 0x02
1747 #define DCBX_PFC_PRI_2 0x04
1748 #define DCBX_PFC_PRI_3 0x08
1749 #define DCBX_PFC_PRI_4 0x10
1750 #define DCBX_PFC_PRI_5 0x20
1751 #define DCBX_PFC_PRI_6 0x40
1752 #define DCBX_PFC_PRI_7 0x80
1756 #elif defined(__LITTLE_ENDIAN)
1761 #define DCBX_PFC_PRI_0 0x01
1762 #define DCBX_PFC_PRI_1 0x02
1763 #define DCBX_PFC_PRI_2 0x04
1764 #define DCBX_PFC_PRI_3 0x08
1765 #define DCBX_PFC_PRI_4 0x10
1766 #define DCBX_PFC_PRI_5 0x20
1767 #define DCBX_PFC_PRI_6 0x40
1768 #define DCBX_PFC_PRI_7 0x80
1772 struct dcbx_app_priority_entry {
1777 #define DCBX_APP_ENTRY_VALID 0x01
1778 #define DCBX_APP_ENTRY_SF_MASK 0x30
1779 #define DCBX_APP_ENTRY_SF_SHIFT 4
1780 #define DCBX_APP_SF_ETH_TYPE 0x10
1781 #define DCBX_APP_SF_PORT 0x20
1782 #elif defined(__LITTLE_ENDIAN)
1784 #define DCBX_APP_ENTRY_VALID 0x01
1785 #define DCBX_APP_ENTRY_SF_MASK 0x30
1786 #define DCBX_APP_ENTRY_SF_SHIFT 4
1787 #define DCBX_APP_SF_ETH_TYPE 0x10
1788 #define DCBX_APP_SF_PORT 0x20
1795 /* FW structure in BE */
1796 struct dcbx_app_priority_feature {
1802 #elif defined(__LITTLE_ENDIAN)
1808 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1811 /* FW structure in BE */
1812 struct dcbx_features {
1814 struct dcbx_ets_feature ets;
1816 struct dcbx_pfc_feature pfc;
1818 struct dcbx_app_priority_feature app;
1821 /* LLDP protocol parameters */
1822 /* FW structure in BE */
1823 struct lldp_params {
1825 u8 msg_fast_tx_interval;
1829 #define LLDP_TX_ONLY 0x01
1830 #define LLDP_RX_ONLY 0x02
1831 #define LLDP_TX_RX 0x03
1832 #define LLDP_DISABLED 0x04
1837 #elif defined(__LITTLE_ENDIAN)
1839 #define LLDP_TX_ONLY 0x01
1840 #define LLDP_RX_ONLY 0x02
1841 #define LLDP_TX_RX 0x03
1842 #define LLDP_DISABLED 0x04
1845 u8 msg_fast_tx_interval;
1851 #define REM_CHASSIS_ID_STAT_LEN 4
1852 #define REM_PORT_ID_STAT_LEN 4
1853 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1854 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1855 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
1856 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1859 struct lldp_dcbx_stat {
1860 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1861 #define LOCAL_PORT_ID_STAT_LEN 2
1862 /* Holds local Chassis ID 8B payload of constant subtype 4. */
1863 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1864 /* Holds local Port ID 8B payload of constant subtype 3. */
1865 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1866 /* Number of DCBX frames transmitted. */
1867 u32 num_tx_dcbx_pkts;
1868 /* Number of DCBX frames received. */
1869 u32 num_rx_dcbx_pkts;
1872 /* ADMIN MIB - DCBX local machine default configuration. */
1873 struct lldp_admin_mib {
1875 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1876 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1877 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1878 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1879 #define DCBX_ETS_RECO_VALID 0x00000010
1880 #define DCBX_ETS_WILLING 0x00000020
1881 #define DCBX_PFC_WILLING 0x00000040
1882 #define DCBX_APP_WILLING 0x00000080
1883 #define DCBX_VERSION_CEE 0x00000100
1884 #define DCBX_VERSION_IEEE 0x00000200
1885 #define DCBX_DCBX_ENABLED 0x00000400
1886 #define DCBX_CEE_VERSION_MASK 0x0000f000
1887 #define DCBX_CEE_VERSION_SHIFT 12
1888 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1889 #define DCBX_CEE_MAX_VERSION_SHIFT 16
1890 struct dcbx_features features;
1893 /* REMOTE MIB - remote machine DCBX configuration. */
1894 struct lldp_remote_mib {
1897 #define DCBX_ETS_TLV_RX 0x00000001
1898 #define DCBX_PFC_TLV_RX 0x00000002
1899 #define DCBX_APP_TLV_RX 0x00000004
1900 #define DCBX_ETS_RX_ERROR 0x00000010
1901 #define DCBX_PFC_RX_ERROR 0x00000020
1902 #define DCBX_APP_RX_ERROR 0x00000040
1903 #define DCBX_ETS_REM_WILLING 0x00000100
1904 #define DCBX_PFC_REM_WILLING 0x00000200
1905 #define DCBX_APP_REM_WILLING 0x00000400
1906 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1907 #define DCBX_REMOTE_MIB_VALID 0x00002000
1908 struct dcbx_features features;
1912 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1913 struct lldp_local_mib {
1915 /* Indicates if there is mismatch with negotiation results. */
1917 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1918 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1919 #define DCBX_LOCAL_APP_ERROR 0x00000004
1920 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1921 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1922 #define DCBX_REMOTE_MIB_ERROR 0x00000040
1923 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
1924 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
1925 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
1926 struct dcbx_features features;
1929 /***END OF DCBX STRUCTURES DECLARATIONS***/
1931 /***********************************************************/
1933 /***********************************************************/
1934 #define SHMEM_LINK_CONFIG_SIZE 2
1937 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff
1938 #define REQ_DUPLEX_PHY0_SHIFT 0
1939 #define REQ_DUPLEX_PHY1_MASK 0xffff0000
1940 #define REQ_DUPLEX_PHY1_SHIFT 16
1942 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff
1943 #define REQ_FLOW_CTRL_PHY0_SHIFT 0
1944 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000
1945 #define REQ_FLOW_CTRL_PHY1_SHIFT 16
1946 u32 req_line_speed; /* Also determine AutoNeg */
1947 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff
1948 #define REQ_LINE_SPD_PHY0_SHIFT 0
1949 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000
1950 #define REQ_LINE_SPD_PHY1_SHIFT 16
1951 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
1952 u32 additional_config;
1953 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff
1954 #define REQ_FC_AUTO_ADV0_SHIFT 0
1955 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000
1957 #define LFA_LINK_FLAP_REASON_OFFSET 0
1958 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
1959 #define LFA_LINK_DOWN 0x1
1960 #define LFA_LOOPBACK_ENABLED 0x2
1961 #define LFA_DUPLEX_MISMATCH 0x3
1962 #define LFA_MFW_IS_TOO_OLD 0x4
1963 #define LFA_LINK_SPEED_MISMATCH 0x5
1964 #define LFA_FLOW_CTRL_MISMATCH 0x6
1965 #define LFA_SPEED_CAP_MISMATCH 0x7
1966 #define LFA_DCC_LFA_DISABLED 0x8
1967 #define LFA_EEE_MISMATCH 0x9
1969 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
1970 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
1972 #define LINK_FLAP_COUNT_OFFSET 16
1973 #define LINK_FLAP_COUNT_MASK 0x00ff0000
1975 #define LFA_FLAGS_MASK 0xff000000
1976 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24)
1979 struct ncsi_oem_fcoe_features {
1981 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF
1982 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0
1984 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000
1985 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16
1988 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF
1989 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0
1991 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000
1992 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16
1995 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF
1996 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0
1998 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000
1999 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16
2002 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F
2003 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
2006 struct ncsi_oem_data {
2007 u32 driver_version[4];
2008 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
2011 struct shmem2_region {
2013 u32 size; /* 0x0000 */
2015 u32 dcc_support; /* 0x0004 */
2016 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
2017 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
2018 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
2019 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
2020 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
2021 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
2023 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */
2025 * For backwards compatibility, if the mf_cfg_addr does not exist
2026 * (the size filed is smaller than 0xc) the mf_cfg resides at the
2027 * end of struct shmem_region
2029 u32 mf_cfg_addr; /* 0x0010 */
2030 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
2032 struct fw_flr_mb flr_mb; /* 0x0014 */
2033 u32 dcbx_lldp_params_offset; /* 0x0028 */
2034 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
2035 u32 dcbx_neg_res_offset; /* 0x002c */
2036 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
2037 u32 dcbx_remote_mib_offset; /* 0x0030 */
2038 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
2040 * The other shmemX_base_addr holds the other path's shmem address
2041 * required for example in case of common phy init, or for path1 to know
2042 * the address of mcp debug trace which is located in offset from shmem
2045 u32 other_shmem_base_addr; /* 0x0034 */
2046 u32 other_shmem2_base_addr; /* 0x0038 */
2048 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
2049 * which were disabled/flred
2051 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */
2054 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
2057 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2059 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */
2060 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
2063 * edebug_driver_if field is used to transfer messages between edebug
2064 * app to the driver through shmem2.
2067 * bits 0-2 - function number / instance of driver to perform request
2068 * bits 3-5 - op code / is_ack?
2071 u32 edebug_driver_if[2]; /* 0x0068 */
2072 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
2073 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
2074 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
2076 u32 nvm_retain_bitmap_addr; /* 0x0070 */
2078 /* afex support of that driver */
2079 u32 afex_driver_support; /* 0x0074 */
2080 #define SHMEM_AFEX_VERSION_MASK 0x100f
2081 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
2082 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
2084 /* driver receives addr in scratchpad to which it should respond */
2085 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2087 /* generic params from MCP to driver (value depends on the msg sent
2090 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */
2091 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */
2093 u32 swim_base_addr; /* 0x0108 */
2097 /* bitmap notifying which VIF profiles stored in nvram are enabled by
2100 u32 afex_profiles_enabled[2];
2102 /* generic flags controlled by the driver */
2104 #define DRV_FLAGS_DCB_CONFIGURED 0x0
2105 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
2106 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
2108 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \
2109 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
2110 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
2111 /* pointer to extended dev_info shared data copied from nvm image */
2112 u32 extended_dev_info_shared_addr;
2113 u32 ncsi_oem_data_addr;
2115 u32 ocsd_host_addr; /* initialized by option ROM */
2116 u32 ocbb_host_addr; /* initialized by option ROM */
2117 u32 ocsd_req_update_interval; /* initialized by option ROM */
2118 u32 temperature_in_half_celsius;
2119 u32 glob_struct_in_host;
2121 u32 dcbx_neg_res_ext_offset;
2122 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
2124 u32 drv_capabilities_flag[E2_FUNC_MAX];
2125 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2126 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
2127 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
2128 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
2130 u32 extended_dev_info_shared_cfg_size;
2132 u32 dcbx_en[PORT_MAX];
2134 /* The offset points to the multi threaded meta structure */
2135 u32 multi_thread_data_offset;
2137 /* address of DMAable host address holding values from the drivers */
2138 u32 drv_info_host_addr_lo;
2139 u32 drv_info_host_addr_hi;
2141 /* general values written by the MFW (such as current version) */
2142 u32 drv_info_control;
2143 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff
2144 #define DRV_INFO_CONTROL_VER_SHIFT 0
2145 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2146 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
2147 u32 ibft_host_addr; /* initialized by option ROM */
2148 struct eee_remote_vals eee_remote_vals[PORT_MAX];
2149 u32 reserved[E2_FUNC_MAX];
2152 /* the status of EEE auto-negotiation
2153 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2154 * bits 19:16 the supported modes for EEE.
2155 * bits 23:20 the speeds advertised for EEE.
2156 * bits 27:24 the speeds the Link partner advertised for EEE.
2157 * The supported/adv. modes in bits 27:19 originate from the
2158 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2159 * bit 28 when 1'b1 EEE was requested.
2160 * bit 29 when 1'b1 tx lpi was requested.
2161 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
2163 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2164 * value. When 1'b1 those bits contains a value times 16 microseconds.
2166 u32 eee_status[PORT_MAX];
2167 #define SHMEM_EEE_TIMER_MASK 0x0000ffff
2168 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
2169 #define SHMEM_EEE_SUPPORTED_SHIFT 16
2170 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
2171 #define SHMEM_EEE_100M_ADV (1<<0)
2172 #define SHMEM_EEE_1G_ADV (1<<1)
2173 #define SHMEM_EEE_10G_ADV (1<<2)
2174 #define SHMEM_EEE_ADV_STATUS_SHIFT 20
2175 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
2176 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24
2177 #define SHMEM_EEE_REQUESTED_BIT 0x10000000
2178 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000
2179 #define SHMEM_EEE_ACTIVE_BIT 0x40000000
2180 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
2182 u32 sizeof_port_stats;
2184 /* Link Flap Avoidance */
2185 u32 lfa_host_addr[PORT_MAX];
2188 u32 reserved2; /* Offset 0x148 */
2189 u32 reserved3; /* Offset 0x14C */
2190 u32 reserved4; /* Offset 0x150 */
2191 u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */
2192 #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0)
2197 u32 rx_stat_ifhcinoctets;
2198 u32 rx_stat_ifhcinbadoctets;
2199 u32 rx_stat_etherstatsfragments;
2200 u32 rx_stat_ifhcinucastpkts;
2201 u32 rx_stat_ifhcinmulticastpkts;
2202 u32 rx_stat_ifhcinbroadcastpkts;
2203 u32 rx_stat_dot3statsfcserrors;
2204 u32 rx_stat_dot3statsalignmenterrors;
2205 u32 rx_stat_dot3statscarriersenseerrors;
2206 u32 rx_stat_xonpauseframesreceived;
2207 u32 rx_stat_xoffpauseframesreceived;
2208 u32 rx_stat_maccontrolframesreceived;
2209 u32 rx_stat_xoffstateentered;
2210 u32 rx_stat_dot3statsframestoolong;
2211 u32 rx_stat_etherstatsjabbers;
2212 u32 rx_stat_etherstatsundersizepkts;
2213 u32 rx_stat_etherstatspkts64octets;
2214 u32 rx_stat_etherstatspkts65octetsto127octets;
2215 u32 rx_stat_etherstatspkts128octetsto255octets;
2216 u32 rx_stat_etherstatspkts256octetsto511octets;
2217 u32 rx_stat_etherstatspkts512octetsto1023octets;
2218 u32 rx_stat_etherstatspkts1024octetsto1522octets;
2219 u32 rx_stat_etherstatspktsover1522octets;
2221 u32 rx_stat_falsecarriererrors;
2223 u32 tx_stat_ifhcoutoctets;
2224 u32 tx_stat_ifhcoutbadoctets;
2225 u32 tx_stat_etherstatscollisions;
2226 u32 tx_stat_outxonsent;
2227 u32 tx_stat_outxoffsent;
2228 u32 tx_stat_flowcontroldone;
2229 u32 tx_stat_dot3statssinglecollisionframes;
2230 u32 tx_stat_dot3statsmultiplecollisionframes;
2231 u32 tx_stat_dot3statsdeferredtransmissions;
2232 u32 tx_stat_dot3statsexcessivecollisions;
2233 u32 tx_stat_dot3statslatecollisions;
2234 u32 tx_stat_ifhcoutucastpkts;
2235 u32 tx_stat_ifhcoutmulticastpkts;
2236 u32 tx_stat_ifhcoutbroadcastpkts;
2237 u32 tx_stat_etherstatspkts64octets;
2238 u32 tx_stat_etherstatspkts65octetsto127octets;
2239 u32 tx_stat_etherstatspkts128octetsto255octets;
2240 u32 tx_stat_etherstatspkts256octetsto511octets;
2241 u32 tx_stat_etherstatspkts512octetsto1023octets;
2242 u32 tx_stat_etherstatspkts1024octetsto1522octets;
2243 u32 tx_stat_etherstatspktsover1522octets;
2244 u32 tx_stat_dot3statsinternalmactransmiterrors;
2248 struct bmac1_stats {
2249 u32 tx_stat_gtpkt_lo;
2250 u32 tx_stat_gtpkt_hi;
2251 u32 tx_stat_gtxpf_lo;
2252 u32 tx_stat_gtxpf_hi;
2253 u32 tx_stat_gtfcs_lo;
2254 u32 tx_stat_gtfcs_hi;
2255 u32 tx_stat_gtmca_lo;
2256 u32 tx_stat_gtmca_hi;
2257 u32 tx_stat_gtbca_lo;
2258 u32 tx_stat_gtbca_hi;
2259 u32 tx_stat_gtfrg_lo;
2260 u32 tx_stat_gtfrg_hi;
2261 u32 tx_stat_gtovr_lo;
2262 u32 tx_stat_gtovr_hi;
2263 u32 tx_stat_gt64_lo;
2264 u32 tx_stat_gt64_hi;
2265 u32 tx_stat_gt127_lo;
2266 u32 tx_stat_gt127_hi;
2267 u32 tx_stat_gt255_lo;
2268 u32 tx_stat_gt255_hi;
2269 u32 tx_stat_gt511_lo;
2270 u32 tx_stat_gt511_hi;
2271 u32 tx_stat_gt1023_lo;
2272 u32 tx_stat_gt1023_hi;
2273 u32 tx_stat_gt1518_lo;
2274 u32 tx_stat_gt1518_hi;
2275 u32 tx_stat_gt2047_lo;
2276 u32 tx_stat_gt2047_hi;
2277 u32 tx_stat_gt4095_lo;
2278 u32 tx_stat_gt4095_hi;
2279 u32 tx_stat_gt9216_lo;
2280 u32 tx_stat_gt9216_hi;
2281 u32 tx_stat_gt16383_lo;
2282 u32 tx_stat_gt16383_hi;
2283 u32 tx_stat_gtmax_lo;
2284 u32 tx_stat_gtmax_hi;
2285 u32 tx_stat_gtufl_lo;
2286 u32 tx_stat_gtufl_hi;
2287 u32 tx_stat_gterr_lo;
2288 u32 tx_stat_gterr_hi;
2289 u32 tx_stat_gtbyt_lo;
2290 u32 tx_stat_gtbyt_hi;
2292 u32 rx_stat_gr64_lo;
2293 u32 rx_stat_gr64_hi;
2294 u32 rx_stat_gr127_lo;
2295 u32 rx_stat_gr127_hi;
2296 u32 rx_stat_gr255_lo;
2297 u32 rx_stat_gr255_hi;
2298 u32 rx_stat_gr511_lo;
2299 u32 rx_stat_gr511_hi;
2300 u32 rx_stat_gr1023_lo;
2301 u32 rx_stat_gr1023_hi;
2302 u32 rx_stat_gr1518_lo;
2303 u32 rx_stat_gr1518_hi;
2304 u32 rx_stat_gr2047_lo;
2305 u32 rx_stat_gr2047_hi;
2306 u32 rx_stat_gr4095_lo;
2307 u32 rx_stat_gr4095_hi;
2308 u32 rx_stat_gr9216_lo;
2309 u32 rx_stat_gr9216_hi;
2310 u32 rx_stat_gr16383_lo;
2311 u32 rx_stat_gr16383_hi;
2312 u32 rx_stat_grmax_lo;
2313 u32 rx_stat_grmax_hi;
2314 u32 rx_stat_grpkt_lo;
2315 u32 rx_stat_grpkt_hi;
2316 u32 rx_stat_grfcs_lo;
2317 u32 rx_stat_grfcs_hi;
2318 u32 rx_stat_grmca_lo;
2319 u32 rx_stat_grmca_hi;
2320 u32 rx_stat_grbca_lo;
2321 u32 rx_stat_grbca_hi;
2322 u32 rx_stat_grxcf_lo;
2323 u32 rx_stat_grxcf_hi;
2324 u32 rx_stat_grxpf_lo;
2325 u32 rx_stat_grxpf_hi;
2326 u32 rx_stat_grxuo_lo;
2327 u32 rx_stat_grxuo_hi;
2328 u32 rx_stat_grjbr_lo;
2329 u32 rx_stat_grjbr_hi;
2330 u32 rx_stat_grovr_lo;
2331 u32 rx_stat_grovr_hi;
2332 u32 rx_stat_grflr_lo;
2333 u32 rx_stat_grflr_hi;
2334 u32 rx_stat_grmeg_lo;
2335 u32 rx_stat_grmeg_hi;
2336 u32 rx_stat_grmeb_lo;
2337 u32 rx_stat_grmeb_hi;
2338 u32 rx_stat_grbyt_lo;
2339 u32 rx_stat_grbyt_hi;
2340 u32 rx_stat_grund_lo;
2341 u32 rx_stat_grund_hi;
2342 u32 rx_stat_grfrg_lo;
2343 u32 rx_stat_grfrg_hi;
2344 u32 rx_stat_grerb_lo;
2345 u32 rx_stat_grerb_hi;
2346 u32 rx_stat_grfre_lo;
2347 u32 rx_stat_grfre_hi;
2348 u32 rx_stat_gripj_lo;
2349 u32 rx_stat_gripj_hi;
2352 struct bmac2_stats {
2353 u32 tx_stat_gtpk_lo; /* gtpok */
2354 u32 tx_stat_gtpk_hi; /* gtpok */
2355 u32 tx_stat_gtxpf_lo; /* gtpf */
2356 u32 tx_stat_gtxpf_hi; /* gtpf */
2357 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */
2358 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */
2359 u32 tx_stat_gtfcs_lo;
2360 u32 tx_stat_gtfcs_hi;
2361 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */
2362 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */
2363 u32 tx_stat_gtmca_lo;
2364 u32 tx_stat_gtmca_hi;
2365 u32 tx_stat_gtbca_lo;
2366 u32 tx_stat_gtbca_hi;
2367 u32 tx_stat_gtovr_lo;
2368 u32 tx_stat_gtovr_hi;
2369 u32 tx_stat_gtfrg_lo;
2370 u32 tx_stat_gtfrg_hi;
2371 u32 tx_stat_gtpkt1_lo; /* gtpkt */
2372 u32 tx_stat_gtpkt1_hi; /* gtpkt */
2373 u32 tx_stat_gt64_lo;
2374 u32 tx_stat_gt64_hi;
2375 u32 tx_stat_gt127_lo;
2376 u32 tx_stat_gt127_hi;
2377 u32 tx_stat_gt255_lo;
2378 u32 tx_stat_gt255_hi;
2379 u32 tx_stat_gt511_lo;
2380 u32 tx_stat_gt511_hi;
2381 u32 tx_stat_gt1023_lo;
2382 u32 tx_stat_gt1023_hi;
2383 u32 tx_stat_gt1518_lo;
2384 u32 tx_stat_gt1518_hi;
2385 u32 tx_stat_gt2047_lo;
2386 u32 tx_stat_gt2047_hi;
2387 u32 tx_stat_gt4095_lo;
2388 u32 tx_stat_gt4095_hi;
2389 u32 tx_stat_gt9216_lo;
2390 u32 tx_stat_gt9216_hi;
2391 u32 tx_stat_gt16383_lo;
2392 u32 tx_stat_gt16383_hi;
2393 u32 tx_stat_gtmax_lo;
2394 u32 tx_stat_gtmax_hi;
2395 u32 tx_stat_gtufl_lo;
2396 u32 tx_stat_gtufl_hi;
2397 u32 tx_stat_gterr_lo;
2398 u32 tx_stat_gterr_hi;
2399 u32 tx_stat_gtbyt_lo;
2400 u32 tx_stat_gtbyt_hi;
2402 u32 rx_stat_gr64_lo;
2403 u32 rx_stat_gr64_hi;
2404 u32 rx_stat_gr127_lo;
2405 u32 rx_stat_gr127_hi;
2406 u32 rx_stat_gr255_lo;
2407 u32 rx_stat_gr255_hi;
2408 u32 rx_stat_gr511_lo;
2409 u32 rx_stat_gr511_hi;
2410 u32 rx_stat_gr1023_lo;
2411 u32 rx_stat_gr1023_hi;
2412 u32 rx_stat_gr1518_lo;
2413 u32 rx_stat_gr1518_hi;
2414 u32 rx_stat_gr2047_lo;
2415 u32 rx_stat_gr2047_hi;
2416 u32 rx_stat_gr4095_lo;
2417 u32 rx_stat_gr4095_hi;
2418 u32 rx_stat_gr9216_lo;
2419 u32 rx_stat_gr9216_hi;
2420 u32 rx_stat_gr16383_lo;
2421 u32 rx_stat_gr16383_hi;
2422 u32 rx_stat_grmax_lo;
2423 u32 rx_stat_grmax_hi;
2424 u32 rx_stat_grpkt_lo;
2425 u32 rx_stat_grpkt_hi;
2426 u32 rx_stat_grfcs_lo;
2427 u32 rx_stat_grfcs_hi;
2428 u32 rx_stat_gruca_lo;
2429 u32 rx_stat_gruca_hi;
2430 u32 rx_stat_grmca_lo;
2431 u32 rx_stat_grmca_hi;
2432 u32 rx_stat_grbca_lo;
2433 u32 rx_stat_grbca_hi;
2434 u32 rx_stat_grxpf_lo; /* grpf */
2435 u32 rx_stat_grxpf_hi; /* grpf */
2436 u32 rx_stat_grpp_lo;
2437 u32 rx_stat_grpp_hi;
2438 u32 rx_stat_grxuo_lo; /* gruo */
2439 u32 rx_stat_grxuo_hi; /* gruo */
2440 u32 rx_stat_grjbr_lo;
2441 u32 rx_stat_grjbr_hi;
2442 u32 rx_stat_grovr_lo;
2443 u32 rx_stat_grovr_hi;
2444 u32 rx_stat_grxcf_lo; /* grcf */
2445 u32 rx_stat_grxcf_hi; /* grcf */
2446 u32 rx_stat_grflr_lo;
2447 u32 rx_stat_grflr_hi;
2448 u32 rx_stat_grpok_lo;
2449 u32 rx_stat_grpok_hi;
2450 u32 rx_stat_grmeg_lo;
2451 u32 rx_stat_grmeg_hi;
2452 u32 rx_stat_grmeb_lo;
2453 u32 rx_stat_grmeb_hi;
2454 u32 rx_stat_grbyt_lo;
2455 u32 rx_stat_grbyt_hi;
2456 u32 rx_stat_grund_lo;
2457 u32 rx_stat_grund_hi;
2458 u32 rx_stat_grfrg_lo;
2459 u32 rx_stat_grfrg_hi;
2460 u32 rx_stat_grerb_lo; /* grerrbyt */
2461 u32 rx_stat_grerb_hi; /* grerrbyt */
2462 u32 rx_stat_grfre_lo; /* grfrerr */
2463 u32 rx_stat_grfre_hi; /* grfrerr */
2464 u32 rx_stat_gripj_lo;
2465 u32 rx_stat_gripj_hi;
2468 struct mstat_stats {
2470 /* OTE MSTAT on E3 has a bug where this register's contents are
2471 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2515 u32 tx_collisions_lo;
2516 u32 tx_collisions_hi;
2517 u32 tx_singlecollision_lo;
2518 u32 tx_singlecollision_hi;
2519 u32 tx_multiplecollisions_lo;
2520 u32 tx_multiplecollisions_hi;
2523 u32 tx_excessivecollisions_lo;
2524 u32 tx_excessivecollisions_hi;
2525 u32 tx_latecollisions_lo;
2526 u32 tx_latecollisions_hi;
2585 u32 rx_alignmenterrors_lo;
2586 u32 rx_alignmenterrors_hi;
2587 u32 rx_falsecarrier_lo;
2588 u32 rx_falsecarrier_hi;
2589 u32 rx_llfcmsgcnt_lo;
2590 u32 rx_llfcmsgcnt_hi;
2595 struct emac_stats emac_stats;
2596 struct bmac1_stats bmac1_stats;
2597 struct bmac2_stats bmac2_stats;
2598 struct mstat_stats mstat_stats;
2604 u32 rx_stat_ifhcinbadoctets_hi;
2605 u32 rx_stat_ifhcinbadoctets_lo;
2607 /* out_bad_octets */
2608 u32 tx_stat_ifhcoutbadoctets_hi;
2609 u32 tx_stat_ifhcoutbadoctets_lo;
2611 /* crc_receive_errors */
2612 u32 rx_stat_dot3statsfcserrors_hi;
2613 u32 rx_stat_dot3statsfcserrors_lo;
2614 /* alignment_errors */
2615 u32 rx_stat_dot3statsalignmenterrors_hi;
2616 u32 rx_stat_dot3statsalignmenterrors_lo;
2617 /* carrier_sense_errors */
2618 u32 rx_stat_dot3statscarriersenseerrors_hi;
2619 u32 rx_stat_dot3statscarriersenseerrors_lo;
2620 /* false_carrier_detections */
2621 u32 rx_stat_falsecarriererrors_hi;
2622 u32 rx_stat_falsecarriererrors_lo;
2624 /* runt_packets_received */
2625 u32 rx_stat_etherstatsundersizepkts_hi;
2626 u32 rx_stat_etherstatsundersizepkts_lo;
2627 /* jabber_packets_received */
2628 u32 rx_stat_dot3statsframestoolong_hi;
2629 u32 rx_stat_dot3statsframestoolong_lo;
2631 /* error_runt_packets_received */
2632 u32 rx_stat_etherstatsfragments_hi;
2633 u32 rx_stat_etherstatsfragments_lo;
2634 /* error_jabber_packets_received */
2635 u32 rx_stat_etherstatsjabbers_hi;
2636 u32 rx_stat_etherstatsjabbers_lo;
2638 /* control_frames_received */
2639 u32 rx_stat_maccontrolframesreceived_hi;
2640 u32 rx_stat_maccontrolframesreceived_lo;
2641 u32 rx_stat_mac_xpf_hi;
2642 u32 rx_stat_mac_xpf_lo;
2643 u32 rx_stat_mac_xcf_hi;
2644 u32 rx_stat_mac_xcf_lo;
2646 /* xoff_state_entered */
2647 u32 rx_stat_xoffstateentered_hi;
2648 u32 rx_stat_xoffstateentered_lo;
2649 /* pause_xon_frames_received */
2650 u32 rx_stat_xonpauseframesreceived_hi;
2651 u32 rx_stat_xonpauseframesreceived_lo;
2652 /* pause_xoff_frames_received */
2653 u32 rx_stat_xoffpauseframesreceived_hi;
2654 u32 rx_stat_xoffpauseframesreceived_lo;
2655 /* pause_xon_frames_transmitted */
2656 u32 tx_stat_outxonsent_hi;
2657 u32 tx_stat_outxonsent_lo;
2658 /* pause_xoff_frames_transmitted */
2659 u32 tx_stat_outxoffsent_hi;
2660 u32 tx_stat_outxoffsent_lo;
2661 /* flow_control_done */
2662 u32 tx_stat_flowcontroldone_hi;
2663 u32 tx_stat_flowcontroldone_lo;
2665 /* ether_stats_collisions */
2666 u32 tx_stat_etherstatscollisions_hi;
2667 u32 tx_stat_etherstatscollisions_lo;
2668 /* single_collision_transmit_frames */
2669 u32 tx_stat_dot3statssinglecollisionframes_hi;
2670 u32 tx_stat_dot3statssinglecollisionframes_lo;
2671 /* multiple_collision_transmit_frames */
2672 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
2673 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
2674 /* deferred_transmissions */
2675 u32 tx_stat_dot3statsdeferredtransmissions_hi;
2676 u32 tx_stat_dot3statsdeferredtransmissions_lo;
2677 /* excessive_collision_frames */
2678 u32 tx_stat_dot3statsexcessivecollisions_hi;
2679 u32 tx_stat_dot3statsexcessivecollisions_lo;
2680 /* late_collision_frames */
2681 u32 tx_stat_dot3statslatecollisions_hi;
2682 u32 tx_stat_dot3statslatecollisions_lo;
2684 /* frames_transmitted_64_bytes */
2685 u32 tx_stat_etherstatspkts64octets_hi;
2686 u32 tx_stat_etherstatspkts64octets_lo;
2687 /* frames_transmitted_65_127_bytes */
2688 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
2689 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
2690 /* frames_transmitted_128_255_bytes */
2691 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
2692 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
2693 /* frames_transmitted_256_511_bytes */
2694 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
2695 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
2696 /* frames_transmitted_512_1023_bytes */
2697 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
2698 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
2699 /* frames_transmitted_1024_1522_bytes */
2700 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
2701 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
2702 /* frames_transmitted_1523_9022_bytes */
2703 u32 tx_stat_etherstatspktsover1522octets_hi;
2704 u32 tx_stat_etherstatspktsover1522octets_lo;
2705 u32 tx_stat_mac_2047_hi;
2706 u32 tx_stat_mac_2047_lo;
2707 u32 tx_stat_mac_4095_hi;
2708 u32 tx_stat_mac_4095_lo;
2709 u32 tx_stat_mac_9216_hi;
2710 u32 tx_stat_mac_9216_lo;
2711 u32 tx_stat_mac_16383_hi;
2712 u32 tx_stat_mac_16383_lo;
2714 /* internal_mac_transmit_errors */
2715 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
2716 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
2718 /* if_out_discards */
2719 u32 tx_stat_mac_ufl_hi;
2720 u32 tx_stat_mac_ufl_lo;
2724 #define MAC_STX_IDX_MAX 2
2726 struct host_port_stats {
2727 u32 host_port_stats_counter;
2729 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2734 u32 not_used; /* obsolete */
2735 u32 pfc_frames_tx_hi;
2736 u32 pfc_frames_tx_lo;
2737 u32 pfc_frames_rx_hi;
2738 u32 pfc_frames_rx_lo;
2740 u32 eee_lpi_count_hi;
2741 u32 eee_lpi_count_lo;
2745 struct host_func_stats {
2746 u32 host_func_stats_start;
2748 u32 total_bytes_received_hi;
2749 u32 total_bytes_received_lo;
2751 u32 total_bytes_transmitted_hi;
2752 u32 total_bytes_transmitted_lo;
2754 u32 total_unicast_packets_received_hi;
2755 u32 total_unicast_packets_received_lo;
2757 u32 total_multicast_packets_received_hi;
2758 u32 total_multicast_packets_received_lo;
2760 u32 total_broadcast_packets_received_hi;
2761 u32 total_broadcast_packets_received_lo;
2763 u32 total_unicast_packets_transmitted_hi;
2764 u32 total_unicast_packets_transmitted_lo;
2766 u32 total_multicast_packets_transmitted_hi;
2767 u32 total_multicast_packets_transmitted_lo;
2769 u32 total_broadcast_packets_transmitted_hi;
2770 u32 total_broadcast_packets_transmitted_lo;
2772 u32 valid_bytes_received_hi;
2773 u32 valid_bytes_received_lo;
2775 u32 host_func_stats_end;
2778 /* VIC definitions */
2779 #define VICSTATST_UIF_INDEX 2
2782 /* stats collected for afex.
2783 * NOTE: structure is exactly as expected to be received by the switch.
2784 * order must remain exactly as is unless protocol changes !
2787 u32 tx_unicast_frames_hi;
2788 u32 tx_unicast_frames_lo;
2789 u32 tx_unicast_bytes_hi;
2790 u32 tx_unicast_bytes_lo;
2791 u32 tx_multicast_frames_hi;
2792 u32 tx_multicast_frames_lo;
2793 u32 tx_multicast_bytes_hi;
2794 u32 tx_multicast_bytes_lo;
2795 u32 tx_broadcast_frames_hi;
2796 u32 tx_broadcast_frames_lo;
2797 u32 tx_broadcast_bytes_hi;
2798 u32 tx_broadcast_bytes_lo;
2799 u32 tx_frames_discarded_hi;
2800 u32 tx_frames_discarded_lo;
2801 u32 tx_frames_dropped_hi;
2802 u32 tx_frames_dropped_lo;
2804 u32 rx_unicast_frames_hi;
2805 u32 rx_unicast_frames_lo;
2806 u32 rx_unicast_bytes_hi;
2807 u32 rx_unicast_bytes_lo;
2808 u32 rx_multicast_frames_hi;
2809 u32 rx_multicast_frames_lo;
2810 u32 rx_multicast_bytes_hi;
2811 u32 rx_multicast_bytes_lo;
2812 u32 rx_broadcast_frames_hi;
2813 u32 rx_broadcast_frames_lo;
2814 u32 rx_broadcast_bytes_hi;
2815 u32 rx_broadcast_bytes_lo;
2816 u32 rx_frames_discarded_hi;
2817 u32 rx_frames_discarded_lo;
2818 u32 rx_frames_dropped_hi;
2819 u32 rx_frames_dropped_lo;
2822 #define BCM_5710_FW_MAJOR_VERSION 7
2823 #define BCM_5710_FW_MINOR_VERSION 8
2824 #define BCM_5710_FW_REVISION_VERSION 2
2825 #define BCM_5710_FW_ENGINEERING_VERSION 0
2826 #define BCM_5710_FW_COMPILE_FLAGS 1
2832 struct atten_sp_status_block {
2834 __le32 attn_bits_ack;
2837 __le16 attn_bits_index;
2843 * The eth aggregative context of Cstorm
2845 struct cstorm_eth_ag_context {
2846 u32 __reserved0[10];
2851 * dmae command structure
2853 struct dmae_command {
2855 #define DMAE_COMMAND_SRC (0x1<<0)
2856 #define DMAE_COMMAND_SRC_SHIFT 0
2857 #define DMAE_COMMAND_DST (0x3<<1)
2858 #define DMAE_COMMAND_DST_SHIFT 1
2859 #define DMAE_COMMAND_C_DST (0x1<<3)
2860 #define DMAE_COMMAND_C_DST_SHIFT 3
2861 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2862 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2863 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2864 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2865 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2866 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2867 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2868 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2869 #define DMAE_COMMAND_PORT (0x1<<11)
2870 #define DMAE_COMMAND_PORT_SHIFT 11
2871 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2872 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2873 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2874 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2875 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2876 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2877 #define DMAE_COMMAND_E1HVN (0x3<<15)
2878 #define DMAE_COMMAND_E1HVN_SHIFT 15
2879 #define DMAE_COMMAND_DST_VN (0x3<<17)
2880 #define DMAE_COMMAND_DST_VN_SHIFT 17
2881 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2882 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2883 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2884 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2885 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2886 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2891 #if defined(__BIG_ENDIAN)
2893 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2894 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2895 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2896 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2897 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2898 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2899 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2900 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2901 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2902 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2903 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2904 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2906 #elif defined(__LITTLE_ENDIAN)
2909 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2910 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2911 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2912 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2913 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2914 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2915 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2916 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2917 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2918 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2919 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2920 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2927 #if defined(__BIG_ENDIAN)
2930 #elif defined(__LITTLE_ENDIAN)
2934 #if defined(__BIG_ENDIAN)
2937 #elif defined(__LITTLE_ENDIAN)
2941 #if defined(__BIG_ENDIAN)
2944 #elif defined(__LITTLE_ENDIAN)
2952 * common data for all protocols
2954 struct doorbell_hdr {
2956 #define DOORBELL_HDR_RX (0x1<<0)
2957 #define DOORBELL_HDR_RX_SHIFT 0
2958 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
2959 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
2960 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
2961 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
2962 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
2963 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
2969 struct eth_tx_doorbell {
2970 #if defined(__BIG_ENDIAN)
2973 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2974 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2975 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2976 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2977 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2978 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2979 struct doorbell_hdr hdr;
2980 #elif defined(__LITTLE_ENDIAN)
2981 struct doorbell_hdr hdr;
2983 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2984 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2985 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2986 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2987 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2988 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2995 * 3 lines. status block
2997 struct hc_status_block_e1x {
2998 __le16 index_values[HC_SB_MAX_INDICES_E1X];
2999 __le16 running_index[HC_SB_MAX_SM];
3006 struct host_hc_status_block_e1x {
3007 struct hc_status_block_e1x sb;
3012 * 3 lines. status block
3014 struct hc_status_block_e2 {
3015 __le16 index_values[HC_SB_MAX_INDICES_E2];
3016 __le16 running_index[HC_SB_MAX_SM];
3017 __le32 reserved[11];
3023 struct host_hc_status_block_e2 {
3024 struct hc_status_block_e2 sb;
3029 * 5 lines. slow-path status block
3031 struct hc_sp_status_block {
3032 __le16 index_values[HC_SP_SB_MAX_INDICES];
3033 __le16 running_index;
3041 struct host_sp_status_block {
3042 struct atten_sp_status_block atten_status_block;
3043 struct hc_sp_status_block sp_sb;
3048 * IGU driver acknowledgment register
3050 struct igu_ack_register {
3051 #if defined(__BIG_ENDIAN)
3052 u16 sb_id_and_flags;
3053 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3054 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3055 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3056 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3057 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3058 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3059 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3060 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3061 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3062 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3063 u16 status_block_index;
3064 #elif defined(__LITTLE_ENDIAN)
3065 u16 status_block_index;
3066 u16 sb_id_and_flags;
3067 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3068 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3069 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3070 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3071 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3072 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3073 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3074 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3075 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3076 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3082 * IGU driver acknowledgement register
3084 struct igu_backward_compatible {
3085 u32 sb_id_and_flags;
3086 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3087 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3088 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3089 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3090 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3091 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3092 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3093 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3094 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3095 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3096 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3097 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3103 * IGU driver acknowledgement register
3105 struct igu_regular {
3106 u32 sb_id_and_flags;
3107 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3108 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3109 #define IGU_REGULAR_RESERVED0 (0x1<<20)
3110 #define IGU_REGULAR_RESERVED0_SHIFT 20
3111 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
3112 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
3113 #define IGU_REGULAR_BUPDATE (0x1<<24)
3114 #define IGU_REGULAR_BUPDATE_SHIFT 24
3115 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
3116 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
3117 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
3118 #define IGU_REGULAR_RESERVED_1_SHIFT 27
3119 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
3120 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
3121 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
3122 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3123 #define IGU_REGULAR_BCLEANUP (0x1<<31)
3124 #define IGU_REGULAR_BCLEANUP_SHIFT 31
3129 * IGU driver acknowledgement register
3131 union igu_consprod_reg {
3132 struct igu_regular regular;
3133 struct igu_backward_compatible backward_compatible;
3138 * Igu control commands
3141 IGU_CTRL_CMD_TYPE_RD,
3142 IGU_CTRL_CMD_TYPE_WR,
3148 * Control register for the IGU command register
3150 struct igu_ctrl_reg {
3152 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3153 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
3154 #define IGU_CTRL_REG_FID (0x7F<<12)
3155 #define IGU_CTRL_REG_FID_SHIFT 12
3156 #define IGU_CTRL_REG_RESERVED (0x1<<19)
3157 #define IGU_CTRL_REG_RESERVED_SHIFT 19
3158 #define IGU_CTRL_REG_TYPE (0x1<<20)
3159 #define IGU_CTRL_REG_TYPE_SHIFT 20
3160 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3161 #define IGU_CTRL_REG_UNUSED_SHIFT 21
3166 * Igu interrupt command
3180 enum igu_seg_access {
3181 IGU_SEG_ACCESS_NORM,
3183 IGU_SEG_ACCESS_ATTN,
3189 * Parser parsing flags field
3191 struct parsing_flags {
3193 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3194 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3195 #define PARSING_FLAGS_VLAN (0x1<<1)
3196 #define PARSING_FLAGS_VLAN_SHIFT 1
3197 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3198 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3199 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3200 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3201 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3202 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3203 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3204 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3205 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3206 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3207 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3208 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3209 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3210 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3211 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3212 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3213 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3214 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3215 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3216 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3217 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
3218 #define PARSING_FLAGS_RESERVED0_SHIFT 14
3223 * Parsing flags for TCP ACK type
3225 enum prs_flags_ack_type {
3226 PRS_FLAG_PUREACK_PIGGY,
3227 PRS_FLAG_PUREACK_PURE,
3228 MAX_PRS_FLAGS_ACK_TYPE
3233 * Parsing flags for Ethernet address type
3235 enum prs_flags_eth_addr_type {
3236 PRS_FLAG_ETHTYPE_NON_UNICAST,
3237 PRS_FLAG_ETHTYPE_UNICAST,
3238 MAX_PRS_FLAGS_ETH_ADDR_TYPE
3243 * Parsing flags for over-ethernet protocol
3245 enum prs_flags_over_eth {
3246 PRS_FLAG_OVERETH_UNKNOWN,
3247 PRS_FLAG_OVERETH_IPV4,
3248 PRS_FLAG_OVERETH_IPV6,
3249 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
3250 MAX_PRS_FLAGS_OVER_ETH
3255 * Parsing flags for over-IP protocol
3257 enum prs_flags_over_ip {
3258 PRS_FLAG_OVERIP_UNKNOWN,
3259 PRS_FLAG_OVERIP_TCP,
3260 PRS_FLAG_OVERIP_UDP,
3261 MAX_PRS_FLAGS_OVER_IP
3266 * SDM operation gen command (generate aggregative interrupt)
3270 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3271 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3272 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3273 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3274 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3275 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3276 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3277 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3278 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3279 #define SDM_OP_GEN_RESERVED_SHIFT 17
3284 * Timers connection context
3286 struct timers_block_context {
3291 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3292 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3293 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3294 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3295 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3296 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3301 * The eth aggregative context of Tstorm
3303 struct tstorm_eth_ag_context {
3304 u32 __reserved0[14];
3309 * The eth aggregative context of Ustorm
3311 struct ustorm_eth_ag_context {
3313 #if defined(__BIG_ENDIAN)
3317 #elif defined(__LITTLE_ENDIAN)
3327 * The eth aggregative context of Xstorm
3329 struct xstorm_eth_ag_context {
3331 #if defined(__BIG_ENDIAN)
3335 #elif defined(__LITTLE_ENDIAN)
3345 * doorbell message sent to the chip
3348 #if defined(__BIG_ENDIAN)
3351 struct doorbell_hdr header;
3352 #elif defined(__LITTLE_ENDIAN)
3353 struct doorbell_hdr header;
3361 * doorbell message sent to the chip
3363 struct doorbell_set_prod {
3364 #if defined(__BIG_ENDIAN)
3367 struct doorbell_hdr header;
3368 #elif defined(__LITTLE_ENDIAN)
3369 struct doorbell_hdr header;
3381 struct regpair_native {
3387 * Classify rule opcodes in E2/E3
3389 enum classify_rule {
3390 CLASSIFY_RULE_OPCODE_MAC,
3391 CLASSIFY_RULE_OPCODE_VLAN,
3392 CLASSIFY_RULE_OPCODE_PAIR,
3398 * Classify rule types in E2/E3
3400 enum classify_rule_action_type {
3401 CLASSIFY_RULE_REMOVE,
3403 MAX_CLASSIFY_RULE_ACTION_TYPE
3408 * client init ramrod data
3410 struct client_init_general_data {
3412 u8 statistics_counter_id;
3413 u8 statistics_en_flg;
3418 u8 statistics_zero_flg;
3427 * client init rx data
3429 struct client_init_rx_data {
3431 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3432 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3433 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3434 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3435 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3436 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3437 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
3438 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3439 u8 vmqueue_mode_en_flg;
3440 u8 extra_data_over_sgl_en_flg;
3441 u8 cache_line_alignment_log_size;
3442 u8 enable_dynamic_hc;
3443 u8 max_sges_for_packet;
3445 u8 drop_ip_cs_err_flg;
3446 u8 drop_tcp_cs_err_flg;
3448 u8 drop_udp_cs_err_flg;
3449 u8 inner_vlan_removal_enable_flg;
3450 u8 outer_vlan_removal_enable_flg;
3452 u8 rx_sb_index_number;
3453 u8 dont_verify_rings_pause_thr_flg;
3455 u8 silent_vlan_removal_flg;
3456 __le16 max_bytes_on_bd;
3457 __le16 sge_buff_size;
3458 u8 approx_mcast_engine_id;
3460 struct regpair bd_page_base;
3461 struct regpair sge_page_base;
3462 struct regpair cqe_page_base;
3465 __le16 max_agg_size;
3467 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3468 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3469 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3470 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3471 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3472 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3473 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3474 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3475 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3476 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3477 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3478 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3479 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3480 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3481 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3482 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3483 __le16 cqe_pause_thr_low;
3484 __le16 cqe_pause_thr_high;
3485 __le16 bd_pause_thr_low;
3486 __le16 bd_pause_thr_high;
3487 __le16 sge_pause_thr_low;
3488 __le16 sge_pause_thr_high;
3490 __le16 silent_vlan_value;
3491 __le16 silent_vlan_mask;
3492 __le32 reserved6[2];
3496 * client init tx data
3498 struct client_init_tx_data {
3499 u8 enforce_security_flg;
3500 u8 tx_status_block_id;
3501 u8 tx_sb_index_number;
3502 u8 tss_leading_client_id;
3503 u8 tx_switching_flg;
3504 u8 anti_spoofing_flg;
3505 __le16 default_vlan;
3506 struct regpair tx_bd_page_base;
3508 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3509 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3510 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3511 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3512 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3513 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3514 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3515 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3516 #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4)
3517 #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4
3518 u8 default_vlan_flg;
3519 u8 force_default_pri_flg;
3524 * client init ramrod data
3526 struct client_init_ramrod_data {
3527 struct client_init_general_data general;
3528 struct client_init_rx_data rx;
3529 struct client_init_tx_data tx;
3534 * client update ramrod data
3536 struct client_update_ramrod_data {
3539 u8 inner_vlan_removal_enable_flg;
3540 u8 inner_vlan_removal_change_flg;
3541 u8 outer_vlan_removal_enable_flg;
3542 u8 outer_vlan_removal_change_flg;
3543 u8 anti_spoofing_enable_flg;
3544 u8 anti_spoofing_change_flg;
3546 u8 activate_change_flg;
3547 __le16 default_vlan;
3548 u8 default_vlan_enable_flg;
3549 u8 default_vlan_change_flg;
3550 __le16 silent_vlan_value;
3551 __le16 silent_vlan_mask;
3552 u8 silent_vlan_removal_flg;
3553 u8 silent_vlan_change_flg;
3559 * The eth storm context of Cstorm
3561 struct cstorm_eth_st_context {
3566 struct double_regpair {
3575 * Ethernet address typesm used in ethernet tx BDs
3577 enum eth_addr_type {
3589 struct eth_classify_cmd_header {
3590 u8 cmd_general_data;
3591 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3592 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3593 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3594 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3595 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3596 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3597 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3598 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3599 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3600 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3608 * header for eth classification config ramrod
3610 struct eth_classify_header {
3619 * Command for adding/removing a MAC classification rule
3621 struct eth_classify_mac_cmd {
3622 struct eth_classify_cmd_header header;
3632 * Command for adding/removing a MAC-VLAN pair classification rule
3634 struct eth_classify_pair_cmd {
3635 struct eth_classify_cmd_header header;
3645 * Command for adding/removing a VLAN classification rule
3647 struct eth_classify_vlan_cmd {
3648 struct eth_classify_cmd_header header;
3656 * union for eth classification rule
3658 union eth_classify_rule_cmd {
3659 struct eth_classify_mac_cmd mac;
3660 struct eth_classify_vlan_cmd vlan;
3661 struct eth_classify_pair_cmd pair;
3665 * parameters for eth classification configuration ramrod
3667 struct eth_classify_rules_ramrod_data {
3668 struct eth_classify_header header;
3669 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3674 * The data contain client ID need to the ramrod
3676 struct eth_common_ramrod_data {
3683 * The eth storm context of Ustorm
3685 struct ustorm_eth_st_context {
3690 * The eth storm context of Tstorm
3692 struct tstorm_eth_st_context {
3693 u32 __reserved0[28];
3697 * The eth storm context of Xstorm
3699 struct xstorm_eth_st_context {
3704 * Ethernet connection context
3706 struct eth_context {
3707 struct ustorm_eth_st_context ustorm_st_context;
3708 struct tstorm_eth_st_context tstorm_st_context;
3709 struct xstorm_eth_ag_context xstorm_ag_context;
3710 struct tstorm_eth_ag_context tstorm_ag_context;
3711 struct cstorm_eth_ag_context cstorm_ag_context;
3712 struct ustorm_eth_ag_context ustorm_ag_context;
3713 struct timers_block_context timers_context;
3714 struct xstorm_eth_st_context xstorm_st_context;
3715 struct cstorm_eth_st_context cstorm_st_context;
3720 * union for sgl and raw data.
3722 union eth_sgl_or_raw_data {
3728 * eth FP end aggregation CQE parameters struct
3730 struct eth_end_agg_rx_cqe {
3731 u8 type_error_flags;
3732 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3733 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3734 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3735 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3736 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3737 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3741 __le32 timestamp_delta;
3742 __le16 num_of_coalesced_segs;
3747 union eth_sgl_or_raw_data sgl_or_raw_data;
3748 __le32 reserved5[8];
3753 * regular eth FP CQE parameters struct
3755 struct eth_fast_path_rx_cqe {
3756 u8 type_error_flags;
3757 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3758 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3759 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3760 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3761 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3762 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3763 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3764 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3765 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3766 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3767 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
3768 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
3770 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3771 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3772 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3773 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3774 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3775 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3776 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3777 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3778 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3779 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3780 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3781 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3783 u8 placement_offset;
3784 __le32 rss_hash_result;
3786 __le16 pkt_len_or_gro_seg_len;
3788 struct parsing_flags pars_flags;
3789 union eth_sgl_or_raw_data sgl_or_raw_data;
3790 __le32 reserved1[8];
3795 * Command for setting classification flags for a client
3797 struct eth_filter_rules_cmd {
3798 u8 cmd_general_data;
3799 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3800 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3801 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3802 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3803 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3804 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3809 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3810 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3811 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3812 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3813 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3814 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3815 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3816 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3817 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3818 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3819 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3820 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3821 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3822 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3823 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3824 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3826 struct regpair reserved4;
3831 * parameters for eth classification filters ramrod
3833 struct eth_filter_rules_ramrod_data {
3834 struct eth_classify_header header;
3835 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3840 * parameters for eth classification configuration ramrod
3842 struct eth_general_rules_ramrod_data {
3843 struct eth_classify_header header;
3844 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3849 * The data for Halt ramrod
3851 struct eth_halt_ramrod_data {
3858 * Command for setting multicast classification for a client
3860 struct eth_multicast_rules_cmd {
3861 u8 cmd_general_data;
3862 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
3863 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
3864 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
3865 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
3866 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
3867 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
3868 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
3869 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
3874 struct regpair reserved3;
3879 * parameters for multicast classification ramrod
3881 struct eth_multicast_rules_ramrod_data {
3882 struct eth_classify_header header;
3883 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
3888 * Place holder for ramrods protocol specific data
3890 struct ramrod_data {
3896 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
3898 union eth_ramrod_data {
3899 struct ramrod_data general;
3904 * RSS toeplitz hash type, as reported in CQE
3906 enum eth_rss_hash_type {
3913 E1HOV_PRI_HASH_TYPE,
3915 MAX_ETH_RSS_HASH_TYPE
3923 ETH_RSS_MODE_DISABLED,
3924 ETH_RSS_MODE_REGULAR,
3925 ETH_RSS_MODE_VLAN_PRI,
3926 ETH_RSS_MODE_E1HOV_PRI,
3927 ETH_RSS_MODE_IP_DSCP,
3933 * parameters for RSS update ramrod (E2)
3935 struct eth_rss_update_ramrod_data {
3938 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
3939 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
3940 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
3941 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
3942 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
3943 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
3944 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
3945 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
3946 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
3947 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
3948 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
3949 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
3950 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7)
3951 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
3955 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
3956 __le32 rss_key[T_ETH_RSS_KEY];
3963 * The eth Rx Buffer Descriptor
3972 * Eth Rx Cqe structure- general structure for ramrods
3974 struct common_ramrod_eth_rx_cqe {
3976 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
3977 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
3978 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
3979 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
3980 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
3981 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
3984 __le32 conn_and_cmd_data;
3985 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
3986 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
3987 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
3988 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
3989 struct ramrod_data protocol_data;
3991 __le32 reserved2[11];
3995 * Rx Last CQE in page (in ETH)
3997 struct eth_rx_cqe_next_page {
4000 __le32 reserved[14];
4004 * union for all eth rx cqe types (fix their sizes)
4007 struct eth_fast_path_rx_cqe fast_path_cqe;
4008 struct common_ramrod_eth_rx_cqe ramrod_cqe;
4009 struct eth_rx_cqe_next_page next_page_cqe;
4010 struct eth_end_agg_rx_cqe end_agg_cqe;
4015 * Values for RX ETH CQE type field
4017 enum eth_rx_cqe_type {
4018 RX_ETH_CQE_TYPE_ETH_FASTPATH,
4019 RX_ETH_CQE_TYPE_ETH_RAMROD,
4020 RX_ETH_CQE_TYPE_ETH_START_AGG,
4021 RX_ETH_CQE_TYPE_ETH_STOP_AGG,
4027 * Type of SGL/Raw field in ETH RX fast path CQE
4029 enum eth_rx_fp_sel {
4037 * The eth Rx SGE Descriptor
4046 * common data for all protocols
4049 __le32 conn_and_cmd_data;
4050 #define SPE_HDR_CID (0xFFFFFF<<0)
4051 #define SPE_HDR_CID_SHIFT 0
4052 #define SPE_HDR_CMD_ID (0xFF<<24)
4053 #define SPE_HDR_CMD_ID_SHIFT 24
4055 #define SPE_HDR_CONN_TYPE (0xFF<<0)
4056 #define SPE_HDR_CONN_TYPE_SHIFT 0
4057 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
4058 #define SPE_HDR_FUNCTION_ID_SHIFT 8
4063 * specific data for ethernet slow path element
4065 union eth_specific_data {
4066 u8 protocol_data[8];
4067 struct regpair client_update_ramrod_data;
4068 struct regpair client_init_ramrod_init_data;
4069 struct eth_halt_ramrod_data halt_ramrod_data;
4070 struct regpair update_data_addr;
4071 struct eth_common_ramrod_data common_ramrod_data;
4072 struct regpair classify_cfg_addr;
4073 struct regpair filter_cfg_addr;
4074 struct regpair mcast_cfg_addr;
4078 * Ethernet slow path element
4082 union eth_specific_data data;
4087 * Ethernet command ID for slow path elements
4089 enum eth_spqe_cmd_id {
4090 RAMROD_CMD_ID_ETH_UNUSED,
4091 RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4092 RAMROD_CMD_ID_ETH_HALT,
4093 RAMROD_CMD_ID_ETH_FORWARD_SETUP,
4094 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
4095 RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
4096 RAMROD_CMD_ID_ETH_EMPTY,
4097 RAMROD_CMD_ID_ETH_TERMINATE,
4098 RAMROD_CMD_ID_ETH_TPA_UPDATE,
4099 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
4100 RAMROD_CMD_ID_ETH_FILTER_RULES,
4101 RAMROD_CMD_ID_ETH_MULTICAST_RULES,
4102 RAMROD_CMD_ID_ETH_RSS_UPDATE,
4103 RAMROD_CMD_ID_ETH_SET_MAC,
4109 * eth tpa update command
4111 enum eth_tpa_update_command {
4112 TPA_UPDATE_NONE_COMMAND,
4113 TPA_UPDATE_ENABLE_COMMAND,
4114 TPA_UPDATE_DISABLE_COMMAND,
4115 MAX_ETH_TPA_UPDATE_COMMAND
4120 * Tx regular BD structure
4125 __le16 total_pkt_bytes;
4132 * structure for easy accessibility to assembler
4134 struct eth_tx_bd_flags {
4136 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4137 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4138 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4139 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4140 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4141 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4142 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4143 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4144 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4145 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4146 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4147 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4148 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4149 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4153 * The eth Tx Buffer Descriptor
4155 struct eth_tx_start_bd {
4160 __le16 vlan_or_ethertype;
4161 struct eth_tx_bd_flags bd_flags;
4163 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0)
4164 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4165 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4166 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4167 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
4168 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
4169 #define ETH_TX_START_BD_RESREVED (0x1<<7)
4170 #define ETH_TX_START_BD_RESREVED_SHIFT 7
4174 * Tx parsing BD structure for ETH E1/E1h
4176 struct eth_tx_parse_bd_e1x {
4178 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4179 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4180 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
4181 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
4182 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
4183 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
4184 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
4185 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
4186 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
4187 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
4188 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
4189 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
4191 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4192 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4193 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4194 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4195 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4196 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4197 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4198 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4199 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4200 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4201 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4202 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4203 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4204 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4205 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4206 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4208 __le16 total_hlen_w;
4209 __le16 tcp_pseudo_csum;
4212 __le32 tcp_send_seq;
4216 * Tx parsing BD structure for ETH E2
4218 struct eth_tx_parse_bd_e2 {
4219 __le16 dst_mac_addr_lo;
4220 __le16 dst_mac_addr_mid;
4221 __le16 dst_mac_addr_hi;
4222 __le16 src_mac_addr_lo;
4223 __le16 src_mac_addr_mid;
4224 __le16 src_mac_addr_hi;
4225 __le32 parsing_data;
4226 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x7FF<<0)
4227 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
4228 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
4229 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
4230 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
4231 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
4232 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
4233 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
4234 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
4235 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
4239 * The last BD in the BD memory will hold a pointer to the next BD memory
4241 struct eth_tx_next_bd {
4248 * union for 4 Bd types
4250 union eth_tx_bd_types {
4251 struct eth_tx_start_bd start_bd;
4252 struct eth_tx_bd reg_bd;
4253 struct eth_tx_parse_bd_e1x parse_bd_e1x;
4254 struct eth_tx_parse_bd_e2 parse_bd_e2;
4255 struct eth_tx_next_bd next_bd;
4259 * array of 13 bds as appears in the eth xstorm context
4261 struct eth_tx_bds_array {
4262 union eth_tx_bd_types bds[13];
4267 * VLAN mode on TX BDs
4269 enum eth_tx_vlan_type {
4273 X_ETH_FW_ADDED_VLAN,
4274 MAX_ETH_TX_VLAN_TYPE
4279 * Ethernet VLAN filtering mode in E1x
4281 enum eth_vlan_filter_mode {
4282 ETH_VLAN_FILTER_ANY_VLAN,
4283 ETH_VLAN_FILTER_SPECIFIC_VLAN,
4284 ETH_VLAN_FILTER_CLASSIFY,
4285 MAX_ETH_VLAN_FILTER_MODE
4290 * MAC filtering configuration command header
4292 struct mac_configuration_hdr {
4300 * MAC address in list for ramrod
4302 struct mac_configuration_entry {
4303 __le16 lsb_mac_addr;
4304 __le16 middle_mac_addr;
4305 __le16 msb_mac_addr;
4309 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4310 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4311 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4312 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4313 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4314 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4315 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4316 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4317 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4318 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4319 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4320 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4322 __le32 clients_bit_vector;
4326 * MAC filtering configuration command
4328 struct mac_configuration_cmd {
4329 struct mac_configuration_hdr hdr;
4330 struct mac_configuration_entry config_table[64];
4335 * Set-MAC command type (in E1x)
4337 enum set_mac_action_type {
4338 T_ETH_MAC_COMMAND_INVALIDATE,
4339 T_ETH_MAC_COMMAND_SET,
4340 MAX_SET_MAC_ACTION_TYPE
4345 * Ethernet TPA Modes
4354 * tpa update ramrod data
4356 struct tpa_update_ramrod_data {
4361 u8 max_sges_for_packet;
4362 u8 complete_on_both_clients;
4363 u8 dont_verify_rings_pause_thr_flg;
4365 __le16 sge_buff_size;
4366 __le16 max_agg_size;
4367 __le32 sge_page_base_lo;
4368 __le32 sge_page_base_hi;
4369 __le16 sge_pause_thr_low;
4370 __le16 sge_pause_thr_high;
4375 * approximate-match multicast filtering for E1H per function in Tstorm
4377 struct tstorm_eth_approximate_match_multicast_filtering {
4378 u32 mcast_add_hash_bit_array[8];
4383 * Common configuration parameters per function in Tstorm
4385 struct tstorm_eth_function_common_config {
4386 __le16 config_flags;
4387 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4388 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4389 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4390 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4391 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4392 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4393 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4394 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4395 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4396 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4397 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4398 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4399 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4400 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4408 * MAC filtering configuration parameters per port in Tstorm
4410 struct tstorm_eth_mac_filter_config {
4412 u32 ucast_accept_all;
4414 u32 mcast_accept_all;
4415 u32 bcast_accept_all;
4417 u32 unmatched_unicast;
4422 * tx only queue init ramrod data
4424 struct tx_queue_init_ramrod_data {
4425 struct client_init_general_data general;
4426 struct client_init_tx_data tx;
4431 * Three RX producers for ETH
4433 struct ustorm_eth_rx_producers {
4434 #if defined(__BIG_ENDIAN)
4437 #elif defined(__LITTLE_ENDIAN)
4441 #if defined(__BIG_ENDIAN)
4444 #elif defined(__LITTLE_ENDIAN)
4452 * FCoE RX statistics parameters section#0
4454 struct fcoe_rx_stat_params_section0 {
4455 __le32 fcoe_rx_pkt_cnt;
4456 __le32 fcoe_rx_byte_cnt;
4461 * FCoE RX statistics parameters section#1
4463 struct fcoe_rx_stat_params_section1 {
4464 __le32 fcoe_ver_cnt;
4465 __le32 fcoe_rx_drop_pkt_cnt;
4470 * FCoE RX statistics parameters section#2
4472 struct fcoe_rx_stat_params_section2 {
4474 __le32 eofa_del_cnt;
4475 __le32 miss_frame_cnt;
4476 __le32 seq_timeout_cnt;
4477 __le32 drop_seq_cnt;
4478 __le32 fcoe_rx_drop_pkt_cnt;
4479 __le32 fcp_rx_pkt_cnt;
4485 * FCoE TX statistics parameters
4487 struct fcoe_tx_stat_params {
4488 __le32 fcoe_tx_pkt_cnt;
4489 __le32 fcoe_tx_byte_cnt;
4490 __le32 fcp_tx_pkt_cnt;
4495 * FCoE statistics parameters
4497 struct fcoe_statistics_params {
4498 struct fcoe_tx_stat_params tx_stat;
4499 struct fcoe_rx_stat_params_section0 rx_stat0;
4500 struct fcoe_rx_stat_params_section1 rx_stat1;
4501 struct fcoe_rx_stat_params_section2 rx_stat2;
4506 * The data afex vif list ramrod need
4508 struct afex_vif_list_ramrod_data {
4509 u8 afex_vif_list_command;
4511 __le16 vif_list_index;
4519 * cfc delete event data
4521 struct cfc_del_event_data {
4529 * per-port SAFC demo variables
4531 struct cmng_flags_per_port {
4533 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4534 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4535 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4536 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4537 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4538 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4539 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4540 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4541 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4542 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4548 * per-port rate shaping variables
4550 struct rate_shaping_vars_per_port {
4551 u32 rs_periodic_timeout;
4556 * per-port fairness variables
4558 struct fairness_vars_per_port {
4561 u32 fairness_timeout;
4566 * per-port SAFC variables
4568 struct safc_struct_per_port {
4569 #if defined(__BIG_ENDIAN)
4572 u8 safc_timeout_usec;
4573 #elif defined(__LITTLE_ENDIAN)
4574 u8 safc_timeout_usec;
4578 u8 cos_to_traffic_types[MAX_COS_NUMBER];
4579 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4583 * Per-port congestion management variables
4585 struct cmng_struct_per_port {
4586 struct rate_shaping_vars_per_port rs_vars;
4587 struct fairness_vars_per_port fair_vars;
4588 struct safc_struct_per_port safc_vars;
4589 struct cmng_flags_per_port flags;
4593 * a single rate shaping counter. can be used as protocol or vnic counter
4595 struct rate_shaping_counter {
4597 #if defined(__BIG_ENDIAN)
4600 #elif defined(__LITTLE_ENDIAN)
4607 * per-vnic rate shaping variables
4609 struct rate_shaping_vars_per_vn {
4610 struct rate_shaping_counter vn_counter;
4614 * per-vnic fairness variables
4616 struct fairness_vars_per_vn {
4617 u32 cos_credit_delta[MAX_COS_NUMBER];
4618 u32 vn_credit_delta;
4623 * cmng port init state
4626 struct rate_shaping_vars_per_vn vnic_max_rate[4];
4627 struct fairness_vars_per_vn vnic_min_rate[4];
4631 * cmng port init state
4634 struct cmng_struct_per_port port;
4635 struct cmng_vnic vnic;
4640 * driver parameters for congestion management init, all rates are in Mbps
4642 struct cmng_init_input {
4644 u16 vnic_min_rate[4];
4645 u16 vnic_max_rate[4];
4646 u16 cos_min_rate[MAX_COS_NUMBER];
4647 u16 cos_to_pause_mask[MAX_COS_NUMBER];
4648 struct cmng_flags_per_port flags;
4653 * Protocol-common command ID for slow path elements
4655 enum common_spqe_cmd_id {
4656 RAMROD_CMD_ID_COMMON_UNUSED,
4657 RAMROD_CMD_ID_COMMON_FUNCTION_START,
4658 RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4659 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
4660 RAMROD_CMD_ID_COMMON_CFC_DEL,
4661 RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4662 RAMROD_CMD_ID_COMMON_STAT_QUERY,
4663 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4664 RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4665 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
4666 MAX_COMMON_SPQE_CMD_ID
4671 * Per-protocol connection types
4673 enum connection_type {
4674 ETH_CONNECTION_TYPE,
4675 TOE_CONNECTION_TYPE,
4676 RDMA_CONNECTION_TYPE,
4677 ISCSI_CONNECTION_TYPE,
4678 FCOE_CONNECTION_TYPE,
4679 RESERVED_CONNECTION_TYPE_0,
4680 RESERVED_CONNECTION_TYPE_1,
4681 RESERVED_CONNECTION_TYPE_2,
4682 NONE_CONNECTION_TYPE,
4699 * Dynamic HC counters set by the driver
4701 struct hc_dynamic_drv_counter {
4702 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
4706 * zone A per-queue data
4708 struct cstorm_queue_zone_data {
4709 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4710 struct regpair reserved[2];
4715 * Vf-PF channel data in cstorm ram (non-triggered zone)
4717 struct vf_pf_channel_zone_data {
4723 * zone for VF non-triggered data
4725 struct non_trigger_vf_zone {
4726 struct vf_pf_channel_zone_data vf_pf_channel;
4730 * Vf-PF channel trigger zone in cstorm ram
4732 struct vf_pf_channel_zone_trigger {
4737 * zone that triggers the in-bound interrupt
4739 struct trigger_vf_zone {
4740 #if defined(__BIG_ENDIAN)
4743 struct vf_pf_channel_zone_trigger vf_pf_channel;
4744 #elif defined(__LITTLE_ENDIAN)
4745 struct vf_pf_channel_zone_trigger vf_pf_channel;
4753 * zone B per-VF data
4755 struct cstorm_vf_zone_data {
4756 struct non_trigger_vf_zone non_trigger;
4757 struct trigger_vf_zone trigger;
4762 * Dynamic host coalescing init parameters, per state machine
4764 struct dynamic_hc_sm_config {
4766 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
4767 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
4768 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
4769 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
4770 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
4774 * Dynamic host coalescing init parameters
4776 struct dynamic_hc_config {
4777 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
4781 struct e2_integ_data {
4782 #if defined(__BIG_ENDIAN)
4784 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4785 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4786 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4787 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4788 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4789 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4790 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4791 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4792 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4793 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4794 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4795 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4799 #elif defined(__LITTLE_ENDIAN)
4804 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4805 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4806 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4807 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4808 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4809 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4810 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4811 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4812 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4813 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4814 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4815 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4817 #if defined(__BIG_ENDIAN)
4821 #elif defined(__LITTLE_ENDIAN)
4830 * set mac event data
4832 struct eth_event_data {
4842 struct vf_pf_event_data {
4853 struct vf_flr_event_data {
4862 * malicious VF event data
4864 struct malicious_vf_event_data {
4873 * vif list event data
4875 struct vif_list_event_data {
4883 /* function update event data */
4884 struct function_update_event_data {
4893 /* union for all event ring message types */
4895 struct vf_pf_event_data vf_pf_event;
4896 struct eth_event_data eth_event;
4897 struct cfc_del_event_data cfc_del_event;
4898 struct vf_flr_event_data vf_flr_event;
4899 struct malicious_vf_event_data malicious_vf_event;
4900 struct vif_list_event_data vif_list_event;
4901 struct function_update_event_data function_update_event;
4906 * per PF event ring data
4908 struct event_ring_data {
4909 struct regpair_native base_addr;
4910 #if defined(__BIG_ENDIAN)
4914 #elif defined(__LITTLE_ENDIAN)
4924 * event ring message element (each element is 128 bits)
4926 struct event_ring_msg {
4930 union event_data data;
4934 * event ring next page element (128 bits)
4936 struct event_ring_next {
4937 struct regpair addr;
4942 * union for event ring element types (each element is 128 bits)
4944 union event_ring_elem {
4945 struct event_ring_msg message;
4946 struct event_ring_next next_page;
4951 * Common event ring opcodes
4953 enum event_ring_opcode {
4954 EVENT_RING_OPCODE_VF_PF_CHANNEL,
4955 EVENT_RING_OPCODE_FUNCTION_START,
4956 EVENT_RING_OPCODE_FUNCTION_STOP,
4957 EVENT_RING_OPCODE_CFC_DEL,
4958 EVENT_RING_OPCODE_CFC_DEL_WB,
4959 EVENT_RING_OPCODE_STAT_QUERY,
4960 EVENT_RING_OPCODE_STOP_TRAFFIC,
4961 EVENT_RING_OPCODE_START_TRAFFIC,
4962 EVENT_RING_OPCODE_VF_FLR,
4963 EVENT_RING_OPCODE_MALICIOUS_VF,
4964 EVENT_RING_OPCODE_FORWARD_SETUP,
4965 EVENT_RING_OPCODE_RSS_UPDATE_RULES,
4966 EVENT_RING_OPCODE_FUNCTION_UPDATE,
4967 EVENT_RING_OPCODE_AFEX_VIF_LISTS,
4968 EVENT_RING_OPCODE_SET_MAC,
4969 EVENT_RING_OPCODE_CLASSIFICATION_RULES,
4970 EVENT_RING_OPCODE_FILTERS_RULES,
4971 EVENT_RING_OPCODE_MULTICAST_RULES,
4972 MAX_EVENT_RING_OPCODE
4977 * Modes for fairness algorithm
4979 enum fairness_mode {
4980 FAIRNESS_COS_WRR_MODE,
4981 FAIRNESS_COS_ETS_MODE,
4989 struct priority_cos {
4996 * The data for flow control configuration
4998 struct flow_control_configuration {
4999 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
5002 u8 dont_add_pri_0_en;
5011 struct function_start_data {
5017 u8 network_cos_mode;
5021 struct function_update_data {
5022 u8 vif_id_change_flg;
5023 u8 afex_default_vlan_change_flg;
5024 u8 allowed_priorities_change_flg;
5025 u8 network_cos_mode_change_flg;
5027 __le16 afex_default_vlan;
5028 u8 allowed_priorities;
5029 u8 network_cos_mode;
5031 u8 tx_switch_suspend_change_flg;
5032 u8 tx_switch_suspend;
5039 * FW version stored in the Xstorm RAM
5042 #if defined(__BIG_ENDIAN)
5047 #elif defined(__LITTLE_ENDIAN)
5054 #define FW_VERSION_OPTIMIZED (0x1<<0)
5055 #define FW_VERSION_OPTIMIZED_SHIFT 0
5056 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
5057 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
5058 #define FW_VERSION_CHIP_VERSION (0x3<<2)
5059 #define FW_VERSION_CHIP_VERSION_SHIFT 2
5060 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
5061 #define __FW_VERSION_RESERVED_SHIFT 4
5066 * Dynamic Host-Coalescing - Driver(host) counters
5068 struct hc_dynamic_sb_drv_counters {
5069 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
5074 * 2 bytes. configuration/state parameters for a single protocol index
5076 struct hc_index_data {
5077 #if defined(__BIG_ENDIAN)
5079 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5080 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5081 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5082 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5083 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5084 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5085 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5086 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5088 #elif defined(__LITTLE_ENDIAN)
5091 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5092 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5093 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5094 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5095 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5096 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5097 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5098 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5106 struct hc_status_block_sm {
5107 #if defined(__BIG_ENDIAN)
5112 #elif defined(__LITTLE_ENDIAN)
5122 * hold PCI identification variables- used in various places in firmware
5125 #if defined(__BIG_ENDIAN)
5130 #elif defined(__LITTLE_ENDIAN)
5139 * The fast-path status block meta-data, common to all chips
5142 struct regpair_native host_sb_addr;
5143 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
5144 struct pci_entity p_func;
5145 #if defined(__BIG_ENDIAN)
5150 #elif defined(__LITTLE_ENDIAN)
5156 struct regpair_native rsrv1[2];
5161 * Segment types for host coaslescing
5171 * The fast-path status block meta-data
5173 struct hc_sp_status_block_data {
5174 struct regpair_native host_sb_addr;
5175 #if defined(__BIG_ENDIAN)
5180 #elif defined(__LITTLE_ENDIAN)
5186 struct pci_entity p_func;
5191 * The fast-path status block meta-data
5193 struct hc_status_block_data_e1x {
5194 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
5195 struct hc_sb_data common;
5200 * The fast-path status block meta-data
5202 struct hc_status_block_data_e2 {
5203 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
5204 struct hc_sb_data common;
5209 * IGU block operartion modes (in Everest2)
5229 * Multi-function modes
5235 MULTI_FUNCTION_AFEX,
5240 * Protocol-common statistics collected by the Tstorm (per pf)
5242 struct tstorm_per_pf_stats {
5243 struct regpair rcv_error_bytes;
5249 struct per_pf_stats {
5250 struct tstorm_per_pf_stats tstorm_pf_statistics;
5255 * Protocol-common statistics collected by the Tstorm (per port)
5257 struct tstorm_per_port_stats {
5259 __le32 mac_filter_discard;
5260 __le32 brb_truncate_discard;
5261 __le32 mf_tag_discard;
5269 struct per_port_stats {
5270 struct tstorm_per_port_stats tstorm_port_statistics;
5275 * Protocol-common statistics collected by the Tstorm (per client)
5277 struct tstorm_per_queue_stats {
5278 struct regpair rcv_ucast_bytes;
5279 __le32 rcv_ucast_pkts;
5280 __le32 checksum_discard;
5281 struct regpair rcv_bcast_bytes;
5282 __le32 rcv_bcast_pkts;
5283 __le32 pkts_too_big_discard;
5284 struct regpair rcv_mcast_bytes;
5285 __le32 rcv_mcast_pkts;
5286 __le32 ttl0_discard;
5287 __le16 no_buff_discard;
5293 * Protocol-common statistics collected by the Ustorm (per client)
5295 struct ustorm_per_queue_stats {
5296 struct regpair ucast_no_buff_bytes;
5297 struct regpair mcast_no_buff_bytes;
5298 struct regpair bcast_no_buff_bytes;
5299 __le32 ucast_no_buff_pkts;
5300 __le32 mcast_no_buff_pkts;
5301 __le32 bcast_no_buff_pkts;
5302 __le32 coalesced_pkts;
5303 struct regpair coalesced_bytes;
5304 __le32 coalesced_events;
5305 __le32 coalesced_aborts;
5309 * Protocol-common statistics collected by the Xstorm (per client)
5311 struct xstorm_per_queue_stats {
5312 struct regpair ucast_bytes_sent;
5313 struct regpair mcast_bytes_sent;
5314 struct regpair bcast_bytes_sent;
5315 __le32 ucast_pkts_sent;
5316 __le32 mcast_pkts_sent;
5317 __le32 bcast_pkts_sent;
5318 __le32 error_drop_pkts;
5324 struct per_queue_stats {
5325 struct tstorm_per_queue_stats tstorm_queue_statistics;
5326 struct ustorm_per_queue_stats ustorm_queue_statistics;
5327 struct xstorm_per_queue_stats xstorm_queue_statistics;
5332 * FW version stored in first line of pram
5334 struct pram_fw_version {
5340 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
5341 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
5342 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
5343 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
5344 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
5345 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
5346 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
5347 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
5348 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
5349 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
5354 * Ethernet slow path element
5356 union protocol_common_specific_data {
5357 u8 protocol_data[8];
5358 struct regpair phy_address;
5359 struct regpair mac_config_addr;
5360 struct afex_vif_list_ramrod_data afex_vif_list_data;
5364 * The send queue element
5366 struct protocol_common_spe {
5368 union protocol_common_specific_data data;
5373 * The send queue element
5375 struct slow_path_element {
5377 struct regpair protocol_data;
5382 * Protocol-common statistics counter
5384 struct stats_counter {
5385 __le16 xstats_counter;
5388 __le16 tstats_counter;
5391 __le16 ustats_counter;
5394 __le16 cstats_counter;
5403 struct stats_query_entry {
5408 struct regpair address;
5414 struct stats_query_cmd_group {
5415 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
5420 * statistic command header
5422 struct stats_query_header {
5425 __le16 drv_stats_counter;
5427 struct regpair stats_counters_addrs;
5432 * Types of statistcis query entry
5434 enum stats_query_type {
5440 MAX_STATS_QUERY_TYPE
5445 * Indicate of the function status block state
5447 enum status_block_state {
5451 MAX_STATUS_BLOCK_STATE
5456 * Storm IDs (including attentions for IGU related enums)
5469 * Taffic types used in ETS and flow control algorithms
5472 LLFC_TRAFFIC_TYPE_NW,
5473 LLFC_TRAFFIC_TYPE_FCOE,
5474 LLFC_TRAFFIC_TYPE_ISCSI,
5480 * zone A per-queue data
5482 struct tstorm_queue_zone_data {
5483 struct regpair reserved[4];
5488 * zone B per-VF data
5490 struct tstorm_vf_zone_data {
5491 struct regpair reserved;
5496 * zone A per-queue data
5498 struct ustorm_queue_zone_data {
5499 struct ustorm_eth_rx_producers eth_rx_producers;
5500 struct regpair reserved[3];
5505 * zone B per-VF data
5507 struct ustorm_vf_zone_data {
5508 struct regpair reserved;
5513 * data per VF-PF channel
5515 struct vf_pf_channel_data {
5516 #if defined(__BIG_ENDIAN)
5520 #elif defined(__LITTLE_ENDIAN)
5530 * State of VF-PF channel
5532 enum vf_pf_channel_state {
5533 VF_PF_CHANNEL_STATE_READY,
5534 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
5535 MAX_VF_PF_CHANNEL_STATE
5540 * vif_list_rule_kind
5542 enum vif_list_rule_kind {
5545 VIF_LIST_RULE_CLEAR_ALL,
5546 VIF_LIST_RULE_CLEAR_FUNC,
5547 MAX_VIF_LIST_RULE_KIND
5552 * zone A per-queue data
5554 struct xstorm_queue_zone_data {
5555 struct regpair reserved[4];
5560 * zone B per-VF data
5562 struct xstorm_vf_zone_data {
5563 struct regpair reserved;
5566 #endif /* BNX2X_HSI_H */
projects / firefly-linux-kernel-4.4.55.git / blob