1 /* Copyright 2008-2013 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
28 #include "bnx2x_cmn.h"
30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
31 struct link_params *params,
32 u8 dev_addr, u16 addr, u8 byte_cnt,
34 /********************************************************/
36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
37 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
38 #define ETH_MIN_PACKET_SIZE 60
39 #define ETH_MAX_PACKET_SIZE 1500
40 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
41 #define MDIO_ACCESS_TIMEOUT 1000
43 #define I2C_SWITCH_WIDTH 2
46 #define I2C_WA_RETRY_CNT 3
47 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
48 #define MCPR_IMC_COMMAND_READ_OP 1
49 #define MCPR_IMC_COMMAND_WRITE_OP 2
51 /* LED Blink rate that will achieve ~15.9Hz */
52 #define LED_BLINK_RATE_VAL_E3 354
53 #define LED_BLINK_RATE_VAL_E1X_E2 480
54 /***********************************************************/
55 /* Shortcut definitions */
56 /***********************************************************/
58 #define NIG_LATCH_BC_ENABLE_MI_INT 0
60 #define NIG_STATUS_EMAC0_MI_INT \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
62 #define NIG_STATUS_XGXS0_LINK10G \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
64 #define NIG_STATUS_XGXS0_LINK_STATUS \
65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
67 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
68 #define NIG_STATUS_SERDES0_LINK_STATUS \
69 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
70 #define NIG_MASK_MI_INT \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
72 #define NIG_MASK_XGXS0_LINK10G \
73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
74 #define NIG_MASK_XGXS0_LINK_STATUS \
75 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
76 #define NIG_MASK_SERDES0_LINK_STATUS \
77 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
79 #define MDIO_AN_CL73_OR_37_COMPLETE \
80 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
81 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
83 #define XGXS_RESET_BITS \
84 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
85 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
90 #define SERDES_RESET_BITS \
91 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
92 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
93 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
94 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
96 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
97 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
98 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
99 #define AUTONEG_PARALLEL \
100 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
101 #define AUTONEG_SGMII_FIBER_AUTODET \
102 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
103 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
108 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
109 #define GP_STATUS_SPEED_MASK \
110 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
111 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
112 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
113 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
114 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
115 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
116 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
117 #define GP_STATUS_10G_HIG \
118 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
119 #define GP_STATUS_10G_CX4 \
120 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
122 #define GP_STATUS_10G_KX4 \
123 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
125 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
127 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
129 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
130 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
131 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
132 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
133 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
134 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
135 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
136 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
137 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
138 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
139 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
140 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
141 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
142 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
143 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
145 #define LINK_UPDATE_MASK \
146 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
147 LINK_STATUS_LINK_UP | \
148 LINK_STATUS_PHYSICAL_LINK_FLAG | \
149 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
150 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
151 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
152 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
153 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
154 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
156 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
157 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
158 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
159 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
162 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
163 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
164 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
165 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
167 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
168 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
169 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
171 #define SFP_EEPROM_OPTIONS_ADDR 0x40
172 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
173 #define SFP_EEPROM_OPTIONS_SIZE 2
175 #define EDC_MODE_LINEAR 0x0022
176 #define EDC_MODE_LIMITING 0x0044
177 #define EDC_MODE_PASSIVE_DAC 0x0055
180 #define DCBX_INVALID_COS (0xFF)
182 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
183 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
184 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
185 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
186 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
188 #define MAX_PACKET_SIZE (9700)
189 #define MAX_KR_LINK_RETRY 4
191 /**********************************************************/
193 /**********************************************************/
195 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
196 bnx2x_cl45_write(_bp, _phy, \
197 (_phy)->def_md_devad, \
198 (_bank + (_addr & 0xf)), \
201 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
202 bnx2x_cl45_read(_bp, _phy, \
203 (_phy)->def_md_devad, \
204 (_bank + (_addr & 0xf)), \
207 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
209 u32 val = REG_RD(bp, reg);
212 REG_WR(bp, reg, val);
216 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
218 u32 val = REG_RD(bp, reg);
221 REG_WR(bp, reg, val);
226 * bnx2x_check_lfa - This function checks if link reinitialization is required,
227 * or link flap can be avoided.
229 * @params: link parameters
230 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
233 static int bnx2x_check_lfa(struct link_params *params)
235 u32 link_status, cfg_idx, lfa_mask, cfg_size;
236 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
237 u32 saved_val, req_val, eee_status;
238 struct bnx2x *bp = params->bp;
241 REG_RD(bp, params->lfa_base +
242 offsetof(struct shmem_lfa, additional_config));
244 /* NOTE: must be first condition checked -
245 * to verify DCC bit is cleared in any case!
247 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
248 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
249 REG_WR(bp, params->lfa_base +
250 offsetof(struct shmem_lfa, additional_config),
251 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
252 return LFA_DCC_LFA_DISABLED;
255 /* Verify that link is up */
256 link_status = REG_RD(bp, params->shmem_base +
257 offsetof(struct shmem_region,
258 port_mb[params->port].link_status));
259 if (!(link_status & LINK_STATUS_LINK_UP))
260 return LFA_LINK_DOWN;
262 /* if loaded after BOOT from SAN, don't flap the link in any case and
263 * rely on link set by preboot driver
265 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
268 /* Verify that loopback mode is not set */
269 if (params->loopback_mode)
270 return LFA_LOOPBACK_ENABLED;
272 /* Verify that MFW supports LFA */
273 if (!params->lfa_base)
274 return LFA_MFW_IS_TOO_OLD;
276 if (params->num_phys == 3) {
278 lfa_mask = 0xffffffff;
285 saved_val = REG_RD(bp, params->lfa_base +
286 offsetof(struct shmem_lfa, req_duplex));
287 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
288 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
289 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
290 (saved_val & lfa_mask), (req_val & lfa_mask));
291 return LFA_DUPLEX_MISMATCH;
293 /* Compare Flow Control */
294 saved_val = REG_RD(bp, params->lfa_base +
295 offsetof(struct shmem_lfa, req_flow_ctrl));
296 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
297 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
298 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
299 (saved_val & lfa_mask), (req_val & lfa_mask));
300 return LFA_FLOW_CTRL_MISMATCH;
302 /* Compare Link Speed */
303 saved_val = REG_RD(bp, params->lfa_base +
304 offsetof(struct shmem_lfa, req_line_speed));
305 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
306 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
307 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
308 (saved_val & lfa_mask), (req_val & lfa_mask));
309 return LFA_LINK_SPEED_MISMATCH;
312 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
313 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
314 offsetof(struct shmem_lfa,
315 speed_cap_mask[cfg_idx]));
317 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
318 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
320 params->speed_cap_mask[cfg_idx]);
321 return LFA_SPEED_CAP_MISMATCH;
325 cur_req_fc_auto_adv =
326 REG_RD(bp, params->lfa_base +
327 offsetof(struct shmem_lfa, additional_config)) &
328 REQ_FC_AUTO_ADV_MASK;
330 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
331 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
332 cur_req_fc_auto_adv, params->req_fc_auto_adv);
333 return LFA_FLOW_CTRL_MISMATCH;
336 eee_status = REG_RD(bp, params->shmem2_base +
337 offsetof(struct shmem2_region,
338 eee_status[params->port]));
340 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
341 (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
342 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
343 (params->eee_mode & EEE_MODE_ADV_LPI))) {
344 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
346 return LFA_EEE_MISMATCH;
349 /* LFA conditions are met */
352 /******************************************************************/
353 /* EPIO/GPIO section */
354 /******************************************************************/
355 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
357 u32 epio_mask, gp_oenable;
361 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
365 epio_mask = 1 << epio_pin;
366 /* Set this EPIO to output */
367 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
368 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
370 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
372 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
374 u32 epio_mask, gp_output, gp_oenable;
378 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
381 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
382 epio_mask = 1 << epio_pin;
383 /* Set this EPIO to output */
384 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
386 gp_output |= epio_mask;
388 gp_output &= ~epio_mask;
390 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
392 /* Set the value for this EPIO */
393 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
394 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
397 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
399 if (pin_cfg == PIN_CFG_NA)
401 if (pin_cfg >= PIN_CFG_EPIO0) {
402 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
404 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
405 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
406 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
410 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
412 if (pin_cfg == PIN_CFG_NA)
414 if (pin_cfg >= PIN_CFG_EPIO0) {
415 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
417 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
418 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
419 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
424 /******************************************************************/
426 /******************************************************************/
427 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
429 /* ETS disabled configuration*/
430 struct bnx2x *bp = params->bp;
432 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
434 /* mapping between entry priority to client number (0,1,2 -debug and
435 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
437 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
438 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
441 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
442 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
443 * as strict. Bits 0,1,2 - debug and management entries, 3 -
444 * COS0 entry, 4 - COS1 entry.
445 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
446 * bit4 bit3 bit2 bit1 bit0
447 * MCP and debug are strict
450 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
451 /* defines which entries (clients) are subjected to WFQ arbitration */
452 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
453 /* For strict priority entries defines the number of consecutive
454 * slots for the highest priority.
456 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
457 /* mapping between the CREDIT_WEIGHT registers and actual client
460 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
461 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
462 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
464 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
465 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
466 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
467 /* ETS mode disable */
468 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
469 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
470 * weight for COS0/COS1.
472 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
473 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
474 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
475 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
476 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
477 /* Defines the number of consecutive slots for the strict priority */
478 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
480 /******************************************************************************
482 * Getting min_w_val will be set according to line speed .
484 ******************************************************************************/
485 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
488 /* Calculate min_w_val.*/
490 if (vars->line_speed == SPEED_20000)
491 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
493 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
495 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
496 /* If the link isn't up (static configuration for example ) The
497 * link will be according to 20GBPS.
501 /******************************************************************************
503 * Getting credit upper bound form min_w_val.
505 ******************************************************************************/
506 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
508 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
510 return credit_upper_bound;
512 /******************************************************************************
514 * Set credit upper bound for NIG.
516 ******************************************************************************/
517 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
518 const struct link_params *params,
521 struct bnx2x *bp = params->bp;
522 const u8 port = params->port;
523 const u32 credit_upper_bound =
524 bnx2x_ets_get_credit_upper_bound(min_w_val);
526 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
527 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
528 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
529 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
530 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
531 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
532 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
533 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
534 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
535 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
536 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
537 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
540 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
542 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
544 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
548 /******************************************************************************
550 * Will return the NIG ETS registers to init values.Except
551 * credit_upper_bound.
552 * That isn't used in this configuration (No WFQ is enabled) and will be
553 * configured acording to spec
555 ******************************************************************************/
556 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
557 const struct link_vars *vars)
559 struct bnx2x *bp = params->bp;
560 const u8 port = params->port;
561 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
562 /* Mapping between entry priority to client number (0,1,2 -debug and
563 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
564 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
565 * reset value or init tool
568 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
569 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
571 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
572 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
574 /* For strict priority entries defines the number of consecutive
575 * slots for the highest priority.
577 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
578 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
579 /* Mapping between the CREDIT_WEIGHT registers and actual client
584 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
585 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
588 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
590 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
593 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
594 * as strict. Bits 0,1,2 - debug and management entries, 3 -
595 * COS0 entry, 4 - COS1 entry.
596 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
597 * bit4 bit3 bit2 bit1 bit0
598 * MCP and debug are strict
601 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
603 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
604 /* defines which entries (clients) are subjected to WFQ arbitration */
605 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
606 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
608 /* Please notice the register address are note continuous and a
609 * for here is note appropriate.In 2 port mode port0 only COS0-5
610 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
611 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
612 * are never used for WFQ
614 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
615 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
616 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
617 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
618 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
619 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
620 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
621 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
622 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
623 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
624 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
625 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
627 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
628 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
629 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
632 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
634 /******************************************************************************
636 * Set credit upper bound for PBF.
638 ******************************************************************************/
639 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
640 const struct link_params *params,
643 struct bnx2x *bp = params->bp;
644 const u32 credit_upper_bound =
645 bnx2x_ets_get_credit_upper_bound(min_w_val);
646 const u8 port = params->port;
647 u32 base_upper_bound = 0;
650 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
651 * port mode port1 has COS0-2 that can be used for WFQ.
654 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
655 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
657 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
658 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
661 for (i = 0; i < max_cos; i++)
662 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
665 /******************************************************************************
667 * Will return the PBF ETS registers to init values.Except
668 * credit_upper_bound.
669 * That isn't used in this configuration (No WFQ is enabled) and will be
670 * configured acording to spec
672 ******************************************************************************/
673 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
675 struct bnx2x *bp = params->bp;
676 const u8 port = params->port;
677 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
682 /* Mapping between entry priority to client number 0 - COS0
683 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
684 * TODO_ETS - Should be done by reset value or init tool
687 /* 0x688 (|011|0 10|00 1|000) */
688 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
690 /* (10 1|100 |011|0 10|00 1|000) */
691 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
693 /* TODO_ETS - Should be done by reset value or init tool */
695 /* 0x688 (|011|0 10|00 1|000)*/
696 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
698 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
699 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
701 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
702 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
705 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
706 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
708 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
709 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
710 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
711 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
714 base_weight = PBF_REG_COS0_WEIGHT_P0;
715 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
717 base_weight = PBF_REG_COS0_WEIGHT_P1;
718 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
721 for (i = 0; i < max_cos; i++)
722 REG_WR(bp, base_weight + (0x4 * i), 0);
724 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
726 /******************************************************************************
728 * E3B0 disable will return basicly the values to init values.
730 ******************************************************************************/
731 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
732 const struct link_vars *vars)
734 struct bnx2x *bp = params->bp;
736 if (!CHIP_IS_E3B0(bp)) {
738 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
742 bnx2x_ets_e3b0_nig_disabled(params, vars);
744 bnx2x_ets_e3b0_pbf_disabled(params);
749 /******************************************************************************
751 * Disable will return basicly the values to init values.
753 ******************************************************************************/
754 int bnx2x_ets_disabled(struct link_params *params,
755 struct link_vars *vars)
757 struct bnx2x *bp = params->bp;
758 int bnx2x_status = 0;
760 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
761 bnx2x_ets_e2e3a0_disabled(params);
762 else if (CHIP_IS_E3B0(bp))
763 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
765 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
772 /******************************************************************************
774 * Set the COS mappimg to SP and BW until this point all the COS are not
776 ******************************************************************************/
777 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
778 const struct bnx2x_ets_params *ets_params,
779 const u8 cos_sp_bitmap,
780 const u8 cos_bw_bitmap)
782 struct bnx2x *bp = params->bp;
783 const u8 port = params->port;
784 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
785 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
786 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
787 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
789 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
790 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
792 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
793 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
795 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
796 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
797 nig_cli_subject2wfq_bitmap);
799 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
800 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
801 pbf_cli_subject2wfq_bitmap);
806 /******************************************************************************
808 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
809 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
810 ******************************************************************************/
811 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
813 const u32 min_w_val_nig,
814 const u32 min_w_val_pbf,
819 u32 nig_reg_adress_crd_weight = 0;
820 u32 pbf_reg_adress_crd_weight = 0;
821 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
822 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
823 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
827 nig_reg_adress_crd_weight =
828 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
829 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
830 pbf_reg_adress_crd_weight = (port) ?
831 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
834 nig_reg_adress_crd_weight = (port) ?
835 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
836 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
837 pbf_reg_adress_crd_weight = (port) ?
838 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
841 nig_reg_adress_crd_weight = (port) ?
842 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
843 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
845 pbf_reg_adress_crd_weight = (port) ?
846 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
851 nig_reg_adress_crd_weight =
852 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
853 pbf_reg_adress_crd_weight =
854 PBF_REG_COS3_WEIGHT_P0;
859 nig_reg_adress_crd_weight =
860 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
861 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
866 nig_reg_adress_crd_weight =
867 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
868 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
872 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
874 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
878 /******************************************************************************
880 * Calculate the total BW.A value of 0 isn't legal.
882 ******************************************************************************/
883 static int bnx2x_ets_e3b0_get_total_bw(
884 const struct link_params *params,
885 struct bnx2x_ets_params *ets_params,
888 struct bnx2x *bp = params->bp;
890 u8 is_bw_cos_exist = 0;
893 /* Calculate total BW requested */
894 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
895 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
897 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
898 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
900 /* This is to prevent a state when ramrods
903 ets_params->cos[cos_idx].params.bw_params.bw
907 ets_params->cos[cos_idx].params.bw_params.bw;
911 /* Check total BW is valid */
912 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
913 if (*total_bw == 0) {
915 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
919 "bnx2x_ets_E3B0_config total BW should be 100\n");
920 /* We can handle a case whre the BW isn't 100 this can happen
921 * if the TC are joined.
927 /******************************************************************************
929 * Invalidate all the sp_pri_to_cos.
931 ******************************************************************************/
932 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
935 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
936 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
938 /******************************************************************************
940 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
941 * according to sp_pri_to_cos.
943 ******************************************************************************/
944 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
945 u8 *sp_pri_to_cos, const u8 pri,
948 struct bnx2x *bp = params->bp;
949 const u8 port = params->port;
950 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
951 DCBX_E3B0_MAX_NUM_COS_PORT0;
953 if (pri >= max_num_of_cos) {
954 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
955 "parameter Illegal strict priority\n");
959 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
960 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
961 "parameter There can't be two COS's with "
962 "the same strict pri\n");
966 sp_pri_to_cos[pri] = cos_entry;
971 /******************************************************************************
973 * Returns the correct value according to COS and priority in
974 * the sp_pri_cli register.
976 ******************************************************************************/
977 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
983 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
984 (pri_set + pri_offset));
988 /******************************************************************************
990 * Returns the correct value according to COS and priority in the
991 * sp_pri_cli register for NIG.
993 ******************************************************************************/
994 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
996 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
997 const u8 nig_cos_offset = 3;
998 const u8 nig_pri_offset = 3;
1000 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1004 /******************************************************************************
1006 * Returns the correct value according to COS and priority in the
1007 * sp_pri_cli register for PBF.
1009 ******************************************************************************/
1010 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1012 const u8 pbf_cos_offset = 0;
1013 const u8 pbf_pri_offset = 0;
1015 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1020 /******************************************************************************
1022 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1023 * according to sp_pri_to_cos.(which COS has higher priority)
1025 ******************************************************************************/
1026 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1029 struct bnx2x *bp = params->bp;
1031 const u8 port = params->port;
1032 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1033 u64 pri_cli_nig = 0x210;
1034 u32 pri_cli_pbf = 0x0;
1037 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1038 DCBX_E3B0_MAX_NUM_COS_PORT0;
1040 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1042 /* Set all the strict priority first */
1043 for (i = 0; i < max_num_of_cos; i++) {
1044 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1045 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1047 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1048 "invalid cos entry\n");
1052 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1053 sp_pri_to_cos[i], pri_set);
1055 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1056 sp_pri_to_cos[i], pri_set);
1057 pri_bitmask = 1 << sp_pri_to_cos[i];
1058 /* COS is used remove it from bitmap.*/
1059 if (!(pri_bitmask & cos_bit_to_set)) {
1061 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1062 "invalid There can't be two COS's with"
1063 " the same strict pri\n");
1066 cos_bit_to_set &= ~pri_bitmask;
1071 /* Set all the Non strict priority i= COS*/
1072 for (i = 0; i < max_num_of_cos; i++) {
1073 pri_bitmask = 1 << i;
1074 /* Check if COS was already used for SP */
1075 if (pri_bitmask & cos_bit_to_set) {
1076 /* COS wasn't used for SP */
1077 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1080 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1082 /* COS is used remove it from bitmap.*/
1083 cos_bit_to_set &= ~pri_bitmask;
1088 if (pri_set != max_num_of_cos) {
1089 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1090 "entries were set\n");
1095 /* Only 6 usable clients*/
1096 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1099 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1101 /* Only 9 usable clients*/
1102 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1103 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1105 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1107 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1110 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1115 /******************************************************************************
1117 * Configure the COS to ETS according to BW and SP settings.
1118 ******************************************************************************/
1119 int bnx2x_ets_e3b0_config(const struct link_params *params,
1120 const struct link_vars *vars,
1121 struct bnx2x_ets_params *ets_params)
1123 struct bnx2x *bp = params->bp;
1124 int bnx2x_status = 0;
1125 const u8 port = params->port;
1127 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1128 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1129 u8 cos_bw_bitmap = 0;
1130 u8 cos_sp_bitmap = 0;
1131 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1132 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1133 DCBX_E3B0_MAX_NUM_COS_PORT0;
1136 if (!CHIP_IS_E3B0(bp)) {
1138 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1142 if ((ets_params->num_of_cos > max_num_of_cos)) {
1143 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1144 "isn't supported\n");
1148 /* Prepare sp strict priority parameters*/
1149 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1151 /* Prepare BW parameters*/
1152 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1156 "bnx2x_ets_E3B0_config get_total_bw failed\n");
1160 /* Upper bound is set according to current link speed (min_w_val
1161 * should be the same for upper bound and COS credit val).
1163 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1164 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1167 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1168 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1169 cos_bw_bitmap |= (1 << cos_entry);
1170 /* The function also sets the BW in HW(not the mappin
1173 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1174 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1176 ets_params->cos[cos_entry].params.bw_params.bw,
1178 } else if (bnx2x_cos_state_strict ==
1179 ets_params->cos[cos_entry].state){
1180 cos_sp_bitmap |= (1 << cos_entry);
1182 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1185 ets_params->cos[cos_entry].params.sp_params.pri,
1190 "bnx2x_ets_e3b0_config cos state not valid\n");
1195 "bnx2x_ets_e3b0_config set cos bw failed\n");
1196 return bnx2x_status;
1200 /* Set SP register (which COS has higher priority) */
1201 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1206 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1207 return bnx2x_status;
1210 /* Set client mapping of BW and strict */
1211 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1216 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1217 return bnx2x_status;
1221 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1223 /* ETS disabled configuration */
1224 struct bnx2x *bp = params->bp;
1225 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1226 /* Defines which entries (clients) are subjected to WFQ arbitration
1230 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1231 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1232 * client numbers (WEIGHT_0 does not actually have to represent
1234 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1235 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1237 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1239 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1240 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1241 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1242 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1244 /* ETS mode enabled*/
1245 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1247 /* Defines the number of consecutive slots for the strict priority */
1248 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1249 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1250 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1251 * entry, 4 - COS1 entry.
1252 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1253 * bit4 bit3 bit2 bit1 bit0
1254 * MCP and debug are strict
1256 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1258 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1259 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1260 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1261 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1262 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1265 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1268 /* ETS disabled configuration*/
1269 struct bnx2x *bp = params->bp;
1270 const u32 total_bw = cos0_bw + cos1_bw;
1271 u32 cos0_credit_weight = 0;
1272 u32 cos1_credit_weight = 0;
1274 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1279 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1283 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1285 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1288 bnx2x_ets_bw_limit_common(params);
1290 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1291 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1293 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1294 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1297 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1299 /* ETS disabled configuration*/
1300 struct bnx2x *bp = params->bp;
1303 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1304 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1305 * as strict. Bits 0,1,2 - debug and management entries,
1306 * 3 - COS0 entry, 4 - COS1 entry.
1307 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1308 * bit4 bit3 bit2 bit1 bit0
1309 * MCP and debug are strict
1311 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1312 /* For strict priority entries defines the number of consecutive slots
1313 * for the highest priority.
1315 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1316 /* ETS mode disable */
1317 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1318 /* Defines the number of consecutive slots for the strict priority */
1319 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1321 /* Defines the number of consecutive slots for the strict priority */
1322 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1324 /* Mapping between entry priority to client number (0,1,2 -debug and
1325 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1327 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1328 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1329 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1331 val = (!strict_cos) ? 0x2318 : 0x22E0;
1332 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1337 /******************************************************************/
1339 /******************************************************************/
1340 static void bnx2x_update_pfc_xmac(struct link_params *params,
1341 struct link_vars *vars,
1344 struct bnx2x *bp = params->bp;
1346 u32 pause_val, pfc0_val, pfc1_val;
1348 /* XMAC base adrr */
1349 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1351 /* Initialize pause and pfc registers */
1352 pause_val = 0x18000;
1353 pfc0_val = 0xFFFF8000;
1356 /* No PFC support */
1357 if (!(params->feature_config_flags &
1358 FEATURE_CONFIG_PFC_ENABLED)) {
1360 /* RX flow control - Process pause frame in receive direction
1362 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1363 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1365 /* TX flow control - Send pause packet when buffer is full */
1366 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1367 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1368 } else {/* PFC support */
1369 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1370 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1371 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1372 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1373 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1374 /* Write pause and PFC registers */
1375 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1376 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1377 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1378 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1382 /* Write pause and PFC registers */
1383 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1384 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1385 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1388 /* Set MAC address for source TX Pause/PFC frames */
1389 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1390 ((params->mac_addr[2] << 24) |
1391 (params->mac_addr[3] << 16) |
1392 (params->mac_addr[4] << 8) |
1393 (params->mac_addr[5])));
1394 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1395 ((params->mac_addr[0] << 8) |
1396 (params->mac_addr[1])));
1402 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1403 u32 pfc_frames_sent[2],
1404 u32 pfc_frames_received[2])
1406 /* Read pfc statistic */
1407 struct bnx2x *bp = params->bp;
1408 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1412 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1414 /* PFC received frames */
1415 val_xoff = REG_RD(bp, emac_base +
1416 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1417 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1418 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1419 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1421 pfc_frames_received[0] = val_xon + val_xoff;
1423 /* PFC received sent */
1424 val_xoff = REG_RD(bp, emac_base +
1425 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1426 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1427 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1428 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1430 pfc_frames_sent[0] = val_xon + val_xoff;
1433 /* Read pfc statistic*/
1434 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1435 u32 pfc_frames_sent[2],
1436 u32 pfc_frames_received[2])
1438 /* Read pfc statistic */
1439 struct bnx2x *bp = params->bp;
1441 DP(NETIF_MSG_LINK, "pfc statistic\n");
1446 if (vars->mac_type == MAC_TYPE_EMAC) {
1447 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1448 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1449 pfc_frames_received);
1452 /******************************************************************/
1453 /* MAC/PBF section */
1454 /******************************************************************/
1455 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1458 u32 new_mode, cur_mode;
1460 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1461 * (a value of 49==0x31) and make sure that the AUTO poll is off
1463 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1465 if (USES_WARPCORE(bp))
1466 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1468 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1470 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1471 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1474 new_mode = cur_mode &
1475 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1476 new_mode |= clc_cnt;
1477 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1479 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1480 cur_mode, new_mode);
1481 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1485 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1486 struct link_params *params)
1489 /* Set mdio clock per phy */
1490 for (phy_index = INT_PHY; phy_index < params->num_phys;
1492 bnx2x_set_mdio_clk(bp, params->chip_id,
1493 params->phy[phy_index].mdio_ctrl);
1496 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1498 u32 port4mode_ovwr_val;
1499 /* Check 4-port override enabled */
1500 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1501 if (port4mode_ovwr_val & (1<<0)) {
1502 /* Return 4-port mode override value */
1503 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1505 /* Return 4-port mode from input pin */
1506 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1509 static void bnx2x_emac_init(struct link_params *params,
1510 struct link_vars *vars)
1512 /* reset and unreset the emac core */
1513 struct bnx2x *bp = params->bp;
1514 u8 port = params->port;
1515 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1519 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1520 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1522 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1523 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1525 /* init emac - use read-modify-write */
1526 /* self clear reset */
1527 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1528 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1532 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1533 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1535 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1539 } while (val & EMAC_MODE_RESET);
1541 bnx2x_set_mdio_emac_per_phy(bp, params);
1542 /* Set mac address */
1543 val = ((params->mac_addr[0] << 8) |
1544 params->mac_addr[1]);
1545 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1547 val = ((params->mac_addr[2] << 24) |
1548 (params->mac_addr[3] << 16) |
1549 (params->mac_addr[4] << 8) |
1550 params->mac_addr[5]);
1551 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1554 static void bnx2x_set_xumac_nig(struct link_params *params,
1558 struct bnx2x *bp = params->bp;
1560 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1562 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1564 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1565 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1568 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1570 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1572 struct bnx2x *bp = params->bp;
1573 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1574 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1576 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1578 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1579 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1581 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1582 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1583 /* Disable RX and TX */
1584 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1587 static void bnx2x_umac_enable(struct link_params *params,
1588 struct link_vars *vars, u8 lb)
1591 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1592 struct bnx2x *bp = params->bp;
1594 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1595 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1596 usleep_range(1000, 2000);
1598 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1599 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1601 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1603 /* This register opens the gate for the UMAC despite its name */
1604 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1606 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1607 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1608 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1609 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1610 switch (vars->line_speed) {
1624 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1628 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1629 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1631 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1632 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1634 if (vars->duplex == DUPLEX_HALF)
1635 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1637 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1640 /* Configure UMAC for EEE */
1641 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1642 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1643 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1644 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1645 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1647 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1650 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1651 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1652 ((params->mac_addr[2] << 24) |
1653 (params->mac_addr[3] << 16) |
1654 (params->mac_addr[4] << 8) |
1655 (params->mac_addr[5])));
1656 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1657 ((params->mac_addr[0] << 8) |
1658 (params->mac_addr[1])));
1660 /* Enable RX and TX */
1661 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1662 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1663 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1664 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1667 /* Remove SW Reset */
1668 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1670 /* Check loopback mode */
1672 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1673 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1675 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1676 * length used by the MAC receive logic to check frames.
1678 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1679 bnx2x_set_xumac_nig(params,
1680 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1681 vars->mac_type = MAC_TYPE_UMAC;
1685 /* Define the XMAC mode */
1686 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1688 struct bnx2x *bp = params->bp;
1689 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1691 /* In 4-port mode, need to set the mode only once, so if XMAC is
1692 * already out of reset, it means the mode has already been set,
1693 * and it must not* reset the XMAC again, since it controls both
1697 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1698 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1699 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1701 (REG_RD(bp, MISC_REG_RESET_REG_2) &
1702 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1704 "XMAC already out of reset in 4-port mode\n");
1709 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1710 MISC_REGISTERS_RESET_REG_2_XMAC);
1711 usleep_range(1000, 2000);
1713 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1714 MISC_REGISTERS_RESET_REG_2_XMAC);
1716 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1718 /* Set the number of ports on the system side to up to 2 */
1719 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1721 /* Set the number of ports on the Warp Core to 10G */
1722 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1724 /* Set the number of ports on the system side to 1 */
1725 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1726 if (max_speed == SPEED_10000) {
1728 "Init XMAC to 10G x 1 port per path\n");
1729 /* Set the number of ports on the Warp Core to 10G */
1730 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1733 "Init XMAC to 20G x 2 ports per path\n");
1734 /* Set the number of ports on the Warp Core to 20G */
1735 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1739 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1740 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1741 usleep_range(1000, 2000);
1743 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1744 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1748 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1750 u8 port = params->port;
1751 struct bnx2x *bp = params->bp;
1752 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1755 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1756 MISC_REGISTERS_RESET_REG_2_XMAC) {
1757 /* Send an indication to change the state in the NIG back to XON
1758 * Clearing this bit enables the next set of this bit to get
1761 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1762 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1763 (pfc_ctrl & ~(1<<1)));
1764 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1765 (pfc_ctrl | (1<<1)));
1766 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1767 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1769 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1771 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1772 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1776 static int bnx2x_xmac_enable(struct link_params *params,
1777 struct link_vars *vars, u8 lb)
1780 struct bnx2x *bp = params->bp;
1781 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1783 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1785 bnx2x_xmac_init(params, vars->line_speed);
1787 /* This register determines on which events the MAC will assert
1788 * error on the i/f to the NIG along w/ EOP.
1791 /* This register tells the NIG whether to send traffic to UMAC
1794 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1796 /* When XMAC is in XLGMII mode, disable sending idles for fault
1799 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1800 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1801 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1802 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1803 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1804 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1805 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1806 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1808 /* Set Max packet size */
1809 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1811 /* CRC append for Tx packets */
1812 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1815 bnx2x_update_pfc_xmac(params, vars, 0);
1817 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1818 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1819 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1820 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1822 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1825 /* Enable TX and RX */
1826 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1828 /* Set MAC in XLGMII mode for dual-mode */
1829 if ((vars->line_speed == SPEED_20000) &&
1830 (params->phy[INT_PHY].supported &
1831 SUPPORTED_20000baseKR2_Full))
1832 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1834 /* Check loopback mode */
1836 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1837 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1838 bnx2x_set_xumac_nig(params,
1839 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1841 vars->mac_type = MAC_TYPE_XMAC;
1846 static int bnx2x_emac_enable(struct link_params *params,
1847 struct link_vars *vars, u8 lb)
1849 struct bnx2x *bp = params->bp;
1850 u8 port = params->port;
1851 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1854 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1857 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1858 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1860 /* enable emac and not bmac */
1861 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1864 if (vars->phy_flags & PHY_XGXS_FLAG) {
1865 u32 ser_lane = ((params->lane_config &
1866 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1867 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1869 DP(NETIF_MSG_LINK, "XGXS\n");
1870 /* select the master lanes (out of 0-3) */
1871 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1873 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1875 } else { /* SerDes */
1876 DP(NETIF_MSG_LINK, "SerDes\n");
1878 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1881 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1882 EMAC_RX_MODE_RESET);
1883 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1884 EMAC_TX_MODE_RESET);
1886 /* pause enable/disable */
1887 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1888 EMAC_RX_MODE_FLOW_EN);
1890 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1891 (EMAC_TX_MODE_EXT_PAUSE_EN |
1892 EMAC_TX_MODE_FLOW_EN));
1893 if (!(params->feature_config_flags &
1894 FEATURE_CONFIG_PFC_ENABLED)) {
1895 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1896 bnx2x_bits_en(bp, emac_base +
1897 EMAC_REG_EMAC_RX_MODE,
1898 EMAC_RX_MODE_FLOW_EN);
1900 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1901 bnx2x_bits_en(bp, emac_base +
1902 EMAC_REG_EMAC_TX_MODE,
1903 (EMAC_TX_MODE_EXT_PAUSE_EN |
1904 EMAC_TX_MODE_FLOW_EN));
1906 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1907 EMAC_TX_MODE_FLOW_EN);
1909 /* KEEP_VLAN_TAG, promiscuous */
1910 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1911 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1913 /* Setting this bit causes MAC control frames (except for pause
1914 * frames) to be passed on for processing. This setting has no
1915 * affect on the operation of the pause frames. This bit effects
1916 * all packets regardless of RX Parser packet sorting logic.
1917 * Turn the PFC off to make sure we are in Xon state before
1920 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1921 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1922 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1923 /* Enable PFC again */
1924 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1925 EMAC_REG_RX_PFC_MODE_RX_EN |
1926 EMAC_REG_RX_PFC_MODE_TX_EN |
1927 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1929 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1931 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1933 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1934 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1936 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1939 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1944 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1947 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1949 /* Enable emac for jumbo packets */
1950 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1951 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1952 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1955 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1957 /* Disable the NIG in/out to the bmac */
1958 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1959 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1960 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1962 /* Enable the NIG in/out to the emac */
1963 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1965 if ((params->feature_config_flags &
1966 FEATURE_CONFIG_PFC_ENABLED) ||
1967 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1970 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1971 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1973 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1975 vars->mac_type = MAC_TYPE_EMAC;
1979 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1980 struct link_vars *vars)
1983 struct bnx2x *bp = params->bp;
1984 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1985 NIG_REG_INGRESS_BMAC0_MEM;
1988 if ((!(params->feature_config_flags &
1989 FEATURE_CONFIG_PFC_ENABLED)) &&
1990 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1991 /* Enable BigMAC to react on received Pause packets */
1995 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1999 if (!(params->feature_config_flags &
2000 FEATURE_CONFIG_PFC_ENABLED) &&
2001 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2005 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2008 static void bnx2x_update_pfc_bmac2(struct link_params *params,
2009 struct link_vars *vars,
2012 /* Set rx control: Strip CRC and enable BigMAC to relay
2013 * control packets to the system as well
2016 struct bnx2x *bp = params->bp;
2017 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2018 NIG_REG_INGRESS_BMAC0_MEM;
2021 if ((!(params->feature_config_flags &
2022 FEATURE_CONFIG_PFC_ENABLED)) &&
2023 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
2024 /* Enable BigMAC to react on received Pause packets */
2028 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2033 if (!(params->feature_config_flags &
2034 FEATURE_CONFIG_PFC_ENABLED) &&
2035 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2039 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2041 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2042 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2043 /* Enable PFC RX & TX & STATS and set 8 COS */
2045 wb_data[0] |= (1<<0); /* RX */
2046 wb_data[0] |= (1<<1); /* TX */
2047 wb_data[0] |= (1<<2); /* Force initial Xon */
2048 wb_data[0] |= (1<<3); /* 8 cos */
2049 wb_data[0] |= (1<<5); /* STATS */
2051 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2053 /* Clear the force Xon */
2054 wb_data[0] &= ~(1<<2);
2056 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2057 /* Disable PFC RX & TX & STATS and set 8 COS */
2062 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2064 /* Set Time (based unit is 512 bit time) between automatic
2065 * re-sending of PP packets amd enable automatic re-send of
2066 * Per-Priroity Packet as long as pp_gen is asserted and
2067 * pp_disable is low.
2070 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2071 val |= (1<<16); /* enable automatic re-send */
2075 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2079 val = 0x3; /* Enable RX and TX */
2081 val |= 0x4; /* Local loopback */
2082 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2084 /* When PFC enabled, Pass pause frames towards the NIG. */
2085 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2086 val |= ((1<<6)|(1<<5));
2090 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2093 /******************************************************************************
2095 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2096 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2097 ******************************************************************************/
2098 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2100 u32 priority_mask, u8 port)
2102 u32 nig_reg_rx_priority_mask_add = 0;
2104 switch (cos_entry) {
2106 nig_reg_rx_priority_mask_add = (port) ?
2107 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2108 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2111 nig_reg_rx_priority_mask_add = (port) ?
2112 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2113 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2116 nig_reg_rx_priority_mask_add = (port) ?
2117 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2118 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2123 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2128 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2133 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2137 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2141 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2143 struct bnx2x *bp = params->bp;
2145 REG_WR(bp, params->shmem_base +
2146 offsetof(struct shmem_region,
2147 port_mb[params->port].link_status), link_status);
2150 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2152 struct bnx2x *bp = params->bp;
2154 if (SHMEM2_HAS(bp, link_attr_sync))
2155 REG_WR(bp, params->shmem2_base +
2156 offsetof(struct shmem2_region,
2157 link_attr_sync[params->port]), link_attr);
2160 static void bnx2x_update_pfc_nig(struct link_params *params,
2161 struct link_vars *vars,
2162 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2164 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2165 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2166 u32 pkt_priority_to_cos = 0;
2167 struct bnx2x *bp = params->bp;
2168 u8 port = params->port;
2170 int set_pfc = params->feature_config_flags &
2171 FEATURE_CONFIG_PFC_ENABLED;
2172 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2174 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2175 * MAC control frames (that are not pause packets)
2176 * will be forwarded to the XCM.
2178 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2179 NIG_REG_LLH0_XCM_MASK);
2180 /* NIG params will override non PFC params, since it's possible to
2181 * do transition from PFC to SAFC
2191 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2192 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2197 llfc_out_en = nig_params->llfc_out_en;
2198 llfc_enable = nig_params->llfc_enable;
2199 pause_enable = nig_params->pause_enable;
2200 } else /* Default non PFC mode - PAUSE */
2203 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2204 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2209 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2210 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2211 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2212 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2213 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2214 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2215 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2216 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2218 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2219 NIG_REG_PPP_ENABLE_0, ppp_enable);
2221 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2222 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2224 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2225 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2227 /* Output enable for RX_XCM # IF */
2228 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2229 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2231 /* HW PFC TX enable */
2232 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2233 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2237 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2239 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2240 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2241 nig_params->rx_cos_priority_mask[i], port);
2243 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2244 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2245 nig_params->llfc_high_priority_classes);
2247 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2248 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2249 nig_params->llfc_low_priority_classes);
2251 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2252 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2253 pkt_priority_to_cos);
2256 int bnx2x_update_pfc(struct link_params *params,
2257 struct link_vars *vars,
2258 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2260 /* The PFC and pause are orthogonal to one another, meaning when
2261 * PFC is enabled, the pause are disabled, and when PFC is
2262 * disabled, pause are set according to the pause result.
2265 struct bnx2x *bp = params->bp;
2266 int bnx2x_status = 0;
2267 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2269 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2270 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2272 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2274 bnx2x_update_mng(params, vars->link_status);
2276 /* Update NIG params */
2277 bnx2x_update_pfc_nig(params, vars, pfc_params);
2280 return bnx2x_status;
2282 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2284 if (CHIP_IS_E3(bp)) {
2285 if (vars->mac_type == MAC_TYPE_XMAC)
2286 bnx2x_update_pfc_xmac(params, vars, 0);
2288 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2290 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2292 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2293 bnx2x_emac_enable(params, vars, 0);
2294 return bnx2x_status;
2297 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2299 bnx2x_update_pfc_bmac1(params, vars);
2302 if ((params->feature_config_flags &
2303 FEATURE_CONFIG_PFC_ENABLED) ||
2304 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2306 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2308 return bnx2x_status;
2311 static int bnx2x_bmac1_enable(struct link_params *params,
2312 struct link_vars *vars,
2315 struct bnx2x *bp = params->bp;
2316 u8 port = params->port;
2317 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2318 NIG_REG_INGRESS_BMAC0_MEM;
2322 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2327 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2331 wb_data[0] = ((params->mac_addr[2] << 24) |
2332 (params->mac_addr[3] << 16) |
2333 (params->mac_addr[4] << 8) |
2334 params->mac_addr[5]);
2335 wb_data[1] = ((params->mac_addr[0] << 8) |
2336 params->mac_addr[1]);
2337 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2343 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2347 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2350 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2352 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2354 bnx2x_update_pfc_bmac1(params, vars);
2357 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2359 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2361 /* Set cnt max size */
2362 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2364 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2366 /* Configure SAFC */
2367 wb_data[0] = 0x1000200;
2369 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2375 static int bnx2x_bmac2_enable(struct link_params *params,
2376 struct link_vars *vars,
2379 struct bnx2x *bp = params->bp;
2380 u8 port = params->port;
2381 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2382 NIG_REG_INGRESS_BMAC0_MEM;
2385 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2389 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2392 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2395 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2401 wb_data[0] = ((params->mac_addr[2] << 24) |
2402 (params->mac_addr[3] << 16) |
2403 (params->mac_addr[4] << 8) |
2404 params->mac_addr[5]);
2405 wb_data[1] = ((params->mac_addr[0] << 8) |
2406 params->mac_addr[1]);
2407 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2412 /* Configure SAFC */
2413 wb_data[0] = 0x1000200;
2415 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2420 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2422 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2426 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2428 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2430 /* Set cnt max size */
2431 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2433 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2435 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2440 static int bnx2x_bmac_enable(struct link_params *params,
2441 struct link_vars *vars,
2442 u8 is_lb, u8 reset_bmac)
2445 u8 port = params->port;
2446 struct bnx2x *bp = params->bp;
2448 /* Reset and unreset the BigMac */
2450 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2451 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2452 usleep_range(1000, 2000);
2455 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2456 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2458 /* Enable access for bmac registers */
2459 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2461 /* Enable BMAC according to BMAC type*/
2463 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2465 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2466 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2467 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2468 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2470 if ((params->feature_config_flags &
2471 FEATURE_CONFIG_PFC_ENABLED) ||
2472 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2474 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2475 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2476 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2477 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2478 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2479 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2481 vars->mac_type = MAC_TYPE_BMAC;
2485 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2487 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2488 NIG_REG_INGRESS_BMAC0_MEM;
2490 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2493 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2495 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2496 /* Only if the bmac is out of reset */
2497 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2498 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2500 /* Clear Rx Enable bit in BMAC_CONTROL register */
2501 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2503 wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2505 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2506 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2507 usleep_range(1000, 2000);
2511 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2514 struct bnx2x *bp = params->bp;
2515 u8 port = params->port;
2520 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2522 /* Wait for init credit */
2523 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2524 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2525 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2527 while ((init_crd != crd) && count) {
2528 usleep_range(5000, 10000);
2529 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2532 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2533 if (init_crd != crd) {
2534 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2539 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2540 line_speed == SPEED_10 ||
2541 line_speed == SPEED_100 ||
2542 line_speed == SPEED_1000 ||
2543 line_speed == SPEED_2500) {
2544 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2545 /* Update threshold */
2546 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2547 /* Update init credit */
2548 init_crd = 778; /* (800-18-4) */
2551 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2553 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2554 /* Update threshold */
2555 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2556 /* Update init credit */
2557 switch (line_speed) {
2559 init_crd = thresh + 553 - 22;
2562 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2567 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2568 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2569 line_speed, init_crd);
2571 /* Probe the credit changes */
2572 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2573 usleep_range(5000, 10000);
2574 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2577 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2582 * bnx2x_get_emac_base - retrive emac base address
2584 * @bp: driver handle
2585 * @mdc_mdio_access: access type
2588 * This function selects the MDC/MDIO access (through emac0 or
2589 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2590 * phy has a default access mode, which could also be overridden
2591 * by nvram configuration. This parameter, whether this is the
2592 * default phy configuration, or the nvram overrun
2593 * configuration, is passed here as mdc_mdio_access and selects
2594 * the emac_base for the CL45 read/writes operations
2596 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2597 u32 mdc_mdio_access, u8 port)
2600 switch (mdc_mdio_access) {
2601 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2603 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2604 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2605 emac_base = GRCBASE_EMAC1;
2607 emac_base = GRCBASE_EMAC0;
2609 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2610 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2611 emac_base = GRCBASE_EMAC0;
2613 emac_base = GRCBASE_EMAC1;
2615 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2616 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2618 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2619 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2628 /******************************************************************/
2629 /* CL22 access functions */
2630 /******************************************************************/
2631 static int bnx2x_cl22_write(struct bnx2x *bp,
2632 struct bnx2x_phy *phy,
2638 /* Switch to CL22 */
2639 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2640 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2641 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2644 tmp = ((phy->addr << 21) | (reg << 16) | val |
2645 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2646 EMAC_MDIO_COMM_START_BUSY);
2647 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2649 for (i = 0; i < 50; i++) {
2652 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2653 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2658 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2659 DP(NETIF_MSG_LINK, "write phy register failed\n");
2662 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2666 static int bnx2x_cl22_read(struct bnx2x *bp,
2667 struct bnx2x_phy *phy,
2668 u16 reg, u16 *ret_val)
2674 /* Switch to CL22 */
2675 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2676 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2677 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2680 val = ((phy->addr << 21) | (reg << 16) |
2681 EMAC_MDIO_COMM_COMMAND_READ_22 |
2682 EMAC_MDIO_COMM_START_BUSY);
2683 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2685 for (i = 0; i < 50; i++) {
2688 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2689 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2690 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2695 if (val & EMAC_MDIO_COMM_START_BUSY) {
2696 DP(NETIF_MSG_LINK, "read phy register failed\n");
2701 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2705 /******************************************************************/
2706 /* CL45 access functions */
2707 /******************************************************************/
2708 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2709 u8 devad, u16 reg, u16 *ret_val)
2715 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2716 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2717 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2718 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2721 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2722 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2723 EMAC_MDIO_STATUS_10MB);
2725 val = ((phy->addr << 21) | (devad << 16) | reg |
2726 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2727 EMAC_MDIO_COMM_START_BUSY);
2728 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2730 for (i = 0; i < 50; i++) {
2733 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2734 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2739 if (val & EMAC_MDIO_COMM_START_BUSY) {
2740 DP(NETIF_MSG_LINK, "read phy register failed\n");
2741 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2746 val = ((phy->addr << 21) | (devad << 16) |
2747 EMAC_MDIO_COMM_COMMAND_READ_45 |
2748 EMAC_MDIO_COMM_START_BUSY);
2749 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2751 for (i = 0; i < 50; i++) {
2754 val = REG_RD(bp, phy->mdio_ctrl +
2755 EMAC_REG_EMAC_MDIO_COMM);
2756 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2757 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2761 if (val & EMAC_MDIO_COMM_START_BUSY) {
2762 DP(NETIF_MSG_LINK, "read phy register failed\n");
2763 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2768 /* Work around for E3 A0 */
2769 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2770 phy->flags ^= FLAGS_DUMMY_READ;
2771 if (phy->flags & FLAGS_DUMMY_READ) {
2773 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2777 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2778 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2779 EMAC_MDIO_STATUS_10MB);
2783 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2784 u8 devad, u16 reg, u16 val)
2790 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2791 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2792 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2793 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2796 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2797 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2798 EMAC_MDIO_STATUS_10MB);
2801 tmp = ((phy->addr << 21) | (devad << 16) | reg |
2802 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2803 EMAC_MDIO_COMM_START_BUSY);
2804 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2806 for (i = 0; i < 50; i++) {
2809 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2810 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2815 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2816 DP(NETIF_MSG_LINK, "write phy register failed\n");
2817 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2821 tmp = ((phy->addr << 21) | (devad << 16) | val |
2822 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2823 EMAC_MDIO_COMM_START_BUSY);
2824 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2826 for (i = 0; i < 50; i++) {
2829 tmp = REG_RD(bp, phy->mdio_ctrl +
2830 EMAC_REG_EMAC_MDIO_COMM);
2831 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2836 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2837 DP(NETIF_MSG_LINK, "write phy register failed\n");
2838 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2842 /* Work around for E3 A0 */
2843 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2844 phy->flags ^= FLAGS_DUMMY_READ;
2845 if (phy->flags & FLAGS_DUMMY_READ) {
2847 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2850 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2851 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2852 EMAC_MDIO_STATUS_10MB);
2856 /******************************************************************/
2858 /******************************************************************/
2859 static u8 bnx2x_eee_has_cap(struct link_params *params)
2861 struct bnx2x *bp = params->bp;
2863 if (REG_RD(bp, params->shmem2_base) <=
2864 offsetof(struct shmem2_region, eee_status[params->port]))
2870 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2872 switch (nvram_mode) {
2873 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2874 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2876 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2877 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2879 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2880 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2890 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2892 switch (idle_timer) {
2893 case EEE_MODE_NVRAM_BALANCED_TIME:
2894 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2896 case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2897 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2899 case EEE_MODE_NVRAM_LATENCY_TIME:
2900 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2903 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2910 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2912 u32 eee_mode, eee_idle;
2913 struct bnx2x *bp = params->bp;
2915 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2916 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2917 /* time value in eee_mode --> used directly*/
2918 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2920 /* hsi value in eee_mode --> time */
2921 if (bnx2x_eee_nvram_to_time(params->eee_mode &
2922 EEE_MODE_NVRAM_MASK,
2927 /* hsi values in nvram --> time*/
2928 eee_mode = ((REG_RD(bp, params->shmem_base +
2929 offsetof(struct shmem_region, dev_info.
2930 port_feature_config[params->port].
2932 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2933 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2935 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2942 static int bnx2x_eee_set_timers(struct link_params *params,
2943 struct link_vars *vars)
2945 u32 eee_idle = 0, eee_mode;
2946 struct bnx2x *bp = params->bp;
2948 eee_idle = bnx2x_eee_calc_timer(params);
2951 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2953 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2954 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2955 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2956 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2960 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2961 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2962 /* eee_idle in 1u --> eee_status in 16u */
2964 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2965 SHMEM_EEE_TIME_OUTPUT_BIT;
2967 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2969 vars->eee_status |= eee_mode;
2975 static int bnx2x_eee_initial_config(struct link_params *params,
2976 struct link_vars *vars, u8 mode)
2978 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2980 /* Propogate params' bits --> vars (for migration exposure) */
2981 if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2982 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2984 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2986 if (params->eee_mode & EEE_MODE_ADV_LPI)
2987 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2989 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2991 return bnx2x_eee_set_timers(params, vars);
2994 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2995 struct link_params *params,
2996 struct link_vars *vars)
2998 struct bnx2x *bp = params->bp;
3000 /* Make Certain LPI is disabled */
3001 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3003 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3005 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3010 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
3011 struct link_params *params,
3012 struct link_vars *vars, u8 modes)
3014 struct bnx2x *bp = params->bp;
3017 /* Mask events preventing LPI generation */
3018 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3020 if (modes & SHMEM_EEE_10G_ADV) {
3021 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
3024 if (modes & SHMEM_EEE_1G_ADV) {
3025 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
3029 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3031 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3032 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3037 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3039 struct bnx2x *bp = params->bp;
3041 if (bnx2x_eee_has_cap(params))
3042 REG_WR(bp, params->shmem2_base +
3043 offsetof(struct shmem2_region,
3044 eee_status[params->port]), eee_status);
3047 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3048 struct link_params *params,
3049 struct link_vars *vars)
3051 struct bnx2x *bp = params->bp;
3052 u16 adv = 0, lp = 0;
3056 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3057 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3060 lp_adv |= SHMEM_EEE_100M_ADV;
3062 if (vars->line_speed == SPEED_100)
3064 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3068 lp_adv |= SHMEM_EEE_1G_ADV;
3070 if (vars->line_speed == SPEED_1000)
3072 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3076 lp_adv |= SHMEM_EEE_10G_ADV;
3078 if (vars->line_speed == SPEED_10000)
3080 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3084 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3085 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3088 DP(NETIF_MSG_LINK, "EEE is active\n");
3089 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3094 /******************************************************************/
3095 /* BSC access functions from E3 */
3096 /******************************************************************/
3097 static void bnx2x_bsc_module_sel(struct link_params *params)
3100 u32 board_cfg, sfp_ctrl;
3101 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3102 struct bnx2x *bp = params->bp;
3103 u8 port = params->port;
3104 /* Read I2C output PINs */
3105 board_cfg = REG_RD(bp, params->shmem_base +
3106 offsetof(struct shmem_region,
3107 dev_info.shared_hw_config.board));
3108 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3109 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3110 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3112 /* Read I2C output value */
3113 sfp_ctrl = REG_RD(bp, params->shmem_base +
3114 offsetof(struct shmem_region,
3115 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3116 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3117 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3118 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3119 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3120 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3123 static int bnx2x_bsc_read(struct link_params *params,
3124 struct bnx2x_phy *phy,
3133 struct bnx2x *bp = params->bp;
3135 if (xfer_cnt > 16) {
3136 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3140 bnx2x_bsc_module_sel(params);
3142 xfer_cnt = 16 - lc_addr;
3144 /* Enable the engine */
3145 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3146 val |= MCPR_IMC_COMMAND_ENABLE;
3147 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3149 /* Program slave device ID */
3150 val = (sl_devid << 16) | sl_addr;
3151 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3153 /* Start xfer with 0 byte to update the address pointer ???*/
3154 val = (MCPR_IMC_COMMAND_ENABLE) |
3155 (MCPR_IMC_COMMAND_WRITE_OP <<
3156 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3157 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3158 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3160 /* Poll for completion */
3162 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3163 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3165 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3167 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3176 /* Start xfer with read op */
3177 val = (MCPR_IMC_COMMAND_ENABLE) |
3178 (MCPR_IMC_COMMAND_READ_OP <<
3179 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3180 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3182 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3184 /* Poll for completion */
3186 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3187 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3189 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3191 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3199 for (i = (lc_addr >> 2); i < 4; i++) {
3200 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3202 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3203 ((data_array[i] & 0x0000ff00) << 8) |
3204 ((data_array[i] & 0x00ff0000) >> 8) |
3205 ((data_array[i] & 0xff000000) >> 24);
3211 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3212 u8 devad, u16 reg, u16 or_val)
3215 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3216 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3219 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3220 struct bnx2x_phy *phy,
3221 u8 devad, u16 reg, u16 and_val)
3224 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3225 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3228 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3229 u8 devad, u16 reg, u16 *ret_val)
3232 /* Probe for the phy according to the given phy_addr, and execute
3233 * the read request on it
3235 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3236 if (params->phy[phy_index].addr == phy_addr) {
3237 return bnx2x_cl45_read(params->bp,
3238 ¶ms->phy[phy_index], devad,
3245 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3246 u8 devad, u16 reg, u16 val)
3249 /* Probe for the phy according to the given phy_addr, and execute
3250 * the write request on it
3252 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3253 if (params->phy[phy_index].addr == phy_addr) {
3254 return bnx2x_cl45_write(params->bp,
3255 ¶ms->phy[phy_index], devad,
3261 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3262 struct link_params *params)
3265 struct bnx2x *bp = params->bp;
3266 u32 path_swap, path_swap_ovr;
3270 port = params->port;
3272 if (bnx2x_is_4_port_mode(bp)) {
3273 u32 port_swap, port_swap_ovr;
3275 /* Figure out path swap value */
3276 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3277 if (path_swap_ovr & 0x1)
3278 path_swap = (path_swap_ovr & 0x2);
3280 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3285 /* Figure out port swap value */
3286 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3287 if (port_swap_ovr & 0x1)
3288 port_swap = (port_swap_ovr & 0x2);
3290 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3295 lane = (port<<1) + path;
3296 } else { /* Two port mode - no port swap */
3298 /* Figure out path swap value */
3300 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3301 if (path_swap_ovr & 0x1) {
3302 path_swap = (path_swap_ovr & 0x2);
3305 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3315 static void bnx2x_set_aer_mmd(struct link_params *params,
3316 struct bnx2x_phy *phy)
3319 u16 offset, aer_val;
3320 struct bnx2x *bp = params->bp;
3321 ser_lane = ((params->lane_config &
3322 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3323 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3325 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3326 (phy->addr + ser_lane) : 0;
3328 if (USES_WARPCORE(bp)) {
3329 aer_val = bnx2x_get_warpcore_lane(phy, params);
3330 /* In Dual-lane mode, two lanes are joined together,
3331 * so in order to configure them, the AER broadcast method is
3333 * 0x200 is the broadcast address for lanes 0,1
3334 * 0x201 is the broadcast address for lanes 2,3
3336 if (phy->flags & FLAGS_WC_DUAL_MODE)
3337 aer_val = (aer_val >> 1) | 0x200;
3338 } else if (CHIP_IS_E2(bp))
3339 aer_val = 0x3800 + offset - 1;
3341 aer_val = 0x3800 + offset;
3343 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3344 MDIO_AER_BLOCK_AER_REG, aer_val);
3348 /******************************************************************/
3349 /* Internal phy section */
3350 /******************************************************************/
3352 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3354 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3357 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3358 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3360 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3363 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3366 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3370 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3372 val = SERDES_RESET_BITS << (port*16);
3374 /* Reset and unreset the SerDes/XGXS */
3375 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3377 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3379 bnx2x_set_serdes_access(bp, port);
3381 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3382 DEFAULT_PHY_DEV_ADDR);
3385 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3386 struct link_params *params,
3389 struct bnx2x *bp = params->bp;
3392 /* Set correct devad */
3393 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3394 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3400 static void bnx2x_xgxs_deassert(struct link_params *params)
3402 struct bnx2x *bp = params->bp;
3405 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3406 port = params->port;
3408 val = XGXS_RESET_BITS << (port*16);
3410 /* Reset and unreset the SerDes/XGXS */
3411 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3413 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3414 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params,
3418 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3419 struct link_params *params, u16 *ieee_fc)
3421 struct bnx2x *bp = params->bp;
3422 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3423 /* Resolve pause mode and advertisement Please refer to Table
3424 * 28B-3 of the 802.3ab-1999 spec
3427 switch (phy->req_flow_ctrl) {
3428 case BNX2X_FLOW_CTRL_AUTO:
3429 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3430 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3433 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3436 case BNX2X_FLOW_CTRL_TX:
3437 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3440 case BNX2X_FLOW_CTRL_RX:
3441 case BNX2X_FLOW_CTRL_BOTH:
3442 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3445 case BNX2X_FLOW_CTRL_NONE:
3447 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3450 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3453 static void set_phy_vars(struct link_params *params,
3454 struct link_vars *vars)
3456 struct bnx2x *bp = params->bp;
3457 u8 actual_phy_idx, phy_index, link_cfg_idx;
3458 u8 phy_config_swapped = params->multi_phy_config &
3459 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3460 for (phy_index = INT_PHY; phy_index < params->num_phys;
3462 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3463 actual_phy_idx = phy_index;
3464 if (phy_config_swapped) {
3465 if (phy_index == EXT_PHY1)
3466 actual_phy_idx = EXT_PHY2;
3467 else if (phy_index == EXT_PHY2)
3468 actual_phy_idx = EXT_PHY1;
3470 params->phy[actual_phy_idx].req_flow_ctrl =
3471 params->req_flow_ctrl[link_cfg_idx];
3473 params->phy[actual_phy_idx].req_line_speed =
3474 params->req_line_speed[link_cfg_idx];
3476 params->phy[actual_phy_idx].speed_cap_mask =
3477 params->speed_cap_mask[link_cfg_idx];
3479 params->phy[actual_phy_idx].req_duplex =
3480 params->req_duplex[link_cfg_idx];
3482 if (params->req_line_speed[link_cfg_idx] ==
3484 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3486 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3487 " speed_cap_mask %x\n",
3488 params->phy[actual_phy_idx].req_flow_ctrl,
3489 params->phy[actual_phy_idx].req_line_speed,
3490 params->phy[actual_phy_idx].speed_cap_mask);
3494 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3495 struct bnx2x_phy *phy,
3496 struct link_vars *vars)
3499 struct bnx2x *bp = params->bp;
3500 /* Read modify write pause advertizing */
3501 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3503 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3505 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3506 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3507 if ((vars->ieee_fc &
3508 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3509 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3510 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3512 if ((vars->ieee_fc &
3513 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3514 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3515 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3517 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3518 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3521 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3523 switch (pause_result) { /* ASYM P ASYM P */
3524 case 0xb: /* 1 0 1 1 */
3525 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3528 case 0xe: /* 1 1 1 0 */
3529 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3532 case 0x5: /* 0 1 0 1 */
3533 case 0x7: /* 0 1 1 1 */
3534 case 0xd: /* 1 1 0 1 */
3535 case 0xf: /* 1 1 1 1 */
3536 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3542 if (pause_result & (1<<0))
3543 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3544 if (pause_result & (1<<1))
3545 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3549 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3550 struct link_params *params,
3551 struct link_vars *vars)
3553 u16 ld_pause; /* local */
3554 u16 lp_pause; /* link partner */
3556 struct bnx2x *bp = params->bp;
3557 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3558 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3559 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3560 } else if (CHIP_IS_E3(bp) &&
3561 SINGLE_MEDIA_DIRECT(params)) {
3562 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3563 u16 gp_status, gp_mask;
3564 bnx2x_cl45_read(bp, phy,
3565 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3567 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3568 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3570 if ((gp_status & gp_mask) == gp_mask) {
3571 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3572 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3573 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3574 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3576 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3577 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3578 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3579 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3580 ld_pause = ((ld_pause &
3581 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3583 lp_pause = ((lp_pause &
3584 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3588 bnx2x_cl45_read(bp, phy,
3590 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3591 bnx2x_cl45_read(bp, phy,
3593 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3595 pause_result = (ld_pause &
3596 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3597 pause_result |= (lp_pause &
3598 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3599 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3600 bnx2x_pause_resolve(vars, pause_result);
3604 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3605 struct link_params *params,
3606 struct link_vars *vars)
3609 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3610 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3611 /* Update the advertised flow-controled of LD/LP in AN */
3612 if (phy->req_line_speed == SPEED_AUTO_NEG)
3613 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3614 /* But set the flow-control result as the requested one */
3615 vars->flow_ctrl = phy->req_flow_ctrl;
3616 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3617 vars->flow_ctrl = params->req_fc_auto_adv;
3618 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3620 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3624 /******************************************************************/
3625 /* Warpcore section */
3626 /******************************************************************/
3627 /* The init_internal_warpcore should mirror the xgxs,
3628 * i.e. reset the lane (if needed), set aer for the
3629 * init configuration, and set/clear SGMII flag. Internal
3630 * phy init is done purely in phy_init stage.
3632 #define WC_TX_DRIVER(post2, idriver, ipre) \
3633 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3634 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3635 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3637 #define WC_TX_FIR(post, main, pre) \
3638 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3639 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3640 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3642 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3643 struct link_params *params,
3644 struct link_vars *vars)
3646 struct bnx2x *bp = params->bp;
3648 static struct bnx2x_reg_set reg_set[] = {
3649 /* Step 1 - Program the TX/RX alignment markers */
3650 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3651 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3652 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3653 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3654 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3655 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3656 /* Step 2 - Configure the NP registers */
3657 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3658 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3659 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3660 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3661 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3662 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3663 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3664 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3665 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3667 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3669 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3670 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3672 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3673 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3676 /* Start KR2 work-around timer which handles BCM8073 link-parner */
3677 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3678 bnx2x_update_link_attr(params, vars->link_attr_sync);
3681 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3682 struct link_params *params)
3684 struct bnx2x *bp = params->bp;
3686 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3687 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3688 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3689 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3690 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3693 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3694 struct link_params *params)
3696 /* Restart autoneg on the leading lane only */
3697 struct bnx2x *bp = params->bp;
3698 u16 lane = bnx2x_get_warpcore_lane(phy, params);
3699 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3700 MDIO_AER_BLOCK_AER_REG, lane);
3701 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3702 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3705 bnx2x_set_aer_mmd(params, phy);
3708 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3709 struct link_params *params,
3710 struct link_vars *vars) {
3711 u16 lane, i, cl72_ctrl, an_adv = 0;
3713 struct bnx2x *bp = params->bp;
3714 static struct bnx2x_reg_set reg_set[] = {
3715 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3716 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3717 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3718 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3719 /* Disable Autoneg: re-enable it after adv is done. */
3720 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3721 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3722 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3724 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3725 /* Set to default registers that may be overriden by 10G force */
3726 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3727 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3730 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3731 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3732 cl72_ctrl &= 0x08ff;
3733 cl72_ctrl |= 0x3800;
3734 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3735 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3737 /* Check adding advertisement for 1G KX */
3738 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3739 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3740 (vars->line_speed == SPEED_1000)) {
3741 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3744 /* Enable CL37 1G Parallel Detect */
3745 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3746 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3748 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3749 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3750 (vars->line_speed == SPEED_10000)) {
3751 /* Check adding advertisement for 10G KR */
3753 /* Enable 10G Parallel Detect */
3754 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3755 MDIO_AER_BLOCK_AER_REG, 0);
3757 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3758 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3759 bnx2x_set_aer_mmd(params, phy);
3760 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3763 /* Set Transmit PMD settings */
3764 lane = bnx2x_get_warpcore_lane(phy, params);
3765 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3766 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3767 WC_TX_DRIVER(0x02, 0x06, 0x09));
3768 /* Configure the next lane if dual mode */
3769 if (phy->flags & FLAGS_WC_DUAL_MODE)
3770 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3771 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3772 WC_TX_DRIVER(0x02, 0x06, 0x09));
3773 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3774 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3776 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3777 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3780 /* Advertised speeds */
3781 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3782 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3784 /* Advertised and set FEC (Forward Error Correction) */
3785 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3786 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3787 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3788 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3790 /* Enable CL37 BAM */
3791 if (REG_RD(bp, params->shmem_base +
3792 offsetof(struct shmem_region, dev_info.
3793 port_hw_config[params->port].default_cfg)) &
3794 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3795 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3796 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3798 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3801 /* Advertise pause */
3802 bnx2x_ext_phy_set_pause(params, phy, vars);
3803 /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
3805 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3806 MDIO_WC_REG_UC_INFO_B1_VERSION, &ucode_ver);
3807 if (ucode_ver < 0xd108) {
3808 DP(NETIF_MSG_LINK, "Enable AN KR work-around. WC ver:0x%x\n",
3810 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3812 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3813 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3815 /* Over 1G - AN local device user page 1 */
3816 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3817 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3819 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3820 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3821 (phy->req_line_speed == SPEED_20000)) {
3823 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3824 MDIO_AER_BLOCK_AER_REG, lane);
3826 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3827 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3830 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3831 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3832 bnx2x_set_aer_mmd(params, phy);
3834 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3837 /* Enable Autoneg: only on the main lane */
3838 bnx2x_warpcore_restart_AN_KR(phy, params);
3841 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3842 struct link_params *params,
3843 struct link_vars *vars)
3845 struct bnx2x *bp = params->bp;
3847 static struct bnx2x_reg_set reg_set[] = {
3848 /* Disable Autoneg */
3849 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3850 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3852 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3853 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3854 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3855 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3856 /* Leave cl72 training enable, needed for KR */
3857 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3860 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3861 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3864 lane = bnx2x_get_warpcore_lane(phy, params);
3865 /* Global registers */
3866 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3867 MDIO_AER_BLOCK_AER_REG, 0);
3868 /* Disable CL36 PCS Tx */
3869 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3870 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3871 val16 &= ~(0x0011 << lane);
3872 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3873 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3875 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3876 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3877 val16 |= (0x0303 << (lane << 1));
3878 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3879 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3881 bnx2x_set_aer_mmd(params, phy);
3882 /* Set speed via PMA/PMD register */
3883 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3884 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3886 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3887 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3889 /* Enable encoded forced speed */
3890 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3891 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3893 /* Turn TX scramble payload only the 64/66 scrambler */
3894 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3895 MDIO_WC_REG_TX66_CONTROL, 0x9);
3897 /* Turn RX scramble payload only the 64/66 scrambler */
3898 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3899 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3901 /* Set and clear loopback to cause a reset to 64/66 decoder */
3902 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3903 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3904 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3905 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3909 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3910 struct link_params *params,
3913 struct bnx2x *bp = params->bp;
3914 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3915 u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3917 /* Hold rxSeqStart */
3918 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3919 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3921 /* Hold tx_fifo_reset */
3922 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3923 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3925 /* Disable CL73 AN */
3926 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3928 /* Disable 100FX Enable and Auto-Detect */
3929 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3930 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3932 /* Disable 100FX Idle detect */
3933 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3934 MDIO_WC_REG_FX100_CTRL3, 0x0080);
3936 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3937 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3938 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3940 /* Turn off auto-detect & fiber mode */
3941 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3942 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3945 /* Set filter_force_link, disable_false_link and parallel_detect */
3946 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3947 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3948 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3949 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3950 ((val | 0x0006) & 0xFFFE));
3953 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3954 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3956 misc1_val &= ~(0x1f);
3960 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3961 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3963 cfg_tap_val = REG_RD(bp, params->shmem_base +
3964 offsetof(struct shmem_region, dev_info.
3965 port_hw_config[params->port].
3968 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
3970 tx_drv_brdct = (cfg_tap_val &
3971 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
3972 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
3976 /* TAP values are controlled by nvram, if value there isn't 0 */
3978 tap_val = (u16)tx_equal;
3980 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
3983 tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct,
3986 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
3988 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3989 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3991 /* Set Transmit PMD settings */
3992 lane = bnx2x_get_warpcore_lane(phy, params);
3993 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3994 MDIO_WC_REG_TX_FIR_TAP,
3995 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3996 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3997 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4000 /* Enable fiber mode, enable and invert sig_det */
4001 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4002 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4004 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4005 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4006 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4008 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4010 /* 10G XFI Full Duplex */
4011 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4012 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4014 /* Release tx_fifo_reset */
4015 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4016 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4018 /* Release rxSeqStart */
4019 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4020 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4023 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4024 struct link_params *params)
4027 struct bnx2x *bp = params->bp;
4028 /* Set global registers, so set AER lane to 0 */
4029 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4030 MDIO_AER_BLOCK_AER_REG, 0);
4032 /* Disable sequencer */
4033 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4034 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4036 bnx2x_set_aer_mmd(params, phy);
4038 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4039 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4040 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4041 MDIO_AN_REG_CTRL, 0);
4043 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4044 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4047 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4048 MDIO_WC_REG_CL73_USERB0_CTRL, val);
4050 /* Set 20G KR2 force speed */
4051 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4052 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4054 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4055 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4057 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4058 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4061 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4062 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4063 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4064 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4066 /* Enable sequencer (over lane 0) */
4067 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4068 MDIO_AER_BLOCK_AER_REG, 0);
4070 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4071 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4073 bnx2x_set_aer_mmd(params, phy);
4076 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4077 struct bnx2x_phy *phy,
4080 /* Rx0 anaRxControl1G */
4081 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4082 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4084 /* Rx2 anaRxControl1G */
4085 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4086 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4088 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4089 MDIO_WC_REG_RX66_SCW0, 0xE070);
4091 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4092 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4094 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4095 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4097 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4098 MDIO_WC_REG_RX66_SCW3, 0x8090);
4100 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4101 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4103 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4104 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4106 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4107 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4109 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4110 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4112 /* Serdes Digital Misc1 */
4113 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4114 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4116 /* Serdes Digital4 Misc3 */
4117 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4118 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4120 /* Set Transmit PMD settings */
4121 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4122 MDIO_WC_REG_TX_FIR_TAP,
4123 (WC_TX_FIR(0x12, 0x2d, 0x00) |
4124 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4125 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4126 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4127 WC_TX_DRIVER(0x02, 0x02, 0x02));
4130 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4131 struct link_params *params,
4135 struct bnx2x *bp = params->bp;
4136 u16 val16, digctrl_kx1, digctrl_kx2;
4138 /* Clear XFI clock comp in non-10G single lane mode. */
4139 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4140 MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4142 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4144 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4146 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4147 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4149 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4151 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4152 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4154 switch (phy->req_line_speed) {
4165 "Speed not supported: 0x%x\n", phy->req_line_speed);
4169 if (phy->req_duplex == DUPLEX_FULL)
4172 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4173 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4175 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4176 phy->req_line_speed);
4177 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4178 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4179 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
4182 /* SGMII Slave mode and disable signal detect */
4183 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4184 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4188 digctrl_kx1 &= 0xff4a;
4190 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4191 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4194 /* Turn off parallel detect */
4195 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4196 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4197 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4198 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4199 (digctrl_kx2 & ~(1<<2)));
4201 /* Re-enable parallel detect */
4202 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4203 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4204 (digctrl_kx2 | (1<<2)));
4206 /* Enable autodet */
4207 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4208 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4209 (digctrl_kx1 | 0x10));
4212 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4213 struct bnx2x_phy *phy,
4217 /* Take lane out of reset after configuration is finished */
4218 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4219 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4224 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4225 MDIO_WC_REG_DIGITAL5_MISC6, val);
4226 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4227 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4229 /* Clear SFI/XFI link settings registers */
4230 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4231 struct link_params *params,
4234 struct bnx2x *bp = params->bp;
4236 static struct bnx2x_reg_set wc_regs[] = {
4237 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4238 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4239 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4240 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4241 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4243 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4245 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4247 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4248 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4249 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4250 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4252 /* Set XFI clock comp as default. */
4253 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4254 MDIO_WC_REG_RX66_CONTROL, (3<<13));
4256 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4257 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4260 lane = bnx2x_get_warpcore_lane(phy, params);
4261 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4262 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4266 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4268 u32 shmem_base, u8 port,
4269 u8 *gpio_num, u8 *gpio_port)
4274 if (CHIP_IS_E3(bp)) {
4275 cfg_pin = (REG_RD(bp, shmem_base +
4276 offsetof(struct shmem_region,
4277 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4278 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4279 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4281 /* Should not happen. This function called upon interrupt
4282 * triggered by GPIO ( since EPIO can only generate interrupts
4284 * So if this function was called and none of the GPIOs was set,
4285 * it means the shit hit the fan.
4287 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4288 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4290 "No cfg pin %x for module detect indication\n",
4295 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4296 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4298 *gpio_num = MISC_REGISTERS_GPIO_3;
4305 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4306 struct link_params *params)
4308 struct bnx2x *bp = params->bp;
4309 u8 gpio_num, gpio_port;
4311 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4312 params->shmem_base, params->port,
4313 &gpio_num, &gpio_port) != 0)
4315 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4317 /* Call the handling function in case module is detected */
4323 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4324 struct link_params *params)
4326 u16 gp2_status_reg0, lane;
4327 struct bnx2x *bp = params->bp;
4329 lane = bnx2x_get_warpcore_lane(phy, params);
4331 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4334 return (gp2_status_reg0 >> (8+lane)) & 0x1;
4337 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4338 struct link_params *params,
4339 struct link_vars *vars)
4341 struct bnx2x *bp = params->bp;
4343 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4344 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4346 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4348 if (!vars->turn_to_run_wc_rt)
4351 /* Return if there is no link partner */
4352 if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4353 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4357 if (vars->rx_tx_asic_rst) {
4358 serdes_net_if = (REG_RD(bp, params->shmem_base +
4359 offsetof(struct shmem_region, dev_info.
4360 port_hw_config[params->port].default_cfg)) &
4361 PORT_HW_CFG_NET_SERDES_IF_MASK);
4363 switch (serdes_net_if) {
4364 case PORT_HW_CFG_NET_SERDES_IF_KR:
4365 /* Do we get link yet? */
4366 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4368 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4370 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4373 "gp_status1 0x%x\n", gp_status1);
4375 if (lnkup_kr || lnkup) {
4376 vars->rx_tx_asic_rst = 0;
4378 "link up, rx_tx_asic_rst 0x%x\n",
4379 vars->rx_tx_asic_rst);
4381 /* Reset the lane to see if link comes up.*/
4382 bnx2x_warpcore_reset_lane(bp, phy, 1);
4383 bnx2x_warpcore_reset_lane(bp, phy, 0);
4385 /* Restart Autoneg */
4386 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4387 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4389 vars->rx_tx_asic_rst--;
4390 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4391 vars->rx_tx_asic_rst);
4399 } /*params->rx_tx_asic_rst*/
4402 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4403 struct link_params *params)
4405 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4406 struct bnx2x *bp = params->bp;
4407 bnx2x_warpcore_clear_regs(phy, params, lane);
4408 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4410 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4411 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4412 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4414 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4415 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4419 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4420 struct bnx2x_phy *phy,
4423 struct bnx2x *bp = params->bp;
4425 u8 port = params->port;
4427 cfg_pin = REG_RD(bp, params->shmem_base +
4428 offsetof(struct shmem_region,
4429 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4430 PORT_HW_CFG_E3_TX_LASER_MASK;
4431 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4432 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4434 /* For 20G, the expected pin to be used is 3 pins after the current */
4435 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4436 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4437 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4440 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4441 struct link_params *params,
4442 struct link_vars *vars)
4444 struct bnx2x *bp = params->bp;
4447 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4448 serdes_net_if = (REG_RD(bp, params->shmem_base +
4449 offsetof(struct shmem_region, dev_info.
4450 port_hw_config[params->port].default_cfg)) &
4451 PORT_HW_CFG_NET_SERDES_IF_MASK);
4452 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4453 "serdes_net_if = 0x%x\n",
4454 vars->line_speed, serdes_net_if);
4455 bnx2x_set_aer_mmd(params, phy);
4456 bnx2x_warpcore_reset_lane(bp, phy, 1);
4457 vars->phy_flags |= PHY_XGXS_FLAG;
4458 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4459 (phy->req_line_speed &&
4460 ((phy->req_line_speed == SPEED_100) ||
4461 (phy->req_line_speed == SPEED_10)))) {
4462 vars->phy_flags |= PHY_SGMII_FLAG;
4463 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4464 bnx2x_warpcore_clear_regs(phy, params, lane);
4465 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4467 switch (serdes_net_if) {
4468 case PORT_HW_CFG_NET_SERDES_IF_KR:
4469 /* Enable KR Auto Neg */
4470 if (params->loopback_mode != LOOPBACK_EXT)
4471 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4473 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4474 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4478 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4479 bnx2x_warpcore_clear_regs(phy, params, lane);
4480 if (vars->line_speed == SPEED_10000) {
4481 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4482 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4484 if (SINGLE_MEDIA_DIRECT(params)) {
4485 DP(NETIF_MSG_LINK, "1G Fiber\n");
4488 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4491 bnx2x_warpcore_set_sgmii_speed(phy,
4499 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4500 /* Issue Module detection if module is plugged, or
4501 * enabled transmitter to avoid current leakage in case
4502 * no module is connected
4504 if (bnx2x_is_sfp_module_plugged(phy, params))
4505 bnx2x_sfp_module_detection(phy, params);
4507 bnx2x_sfp_e3_set_transmitter(params, phy, 1);
4509 bnx2x_warpcore_config_sfi(phy, params);
4512 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4513 if (vars->line_speed != SPEED_20000) {
4514 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4517 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4518 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4519 /* Issue Module detection */
4521 bnx2x_sfp_module_detection(phy, params);
4523 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4524 if (!params->loopback_mode) {
4525 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4527 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4528 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4533 "Unsupported Serdes Net Interface 0x%x\n",
4539 /* Take lane out of reset after configuration is finished */
4540 bnx2x_warpcore_reset_lane(bp, phy, 0);
4541 DP(NETIF_MSG_LINK, "Exit config init\n");
4544 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4545 struct link_params *params)
4547 struct bnx2x *bp = params->bp;
4549 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4550 bnx2x_set_mdio_emac_per_phy(bp, params);
4551 bnx2x_set_aer_mmd(params, phy);
4552 /* Global register */
4553 bnx2x_warpcore_reset_lane(bp, phy, 1);
4555 /* Clear loopback settings (if any) */
4557 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4558 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4560 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4561 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4563 /* Update those 1-copy registers */
4564 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4565 MDIO_AER_BLOCK_AER_REG, 0);
4566 /* Enable 1G MDIO (1-copy) */
4567 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4568 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4571 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4572 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4573 lane = bnx2x_get_warpcore_lane(phy, params);
4574 /* Disable CL36 PCS Tx */
4575 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4576 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4577 val16 |= (0x11 << lane);
4578 if (phy->flags & FLAGS_WC_DUAL_MODE)
4579 val16 |= (0x22 << lane);
4580 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4581 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4583 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4584 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4585 val16 &= ~(0x0303 << (lane << 1));
4586 val16 |= (0x0101 << (lane << 1));
4587 if (phy->flags & FLAGS_WC_DUAL_MODE) {
4588 val16 &= ~(0x0c0c << (lane << 1));
4589 val16 |= (0x0404 << (lane << 1));
4592 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4593 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4595 bnx2x_set_aer_mmd(params, phy);
4599 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4600 struct link_params *params)
4602 struct bnx2x *bp = params->bp;
4605 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4606 params->loopback_mode, phy->req_line_speed);
4608 if (phy->req_line_speed < SPEED_10000 ||
4609 phy->supported & SUPPORTED_20000baseKR2_Full) {
4610 /* 10/100/1000/20G-KR2 */
4612 /* Update those 1-copy registers */
4613 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4614 MDIO_AER_BLOCK_AER_REG, 0);
4615 /* Enable 1G MDIO (1-copy) */
4616 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4617 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4619 /* Set 1G loopback based on lane (1-copy) */
4620 lane = bnx2x_get_warpcore_lane(phy, params);
4621 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4622 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4624 if (phy->flags & FLAGS_WC_DUAL_MODE)
4626 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4627 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4630 /* Switch back to 4-copy registers */
4631 bnx2x_set_aer_mmd(params, phy);
4633 /* 10G / 20G-DXGXS */
4634 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4635 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4637 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4638 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4644 static void bnx2x_sync_link(struct link_params *params,
4645 struct link_vars *vars)
4647 struct bnx2x *bp = params->bp;
4649 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4650 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4651 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4652 if (vars->link_up) {
4653 DP(NETIF_MSG_LINK, "phy link up\n");
4655 vars->phy_link_up = 1;
4656 vars->duplex = DUPLEX_FULL;
4657 switch (vars->link_status &
4658 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4660 vars->duplex = DUPLEX_HALF;
4663 vars->line_speed = SPEED_10;
4667 vars->duplex = DUPLEX_HALF;
4671 vars->line_speed = SPEED_100;
4675 vars->duplex = DUPLEX_HALF;
4678 vars->line_speed = SPEED_1000;
4682 vars->duplex = DUPLEX_HALF;
4685 vars->line_speed = SPEED_2500;
4689 vars->line_speed = SPEED_10000;
4692 vars->line_speed = SPEED_20000;
4697 vars->flow_ctrl = 0;
4698 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4699 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4701 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4702 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4704 if (!vars->flow_ctrl)
4705 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4707 if (vars->line_speed &&
4708 ((vars->line_speed == SPEED_10) ||
4709 (vars->line_speed == SPEED_100))) {
4710 vars->phy_flags |= PHY_SGMII_FLAG;
4712 vars->phy_flags &= ~PHY_SGMII_FLAG;
4714 if (vars->line_speed &&
4715 USES_WARPCORE(bp) &&
4716 (vars->line_speed == SPEED_1000))
4717 vars->phy_flags |= PHY_SGMII_FLAG;
4718 /* Anything 10 and over uses the bmac */
4719 link_10g_plus = (vars->line_speed >= SPEED_10000);
4721 if (link_10g_plus) {
4722 if (USES_WARPCORE(bp))
4723 vars->mac_type = MAC_TYPE_XMAC;
4725 vars->mac_type = MAC_TYPE_BMAC;
4727 if (USES_WARPCORE(bp))
4728 vars->mac_type = MAC_TYPE_UMAC;
4730 vars->mac_type = MAC_TYPE_EMAC;
4732 } else { /* Link down */
4733 DP(NETIF_MSG_LINK, "phy link down\n");
4735 vars->phy_link_up = 0;
4737 vars->line_speed = 0;
4738 vars->duplex = DUPLEX_FULL;
4739 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4741 /* Indicate no mac active */
4742 vars->mac_type = MAC_TYPE_NONE;
4743 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4744 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4745 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4746 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4750 void bnx2x_link_status_update(struct link_params *params,
4751 struct link_vars *vars)
4753 struct bnx2x *bp = params->bp;
4754 u8 port = params->port;
4755 u32 sync_offset, media_types;
4756 /* Update PHY configuration */
4757 set_phy_vars(params, vars);
4759 vars->link_status = REG_RD(bp, params->shmem_base +
4760 offsetof(struct shmem_region,
4761 port_mb[port].link_status));
4763 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4764 if (params->loopback_mode != LOOPBACK_NONE &&
4765 params->loopback_mode != LOOPBACK_EXT)
4766 vars->link_status |= LINK_STATUS_LINK_UP;
4768 if (bnx2x_eee_has_cap(params))
4769 vars->eee_status = REG_RD(bp, params->shmem2_base +
4770 offsetof(struct shmem2_region,
4771 eee_status[params->port]));
4773 vars->phy_flags = PHY_XGXS_FLAG;
4774 bnx2x_sync_link(params, vars);
4775 /* Sync media type */
4776 sync_offset = params->shmem_base +
4777 offsetof(struct shmem_region,
4778 dev_info.port_hw_config[port].media_type);
4779 media_types = REG_RD(bp, sync_offset);
4781 params->phy[INT_PHY].media_type =
4782 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4783 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4784 params->phy[EXT_PHY1].media_type =
4785 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4786 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4787 params->phy[EXT_PHY2].media_type =
4788 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4789 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4790 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4792 /* Sync AEU offset */
4793 sync_offset = params->shmem_base +
4794 offsetof(struct shmem_region,
4795 dev_info.port_hw_config[port].aeu_int_mask);
4797 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4799 /* Sync PFC status */
4800 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4801 params->feature_config_flags |=
4802 FEATURE_CONFIG_PFC_ENABLED;
4804 params->feature_config_flags &=
4805 ~FEATURE_CONFIG_PFC_ENABLED;
4807 if (SHMEM2_HAS(bp, link_attr_sync))
4808 vars->link_attr_sync = SHMEM2_RD(bp,
4809 link_attr_sync[params->port]);
4811 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4812 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4813 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4814 vars->line_speed, vars->duplex, vars->flow_ctrl);
4817 static void bnx2x_set_master_ln(struct link_params *params,
4818 struct bnx2x_phy *phy)
4820 struct bnx2x *bp = params->bp;
4821 u16 new_master_ln, ser_lane;
4822 ser_lane = ((params->lane_config &
4823 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4824 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4826 /* Set the master_ln for AN */
4827 CL22_RD_OVER_CL45(bp, phy,
4828 MDIO_REG_BANK_XGXS_BLOCK2,
4829 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4832 CL22_WR_OVER_CL45(bp, phy,
4833 MDIO_REG_BANK_XGXS_BLOCK2 ,
4834 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4835 (new_master_ln | ser_lane));
4838 static int bnx2x_reset_unicore(struct link_params *params,
4839 struct bnx2x_phy *phy,
4842 struct bnx2x *bp = params->bp;
4845 CL22_RD_OVER_CL45(bp, phy,
4846 MDIO_REG_BANK_COMBO_IEEE0,
4847 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4849 /* Reset the unicore */
4850 CL22_WR_OVER_CL45(bp, phy,
4851 MDIO_REG_BANK_COMBO_IEEE0,
4852 MDIO_COMBO_IEEE0_MII_CONTROL,
4854 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4856 bnx2x_set_serdes_access(bp, params->port);
4858 /* Wait for the reset to self clear */
4859 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4862 /* The reset erased the previous bank value */
4863 CL22_RD_OVER_CL45(bp, phy,
4864 MDIO_REG_BANK_COMBO_IEEE0,
4865 MDIO_COMBO_IEEE0_MII_CONTROL,
4868 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4874 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4877 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4882 static void bnx2x_set_swap_lanes(struct link_params *params,
4883 struct bnx2x_phy *phy)
4885 struct bnx2x *bp = params->bp;
4886 /* Each two bits represents a lane number:
4887 * No swap is 0123 => 0x1b no need to enable the swap
4889 u16 rx_lane_swap, tx_lane_swap;
4891 rx_lane_swap = ((params->lane_config &
4892 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4893 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4894 tx_lane_swap = ((params->lane_config &
4895 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4896 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4898 if (rx_lane_swap != 0x1b) {
4899 CL22_WR_OVER_CL45(bp, phy,
4900 MDIO_REG_BANK_XGXS_BLOCK2,
4901 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4903 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4904 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4906 CL22_WR_OVER_CL45(bp, phy,
4907 MDIO_REG_BANK_XGXS_BLOCK2,
4908 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4911 if (tx_lane_swap != 0x1b) {
4912 CL22_WR_OVER_CL45(bp, phy,
4913 MDIO_REG_BANK_XGXS_BLOCK2,
4914 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4916 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4918 CL22_WR_OVER_CL45(bp, phy,
4919 MDIO_REG_BANK_XGXS_BLOCK2,
4920 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4924 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4925 struct link_params *params)
4927 struct bnx2x *bp = params->bp;
4929 CL22_RD_OVER_CL45(bp, phy,
4930 MDIO_REG_BANK_SERDES_DIGITAL,
4931 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4933 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4934 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4936 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4937 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4938 phy->speed_cap_mask, control2);
4939 CL22_WR_OVER_CL45(bp, phy,
4940 MDIO_REG_BANK_SERDES_DIGITAL,
4941 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4944 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4945 (phy->speed_cap_mask &
4946 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4947 DP(NETIF_MSG_LINK, "XGXS\n");
4949 CL22_WR_OVER_CL45(bp, phy,
4950 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4951 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4952 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4954 CL22_RD_OVER_CL45(bp, phy,
4955 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4956 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4961 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4963 CL22_WR_OVER_CL45(bp, phy,
4964 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4965 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4968 /* Disable parallel detection of HiG */
4969 CL22_WR_OVER_CL45(bp, phy,
4970 MDIO_REG_BANK_XGXS_BLOCK2,
4971 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4972 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4973 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4977 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4978 struct link_params *params,
4979 struct link_vars *vars,
4982 struct bnx2x *bp = params->bp;
4986 CL22_RD_OVER_CL45(bp, phy,
4987 MDIO_REG_BANK_COMBO_IEEE0,
4988 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4990 /* CL37 Autoneg Enabled */
4991 if (vars->line_speed == SPEED_AUTO_NEG)
4992 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4993 else /* CL37 Autoneg Disabled */
4994 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4995 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4997 CL22_WR_OVER_CL45(bp, phy,
4998 MDIO_REG_BANK_COMBO_IEEE0,
4999 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5001 /* Enable/Disable Autodetection */
5003 CL22_RD_OVER_CL45(bp, phy,
5004 MDIO_REG_BANK_SERDES_DIGITAL,
5005 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
5006 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5007 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5008 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5009 if (vars->line_speed == SPEED_AUTO_NEG)
5010 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5012 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5014 CL22_WR_OVER_CL45(bp, phy,
5015 MDIO_REG_BANK_SERDES_DIGITAL,
5016 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5018 /* Enable TetonII and BAM autoneg */
5019 CL22_RD_OVER_CL45(bp, phy,
5020 MDIO_REG_BANK_BAM_NEXT_PAGE,
5021 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5023 if (vars->line_speed == SPEED_AUTO_NEG) {
5024 /* Enable BAM aneg Mode and TetonII aneg Mode */
5025 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5026 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5028 /* TetonII and BAM Autoneg Disabled */
5029 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5030 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5032 CL22_WR_OVER_CL45(bp, phy,
5033 MDIO_REG_BANK_BAM_NEXT_PAGE,
5034 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5038 /* Enable Cl73 FSM status bits */
5039 CL22_WR_OVER_CL45(bp, phy,
5040 MDIO_REG_BANK_CL73_USERB0,
5041 MDIO_CL73_USERB0_CL73_UCTRL,
5044 /* Enable BAM Station Manager*/
5045 CL22_WR_OVER_CL45(bp, phy,
5046 MDIO_REG_BANK_CL73_USERB0,
5047 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5048 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5049 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5050 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5052 /* Advertise CL73 link speeds */
5053 CL22_RD_OVER_CL45(bp, phy,
5054 MDIO_REG_BANK_CL73_IEEEB1,
5055 MDIO_CL73_IEEEB1_AN_ADV2,
5057 if (phy->speed_cap_mask &
5058 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5059 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5060 if (phy->speed_cap_mask &
5061 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5062 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5064 CL22_WR_OVER_CL45(bp, phy,
5065 MDIO_REG_BANK_CL73_IEEEB1,
5066 MDIO_CL73_IEEEB1_AN_ADV2,
5069 /* CL73 Autoneg Enabled */
5070 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5072 } else /* CL73 Autoneg Disabled */
5075 CL22_WR_OVER_CL45(bp, phy,
5076 MDIO_REG_BANK_CL73_IEEEB0,
5077 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5080 /* Program SerDes, forced speed */
5081 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5082 struct link_params *params,
5083 struct link_vars *vars)
5085 struct bnx2x *bp = params->bp;
5088 /* Program duplex, disable autoneg and sgmii*/
5089 CL22_RD_OVER_CL45(bp, phy,
5090 MDIO_REG_BANK_COMBO_IEEE0,
5091 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5092 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5093 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5094 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5095 if (phy->req_duplex == DUPLEX_FULL)
5096 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5097 CL22_WR_OVER_CL45(bp, phy,
5098 MDIO_REG_BANK_COMBO_IEEE0,
5099 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5102 * - needed only if the speed is greater than 1G (2.5G or 10G)
5104 CL22_RD_OVER_CL45(bp, phy,
5105 MDIO_REG_BANK_SERDES_DIGITAL,
5106 MDIO_SERDES_DIGITAL_MISC1, ®_val);
5107 /* Clearing the speed value before setting the right speed */
5108 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5110 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5111 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5113 if (!((vars->line_speed == SPEED_1000) ||
5114 (vars->line_speed == SPEED_100) ||
5115 (vars->line_speed == SPEED_10))) {
5117 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5118 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5119 if (vars->line_speed == SPEED_10000)
5121 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5124 CL22_WR_OVER_CL45(bp, phy,
5125 MDIO_REG_BANK_SERDES_DIGITAL,
5126 MDIO_SERDES_DIGITAL_MISC1, reg_val);
5130 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5131 struct link_params *params)
5133 struct bnx2x *bp = params->bp;
5136 /* Set extended capabilities */
5137 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5138 val |= MDIO_OVER_1G_UP1_2_5G;
5139 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5140 val |= MDIO_OVER_1G_UP1_10G;
5141 CL22_WR_OVER_CL45(bp, phy,
5142 MDIO_REG_BANK_OVER_1G,
5143 MDIO_OVER_1G_UP1, val);
5145 CL22_WR_OVER_CL45(bp, phy,
5146 MDIO_REG_BANK_OVER_1G,
5147 MDIO_OVER_1G_UP3, 0x400);
5150 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5151 struct link_params *params,
5154 struct bnx2x *bp = params->bp;
5156 /* For AN, we are always publishing full duplex */
5158 CL22_WR_OVER_CL45(bp, phy,
5159 MDIO_REG_BANK_COMBO_IEEE0,
5160 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5161 CL22_RD_OVER_CL45(bp, phy,
5162 MDIO_REG_BANK_CL73_IEEEB1,
5163 MDIO_CL73_IEEEB1_AN_ADV1, &val);
5164 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5165 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5166 CL22_WR_OVER_CL45(bp, phy,
5167 MDIO_REG_BANK_CL73_IEEEB1,
5168 MDIO_CL73_IEEEB1_AN_ADV1, val);
5171 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5172 struct link_params *params,
5175 struct bnx2x *bp = params->bp;
5178 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5179 /* Enable and restart BAM/CL37 aneg */
5182 CL22_RD_OVER_CL45(bp, phy,
5183 MDIO_REG_BANK_CL73_IEEEB0,
5184 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5187 CL22_WR_OVER_CL45(bp, phy,
5188 MDIO_REG_BANK_CL73_IEEEB0,
5189 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5191 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5192 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5195 CL22_RD_OVER_CL45(bp, phy,
5196 MDIO_REG_BANK_COMBO_IEEE0,
5197 MDIO_COMBO_IEEE0_MII_CONTROL,
5200 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5202 CL22_WR_OVER_CL45(bp, phy,
5203 MDIO_REG_BANK_COMBO_IEEE0,
5204 MDIO_COMBO_IEEE0_MII_CONTROL,
5206 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5207 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5211 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5212 struct link_params *params,
5213 struct link_vars *vars)
5215 struct bnx2x *bp = params->bp;
5218 /* In SGMII mode, the unicore is always slave */
5220 CL22_RD_OVER_CL45(bp, phy,
5221 MDIO_REG_BANK_SERDES_DIGITAL,
5222 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5224 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5225 /* Set sgmii mode (and not fiber) */
5226 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5227 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5228 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5229 CL22_WR_OVER_CL45(bp, phy,
5230 MDIO_REG_BANK_SERDES_DIGITAL,
5231 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5234 /* If forced speed */
5235 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5236 /* Set speed, disable autoneg */
5239 CL22_RD_OVER_CL45(bp, phy,
5240 MDIO_REG_BANK_COMBO_IEEE0,
5241 MDIO_COMBO_IEEE0_MII_CONTROL,
5243 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5244 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5245 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5247 switch (vars->line_speed) {
5250 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5254 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5257 /* There is nothing to set for 10M */
5260 /* Invalid speed for SGMII */
5261 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5266 /* Setting the full duplex */
5267 if (phy->req_duplex == DUPLEX_FULL)
5269 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5270 CL22_WR_OVER_CL45(bp, phy,
5271 MDIO_REG_BANK_COMBO_IEEE0,
5272 MDIO_COMBO_IEEE0_MII_CONTROL,
5275 } else { /* AN mode */
5276 /* Enable and restart AN */
5277 bnx2x_restart_autoneg(phy, params, 0);
5283 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5284 struct link_params *params)
5286 struct bnx2x *bp = params->bp;
5287 u16 pd_10g, status2_1000x;
5288 if (phy->req_line_speed != SPEED_AUTO_NEG)
5290 CL22_RD_OVER_CL45(bp, phy,
5291 MDIO_REG_BANK_SERDES_DIGITAL,
5292 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5294 CL22_RD_OVER_CL45(bp, phy,
5295 MDIO_REG_BANK_SERDES_DIGITAL,
5296 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5298 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5299 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5304 CL22_RD_OVER_CL45(bp, phy,
5305 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5306 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5309 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5310 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5317 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5318 struct link_params *params,
5319 struct link_vars *vars,
5322 u16 ld_pause; /* local driver */
5323 u16 lp_pause; /* link partner */
5325 struct bnx2x *bp = params->bp;
5327 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5328 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5329 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5330 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5332 CL22_RD_OVER_CL45(bp, phy,
5333 MDIO_REG_BANK_CL73_IEEEB1,
5334 MDIO_CL73_IEEEB1_AN_ADV1,
5336 CL22_RD_OVER_CL45(bp, phy,
5337 MDIO_REG_BANK_CL73_IEEEB1,
5338 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5340 pause_result = (ld_pause &
5341 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5342 pause_result |= (lp_pause &
5343 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5344 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5346 CL22_RD_OVER_CL45(bp, phy,
5347 MDIO_REG_BANK_COMBO_IEEE0,
5348 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5350 CL22_RD_OVER_CL45(bp, phy,
5351 MDIO_REG_BANK_COMBO_IEEE0,
5352 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5354 pause_result = (ld_pause &
5355 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5356 pause_result |= (lp_pause &
5357 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5358 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5360 bnx2x_pause_resolve(vars, pause_result);
5364 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5365 struct link_params *params,
5366 struct link_vars *vars,
5369 struct bnx2x *bp = params->bp;
5370 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5372 /* Resolve from gp_status in case of AN complete and not sgmii */
5373 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5374 /* Update the advertised flow-controled of LD/LP in AN */
5375 if (phy->req_line_speed == SPEED_AUTO_NEG)
5376 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5377 /* But set the flow-control result as the requested one */
5378 vars->flow_ctrl = phy->req_flow_ctrl;
5379 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5380 vars->flow_ctrl = params->req_fc_auto_adv;
5381 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5382 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5383 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5384 vars->flow_ctrl = params->req_fc_auto_adv;
5387 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5389 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5392 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5393 struct link_params *params)
5395 struct bnx2x *bp = params->bp;
5396 u16 rx_status, ustat_val, cl37_fsm_received;
5397 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5398 /* Step 1: Make sure signal is detected */
5399 CL22_RD_OVER_CL45(bp, phy,
5403 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5404 (MDIO_RX0_RX_STATUS_SIGDET)) {
5405 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5406 "rx_status(0x80b0) = 0x%x\n", rx_status);
5407 CL22_WR_OVER_CL45(bp, phy,
5408 MDIO_REG_BANK_CL73_IEEEB0,
5409 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5410 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5413 /* Step 2: Check CL73 state machine */
5414 CL22_RD_OVER_CL45(bp, phy,
5415 MDIO_REG_BANK_CL73_USERB0,
5416 MDIO_CL73_USERB0_CL73_USTAT1,
5419 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5420 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5421 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5422 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5423 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5424 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5427 /* Step 3: Check CL37 Message Pages received to indicate LP
5428 * supports only CL37
5430 CL22_RD_OVER_CL45(bp, phy,
5431 MDIO_REG_BANK_REMOTE_PHY,
5432 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5433 &cl37_fsm_received);
5434 if ((cl37_fsm_received &
5435 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5436 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5437 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5438 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5439 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5440 "misc_rx_status(0x8330) = 0x%x\n",
5444 /* The combined cl37/cl73 fsm state information indicating that
5445 * we are connected to a device which does not support cl73, but
5446 * does support cl37 BAM. In this case we disable cl73 and
5447 * restart cl37 auto-neg
5451 CL22_WR_OVER_CL45(bp, phy,
5452 MDIO_REG_BANK_CL73_IEEEB0,
5453 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5455 /* Restart CL37 autoneg */
5456 bnx2x_restart_autoneg(phy, params, 0);
5457 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5460 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5461 struct link_params *params,
5462 struct link_vars *vars,
5465 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5466 vars->link_status |=
5467 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5469 if (bnx2x_direct_parallel_detect_used(phy, params))
5470 vars->link_status |=
5471 LINK_STATUS_PARALLEL_DETECTION_USED;
5473 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5474 struct link_params *params,
5475 struct link_vars *vars,
5480 struct bnx2x *bp = params->bp;
5481 if (phy->req_line_speed == SPEED_AUTO_NEG)
5482 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5484 DP(NETIF_MSG_LINK, "phy link up\n");
5486 vars->phy_link_up = 1;
5487 vars->link_status |= LINK_STATUS_LINK_UP;
5489 switch (speed_mask) {
5491 vars->line_speed = SPEED_10;
5492 if (is_duplex == DUPLEX_FULL)
5493 vars->link_status |= LINK_10TFD;
5495 vars->link_status |= LINK_10THD;
5498 case GP_STATUS_100M:
5499 vars->line_speed = SPEED_100;
5500 if (is_duplex == DUPLEX_FULL)
5501 vars->link_status |= LINK_100TXFD;
5503 vars->link_status |= LINK_100TXHD;
5507 case GP_STATUS_1G_KX:
5508 vars->line_speed = SPEED_1000;
5509 if (is_duplex == DUPLEX_FULL)
5510 vars->link_status |= LINK_1000TFD;
5512 vars->link_status |= LINK_1000THD;
5515 case GP_STATUS_2_5G:
5516 vars->line_speed = SPEED_2500;
5517 if (is_duplex == DUPLEX_FULL)
5518 vars->link_status |= LINK_2500TFD;
5520 vars->link_status |= LINK_2500THD;
5526 "link speed unsupported gp_status 0x%x\n",
5530 case GP_STATUS_10G_KX4:
5531 case GP_STATUS_10G_HIG:
5532 case GP_STATUS_10G_CX4:
5533 case GP_STATUS_10G_KR:
5534 case GP_STATUS_10G_SFI:
5535 case GP_STATUS_10G_XFI:
5536 vars->line_speed = SPEED_10000;
5537 vars->link_status |= LINK_10GTFD;
5539 case GP_STATUS_20G_DXGXS:
5540 case GP_STATUS_20G_KR2:
5541 vars->line_speed = SPEED_20000;
5542 vars->link_status |= LINK_20GTFD;
5546 "link speed unsupported gp_status 0x%x\n",
5550 } else { /* link_down */
5551 DP(NETIF_MSG_LINK, "phy link down\n");
5553 vars->phy_link_up = 0;
5555 vars->duplex = DUPLEX_FULL;
5556 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5557 vars->mac_type = MAC_TYPE_NONE;
5559 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5560 vars->phy_link_up, vars->line_speed);
5564 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5565 struct link_params *params,
5566 struct link_vars *vars)
5568 struct bnx2x *bp = params->bp;
5570 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5573 /* Read gp_status */
5574 CL22_RD_OVER_CL45(bp, phy,
5575 MDIO_REG_BANK_GP_STATUS,
5576 MDIO_GP_STATUS_TOP_AN_STATUS1,
5578 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5579 duplex = DUPLEX_FULL;
5580 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5582 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5583 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5584 gp_status, link_up, speed_mask);
5585 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5590 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5591 if (SINGLE_MEDIA_DIRECT(params)) {
5592 vars->duplex = duplex;
5593 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5594 if (phy->req_line_speed == SPEED_AUTO_NEG)
5595 bnx2x_xgxs_an_resolve(phy, params, vars,
5598 } else { /* Link_down */
5599 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5600 SINGLE_MEDIA_DIRECT(params)) {
5601 /* Check signal is detected */
5602 bnx2x_check_fallback_to_cl37(phy, params);
5606 /* Read LP advertised speeds*/
5607 if (SINGLE_MEDIA_DIRECT(params) &&
5608 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5611 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5612 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5614 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5615 vars->link_status |=
5616 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5617 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5618 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5619 vars->link_status |=
5620 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5622 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5623 MDIO_OVER_1G_LP_UP1, &val);
5625 if (val & MDIO_OVER_1G_UP1_2_5G)
5626 vars->link_status |=
5627 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5628 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5629 vars->link_status |=
5630 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5633 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5634 vars->duplex, vars->flow_ctrl, vars->link_status);
5638 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5639 struct link_params *params,
5640 struct link_vars *vars)
5642 struct bnx2x *bp = params->bp;
5644 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5646 lane = bnx2x_get_warpcore_lane(phy, params);
5647 /* Read gp_status */
5648 if ((params->loopback_mode) &&
5649 (phy->flags & FLAGS_WC_DUAL_MODE)) {
5650 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5651 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5652 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5653 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5655 } else if ((phy->req_line_speed > SPEED_10000) &&
5656 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5658 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5660 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5662 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5663 temp_link_up, link_up);
5666 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5668 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5669 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5671 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5672 /* Check for either KR, 1G, or AN up. */
5673 link_up = ((gp_status1 >> 8) |
5674 (gp_status1 >> 12) |
5677 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5679 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5680 MDIO_AN_REG_STATUS, &an_link);
5681 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5682 MDIO_AN_REG_STATUS, &an_link);
5683 link_up |= (an_link & (1<<2));
5685 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5687 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5688 /* Check Autoneg complete */
5689 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5690 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5692 if (gp_status4 & ((1<<12)<<lane))
5693 vars->link_status |=
5694 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5696 /* Check parallel detect used */
5697 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5698 MDIO_WC_REG_PAR_DET_10G_STATUS,
5701 vars->link_status |=
5702 LINK_STATUS_PARALLEL_DETECTION_USED;
5704 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5705 vars->duplex = duplex;
5709 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5710 SINGLE_MEDIA_DIRECT(params)) {
5713 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5714 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5716 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5717 vars->link_status |=
5718 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5719 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5720 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5721 vars->link_status |=
5722 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5724 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5725 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5727 if (val & MDIO_OVER_1G_UP1_2_5G)
5728 vars->link_status |=
5729 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5730 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5731 vars->link_status |=
5732 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5738 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5739 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5741 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5742 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5744 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5746 if ((lane & 1) == 0)
5749 link_up = !!link_up;
5751 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5754 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5755 vars->duplex, vars->flow_ctrl, vars->link_status);
5758 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5760 struct bnx2x *bp = params->bp;
5761 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
5767 CL22_RD_OVER_CL45(bp, phy,
5768 MDIO_REG_BANK_OVER_1G,
5769 MDIO_OVER_1G_LP_UP2, &lp_up2);
5771 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5772 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5773 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5774 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5779 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5780 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5781 CL22_RD_OVER_CL45(bp, phy,
5783 MDIO_TX0_TX_DRIVER, &tx_driver);
5785 /* Replace tx_driver bits [15:12] */
5787 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5788 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5789 tx_driver |= lp_up2;
5790 CL22_WR_OVER_CL45(bp, phy,
5792 MDIO_TX0_TX_DRIVER, tx_driver);
5797 static int bnx2x_emac_program(struct link_params *params,
5798 struct link_vars *vars)
5800 struct bnx2x *bp = params->bp;
5801 u8 port = params->port;
5804 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5805 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5807 (EMAC_MODE_25G_MODE |
5808 EMAC_MODE_PORT_MII_10M |
5809 EMAC_MODE_HALF_DUPLEX));
5810 switch (vars->line_speed) {
5812 mode |= EMAC_MODE_PORT_MII_10M;
5816 mode |= EMAC_MODE_PORT_MII;
5820 mode |= EMAC_MODE_PORT_GMII;
5824 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5828 /* 10G not valid for EMAC */
5829 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5834 if (vars->duplex == DUPLEX_HALF)
5835 mode |= EMAC_MODE_HALF_DUPLEX;
5837 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5840 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5844 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5845 struct link_params *params)
5849 struct bnx2x *bp = params->bp;
5851 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5852 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5853 CL22_WR_OVER_CL45(bp, phy,
5855 MDIO_RX0_RX_EQ_BOOST,
5856 phy->rx_preemphasis[i]);
5859 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5860 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5861 CL22_WR_OVER_CL45(bp, phy,
5864 phy->tx_preemphasis[i]);
5868 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5869 struct link_params *params,
5870 struct link_vars *vars)
5872 struct bnx2x *bp = params->bp;
5873 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5874 (params->loopback_mode == LOOPBACK_XGXS));
5875 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5876 if (SINGLE_MEDIA_DIRECT(params) &&
5877 (params->feature_config_flags &
5878 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5879 bnx2x_set_preemphasis(phy, params);
5881 /* Forced speed requested? */
5882 if (vars->line_speed != SPEED_AUTO_NEG ||
5883 (SINGLE_MEDIA_DIRECT(params) &&
5884 params->loopback_mode == LOOPBACK_EXT)) {
5885 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5887 /* Disable autoneg */
5888 bnx2x_set_autoneg(phy, params, vars, 0);
5890 /* Program speed and duplex */
5891 bnx2x_program_serdes(phy, params, vars);
5893 } else { /* AN_mode */
5894 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5897 bnx2x_set_brcm_cl37_advertisement(phy, params);
5899 /* Program duplex & pause advertisement (for aneg) */
5900 bnx2x_set_ieee_aneg_advertisement(phy, params,
5903 /* Enable autoneg */
5904 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5906 /* Enable and restart AN */
5907 bnx2x_restart_autoneg(phy, params, enable_cl73);
5910 } else { /* SGMII mode */
5911 DP(NETIF_MSG_LINK, "SGMII\n");
5913 bnx2x_initialize_sgmii_process(phy, params, vars);
5917 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5918 struct link_params *params,
5919 struct link_vars *vars)
5922 vars->phy_flags |= PHY_XGXS_FLAG;
5923 if ((phy->req_line_speed &&
5924 ((phy->req_line_speed == SPEED_100) ||
5925 (phy->req_line_speed == SPEED_10))) ||
5926 (!phy->req_line_speed &&
5927 (phy->speed_cap_mask >=
5928 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5929 (phy->speed_cap_mask <
5930 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5931 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5932 vars->phy_flags |= PHY_SGMII_FLAG;
5934 vars->phy_flags &= ~PHY_SGMII_FLAG;
5936 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5937 bnx2x_set_aer_mmd(params, phy);
5938 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5939 bnx2x_set_master_ln(params, phy);
5941 rc = bnx2x_reset_unicore(params, phy, 0);
5942 /* Reset the SerDes and wait for reset bit return low */
5946 bnx2x_set_aer_mmd(params, phy);
5947 /* Setting the masterLn_def again after the reset */
5948 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5949 bnx2x_set_master_ln(params, phy);
5950 bnx2x_set_swap_lanes(params, phy);
5956 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5957 struct bnx2x_phy *phy,
5958 struct link_params *params)
5961 /* Wait for soft reset to get cleared up to 1 sec */
5962 for (cnt = 0; cnt < 1000; cnt++) {
5963 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5964 bnx2x_cl22_read(bp, phy,
5965 MDIO_PMA_REG_CTRL, &ctrl);
5967 bnx2x_cl45_read(bp, phy,
5969 MDIO_PMA_REG_CTRL, &ctrl);
5970 if (!(ctrl & (1<<15)))
5972 usleep_range(1000, 2000);
5976 netdev_err(bp->dev, "Warning: PHY was not initialized,"
5979 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5983 static void bnx2x_link_int_enable(struct link_params *params)
5985 u8 port = params->port;
5987 struct bnx2x *bp = params->bp;
5989 /* Setting the status to report on link up for either XGXS or SerDes */
5990 if (CHIP_IS_E3(bp)) {
5991 mask = NIG_MASK_XGXS0_LINK_STATUS;
5992 if (!(SINGLE_MEDIA_DIRECT(params)))
5993 mask |= NIG_MASK_MI_INT;
5994 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5995 mask = (NIG_MASK_XGXS0_LINK10G |
5996 NIG_MASK_XGXS0_LINK_STATUS);
5997 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5998 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5999 params->phy[INT_PHY].type !=
6000 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6001 mask |= NIG_MASK_MI_INT;
6002 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6005 } else { /* SerDes */
6006 mask = NIG_MASK_SERDES0_LINK_STATUS;
6007 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6008 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6009 params->phy[INT_PHY].type !=
6010 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6011 mask |= NIG_MASK_MI_INT;
6012 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6016 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6019 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6020 (params->switch_cfg == SWITCH_CFG_10G),
6021 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6022 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6023 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6024 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6025 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6026 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6027 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6028 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6031 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6034 u32 latch_status = 0;
6036 /* Disable the MI INT ( external phy int ) by writing 1 to the
6037 * status register. Link down indication is high-active-signal,
6038 * so in this case we need to write the status to clear the XOR
6040 /* Read Latched signals */
6041 latch_status = REG_RD(bp,
6042 NIG_REG_LATCH_STATUS_0 + port*8);
6043 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6044 /* Handle only those with latched-signal=up.*/
6047 NIG_REG_STATUS_INTERRUPT_PORT0
6049 NIG_STATUS_EMAC0_MI_INT);
6052 NIG_REG_STATUS_INTERRUPT_PORT0
6054 NIG_STATUS_EMAC0_MI_INT);
6056 if (latch_status & 1) {
6058 /* For all latched-signal=up : Re-Arm Latch signals */
6059 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6060 (latch_status & 0xfffe) | (latch_status & 1));
6062 /* For all latched-signal=up,Write original_signal to status */
6065 static void bnx2x_link_int_ack(struct link_params *params,
6066 struct link_vars *vars, u8 is_10g_plus)
6068 struct bnx2x *bp = params->bp;
6069 u8 port = params->port;
6071 /* First reset all status we assume only one line will be
6074 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6075 (NIG_STATUS_XGXS0_LINK10G |
6076 NIG_STATUS_XGXS0_LINK_STATUS |
6077 NIG_STATUS_SERDES0_LINK_STATUS));
6078 if (vars->phy_link_up) {
6079 if (USES_WARPCORE(bp))
6080 mask = NIG_STATUS_XGXS0_LINK_STATUS;
6083 mask = NIG_STATUS_XGXS0_LINK10G;
6084 else if (params->switch_cfg == SWITCH_CFG_10G) {
6085 /* Disable the link interrupt by writing 1 to
6086 * the relevant lane in the status register
6089 ((params->lane_config &
6090 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6091 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6092 mask = ((1 << ser_lane) <<
6093 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6095 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6097 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6100 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6105 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6108 u32 mask = 0xf0000000;
6111 u8 remove_leading_zeros = 1;
6113 /* Need more than 10chars for this format */
6121 digit = ((num & mask) >> shift);
6122 if (digit == 0 && remove_leading_zeros) {
6125 } else if (digit < 0xa)
6126 *str_ptr = digit + '0';
6128 *str_ptr = digit - 0xa + 'a';
6129 remove_leading_zeros = 0;
6137 remove_leading_zeros = 1;
6144 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6151 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6157 u8 *ver_p = version;
6158 u16 remain_len = len;
6159 if (version == NULL || params == NULL)
6163 /* Extract first external phy*/
6165 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6167 if (params->phy[EXT_PHY1].format_fw_ver) {
6168 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6171 ver_p += (len - remain_len);
6173 if ((params->num_phys == MAX_PHYS) &&
6174 (params->phy[EXT_PHY2].ver_addr != 0)) {
6175 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6176 if (params->phy[EXT_PHY2].format_fw_ver) {
6180 status |= params->phy[EXT_PHY2].format_fw_ver(
6184 ver_p = version + (len - remain_len);
6191 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6192 struct link_params *params)
6194 u8 port = params->port;
6195 struct bnx2x *bp = params->bp;
6197 if (phy->req_line_speed != SPEED_1000) {
6200 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6202 if (!CHIP_IS_E3(bp)) {
6203 /* Change the uni_phy_addr in the nig */
6204 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6207 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6211 bnx2x_cl45_write(bp, phy,
6213 (MDIO_REG_BANK_AER_BLOCK +
6214 (MDIO_AER_BLOCK_AER_REG & 0xf)),
6217 bnx2x_cl45_write(bp, phy,
6219 (MDIO_REG_BANK_CL73_IEEEB0 +
6220 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6223 /* Set aer mmd back */
6224 bnx2x_set_aer_mmd(params, phy);
6226 if (!CHIP_IS_E3(bp)) {
6228 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6233 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6234 bnx2x_cl45_read(bp, phy, 5,
6235 (MDIO_REG_BANK_COMBO_IEEE0 +
6236 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6238 bnx2x_cl45_write(bp, phy, 5,
6239 (MDIO_REG_BANK_COMBO_IEEE0 +
6240 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6242 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6246 int bnx2x_set_led(struct link_params *params,
6247 struct link_vars *vars, u8 mode, u32 speed)
6249 u8 port = params->port;
6250 u16 hw_led_mode = params->hw_led_mode;
6254 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6255 struct bnx2x *bp = params->bp;
6256 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6257 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6258 speed, hw_led_mode);
6260 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6261 if (params->phy[phy_idx].set_link_led) {
6262 params->phy[phy_idx].set_link_led(
6263 ¶ms->phy[phy_idx], params, mode);
6268 case LED_MODE_FRONT_PANEL_OFF:
6270 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6271 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6272 SHARED_HW_CFG_LED_MAC1);
6274 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6275 if (params->phy[EXT_PHY1].type ==
6276 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6277 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6278 EMAC_LED_100MB_OVERRIDE |
6279 EMAC_LED_10MB_OVERRIDE);
6281 tmp |= EMAC_LED_OVERRIDE;
6283 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6287 /* For all other phys, OPER mode is same as ON, so in case
6288 * link is down, do nothing
6293 if (((params->phy[EXT_PHY1].type ==
6294 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6295 (params->phy[EXT_PHY1].type ==
6296 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6297 CHIP_IS_E2(bp) && params->num_phys == 2) {
6298 /* This is a work-around for E2+8727 Configurations */
6299 if (mode == LED_MODE_ON ||
6300 speed == SPEED_10000){
6301 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6302 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6304 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6305 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6306 (tmp | EMAC_LED_OVERRIDE));
6307 /* Return here without enabling traffic
6308 * LED blink and setting rate in ON mode.
6309 * In oper mode, enabling LED blink
6310 * and setting rate is needed.
6312 if (mode == LED_MODE_ON)
6315 } else if (SINGLE_MEDIA_DIRECT(params)) {
6316 /* This is a work-around for HW issue found when link
6319 if ((!CHIP_IS_E3(bp)) ||
6321 mode == LED_MODE_ON))
6322 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6324 if (CHIP_IS_E1x(bp) ||
6326 (mode == LED_MODE_ON))
6327 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6329 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6331 } else if ((params->phy[EXT_PHY1].type ==
6332 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6333 (mode == LED_MODE_ON)) {
6334 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6335 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6336 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6337 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6338 /* Break here; otherwise, it'll disable the
6339 * intended override.
6343 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6346 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6347 /* Set blinking rate to ~15.9Hz */
6349 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6350 LED_BLINK_RATE_VAL_E3);
6352 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6353 LED_BLINK_RATE_VAL_E1X_E2);
6354 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6356 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6357 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6358 (tmp & (~EMAC_LED_OVERRIDE)));
6360 if (CHIP_IS_E1(bp) &&
6361 ((speed == SPEED_2500) ||
6362 (speed == SPEED_1000) ||
6363 (speed == SPEED_100) ||
6364 (speed == SPEED_10))) {
6365 /* For speeds less than 10G LED scheme is different */
6366 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6368 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6370 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6377 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6385 /* This function comes to reflect the actual link state read DIRECTLY from the
6388 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6391 struct bnx2x *bp = params->bp;
6392 u16 gp_status = 0, phy_index = 0;
6393 u8 ext_phy_link_up = 0, serdes_phy_type;
6394 struct link_vars temp_vars;
6395 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
6397 if (CHIP_IS_E3(bp)) {
6399 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6401 /* Check 20G link */
6402 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6404 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6408 /* Check 10G link and below*/
6409 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6410 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6411 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6413 gp_status = ((gp_status >> 8) & 0xf) |
6414 ((gp_status >> 12) & 0xf);
6415 link_up = gp_status & (1 << lane);
6420 CL22_RD_OVER_CL45(bp, int_phy,
6421 MDIO_REG_BANK_GP_STATUS,
6422 MDIO_GP_STATUS_TOP_AN_STATUS1,
6424 /* Link is up only if both local phy and external phy are up */
6425 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6428 /* In XGXS loopback mode, do not check external PHY */
6429 if (params->loopback_mode == LOOPBACK_XGXS)
6432 switch (params->num_phys) {
6434 /* No external PHY */
6437 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6438 ¶ms->phy[EXT_PHY1],
6439 params, &temp_vars);
6441 case 3: /* Dual Media */
6442 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6444 serdes_phy_type = ((params->phy[phy_index].media_type ==
6445 ETH_PHY_SFPP_10G_FIBER) ||
6446 (params->phy[phy_index].media_type ==
6447 ETH_PHY_SFP_1G_FIBER) ||
6448 (params->phy[phy_index].media_type ==
6449 ETH_PHY_XFP_FIBER) ||
6450 (params->phy[phy_index].media_type ==
6451 ETH_PHY_DA_TWINAX));
6453 if (is_serdes != serdes_phy_type)
6455 if (params->phy[phy_index].read_status) {
6457 params->phy[phy_index].read_status(
6458 ¶ms->phy[phy_index],
6459 params, &temp_vars);
6464 if (ext_phy_link_up)
6469 static int bnx2x_link_initialize(struct link_params *params,
6470 struct link_vars *vars)
6473 u8 phy_index, non_ext_phy;
6474 struct bnx2x *bp = params->bp;
6475 /* In case of external phy existence, the line speed would be the
6476 * line speed linked up by the external phy. In case it is direct
6477 * only, then the line_speed during initialization will be
6478 * equal to the req_line_speed
6480 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6482 /* Initialize the internal phy in case this is a direct board
6483 * (no external phys), or this board has external phy which requires
6486 if (!USES_WARPCORE(bp))
6487 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars);
6488 /* init ext phy and enable link state int */
6489 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6490 (params->loopback_mode == LOOPBACK_XGXS));
6493 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6494 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6495 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
6496 if (vars->line_speed == SPEED_AUTO_NEG &&
6499 bnx2x_set_parallel_detection(phy, params);
6500 if (params->phy[INT_PHY].config_init)
6501 params->phy[INT_PHY].config_init(phy,
6506 /* Init external phy*/
6508 if (params->phy[INT_PHY].supported &
6510 vars->link_status |= LINK_STATUS_SERDES_LINK;
6512 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6514 /* No need to initialize second phy in case of first
6515 * phy only selection. In case of second phy, we do
6516 * need to initialize the first phy, since they are
6519 if (params->phy[phy_index].supported &
6521 vars->link_status |= LINK_STATUS_SERDES_LINK;
6523 if (phy_index == EXT_PHY2 &&
6524 (bnx2x_phy_selection(params) ==
6525 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6527 "Not initializing second phy\n");
6530 params->phy[phy_index].config_init(
6531 ¶ms->phy[phy_index],
6535 /* Reset the interrupt indication after phy was initialized */
6536 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6538 (NIG_STATUS_XGXS0_LINK10G |
6539 NIG_STATUS_XGXS0_LINK_STATUS |
6540 NIG_STATUS_SERDES0_LINK_STATUS |
6545 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6546 struct link_params *params)
6548 /* Reset the SerDes/XGXS */
6549 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6550 (0x1ff << (params->port*16)));
6553 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6554 struct link_params *params)
6556 struct bnx2x *bp = params->bp;
6560 gpio_port = BP_PATH(bp);
6562 gpio_port = params->port;
6563 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6564 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6566 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6567 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6569 DP(NETIF_MSG_LINK, "reset external PHY\n");
6572 static int bnx2x_update_link_down(struct link_params *params,
6573 struct link_vars *vars)
6575 struct bnx2x *bp = params->bp;
6576 u8 port = params->port;
6578 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6579 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6580 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6581 /* Indicate no mac active */
6582 vars->mac_type = MAC_TYPE_NONE;
6584 /* Update shared memory */
6585 vars->link_status &= ~LINK_UPDATE_MASK;
6586 vars->line_speed = 0;
6587 bnx2x_update_mng(params, vars->link_status);
6589 /* Activate nig drain */
6590 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6593 if (!CHIP_IS_E3(bp))
6594 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6596 usleep_range(10000, 20000);
6597 /* Reset BigMac/Xmac */
6598 if (CHIP_IS_E1x(bp) ||
6600 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6602 if (CHIP_IS_E3(bp)) {
6603 /* Prevent LPI Generation by chip */
6604 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6606 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6608 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6609 SHMEM_EEE_ACTIVE_BIT);
6611 bnx2x_update_mng_eee(params, vars->eee_status);
6612 bnx2x_set_xmac_rxtx(params, 0);
6613 bnx2x_set_umac_rxtx(params, 0);
6619 static int bnx2x_update_link_up(struct link_params *params,
6620 struct link_vars *vars,
6623 struct bnx2x *bp = params->bp;
6624 u8 phy_idx, port = params->port;
6627 vars->link_status |= (LINK_STATUS_LINK_UP |
6628 LINK_STATUS_PHYSICAL_LINK_FLAG);
6629 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6631 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6632 vars->link_status |=
6633 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6635 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6636 vars->link_status |=
6637 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6638 if (USES_WARPCORE(bp)) {
6640 if (bnx2x_xmac_enable(params, vars, 0) ==
6642 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6644 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6645 vars->link_status &= ~LINK_STATUS_LINK_UP;
6648 bnx2x_umac_enable(params, vars, 0);
6649 bnx2x_set_led(params, vars,
6650 LED_MODE_OPER, vars->line_speed);
6652 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6653 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6654 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6655 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6656 (params->port << 2), 1);
6657 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6658 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6659 (params->port << 2), 0xfc20);
6662 if ((CHIP_IS_E1x(bp) ||
6665 if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6667 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6669 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6670 vars->link_status &= ~LINK_STATUS_LINK_UP;
6673 bnx2x_set_led(params, vars,
6674 LED_MODE_OPER, SPEED_10000);
6676 rc = bnx2x_emac_program(params, vars);
6677 bnx2x_emac_enable(params, vars, 0);
6680 if ((vars->link_status &
6681 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6682 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6683 SINGLE_MEDIA_DIRECT(params))
6684 bnx2x_set_gmii_tx_driver(params);
6689 if (CHIP_IS_E1x(bp))
6690 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6694 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6696 /* Update shared memory */
6697 bnx2x_update_mng(params, vars->link_status);
6698 bnx2x_update_mng_eee(params, vars->eee_status);
6699 /* Check remote fault */
6700 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6701 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6702 bnx2x_check_half_open_conn(params, vars, 0);
6709 /* The bnx2x_link_update function should be called upon link
6711 * Link is considered up as follows:
6712 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6714 * - SINGLE_MEDIA - The link between the 577xx and the external
6715 * phy (XGXS) need to up as well as the external link of the
6717 * - DUAL_MEDIA - The link between the 577xx and the first
6718 * external phy needs to be up, and at least one of the 2
6719 * external phy link must be up.
6721 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6723 struct bnx2x *bp = params->bp;
6724 struct link_vars phy_vars[MAX_PHYS];
6725 u8 port = params->port;
6726 u8 link_10g_plus, phy_index;
6727 u8 ext_phy_link_up = 0, cur_link_up;
6730 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6731 u8 active_external_phy = INT_PHY;
6732 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6733 vars->link_status &= ~LINK_UPDATE_MASK;
6734 for (phy_index = INT_PHY; phy_index < params->num_phys;
6736 phy_vars[phy_index].flow_ctrl = 0;
6737 phy_vars[phy_index].link_status = 0;
6738 phy_vars[phy_index].line_speed = 0;
6739 phy_vars[phy_index].duplex = DUPLEX_FULL;
6740 phy_vars[phy_index].phy_link_up = 0;
6741 phy_vars[phy_index].link_up = 0;
6742 phy_vars[phy_index].fault_detected = 0;
6743 /* different consideration, since vars holds inner state */
6744 phy_vars[phy_index].eee_status = vars->eee_status;
6747 if (USES_WARPCORE(bp))
6748 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]);
6750 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6751 port, (vars->phy_flags & PHY_XGXS_FLAG),
6752 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6754 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6756 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6757 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6759 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6761 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6762 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6763 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6766 if (!CHIP_IS_E3(bp))
6767 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6770 * Check external link change only for external phys, and apply
6771 * priority selection between them in case the link on both phys
6772 * is up. Note that instead of the common vars, a temporary
6773 * vars argument is used since each phy may have different link/
6774 * speed/duplex result
6776 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6778 struct bnx2x_phy *phy = ¶ms->phy[phy_index];
6779 if (!phy->read_status)
6781 /* Read link status and params of this ext phy */
6782 cur_link_up = phy->read_status(phy, params,
6783 &phy_vars[phy_index]);
6785 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6788 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6793 if (!ext_phy_link_up) {
6794 ext_phy_link_up = 1;
6795 active_external_phy = phy_index;
6797 switch (bnx2x_phy_selection(params)) {
6798 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6799 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6800 /* In this option, the first PHY makes sure to pass the
6801 * traffic through itself only.
6802 * Its not clear how to reset the link on the second phy
6804 active_external_phy = EXT_PHY1;
6806 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6807 /* In this option, the first PHY makes sure to pass the
6808 * traffic through the second PHY.
6810 active_external_phy = EXT_PHY2;
6813 /* Link indication on both PHYs with the following cases
6815 * - FIRST_PHY means that second phy wasn't initialized,
6816 * hence its link is expected to be down
6817 * - SECOND_PHY means that first phy should not be able
6818 * to link up by itself (using configuration)
6819 * - DEFAULT should be overriden during initialiazation
6821 DP(NETIF_MSG_LINK, "Invalid link indication"
6822 "mpc=0x%x. DISABLING LINK !!!\n",
6823 params->multi_phy_config);
6824 ext_phy_link_up = 0;
6829 prev_line_speed = vars->line_speed;
6831 * Read the status of the internal phy. In case of
6832 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6833 * otherwise this is the link between the 577xx and the first
6836 if (params->phy[INT_PHY].read_status)
6837 params->phy[INT_PHY].read_status(
6838 ¶ms->phy[INT_PHY],
6840 /* The INT_PHY flow control reside in the vars. This include the
6841 * case where the speed or flow control are not set to AUTO.
6842 * Otherwise, the active external phy flow control result is set
6843 * to the vars. The ext_phy_line_speed is needed to check if the
6844 * speed is different between the internal phy and external phy.
6845 * This case may be result of intermediate link speed change.
6847 if (active_external_phy > INT_PHY) {
6848 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6849 /* Link speed is taken from the XGXS. AN and FC result from
6852 vars->link_status |= phy_vars[active_external_phy].link_status;
6854 /* if active_external_phy is first PHY and link is up - disable
6855 * disable TX on second external PHY
6857 if (active_external_phy == EXT_PHY1) {
6858 if (params->phy[EXT_PHY2].phy_specific_func) {
6860 "Disabling TX on EXT_PHY2\n");
6861 params->phy[EXT_PHY2].phy_specific_func(
6862 ¶ms->phy[EXT_PHY2],
6863 params, DISABLE_TX);
6867 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6868 vars->duplex = phy_vars[active_external_phy].duplex;
6869 if (params->phy[active_external_phy].supported &
6871 vars->link_status |= LINK_STATUS_SERDES_LINK;
6873 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6875 vars->eee_status = phy_vars[active_external_phy].eee_status;
6877 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6878 active_external_phy);
6881 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6883 if (params->phy[phy_index].flags &
6884 FLAGS_REARM_LATCH_SIGNAL) {
6885 bnx2x_rearm_latch_signal(bp, port,
6887 active_external_phy);
6891 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6892 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6893 vars->link_status, ext_phy_line_speed);
6894 /* Upon link speed change set the NIG into drain mode. Comes to
6895 * deals with possible FIFO glitch due to clk change when speed
6896 * is decreased without link down indicator
6899 if (vars->phy_link_up) {
6900 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6901 (ext_phy_line_speed != vars->line_speed)) {
6902 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6903 " different than the external"
6904 " link speed %d\n", vars->line_speed,
6905 ext_phy_line_speed);
6906 vars->phy_link_up = 0;
6907 } else if (prev_line_speed != vars->line_speed) {
6908 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6910 usleep_range(1000, 2000);
6914 /* Anything 10 and over uses the bmac */
6915 link_10g_plus = (vars->line_speed >= SPEED_10000);
6917 bnx2x_link_int_ack(params, vars, link_10g_plus);
6919 /* In case external phy link is up, and internal link is down
6920 * (not initialized yet probably after link initialization, it
6921 * needs to be initialized.
6922 * Note that after link down-up as result of cable plug, the xgxs
6923 * link would probably become up again without the need
6926 if (!(SINGLE_MEDIA_DIRECT(params))) {
6927 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6928 " init_preceding = %d\n", ext_phy_link_up,
6930 params->phy[EXT_PHY1].flags &
6931 FLAGS_INIT_XGXS_FIRST);
6932 if (!(params->phy[EXT_PHY1].flags &
6933 FLAGS_INIT_XGXS_FIRST)
6934 && ext_phy_link_up && !vars->phy_link_up) {
6935 vars->line_speed = ext_phy_line_speed;
6936 if (vars->line_speed < SPEED_1000)
6937 vars->phy_flags |= PHY_SGMII_FLAG;
6939 vars->phy_flags &= ~PHY_SGMII_FLAG;
6941 if (params->phy[INT_PHY].config_init)
6942 params->phy[INT_PHY].config_init(
6943 ¶ms->phy[INT_PHY], params,
6947 /* Link is up only if both local phy and external phy (in case of
6948 * non-direct board) are up and no fault detected on active PHY.
6950 vars->link_up = (vars->phy_link_up &&
6952 SINGLE_MEDIA_DIRECT(params)) &&
6953 (phy_vars[active_external_phy].fault_detected == 0));
6955 /* Update the PFC configuration in case it was changed */
6956 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6957 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6959 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6962 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6964 rc = bnx2x_update_link_down(params, vars);
6966 /* Update MCP link status was changed */
6967 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6968 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6973 /*****************************************************************************/
6974 /* External Phy section */
6975 /*****************************************************************************/
6976 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6978 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6979 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6980 usleep_range(1000, 2000);
6981 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6982 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6985 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6986 u32 spirom_ver, u32 ver_addr)
6988 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6989 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6992 REG_WR(bp, ver_addr, spirom_ver);
6995 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6996 struct bnx2x_phy *phy,
6999 u16 fw_ver1, fw_ver2;
7001 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7002 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7003 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7004 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7005 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7009 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7010 struct bnx2x_phy *phy,
7011 struct link_vars *vars)
7014 bnx2x_cl45_read(bp, phy,
7016 MDIO_AN_REG_STATUS, &val);
7017 bnx2x_cl45_read(bp, phy,
7019 MDIO_AN_REG_STATUS, &val);
7021 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7022 if ((val & (1<<0)) == 0)
7023 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7026 /******************************************************************/
7027 /* common BCM8073/BCM8727 PHY SECTION */
7028 /******************************************************************/
7029 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7030 struct link_params *params,
7031 struct link_vars *vars)
7033 struct bnx2x *bp = params->bp;
7034 if (phy->req_line_speed == SPEED_10 ||
7035 phy->req_line_speed == SPEED_100) {
7036 vars->flow_ctrl = phy->req_flow_ctrl;
7040 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7041 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7043 u16 ld_pause; /* local */
7044 u16 lp_pause; /* link partner */
7045 bnx2x_cl45_read(bp, phy,
7047 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7049 bnx2x_cl45_read(bp, phy,
7051 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7052 pause_result = (ld_pause &
7053 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7054 pause_result |= (lp_pause &
7055 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7057 bnx2x_pause_resolve(vars, pause_result);
7058 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7062 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7063 struct bnx2x_phy *phy,
7067 u16 fw_ver1, fw_msgout;
7070 /* Boot port from external ROM */
7072 bnx2x_cl45_write(bp, phy,
7074 MDIO_PMA_REG_GEN_CTRL,
7077 /* Ucode reboot and rst */
7078 bnx2x_cl45_write(bp, phy,
7080 MDIO_PMA_REG_GEN_CTRL,
7083 bnx2x_cl45_write(bp, phy,
7085 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7087 /* Reset internal microprocessor */
7088 bnx2x_cl45_write(bp, phy,
7090 MDIO_PMA_REG_GEN_CTRL,
7091 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7093 /* Release srst bit */
7094 bnx2x_cl45_write(bp, phy,
7096 MDIO_PMA_REG_GEN_CTRL,
7097 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7099 /* Delay 100ms per the PHY specifications */
7102 /* 8073 sometimes taking longer to download */
7107 "bnx2x_8073_8727_external_rom_boot port %x:"
7108 "Download failed. fw version = 0x%x\n",
7114 bnx2x_cl45_read(bp, phy,
7116 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7117 bnx2x_cl45_read(bp, phy,
7119 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7121 usleep_range(1000, 2000);
7122 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7123 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7124 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7126 /* Clear ser_boot_ctl bit */
7127 bnx2x_cl45_write(bp, phy,
7129 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7130 bnx2x_save_bcm_spirom_ver(bp, phy, port);
7133 "bnx2x_8073_8727_external_rom_boot port %x:"
7134 "Download complete. fw version = 0x%x\n",
7140 /******************************************************************/
7141 /* BCM8073 PHY SECTION */
7142 /******************************************************************/
7143 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7145 /* This is only required for 8073A1, version 102 only */
7148 /* Read 8073 HW revision*/
7149 bnx2x_cl45_read(bp, phy,
7151 MDIO_PMA_REG_8073_CHIP_REV, &val);
7154 /* No need to workaround in 8073 A1 */
7158 bnx2x_cl45_read(bp, phy,
7160 MDIO_PMA_REG_ROM_VER2, &val);
7162 /* SNR should be applied only for version 0x102 */
7169 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7171 u16 val, cnt, cnt1 ;
7173 bnx2x_cl45_read(bp, phy,
7175 MDIO_PMA_REG_8073_CHIP_REV, &val);
7178 /* No need to workaround in 8073 A1 */
7181 /* XAUI workaround in 8073 A0: */
7183 /* After loading the boot ROM and restarting Autoneg, poll
7187 for (cnt = 0; cnt < 1000; cnt++) {
7188 bnx2x_cl45_read(bp, phy,
7190 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7192 /* If bit [14] = 0 or bit [13] = 0, continue on with
7193 * system initialization (XAUI work-around not required, as
7194 * these bits indicate 2.5G or 1G link up).
7196 if (!(val & (1<<14)) || !(val & (1<<13))) {
7197 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7199 } else if (!(val & (1<<15))) {
7200 DP(NETIF_MSG_LINK, "bit 15 went off\n");
7201 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7202 * MSB (bit15) goes to 1 (indicating that the XAUI
7203 * workaround has completed), then continue on with
7204 * system initialization.
7206 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7207 bnx2x_cl45_read(bp, phy,
7209 MDIO_PMA_REG_8073_XAUI_WA, &val);
7210 if (val & (1<<15)) {
7212 "XAUI workaround has completed\n");
7215 usleep_range(3000, 6000);
7219 usleep_range(3000, 6000);
7221 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7225 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7227 /* Force KR or KX */
7228 bnx2x_cl45_write(bp, phy,
7229 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7230 bnx2x_cl45_write(bp, phy,
7231 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7232 bnx2x_cl45_write(bp, phy,
7233 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7234 bnx2x_cl45_write(bp, phy,
7235 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7238 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7239 struct bnx2x_phy *phy,
7240 struct link_vars *vars)
7243 struct bnx2x *bp = params->bp;
7244 bnx2x_cl45_read(bp, phy,
7245 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7247 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7248 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7249 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7250 if ((vars->ieee_fc &
7251 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7252 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7253 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7255 if ((vars->ieee_fc &
7256 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7257 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7258 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7260 if ((vars->ieee_fc &
7261 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7262 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7263 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7266 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7268 bnx2x_cl45_write(bp, phy,
7269 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7273 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7274 struct link_params *params,
7277 struct bnx2x *bp = params->bp;
7281 bnx2x_cl45_write(bp, phy,
7282 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7283 bnx2x_cl45_write(bp, phy,
7284 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
7289 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7290 struct link_params *params,
7291 struct link_vars *vars)
7293 struct bnx2x *bp = params->bp;
7296 DP(NETIF_MSG_LINK, "Init 8073\n");
7299 gpio_port = BP_PATH(bp);
7301 gpio_port = params->port;
7302 /* Restore normal power mode*/
7303 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7304 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7306 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7307 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7309 bnx2x_8073_specific_func(phy, params, PHY_INIT);
7310 bnx2x_8073_set_pause_cl37(params, phy, vars);
7312 bnx2x_cl45_read(bp, phy,
7313 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7315 bnx2x_cl45_read(bp, phy,
7316 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7318 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7320 /* Swap polarity if required - Must be done only in non-1G mode */
7321 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7322 /* Configure the 8073 to swap _P and _N of the KR lines */
7323 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7324 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7325 bnx2x_cl45_read(bp, phy,
7327 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7328 bnx2x_cl45_write(bp, phy,
7330 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7335 /* Enable CL37 BAM */
7336 if (REG_RD(bp, params->shmem_base +
7337 offsetof(struct shmem_region, dev_info.
7338 port_hw_config[params->port].default_cfg)) &
7339 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7341 bnx2x_cl45_read(bp, phy,
7343 MDIO_AN_REG_8073_BAM, &val);
7344 bnx2x_cl45_write(bp, phy,
7346 MDIO_AN_REG_8073_BAM, val | 1);
7347 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7349 if (params->loopback_mode == LOOPBACK_EXT) {
7350 bnx2x_807x_force_10G(bp, phy);
7351 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7354 bnx2x_cl45_write(bp, phy,
7355 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7357 if (phy->req_line_speed != SPEED_AUTO_NEG) {
7358 if (phy->req_line_speed == SPEED_10000) {
7360 } else if (phy->req_line_speed == SPEED_2500) {
7362 /* Note that 2.5G works only when used with 1G
7369 if (phy->speed_cap_mask &
7370 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7373 /* Note that 2.5G works only when used with 1G advertisement */
7374 if (phy->speed_cap_mask &
7375 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7376 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7378 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7381 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7382 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7384 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7385 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7386 (phy->req_line_speed == SPEED_2500)) {
7388 /* Allow 2.5G for A1 and above */
7389 bnx2x_cl45_read(bp, phy,
7390 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7392 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7398 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7402 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7403 /* Add support for CL37 (passive mode) II */
7405 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7406 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7407 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7410 /* Add support for CL37 (passive mode) III */
7411 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7413 /* The SNR will improve about 2db by changing BW and FEE main
7414 * tap. Rest commands are executed after link is up
7415 * Change FFE main cursor to 5 in EDC register
7417 if (bnx2x_8073_is_snr_needed(bp, phy))
7418 bnx2x_cl45_write(bp, phy,
7419 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7422 /* Enable FEC (Forware Error Correction) Request in the AN */
7423 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7425 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7427 bnx2x_ext_phy_set_pause(params, phy, vars);
7429 /* Restart autoneg */
7431 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7432 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7433 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7437 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7438 struct link_params *params,
7439 struct link_vars *vars)
7441 struct bnx2x *bp = params->bp;
7444 u16 link_status = 0;
7445 u16 an1000_status = 0;
7447 bnx2x_cl45_read(bp, phy,
7448 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7450 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7452 /* Clear the interrupt LASI status register */
7453 bnx2x_cl45_read(bp, phy,
7454 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7455 bnx2x_cl45_read(bp, phy,
7456 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7457 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7459 bnx2x_cl45_read(bp, phy,
7460 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7462 /* Check the LASI */
7463 bnx2x_cl45_read(bp, phy,
7464 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7466 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7468 /* Check the link status */
7469 bnx2x_cl45_read(bp, phy,
7470 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7471 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7473 bnx2x_cl45_read(bp, phy,
7474 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7475 bnx2x_cl45_read(bp, phy,
7476 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7477 link_up = ((val1 & 4) == 4);
7478 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7481 ((phy->req_line_speed != SPEED_10000))) {
7482 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7485 bnx2x_cl45_read(bp, phy,
7486 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7487 bnx2x_cl45_read(bp, phy,
7488 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7490 /* Check the link status on 1.1.2 */
7491 bnx2x_cl45_read(bp, phy,
7492 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7493 bnx2x_cl45_read(bp, phy,
7494 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7495 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7496 "an_link_status=0x%x\n", val2, val1, an1000_status);
7498 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7499 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7500 /* The SNR will improve about 2dbby changing the BW and FEE main
7501 * tap. The 1st write to change FFE main tap is set before
7502 * restart AN. Change PLL Bandwidth in EDC register
7504 bnx2x_cl45_write(bp, phy,
7505 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7508 /* Change CDR Bandwidth in EDC register */
7509 bnx2x_cl45_write(bp, phy,
7510 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7513 bnx2x_cl45_read(bp, phy,
7514 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7517 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7518 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7520 vars->line_speed = SPEED_10000;
7521 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7523 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7525 vars->line_speed = SPEED_2500;
7526 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7528 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7530 vars->line_speed = SPEED_1000;
7531 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7535 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7540 /* Swap polarity if required */
7541 if (params->lane_config &
7542 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7543 /* Configure the 8073 to swap P and N of the KR lines */
7544 bnx2x_cl45_read(bp, phy,
7546 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7547 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7548 * when it`s in 10G mode.
7550 if (vars->line_speed == SPEED_1000) {
7551 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7557 bnx2x_cl45_write(bp, phy,
7559 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7562 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7563 bnx2x_8073_resolve_fc(phy, params, vars);
7564 vars->duplex = DUPLEX_FULL;
7567 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7568 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7569 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7572 vars->link_status |=
7573 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7575 vars->link_status |=
7576 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7582 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7583 struct link_params *params)
7585 struct bnx2x *bp = params->bp;
7588 gpio_port = BP_PATH(bp);
7590 gpio_port = params->port;
7591 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7593 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7594 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7598 /******************************************************************/
7599 /* BCM8705 PHY SECTION */
7600 /******************************************************************/
7601 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7602 struct link_params *params,
7603 struct link_vars *vars)
7605 struct bnx2x *bp = params->bp;
7606 DP(NETIF_MSG_LINK, "init 8705\n");
7607 /* Restore normal power mode*/
7608 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7609 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7611 bnx2x_ext_phy_hw_reset(bp, params->port);
7612 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7613 bnx2x_wait_reset_complete(bp, phy, params);
7615 bnx2x_cl45_write(bp, phy,
7616 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7617 bnx2x_cl45_write(bp, phy,
7618 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7619 bnx2x_cl45_write(bp, phy,
7620 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7621 bnx2x_cl45_write(bp, phy,
7622 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7623 /* BCM8705 doesn't have microcode, hence the 0 */
7624 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7628 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7629 struct link_params *params,
7630 struct link_vars *vars)
7634 struct bnx2x *bp = params->bp;
7635 DP(NETIF_MSG_LINK, "read status 8705\n");
7636 bnx2x_cl45_read(bp, phy,
7637 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7638 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7640 bnx2x_cl45_read(bp, phy,
7641 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7642 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7644 bnx2x_cl45_read(bp, phy,
7645 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7647 bnx2x_cl45_read(bp, phy,
7648 MDIO_PMA_DEVAD, 0xc809, &val1);
7649 bnx2x_cl45_read(bp, phy,
7650 MDIO_PMA_DEVAD, 0xc809, &val1);
7652 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7653 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7655 vars->line_speed = SPEED_10000;
7656 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7661 /******************************************************************/
7662 /* SFP+ module Section */
7663 /******************************************************************/
7664 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7665 struct bnx2x_phy *phy,
7668 struct bnx2x *bp = params->bp;
7669 /* Disable transmitter only for bootcodes which can enable it afterwards
7673 if (params->feature_config_flags &
7674 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7675 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7677 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7681 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7682 bnx2x_cl45_write(bp, phy,
7684 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7687 static u8 bnx2x_get_gpio_port(struct link_params *params)
7690 u32 swap_val, swap_override;
7691 struct bnx2x *bp = params->bp;
7693 gpio_port = BP_PATH(bp);
7695 gpio_port = params->port;
7696 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7697 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7698 return gpio_port ^ (swap_val && swap_override);
7701 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7702 struct bnx2x_phy *phy,
7706 u8 port = params->port;
7707 struct bnx2x *bp = params->bp;
7710 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7711 tx_en_mode = REG_RD(bp, params->shmem_base +
7712 offsetof(struct shmem_region,
7713 dev_info.port_hw_config[port].sfp_ctrl)) &
7714 PORT_HW_CFG_TX_LASER_MASK;
7715 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7716 "mode = %x\n", tx_en, port, tx_en_mode);
7717 switch (tx_en_mode) {
7718 case PORT_HW_CFG_TX_LASER_MDIO:
7720 bnx2x_cl45_read(bp, phy,
7722 MDIO_PMA_REG_PHY_IDENTIFIER,
7730 bnx2x_cl45_write(bp, phy,
7732 MDIO_PMA_REG_PHY_IDENTIFIER,
7735 case PORT_HW_CFG_TX_LASER_GPIO0:
7736 case PORT_HW_CFG_TX_LASER_GPIO1:
7737 case PORT_HW_CFG_TX_LASER_GPIO2:
7738 case PORT_HW_CFG_TX_LASER_GPIO3:
7741 u8 gpio_port, gpio_mode;
7743 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7745 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7747 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7748 gpio_port = bnx2x_get_gpio_port(params);
7749 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7753 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7758 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7759 struct bnx2x_phy *phy,
7762 struct bnx2x *bp = params->bp;
7763 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7765 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7767 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7770 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7771 struct link_params *params,
7772 u8 dev_addr, u16 addr, u8 byte_cnt,
7773 u8 *o_buf, u8 is_init)
7775 struct bnx2x *bp = params->bp;
7778 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7780 "Reading from eeprom is limited to 0xf\n");
7783 /* Set the read command byte count */
7784 bnx2x_cl45_write(bp, phy,
7785 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7786 (byte_cnt | (dev_addr << 8)));
7788 /* Set the read command address */
7789 bnx2x_cl45_write(bp, phy,
7790 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7793 /* Activate read command */
7794 bnx2x_cl45_write(bp, phy,
7795 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7798 /* Wait up to 500us for command complete status */
7799 for (i = 0; i < 100; i++) {
7800 bnx2x_cl45_read(bp, phy,
7802 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7803 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7804 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7809 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7810 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7812 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7813 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7817 /* Read the buffer */
7818 for (i = 0; i < byte_cnt; i++) {
7819 bnx2x_cl45_read(bp, phy,
7821 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7822 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7825 for (i = 0; i < 100; i++) {
7826 bnx2x_cl45_read(bp, phy,
7828 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7829 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7830 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7832 usleep_range(1000, 2000);
7837 static void bnx2x_warpcore_power_module(struct link_params *params,
7841 struct bnx2x *bp = params->bp;
7843 pin_cfg = (REG_RD(bp, params->shmem_base +
7844 offsetof(struct shmem_region,
7845 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7846 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7847 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7849 if (pin_cfg == PIN_CFG_NA)
7851 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7853 /* Low ==> corresponding SFP+ module is powered
7854 * high ==> the SFP+ module is powered down
7856 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7858 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7859 struct link_params *params,
7861 u16 addr, u8 byte_cnt,
7862 u8 *o_buf, u8 is_init)
7865 u8 i, j = 0, cnt = 0;
7868 struct bnx2x *bp = params->bp;
7870 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7872 "Reading from eeprom is limited to 16 bytes\n");
7876 /* 4 byte aligned address */
7877 addr32 = addr & (~0x3);
7879 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7880 bnx2x_warpcore_power_module(params, 0);
7881 /* Note that 100us are not enough here */
7882 usleep_range(1000, 2000);
7883 bnx2x_warpcore_power_module(params, 1);
7885 rc = bnx2x_bsc_read(params, phy, dev_addr, addr32, 0, byte_cnt,
7887 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7890 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7891 o_buf[j] = *((u8 *)data_array + i);
7899 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7900 struct link_params *params,
7901 u8 dev_addr, u16 addr, u8 byte_cnt,
7902 u8 *o_buf, u8 is_init)
7904 struct bnx2x *bp = params->bp;
7907 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7909 "Reading from eeprom is limited to 0xf\n");
7913 /* Set 2-wire transfer rate of SFP+ module EEPROM
7914 * to 100Khz since some DACs(direct attached cables) do
7915 * not work at 400Khz.
7917 bnx2x_cl45_write(bp, phy,
7919 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7920 ((dev_addr << 8) | 1));
7922 /* Need to read from 1.8000 to clear it */
7923 bnx2x_cl45_read(bp, phy,
7925 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7928 /* Set the read command byte count */
7929 bnx2x_cl45_write(bp, phy,
7931 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7932 ((byte_cnt < 2) ? 2 : byte_cnt));
7934 /* Set the read command address */
7935 bnx2x_cl45_write(bp, phy,
7937 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7939 /* Set the destination address */
7940 bnx2x_cl45_write(bp, phy,
7943 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7945 /* Activate read command */
7946 bnx2x_cl45_write(bp, phy,
7948 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7950 /* Wait appropriate time for two-wire command to finish before
7951 * polling the status register
7953 usleep_range(1000, 2000);
7955 /* Wait up to 500us for command complete status */
7956 for (i = 0; i < 100; i++) {
7957 bnx2x_cl45_read(bp, phy,
7959 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7960 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7961 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7966 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7967 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7969 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7970 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7974 /* Read the buffer */
7975 for (i = 0; i < byte_cnt; i++) {
7976 bnx2x_cl45_read(bp, phy,
7978 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7979 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7982 for (i = 0; i < 100; i++) {
7983 bnx2x_cl45_read(bp, phy,
7985 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7986 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7987 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7989 usleep_range(1000, 2000);
7994 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7995 struct link_params *params, u8 dev_addr,
7996 u16 addr, u16 byte_cnt, u8 *o_buf)
7999 struct bnx2x *bp = params->bp;
8001 u8 *user_data = o_buf;
8002 read_sfp_module_eeprom_func_p read_func;
8004 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8005 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8009 switch (phy->type) {
8010 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8011 read_func = bnx2x_8726_read_sfp_module_eeprom;
8013 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8014 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8015 read_func = bnx2x_8727_read_sfp_module_eeprom;
8017 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8018 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8024 while (!rc && (byte_cnt > 0)) {
8025 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8026 SFP_EEPROM_PAGE_SIZE : byte_cnt;
8027 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8029 byte_cnt -= xfer_size;
8030 user_data += xfer_size;
8036 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8037 struct link_params *params,
8040 struct bnx2x *bp = params->bp;
8041 u32 sync_offset = 0, phy_idx, media_types;
8042 u8 gport, val[2], check_limiting_mode = 0;
8043 *edc_mode = EDC_MODE_LIMITING;
8044 phy->media_type = ETH_PHY_UNSPECIFIED;
8045 /* First check for copper cable */
8046 if (bnx2x_read_sfp_module_eeprom(phy,
8049 SFP_EEPROM_CON_TYPE_ADDR,
8052 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8057 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8059 u8 copper_module_type;
8060 phy->media_type = ETH_PHY_DA_TWINAX;
8061 /* Check if its active cable (includes SFP+ module)
8064 if (bnx2x_read_sfp_module_eeprom(phy,
8067 SFP_EEPROM_FC_TX_TECH_ADDR,
8069 &copper_module_type) != 0) {
8071 "Failed to read copper-cable-type"
8072 " from SFP+ EEPROM\n");
8076 if (copper_module_type &
8077 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8078 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8079 check_limiting_mode = 1;
8080 } else if (copper_module_type &
8081 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8083 "Passive Copper cable detected\n");
8085 EDC_MODE_PASSIVE_DAC;
8088 "Unknown copper-cable-type 0x%x !!!\n",
8089 copper_module_type);
8094 case SFP_EEPROM_CON_TYPE_VAL_LC:
8095 case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8096 check_limiting_mode = 1;
8097 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8098 SFP_EEPROM_COMP_CODE_LR_MASK |
8099 SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8100 DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8101 gport = params->port;
8102 phy->media_type = ETH_PHY_SFP_1G_FIBER;
8103 if (phy->req_line_speed != SPEED_1000) {
8104 phy->req_line_speed = SPEED_1000;
8105 if (!CHIP_IS_E1x(bp)) {
8106 gport = BP_PATH(bp) +
8107 (params->port << 1);
8110 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8114 int idx, cfg_idx = 0;
8115 DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8116 for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8117 if (params->phy[idx].type == phy->type) {
8118 cfg_idx = LINK_CONFIG_IDX(idx);
8122 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8123 phy->req_line_speed = params->req_line_speed[cfg_idx];
8127 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8131 sync_offset = params->shmem_base +
8132 offsetof(struct shmem_region,
8133 dev_info.port_hw_config[params->port].media_type);
8134 media_types = REG_RD(bp, sync_offset);
8135 /* Update media type for non-PMF sync */
8136 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8137 if (&(params->phy[phy_idx]) == phy) {
8138 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8139 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8140 media_types |= ((phy->media_type &
8141 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8142 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8146 REG_WR(bp, sync_offset, media_types);
8147 if (check_limiting_mode) {
8148 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8149 if (bnx2x_read_sfp_module_eeprom(phy,
8152 SFP_EEPROM_OPTIONS_ADDR,
8153 SFP_EEPROM_OPTIONS_SIZE,
8156 "Failed to read Option field from module EEPROM\n");
8159 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8160 *edc_mode = EDC_MODE_LINEAR;
8162 *edc_mode = EDC_MODE_LIMITING;
8164 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8167 /* This function read the relevant field from the module (SFP+), and verify it
8168 * is compliant with this board
8170 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8171 struct link_params *params)
8173 struct bnx2x *bp = params->bp;
8175 u32 fw_resp, fw_cmd_param;
8176 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8177 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8178 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8179 val = REG_RD(bp, params->shmem_base +
8180 offsetof(struct shmem_region, dev_info.
8181 port_feature_config[params->port].config));
8182 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8183 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8184 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8188 if (params->feature_config_flags &
8189 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8190 /* Use specific phy request */
8191 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8192 } else if (params->feature_config_flags &
8193 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8194 /* Use first phy request only in case of non-dual media*/
8195 if (DUAL_MEDIA(params)) {
8197 "FW does not support OPT MDL verification\n");
8200 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8202 /* No support in OPT MDL detection */
8204 "FW does not support OPT MDL verification\n");
8208 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8209 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8210 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8211 DP(NETIF_MSG_LINK, "Approved module\n");
8215 /* Format the warning message */
8216 if (bnx2x_read_sfp_module_eeprom(phy,
8219 SFP_EEPROM_VENDOR_NAME_ADDR,
8220 SFP_EEPROM_VENDOR_NAME_SIZE,
8222 vendor_name[0] = '\0';
8224 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8225 if (bnx2x_read_sfp_module_eeprom(phy,
8228 SFP_EEPROM_PART_NO_ADDR,
8229 SFP_EEPROM_PART_NO_SIZE,
8231 vendor_pn[0] = '\0';
8233 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8235 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
8236 " Port %d from %s part number %s\n",
8237 params->port, vendor_name, vendor_pn);
8238 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8239 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8240 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8244 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8245 struct link_params *params)
8250 struct bnx2x *bp = params->bp;
8252 /* Initialization time after hot-plug may take up to 300ms for
8253 * some phys type ( e.g. JDSU )
8256 for (timeout = 0; timeout < 60; timeout++) {
8257 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8258 rc = bnx2x_warpcore_read_sfp_module_eeprom(
8259 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8262 rc = bnx2x_read_sfp_module_eeprom(phy, params,
8267 "SFP+ module initialization took %d ms\n",
8271 usleep_range(5000, 10000);
8273 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8278 static void bnx2x_8727_power_module(struct bnx2x *bp,
8279 struct bnx2x_phy *phy,
8281 /* Make sure GPIOs are not using for LED mode */
8283 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8284 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8286 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8287 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8288 * where the 1st bit is the over-current(only input), and 2nd bit is
8289 * for power( only output )
8291 * In case of NOC feature is disabled and power is up, set GPIO control
8292 * as input to enable listening of over-current indication
8294 if (phy->flags & FLAGS_NOC)
8299 /* Set GPIO control to OUTPUT, and set the power bit
8300 * to according to the is_power_up
8304 bnx2x_cl45_write(bp, phy,
8306 MDIO_PMA_REG_8727_GPIO_CTRL,
8310 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8311 struct bnx2x_phy *phy,
8314 u16 cur_limiting_mode;
8316 bnx2x_cl45_read(bp, phy,
8318 MDIO_PMA_REG_ROM_VER2,
8319 &cur_limiting_mode);
8320 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8323 if (edc_mode == EDC_MODE_LIMITING) {
8324 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8325 bnx2x_cl45_write(bp, phy,
8327 MDIO_PMA_REG_ROM_VER2,
8329 } else { /* LRM mode ( default )*/
8331 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8333 /* Changing to LRM mode takes quite few seconds. So do it only
8334 * if current mode is limiting (default is LRM)
8336 if (cur_limiting_mode != EDC_MODE_LIMITING)
8339 bnx2x_cl45_write(bp, phy,
8341 MDIO_PMA_REG_LRM_MODE,
8343 bnx2x_cl45_write(bp, phy,
8345 MDIO_PMA_REG_ROM_VER2,
8347 bnx2x_cl45_write(bp, phy,
8349 MDIO_PMA_REG_MISC_CTRL0,
8351 bnx2x_cl45_write(bp, phy,
8353 MDIO_PMA_REG_LRM_MODE,
8359 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8360 struct bnx2x_phy *phy,
8365 bnx2x_cl45_read(bp, phy,
8367 MDIO_PMA_REG_PHY_IDENTIFIER,
8370 bnx2x_cl45_write(bp, phy,
8372 MDIO_PMA_REG_PHY_IDENTIFIER,
8373 (phy_identifier & ~(1<<9)));
8375 bnx2x_cl45_read(bp, phy,
8377 MDIO_PMA_REG_ROM_VER2,
8379 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8380 bnx2x_cl45_write(bp, phy,
8382 MDIO_PMA_REG_ROM_VER2,
8383 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8385 bnx2x_cl45_write(bp, phy,
8387 MDIO_PMA_REG_PHY_IDENTIFIER,
8388 (phy_identifier | (1<<9)));
8393 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8394 struct link_params *params,
8397 struct bnx2x *bp = params->bp;
8401 bnx2x_sfp_set_transmitter(params, phy, 0);
8404 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8405 bnx2x_sfp_set_transmitter(params, phy, 1);
8408 bnx2x_cl45_write(bp, phy,
8409 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8411 bnx2x_cl45_write(bp, phy,
8412 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8414 bnx2x_cl45_write(bp, phy,
8415 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8416 /* Make MOD_ABS give interrupt on change */
8417 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8418 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8421 if (phy->flags & FLAGS_NOC)
8423 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8424 * status which reflect SFP+ module over-current
8426 if (!(phy->flags & FLAGS_NOC))
8427 val &= 0xff8f; /* Reset bits 4-6 */
8428 bnx2x_cl45_write(bp, phy,
8429 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8433 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8439 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8442 struct bnx2x *bp = params->bp;
8444 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8445 offsetof(struct shmem_region,
8446 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8447 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8448 switch (fault_led_gpio) {
8449 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8451 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8452 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8453 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8454 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8456 u8 gpio_port = bnx2x_get_gpio_port(params);
8457 u16 gpio_pin = fault_led_gpio -
8458 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8459 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8460 "pin %x port %x mode %x\n",
8461 gpio_pin, gpio_port, gpio_mode);
8462 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8466 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8471 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8475 u8 port = params->port;
8476 struct bnx2x *bp = params->bp;
8477 pin_cfg = (REG_RD(bp, params->shmem_base +
8478 offsetof(struct shmem_region,
8479 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8480 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8481 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8482 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8483 gpio_mode, pin_cfg);
8484 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8487 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8490 struct bnx2x *bp = params->bp;
8491 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8492 if (CHIP_IS_E3(bp)) {
8493 /* Low ==> if SFP+ module is supported otherwise
8494 * High ==> if SFP+ module is not on the approved vendor list
8496 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8498 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8501 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8502 struct link_params *params)
8504 struct bnx2x *bp = params->bp;
8505 bnx2x_warpcore_power_module(params, 0);
8506 /* Put Warpcore in low power mode */
8507 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8509 /* Put LCPLL in low power mode */
8510 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8511 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8512 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8515 static void bnx2x_power_sfp_module(struct link_params *params,
8516 struct bnx2x_phy *phy,
8519 struct bnx2x *bp = params->bp;
8520 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8522 switch (phy->type) {
8523 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8524 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8525 bnx2x_8727_power_module(params->bp, phy, power);
8527 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8528 bnx2x_warpcore_power_module(params, power);
8534 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8535 struct bnx2x_phy *phy,
8539 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8540 struct bnx2x *bp = params->bp;
8542 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8543 /* This is a global register which controls all lanes */
8544 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8545 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8546 val &= ~(0xf << (lane << 2));
8549 case EDC_MODE_LINEAR:
8550 case EDC_MODE_LIMITING:
8551 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8553 case EDC_MODE_PASSIVE_DAC:
8554 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8560 val |= (mode << (lane << 2));
8561 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8562 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8564 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8565 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8567 /* Restart microcode to re-read the new mode */
8568 bnx2x_warpcore_reset_lane(bp, phy, 1);
8569 bnx2x_warpcore_reset_lane(bp, phy, 0);
8573 static void bnx2x_set_limiting_mode(struct link_params *params,
8574 struct bnx2x_phy *phy,
8577 switch (phy->type) {
8578 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8579 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8581 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8582 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8583 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8585 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8586 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8591 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8592 struct link_params *params)
8594 struct bnx2x *bp = params->bp;
8598 u32 val = REG_RD(bp, params->shmem_base +
8599 offsetof(struct shmem_region, dev_info.
8600 port_feature_config[params->port].config));
8601 /* Enabled transmitter by default */
8602 bnx2x_sfp_set_transmitter(params, phy, 1);
8603 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8605 /* Power up module */
8606 bnx2x_power_sfp_module(params, phy, 1);
8607 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8608 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8610 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8611 /* Check SFP+ module compatibility */
8612 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8614 /* Turn on fault module-detected led */
8615 bnx2x_set_sfp_module_fault_led(params,
8616 MISC_REGISTERS_GPIO_HIGH);
8618 /* Check if need to power down the SFP+ module */
8619 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8620 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8621 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8622 bnx2x_power_sfp_module(params, phy, 0);
8626 /* Turn off fault module-detected led */
8627 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8630 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8631 * is done automatically
8633 bnx2x_set_limiting_mode(params, phy, edc_mode);
8635 /* Disable transmit for this module if the module is not approved, and
8636 * laser needs to be disabled.
8639 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8640 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8641 bnx2x_sfp_set_transmitter(params, phy, 0);
8646 void bnx2x_handle_module_detect_int(struct link_params *params)
8648 struct bnx2x *bp = params->bp;
8649 struct bnx2x_phy *phy;
8651 u8 gpio_num, gpio_port;
8652 if (CHIP_IS_E3(bp)) {
8653 phy = ¶ms->phy[INT_PHY];
8654 /* Always enable TX laser,will be disabled in case of fault */
8655 bnx2x_sfp_set_transmitter(params, phy, 1);
8657 phy = ¶ms->phy[EXT_PHY1];
8659 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8660 params->port, &gpio_num, &gpio_port) ==
8662 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8666 /* Set valid module led off */
8667 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8669 /* Get current gpio val reflecting module plugged in / out*/
8670 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8672 /* Call the handling function in case module is detected */
8673 if (gpio_val == 0) {
8674 bnx2x_set_mdio_emac_per_phy(bp, params);
8675 bnx2x_set_aer_mmd(params, phy);
8677 bnx2x_power_sfp_module(params, phy, 1);
8678 bnx2x_set_gpio_int(bp, gpio_num,
8679 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8681 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8682 bnx2x_sfp_module_detection(phy, params);
8683 if (CHIP_IS_E3(bp)) {
8685 /* In case WC is out of reset, reconfigure the
8686 * link speed while taking into account 1G
8687 * module limitation.
8689 bnx2x_cl45_read(bp, phy,
8691 MDIO_WC_REG_DIGITAL5_MISC6,
8693 if ((!rx_tx_in_reset) &&
8694 (params->link_flags &
8696 bnx2x_warpcore_reset_lane(bp, phy, 1);
8697 bnx2x_warpcore_config_sfi(phy, params);
8698 bnx2x_warpcore_reset_lane(bp, phy, 0);
8702 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8705 bnx2x_set_gpio_int(bp, gpio_num,
8706 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8708 /* Module was plugged out.
8709 * Disable transmit for this module
8711 phy->media_type = ETH_PHY_NOT_PRESENT;
8715 /******************************************************************/
8716 /* Used by 8706 and 8727 */
8717 /******************************************************************/
8718 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8719 struct bnx2x_phy *phy,
8720 u16 alarm_status_offset,
8721 u16 alarm_ctrl_offset)
8723 u16 alarm_status, val;
8724 bnx2x_cl45_read(bp, phy,
8725 MDIO_PMA_DEVAD, alarm_status_offset,
8727 bnx2x_cl45_read(bp, phy,
8728 MDIO_PMA_DEVAD, alarm_status_offset,
8730 /* Mask or enable the fault event. */
8731 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8732 if (alarm_status & (1<<0))
8736 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8738 /******************************************************************/
8739 /* common BCM8706/BCM8726 PHY SECTION */
8740 /******************************************************************/
8741 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8742 struct link_params *params,
8743 struct link_vars *vars)
8746 u16 val1, val2, rx_sd, pcs_status;
8747 struct bnx2x *bp = params->bp;
8748 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8750 bnx2x_cl45_read(bp, phy,
8751 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8753 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8754 MDIO_PMA_LASI_TXCTRL);
8756 /* Clear LASI indication*/
8757 bnx2x_cl45_read(bp, phy,
8758 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8759 bnx2x_cl45_read(bp, phy,
8760 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8761 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8763 bnx2x_cl45_read(bp, phy,
8764 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8765 bnx2x_cl45_read(bp, phy,
8766 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8767 bnx2x_cl45_read(bp, phy,
8768 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8769 bnx2x_cl45_read(bp, phy,
8770 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8772 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8773 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8774 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8775 * are set, or if the autoneg bit 1 is set
8777 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8780 vars->line_speed = SPEED_1000;
8782 vars->line_speed = SPEED_10000;
8783 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8784 vars->duplex = DUPLEX_FULL;
8787 /* Capture 10G link fault. Read twice to clear stale value. */
8788 if (vars->line_speed == SPEED_10000) {
8789 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8790 MDIO_PMA_LASI_TXSTAT, &val1);
8791 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8792 MDIO_PMA_LASI_TXSTAT, &val1);
8794 vars->fault_detected = 1;
8800 /******************************************************************/
8801 /* BCM8706 PHY SECTION */
8802 /******************************************************************/
8803 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8804 struct link_params *params,
8805 struct link_vars *vars)
8809 struct bnx2x *bp = params->bp;
8811 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8812 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8814 bnx2x_ext_phy_hw_reset(bp, params->port);
8815 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8816 bnx2x_wait_reset_complete(bp, phy, params);
8818 /* Wait until fw is loaded */
8819 for (cnt = 0; cnt < 100; cnt++) {
8820 bnx2x_cl45_read(bp, phy,
8821 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8824 usleep_range(10000, 20000);
8826 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8827 if ((params->feature_config_flags &
8828 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8831 for (i = 0; i < 4; i++) {
8832 reg = MDIO_XS_8706_REG_BANK_RX0 +
8833 i*(MDIO_XS_8706_REG_BANK_RX1 -
8834 MDIO_XS_8706_REG_BANK_RX0);
8835 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8836 /* Clear first 3 bits of the control */
8838 /* Set control bits according to configuration */
8839 val |= (phy->rx_preemphasis[i] & 0x7);
8840 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8841 " reg 0x%x <-- val 0x%x\n", reg, val);
8842 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8846 if (phy->req_line_speed == SPEED_10000) {
8847 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8849 bnx2x_cl45_write(bp, phy,
8851 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8852 bnx2x_cl45_write(bp, phy,
8853 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8855 /* Arm LASI for link and Tx fault. */
8856 bnx2x_cl45_write(bp, phy,
8857 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8859 /* Force 1Gbps using autoneg with 1G advertisement */
8861 /* Allow CL37 through CL73 */
8862 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8863 bnx2x_cl45_write(bp, phy,
8864 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8866 /* Enable Full-Duplex advertisement on CL37 */
8867 bnx2x_cl45_write(bp, phy,
8868 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8869 /* Enable CL37 AN */
8870 bnx2x_cl45_write(bp, phy,
8871 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8873 bnx2x_cl45_write(bp, phy,
8874 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8876 /* Enable clause 73 AN */
8877 bnx2x_cl45_write(bp, phy,
8878 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8879 bnx2x_cl45_write(bp, phy,
8880 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8882 bnx2x_cl45_write(bp, phy,
8883 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8886 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8888 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8889 * power mode, if TX Laser is disabled
8892 tx_en_mode = REG_RD(bp, params->shmem_base +
8893 offsetof(struct shmem_region,
8894 dev_info.port_hw_config[params->port].sfp_ctrl))
8895 & PORT_HW_CFG_TX_LASER_MASK;
8897 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8898 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8899 bnx2x_cl45_read(bp, phy,
8900 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8902 bnx2x_cl45_write(bp, phy,
8903 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8909 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8910 struct link_params *params,
8911 struct link_vars *vars)
8913 return bnx2x_8706_8726_read_status(phy, params, vars);
8916 /******************************************************************/
8917 /* BCM8726 PHY SECTION */
8918 /******************************************************************/
8919 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8920 struct link_params *params)
8922 struct bnx2x *bp = params->bp;
8923 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8924 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8927 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8928 struct link_params *params)
8930 struct bnx2x *bp = params->bp;
8931 /* Need to wait 100ms after reset */
8934 /* Micro controller re-boot */
8935 bnx2x_cl45_write(bp, phy,
8936 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8938 /* Set soft reset */
8939 bnx2x_cl45_write(bp, phy,
8941 MDIO_PMA_REG_GEN_CTRL,
8942 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8944 bnx2x_cl45_write(bp, phy,
8946 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8948 bnx2x_cl45_write(bp, phy,
8950 MDIO_PMA_REG_GEN_CTRL,
8951 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8953 /* Wait for 150ms for microcode load */
8956 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8957 bnx2x_cl45_write(bp, phy,
8959 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8962 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8965 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8966 struct link_params *params,
8967 struct link_vars *vars)
8969 struct bnx2x *bp = params->bp;
8971 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8973 bnx2x_cl45_read(bp, phy,
8974 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8976 if (val1 & (1<<15)) {
8977 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8979 vars->line_speed = 0;
8986 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8987 struct link_params *params,
8988 struct link_vars *vars)
8990 struct bnx2x *bp = params->bp;
8991 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8993 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8994 bnx2x_wait_reset_complete(bp, phy, params);
8996 bnx2x_8726_external_rom_boot(phy, params);
8998 /* Need to call module detected on initialization since the module
8999 * detection triggered by actual module insertion might occur before
9000 * driver is loaded, and when driver is loaded, it reset all
9001 * registers, including the transmitter
9003 bnx2x_sfp_module_detection(phy, params);
9005 if (phy->req_line_speed == SPEED_1000) {
9006 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9007 bnx2x_cl45_write(bp, phy,
9008 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9009 bnx2x_cl45_write(bp, phy,
9010 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9011 bnx2x_cl45_write(bp, phy,
9012 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9013 bnx2x_cl45_write(bp, phy,
9014 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9016 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9017 (phy->speed_cap_mask &
9018 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9019 ((phy->speed_cap_mask &
9020 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9021 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9022 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9023 /* Set Flow control */
9024 bnx2x_ext_phy_set_pause(params, phy, vars);
9025 bnx2x_cl45_write(bp, phy,
9026 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9027 bnx2x_cl45_write(bp, phy,
9028 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9029 bnx2x_cl45_write(bp, phy,
9030 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9031 bnx2x_cl45_write(bp, phy,
9032 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9033 bnx2x_cl45_write(bp, phy,
9034 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9035 /* Enable RX-ALARM control to receive interrupt for 1G speed
9038 bnx2x_cl45_write(bp, phy,
9039 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9040 bnx2x_cl45_write(bp, phy,
9041 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9044 } else { /* Default 10G. Set only LASI control */
9045 bnx2x_cl45_write(bp, phy,
9046 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9049 /* Set TX PreEmphasis if needed */
9050 if ((params->feature_config_flags &
9051 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9053 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9054 phy->tx_preemphasis[0],
9055 phy->tx_preemphasis[1]);
9056 bnx2x_cl45_write(bp, phy,
9058 MDIO_PMA_REG_8726_TX_CTRL1,
9059 phy->tx_preemphasis[0]);
9061 bnx2x_cl45_write(bp, phy,
9063 MDIO_PMA_REG_8726_TX_CTRL2,
9064 phy->tx_preemphasis[1]);
9071 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9072 struct link_params *params)
9074 struct bnx2x *bp = params->bp;
9075 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9076 /* Set serial boot control for external load */
9077 bnx2x_cl45_write(bp, phy,
9079 MDIO_PMA_REG_GEN_CTRL, 0x0001);
9082 /******************************************************************/
9083 /* BCM8727 PHY SECTION */
9084 /******************************************************************/
9086 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9087 struct link_params *params, u8 mode)
9089 struct bnx2x *bp = params->bp;
9090 u16 led_mode_bitmask = 0;
9091 u16 gpio_pins_bitmask = 0;
9093 /* Only NOC flavor requires to set the LED specifically */
9094 if (!(phy->flags & FLAGS_NOC))
9097 case LED_MODE_FRONT_PANEL_OFF:
9099 led_mode_bitmask = 0;
9100 gpio_pins_bitmask = 0x03;
9103 led_mode_bitmask = 0;
9104 gpio_pins_bitmask = 0x02;
9107 led_mode_bitmask = 0x60;
9108 gpio_pins_bitmask = 0x11;
9111 bnx2x_cl45_read(bp, phy,
9113 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9116 val |= led_mode_bitmask;
9117 bnx2x_cl45_write(bp, phy,
9119 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9121 bnx2x_cl45_read(bp, phy,
9123 MDIO_PMA_REG_8727_GPIO_CTRL,
9126 val |= gpio_pins_bitmask;
9127 bnx2x_cl45_write(bp, phy,
9129 MDIO_PMA_REG_8727_GPIO_CTRL,
9132 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9133 struct link_params *params) {
9134 u32 swap_val, swap_override;
9136 /* The PHY reset is controlled by GPIO 1. Fake the port number
9137 * to cancel the swap done in set_gpio()
9139 struct bnx2x *bp = params->bp;
9140 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9141 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9142 port = (swap_val && swap_override) ^ 1;
9143 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9144 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9147 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9148 struct link_params *params)
9150 struct bnx2x *bp = params->bp;
9152 /* Set option 1G speed */
9153 if ((phy->req_line_speed == SPEED_1000) ||
9154 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9155 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9156 bnx2x_cl45_write(bp, phy,
9157 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9158 bnx2x_cl45_write(bp, phy,
9159 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9160 bnx2x_cl45_read(bp, phy,
9161 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9162 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9163 /* Power down the XAUI until link is up in case of dual-media
9166 if (DUAL_MEDIA(params)) {
9167 bnx2x_cl45_read(bp, phy,
9169 MDIO_PMA_REG_8727_PCS_GP, &val);
9171 bnx2x_cl45_write(bp, phy,
9173 MDIO_PMA_REG_8727_PCS_GP, val);
9175 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9176 ((phy->speed_cap_mask &
9177 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9178 ((phy->speed_cap_mask &
9179 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9180 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9182 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9183 bnx2x_cl45_write(bp, phy,
9184 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9185 bnx2x_cl45_write(bp, phy,
9186 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9188 /* Since the 8727 has only single reset pin, need to set the 10G
9189 * registers although it is default
9191 bnx2x_cl45_write(bp, phy,
9192 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9194 bnx2x_cl45_write(bp, phy,
9195 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9196 bnx2x_cl45_write(bp, phy,
9197 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9198 bnx2x_cl45_write(bp, phy,
9199 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9204 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9205 struct link_params *params,
9206 struct link_vars *vars)
9209 u16 tmp1, mod_abs, tmp2;
9210 struct bnx2x *bp = params->bp;
9211 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9213 bnx2x_wait_reset_complete(bp, phy, params);
9215 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9217 bnx2x_8727_specific_func(phy, params, PHY_INIT);
9218 /* Initially configure MOD_ABS to interrupt when module is
9221 bnx2x_cl45_read(bp, phy,
9222 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9223 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9224 * When the EDC is off it locks onto a reference clock and avoids
9228 if (!(phy->flags & FLAGS_NOC))
9230 bnx2x_cl45_write(bp, phy,
9231 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9233 /* Enable/Disable PHY transmitter output */
9234 bnx2x_set_disable_pmd_transmit(params, phy, 0);
9236 bnx2x_8727_power_module(bp, phy, 1);
9238 bnx2x_cl45_read(bp, phy,
9239 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9241 bnx2x_cl45_read(bp, phy,
9242 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9244 bnx2x_8727_config_speed(phy, params);
9247 /* Set TX PreEmphasis if needed */
9248 if ((params->feature_config_flags &
9249 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9250 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9251 phy->tx_preemphasis[0],
9252 phy->tx_preemphasis[1]);
9253 bnx2x_cl45_write(bp, phy,
9254 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9255 phy->tx_preemphasis[0]);
9257 bnx2x_cl45_write(bp, phy,
9258 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9259 phy->tx_preemphasis[1]);
9262 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9263 * power mode, if TX Laser is disabled
9265 tx_en_mode = REG_RD(bp, params->shmem_base +
9266 offsetof(struct shmem_region,
9267 dev_info.port_hw_config[params->port].sfp_ctrl))
9268 & PORT_HW_CFG_TX_LASER_MASK;
9270 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9272 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9273 bnx2x_cl45_read(bp, phy,
9274 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9277 bnx2x_cl45_write(bp, phy,
9278 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9279 bnx2x_cl45_read(bp, phy,
9280 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9282 bnx2x_cl45_write(bp, phy,
9283 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9290 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9291 struct link_params *params)
9293 struct bnx2x *bp = params->bp;
9294 u16 mod_abs, rx_alarm_status;
9295 u32 val = REG_RD(bp, params->shmem_base +
9296 offsetof(struct shmem_region, dev_info.
9297 port_feature_config[params->port].
9299 bnx2x_cl45_read(bp, phy,
9301 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9302 if (mod_abs & (1<<8)) {
9304 /* Module is absent */
9306 "MOD_ABS indication show module is absent\n");
9307 phy->media_type = ETH_PHY_NOT_PRESENT;
9308 /* 1. Set mod_abs to detect next module
9310 * 2. Set EDC off by setting OPTXLOS signal input to low
9312 * When the EDC is off it locks onto a reference clock and
9313 * avoids becoming 'lost'.
9316 if (!(phy->flags & FLAGS_NOC))
9318 bnx2x_cl45_write(bp, phy,
9320 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9322 /* Clear RX alarm since it stays up as long as
9323 * the mod_abs wasn't changed
9325 bnx2x_cl45_read(bp, phy,
9327 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9330 /* Module is present */
9332 "MOD_ABS indication show module is present\n");
9333 /* First disable transmitter, and if the module is ok, the
9334 * module_detection will enable it
9335 * 1. Set mod_abs to detect next module absent event ( bit 8)
9336 * 2. Restore the default polarity of the OPRXLOS signal and
9337 * this signal will then correctly indicate the presence or
9338 * absence of the Rx signal. (bit 9)
9341 if (!(phy->flags & FLAGS_NOC))
9343 bnx2x_cl45_write(bp, phy,
9345 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9347 /* Clear RX alarm since it stays up as long as the mod_abs
9348 * wasn't changed. This is need to be done before calling the
9349 * module detection, otherwise it will clear* the link update
9352 bnx2x_cl45_read(bp, phy,
9354 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9357 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9358 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9359 bnx2x_sfp_set_transmitter(params, phy, 0);
9361 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9362 bnx2x_sfp_module_detection(phy, params);
9364 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9366 /* Reconfigure link speed based on module type limitations */
9367 bnx2x_8727_config_speed(phy, params);
9370 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9372 /* No need to check link status in case of module plugged in/out */
9375 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9376 struct link_params *params,
9377 struct link_vars *vars)
9380 struct bnx2x *bp = params->bp;
9381 u8 link_up = 0, oc_port = params->port;
9382 u16 link_status = 0;
9383 u16 rx_alarm_status, lasi_ctrl, val1;
9385 /* If PHY is not initialized, do not check link status */
9386 bnx2x_cl45_read(bp, phy,
9387 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9392 /* Check the LASI on Rx */
9393 bnx2x_cl45_read(bp, phy,
9394 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9396 vars->line_speed = 0;
9397 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
9399 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9400 MDIO_PMA_LASI_TXCTRL);
9402 bnx2x_cl45_read(bp, phy,
9403 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9405 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9408 bnx2x_cl45_read(bp, phy,
9409 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9411 /* If a module is present and there is need to check
9414 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9415 /* Check over-current using 8727 GPIO0 input*/
9416 bnx2x_cl45_read(bp, phy,
9417 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9420 if ((val1 & (1<<8)) == 0) {
9421 if (!CHIP_IS_E1x(bp))
9422 oc_port = BP_PATH(bp) + (params->port << 1);
9424 "8727 Power fault has been detected on port %d\n",
9426 netdev_err(bp->dev, "Error: Power fault on Port %d has "
9427 "been detected and the power to "
9428 "that SFP+ module has been removed "
9429 "to prevent failure of the card. "
9430 "Please remove the SFP+ module and "
9431 "restart the system to clear this "
9434 /* Disable all RX_ALARMs except for mod_abs */
9435 bnx2x_cl45_write(bp, phy,
9437 MDIO_PMA_LASI_RXCTRL, (1<<5));
9439 bnx2x_cl45_read(bp, phy,
9441 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9442 /* Wait for module_absent_event */
9444 bnx2x_cl45_write(bp, phy,
9446 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9447 /* Clear RX alarm */
9448 bnx2x_cl45_read(bp, phy,
9450 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9451 bnx2x_8727_power_module(params->bp, phy, 0);
9454 } /* Over current check */
9456 /* When module absent bit is set, check module */
9457 if (rx_alarm_status & (1<<5)) {
9458 bnx2x_8727_handle_mod_abs(phy, params);
9459 /* Enable all mod_abs and link detection bits */
9460 bnx2x_cl45_write(bp, phy,
9461 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9465 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9466 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9467 bnx2x_sfp_set_transmitter(params, phy, 1);
9469 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9473 bnx2x_cl45_read(bp, phy,
9475 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9477 /* Bits 0..2 --> speed detected,
9478 * Bits 13..15--> link is down
9480 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9482 vars->line_speed = SPEED_10000;
9483 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9485 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9487 vars->line_speed = SPEED_1000;
9488 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9492 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9496 /* Capture 10G link fault. */
9497 if (vars->line_speed == SPEED_10000) {
9498 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9499 MDIO_PMA_LASI_TXSTAT, &val1);
9501 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9502 MDIO_PMA_LASI_TXSTAT, &val1);
9504 if (val1 & (1<<0)) {
9505 vars->fault_detected = 1;
9510 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9511 vars->duplex = DUPLEX_FULL;
9512 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9515 if ((DUAL_MEDIA(params)) &&
9516 (phy->req_line_speed == SPEED_1000)) {
9517 bnx2x_cl45_read(bp, phy,
9519 MDIO_PMA_REG_8727_PCS_GP, &val1);
9520 /* In case of dual-media board and 1G, power up the XAUI side,
9521 * otherwise power it down. For 10G it is done automatically
9527 bnx2x_cl45_write(bp, phy,
9529 MDIO_PMA_REG_8727_PCS_GP, val1);
9534 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9535 struct link_params *params)
9537 struct bnx2x *bp = params->bp;
9539 /* Enable/Disable PHY transmitter output */
9540 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9542 /* Disable Transmitter */
9543 bnx2x_sfp_set_transmitter(params, phy, 0);
9545 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9549 /******************************************************************/
9550 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9551 /******************************************************************/
9552 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9556 u16 val, fw_ver2, cnt, i;
9557 static struct bnx2x_reg_set reg_set[] = {
9558 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9559 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9560 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9561 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9562 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9566 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9567 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9568 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9569 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9572 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9573 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9574 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9575 bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9576 reg_set[i].reg, reg_set[i].val);
9578 for (cnt = 0; cnt < 100; cnt++) {
9579 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9585 DP(NETIF_MSG_LINK, "Unable to read 848xx "
9586 "phy fw version(1)\n");
9587 bnx2x_save_spirom_version(bp, port, 0,
9593 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9594 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9595 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9596 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9597 for (cnt = 0; cnt < 100; cnt++) {
9598 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9604 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9606 bnx2x_save_spirom_version(bp, port, 0,
9611 /* lower 16 bits of the register SPI_FW_STATUS */
9612 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9613 /* upper 16 bits of register SPI_FW_STATUS */
9614 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9616 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9621 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9622 struct bnx2x_phy *phy)
9625 static struct bnx2x_reg_set reg_set[] = {
9626 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9627 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9628 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9629 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9630 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9631 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9632 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9634 /* PHYC_CTL_LED_CTL */
9635 bnx2x_cl45_read(bp, phy,
9637 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9641 bnx2x_cl45_write(bp, phy,
9643 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9645 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9646 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9649 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9650 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
9651 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9653 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9655 /* stretch_en for LED3*/
9656 bnx2x_cl45_read_or_write(bp, phy,
9657 MDIO_PMA_DEVAD, offset,
9658 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9661 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9662 struct link_params *params,
9665 struct bnx2x *bp = params->bp;
9668 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9669 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9670 /* Save spirom version */
9671 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9673 /* This phy uses the NIG latch mechanism since link indication
9674 * arrives through its LED4 and not via its LASI signal, so we
9675 * get steady signal instead of clear on read
9677 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9678 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9680 bnx2x_848xx_set_led(bp, phy);
9685 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9686 struct link_params *params,
9687 struct link_vars *vars)
9689 struct bnx2x *bp = params->bp;
9690 u16 autoneg_val, an_1000_val, an_10_100_val;
9692 bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9693 bnx2x_cl45_write(bp, phy,
9694 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9696 /* set 1000 speed advertisement */
9697 bnx2x_cl45_read(bp, phy,
9698 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9701 bnx2x_ext_phy_set_pause(params, phy, vars);
9702 bnx2x_cl45_read(bp, phy,
9704 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9706 bnx2x_cl45_read(bp, phy,
9707 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9709 /* Disable forced speed */
9710 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9711 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9713 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9714 (phy->speed_cap_mask &
9715 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9716 (phy->req_line_speed == SPEED_1000)) {
9717 an_1000_val |= (1<<8);
9718 autoneg_val |= (1<<9 | 1<<12);
9719 if (phy->req_duplex == DUPLEX_FULL)
9720 an_1000_val |= (1<<9);
9721 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9723 an_1000_val &= ~((1<<8) | (1<<9));
9725 bnx2x_cl45_write(bp, phy,
9726 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9729 /* set 100 speed advertisement */
9730 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9731 (phy->speed_cap_mask &
9732 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9733 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9734 an_10_100_val |= (1<<7);
9735 /* Enable autoneg and restart autoneg for legacy speeds */
9736 autoneg_val |= (1<<9 | 1<<12);
9738 if (phy->req_duplex == DUPLEX_FULL)
9739 an_10_100_val |= (1<<8);
9740 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9742 /* set 10 speed advertisement */
9743 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9744 (phy->speed_cap_mask &
9745 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9746 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9748 (SUPPORTED_10baseT_Half |
9749 SUPPORTED_10baseT_Full)))) {
9750 an_10_100_val |= (1<<5);
9751 autoneg_val |= (1<<9 | 1<<12);
9752 if (phy->req_duplex == DUPLEX_FULL)
9753 an_10_100_val |= (1<<6);
9754 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9757 /* Only 10/100 are allowed to work in FORCE mode */
9758 if ((phy->req_line_speed == SPEED_100) &&
9760 (SUPPORTED_100baseT_Half |
9761 SUPPORTED_100baseT_Full))) {
9762 autoneg_val |= (1<<13);
9763 /* Enabled AUTO-MDIX when autoneg is disabled */
9764 bnx2x_cl45_write(bp, phy,
9765 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9766 (1<<15 | 1<<9 | 7<<0));
9767 /* The PHY needs this set even for forced link. */
9768 an_10_100_val |= (1<<8) | (1<<7);
9769 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9771 if ((phy->req_line_speed == SPEED_10) &&
9773 (SUPPORTED_10baseT_Half |
9774 SUPPORTED_10baseT_Full))) {
9775 /* Enabled AUTO-MDIX when autoneg is disabled */
9776 bnx2x_cl45_write(bp, phy,
9777 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9778 (1<<15 | 1<<9 | 7<<0));
9779 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9782 bnx2x_cl45_write(bp, phy,
9783 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9786 if (phy->req_duplex == DUPLEX_FULL)
9787 autoneg_val |= (1<<8);
9789 /* Always write this if this is not 84833/4.
9790 * For 84833/4, write it only when it's a forced speed.
9792 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9793 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
9794 ((autoneg_val & (1<<12)) == 0))
9795 bnx2x_cl45_write(bp, phy,
9797 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9799 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9800 (phy->speed_cap_mask &
9801 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9802 (phy->req_line_speed == SPEED_10000)) {
9803 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9804 /* Restart autoneg for 10G*/
9806 bnx2x_cl45_read_or_write(
9809 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9811 bnx2x_cl45_write(bp, phy,
9812 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9815 bnx2x_cl45_write(bp, phy,
9817 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9823 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9824 struct link_params *params,
9825 struct link_vars *vars)
9827 struct bnx2x *bp = params->bp;
9828 /* Restore normal power mode*/
9829 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9830 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9833 bnx2x_ext_phy_hw_reset(bp, params->port);
9834 bnx2x_wait_reset_complete(bp, phy, params);
9836 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9837 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9840 #define PHY84833_CMDHDLR_WAIT 300
9841 #define PHY84833_CMDHDLR_MAX_ARGS 5
9842 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9843 struct link_params *params, u16 fw_cmd,
9844 u16 cmd_args[], int argc)
9848 struct bnx2x *bp = params->bp;
9849 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9850 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9851 MDIO_84833_CMD_HDLR_STATUS,
9852 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9853 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9854 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9855 MDIO_84833_CMD_HDLR_STATUS, &val);
9856 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9858 usleep_range(1000, 2000);
9860 if (idx >= PHY84833_CMDHDLR_WAIT) {
9861 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9865 /* Prepare argument(s) and issue command */
9866 for (idx = 0; idx < argc; idx++) {
9867 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9868 MDIO_84833_CMD_HDLR_DATA1 + idx,
9871 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9872 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9873 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9874 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9875 MDIO_84833_CMD_HDLR_STATUS, &val);
9876 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9877 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9879 usleep_range(1000, 2000);
9881 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9882 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9883 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9886 /* Gather returning data */
9887 for (idx = 0; idx < argc; idx++) {
9888 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9889 MDIO_84833_CMD_HDLR_DATA1 + idx,
9892 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9893 MDIO_84833_CMD_HDLR_STATUS,
9894 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9898 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9899 struct link_params *params,
9900 struct link_vars *vars)
9903 u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9905 struct bnx2x *bp = params->bp;
9907 /* Check for configuration. */
9908 pair_swap = REG_RD(bp, params->shmem_base +
9909 offsetof(struct shmem_region,
9910 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9911 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9916 /* Only the second argument is used for this command */
9917 data[1] = (u16)pair_swap;
9919 status = bnx2x_84833_cmd_hdlr(phy, params,
9920 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9922 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9927 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9928 u32 shmem_base_path[],
9934 if (CHIP_IS_E3(bp)) {
9935 /* Assume that these will be GPIOs, not EPIOs. */
9936 for (idx = 0; idx < 2; idx++) {
9937 /* Map config param to register bit. */
9938 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9939 offsetof(struct shmem_region,
9940 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9941 reset_pin[idx] = (reset_pin[idx] &
9942 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9943 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9944 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9945 reset_pin[idx] = (1 << reset_pin[idx]);
9947 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9949 /* E2, look from diff place of shmem. */
9950 for (idx = 0; idx < 2; idx++) {
9951 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9952 offsetof(struct shmem_region,
9953 dev_info.port_hw_config[0].default_cfg));
9954 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9955 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9956 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9957 reset_pin[idx] = (1 << reset_pin[idx]);
9959 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9965 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9966 struct link_params *params)
9968 struct bnx2x *bp = params->bp;
9970 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9971 offsetof(struct shmem2_region,
9972 other_shmem_base_addr));
9974 u32 shmem_base_path[2];
9976 /* Work around for 84833 LED failure inside RESET status */
9977 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9978 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9979 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9980 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9981 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9982 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9984 shmem_base_path[0] = params->shmem_base;
9985 shmem_base_path[1] = other_shmem_base_addr;
9987 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9990 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9992 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9998 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
9999 struct link_params *params,
10000 struct link_vars *vars)
10003 struct bnx2x *bp = params->bp;
10006 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10008 /* Prevent Phy from working in EEE and advertising it */
10009 rc = bnx2x_84833_cmd_hdlr(phy, params,
10010 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10012 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10016 return bnx2x_eee_disable(phy, params, vars);
10019 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10020 struct link_params *params,
10021 struct link_vars *vars)
10024 struct bnx2x *bp = params->bp;
10027 rc = bnx2x_84833_cmd_hdlr(phy, params,
10028 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10030 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10034 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10037 #define PHY84833_CONSTANT_LATENCY 1193
10038 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10039 struct link_params *params,
10040 struct link_vars *vars)
10042 struct bnx2x *bp = params->bp;
10043 u8 port, initialize = 1;
10045 u32 actual_phy_selection;
10046 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10049 usleep_range(1000, 2000);
10051 if (!(CHIP_IS_E1x(bp)))
10052 port = BP_PATH(bp);
10054 port = params->port;
10056 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10057 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10058 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10062 bnx2x_cl45_write(bp, phy,
10064 MDIO_PMA_REG_CTRL, 0x8000);
10067 bnx2x_wait_reset_complete(bp, phy, params);
10069 /* Wait for GPHY to come out of reset */
10071 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10072 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10073 /* BCM84823 requires that XGXS links up first @ 10G for normal
10077 temp = vars->line_speed;
10078 vars->line_speed = SPEED_10000;
10079 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0);
10080 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
10081 vars->line_speed = temp;
10084 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10085 MDIO_CTL_REG_84823_MEDIA, &val);
10086 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10087 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10088 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10089 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10090 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10092 if (CHIP_IS_E3(bp)) {
10093 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10094 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10096 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10097 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10100 actual_phy_selection = bnx2x_phy_selection(params);
10102 switch (actual_phy_selection) {
10103 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10104 /* Do nothing. Essentially this is like the priority copper */
10106 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10107 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10109 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10110 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10112 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10113 /* Do nothing here. The first PHY won't be initialized at all */
10115 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10116 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10120 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10121 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10123 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10124 MDIO_CTL_REG_84823_MEDIA, val);
10125 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10126 params->multi_phy_config, val);
10128 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10129 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10130 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10132 /* Keep AutogrEEEn disabled. */
10135 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10136 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10137 rc = bnx2x_84833_cmd_hdlr(phy, params,
10138 PHY84833_CMD_SET_EEE_MODE, cmd_args,
10139 PHY84833_CMDHDLR_MAX_ARGS);
10141 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10144 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10146 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10147 /* 84833 PHY has a better feature and doesn't need to support this. */
10148 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10149 u32 cms_enable = REG_RD(bp, params->shmem_base +
10150 offsetof(struct shmem_region,
10151 dev_info.port_hw_config[params->port].default_cfg)) &
10152 PORT_HW_CFG_ENABLE_CMS_MASK;
10154 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10155 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10157 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10159 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10160 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10161 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10164 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10165 MDIO_84833_TOP_CFG_FW_REV, &val);
10167 /* Configure EEE support */
10168 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10169 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10170 bnx2x_eee_has_cap(params)) {
10171 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10173 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10174 bnx2x_8483x_disable_eee(phy, params, vars);
10178 if ((phy->req_duplex == DUPLEX_FULL) &&
10179 (params->eee_mode & EEE_MODE_ADV_LPI) &&
10180 (bnx2x_eee_calc_timer(params) ||
10181 !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10182 rc = bnx2x_8483x_enable_eee(phy, params, vars);
10184 rc = bnx2x_8483x_disable_eee(phy, params, vars);
10186 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10190 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10193 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10194 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10195 /* Bring PHY out of super isolate mode as the final step. */
10196 bnx2x_cl45_read_and_write(bp, phy,
10198 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10199 (u16)~MDIO_84833_SUPER_ISOLATE);
10204 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10205 struct link_params *params,
10206 struct link_vars *vars)
10208 struct bnx2x *bp = params->bp;
10209 u16 val, val1, val2;
10213 /* Check 10G-BaseT link status */
10214 /* Check PMD signal ok */
10215 bnx2x_cl45_read(bp, phy,
10216 MDIO_AN_DEVAD, 0xFFFA, &val1);
10217 bnx2x_cl45_read(bp, phy,
10218 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10220 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10222 /* Check link 10G */
10223 if (val2 & (1<<11)) {
10224 vars->line_speed = SPEED_10000;
10225 vars->duplex = DUPLEX_FULL;
10227 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10228 } else { /* Check Legacy speed link */
10229 u16 legacy_status, legacy_speed;
10231 /* Enable expansion register 0x42 (Operation mode status) */
10232 bnx2x_cl45_write(bp, phy,
10234 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10236 /* Get legacy speed operation status */
10237 bnx2x_cl45_read(bp, phy,
10239 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10242 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10244 link_up = ((legacy_status & (1<<11)) == (1<<11));
10245 legacy_speed = (legacy_status & (3<<9));
10246 if (legacy_speed == (0<<9))
10247 vars->line_speed = SPEED_10;
10248 else if (legacy_speed == (1<<9))
10249 vars->line_speed = SPEED_100;
10250 else if (legacy_speed == (2<<9))
10251 vars->line_speed = SPEED_1000;
10252 else { /* Should not happen: Treat as link down */
10253 vars->line_speed = 0;
10258 if (legacy_status & (1<<8))
10259 vars->duplex = DUPLEX_FULL;
10261 vars->duplex = DUPLEX_HALF;
10264 "Link is up in %dMbps, is_duplex_full= %d\n",
10266 (vars->duplex == DUPLEX_FULL));
10267 /* Check legacy speed AN resolution */
10268 bnx2x_cl45_read(bp, phy,
10270 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10273 vars->link_status |=
10274 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10275 bnx2x_cl45_read(bp, phy,
10277 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10279 if ((val & (1<<0)) == 0)
10280 vars->link_status |=
10281 LINK_STATUS_PARALLEL_DETECTION_USED;
10285 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10287 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10289 /* Read LP advertised speeds */
10290 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10291 MDIO_AN_REG_CL37_FC_LP, &val);
10293 vars->link_status |=
10294 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10296 vars->link_status |=
10297 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10299 vars->link_status |=
10300 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10302 vars->link_status |=
10303 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10305 vars->link_status |=
10306 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10308 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10309 MDIO_AN_REG_1000T_STATUS, &val);
10312 vars->link_status |=
10313 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10315 vars->link_status |=
10316 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10318 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10319 MDIO_AN_REG_MASTER_STATUS, &val);
10322 vars->link_status |=
10323 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10325 /* Determine if EEE was negotiated */
10326 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10327 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10328 bnx2x_eee_an_resolve(phy, params, vars);
10334 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10338 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10339 status = bnx2x_format_ver(spirom_ver, str, len);
10343 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10344 struct link_params *params)
10346 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10347 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10348 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10349 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10352 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10353 struct link_params *params)
10355 bnx2x_cl45_write(params->bp, phy,
10356 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10357 bnx2x_cl45_write(params->bp, phy,
10358 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10361 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10362 struct link_params *params)
10364 struct bnx2x *bp = params->bp;
10368 if (!(CHIP_IS_E1x(bp)))
10369 port = BP_PATH(bp);
10371 port = params->port;
10373 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10374 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10375 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10378 bnx2x_cl45_read(bp, phy,
10380 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10381 val16 |= MDIO_84833_SUPER_ISOLATE;
10382 bnx2x_cl45_write(bp, phy,
10384 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10388 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10389 struct link_params *params, u8 mode)
10391 struct bnx2x *bp = params->bp;
10395 if (!(CHIP_IS_E1x(bp)))
10396 port = BP_PATH(bp);
10398 port = params->port;
10403 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10405 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10406 SHARED_HW_CFG_LED_EXTPHY1) {
10408 /* Set LED masks */
10409 bnx2x_cl45_write(bp, phy,
10411 MDIO_PMA_REG_8481_LED1_MASK,
10414 bnx2x_cl45_write(bp, phy,
10416 MDIO_PMA_REG_8481_LED2_MASK,
10419 bnx2x_cl45_write(bp, phy,
10421 MDIO_PMA_REG_8481_LED3_MASK,
10424 bnx2x_cl45_write(bp, phy,
10426 MDIO_PMA_REG_8481_LED5_MASK,
10430 bnx2x_cl45_write(bp, phy,
10432 MDIO_PMA_REG_8481_LED1_MASK,
10436 case LED_MODE_FRONT_PANEL_OFF:
10438 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10441 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10442 SHARED_HW_CFG_LED_EXTPHY1) {
10444 /* Set LED masks */
10445 bnx2x_cl45_write(bp, phy,
10447 MDIO_PMA_REG_8481_LED1_MASK,
10450 bnx2x_cl45_write(bp, phy,
10452 MDIO_PMA_REG_8481_LED2_MASK,
10455 bnx2x_cl45_write(bp, phy,
10457 MDIO_PMA_REG_8481_LED3_MASK,
10460 bnx2x_cl45_write(bp, phy,
10462 MDIO_PMA_REG_8481_LED5_MASK,
10466 bnx2x_cl45_write(bp, phy,
10468 MDIO_PMA_REG_8481_LED1_MASK,
10471 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10472 /* Disable MI_INT interrupt before setting LED4
10473 * source to constant off.
10475 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10478 params->link_flags |=
10479 LINK_FLAGS_INT_DISABLED;
10483 NIG_REG_MASK_INTERRUPT_PORT0 +
10487 bnx2x_cl45_write(bp, phy,
10489 MDIO_PMA_REG_8481_SIGNAL_MASK,
10496 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10498 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10499 SHARED_HW_CFG_LED_EXTPHY1) {
10500 /* Set control reg */
10501 bnx2x_cl45_read(bp, phy,
10503 MDIO_PMA_REG_8481_LINK_SIGNAL,
10508 bnx2x_cl45_write(bp, phy,
10510 MDIO_PMA_REG_8481_LINK_SIGNAL,
10513 /* Set LED masks */
10514 bnx2x_cl45_write(bp, phy,
10516 MDIO_PMA_REG_8481_LED1_MASK,
10519 bnx2x_cl45_write(bp, phy,
10521 MDIO_PMA_REG_8481_LED2_MASK,
10524 bnx2x_cl45_write(bp, phy,
10526 MDIO_PMA_REG_8481_LED3_MASK,
10529 bnx2x_cl45_write(bp, phy,
10531 MDIO_PMA_REG_8481_LED5_MASK,
10534 bnx2x_cl45_write(bp, phy,
10536 MDIO_PMA_REG_8481_LED1_MASK,
10539 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10540 /* Disable MI_INT interrupt before setting LED4
10541 * source to constant on.
10543 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10546 params->link_flags |=
10547 LINK_FLAGS_INT_DISABLED;
10551 NIG_REG_MASK_INTERRUPT_PORT0 +
10555 bnx2x_cl45_write(bp, phy,
10557 MDIO_PMA_REG_8481_SIGNAL_MASK,
10563 case LED_MODE_OPER:
10565 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10567 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10568 SHARED_HW_CFG_LED_EXTPHY1) {
10570 /* Set control reg */
10571 bnx2x_cl45_read(bp, phy,
10573 MDIO_PMA_REG_8481_LINK_SIGNAL,
10577 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10578 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10579 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10580 bnx2x_cl45_write(bp, phy,
10582 MDIO_PMA_REG_8481_LINK_SIGNAL,
10586 /* Set LED masks */
10587 bnx2x_cl45_write(bp, phy,
10589 MDIO_PMA_REG_8481_LED1_MASK,
10592 bnx2x_cl45_write(bp, phy,
10594 MDIO_PMA_REG_8481_LED2_MASK,
10597 bnx2x_cl45_write(bp, phy,
10599 MDIO_PMA_REG_8481_LED3_MASK,
10602 bnx2x_cl45_write(bp, phy,
10604 MDIO_PMA_REG_8481_LED5_MASK,
10608 bnx2x_cl45_write(bp, phy,
10610 MDIO_PMA_REG_8481_LED1_MASK,
10613 /* Tell LED3 to blink on source */
10614 bnx2x_cl45_read(bp, phy,
10616 MDIO_PMA_REG_8481_LINK_SIGNAL,
10619 val |= (1<<6); /* A83B[8:6]= 1 */
10620 bnx2x_cl45_write(bp, phy,
10622 MDIO_PMA_REG_8481_LINK_SIGNAL,
10625 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10626 /* Restore LED4 source to external link,
10627 * and re-enable interrupts.
10629 bnx2x_cl45_write(bp, phy,
10631 MDIO_PMA_REG_8481_SIGNAL_MASK,
10633 if (params->link_flags &
10634 LINK_FLAGS_INT_DISABLED) {
10635 bnx2x_link_int_enable(params);
10636 params->link_flags &=
10637 ~LINK_FLAGS_INT_DISABLED;
10644 /* This is a workaround for E3+84833 until autoneg
10645 * restart is fixed in f/w
10647 if (CHIP_IS_E3(bp)) {
10648 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10649 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10653 /******************************************************************/
10654 /* 54618SE PHY SECTION */
10655 /******************************************************************/
10656 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10657 struct link_params *params,
10660 struct bnx2x *bp = params->bp;
10664 /* Configure LED4: set to INTR (0x6). */
10665 /* Accessing shadow register 0xe. */
10666 bnx2x_cl22_write(bp, phy,
10667 MDIO_REG_GPHY_SHADOW,
10668 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10669 bnx2x_cl22_read(bp, phy,
10670 MDIO_REG_GPHY_SHADOW,
10672 temp &= ~(0xf << 4);
10673 temp |= (0x6 << 4);
10674 bnx2x_cl22_write(bp, phy,
10675 MDIO_REG_GPHY_SHADOW,
10676 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10677 /* Configure INTR based on link status change. */
10678 bnx2x_cl22_write(bp, phy,
10679 MDIO_REG_INTR_MASK,
10680 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10685 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10686 struct link_params *params,
10687 struct link_vars *vars)
10689 struct bnx2x *bp = params->bp;
10691 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10694 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10695 usleep_range(1000, 2000);
10697 /* This works with E3 only, no need to check the chip
10698 * before determining the port.
10700 port = params->port;
10702 cfg_pin = (REG_RD(bp, params->shmem_base +
10703 offsetof(struct shmem_region,
10704 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10705 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10706 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10708 /* Drive pin high to bring the GPHY out of reset. */
10709 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10711 /* wait for GPHY to reset */
10715 bnx2x_cl22_write(bp, phy,
10716 MDIO_PMA_REG_CTRL, 0x8000);
10717 bnx2x_wait_reset_complete(bp, phy, params);
10719 /* Wait for GPHY to reset */
10723 bnx2x_54618se_specific_func(phy, params, PHY_INIT);
10724 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10725 bnx2x_cl22_write(bp, phy,
10726 MDIO_REG_GPHY_SHADOW,
10727 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10728 bnx2x_cl22_read(bp, phy,
10729 MDIO_REG_GPHY_SHADOW,
10731 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10732 bnx2x_cl22_write(bp, phy,
10733 MDIO_REG_GPHY_SHADOW,
10734 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10737 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10738 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10740 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10741 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10742 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10744 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10745 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10746 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10748 /* Read all advertisement */
10749 bnx2x_cl22_read(bp, phy,
10753 bnx2x_cl22_read(bp, phy,
10757 bnx2x_cl22_read(bp, phy,
10761 /* Disable forced speed */
10762 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10763 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10766 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10767 (phy->speed_cap_mask &
10768 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10769 (phy->req_line_speed == SPEED_1000)) {
10770 an_1000_val |= (1<<8);
10771 autoneg_val |= (1<<9 | 1<<12);
10772 if (phy->req_duplex == DUPLEX_FULL)
10773 an_1000_val |= (1<<9);
10774 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10776 an_1000_val &= ~((1<<8) | (1<<9));
10778 bnx2x_cl22_write(bp, phy,
10781 bnx2x_cl22_read(bp, phy,
10785 /* Set 100 speed advertisement */
10786 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10787 (phy->speed_cap_mask &
10788 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10789 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10790 an_10_100_val |= (1<<7);
10791 /* Enable autoneg and restart autoneg for legacy speeds */
10792 autoneg_val |= (1<<9 | 1<<12);
10794 if (phy->req_duplex == DUPLEX_FULL)
10795 an_10_100_val |= (1<<8);
10796 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10799 /* Set 10 speed advertisement */
10800 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10801 (phy->speed_cap_mask &
10802 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10803 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10804 an_10_100_val |= (1<<5);
10805 autoneg_val |= (1<<9 | 1<<12);
10806 if (phy->req_duplex == DUPLEX_FULL)
10807 an_10_100_val |= (1<<6);
10808 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10811 /* Only 10/100 are allowed to work in FORCE mode */
10812 if (phy->req_line_speed == SPEED_100) {
10813 autoneg_val |= (1<<13);
10814 /* Enabled AUTO-MDIX when autoneg is disabled */
10815 bnx2x_cl22_write(bp, phy,
10817 (1<<15 | 1<<9 | 7<<0));
10818 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10820 if (phy->req_line_speed == SPEED_10) {
10821 /* Enabled AUTO-MDIX when autoneg is disabled */
10822 bnx2x_cl22_write(bp, phy,
10824 (1<<15 | 1<<9 | 7<<0));
10825 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10828 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10831 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10832 MDIO_REG_GPHY_EXP_ACCESS_TOP |
10833 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10834 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10836 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10838 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10840 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10841 bnx2x_eee_disable(phy, params, vars);
10842 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10843 (phy->req_duplex == DUPLEX_FULL) &&
10844 (bnx2x_eee_calc_timer(params) ||
10845 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10846 /* Need to advertise EEE only when requested,
10847 * and either no LPI assertion was requested,
10848 * or it was requested and a valid timer was set.
10849 * Also notice full duplex is required for EEE.
10851 bnx2x_eee_advertise(phy, params, vars,
10854 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10855 bnx2x_eee_disable(phy, params, vars);
10858 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10859 SHMEM_EEE_SUPPORTED_SHIFT;
10861 if (phy->flags & FLAGS_EEE) {
10862 /* Handle legacy auto-grEEEn */
10863 if (params->feature_config_flags &
10864 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10866 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10869 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10871 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10872 MDIO_AN_REG_EEE_ADV, temp);
10876 bnx2x_cl22_write(bp, phy,
10878 an_10_100_val | fc_val);
10880 if (phy->req_duplex == DUPLEX_FULL)
10881 autoneg_val |= (1<<8);
10883 bnx2x_cl22_write(bp, phy,
10884 MDIO_PMA_REG_CTRL, autoneg_val);
10890 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10891 struct link_params *params, u8 mode)
10893 struct bnx2x *bp = params->bp;
10896 bnx2x_cl22_write(bp, phy,
10897 MDIO_REG_GPHY_SHADOW,
10898 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10899 bnx2x_cl22_read(bp, phy,
10900 MDIO_REG_GPHY_SHADOW,
10904 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10906 case LED_MODE_FRONT_PANEL_OFF:
10910 case LED_MODE_OPER:
10919 bnx2x_cl22_write(bp, phy,
10920 MDIO_REG_GPHY_SHADOW,
10921 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10926 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10927 struct link_params *params)
10929 struct bnx2x *bp = params->bp;
10933 /* In case of no EPIO routed to reset the GPHY, put it
10934 * in low power mode.
10936 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10937 /* This works with E3 only, no need to check the chip
10938 * before determining the port.
10940 port = params->port;
10941 cfg_pin = (REG_RD(bp, params->shmem_base +
10942 offsetof(struct shmem_region,
10943 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10944 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10945 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10947 /* Drive pin low to put GPHY in reset. */
10948 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10951 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10952 struct link_params *params,
10953 struct link_vars *vars)
10955 struct bnx2x *bp = params->bp;
10958 u16 legacy_status, legacy_speed;
10960 /* Get speed operation status */
10961 bnx2x_cl22_read(bp, phy,
10962 MDIO_REG_GPHY_AUX_STATUS,
10964 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10966 /* Read status to clear the PHY interrupt. */
10967 bnx2x_cl22_read(bp, phy,
10968 MDIO_REG_INTR_STATUS,
10971 link_up = ((legacy_status & (1<<2)) == (1<<2));
10974 legacy_speed = (legacy_status & (7<<8));
10975 if (legacy_speed == (7<<8)) {
10976 vars->line_speed = SPEED_1000;
10977 vars->duplex = DUPLEX_FULL;
10978 } else if (legacy_speed == (6<<8)) {
10979 vars->line_speed = SPEED_1000;
10980 vars->duplex = DUPLEX_HALF;
10981 } else if (legacy_speed == (5<<8)) {
10982 vars->line_speed = SPEED_100;
10983 vars->duplex = DUPLEX_FULL;
10985 /* Omitting 100Base-T4 for now */
10986 else if (legacy_speed == (3<<8)) {
10987 vars->line_speed = SPEED_100;
10988 vars->duplex = DUPLEX_HALF;
10989 } else if (legacy_speed == (2<<8)) {
10990 vars->line_speed = SPEED_10;
10991 vars->duplex = DUPLEX_FULL;
10992 } else if (legacy_speed == (1<<8)) {
10993 vars->line_speed = SPEED_10;
10994 vars->duplex = DUPLEX_HALF;
10995 } else /* Should not happen */
10996 vars->line_speed = 0;
10999 "Link is up in %dMbps, is_duplex_full= %d\n",
11001 (vars->duplex == DUPLEX_FULL));
11003 /* Check legacy speed AN resolution */
11004 bnx2x_cl22_read(bp, phy,
11008 vars->link_status |=
11009 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11010 bnx2x_cl22_read(bp, phy,
11013 if ((val & (1<<0)) == 0)
11014 vars->link_status |=
11015 LINK_STATUS_PARALLEL_DETECTION_USED;
11017 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11020 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11022 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11023 /* Report LP advertised speeds */
11024 bnx2x_cl22_read(bp, phy, 0x5, &val);
11027 vars->link_status |=
11028 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11030 vars->link_status |=
11031 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11033 vars->link_status |=
11034 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11036 vars->link_status |=
11037 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11039 vars->link_status |=
11040 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11042 bnx2x_cl22_read(bp, phy, 0xa, &val);
11044 vars->link_status |=
11045 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11047 vars->link_status |=
11048 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11050 if ((phy->flags & FLAGS_EEE) &&
11051 bnx2x_eee_has_cap(params))
11052 bnx2x_eee_an_resolve(phy, params, vars);
11058 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11059 struct link_params *params)
11061 struct bnx2x *bp = params->bp;
11063 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11065 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11067 /* Enable master/slave manual mmode and set to master */
11068 /* mii write 9 [bits set 11 12] */
11069 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11071 /* forced 1G and disable autoneg */
11072 /* set val [mii read 0] */
11073 /* set val [expr $val & [bits clear 6 12 13]] */
11074 /* set val [expr $val | [bits set 6 8]] */
11075 /* mii write 0 $val */
11076 bnx2x_cl22_read(bp, phy, 0x00, &val);
11077 val &= ~((1<<6) | (1<<12) | (1<<13));
11078 val |= (1<<6) | (1<<8);
11079 bnx2x_cl22_write(bp, phy, 0x00, val);
11081 /* Set external loopback and Tx using 6dB coding */
11082 /* mii write 0x18 7 */
11083 /* set val [mii read 0x18] */
11084 /* mii write 0x18 [expr $val | [bits set 10 15]] */
11085 bnx2x_cl22_write(bp, phy, 0x18, 7);
11086 bnx2x_cl22_read(bp, phy, 0x18, &val);
11087 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11089 /* This register opens the gate for the UMAC despite its name */
11090 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11092 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11093 * length used by the MAC receive logic to check frames.
11095 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11098 /******************************************************************/
11099 /* SFX7101 PHY SECTION */
11100 /******************************************************************/
11101 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11102 struct link_params *params)
11104 struct bnx2x *bp = params->bp;
11105 /* SFX7101_XGXS_TEST1 */
11106 bnx2x_cl45_write(bp, phy,
11107 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11110 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11111 struct link_params *params,
11112 struct link_vars *vars)
11114 u16 fw_ver1, fw_ver2, val;
11115 struct bnx2x *bp = params->bp;
11116 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11118 /* Restore normal power mode*/
11119 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11120 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11122 bnx2x_ext_phy_hw_reset(bp, params->port);
11123 bnx2x_wait_reset_complete(bp, phy, params);
11125 bnx2x_cl45_write(bp, phy,
11126 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11127 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11128 bnx2x_cl45_write(bp, phy,
11129 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11131 bnx2x_ext_phy_set_pause(params, phy, vars);
11132 /* Restart autoneg */
11133 bnx2x_cl45_read(bp, phy,
11134 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11136 bnx2x_cl45_write(bp, phy,
11137 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11139 /* Save spirom version */
11140 bnx2x_cl45_read(bp, phy,
11141 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11143 bnx2x_cl45_read(bp, phy,
11144 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11145 bnx2x_save_spirom_version(bp, params->port,
11146 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11150 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11151 struct link_params *params,
11152 struct link_vars *vars)
11154 struct bnx2x *bp = params->bp;
11157 bnx2x_cl45_read(bp, phy,
11158 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11159 bnx2x_cl45_read(bp, phy,
11160 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11161 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11163 bnx2x_cl45_read(bp, phy,
11164 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11165 bnx2x_cl45_read(bp, phy,
11166 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11167 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11169 link_up = ((val1 & 4) == 4);
11170 /* If link is up print the AN outcome of the SFX7101 PHY */
11172 bnx2x_cl45_read(bp, phy,
11173 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11175 vars->line_speed = SPEED_10000;
11176 vars->duplex = DUPLEX_FULL;
11177 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11178 val2, (val2 & (1<<14)));
11179 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11180 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11182 /* Read LP advertised speeds */
11183 if (val2 & (1<<11))
11184 vars->link_status |=
11185 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11190 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11194 str[0] = (spirom_ver & 0xFF);
11195 str[1] = (spirom_ver & 0xFF00) >> 8;
11196 str[2] = (spirom_ver & 0xFF0000) >> 16;
11197 str[3] = (spirom_ver & 0xFF000000) >> 24;
11203 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11207 bnx2x_cl45_read(bp, phy,
11209 MDIO_PMA_REG_7101_RESET, &val);
11211 for (cnt = 0; cnt < 10; cnt++) {
11213 /* Writes a self-clearing reset */
11214 bnx2x_cl45_write(bp, phy,
11216 MDIO_PMA_REG_7101_RESET,
11218 /* Wait for clear */
11219 bnx2x_cl45_read(bp, phy,
11221 MDIO_PMA_REG_7101_RESET, &val);
11223 if ((val & (1<<15)) == 0)
11228 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11229 struct link_params *params) {
11230 /* Low power mode is controlled by GPIO 2 */
11231 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11232 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11233 /* The PHY reset is controlled by GPIO 1 */
11234 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11235 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11238 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11239 struct link_params *params, u8 mode)
11242 struct bnx2x *bp = params->bp;
11244 case LED_MODE_FRONT_PANEL_OFF:
11251 case LED_MODE_OPER:
11255 bnx2x_cl45_write(bp, phy,
11257 MDIO_PMA_REG_7107_LINK_LED_CNTL,
11261 /******************************************************************/
11262 /* STATIC PHY DECLARATION */
11263 /******************************************************************/
11265 static const struct bnx2x_phy phy_null = {
11266 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11269 .flags = FLAGS_INIT_XGXS_FIRST,
11270 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11271 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11274 .media_type = ETH_PHY_NOT_PRESENT,
11276 .req_flow_ctrl = 0,
11277 .req_line_speed = 0,
11278 .speed_cap_mask = 0,
11281 .config_init = (config_init_t)NULL,
11282 .read_status = (read_status_t)NULL,
11283 .link_reset = (link_reset_t)NULL,
11284 .config_loopback = (config_loopback_t)NULL,
11285 .format_fw_ver = (format_fw_ver_t)NULL,
11286 .hw_reset = (hw_reset_t)NULL,
11287 .set_link_led = (set_link_led_t)NULL,
11288 .phy_specific_func = (phy_specific_func_t)NULL
11291 static const struct bnx2x_phy phy_serdes = {
11292 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11296 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11297 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11299 .supported = (SUPPORTED_10baseT_Half |
11300 SUPPORTED_10baseT_Full |
11301 SUPPORTED_100baseT_Half |
11302 SUPPORTED_100baseT_Full |
11303 SUPPORTED_1000baseT_Full |
11304 SUPPORTED_2500baseX_Full |
11306 SUPPORTED_Autoneg |
11308 SUPPORTED_Asym_Pause),
11309 .media_type = ETH_PHY_BASE_T,
11311 .req_flow_ctrl = 0,
11312 .req_line_speed = 0,
11313 .speed_cap_mask = 0,
11316 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11317 .read_status = (read_status_t)bnx2x_link_settings_status,
11318 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11319 .config_loopback = (config_loopback_t)NULL,
11320 .format_fw_ver = (format_fw_ver_t)NULL,
11321 .hw_reset = (hw_reset_t)NULL,
11322 .set_link_led = (set_link_led_t)NULL,
11323 .phy_specific_func = (phy_specific_func_t)NULL
11326 static const struct bnx2x_phy phy_xgxs = {
11327 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11331 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11332 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11334 .supported = (SUPPORTED_10baseT_Half |
11335 SUPPORTED_10baseT_Full |
11336 SUPPORTED_100baseT_Half |
11337 SUPPORTED_100baseT_Full |
11338 SUPPORTED_1000baseT_Full |
11339 SUPPORTED_2500baseX_Full |
11340 SUPPORTED_10000baseT_Full |
11342 SUPPORTED_Autoneg |
11344 SUPPORTED_Asym_Pause),
11345 .media_type = ETH_PHY_CX4,
11347 .req_flow_ctrl = 0,
11348 .req_line_speed = 0,
11349 .speed_cap_mask = 0,
11352 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11353 .read_status = (read_status_t)bnx2x_link_settings_status,
11354 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11355 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11356 .format_fw_ver = (format_fw_ver_t)NULL,
11357 .hw_reset = (hw_reset_t)NULL,
11358 .set_link_led = (set_link_led_t)NULL,
11359 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11361 static const struct bnx2x_phy phy_warpcore = {
11362 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11365 .flags = FLAGS_TX_ERROR_CHECK,
11366 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11367 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11369 .supported = (SUPPORTED_10baseT_Half |
11370 SUPPORTED_10baseT_Full |
11371 SUPPORTED_100baseT_Half |
11372 SUPPORTED_100baseT_Full |
11373 SUPPORTED_1000baseT_Full |
11374 SUPPORTED_10000baseT_Full |
11375 SUPPORTED_20000baseKR2_Full |
11376 SUPPORTED_20000baseMLD2_Full |
11378 SUPPORTED_Autoneg |
11380 SUPPORTED_Asym_Pause),
11381 .media_type = ETH_PHY_UNSPECIFIED,
11383 .req_flow_ctrl = 0,
11384 .req_line_speed = 0,
11385 .speed_cap_mask = 0,
11386 /* req_duplex = */0,
11388 .config_init = (config_init_t)bnx2x_warpcore_config_init,
11389 .read_status = (read_status_t)bnx2x_warpcore_read_status,
11390 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
11391 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11392 .format_fw_ver = (format_fw_ver_t)NULL,
11393 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
11394 .set_link_led = (set_link_led_t)NULL,
11395 .phy_specific_func = (phy_specific_func_t)NULL
11399 static const struct bnx2x_phy phy_7101 = {
11400 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11403 .flags = FLAGS_FAN_FAILURE_DET_REQ,
11404 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11405 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11407 .supported = (SUPPORTED_10000baseT_Full |
11409 SUPPORTED_Autoneg |
11411 SUPPORTED_Asym_Pause),
11412 .media_type = ETH_PHY_BASE_T,
11414 .req_flow_ctrl = 0,
11415 .req_line_speed = 0,
11416 .speed_cap_mask = 0,
11419 .config_init = (config_init_t)bnx2x_7101_config_init,
11420 .read_status = (read_status_t)bnx2x_7101_read_status,
11421 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11422 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11423 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
11424 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
11425 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
11426 .phy_specific_func = (phy_specific_func_t)NULL
11428 static const struct bnx2x_phy phy_8073 = {
11429 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11433 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11434 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11436 .supported = (SUPPORTED_10000baseT_Full |
11437 SUPPORTED_2500baseX_Full |
11438 SUPPORTED_1000baseT_Full |
11440 SUPPORTED_Autoneg |
11442 SUPPORTED_Asym_Pause),
11443 .media_type = ETH_PHY_KR,
11445 .req_flow_ctrl = 0,
11446 .req_line_speed = 0,
11447 .speed_cap_mask = 0,
11450 .config_init = (config_init_t)bnx2x_8073_config_init,
11451 .read_status = (read_status_t)bnx2x_8073_read_status,
11452 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
11453 .config_loopback = (config_loopback_t)NULL,
11454 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11455 .hw_reset = (hw_reset_t)NULL,
11456 .set_link_led = (set_link_led_t)NULL,
11457 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11459 static const struct bnx2x_phy phy_8705 = {
11460 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11463 .flags = FLAGS_INIT_XGXS_FIRST,
11464 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11465 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11467 .supported = (SUPPORTED_10000baseT_Full |
11470 SUPPORTED_Asym_Pause),
11471 .media_type = ETH_PHY_XFP_FIBER,
11473 .req_flow_ctrl = 0,
11474 .req_line_speed = 0,
11475 .speed_cap_mask = 0,
11478 .config_init = (config_init_t)bnx2x_8705_config_init,
11479 .read_status = (read_status_t)bnx2x_8705_read_status,
11480 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11481 .config_loopback = (config_loopback_t)NULL,
11482 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
11483 .hw_reset = (hw_reset_t)NULL,
11484 .set_link_led = (set_link_led_t)NULL,
11485 .phy_specific_func = (phy_specific_func_t)NULL
11487 static const struct bnx2x_phy phy_8706 = {
11488 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11491 .flags = FLAGS_INIT_XGXS_FIRST,
11492 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11493 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11495 .supported = (SUPPORTED_10000baseT_Full |
11496 SUPPORTED_1000baseT_Full |
11499 SUPPORTED_Asym_Pause),
11500 .media_type = ETH_PHY_SFPP_10G_FIBER,
11502 .req_flow_ctrl = 0,
11503 .req_line_speed = 0,
11504 .speed_cap_mask = 0,
11507 .config_init = (config_init_t)bnx2x_8706_config_init,
11508 .read_status = (read_status_t)bnx2x_8706_read_status,
11509 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11510 .config_loopback = (config_loopback_t)NULL,
11511 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11512 .hw_reset = (hw_reset_t)NULL,
11513 .set_link_led = (set_link_led_t)NULL,
11514 .phy_specific_func = (phy_specific_func_t)NULL
11517 static const struct bnx2x_phy phy_8726 = {
11518 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11521 .flags = (FLAGS_INIT_XGXS_FIRST |
11522 FLAGS_TX_ERROR_CHECK),
11523 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11524 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11526 .supported = (SUPPORTED_10000baseT_Full |
11527 SUPPORTED_1000baseT_Full |
11528 SUPPORTED_Autoneg |
11531 SUPPORTED_Asym_Pause),
11532 .media_type = ETH_PHY_NOT_PRESENT,
11534 .req_flow_ctrl = 0,
11535 .req_line_speed = 0,
11536 .speed_cap_mask = 0,
11539 .config_init = (config_init_t)bnx2x_8726_config_init,
11540 .read_status = (read_status_t)bnx2x_8726_read_status,
11541 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
11542 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11543 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11544 .hw_reset = (hw_reset_t)NULL,
11545 .set_link_led = (set_link_led_t)NULL,
11546 .phy_specific_func = (phy_specific_func_t)NULL
11549 static const struct bnx2x_phy phy_8727 = {
11550 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11553 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11554 FLAGS_TX_ERROR_CHECK),
11555 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11556 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11558 .supported = (SUPPORTED_10000baseT_Full |
11559 SUPPORTED_1000baseT_Full |
11562 SUPPORTED_Asym_Pause),
11563 .media_type = ETH_PHY_NOT_PRESENT,
11565 .req_flow_ctrl = 0,
11566 .req_line_speed = 0,
11567 .speed_cap_mask = 0,
11570 .config_init = (config_init_t)bnx2x_8727_config_init,
11571 .read_status = (read_status_t)bnx2x_8727_read_status,
11572 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
11573 .config_loopback = (config_loopback_t)NULL,
11574 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11575 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
11576 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
11577 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11579 static const struct bnx2x_phy phy_8481 = {
11580 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11583 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11584 FLAGS_REARM_LATCH_SIGNAL,
11585 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11586 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11588 .supported = (SUPPORTED_10baseT_Half |
11589 SUPPORTED_10baseT_Full |
11590 SUPPORTED_100baseT_Half |
11591 SUPPORTED_100baseT_Full |
11592 SUPPORTED_1000baseT_Full |
11593 SUPPORTED_10000baseT_Full |
11595 SUPPORTED_Autoneg |
11597 SUPPORTED_Asym_Pause),
11598 .media_type = ETH_PHY_BASE_T,
11600 .req_flow_ctrl = 0,
11601 .req_line_speed = 0,
11602 .speed_cap_mask = 0,
11605 .config_init = (config_init_t)bnx2x_8481_config_init,
11606 .read_status = (read_status_t)bnx2x_848xx_read_status,
11607 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
11608 .config_loopback = (config_loopback_t)NULL,
11609 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11610 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
11611 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11612 .phy_specific_func = (phy_specific_func_t)NULL
11615 static const struct bnx2x_phy phy_84823 = {
11616 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11619 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11620 FLAGS_REARM_LATCH_SIGNAL |
11621 FLAGS_TX_ERROR_CHECK),
11622 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11623 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11625 .supported = (SUPPORTED_10baseT_Half |
11626 SUPPORTED_10baseT_Full |
11627 SUPPORTED_100baseT_Half |
11628 SUPPORTED_100baseT_Full |
11629 SUPPORTED_1000baseT_Full |
11630 SUPPORTED_10000baseT_Full |
11632 SUPPORTED_Autoneg |
11634 SUPPORTED_Asym_Pause),
11635 .media_type = ETH_PHY_BASE_T,
11637 .req_flow_ctrl = 0,
11638 .req_line_speed = 0,
11639 .speed_cap_mask = 0,
11642 .config_init = (config_init_t)bnx2x_848x3_config_init,
11643 .read_status = (read_status_t)bnx2x_848xx_read_status,
11644 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11645 .config_loopback = (config_loopback_t)NULL,
11646 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11647 .hw_reset = (hw_reset_t)NULL,
11648 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11649 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11652 static const struct bnx2x_phy phy_84833 = {
11653 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11656 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11657 FLAGS_REARM_LATCH_SIGNAL |
11658 FLAGS_TX_ERROR_CHECK),
11659 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11660 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11662 .supported = (SUPPORTED_100baseT_Half |
11663 SUPPORTED_100baseT_Full |
11664 SUPPORTED_1000baseT_Full |
11665 SUPPORTED_10000baseT_Full |
11667 SUPPORTED_Autoneg |
11669 SUPPORTED_Asym_Pause),
11670 .media_type = ETH_PHY_BASE_T,
11672 .req_flow_ctrl = 0,
11673 .req_line_speed = 0,
11674 .speed_cap_mask = 0,
11677 .config_init = (config_init_t)bnx2x_848x3_config_init,
11678 .read_status = (read_status_t)bnx2x_848xx_read_status,
11679 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11680 .config_loopback = (config_loopback_t)NULL,
11681 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11682 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11683 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11684 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11687 static const struct bnx2x_phy phy_84834 = {
11688 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11691 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11692 FLAGS_REARM_LATCH_SIGNAL,
11693 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11694 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11696 .supported = (SUPPORTED_100baseT_Half |
11697 SUPPORTED_100baseT_Full |
11698 SUPPORTED_1000baseT_Full |
11699 SUPPORTED_10000baseT_Full |
11701 SUPPORTED_Autoneg |
11703 SUPPORTED_Asym_Pause),
11704 .media_type = ETH_PHY_BASE_T,
11706 .req_flow_ctrl = 0,
11707 .req_line_speed = 0,
11708 .speed_cap_mask = 0,
11711 .config_init = (config_init_t)bnx2x_848x3_config_init,
11712 .read_status = (read_status_t)bnx2x_848xx_read_status,
11713 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11714 .config_loopback = (config_loopback_t)NULL,
11715 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11716 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11717 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11718 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11721 static const struct bnx2x_phy phy_54618se = {
11722 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11725 .flags = FLAGS_INIT_XGXS_FIRST,
11726 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11727 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11729 .supported = (SUPPORTED_10baseT_Half |
11730 SUPPORTED_10baseT_Full |
11731 SUPPORTED_100baseT_Half |
11732 SUPPORTED_100baseT_Full |
11733 SUPPORTED_1000baseT_Full |
11735 SUPPORTED_Autoneg |
11737 SUPPORTED_Asym_Pause),
11738 .media_type = ETH_PHY_BASE_T,
11740 .req_flow_ctrl = 0,
11741 .req_line_speed = 0,
11742 .speed_cap_mask = 0,
11743 /* req_duplex = */0,
11745 .config_init = (config_init_t)bnx2x_54618se_config_init,
11746 .read_status = (read_status_t)bnx2x_54618se_read_status,
11747 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
11748 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11749 .format_fw_ver = (format_fw_ver_t)NULL,
11750 .hw_reset = (hw_reset_t)NULL,
11751 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led,
11752 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
11754 /*****************************************************************/
11756 /* Populate the phy according. Main function: bnx2x_populate_phy */
11758 /*****************************************************************/
11760 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11761 struct bnx2x_phy *phy, u8 port,
11764 /* Get the 4 lanes xgxs config rx and tx */
11765 u32 rx = 0, tx = 0, i;
11766 for (i = 0; i < 2; i++) {
11767 /* INT_PHY and EXT_PHY1 share the same value location in
11768 * the shmem. When num_phys is greater than 1, than this value
11769 * applies only to EXT_PHY1
11771 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11772 rx = REG_RD(bp, shmem_base +
11773 offsetof(struct shmem_region,
11774 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11776 tx = REG_RD(bp, shmem_base +
11777 offsetof(struct shmem_region,
11778 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11780 rx = REG_RD(bp, shmem_base +
11781 offsetof(struct shmem_region,
11782 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11784 tx = REG_RD(bp, shmem_base +
11785 offsetof(struct shmem_region,
11786 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11789 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11790 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11792 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11793 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11797 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11798 u8 phy_index, u8 port)
11800 u32 ext_phy_config = 0;
11801 switch (phy_index) {
11803 ext_phy_config = REG_RD(bp, shmem_base +
11804 offsetof(struct shmem_region,
11805 dev_info.port_hw_config[port].external_phy_config));
11808 ext_phy_config = REG_RD(bp, shmem_base +
11809 offsetof(struct shmem_region,
11810 dev_info.port_hw_config[port].external_phy_config2));
11813 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11817 return ext_phy_config;
11819 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11820 struct bnx2x_phy *phy)
11824 u32 switch_cfg = (REG_RD(bp, shmem_base +
11825 offsetof(struct shmem_region,
11826 dev_info.port_feature_config[port].link_config)) &
11827 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11828 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11829 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11831 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11832 if (USES_WARPCORE(bp)) {
11834 phy_addr = REG_RD(bp,
11835 MISC_REG_WC0_CTRL_PHY_ADDR);
11836 *phy = phy_warpcore;
11837 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11838 phy->flags |= FLAGS_4_PORT_MODE;
11840 phy->flags &= ~FLAGS_4_PORT_MODE;
11841 /* Check Dual mode */
11842 serdes_net_if = (REG_RD(bp, shmem_base +
11843 offsetof(struct shmem_region, dev_info.
11844 port_hw_config[port].default_cfg)) &
11845 PORT_HW_CFG_NET_SERDES_IF_MASK);
11846 /* Set the appropriate supported and flags indications per
11847 * interface type of the chip
11849 switch (serdes_net_if) {
11850 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11851 phy->supported &= (SUPPORTED_10baseT_Half |
11852 SUPPORTED_10baseT_Full |
11853 SUPPORTED_100baseT_Half |
11854 SUPPORTED_100baseT_Full |
11855 SUPPORTED_1000baseT_Full |
11857 SUPPORTED_Autoneg |
11859 SUPPORTED_Asym_Pause);
11860 phy->media_type = ETH_PHY_BASE_T;
11862 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11863 phy->supported &= (SUPPORTED_1000baseT_Full |
11864 SUPPORTED_10000baseT_Full |
11867 SUPPORTED_Asym_Pause);
11868 phy->media_type = ETH_PHY_XFP_FIBER;
11870 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11871 phy->supported &= (SUPPORTED_1000baseT_Full |
11872 SUPPORTED_10000baseT_Full |
11875 SUPPORTED_Asym_Pause);
11876 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
11878 case PORT_HW_CFG_NET_SERDES_IF_KR:
11879 phy->media_type = ETH_PHY_KR;
11880 phy->supported &= (SUPPORTED_1000baseT_Full |
11881 SUPPORTED_10000baseT_Full |
11883 SUPPORTED_Autoneg |
11885 SUPPORTED_Asym_Pause);
11887 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11888 phy->media_type = ETH_PHY_KR;
11889 phy->flags |= FLAGS_WC_DUAL_MODE;
11890 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11893 SUPPORTED_Asym_Pause);
11895 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11896 phy->media_type = ETH_PHY_KR;
11897 phy->flags |= FLAGS_WC_DUAL_MODE;
11898 phy->supported &= (SUPPORTED_20000baseKR2_Full |
11899 SUPPORTED_10000baseT_Full |
11900 SUPPORTED_1000baseT_Full |
11901 SUPPORTED_Autoneg |
11904 SUPPORTED_Asym_Pause);
11905 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
11908 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11913 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11914 * was not set as expected. For B0, ECO will be enabled so there
11915 * won't be an issue there
11917 if (CHIP_REV(bp) == CHIP_REV_Ax)
11918 phy->flags |= FLAGS_MDC_MDIO_WA;
11920 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11922 switch (switch_cfg) {
11923 case SWITCH_CFG_1G:
11924 phy_addr = REG_RD(bp,
11925 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11929 case SWITCH_CFG_10G:
11930 phy_addr = REG_RD(bp,
11931 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11936 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11940 phy->addr = (u8)phy_addr;
11941 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11942 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11944 if (CHIP_IS_E2(bp))
11945 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11947 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11949 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11950 port, phy->addr, phy->mdio_ctrl);
11952 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11956 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11961 struct bnx2x_phy *phy)
11963 u32 ext_phy_config, phy_type, config2;
11964 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11965 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11967 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11968 /* Select the phy type */
11969 switch (phy_type) {
11970 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11971 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11974 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11977 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11980 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11981 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11984 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11985 /* BCM8727_NOC => BCM8727 no over current */
11986 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11988 phy->flags |= FLAGS_NOC;
11990 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11991 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11992 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11995 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11998 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12001 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12004 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12007 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12008 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12009 *phy = phy_54618se;
12010 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12011 phy->flags |= FLAGS_EEE;
12013 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12016 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12021 /* In case external PHY wasn't found */
12022 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12023 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12028 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12029 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12031 /* The shmem address of the phy version is located on different
12032 * structures. In case this structure is too old, do not set
12035 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12036 dev_info.shared_hw_config.config2));
12037 if (phy_index == EXT_PHY1) {
12038 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12039 port_mb[port].ext_phy_fw_version);
12041 /* Check specific mdc mdio settings */
12042 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12043 mdc_mdio_access = config2 &
12044 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12046 u32 size = REG_RD(bp, shmem2_base);
12049 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12050 phy->ver_addr = shmem2_base +
12051 offsetof(struct shmem2_region,
12052 ext_phy_fw_version2[port]);
12054 /* Check specific mdc mdio settings */
12055 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12056 mdc_mdio_access = (config2 &
12057 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12058 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12059 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12061 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12063 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12064 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12066 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12067 * version lower than or equal to 1.39
12069 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12070 if (((raw_ver & 0x7F) <= 39) &&
12071 (((raw_ver & 0xF80) >> 7) <= 1))
12072 phy->supported &= ~(SUPPORTED_100baseT_Half |
12073 SUPPORTED_100baseT_Full);
12076 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12077 phy_type, port, phy_index);
12078 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
12079 phy->addr, phy->mdio_ctrl);
12083 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12084 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12087 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12088 if (phy_index == INT_PHY)
12089 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12090 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12095 static void bnx2x_phy_def_cfg(struct link_params *params,
12096 struct bnx2x_phy *phy,
12099 struct bnx2x *bp = params->bp;
12101 /* Populate the default phy configuration for MF mode */
12102 if (phy_index == EXT_PHY2) {
12103 link_config = REG_RD(bp, params->shmem_base +
12104 offsetof(struct shmem_region, dev_info.
12105 port_feature_config[params->port].link_config2));
12106 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12107 offsetof(struct shmem_region,
12109 port_hw_config[params->port].speed_capability_mask2));
12111 link_config = REG_RD(bp, params->shmem_base +
12112 offsetof(struct shmem_region, dev_info.
12113 port_feature_config[params->port].link_config));
12114 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12115 offsetof(struct shmem_region,
12117 port_hw_config[params->port].speed_capability_mask));
12120 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12121 phy_index, link_config, phy->speed_cap_mask);
12123 phy->req_duplex = DUPLEX_FULL;
12124 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
12125 case PORT_FEATURE_LINK_SPEED_10M_HALF:
12126 phy->req_duplex = DUPLEX_HALF;
12127 case PORT_FEATURE_LINK_SPEED_10M_FULL:
12128 phy->req_line_speed = SPEED_10;
12130 case PORT_FEATURE_LINK_SPEED_100M_HALF:
12131 phy->req_duplex = DUPLEX_HALF;
12132 case PORT_FEATURE_LINK_SPEED_100M_FULL:
12133 phy->req_line_speed = SPEED_100;
12135 case PORT_FEATURE_LINK_SPEED_1G:
12136 phy->req_line_speed = SPEED_1000;
12138 case PORT_FEATURE_LINK_SPEED_2_5G:
12139 phy->req_line_speed = SPEED_2500;
12141 case PORT_FEATURE_LINK_SPEED_10G_CX4:
12142 phy->req_line_speed = SPEED_10000;
12145 phy->req_line_speed = SPEED_AUTO_NEG;
12149 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
12150 case PORT_FEATURE_FLOW_CONTROL_AUTO:
12151 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12153 case PORT_FEATURE_FLOW_CONTROL_TX:
12154 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12156 case PORT_FEATURE_FLOW_CONTROL_RX:
12157 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12159 case PORT_FEATURE_FLOW_CONTROL_BOTH:
12160 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12163 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12168 u32 bnx2x_phy_selection(struct link_params *params)
12170 u32 phy_config_swapped, prio_cfg;
12171 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12173 phy_config_swapped = params->multi_phy_config &
12174 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12176 prio_cfg = params->multi_phy_config &
12177 PORT_HW_CFG_PHY_SELECTION_MASK;
12179 if (phy_config_swapped) {
12180 switch (prio_cfg) {
12181 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12182 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12184 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12185 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12187 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12188 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12190 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12191 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12195 return_cfg = prio_cfg;
12200 int bnx2x_phy_probe(struct link_params *params)
12202 u8 phy_index, actual_phy_idx;
12203 u32 phy_config_swapped, sync_offset, media_types;
12204 struct bnx2x *bp = params->bp;
12205 struct bnx2x_phy *phy;
12206 params->num_phys = 0;
12207 DP(NETIF_MSG_LINK, "Begin phy probe\n");
12208 phy_config_swapped = params->multi_phy_config &
12209 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12211 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12213 actual_phy_idx = phy_index;
12214 if (phy_config_swapped) {
12215 if (phy_index == EXT_PHY1)
12216 actual_phy_idx = EXT_PHY2;
12217 else if (phy_index == EXT_PHY2)
12218 actual_phy_idx = EXT_PHY1;
12220 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12221 " actual_phy_idx %x\n", phy_config_swapped,
12222 phy_index, actual_phy_idx);
12223 phy = ¶ms->phy[actual_phy_idx];
12224 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12225 params->shmem2_base, params->port,
12227 params->num_phys = 0;
12228 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12230 for (phy_index = INT_PHY;
12231 phy_index < MAX_PHYS;
12236 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12239 if (params->feature_config_flags &
12240 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12241 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12243 if (!(params->feature_config_flags &
12244 FEATURE_CONFIG_MT_SUPPORT))
12245 phy->flags |= FLAGS_MDC_MDIO_WA_G;
12247 sync_offset = params->shmem_base +
12248 offsetof(struct shmem_region,
12249 dev_info.port_hw_config[params->port].media_type);
12250 media_types = REG_RD(bp, sync_offset);
12252 /* Update media type for non-PMF sync only for the first time
12253 * In case the media type changes afterwards, it will be updated
12254 * using the update_status function
12256 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12257 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12258 actual_phy_idx))) == 0) {
12259 media_types |= ((phy->media_type &
12260 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12261 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12264 REG_WR(bp, sync_offset, media_types);
12266 bnx2x_phy_def_cfg(params, phy, phy_index);
12267 params->num_phys++;
12270 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12274 static void bnx2x_init_bmac_loopback(struct link_params *params,
12275 struct link_vars *vars)
12277 struct bnx2x *bp = params->bp;
12279 vars->line_speed = SPEED_10000;
12280 vars->duplex = DUPLEX_FULL;
12281 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12282 vars->mac_type = MAC_TYPE_BMAC;
12284 vars->phy_flags = PHY_XGXS_FLAG;
12286 bnx2x_xgxs_deassert(params);
12288 /* Set bmac loopback */
12289 bnx2x_bmac_enable(params, vars, 1, 1);
12291 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12294 static void bnx2x_init_emac_loopback(struct link_params *params,
12295 struct link_vars *vars)
12297 struct bnx2x *bp = params->bp;
12299 vars->line_speed = SPEED_1000;
12300 vars->duplex = DUPLEX_FULL;
12301 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12302 vars->mac_type = MAC_TYPE_EMAC;
12304 vars->phy_flags = PHY_XGXS_FLAG;
12306 bnx2x_xgxs_deassert(params);
12307 /* Set bmac loopback */
12308 bnx2x_emac_enable(params, vars, 1);
12309 bnx2x_emac_program(params, vars);
12310 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12313 static void bnx2x_init_xmac_loopback(struct link_params *params,
12314 struct link_vars *vars)
12316 struct bnx2x *bp = params->bp;
12318 if (!params->req_line_speed[0])
12319 vars->line_speed = SPEED_10000;
12321 vars->line_speed = params->req_line_speed[0];
12322 vars->duplex = DUPLEX_FULL;
12323 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12324 vars->mac_type = MAC_TYPE_XMAC;
12325 vars->phy_flags = PHY_XGXS_FLAG;
12326 /* Set WC to loopback mode since link is required to provide clock
12327 * to the XMAC in 20G mode
12329 bnx2x_set_aer_mmd(params, ¶ms->phy[0]);
12330 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0);
12331 params->phy[INT_PHY].config_loopback(
12332 ¶ms->phy[INT_PHY],
12335 bnx2x_xmac_enable(params, vars, 1);
12336 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12339 static void bnx2x_init_umac_loopback(struct link_params *params,
12340 struct link_vars *vars)
12342 struct bnx2x *bp = params->bp;
12344 vars->line_speed = SPEED_1000;
12345 vars->duplex = DUPLEX_FULL;
12346 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12347 vars->mac_type = MAC_TYPE_UMAC;
12348 vars->phy_flags = PHY_XGXS_FLAG;
12349 bnx2x_umac_enable(params, vars, 1);
12351 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12354 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12355 struct link_vars *vars)
12357 struct bnx2x *bp = params->bp;
12358 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
12360 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12361 vars->duplex = DUPLEX_FULL;
12362 if (params->req_line_speed[0] == SPEED_1000)
12363 vars->line_speed = SPEED_1000;
12364 else if ((params->req_line_speed[0] == SPEED_20000) ||
12365 (int_phy->flags & FLAGS_WC_DUAL_MODE))
12366 vars->line_speed = SPEED_20000;
12368 vars->line_speed = SPEED_10000;
12370 if (!USES_WARPCORE(bp))
12371 bnx2x_xgxs_deassert(params);
12372 bnx2x_link_initialize(params, vars);
12374 if (params->req_line_speed[0] == SPEED_1000) {
12375 if (USES_WARPCORE(bp))
12376 bnx2x_umac_enable(params, vars, 0);
12378 bnx2x_emac_program(params, vars);
12379 bnx2x_emac_enable(params, vars, 0);
12382 if (USES_WARPCORE(bp))
12383 bnx2x_xmac_enable(params, vars, 0);
12385 bnx2x_bmac_enable(params, vars, 0, 1);
12388 if (params->loopback_mode == LOOPBACK_XGXS) {
12389 /* Set 10G XGXS loopback */
12390 int_phy->config_loopback(int_phy, params);
12392 /* Set external phy loopback */
12394 for (phy_index = EXT_PHY1;
12395 phy_index < params->num_phys; phy_index++)
12396 if (params->phy[phy_index].config_loopback)
12397 params->phy[phy_index].config_loopback(
12398 ¶ms->phy[phy_index],
12401 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12403 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12406 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12408 struct bnx2x *bp = params->bp;
12409 u8 val = en * 0x1F;
12411 /* Open / close the gate between the NIG and the BRB */
12412 if (!CHIP_IS_E1x(bp))
12414 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12416 if (!CHIP_IS_E1(bp)) {
12417 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12421 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12422 NIG_REG_LLH0_BRB1_NOT_MCP), en);
12424 static int bnx2x_avoid_link_flap(struct link_params *params,
12425 struct link_vars *vars)
12428 u32 dont_clear_stat, lfa_sts;
12429 struct bnx2x *bp = params->bp;
12431 /* Sync the link parameters */
12432 bnx2x_link_status_update(params, vars);
12435 * The module verification was already done by previous link owner,
12436 * so this call is meant only to get warning message
12439 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12440 struct bnx2x_phy *phy = ¶ms->phy[phy_idx];
12441 if (phy->phy_specific_func) {
12442 DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12443 phy->phy_specific_func(phy, params, PHY_INIT);
12445 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12446 (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12447 (phy->media_type == ETH_PHY_DA_TWINAX))
12448 bnx2x_verify_sfp_module(phy, params);
12450 lfa_sts = REG_RD(bp, params->lfa_base +
12451 offsetof(struct shmem_lfa,
12454 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12456 /* Re-enable the NIG/MAC */
12457 if (CHIP_IS_E3(bp)) {
12458 if (!dont_clear_stat) {
12459 REG_WR(bp, GRCBASE_MISC +
12460 MISC_REGISTERS_RESET_REG_2_CLEAR,
12461 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12463 REG_WR(bp, GRCBASE_MISC +
12464 MISC_REGISTERS_RESET_REG_2_SET,
12465 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12468 if (vars->line_speed < SPEED_10000)
12469 bnx2x_umac_enable(params, vars, 0);
12471 bnx2x_xmac_enable(params, vars, 0);
12473 if (vars->line_speed < SPEED_10000)
12474 bnx2x_emac_enable(params, vars, 0);
12476 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12479 /* Increment LFA count */
12480 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12481 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12482 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12483 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12484 /* Clear link flap reason */
12485 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12487 REG_WR(bp, params->lfa_base +
12488 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12490 /* Disable NIG DRAIN */
12491 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12493 /* Enable interrupts */
12494 bnx2x_link_int_enable(params);
12498 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12499 struct link_vars *vars,
12502 u32 lfa_sts, cfg_idx, tmp_val;
12503 struct bnx2x *bp = params->bp;
12505 bnx2x_link_reset(params, vars, 1);
12507 if (!params->lfa_base)
12509 /* Store the new link parameters */
12510 REG_WR(bp, params->lfa_base +
12511 offsetof(struct shmem_lfa, req_duplex),
12512 params->req_duplex[0] | (params->req_duplex[1] << 16));
12514 REG_WR(bp, params->lfa_base +
12515 offsetof(struct shmem_lfa, req_flow_ctrl),
12516 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12518 REG_WR(bp, params->lfa_base +
12519 offsetof(struct shmem_lfa, req_line_speed),
12520 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12522 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12523 REG_WR(bp, params->lfa_base +
12524 offsetof(struct shmem_lfa,
12525 speed_cap_mask[cfg_idx]),
12526 params->speed_cap_mask[cfg_idx]);
12529 tmp_val = REG_RD(bp, params->lfa_base +
12530 offsetof(struct shmem_lfa, additional_config));
12531 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12532 tmp_val |= params->req_fc_auto_adv;
12534 REG_WR(bp, params->lfa_base +
12535 offsetof(struct shmem_lfa, additional_config), tmp_val);
12537 lfa_sts = REG_RD(bp, params->lfa_base +
12538 offsetof(struct shmem_lfa, lfa_sts));
12540 /* Clear the "Don't Clear Statistics" bit, and set reason */
12541 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12543 /* Set link flap reason */
12544 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12545 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12546 LFA_LINK_FLAP_REASON_OFFSET);
12548 /* Increment link flap counter */
12549 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12550 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12551 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12552 << LINK_FLAP_COUNT_OFFSET));
12553 REG_WR(bp, params->lfa_base +
12554 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12555 /* Proceed with regular link initialization */
12558 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12561 struct bnx2x *bp = params->bp;
12562 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12563 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12564 params->req_line_speed[0], params->req_flow_ctrl[0]);
12565 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12566 params->req_line_speed[1], params->req_flow_ctrl[1]);
12567 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12568 vars->link_status = 0;
12569 vars->phy_link_up = 0;
12571 vars->line_speed = 0;
12572 vars->duplex = DUPLEX_FULL;
12573 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12574 vars->mac_type = MAC_TYPE_NONE;
12575 vars->phy_flags = 0;
12576 vars->check_kr2_recovery_cnt = 0;
12577 params->link_flags = PHY_INITIALIZED;
12578 /* Driver opens NIG-BRB filters */
12579 bnx2x_set_rx_filter(params, 1);
12580 /* Check if link flap can be avoided */
12581 lfa_status = bnx2x_check_lfa(params);
12583 if (lfa_status == 0) {
12584 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12585 return bnx2x_avoid_link_flap(params, vars);
12588 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12590 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12592 /* Disable attentions */
12593 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12594 (NIG_MASK_XGXS0_LINK_STATUS |
12595 NIG_MASK_XGXS0_LINK10G |
12596 NIG_MASK_SERDES0_LINK_STATUS |
12599 bnx2x_emac_init(params, vars);
12601 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12602 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12604 if (params->num_phys == 0) {
12605 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12608 set_phy_vars(params, vars);
12610 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12611 switch (params->loopback_mode) {
12612 case LOOPBACK_BMAC:
12613 bnx2x_init_bmac_loopback(params, vars);
12615 case LOOPBACK_EMAC:
12616 bnx2x_init_emac_loopback(params, vars);
12618 case LOOPBACK_XMAC:
12619 bnx2x_init_xmac_loopback(params, vars);
12621 case LOOPBACK_UMAC:
12622 bnx2x_init_umac_loopback(params, vars);
12624 case LOOPBACK_XGXS:
12625 case LOOPBACK_EXT_PHY:
12626 bnx2x_init_xgxs_loopback(params, vars);
12629 if (!CHIP_IS_E3(bp)) {
12630 if (params->switch_cfg == SWITCH_CFG_10G)
12631 bnx2x_xgxs_deassert(params);
12633 bnx2x_serdes_deassert(bp, params->port);
12635 bnx2x_link_initialize(params, vars);
12637 bnx2x_link_int_enable(params);
12640 bnx2x_update_mng(params, vars->link_status);
12642 bnx2x_update_mng_eee(params, vars->eee_status);
12646 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12649 struct bnx2x *bp = params->bp;
12650 u8 phy_index, port = params->port, clear_latch_ind = 0;
12651 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12652 /* Disable attentions */
12653 vars->link_status = 0;
12654 bnx2x_update_mng(params, vars->link_status);
12655 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12656 SHMEM_EEE_ACTIVE_BIT);
12657 bnx2x_update_mng_eee(params, vars->eee_status);
12658 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12659 (NIG_MASK_XGXS0_LINK_STATUS |
12660 NIG_MASK_XGXS0_LINK10G |
12661 NIG_MASK_SERDES0_LINK_STATUS |
12664 /* Activate nig drain */
12665 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12667 /* Disable nig egress interface */
12668 if (!CHIP_IS_E3(bp)) {
12669 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12670 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12673 if (!CHIP_IS_E3(bp)) {
12674 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12676 bnx2x_set_xmac_rxtx(params, 0);
12677 bnx2x_set_umac_rxtx(params, 0);
12680 if (!CHIP_IS_E3(bp))
12681 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12683 usleep_range(10000, 20000);
12684 /* The PHY reset is controlled by GPIO 1
12685 * Hold it as vars low
12687 /* Clear link led */
12688 bnx2x_set_mdio_emac_per_phy(bp, params);
12689 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12691 if (reset_ext_phy) {
12692 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12694 if (params->phy[phy_index].link_reset) {
12695 bnx2x_set_aer_mmd(params,
12696 ¶ms->phy[phy_index]);
12697 params->phy[phy_index].link_reset(
12698 ¶ms->phy[phy_index],
12701 if (params->phy[phy_index].flags &
12702 FLAGS_REARM_LATCH_SIGNAL)
12703 clear_latch_ind = 1;
12707 if (clear_latch_ind) {
12708 /* Clear latching indication */
12709 bnx2x_rearm_latch_signal(bp, port, 0);
12710 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12711 1 << NIG_LATCH_BC_ENABLE_MI_INT);
12713 if (params->phy[INT_PHY].link_reset)
12714 params->phy[INT_PHY].link_reset(
12715 ¶ms->phy[INT_PHY], params);
12717 /* Disable nig ingress interface */
12718 if (!CHIP_IS_E3(bp)) {
12720 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12721 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12722 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12723 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12725 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12726 bnx2x_set_xumac_nig(params, 0, 0);
12727 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12728 MISC_REGISTERS_RESET_REG_2_XMAC)
12729 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12730 XMAC_CTRL_REG_SOFT_RESET);
12733 vars->phy_flags = 0;
12736 int bnx2x_lfa_reset(struct link_params *params,
12737 struct link_vars *vars)
12739 struct bnx2x *bp = params->bp;
12741 vars->phy_flags = 0;
12742 params->link_flags &= ~PHY_INITIALIZED;
12743 if (!params->lfa_base)
12744 return bnx2x_link_reset(params, vars, 1);
12746 * Activate NIG drain so that during this time the device won't send
12747 * anything while it is unable to response.
12749 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12752 * Close gracefully the gate from BMAC to NIG such that no half packets
12755 if (!CHIP_IS_E3(bp))
12756 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12758 if (CHIP_IS_E3(bp)) {
12759 bnx2x_set_xmac_rxtx(params, 0);
12760 bnx2x_set_umac_rxtx(params, 0);
12762 /* Wait 10ms for the pipe to clean up*/
12763 usleep_range(10000, 20000);
12765 /* Clean the NIG-BRB using the network filters in a way that will
12766 * not cut a packet in the middle.
12768 bnx2x_set_rx_filter(params, 0);
12771 * Re-open the gate between the BMAC and the NIG, after verifying the
12772 * gate to the BRB is closed, otherwise packets may arrive to the
12773 * firmware before driver had initialized it. The target is to achieve
12774 * minimum management protocol down time.
12776 if (!CHIP_IS_E3(bp))
12777 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12779 if (CHIP_IS_E3(bp)) {
12780 bnx2x_set_xmac_rxtx(params, 1);
12781 bnx2x_set_umac_rxtx(params, 1);
12783 /* Disable NIG drain */
12784 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12788 /****************************************************************************/
12789 /* Common function */
12790 /****************************************************************************/
12791 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12792 u32 shmem_base_path[],
12793 u32 shmem2_base_path[], u8 phy_index,
12796 struct bnx2x_phy phy[PORT_MAX];
12797 struct bnx2x_phy *phy_blk[PORT_MAX];
12800 s8 port_of_path = 0;
12801 u32 swap_val, swap_override;
12802 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12803 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12804 port ^= (swap_val && swap_override);
12805 bnx2x_ext_phy_hw_reset(bp, port);
12806 /* PART1 - Reset both phys */
12807 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12808 u32 shmem_base, shmem2_base;
12809 /* In E2, same phy is using for port0 of the two paths */
12810 if (CHIP_IS_E1x(bp)) {
12811 shmem_base = shmem_base_path[0];
12812 shmem2_base = shmem2_base_path[0];
12813 port_of_path = port;
12815 shmem_base = shmem_base_path[port];
12816 shmem2_base = shmem2_base_path[port];
12820 /* Extract the ext phy address for the port */
12821 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12822 port_of_path, &phy[port]) !=
12824 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12827 /* Disable attentions */
12828 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12830 (NIG_MASK_XGXS0_LINK_STATUS |
12831 NIG_MASK_XGXS0_LINK10G |
12832 NIG_MASK_SERDES0_LINK_STATUS |
12835 /* Need to take the phy out of low power mode in order
12836 * to write to access its registers
12838 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12839 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12842 /* Reset the phy */
12843 bnx2x_cl45_write(bp, &phy[port],
12849 /* Add delay of 150ms after reset */
12852 if (phy[PORT_0].addr & 0x1) {
12853 phy_blk[PORT_0] = &(phy[PORT_1]);
12854 phy_blk[PORT_1] = &(phy[PORT_0]);
12856 phy_blk[PORT_0] = &(phy[PORT_0]);
12857 phy_blk[PORT_1] = &(phy[PORT_1]);
12860 /* PART2 - Download firmware to both phys */
12861 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12862 if (CHIP_IS_E1x(bp))
12863 port_of_path = port;
12867 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12868 phy_blk[port]->addr);
12869 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12873 /* Only set bit 10 = 1 (Tx power down) */
12874 bnx2x_cl45_read(bp, phy_blk[port],
12876 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12878 /* Phase1 of TX_POWER_DOWN reset */
12879 bnx2x_cl45_write(bp, phy_blk[port],
12881 MDIO_PMA_REG_TX_POWER_DOWN,
12885 /* Toggle Transmitter: Power down and then up with 600ms delay
12890 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12891 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12892 /* Phase2 of POWER_DOWN_RESET */
12893 /* Release bit 10 (Release Tx power down) */
12894 bnx2x_cl45_read(bp, phy_blk[port],
12896 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12898 bnx2x_cl45_write(bp, phy_blk[port],
12900 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12901 usleep_range(15000, 30000);
12903 /* Read modify write the SPI-ROM version select register */
12904 bnx2x_cl45_read(bp, phy_blk[port],
12906 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12907 bnx2x_cl45_write(bp, phy_blk[port],
12909 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12911 /* set GPIO2 back to LOW */
12912 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12913 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12917 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12918 u32 shmem_base_path[],
12919 u32 shmem2_base_path[], u8 phy_index,
12924 struct bnx2x_phy phy;
12925 /* Use port1 because of the static port-swap */
12926 /* Enable the module detection interrupt */
12927 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12928 val |= ((1<<MISC_REGISTERS_GPIO_3)|
12929 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12930 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12932 bnx2x_ext_phy_hw_reset(bp, 0);
12933 usleep_range(5000, 10000);
12934 for (port = 0; port < PORT_MAX; port++) {
12935 u32 shmem_base, shmem2_base;
12937 /* In E2, same phy is using for port0 of the two paths */
12938 if (CHIP_IS_E1x(bp)) {
12939 shmem_base = shmem_base_path[0];
12940 shmem2_base = shmem2_base_path[0];
12942 shmem_base = shmem_base_path[port];
12943 shmem2_base = shmem2_base_path[port];
12945 /* Extract the ext phy address for the port */
12946 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12949 DP(NETIF_MSG_LINK, "populate phy failed\n");
12954 bnx2x_cl45_write(bp, &phy,
12955 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12958 /* Set fault module detected LED on */
12959 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12960 MISC_REGISTERS_GPIO_HIGH,
12966 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12967 u8 *io_gpio, u8 *io_port)
12970 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12971 offsetof(struct shmem_region,
12972 dev_info.port_hw_config[PORT_0].default_cfg));
12973 switch (phy_gpio_reset) {
12974 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12978 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12982 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12986 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12990 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12994 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12998 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13002 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13007 /* Don't override the io_gpio and io_port */
13012 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13013 u32 shmem_base_path[],
13014 u32 shmem2_base_path[], u8 phy_index,
13017 s8 port, reset_gpio;
13018 u32 swap_val, swap_override;
13019 struct bnx2x_phy phy[PORT_MAX];
13020 struct bnx2x_phy *phy_blk[PORT_MAX];
13022 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13023 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13025 reset_gpio = MISC_REGISTERS_GPIO_1;
13028 /* Retrieve the reset gpio/port which control the reset.
13029 * Default is GPIO1, PORT1
13031 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13032 (u8 *)&reset_gpio, (u8 *)&port);
13034 /* Calculate the port based on port swap */
13035 port ^= (swap_val && swap_override);
13037 /* Initiate PHY reset*/
13038 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13040 usleep_range(1000, 2000);
13041 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13044 usleep_range(5000, 10000);
13046 /* PART1 - Reset both phys */
13047 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13048 u32 shmem_base, shmem2_base;
13050 /* In E2, same phy is using for port0 of the two paths */
13051 if (CHIP_IS_E1x(bp)) {
13052 shmem_base = shmem_base_path[0];
13053 shmem2_base = shmem2_base_path[0];
13054 port_of_path = port;
13056 shmem_base = shmem_base_path[port];
13057 shmem2_base = shmem2_base_path[port];
13061 /* Extract the ext phy address for the port */
13062 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13063 port_of_path, &phy[port]) !=
13065 DP(NETIF_MSG_LINK, "populate phy failed\n");
13068 /* disable attentions */
13069 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13071 (NIG_MASK_XGXS0_LINK_STATUS |
13072 NIG_MASK_XGXS0_LINK10G |
13073 NIG_MASK_SERDES0_LINK_STATUS |
13077 /* Reset the phy */
13078 bnx2x_cl45_write(bp, &phy[port],
13079 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13082 /* Add delay of 150ms after reset */
13084 if (phy[PORT_0].addr & 0x1) {
13085 phy_blk[PORT_0] = &(phy[PORT_1]);
13086 phy_blk[PORT_1] = &(phy[PORT_0]);
13088 phy_blk[PORT_0] = &(phy[PORT_0]);
13089 phy_blk[PORT_1] = &(phy[PORT_1]);
13091 /* PART2 - Download firmware to both phys */
13092 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13093 if (CHIP_IS_E1x(bp))
13094 port_of_path = port;
13097 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13098 phy_blk[port]->addr);
13099 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13102 /* Disable PHY transmitter output */
13103 bnx2x_cl45_write(bp, phy_blk[port],
13105 MDIO_PMA_REG_TX_DISABLE, 1);
13111 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13112 u32 shmem_base_path[],
13113 u32 shmem2_base_path[],
13118 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13119 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13121 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13122 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13127 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13128 u32 shmem2_base_path[], u8 phy_index,
13129 u32 ext_phy_type, u32 chip_id)
13133 switch (ext_phy_type) {
13134 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13135 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13137 phy_index, chip_id);
13139 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13140 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13141 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13142 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13144 phy_index, chip_id);
13147 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13148 /* GPIO1 affects both ports, so there's need to pull
13149 * it for single port alone
13151 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13153 phy_index, chip_id);
13155 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13156 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13157 /* GPIO3's are linked, and so both need to be toggled
13158 * to obtain required 2us pulse.
13160 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13162 phy_index, chip_id);
13164 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13169 "ext_phy 0x%x common init not required\n",
13175 netdev_err(bp->dev, "Warning: PHY was not initialized,"
13181 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13182 u32 shmem2_base_path[], u32 chip_id)
13187 u32 ext_phy_type, ext_phy_config;
13189 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13190 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13191 DP(NETIF_MSG_LINK, "Begin common phy init\n");
13192 if (CHIP_IS_E3(bp)) {
13194 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13195 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13197 /* Check if common init was already done */
13198 phy_ver = REG_RD(bp, shmem_base_path[0] +
13199 offsetof(struct shmem_region,
13200 port_mb[PORT_0].ext_phy_fw_version));
13202 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13207 /* Read the ext_phy_type for arbitrary port(0) */
13208 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13210 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13211 shmem_base_path[0],
13213 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13214 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13216 phy_index, ext_phy_type,
13222 static void bnx2x_check_over_curr(struct link_params *params,
13223 struct link_vars *vars)
13225 struct bnx2x *bp = params->bp;
13227 u8 port = params->port;
13230 cfg_pin = (REG_RD(bp, params->shmem_base +
13231 offsetof(struct shmem_region,
13232 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13233 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13234 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13236 /* Ignore check if no external input PIN available */
13237 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13241 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13242 netdev_err(bp->dev, "Error: Power fault on Port %d has"
13243 " been detected and the power to "
13244 "that SFP+ module has been removed"
13245 " to prevent failure of the card."
13246 " Please remove the SFP+ module and"
13247 " restart the system to clear this"
13250 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13251 bnx2x_warpcore_power_module(params, 0);
13254 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13257 /* Returns 0 if no change occured since last check; 1 otherwise. */
13258 static u8 bnx2x_analyze_link_error(struct link_params *params,
13259 struct link_vars *vars, u32 status,
13260 u32 phy_flag, u32 link_flag, u8 notify)
13262 struct bnx2x *bp = params->bp;
13263 /* Compare new value with previous value */
13265 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13267 if ((status ^ old_status) == 0)
13270 /* If values differ */
13271 switch (phy_flag) {
13272 case PHY_HALF_OPEN_CONN_FLAG:
13273 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13275 case PHY_SFP_TX_FAULT_FLAG:
13276 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13279 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13281 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13282 old_status, status);
13284 /* a. Update shmem->link_status accordingly
13285 * b. Update link_vars->link_up
13288 vars->link_status &= ~LINK_STATUS_LINK_UP;
13289 vars->link_status |= link_flag;
13291 vars->phy_flags |= phy_flag;
13293 /* activate nig drain */
13294 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13295 /* Set LED mode to off since the PHY doesn't know about these
13298 led_mode = LED_MODE_OFF;
13300 vars->link_status |= LINK_STATUS_LINK_UP;
13301 vars->link_status &= ~link_flag;
13303 vars->phy_flags &= ~phy_flag;
13304 led_mode = LED_MODE_OPER;
13306 /* Clear nig drain */
13307 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13309 bnx2x_sync_link(params, vars);
13310 /* Update the LED according to the link state */
13311 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13313 /* Update link status in the shared memory */
13314 bnx2x_update_mng(params, vars->link_status);
13316 /* C. Trigger General Attention */
13317 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13319 bnx2x_notify_link_changed(bp);
13324 /******************************************************************************
13326 * This function checks for half opened connection change indication.
13327 * When such change occurs, it calls the bnx2x_analyze_link_error
13328 * to check if Remote Fault is set or cleared. Reception of remote fault
13329 * status message in the MAC indicates that the peer's MAC has detected
13330 * a fault, for example, due to break in the TX side of fiber.
13332 ******************************************************************************/
13333 int bnx2x_check_half_open_conn(struct link_params *params,
13334 struct link_vars *vars,
13337 struct bnx2x *bp = params->bp;
13338 u32 lss_status = 0;
13340 /* In case link status is physically up @ 10G do */
13341 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13342 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13345 if (CHIP_IS_E3(bp) &&
13346 (REG_RD(bp, MISC_REG_RESET_REG_2) &
13347 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13348 /* Check E3 XMAC */
13349 /* Note that link speed cannot be queried here, since it may be
13350 * zero while link is down. In case UMAC is active, LSS will
13351 * simply not be set
13353 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13355 /* Clear stick bits (Requires rising edge) */
13356 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13357 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13358 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13359 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13360 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13363 bnx2x_analyze_link_error(params, vars, lss_status,
13364 PHY_HALF_OPEN_CONN_FLAG,
13365 LINK_STATUS_NONE, notify);
13366 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13367 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13368 /* Check E1X / E2 BMAC */
13369 u32 lss_status_reg;
13371 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13372 NIG_REG_INGRESS_BMAC0_MEM;
13373 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
13374 if (CHIP_IS_E2(bp))
13375 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13377 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13379 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13380 lss_status = (wb_data[0] > 0);
13382 bnx2x_analyze_link_error(params, vars, lss_status,
13383 PHY_HALF_OPEN_CONN_FLAG,
13384 LINK_STATUS_NONE, notify);
13388 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13389 struct link_params *params,
13390 struct link_vars *vars)
13392 struct bnx2x *bp = params->bp;
13393 u32 cfg_pin, value = 0;
13394 u8 led_change, port = params->port;
13396 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13397 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13398 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13399 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13400 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13402 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13403 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13407 led_change = bnx2x_analyze_link_error(params, vars, value,
13408 PHY_SFP_TX_FAULT_FLAG,
13409 LINK_STATUS_SFP_TX_FAULT, 1);
13412 /* Change TX_Fault led, set link status for further syncs */
13415 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13416 led_mode = MISC_REGISTERS_GPIO_HIGH;
13417 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13419 led_mode = MISC_REGISTERS_GPIO_LOW;
13420 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13423 /* If module is unapproved, led should be on regardless */
13424 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13425 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13427 bnx2x_set_e3_module_fault_led(params, led_mode);
13431 static void bnx2x_disable_kr2(struct link_params *params,
13432 struct link_vars *vars,
13433 struct bnx2x_phy *phy)
13435 struct bnx2x *bp = params->bp;
13437 static struct bnx2x_reg_set reg_set[] = {
13438 /* Step 1 - Program the TX/RX alignment markers */
13439 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
13440 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
13441 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
13442 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
13443 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
13444 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
13445 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
13446 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
13447 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
13448 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
13449 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
13450 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
13451 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
13452 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
13453 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
13455 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
13457 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
13458 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
13460 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
13461 bnx2x_update_link_attr(params, vars->link_attr_sync);
13463 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
13464 /* Restart AN on leading lane */
13465 bnx2x_warpcore_restart_AN_KR(phy, params);
13468 static void bnx2x_kr2_recovery(struct link_params *params,
13469 struct link_vars *vars,
13470 struct bnx2x_phy *phy)
13472 struct bnx2x *bp = params->bp;
13473 DP(NETIF_MSG_LINK, "KR2 recovery\n");
13474 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13475 bnx2x_warpcore_restart_AN_KR(phy, params);
13478 static void bnx2x_check_kr2_wa(struct link_params *params,
13479 struct link_vars *vars,
13480 struct bnx2x_phy *phy)
13482 struct bnx2x *bp = params->bp;
13483 u16 base_page, next_page, not_kr2_device, lane;
13486 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13487 * Since some switches tend to reinit the AN process and clear the
13488 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13489 * and recovered many times
13491 if (vars->check_kr2_recovery_cnt > 0) {
13492 vars->check_kr2_recovery_cnt--;
13496 sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13498 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13499 bnx2x_kr2_recovery(params, vars, phy);
13500 DP(NETIF_MSG_LINK, "No sigdet\n");
13505 lane = bnx2x_get_warpcore_lane(phy, params);
13506 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13507 MDIO_AER_BLOCK_AER_REG, lane);
13508 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13509 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13510 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13511 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13512 bnx2x_set_aer_mmd(params, phy);
13514 /* CL73 has not begun yet */
13515 if (base_page == 0) {
13516 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13517 bnx2x_kr2_recovery(params, vars, phy);
13518 DP(NETIF_MSG_LINK, "No BP\n");
13523 /* In case NP bit is not set in the BasePage, or it is set,
13524 * but only KX is advertised, declare this link partner as non-KR2
13527 not_kr2_device = (((base_page & 0x8000) == 0) ||
13528 (((base_page & 0x8000) &&
13529 ((next_page & 0xe0) == 0x2))));
13531 /* In case KR2 is already disabled, check if we need to re-enable it */
13532 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13533 if (!not_kr2_device) {
13534 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13536 bnx2x_kr2_recovery(params, vars, phy);
13540 /* KR2 is enabled, but not KR2 device */
13541 if (not_kr2_device) {
13542 /* Disable KR2 on both lanes */
13543 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13544 bnx2x_disable_kr2(params, vars, phy);
13549 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13552 struct bnx2x *bp = params->bp;
13553 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13554 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13555 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]);
13556 if (bnx2x_check_half_open_conn(params, vars, 1) !=
13558 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13563 if (CHIP_IS_E3(bp)) {
13564 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
13565 bnx2x_set_aer_mmd(params, phy);
13566 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13567 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13568 bnx2x_check_kr2_wa(params, vars, phy);
13569 bnx2x_check_over_curr(params, vars);
13570 if (vars->rx_tx_asic_rst)
13571 bnx2x_warpcore_config_runtime(phy, params, vars);
13573 if ((REG_RD(bp, params->shmem_base +
13574 offsetof(struct shmem_region, dev_info.
13575 port_hw_config[params->port].default_cfg))
13576 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13577 PORT_HW_CFG_NET_SERDES_IF_SFI) {
13578 if (bnx2x_is_sfp_module_plugged(phy, params)) {
13579 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13580 } else if (vars->link_status &
13581 LINK_STATUS_SFP_TX_FAULT) {
13582 /* Clean trail, interrupt corrects the leds */
13583 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13584 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13585 /* Update link status in the shared memory */
13586 bnx2x_update_mng(params, vars->link_status);
13592 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13597 u8 phy_index, fan_failure_det_req = 0;
13598 struct bnx2x_phy phy;
13599 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13601 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13604 DP(NETIF_MSG_LINK, "populate phy failed\n");
13607 fan_failure_det_req |= (phy.flags &
13608 FLAGS_FAN_FAILURE_DET_REQ);
13610 return fan_failure_det_req;
13613 void bnx2x_hw_reset_phy(struct link_params *params)
13616 struct bnx2x *bp = params->bp;
13617 bnx2x_update_mng(params, 0);
13618 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13619 (NIG_MASK_XGXS0_LINK_STATUS |
13620 NIG_MASK_XGXS0_LINK10G |
13621 NIG_MASK_SERDES0_LINK_STATUS |
13624 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13626 if (params->phy[phy_index].hw_reset) {
13627 params->phy[phy_index].hw_reset(
13628 ¶ms->phy[phy_index],
13630 params->phy[phy_index] = phy_null;
13635 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13636 u32 chip_id, u32 shmem_base, u32 shmem2_base,
13639 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13641 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13642 if (CHIP_IS_E3(bp)) {
13643 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13650 struct bnx2x_phy phy;
13651 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13653 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13654 shmem2_base, port, &phy)
13656 DP(NETIF_MSG_LINK, "populate phy failed\n");
13659 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13660 gpio_num = MISC_REGISTERS_GPIO_3;
13667 if (gpio_num == 0xff)
13670 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13671 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13673 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13674 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13675 gpio_port ^= (swap_val && swap_override);
13677 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13678 (gpio_num + (gpio_port << 2));
13680 sync_offset = shmem_base +
13681 offsetof(struct shmem_region,
13682 dev_info.port_hw_config[port].aeu_int_mask);
13683 REG_WR(bp, sync_offset, vars->aeu_int_mask);
13685 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13686 gpio_num, gpio_port, vars->aeu_int_mask);
13689 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13691 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13693 /* Open appropriate AEU for interrupts */
13694 aeu_mask = REG_RD(bp, offset);
13695 aeu_mask |= vars->aeu_int_mask;
13696 REG_WR(bp, offset, aeu_mask);
13698 /* Enable the GPIO to trigger interrupt */
13699 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13700 val |= 1 << (gpio_num + (gpio_port << 2));
13701 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);