1 /* Copyright 2008-2012 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
22 /***********************************************************/
24 /***********************************************************/
25 #define DEFAULT_PHY_DEV_ADDR 3
26 #define E2_DEFAULT_PHY_DEV_ADDR 5
30 #define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
31 #define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
32 #define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
33 #define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
34 #define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
36 #define NET_SERDES_IF_XFI 1
37 #define NET_SERDES_IF_SFI 2
38 #define NET_SERDES_IF_KR 3
39 #define NET_SERDES_IF_DXGXS 4
41 #define SPEED_AUTO_NEG 0
42 #define SPEED_20000 20000
44 #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
45 #define SFP_EEPROM_VENDOR_NAME_SIZE 16
46 #define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
47 #define SFP_EEPROM_VENDOR_OUI_SIZE 3
48 #define SFP_EEPROM_PART_NO_ADDR 0x28
49 #define SFP_EEPROM_PART_NO_SIZE 16
50 #define SFP_EEPROM_REVISION_ADDR 0x38
51 #define SFP_EEPROM_REVISION_SIZE 4
52 #define SFP_EEPROM_SERIAL_ADDR 0x44
53 #define SFP_EEPROM_SERIAL_SIZE 16
54 #define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
55 #define SFP_EEPROM_DATE_SIZE 6
56 #define PWR_FLT_ERR_MSG_LEN 250
58 #define XGXS_EXT_PHY_TYPE(ext_phy_config) \
59 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
60 #define XGXS_EXT_PHY_ADDR(ext_phy_config) \
61 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
62 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
63 #define SERDES_EXT_PHY_TYPE(ext_phy_config) \
64 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
66 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
67 #define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
68 /* Single Media board contains single external phy */
69 #define SINGLE_MEDIA(params) (params->num_phys == 2)
70 /* Dual Media board contains two external phy with different media */
71 #define DUAL_MEDIA(params) (params->num_phys == 3)
73 #define FW_PARAM_PHY_ADDR_MASK 0x000000FF
74 #define FW_PARAM_PHY_TYPE_MASK 0x0000FF00
75 #define FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
76 #define FW_PARAM_MDIO_CTRL_OFFSET 16
77 #define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
78 FW_PARAM_PHY_ADDR_MASK)
79 #define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
80 FW_PARAM_PHY_TYPE_MASK)
81 #define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
82 FW_PARAM_MDIO_CTRL_MASK) >> \
83 FW_PARAM_MDIO_CTRL_OFFSET)
84 #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
85 (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
88 #define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
89 #define PFC_BRB_FULL_LB_XON_THRESHOLD 250
91 #define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
93 #define BMAC_CONTROL_RX_ENABLE 2
94 /***********************************************************/
96 /***********************************************************/
102 /* Same configuration is shared between the XGXS and the first external phy */
103 #define LINK_CONFIG_SIZE (MAX_PHYS - 1)
104 #define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
106 /***********************************************************/
107 /* bnx2x_phy struct */
108 /* Defines the required arguments and function per phy */
109 /***********************************************************/
114 typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
115 struct link_vars *vars);
116 typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
117 struct link_vars *vars);
118 typedef void (*link_reset_t)(struct bnx2x_phy *phy,
119 struct link_params *params);
120 typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
121 struct link_params *params);
122 typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
123 typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
124 typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
125 struct link_params *params, u8 mode);
126 typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
127 struct link_params *params, u32 action);
132 /* Loaded during init */
136 /* Require HW lock */
137 #define FLAGS_HW_LOCK_REQUIRED (1<<0)
138 /* No Over-Current detection */
139 #define FLAGS_NOC (1<<1)
140 /* Fan failure detection required */
141 #define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
142 /* Initialize first the XGXS and only then the phy itself */
143 #define FLAGS_INIT_XGXS_FIRST (1<<3)
144 #define FLAGS_WC_DUAL_MODE (1<<4)
145 #define FLAGS_4_PORT_MODE (1<<5)
146 #define FLAGS_REARM_LATCH_SIGNAL (1<<6)
147 #define FLAGS_SFP_NOT_APPROVED (1<<7)
148 #define FLAGS_MDC_MDIO_WA (1<<8)
149 #define FLAGS_DUMMY_READ (1<<9)
150 #define FLAGS_MDC_MDIO_WA_B0 (1<<10)
151 #define FLAGS_TX_ERROR_CHECK (1<<12)
153 /* preemphasis values for the rx side */
154 u16 rx_preemphasis[4];
156 /* preemphasis values for the tx side */
157 u16 tx_preemphasis[4];
159 /* EMAC address for access MDIO */
165 #define ETH_PHY_UNSPECIFIED 0x0
166 #define ETH_PHY_SFP_FIBER 0x1
167 #define ETH_PHY_XFP_FIBER 0x2
168 #define ETH_PHY_DA_TWINAX 0x3
169 #define ETH_PHY_BASE_T 0x4
170 #define ETH_PHY_KR 0xf0
171 #define ETH_PHY_CX4 0xf1
172 #define ETH_PHY_NOT_PRESENT 0xff
174 /* The address in which version is located*/
185 /* Called per phy/port init, and it configures LASI, speed, autoneg,
186 duplex, flow control negotiation, etc. */
187 config_init_t config_init;
189 /* Called due to interrupt. It determines the link, speed */
190 read_status_t read_status;
192 /* Called when driver is unloading. Should reset the phy */
193 link_reset_t link_reset;
195 /* Set the loopback configuration for the phy */
196 config_loopback_t config_loopback;
198 /* Format the given raw number into str up to len */
199 format_fw_ver_t format_fw_ver;
201 /* Reset the phy (both ports) */
204 /* Set link led mode (on/off/oper)*/
205 set_link_led_t set_link_led;
207 /* PHY Specific tasks */
208 phy_specific_func_t phy_specific_func;
213 /* Inputs parameters to the CLC */
218 /* Default / User Configuration */
220 #define LOOPBACK_NONE 0
221 #define LOOPBACK_EMAC 1
222 #define LOOPBACK_BMAC 2
223 #define LOOPBACK_XGXS 3
224 #define LOOPBACK_EXT_PHY 4
225 #define LOOPBACK_EXT 5
226 #define LOOPBACK_UMAC 6
227 #define LOOPBACK_XMAC 7
229 /* Device parameters */
232 u16 req_duplex[LINK_CONFIG_SIZE];
233 u16 req_flow_ctrl[LINK_CONFIG_SIZE];
235 u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
237 /* shmem parameters */
240 u32 speed_cap_mask[LINK_CONFIG_SIZE];
242 #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
243 #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
244 #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
248 /* Phy register parameter */
252 u32 feature_config_flags;
253 #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
254 #define FEATURE_CONFIG_PFC_ENABLED (1<<1)
255 #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
256 #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
257 #define FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
258 #define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
259 #define FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
260 /* Will be populated during common init */
261 struct bnx2x_phy phy[MAX_PHYS];
263 /* Will be populated during common init */
267 u16 hw_led_mode; /* part of the hw_config read from the shmem */
268 u32 multi_phy_config;
270 /* Device pointer passed to all callback functions */
272 u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
273 req_flow_ctrl is set to AUTO */
276 /* Output parameters */
279 #define PHY_XGXS_FLAG (1<<0)
280 #define PHY_SGMII_FLAG (1<<1)
281 #define PHY_PHYSICAL_LINK_FLAG (1<<2)
282 #define PHY_HALF_OPEN_CONN_FLAG (1<<3)
283 #define PHY_OVER_CURRENT_FLAG (1<<4)
286 #define MAC_TYPE_NONE 0
287 #define MAC_TYPE_EMAC 1
288 #define MAC_TYPE_BMAC 2
289 #define MAC_TYPE_UMAC 3
290 #define MAC_TYPE_XMAC 4
292 u8 phy_link_up; /* internal phy link indication */
301 /* The same definitions as the shmem parameter */
306 #define PERIODIC_FLAGS_LINK_EVENT 0x0001
310 u8 turn_to_run_wc_rt;
314 /***********************************************************/
316 /***********************************************************/
317 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);
319 /* Reset the link. Should be called when driver or interface goes down
320 Before calling phy firmware upgrade, the reset_ext_phy should be set
322 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
325 /* bnx2x_link_update should be called upon link interrupt */
326 int bnx2x_link_update(struct link_params *params, struct link_vars *vars);
328 /* use the following phy functions to read/write from external_phy
329 In order to use it to read/write internal phy registers, use
330 DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
332 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
333 u8 devad, u16 reg, u16 *ret_val);
335 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
336 u8 devad, u16 reg, u16 val);
338 /* Reads the link_status from the shmem,
339 and update the link vars accordingly */
340 void bnx2x_link_status_update(struct link_params *input,
341 struct link_vars *output);
342 /* returns string representing the fw_version of the external phy */
343 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
347 Basically, the CLC takes care of the led for the link, but in case one needs
348 to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
349 blink the led, and LED_MODE_OFF to set the led off.*/
350 int bnx2x_set_led(struct link_params *params,
351 struct link_vars *vars, u8 mode, u32 speed);
352 #define LED_MODE_OFF 0
353 #define LED_MODE_ON 1
354 #define LED_MODE_OPER 2
355 #define LED_MODE_FRONT_PANEL_OFF 3
357 /* bnx2x_handle_module_detect_int should be called upon module detection
359 void bnx2x_handle_module_detect_int(struct link_params *params);
361 /* Get the actual link status. In case it returns 0, link is up,
362 otherwise link is down*/
363 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
366 /* One-time initialization for external phy after power up */
367 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
368 u32 shmem2_base_path[], u32 chip_id);
370 /* Reset the external PHY using GPIO */
371 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
373 /* Reset the external of SFX7101 */
374 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
376 /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
377 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
378 struct link_params *params, u16 addr,
379 u8 byte_cnt, u8 *o_buf);
381 void bnx2x_hw_reset_phy(struct link_params *params);
383 /* Checks if HW lock is required for this phy/board type */
384 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
387 /* Check swap bit and adjust PHY order */
388 u32 bnx2x_phy_selection(struct link_params *params);
390 /* Probe the phys on board, and populate them in "params" */
391 int bnx2x_phy_probe(struct link_params *params);
393 /* Checks if fan failure detection is required on one of the phys on board */
394 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
395 u32 shmem2_base, u8 port);
401 /* Number of maximum COS per chip */
402 #define DCBX_E2E3_MAX_NUM_COS (2)
403 #define DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
404 #define DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
405 #define DCBX_E3B0_MAX_NUM_COS ( \
406 MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
407 DCBX_E3B0_MAX_NUM_COS_PORT1))
409 #define DCBX_MAX_NUM_COS ( \
410 MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
411 DCBX_E2E3_MAX_NUM_COS))
413 /* PFC port configuration params */
414 struct bnx2x_nig_brb_pfc_port_params {
419 u32 pkt_priority_to_cos;
420 u8 num_of_rx_cos_priority_mask;
421 u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
422 u32 llfc_high_priority_classes;
423 u32 llfc_low_priority_classes;
430 /* ETS port configuration params */
431 struct bnx2x_ets_bw_params {
435 struct bnx2x_ets_sp_params {
437 * valid values are 0 - 5. 0 is highest strict priority.
438 * There can't be two COS's with the same pri.
443 enum bnx2x_cos_state {
444 bnx2x_cos_state_strict = 0,
445 bnx2x_cos_state_bw = 1,
448 struct bnx2x_ets_cos_params {
449 enum bnx2x_cos_state state ;
451 struct bnx2x_ets_bw_params bw_params;
452 struct bnx2x_ets_sp_params sp_params;
456 struct bnx2x_ets_params {
457 u8 num_of_cos; /* Number of valid COS entries*/
458 struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS];
462 * Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
463 * when link is already up
465 int bnx2x_update_pfc(struct link_params *params,
466 struct link_vars *vars,
467 struct bnx2x_nig_brb_pfc_port_params *pfc_params);
470 /* Used to configure the ETS to disable */
471 int bnx2x_ets_disabled(struct link_params *params,
472 struct link_vars *vars);
474 /* Used to configure the ETS to BW limited */
475 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
478 /* Used to configure the ETS to strict */
479 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
482 /* Configure the COS to ETS according to BW and SP settings.*/
483 int bnx2x_ets_e3b0_config(const struct link_params *params,
484 const struct link_vars *vars,
485 struct bnx2x_ets_params *ets_params);
486 /* Read pfc statistic*/
487 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
488 u32 pfc_frames_sent[2],
489 u32 pfc_frames_received[2]);
490 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
491 u32 chip_id, u32 shmem_base, u32 shmem2_base,
494 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
495 struct link_params *params);
497 void bnx2x_period_func(struct link_params *params, struct link_vars *vars);
499 int bnx2x_check_half_open_conn(struct link_params *params,
500 struct link_vars *vars, u8 notify);
501 #endif /* BNX2X_LINK_H */