1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
77 /* Time in jiffies before concluding the transmitter is hung */
78 #define TX_TIMEOUT (5*HZ)
80 static char version[] __devinitdata =
81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
82 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
84 MODULE_AUTHOR("Eliezer Tamir");
85 MODULE_DESCRIPTION("Broadcom NetXtreme II "
86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver");
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(DRV_MODULE_VERSION);
91 MODULE_FIRMWARE(FW_FILE_NAME_E1);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
93 MODULE_FIRMWARE(FW_FILE_NAME_E2);
97 module_param(num_queues, int, 0);
98 MODULE_PARM_DESC(num_queues,
99 " Set number of queues (default is as a number of CPUs)");
101 static int disable_tpa;
102 module_param(disable_tpa, int, 0);
103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
105 #define INT_MODE_INTx 1
106 #define INT_MODE_MSI 2
108 module_param(int_mode, int, 0);
109 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
112 static int dropless_fc;
113 module_param(dropless_fc, int, 0);
114 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
116 static int mrrs = -1;
117 module_param(mrrs, int, 0);
118 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
121 module_param(debug, int, 0);
122 MODULE_PARM_DESC(debug, " Default debug msglevel");
126 struct workqueue_struct *bnx2x_wq;
128 enum bnx2x_board_type {
144 /* indexed by board_type, above */
147 } board_info[] __devinitdata = {
148 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
149 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
150 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
151 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
152 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
153 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
154 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
155 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
156 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
157 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
159 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"},
160 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"},
163 #ifndef PCI_DEVICE_ID_NX2_57710
164 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
166 #ifndef PCI_DEVICE_ID_NX2_57711
167 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
169 #ifndef PCI_DEVICE_ID_NX2_57711E
170 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
172 #ifndef PCI_DEVICE_ID_NX2_57712
173 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
175 #ifndef PCI_DEVICE_ID_NX2_57712_MF
176 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
178 #ifndef PCI_DEVICE_ID_NX2_57800
179 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
181 #ifndef PCI_DEVICE_ID_NX2_57800_MF
182 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
184 #ifndef PCI_DEVICE_ID_NX2_57810
185 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
187 #ifndef PCI_DEVICE_ID_NX2_57810_MF
188 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
190 #ifndef PCI_DEVICE_ID_NX2_57840
191 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
193 #ifndef PCI_DEVICE_ID_NX2_57840_MF
194 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
196 #ifndef PCI_DEVICE_ID_NX2_57811
197 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
199 #ifndef PCI_DEVICE_ID_NX2_57811_MF
200 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
202 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
210 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
211 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
212 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
213 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
214 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
215 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
219 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
221 /* Global resources for unloading a previously loaded device */
222 #define BNX2X_PREV_WAIT_NEEDED 1
223 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
224 static LIST_HEAD(bnx2x_prev_list);
225 /****************************************************************************
226 * General service functions
227 ****************************************************************************/
229 static void __storm_memset_dma_mapping(struct bnx2x *bp,
230 u32 addr, dma_addr_t mapping)
232 REG_WR(bp, addr, U64_LO(mapping));
233 REG_WR(bp, addr + 4, U64_HI(mapping));
236 static void storm_memset_spq_addr(struct bnx2x *bp,
237 dma_addr_t mapping, u16 abs_fid)
239 u32 addr = XSEM_REG_FAST_MEMORY +
240 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
242 __storm_memset_dma_mapping(bp, addr, mapping);
245 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
248 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
250 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
252 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
254 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
258 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
261 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
263 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
265 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
267 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
271 static void storm_memset_eq_data(struct bnx2x *bp,
272 struct event_ring_data *eq_data,
275 size_t size = sizeof(struct event_ring_data);
277 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
279 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
282 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
285 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
286 REG_WR16(bp, addr, eq_prod);
290 * locking is done by mcp
292 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
294 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
295 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
296 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
297 PCICFG_VENDOR_ID_OFFSET);
300 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
304 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
305 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
306 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
307 PCICFG_VENDOR_ID_OFFSET);
312 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
313 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
314 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
315 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
316 #define DMAE_DP_DST_NONE "dst_addr [none]"
319 /* copy command into DMAE command memory and set DMAE command go */
320 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
325 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
326 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
327 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
329 REG_WR(bp, dmae_reg_go_c[idx], 1);
332 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
334 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
338 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
340 return opcode & ~DMAE_CMD_SRC_RESET;
343 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
344 bool with_comp, u8 comp_type)
348 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
349 (dst_type << DMAE_COMMAND_DST_SHIFT));
351 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
353 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
354 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
355 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
356 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
359 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
361 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
364 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
368 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
369 struct dmae_command *dmae,
370 u8 src_type, u8 dst_type)
372 memset(dmae, 0, sizeof(struct dmae_command));
375 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
376 true, DMAE_COMP_PCI);
378 /* fill in the completion parameters */
379 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
380 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
381 dmae->comp_val = DMAE_COMP_VAL;
384 /* issue a dmae command over the init-channel and wailt for completion */
385 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
386 struct dmae_command *dmae)
388 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
389 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
393 * Lock the dmae channel. Disable BHs to prevent a dead-lock
394 * as long as this code is called both from syscall context and
395 * from ndo_set_rx_mode() flow that may be called from BH.
397 spin_lock_bh(&bp->dmae_lock);
399 /* reset completion */
402 /* post the command on the channel used for initializations */
403 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
405 /* wait for completion */
407 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
410 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
411 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
412 BNX2X_ERR("DMAE timeout!\n");
419 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
420 BNX2X_ERR("DMAE PCI error!\n");
425 spin_unlock_bh(&bp->dmae_lock);
429 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
432 struct dmae_command dmae;
434 if (!bp->dmae_ready) {
435 u32 *data = bnx2x_sp(bp, wb_data[0]);
438 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
440 bnx2x_init_str_wr(bp, dst_addr, data, len32);
444 /* set opcode and fixed command fields */
445 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
447 /* fill in addresses and len */
448 dmae.src_addr_lo = U64_LO(dma_addr);
449 dmae.src_addr_hi = U64_HI(dma_addr);
450 dmae.dst_addr_lo = dst_addr >> 2;
451 dmae.dst_addr_hi = 0;
454 /* issue the command and wait for completion */
455 bnx2x_issue_dmae_with_comp(bp, &dmae);
458 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
460 struct dmae_command dmae;
462 if (!bp->dmae_ready) {
463 u32 *data = bnx2x_sp(bp, wb_data[0]);
467 for (i = 0; i < len32; i++)
468 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
470 for (i = 0; i < len32; i++)
471 data[i] = REG_RD(bp, src_addr + i*4);
476 /* set opcode and fixed command fields */
477 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
479 /* fill in addresses and len */
480 dmae.src_addr_lo = src_addr >> 2;
481 dmae.src_addr_hi = 0;
482 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
483 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
486 /* issue the command and wait for completion */
487 bnx2x_issue_dmae_with_comp(bp, &dmae);
490 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
493 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
496 while (len > dmae_wr_max) {
497 bnx2x_write_dmae(bp, phys_addr + offset,
498 addr + offset, dmae_wr_max);
499 offset += dmae_wr_max * 4;
503 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
506 static int bnx2x_mc_assert(struct bnx2x *bp)
510 u32 row0, row1, row2, row3;
513 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
514 XSTORM_ASSERT_LIST_INDEX_OFFSET);
516 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
518 /* print the asserts */
519 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
521 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
522 XSTORM_ASSERT_LIST_OFFSET(i));
523 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
524 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
525 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
526 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
527 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
528 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
530 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
531 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
532 i, row3, row2, row1, row0);
540 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
541 TSTORM_ASSERT_LIST_INDEX_OFFSET);
543 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
545 /* print the asserts */
546 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
548 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
549 TSTORM_ASSERT_LIST_OFFSET(i));
550 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
551 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
552 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
553 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
554 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
555 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
557 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
558 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
559 i, row3, row2, row1, row0);
567 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
568 CSTORM_ASSERT_LIST_INDEX_OFFSET);
570 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
572 /* print the asserts */
573 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
575 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
576 CSTORM_ASSERT_LIST_OFFSET(i));
577 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
578 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
579 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
580 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
581 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
582 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
584 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
585 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
586 i, row3, row2, row1, row0);
594 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
595 USTORM_ASSERT_LIST_INDEX_OFFSET);
597 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
599 /* print the asserts */
600 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
602 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
603 USTORM_ASSERT_LIST_OFFSET(i));
604 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
605 USTORM_ASSERT_LIST_OFFSET(i) + 4);
606 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
607 USTORM_ASSERT_LIST_OFFSET(i) + 8);
608 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
609 USTORM_ASSERT_LIST_OFFSET(i) + 12);
611 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
612 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
613 i, row3, row2, row1, row0);
623 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
629 u32 trace_shmem_base;
631 BNX2X_ERR("NO MCP - can not dump\n");
634 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
635 (bp->common.bc_ver & 0xff0000) >> 16,
636 (bp->common.bc_ver & 0xff00) >> 8,
637 (bp->common.bc_ver & 0xff));
639 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
640 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
641 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
643 if (BP_PATH(bp) == 0)
644 trace_shmem_base = bp->common.shmem_base;
646 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
647 addr = trace_shmem_base - 0x800;
649 /* validate TRCB signature */
650 mark = REG_RD(bp, addr);
651 if (mark != MFW_TRACE_SIGNATURE) {
652 BNX2X_ERR("Trace buffer signature is missing.");
656 /* read cyclic buffer pointer */
658 mark = REG_RD(bp, addr);
659 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
660 + ((mark + 0x3) & ~0x3) - 0x08000000;
661 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
664 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
665 for (word = 0; word < 8; word++)
666 data[word] = htonl(REG_RD(bp, offset + 4*word));
668 pr_cont("%s", (char *)data);
670 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
671 for (word = 0; word < 8; word++)
672 data[word] = htonl(REG_RD(bp, offset + 4*word));
674 pr_cont("%s", (char *)data);
676 printk("%s" "end of fw dump\n", lvl);
679 static void bnx2x_fw_dump(struct bnx2x *bp)
681 bnx2x_fw_dump_lvl(bp, KERN_ERR);
684 void bnx2x_panic_dump(struct bnx2x *bp)
688 struct hc_sp_status_block_data sp_sb_data;
689 int func = BP_FUNC(bp);
690 #ifdef BNX2X_STOP_ON_ERROR
691 u16 start = 0, end = 0;
695 bp->stats_state = STATS_STATE_DISABLED;
696 bp->eth_stats.unrecoverable_error++;
697 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
699 BNX2X_ERR("begin crash dump -----------------\n");
703 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
704 bp->def_idx, bp->def_att_idx, bp->attn_state,
705 bp->spq_prod_idx, bp->stats_counter);
706 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
707 bp->def_status_blk->atten_status_block.attn_bits,
708 bp->def_status_blk->atten_status_block.attn_bits_ack,
709 bp->def_status_blk->atten_status_block.status_block_id,
710 bp->def_status_blk->atten_status_block.attn_bits_index);
712 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
714 bp->def_status_blk->sp_sb.index_values[i],
715 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
717 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
718 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
719 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
722 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
723 sp_sb_data.igu_sb_id,
724 sp_sb_data.igu_seg_id,
725 sp_sb_data.p_func.pf_id,
726 sp_sb_data.p_func.vnic_id,
727 sp_sb_data.p_func.vf_id,
728 sp_sb_data.p_func.vf_valid,
732 for_each_eth_queue(bp, i) {
733 struct bnx2x_fastpath *fp = &bp->fp[i];
735 struct hc_status_block_data_e2 sb_data_e2;
736 struct hc_status_block_data_e1x sb_data_e1x;
737 struct hc_status_block_sm *hc_sm_p =
739 sb_data_e1x.common.state_machine :
740 sb_data_e2.common.state_machine;
741 struct hc_index_data *hc_index_p =
743 sb_data_e1x.index_data :
744 sb_data_e2.index_data;
747 struct bnx2x_fp_txdata txdata;
750 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
751 i, fp->rx_bd_prod, fp->rx_bd_cons,
753 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
754 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
755 fp->rx_sge_prod, fp->last_max_sge,
756 le16_to_cpu(fp->fp_hc_idx));
759 for_each_cos_in_tx_queue(fp, cos)
761 txdata = *fp->txdata_ptr[cos];
762 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
763 i, txdata.tx_pkt_prod,
764 txdata.tx_pkt_cons, txdata.tx_bd_prod,
766 le16_to_cpu(*txdata.tx_cons_sb));
769 loop = CHIP_IS_E1x(bp) ?
770 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
778 BNX2X_ERR(" run indexes (");
779 for (j = 0; j < HC_SB_MAX_SM; j++)
781 fp->sb_running_index[j],
782 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
784 BNX2X_ERR(" indexes (");
785 for (j = 0; j < loop; j++)
787 fp->sb_index_values[j],
788 (j == loop - 1) ? ")" : " ");
790 data_size = CHIP_IS_E1x(bp) ?
791 sizeof(struct hc_status_block_data_e1x) :
792 sizeof(struct hc_status_block_data_e2);
793 data_size /= sizeof(u32);
794 sb_data_p = CHIP_IS_E1x(bp) ?
795 (u32 *)&sb_data_e1x :
797 /* copy sb data in here */
798 for (j = 0; j < data_size; j++)
799 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
800 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
803 if (!CHIP_IS_E1x(bp)) {
804 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
805 sb_data_e2.common.p_func.pf_id,
806 sb_data_e2.common.p_func.vf_id,
807 sb_data_e2.common.p_func.vf_valid,
808 sb_data_e2.common.p_func.vnic_id,
809 sb_data_e2.common.same_igu_sb_1b,
810 sb_data_e2.common.state);
812 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
813 sb_data_e1x.common.p_func.pf_id,
814 sb_data_e1x.common.p_func.vf_id,
815 sb_data_e1x.common.p_func.vf_valid,
816 sb_data_e1x.common.p_func.vnic_id,
817 sb_data_e1x.common.same_igu_sb_1b,
818 sb_data_e1x.common.state);
822 for (j = 0; j < HC_SB_MAX_SM; j++) {
823 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
824 j, hc_sm_p[j].__flags,
825 hc_sm_p[j].igu_sb_id,
826 hc_sm_p[j].igu_seg_id,
827 hc_sm_p[j].time_to_expire,
828 hc_sm_p[j].timer_value);
832 for (j = 0; j < loop; j++) {
833 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
835 hc_index_p[j].timeout);
839 #ifdef BNX2X_STOP_ON_ERROR
842 for_each_rx_queue(bp, i) {
843 struct bnx2x_fastpath *fp = &bp->fp[i];
845 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
846 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
847 for (j = start; j != end; j = RX_BD(j + 1)) {
848 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
849 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
851 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
852 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
855 start = RX_SGE(fp->rx_sge_prod);
856 end = RX_SGE(fp->last_max_sge);
857 for (j = start; j != end; j = RX_SGE(j + 1)) {
858 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
859 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
861 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
862 i, j, rx_sge[1], rx_sge[0], sw_page->page);
865 start = RCQ_BD(fp->rx_comp_cons - 10);
866 end = RCQ_BD(fp->rx_comp_cons + 503);
867 for (j = start; j != end; j = RCQ_BD(j + 1)) {
868 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
870 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
871 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
876 for_each_tx_queue(bp, i) {
877 struct bnx2x_fastpath *fp = &bp->fp[i];
878 for_each_cos_in_tx_queue(fp, cos) {
879 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
881 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
882 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
883 for (j = start; j != end; j = TX_BD(j + 1)) {
884 struct sw_tx_bd *sw_bd =
885 &txdata->tx_buf_ring[j];
887 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
888 i, cos, j, sw_bd->skb,
892 start = TX_BD(txdata->tx_bd_cons - 10);
893 end = TX_BD(txdata->tx_bd_cons + 254);
894 for (j = start; j != end; j = TX_BD(j + 1)) {
895 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
897 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
898 i, cos, j, tx_bd[0], tx_bd[1],
906 BNX2X_ERR("end crash dump -----------------\n");
912 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
915 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
916 #define FLR_WAIT_INTERVAL 50 /* usec */
917 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
919 struct pbf_pN_buf_regs {
926 struct pbf_pN_cmd_regs {
932 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
933 struct pbf_pN_buf_regs *regs,
936 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
937 u32 cur_cnt = poll_count;
939 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
940 crd = crd_start = REG_RD(bp, regs->crd);
941 init_crd = REG_RD(bp, regs->init_crd);
943 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
944 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
945 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
947 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
948 (init_crd - crd_start))) {
950 udelay(FLR_WAIT_INTERVAL);
951 crd = REG_RD(bp, regs->crd);
952 crd_freed = REG_RD(bp, regs->crd_freed);
954 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
956 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
958 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
959 regs->pN, crd_freed);
963 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
964 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
967 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
968 struct pbf_pN_cmd_regs *regs,
971 u32 occup, to_free, freed, freed_start;
972 u32 cur_cnt = poll_count;
974 occup = to_free = REG_RD(bp, regs->lines_occup);
975 freed = freed_start = REG_RD(bp, regs->lines_freed);
977 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
978 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
980 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
982 udelay(FLR_WAIT_INTERVAL);
983 occup = REG_RD(bp, regs->lines_occup);
984 freed = REG_RD(bp, regs->lines_freed);
986 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
988 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
990 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
995 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
996 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
999 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1000 u32 expected, u32 poll_count)
1002 u32 cur_cnt = poll_count;
1005 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1006 udelay(FLR_WAIT_INTERVAL);
1011 static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1012 char *msg, u32 poll_cnt)
1014 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1016 BNX2X_ERR("%s usage count=%d\n", msg, val);
1022 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1024 /* adjust polling timeout */
1025 if (CHIP_REV_IS_EMUL(bp))
1026 return FLR_POLL_CNT * 2000;
1028 if (CHIP_REV_IS_FPGA(bp))
1029 return FLR_POLL_CNT * 120;
1031 return FLR_POLL_CNT;
1034 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1036 struct pbf_pN_cmd_regs cmd_regs[] = {
1037 {0, (CHIP_IS_E3B0(bp)) ?
1038 PBF_REG_TQ_OCCUPANCY_Q0 :
1039 PBF_REG_P0_TQ_OCCUPANCY,
1040 (CHIP_IS_E3B0(bp)) ?
1041 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1042 PBF_REG_P0_TQ_LINES_FREED_CNT},
1043 {1, (CHIP_IS_E3B0(bp)) ?
1044 PBF_REG_TQ_OCCUPANCY_Q1 :
1045 PBF_REG_P1_TQ_OCCUPANCY,
1046 (CHIP_IS_E3B0(bp)) ?
1047 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1048 PBF_REG_P1_TQ_LINES_FREED_CNT},
1049 {4, (CHIP_IS_E3B0(bp)) ?
1050 PBF_REG_TQ_OCCUPANCY_LB_Q :
1051 PBF_REG_P4_TQ_OCCUPANCY,
1052 (CHIP_IS_E3B0(bp)) ?
1053 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1054 PBF_REG_P4_TQ_LINES_FREED_CNT}
1057 struct pbf_pN_buf_regs buf_regs[] = {
1058 {0, (CHIP_IS_E3B0(bp)) ?
1059 PBF_REG_INIT_CRD_Q0 :
1060 PBF_REG_P0_INIT_CRD ,
1061 (CHIP_IS_E3B0(bp)) ?
1064 (CHIP_IS_E3B0(bp)) ?
1065 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1066 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1067 {1, (CHIP_IS_E3B0(bp)) ?
1068 PBF_REG_INIT_CRD_Q1 :
1069 PBF_REG_P1_INIT_CRD,
1070 (CHIP_IS_E3B0(bp)) ?
1073 (CHIP_IS_E3B0(bp)) ?
1074 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1075 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1076 {4, (CHIP_IS_E3B0(bp)) ?
1077 PBF_REG_INIT_CRD_LB_Q :
1078 PBF_REG_P4_INIT_CRD,
1079 (CHIP_IS_E3B0(bp)) ?
1080 PBF_REG_CREDIT_LB_Q :
1082 (CHIP_IS_E3B0(bp)) ?
1083 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1084 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1089 /* Verify the command queues are flushed P0, P1, P4 */
1090 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1091 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1094 /* Verify the transmission buffers are flushed P0, P1, P4 */
1095 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1096 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1099 #define OP_GEN_PARAM(param) \
1100 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1102 #define OP_GEN_TYPE(type) \
1103 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1105 #define OP_GEN_AGG_VECT(index) \
1106 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1109 static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1112 struct sdm_op_gen op_gen = {0};
1114 u32 comp_addr = BAR_CSTRORM_INTMEM +
1115 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1118 if (REG_RD(bp, comp_addr)) {
1119 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1123 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1124 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1125 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1126 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1128 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1129 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1131 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1132 BNX2X_ERR("FW final cleanup did not succeed\n");
1133 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1134 (REG_RD(bp, comp_addr)));
1137 /* Zero completion for nxt FLR */
1138 REG_WR(bp, comp_addr, 0);
1143 static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1148 pos = pci_pcie_cap(dev);
1152 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1153 return status & PCI_EXP_DEVSTA_TRPND;
1156 /* PF FLR specific routines
1158 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1161 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1162 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1163 CFC_REG_NUM_LCIDS_INSIDE_PF,
1164 "CFC PF usage counter timed out",
1169 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1170 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1171 DORQ_REG_PF_USAGE_CNT,
1172 "DQ PF usage counter timed out",
1176 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1177 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1178 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1179 "QM PF usage counter timed out",
1183 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1184 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1185 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1186 "Timers VNIC usage counter timed out",
1189 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1190 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1191 "Timers NUM_SCANS usage counter timed out",
1195 /* Wait DMAE PF usage counter to zero */
1196 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1197 dmae_reg_go_c[INIT_DMAE_C(bp)],
1198 "DMAE dommand register timed out",
1205 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1209 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1210 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1212 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1213 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1215 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1216 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1218 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1219 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1221 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1222 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1224 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1225 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1227 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1228 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1230 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1231 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1235 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1237 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1239 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1241 /* Re-enable PF target read access */
1242 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1244 /* Poll HW usage counters */
1245 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1246 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1249 /* Zero the igu 'trailing edge' and 'leading edge' */
1251 /* Send the FW cleanup command */
1252 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1257 /* Verify TX hw is flushed */
1258 bnx2x_tx_hw_flushed(bp, poll_cnt);
1260 /* Wait 100ms (not adjusted according to platform) */
1263 /* Verify no pending pci transactions */
1264 if (bnx2x_is_pcie_pending(bp->pdev))
1265 BNX2X_ERR("PCIE Transactions still pending\n");
1268 bnx2x_hw_enable_status(bp);
1271 * Master enable - Due to WB DMAE writes performed before this
1272 * register is re-initialized as part of the regular function init
1274 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1279 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1281 int port = BP_PORT(bp);
1282 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1283 u32 val = REG_RD(bp, addr);
1284 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1285 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1286 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1289 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1290 HC_CONFIG_0_REG_INT_LINE_EN_0);
1291 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1292 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1294 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1296 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1297 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1298 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1299 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1301 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1302 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1303 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1304 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1306 if (!CHIP_IS_E1(bp)) {
1308 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1310 REG_WR(bp, addr, val);
1312 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1317 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1320 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1321 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1323 REG_WR(bp, addr, val);
1325 * Ensure that HC_CONFIG is written before leading/trailing edge config
1330 if (!CHIP_IS_E1(bp)) {
1331 /* init leading/trailing edge */
1333 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1335 /* enable nig and gpio3 attention */
1340 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1341 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1344 /* Make sure that interrupts are indeed enabled from here on */
1348 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1351 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1352 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1353 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1355 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1358 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1359 IGU_PF_CONF_SINGLE_ISR_EN);
1360 val |= (IGU_PF_CONF_FUNC_EN |
1361 IGU_PF_CONF_MSI_MSIX_EN |
1362 IGU_PF_CONF_ATTN_BIT_EN);
1365 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1367 val &= ~IGU_PF_CONF_INT_LINE_EN;
1368 val |= (IGU_PF_CONF_FUNC_EN |
1369 IGU_PF_CONF_MSI_MSIX_EN |
1370 IGU_PF_CONF_ATTN_BIT_EN |
1371 IGU_PF_CONF_SINGLE_ISR_EN);
1373 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1374 val |= (IGU_PF_CONF_FUNC_EN |
1375 IGU_PF_CONF_INT_LINE_EN |
1376 IGU_PF_CONF_ATTN_BIT_EN |
1377 IGU_PF_CONF_SINGLE_ISR_EN);
1380 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1381 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1383 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1385 if (val & IGU_PF_CONF_INT_LINE_EN)
1386 pci_intx(bp->pdev, true);
1390 /* init leading/trailing edge */
1392 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1394 /* enable nig and gpio3 attention */
1399 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1400 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1402 /* Make sure that interrupts are indeed enabled from here on */
1406 void bnx2x_int_enable(struct bnx2x *bp)
1408 if (bp->common.int_block == INT_BLOCK_HC)
1409 bnx2x_hc_int_enable(bp);
1411 bnx2x_igu_int_enable(bp);
1414 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1416 int port = BP_PORT(bp);
1417 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1418 u32 val = REG_RD(bp, addr);
1421 * in E1 we must use only PCI configuration space to disable
1422 * MSI/MSIX capablility
1423 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1425 if (CHIP_IS_E1(bp)) {
1426 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1427 * Use mask register to prevent from HC sending interrupts
1428 * after we exit the function
1430 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1432 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1433 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1434 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1436 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1437 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1438 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1439 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1441 DP(NETIF_MSG_IFDOWN,
1442 "write %x to HC %d (addr 0x%x)\n",
1445 /* flush all outstanding writes */
1448 REG_WR(bp, addr, val);
1449 if (REG_RD(bp, addr) != val)
1450 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1453 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1455 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1457 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1458 IGU_PF_CONF_INT_LINE_EN |
1459 IGU_PF_CONF_ATTN_BIT_EN);
1461 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1463 /* flush all outstanding writes */
1466 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1467 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1468 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1471 void bnx2x_int_disable(struct bnx2x *bp)
1473 if (bp->common.int_block == INT_BLOCK_HC)
1474 bnx2x_hc_int_disable(bp);
1476 bnx2x_igu_int_disable(bp);
1479 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1481 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1485 /* prevent the HW from sending interrupts */
1486 bnx2x_int_disable(bp);
1488 /* make sure all ISRs are done */
1490 synchronize_irq(bp->msix_table[0].vector);
1495 for_each_eth_queue(bp, i)
1496 synchronize_irq(bp->msix_table[offset++].vector);
1498 synchronize_irq(bp->pdev->irq);
1500 /* make sure sp_task is not running */
1501 cancel_delayed_work(&bp->sp_task);
1502 cancel_delayed_work(&bp->period_task);
1503 flush_workqueue(bnx2x_wq);
1509 * General service functions
1512 /* Return true if succeeded to acquire the lock */
1513 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1516 u32 resource_bit = (1 << resource);
1517 int func = BP_FUNC(bp);
1518 u32 hw_lock_control_reg;
1520 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1521 "Trying to take a lock on resource %d\n", resource);
1523 /* Validating that the resource is within range */
1524 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1525 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1526 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1527 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1532 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1534 hw_lock_control_reg =
1535 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1537 /* Try to acquire the lock */
1538 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1539 lock_status = REG_RD(bp, hw_lock_control_reg);
1540 if (lock_status & resource_bit)
1543 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1544 "Failed to get a lock on resource %d\n", resource);
1549 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1551 * @bp: driver handle
1553 * Returns the recovery leader resource id according to the engine this function
1554 * belongs to. Currently only only 2 engines is supported.
1556 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1559 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1561 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1565 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1567 * @bp: driver handle
1569 * Tries to aquire a leader lock for current engine.
1571 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1573 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1577 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1580 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1582 struct bnx2x *bp = fp->bp;
1583 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1584 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1585 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1586 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1589 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1590 fp->index, cid, command, bp->state,
1591 rr_cqe->ramrod_cqe.ramrod_type);
1594 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1595 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1596 drv_cmd = BNX2X_Q_CMD_UPDATE;
1599 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1600 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1601 drv_cmd = BNX2X_Q_CMD_SETUP;
1604 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1605 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1606 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1609 case (RAMROD_CMD_ID_ETH_HALT):
1610 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1611 drv_cmd = BNX2X_Q_CMD_HALT;
1614 case (RAMROD_CMD_ID_ETH_TERMINATE):
1615 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1616 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1619 case (RAMROD_CMD_ID_ETH_EMPTY):
1620 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1621 drv_cmd = BNX2X_Q_CMD_EMPTY;
1625 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1626 command, fp->index);
1630 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1631 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1632 /* q_obj->complete_cmd() failure means that this was
1633 * an unexpected completion.
1635 * In this case we don't want to increase the bp->spq_left
1636 * because apparently we haven't sent this command the first
1639 #ifdef BNX2X_STOP_ON_ERROR
1645 smp_mb__before_atomic_inc();
1646 atomic_inc(&bp->cq_spq_left);
1647 /* push the change in bp->spq_left and towards the memory */
1648 smp_mb__after_atomic_inc();
1650 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1652 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1653 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1654 /* if Q update ramrod is completed for last Q in AFEX vif set
1655 * flow, then ACK MCP at the end
1657 * mark pending ACK to MCP bit.
1658 * prevent case that both bits are cleared.
1659 * At the end of load/unload driver checks that
1660 * sp_state is cleaerd, and this order prevents
1663 smp_mb__before_clear_bit();
1664 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1666 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1667 smp_mb__after_clear_bit();
1669 /* schedule workqueue to send ack to MCP */
1670 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1676 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1677 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1679 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1681 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1685 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1687 struct bnx2x *bp = netdev_priv(dev_instance);
1688 u16 status = bnx2x_ack_int(bp);
1693 /* Return here if interrupt is shared and it's not for us */
1694 if (unlikely(status == 0)) {
1695 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1698 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1700 #ifdef BNX2X_STOP_ON_ERROR
1701 if (unlikely(bp->panic))
1705 for_each_eth_queue(bp, i) {
1706 struct bnx2x_fastpath *fp = &bp->fp[i];
1708 mask = 0x2 << (fp->index + CNIC_PRESENT);
1709 if (status & mask) {
1710 /* Handle Rx or Tx according to SB id */
1711 prefetch(fp->rx_cons_sb);
1712 for_each_cos_in_tx_queue(fp, cos)
1713 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1714 prefetch(&fp->sb_running_index[SM_RX_ID]);
1715 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1722 if (status & (mask | 0x1)) {
1723 struct cnic_ops *c_ops = NULL;
1725 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1727 c_ops = rcu_dereference(bp->cnic_ops);
1729 c_ops->cnic_handler(bp->cnic_data, NULL);
1737 if (unlikely(status & 0x1)) {
1738 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1745 if (unlikely(status))
1746 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1755 * General service functions
1758 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1761 u32 resource_bit = (1 << resource);
1762 int func = BP_FUNC(bp);
1763 u32 hw_lock_control_reg;
1766 /* Validating that the resource is within range */
1767 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1768 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1769 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1774 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1776 hw_lock_control_reg =
1777 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1780 /* Validating that the resource is not already taken */
1781 lock_status = REG_RD(bp, hw_lock_control_reg);
1782 if (lock_status & resource_bit) {
1783 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1784 lock_status, resource_bit);
1788 /* Try for 5 second every 5ms */
1789 for (cnt = 0; cnt < 1000; cnt++) {
1790 /* Try to acquire the lock */
1791 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1792 lock_status = REG_RD(bp, hw_lock_control_reg);
1793 if (lock_status & resource_bit)
1798 BNX2X_ERR("Timeout\n");
1802 int bnx2x_release_leader_lock(struct bnx2x *bp)
1804 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1807 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1810 u32 resource_bit = (1 << resource);
1811 int func = BP_FUNC(bp);
1812 u32 hw_lock_control_reg;
1814 /* Validating that the resource is within range */
1815 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1816 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1817 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1822 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1824 hw_lock_control_reg =
1825 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1828 /* Validating that the resource is currently taken */
1829 lock_status = REG_RD(bp, hw_lock_control_reg);
1830 if (!(lock_status & resource_bit)) {
1831 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1832 lock_status, resource_bit);
1836 REG_WR(bp, hw_lock_control_reg, resource_bit);
1841 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1843 /* The GPIO should be swapped if swap register is set and active */
1844 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1845 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1846 int gpio_shift = gpio_num +
1847 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1848 u32 gpio_mask = (1 << gpio_shift);
1852 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1853 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1857 /* read GPIO value */
1858 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1860 /* get the requested pin value */
1861 if ((gpio_reg & gpio_mask) == gpio_mask)
1866 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1871 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1873 /* The GPIO should be swapped if swap register is set and active */
1874 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1875 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1876 int gpio_shift = gpio_num +
1877 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1878 u32 gpio_mask = (1 << gpio_shift);
1881 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1882 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1886 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1887 /* read GPIO and mask except the float bits */
1888 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1891 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1893 "Set GPIO %d (shift %d) -> output low\n",
1894 gpio_num, gpio_shift);
1895 /* clear FLOAT and set CLR */
1896 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1897 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1900 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1902 "Set GPIO %d (shift %d) -> output high\n",
1903 gpio_num, gpio_shift);
1904 /* clear FLOAT and set SET */
1905 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1906 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1909 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1911 "Set GPIO %d (shift %d) -> input\n",
1912 gpio_num, gpio_shift);
1914 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1921 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1922 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1927 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1932 /* Any port swapping should be handled by caller. */
1934 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1935 /* read GPIO and mask except the float bits */
1936 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1937 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1938 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1939 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1942 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1943 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1945 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1948 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1949 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1951 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1954 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1955 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1957 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1961 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1967 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1969 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1974 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1976 /* The GPIO should be swapped if swap register is set and active */
1977 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1978 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1979 int gpio_shift = gpio_num +
1980 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1981 u32 gpio_mask = (1 << gpio_shift);
1984 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1985 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1989 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1991 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1994 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1996 "Clear GPIO INT %d (shift %d) -> output low\n",
1997 gpio_num, gpio_shift);
1998 /* clear SET and set CLR */
1999 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2000 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2003 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2005 "Set GPIO INT %d (shift %d) -> output high\n",
2006 gpio_num, gpio_shift);
2007 /* clear CLR and set SET */
2008 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2009 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2016 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2017 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2022 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2024 u32 spio_mask = (1 << spio_num);
2027 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2028 (spio_num > MISC_REGISTERS_SPIO_7)) {
2029 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2033 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2034 /* read SPIO and mask except the float bits */
2035 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2038 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2039 DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num);
2040 /* clear FLOAT and set CLR */
2041 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2042 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2045 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2046 DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num);
2047 /* clear FLOAT and set SET */
2048 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2049 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2052 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2053 DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num);
2055 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2062 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2063 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2068 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2070 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2071 switch (bp->link_vars.ieee_fc &
2072 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2073 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2074 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2078 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2079 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2083 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2084 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2088 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2094 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2096 if (!BP_NOMCP(bp)) {
2098 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2099 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2101 * Initialize link parameters structure variables
2102 * It is recommended to turn off RX FC for jumbo frames
2103 * for better performance
2105 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2106 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2108 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2110 bnx2x_acquire_phy_lock(bp);
2112 if (load_mode == LOAD_DIAG) {
2113 struct link_params *lp = &bp->link_params;
2114 lp->loopback_mode = LOOPBACK_XGXS;
2115 /* do PHY loopback at 10G speed, if possible */
2116 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2117 if (lp->speed_cap_mask[cfx_idx] &
2118 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2119 lp->req_line_speed[cfx_idx] =
2122 lp->req_line_speed[cfx_idx] =
2127 if (load_mode == LOAD_LOOPBACK_EXT) {
2128 struct link_params *lp = &bp->link_params;
2129 lp->loopback_mode = LOOPBACK_EXT;
2132 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2134 bnx2x_release_phy_lock(bp);
2136 bnx2x_calc_fc_adv(bp);
2138 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2139 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2140 bnx2x_link_report(bp);
2142 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2143 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2146 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2150 void bnx2x_link_set(struct bnx2x *bp)
2152 if (!BP_NOMCP(bp)) {
2153 bnx2x_acquire_phy_lock(bp);
2154 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2155 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2156 bnx2x_release_phy_lock(bp);
2158 bnx2x_calc_fc_adv(bp);
2160 BNX2X_ERR("Bootcode is missing - can not set link\n");
2163 static void bnx2x__link_reset(struct bnx2x *bp)
2165 if (!BP_NOMCP(bp)) {
2166 bnx2x_acquire_phy_lock(bp);
2167 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2168 bnx2x_release_phy_lock(bp);
2170 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2173 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2177 if (!BP_NOMCP(bp)) {
2178 bnx2x_acquire_phy_lock(bp);
2179 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2181 bnx2x_release_phy_lock(bp);
2183 BNX2X_ERR("Bootcode is missing - can not test link\n");
2189 /* Calculates the sum of vn_min_rates.
2190 It's needed for further normalizing of the min_rates.
2192 sum of vn_min_rates.
2194 0 - if all the min_rates are 0.
2195 In the later case fainess algorithm should be deactivated.
2196 If not all min_rates are zero then those that are zeroes will be set to 1.
2198 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2199 struct cmng_init_input *input)
2204 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2205 u32 vn_cfg = bp->mf_config[vn];
2206 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2207 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2209 /* Skip hidden vns */
2210 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2212 /* If min rate is zero - set it to 1 */
2213 else if (!vn_min_rate)
2214 vn_min_rate = DEF_MIN_RATE;
2218 input->vnic_min_rate[vn] = vn_min_rate;
2221 /* if ETS or all min rates are zeros - disable fairness */
2222 if (BNX2X_IS_ETS_ENABLED(bp)) {
2223 input->flags.cmng_enables &=
2224 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2225 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2226 } else if (all_zero) {
2227 input->flags.cmng_enables &=
2228 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2230 "All MIN values are zeroes fairness will be disabled\n");
2232 input->flags.cmng_enables |=
2233 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2236 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2237 struct cmng_init_input *input)
2240 u32 vn_cfg = bp->mf_config[vn];
2242 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2245 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2248 /* maxCfg in percents of linkspeed */
2249 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2250 } else /* SD modes */
2251 /* maxCfg is absolute in 100Mb units */
2252 vn_max_rate = maxCfg * 100;
2255 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2257 input->vnic_max_rate[vn] = vn_max_rate;
2261 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2263 if (CHIP_REV_IS_SLOW(bp))
2264 return CMNG_FNS_NONE;
2266 return CMNG_FNS_MINMAX;
2268 return CMNG_FNS_NONE;
2271 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2273 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2276 return; /* what should be the default bvalue in this case */
2278 /* For 2 port configuration the absolute function number formula
2280 * abs_func = 2 * vn + BP_PORT + BP_PATH
2282 * and there are 4 functions per port
2284 * For 4 port configuration it is
2285 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2287 * and there are 2 functions per port
2289 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2290 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2292 if (func >= E1H_FUNC_MAX)
2296 MF_CFG_RD(bp, func_mf_config[func].config);
2298 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2299 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2300 bp->flags |= MF_FUNC_DIS;
2302 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2303 bp->flags &= ~MF_FUNC_DIS;
2307 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2309 struct cmng_init_input input;
2310 memset(&input, 0, sizeof(struct cmng_init_input));
2312 input.port_rate = bp->link_vars.line_speed;
2314 if (cmng_type == CMNG_FNS_MINMAX) {
2317 /* read mf conf from shmem */
2319 bnx2x_read_mf_cfg(bp);
2321 /* vn_weight_sum and enable fairness if not 0 */
2322 bnx2x_calc_vn_min(bp, &input);
2324 /* calculate and set min-max rate for each vn */
2326 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2327 bnx2x_calc_vn_max(bp, vn, &input);
2329 /* always enable rate shaping and fairness */
2330 input.flags.cmng_enables |=
2331 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2333 bnx2x_init_cmng(&input, &bp->cmng);
2337 /* rate shaping and fairness are disabled */
2339 "rate shaping and fairness are disabled\n");
2342 static void storm_memset_cmng(struct bnx2x *bp,
2343 struct cmng_init *cmng,
2347 size_t size = sizeof(struct cmng_struct_per_port);
2349 u32 addr = BAR_XSTRORM_INTMEM +
2350 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2352 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2354 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2355 int func = func_by_vn(bp, vn);
2357 addr = BAR_XSTRORM_INTMEM +
2358 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2359 size = sizeof(struct rate_shaping_vars_per_vn);
2360 __storm_memset_struct(bp, addr, size,
2361 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2363 addr = BAR_XSTRORM_INTMEM +
2364 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2365 size = sizeof(struct fairness_vars_per_vn);
2366 __storm_memset_struct(bp, addr, size,
2367 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2371 /* This function is called upon link interrupt */
2372 static void bnx2x_link_attn(struct bnx2x *bp)
2374 /* Make sure that we are synced with the current statistics */
2375 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2377 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2379 if (bp->link_vars.link_up) {
2381 /* dropless flow control */
2382 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2383 int port = BP_PORT(bp);
2384 u32 pause_enabled = 0;
2386 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2389 REG_WR(bp, BAR_USTRORM_INTMEM +
2390 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2394 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2395 struct host_port_stats *pstats;
2397 pstats = bnx2x_sp(bp, port_stats);
2398 /* reset old mac stats */
2399 memset(&(pstats->mac_stx[0]), 0,
2400 sizeof(struct mac_stx));
2402 if (bp->state == BNX2X_STATE_OPEN)
2403 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2406 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2407 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2409 if (cmng_fns != CMNG_FNS_NONE) {
2410 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2411 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2413 /* rate shaping and fairness are disabled */
2415 "single function mode without fairness\n");
2418 __bnx2x_link_report(bp);
2421 bnx2x_link_sync_notify(bp);
2424 void bnx2x__link_status_update(struct bnx2x *bp)
2426 if (bp->state != BNX2X_STATE_OPEN)
2429 /* read updated dcb configuration */
2430 bnx2x_dcbx_pmf_update(bp);
2432 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2434 if (bp->link_vars.link_up)
2435 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2437 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2439 /* indicate link status */
2440 bnx2x_link_report(bp);
2443 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2444 u16 vlan_val, u8 allowed_prio)
2446 struct bnx2x_func_state_params func_params = {0};
2447 struct bnx2x_func_afex_update_params *f_update_params =
2448 &func_params.params.afex_update;
2450 func_params.f_obj = &bp->func_obj;
2451 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2453 /* no need to wait for RAMROD completion, so don't
2454 * set RAMROD_COMP_WAIT flag
2457 f_update_params->vif_id = vifid;
2458 f_update_params->afex_default_vlan = vlan_val;
2459 f_update_params->allowed_priorities = allowed_prio;
2461 /* if ramrod can not be sent, response to MCP immediately */
2462 if (bnx2x_func_state_change(bp, &func_params) < 0)
2463 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2468 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2469 u16 vif_index, u8 func_bit_map)
2471 struct bnx2x_func_state_params func_params = {0};
2472 struct bnx2x_func_afex_viflists_params *update_params =
2473 &func_params.params.afex_viflists;
2477 /* validate only LIST_SET and LIST_GET are received from switch */
2478 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2479 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2482 func_params.f_obj = &bp->func_obj;
2483 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2485 /* set parameters according to cmd_type */
2486 update_params->afex_vif_list_command = cmd_type;
2487 update_params->vif_list_index = cpu_to_le16(vif_index);
2488 update_params->func_bit_map =
2489 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2490 update_params->func_to_clear = 0;
2492 (cmd_type == VIF_LIST_RULE_GET) ?
2493 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2494 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2496 /* if ramrod can not be sent, respond to MCP immediately for
2497 * SET and GET requests (other are not triggered from MCP)
2499 rc = bnx2x_func_state_change(bp, &func_params);
2501 bnx2x_fw_command(bp, drv_msg_code, 0);
2506 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2508 struct afex_stats afex_stats;
2509 u32 func = BP_ABS_FUNC(bp);
2516 u32 addr_to_write, vifid, addrs, stats_type, i;
2518 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2519 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2521 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2522 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2525 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2526 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2527 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2529 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2531 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2535 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2536 addr_to_write = SHMEM2_RD(bp,
2537 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2538 stats_type = SHMEM2_RD(bp,
2539 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2542 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2545 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2547 /* write response to scratchpad, for MCP */
2548 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2549 REG_WR(bp, addr_to_write + i*sizeof(u32),
2550 *(((u32 *)(&afex_stats))+i));
2552 /* send ack message to MCP */
2553 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2556 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2557 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2558 bp->mf_config[BP_VN(bp)] = mf_config;
2560 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2563 /* if VIF_SET is "enabled" */
2564 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2565 /* set rate limit directly to internal RAM */
2566 struct cmng_init_input cmng_input;
2567 struct rate_shaping_vars_per_vn m_rs_vn;
2568 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2569 u32 addr = BAR_XSTRORM_INTMEM +
2570 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2572 bp->mf_config[BP_VN(bp)] = mf_config;
2574 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2575 m_rs_vn.vn_counter.rate =
2576 cmng_input.vnic_max_rate[BP_VN(bp)];
2577 m_rs_vn.vn_counter.quota =
2578 (m_rs_vn.vn_counter.rate *
2579 RS_PERIODIC_TIMEOUT_USEC) / 8;
2581 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2583 /* read relevant values from mf_cfg struct in shmem */
2585 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2586 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2587 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2589 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2590 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2591 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2592 vlan_prio = (mf_config &
2593 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2594 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2595 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2598 func_mf_config[func].afex_config) &
2599 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2600 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2603 func_mf_config[func].afex_config) &
2604 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2605 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2607 /* send ramrod to FW, return in case of failure */
2608 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2612 bp->afex_def_vlan_tag = vlan_val;
2613 bp->afex_vlan_mode = vlan_mode;
2615 /* notify link down because BP->flags is disabled */
2616 bnx2x_link_report(bp);
2618 /* send INVALID VIF ramrod to FW */
2619 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2621 /* Reset the default afex VLAN */
2622 bp->afex_def_vlan_tag = -1;
2627 static void bnx2x_pmf_update(struct bnx2x *bp)
2629 int port = BP_PORT(bp);
2633 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2636 * We need the mb() to ensure the ordering between the writing to
2637 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2641 /* queue a periodic task */
2642 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2644 bnx2x_dcbx_pmf_update(bp);
2646 /* enable nig attention */
2647 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2648 if (bp->common.int_block == INT_BLOCK_HC) {
2649 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2650 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2651 } else if (!CHIP_IS_E1x(bp)) {
2652 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2653 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2656 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2664 * General service functions
2667 /* send the MCP a request, block until there is a reply */
2668 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2670 int mb_idx = BP_FW_MB_IDX(bp);
2674 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2676 mutex_lock(&bp->fw_mb_mutex);
2678 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2679 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2681 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2682 (command | seq), param);
2685 /* let the FW do it's magic ... */
2688 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2690 /* Give the FW up to 5 second (500*10ms) */
2691 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2693 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2694 cnt*delay, rc, seq);
2696 /* is this a reply to our command? */
2697 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2698 rc &= FW_MSG_CODE_MASK;
2701 BNX2X_ERR("FW failed to respond!\n");
2705 mutex_unlock(&bp->fw_mb_mutex);
2711 static void storm_memset_func_cfg(struct bnx2x *bp,
2712 struct tstorm_eth_function_common_config *tcfg,
2715 size_t size = sizeof(struct tstorm_eth_function_common_config);
2717 u32 addr = BAR_TSTRORM_INTMEM +
2718 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2720 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2723 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2725 if (CHIP_IS_E1x(bp)) {
2726 struct tstorm_eth_function_common_config tcfg = {0};
2728 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2731 /* Enable the function in the FW */
2732 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2733 storm_memset_func_en(bp, p->func_id, 1);
2736 if (p->func_flgs & FUNC_FLG_SPQ) {
2737 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2738 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2739 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2744 * bnx2x_get_tx_only_flags - Return common flags
2748 * @zero_stats TRUE if statistics zeroing is needed
2750 * Return the flags that are common for the Tx-only and not normal connections.
2752 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2753 struct bnx2x_fastpath *fp,
2756 unsigned long flags = 0;
2758 /* PF driver will always initialize the Queue to an ACTIVE state */
2759 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2761 /* tx only connections collect statistics (on the same index as the
2762 * parent connection). The statistics are zeroed when the parent
2763 * connection is initialized.
2766 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2768 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2774 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2775 struct bnx2x_fastpath *fp,
2778 unsigned long flags = 0;
2780 /* calculate other queue flags */
2782 __set_bit(BNX2X_Q_FLG_OV, &flags);
2784 if (IS_FCOE_FP(fp)) {
2785 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2786 /* For FCoE - force usage of default priority (for afex) */
2787 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2790 if (!fp->disable_tpa) {
2791 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2792 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2793 if (fp->mode == TPA_MODE_GRO)
2794 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2798 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2799 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2802 /* Always set HW VLAN stripping */
2803 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2805 /* configure silent vlan removal */
2807 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2810 return flags | bnx2x_get_common_flags(bp, fp, true);
2813 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2814 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2817 gen_init->stat_id = bnx2x_stats_id(fp);
2818 gen_init->spcl_id = fp->cl_id;
2820 /* Always use mini-jumbo MTU for FCoE L2 ring */
2822 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2824 gen_init->mtu = bp->dev->mtu;
2826 gen_init->cos = cos;
2829 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2830 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2831 struct bnx2x_rxq_setup_params *rxq_init)
2835 u16 tpa_agg_size = 0;
2837 if (!fp->disable_tpa) {
2838 pause->sge_th_lo = SGE_TH_LO(bp);
2839 pause->sge_th_hi = SGE_TH_HI(bp);
2841 /* validate SGE ring has enough to cross high threshold */
2842 WARN_ON(bp->dropless_fc &&
2843 pause->sge_th_hi + FW_PREFETCH_CNT >
2844 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2846 tpa_agg_size = min_t(u32,
2847 (min_t(u32, 8, MAX_SKB_FRAGS) *
2848 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2849 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2851 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2852 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2853 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2857 /* pause - not for e1 */
2858 if (!CHIP_IS_E1(bp)) {
2859 pause->bd_th_lo = BD_TH_LO(bp);
2860 pause->bd_th_hi = BD_TH_HI(bp);
2862 pause->rcq_th_lo = RCQ_TH_LO(bp);
2863 pause->rcq_th_hi = RCQ_TH_HI(bp);
2865 * validate that rings have enough entries to cross
2868 WARN_ON(bp->dropless_fc &&
2869 pause->bd_th_hi + FW_PREFETCH_CNT >
2871 WARN_ON(bp->dropless_fc &&
2872 pause->rcq_th_hi + FW_PREFETCH_CNT >
2873 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2879 rxq_init->dscr_map = fp->rx_desc_mapping;
2880 rxq_init->sge_map = fp->rx_sge_mapping;
2881 rxq_init->rcq_map = fp->rx_comp_mapping;
2882 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2884 /* This should be a maximum number of data bytes that may be
2885 * placed on the BD (not including paddings).
2887 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2888 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
2890 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2891 rxq_init->tpa_agg_sz = tpa_agg_size;
2892 rxq_init->sge_buf_sz = sge_sz;
2893 rxq_init->max_sges_pkt = max_sge;
2894 rxq_init->rss_engine_id = BP_FUNC(bp);
2895 rxq_init->mcast_engine_id = BP_FUNC(bp);
2897 /* Maximum number or simultaneous TPA aggregation for this Queue.
2899 * For PF Clients it should be the maximum avaliable number.
2900 * VF driver(s) may want to define it to a smaller value.
2902 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2904 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2905 rxq_init->fw_sb_id = fp->fw_sb_id;
2908 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2910 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2911 /* configure silent vlan removal
2912 * if multi function mode is afex, then mask default vlan
2914 if (IS_MF_AFEX(bp)) {
2915 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
2916 rxq_init->silent_removal_mask = VLAN_VID_MASK;
2920 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2921 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2924 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
2925 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2926 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2927 txq_init->fw_sb_id = fp->fw_sb_id;
2930 * set the tss leading client id for TX classfication ==
2931 * leading RSS client id
2933 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2935 if (IS_FCOE_FP(fp)) {
2936 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2937 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2941 static void bnx2x_pf_init(struct bnx2x *bp)
2943 struct bnx2x_func_init_params func_init = {0};
2944 struct event_ring_data eq_data = { {0} };
2947 if (!CHIP_IS_E1x(bp)) {
2948 /* reset IGU PF statistics: MSIX + ATTN */
2950 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2951 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2952 (CHIP_MODE_IS_4_PORT(bp) ?
2953 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2955 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2956 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2957 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2958 (CHIP_MODE_IS_4_PORT(bp) ?
2959 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2962 /* function setup flags */
2963 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2965 /* This flag is relevant for E1x only.
2966 * E2 doesn't have a TPA configuration in a function level.
2968 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2970 func_init.func_flgs = flags;
2971 func_init.pf_id = BP_FUNC(bp);
2972 func_init.func_id = BP_FUNC(bp);
2973 func_init.spq_map = bp->spq_mapping;
2974 func_init.spq_prod = bp->spq_prod_idx;
2976 bnx2x_func_init(bp, &func_init);
2978 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2981 * Congestion management values depend on the link rate
2982 * There is no active link so initial link rate is set to 10 Gbps.
2983 * When the link comes up The congestion management values are
2984 * re-calculated according to the actual link rate.
2986 bp->link_vars.line_speed = SPEED_10000;
2987 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2989 /* Only the PMF sets the HW */
2991 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2993 /* init Event Queue */
2994 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2995 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2996 eq_data.producer = bp->eq_prod;
2997 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2998 eq_data.sb_id = DEF_SB_ID;
2999 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3003 static void bnx2x_e1h_disable(struct bnx2x *bp)
3005 int port = BP_PORT(bp);
3007 bnx2x_tx_disable(bp);
3009 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3012 static void bnx2x_e1h_enable(struct bnx2x *bp)
3014 int port = BP_PORT(bp);
3016 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3018 /* Tx queue should be only reenabled */
3019 netif_tx_wake_all_queues(bp->dev);
3022 * Should not call netif_carrier_on since it will be called if the link
3023 * is up when checking for link state
3027 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3029 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3031 struct eth_stats_info *ether_stat =
3032 &bp->slowpath->drv_info_to_mcp.ether_stat;
3034 /* leave last char as NULL */
3035 memcpy(ether_stat->version, DRV_MODULE_VERSION,
3036 ETH_STAT_INFO_VERSION_LEN - 1);
3038 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3039 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3040 ether_stat->mac_local);
3042 ether_stat->mtu_size = bp->dev->mtu;
3044 if (bp->dev->features & NETIF_F_RXCSUM)
3045 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3046 if (bp->dev->features & NETIF_F_TSO)
3047 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3048 ether_stat->feature_flags |= bp->common.boot_mode;
3050 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3052 ether_stat->txq_size = bp->tx_ring_size;
3053 ether_stat->rxq_size = bp->rx_ring_size;
3056 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3059 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3060 struct fcoe_stats_info *fcoe_stat =
3061 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3063 memcpy(fcoe_stat->mac_local, bp->fip_mac, ETH_ALEN);
3065 fcoe_stat->qos_priority =
3066 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3068 /* insert FCoE stats from ramrod response */
3070 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3071 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3072 tstorm_queue_statistics;
3074 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3075 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3076 xstorm_queue_statistics;
3078 struct fcoe_statistics_params *fw_fcoe_stat =
3079 &bp->fw_stats_data->fcoe;
3081 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3082 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3084 ADD_64(fcoe_stat->rx_bytes_hi,
3085 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3086 fcoe_stat->rx_bytes_lo,
3087 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3089 ADD_64(fcoe_stat->rx_bytes_hi,
3090 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3091 fcoe_stat->rx_bytes_lo,
3092 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3094 ADD_64(fcoe_stat->rx_bytes_hi,
3095 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3096 fcoe_stat->rx_bytes_lo,
3097 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3099 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3100 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3102 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3103 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3105 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3106 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3108 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3109 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3111 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3112 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3114 ADD_64(fcoe_stat->tx_bytes_hi,
3115 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3116 fcoe_stat->tx_bytes_lo,
3117 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3119 ADD_64(fcoe_stat->tx_bytes_hi,
3120 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3121 fcoe_stat->tx_bytes_lo,
3122 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3124 ADD_64(fcoe_stat->tx_bytes_hi,
3125 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3126 fcoe_stat->tx_bytes_lo,
3127 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3129 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3130 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3132 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3133 fcoe_q_xstorm_stats->ucast_pkts_sent);
3135 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3136 fcoe_q_xstorm_stats->bcast_pkts_sent);
3138 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3139 fcoe_q_xstorm_stats->mcast_pkts_sent);
3142 /* ask L5 driver to add data to the struct */
3143 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3147 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3150 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3151 struct iscsi_stats_info *iscsi_stat =
3152 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3154 memcpy(iscsi_stat->mac_local, bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3156 iscsi_stat->qos_priority =
3157 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3159 /* ask L5 driver to add data to the struct */
3160 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3164 /* called due to MCP event (on pmf):
3165 * reread new bandwidth configuration
3167 * notify others function about the change
3169 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3171 if (bp->link_vars.link_up) {
3172 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3173 bnx2x_link_sync_notify(bp);
3175 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3178 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3180 bnx2x_config_mf_bw(bp);
3181 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3184 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3186 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3187 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3190 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3192 enum drv_info_opcode op_code;
3193 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3195 /* if drv_info version supported by MFW doesn't match - send NACK */
3196 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3197 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3201 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3202 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3204 memset(&bp->slowpath->drv_info_to_mcp, 0,
3205 sizeof(union drv_info_to_mcp));
3208 case ETH_STATS_OPCODE:
3209 bnx2x_drv_info_ether_stat(bp);
3211 case FCOE_STATS_OPCODE:
3212 bnx2x_drv_info_fcoe_stat(bp);
3214 case ISCSI_STATS_OPCODE:
3215 bnx2x_drv_info_iscsi_stat(bp);
3218 /* if op code isn't supported - send NACK */
3219 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3223 /* if we got drv_info attn from MFW then these fields are defined in
3226 SHMEM2_WR(bp, drv_info_host_addr_lo,
3227 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3228 SHMEM2_WR(bp, drv_info_host_addr_hi,
3229 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3231 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3234 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3236 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3238 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3241 * This is the only place besides the function initialization
3242 * where the bp->flags can change so it is done without any
3245 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3246 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3247 bp->flags |= MF_FUNC_DIS;
3249 bnx2x_e1h_disable(bp);
3251 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3252 bp->flags &= ~MF_FUNC_DIS;
3254 bnx2x_e1h_enable(bp);
3256 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3258 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3259 bnx2x_config_mf_bw(bp);
3260 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3263 /* Report results to MCP */
3265 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3267 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3270 /* must be called under the spq lock */
3271 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3273 struct eth_spe *next_spe = bp->spq_prod_bd;
3275 if (bp->spq_prod_bd == bp->spq_last_bd) {
3276 bp->spq_prod_bd = bp->spq;
3277 bp->spq_prod_idx = 0;
3278 DP(BNX2X_MSG_SP, "end of spq\n");
3286 /* must be called under the spq lock */
3287 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3289 int func = BP_FUNC(bp);
3292 * Make sure that BD data is updated before writing the producer:
3293 * BD data is written to the memory, the producer is read from the
3294 * memory, thus we need a full memory barrier to ensure the ordering.
3298 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3304 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3306 * @cmd: command to check
3307 * @cmd_type: command type
3309 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3311 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3312 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3313 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3314 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3315 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3316 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3317 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3326 * bnx2x_sp_post - place a single command on an SP ring
3328 * @bp: driver handle
3329 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3330 * @cid: SW CID the command is related to
3331 * @data_hi: command private data address (high 32 bits)
3332 * @data_lo: command private data address (low 32 bits)
3333 * @cmd_type: command type (e.g. NONE, ETH)
3335 * SP data is handled as if it's always an address pair, thus data fields are
3336 * not swapped to little endian in upper functions. Instead this function swaps
3337 * data as if it's two u32 fields.
3339 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3340 u32 data_hi, u32 data_lo, int cmd_type)
3342 struct eth_spe *spe;
3344 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3346 #ifdef BNX2X_STOP_ON_ERROR
3347 if (unlikely(bp->panic)) {
3348 BNX2X_ERR("Can't post SP when there is panic\n");
3353 spin_lock_bh(&bp->spq_lock);
3356 if (!atomic_read(&bp->eq_spq_left)) {
3357 BNX2X_ERR("BUG! EQ ring full!\n");
3358 spin_unlock_bh(&bp->spq_lock);
3362 } else if (!atomic_read(&bp->cq_spq_left)) {
3363 BNX2X_ERR("BUG! SPQ ring full!\n");
3364 spin_unlock_bh(&bp->spq_lock);
3369 spe = bnx2x_sp_get_next(bp);
3371 /* CID needs port number to be encoded int it */
3372 spe->hdr.conn_and_cmd_data =
3373 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3376 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3378 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3379 SPE_HDR_FUNCTION_ID);
3381 spe->hdr.type = cpu_to_le16(type);
3383 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3384 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3387 * It's ok if the actual decrement is issued towards the memory
3388 * somewhere between the spin_lock and spin_unlock. Thus no
3389 * more explict memory barrier is needed.
3392 atomic_dec(&bp->eq_spq_left);
3394 atomic_dec(&bp->cq_spq_left);
3398 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3399 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3400 (u32)(U64_LO(bp->spq_mapping) +
3401 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3402 HW_CID(bp, cid), data_hi, data_lo, type,
3403 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3405 bnx2x_sp_prod_update(bp);
3406 spin_unlock_bh(&bp->spq_lock);
3410 /* acquire split MCP access lock register */
3411 static int bnx2x_acquire_alr(struct bnx2x *bp)
3417 for (j = 0; j < 1000; j++) {
3419 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3420 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3421 if (val & (1L << 31))
3426 if (!(val & (1L << 31))) {
3427 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3434 /* release split MCP access lock register */
3435 static void bnx2x_release_alr(struct bnx2x *bp)
3437 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3440 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3441 #define BNX2X_DEF_SB_IDX 0x0002
3443 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3445 struct host_sp_status_block *def_sb = bp->def_status_blk;
3448 barrier(); /* status block is written to by the chip */
3449 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3450 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3451 rc |= BNX2X_DEF_SB_ATT_IDX;
3454 if (bp->def_idx != def_sb->sp_sb.running_index) {
3455 bp->def_idx = def_sb->sp_sb.running_index;
3456 rc |= BNX2X_DEF_SB_IDX;
3459 /* Do not reorder: indecies reading should complete before handling */
3465 * slow path service functions
3468 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3470 int port = BP_PORT(bp);
3471 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3472 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3473 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3474 NIG_REG_MASK_INTERRUPT_PORT0;
3479 if (bp->attn_state & asserted)
3480 BNX2X_ERR("IGU ERROR\n");
3482 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3483 aeu_mask = REG_RD(bp, aeu_addr);
3485 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3486 aeu_mask, asserted);
3487 aeu_mask &= ~(asserted & 0x3ff);
3488 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3490 REG_WR(bp, aeu_addr, aeu_mask);
3491 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3493 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3494 bp->attn_state |= asserted;
3495 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3497 if (asserted & ATTN_HARD_WIRED_MASK) {
3498 if (asserted & ATTN_NIG_FOR_FUNC) {
3500 bnx2x_acquire_phy_lock(bp);
3502 /* save nig interrupt mask */
3503 nig_mask = REG_RD(bp, nig_int_mask_addr);
3505 /* If nig_mask is not set, no need to call the update
3509 REG_WR(bp, nig_int_mask_addr, 0);
3511 bnx2x_link_attn(bp);
3514 /* handle unicore attn? */
3516 if (asserted & ATTN_SW_TIMER_4_FUNC)
3517 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3519 if (asserted & GPIO_2_FUNC)
3520 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3522 if (asserted & GPIO_3_FUNC)
3523 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3525 if (asserted & GPIO_4_FUNC)
3526 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3529 if (asserted & ATTN_GENERAL_ATTN_1) {
3530 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3531 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3533 if (asserted & ATTN_GENERAL_ATTN_2) {
3534 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3535 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3537 if (asserted & ATTN_GENERAL_ATTN_3) {
3538 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3539 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3542 if (asserted & ATTN_GENERAL_ATTN_4) {
3543 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3544 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3546 if (asserted & ATTN_GENERAL_ATTN_5) {
3547 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3548 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3550 if (asserted & ATTN_GENERAL_ATTN_6) {
3551 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3552 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3556 } /* if hardwired */
3558 if (bp->common.int_block == INT_BLOCK_HC)
3559 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3560 COMMAND_REG_ATTN_BITS_SET);
3562 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3564 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3565 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3566 REG_WR(bp, reg_addr, asserted);
3568 /* now set back the mask */
3569 if (asserted & ATTN_NIG_FOR_FUNC) {
3570 REG_WR(bp, nig_int_mask_addr, nig_mask);
3571 bnx2x_release_phy_lock(bp);
3575 static void bnx2x_fan_failure(struct bnx2x *bp)
3577 int port = BP_PORT(bp);
3579 /* mark the failure */
3582 dev_info.port_hw_config[port].external_phy_config);
3584 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3585 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3586 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3589 /* log the failure */
3590 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3591 "Please contact OEM Support for assistance\n");
3594 * Scheudle device reset (unload)
3595 * This is due to some boards consuming sufficient power when driver is
3596 * up to overheat if fan fails.
3598 smp_mb__before_clear_bit();
3599 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3600 smp_mb__after_clear_bit();
3601 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3605 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3607 int port = BP_PORT(bp);
3611 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3612 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3614 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3616 val = REG_RD(bp, reg_offset);
3617 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3618 REG_WR(bp, reg_offset, val);
3620 BNX2X_ERR("SPIO5 hw attention\n");
3622 /* Fan failure attention */
3623 bnx2x_hw_reset_phy(&bp->link_params);
3624 bnx2x_fan_failure(bp);
3627 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3628 bnx2x_acquire_phy_lock(bp);
3629 bnx2x_handle_module_detect_int(&bp->link_params);
3630 bnx2x_release_phy_lock(bp);
3633 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3635 val = REG_RD(bp, reg_offset);
3636 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3637 REG_WR(bp, reg_offset, val);
3639 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3640 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3645 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3649 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3651 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3652 BNX2X_ERR("DB hw attention 0x%x\n", val);
3653 /* DORQ discard attention */
3655 BNX2X_ERR("FATAL error from DORQ\n");
3658 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3660 int port = BP_PORT(bp);
3663 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3664 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3666 val = REG_RD(bp, reg_offset);
3667 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3668 REG_WR(bp, reg_offset, val);
3670 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3671 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3676 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3680 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3682 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3683 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3684 /* CFC error attention */
3686 BNX2X_ERR("FATAL error from CFC\n");
3689 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3690 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3691 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3692 /* RQ_USDMDP_FIFO_OVERFLOW */
3694 BNX2X_ERR("FATAL error from PXP\n");
3696 if (!CHIP_IS_E1x(bp)) {
3697 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3698 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3702 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3704 int port = BP_PORT(bp);
3707 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3708 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3710 val = REG_RD(bp, reg_offset);
3711 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3712 REG_WR(bp, reg_offset, val);
3714 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3715 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3720 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3724 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3726 if (attn & BNX2X_PMF_LINK_ASSERT) {
3727 int func = BP_FUNC(bp);
3729 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3730 bnx2x_read_mf_cfg(bp);
3731 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3732 func_mf_config[BP_ABS_FUNC(bp)].config);
3734 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3735 if (val & DRV_STATUS_DCC_EVENT_MASK)
3737 (val & DRV_STATUS_DCC_EVENT_MASK));
3739 if (val & DRV_STATUS_SET_MF_BW)
3740 bnx2x_set_mf_bw(bp);
3742 if (val & DRV_STATUS_DRV_INFO_REQ)
3743 bnx2x_handle_drv_info_req(bp);
3744 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3745 bnx2x_pmf_update(bp);
3748 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3749 bp->dcbx_enabled > 0)
3750 /* start dcbx state machine */
3751 bnx2x_dcbx_set_params(bp,
3752 BNX2X_DCBX_STATE_NEG_RECEIVED);
3753 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3754 bnx2x_handle_afex_cmd(bp,
3755 val & DRV_STATUS_AFEX_EVENT_MASK);
3756 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3757 bnx2x_handle_eee_event(bp);
3758 if (bp->link_vars.periodic_flags &
3759 PERIODIC_FLAGS_LINK_EVENT) {
3760 /* sync with link */
3761 bnx2x_acquire_phy_lock(bp);
3762 bp->link_vars.periodic_flags &=
3763 ~PERIODIC_FLAGS_LINK_EVENT;
3764 bnx2x_release_phy_lock(bp);
3766 bnx2x_link_sync_notify(bp);
3767 bnx2x_link_report(bp);
3769 /* Always call it here: bnx2x_link_report() will
3770 * prevent the link indication duplication.
3772 bnx2x__link_status_update(bp);
3773 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3775 BNX2X_ERR("MC assert!\n");
3776 bnx2x_mc_assert(bp);
3777 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3778 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3779 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3780 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3783 } else if (attn & BNX2X_MCP_ASSERT) {
3785 BNX2X_ERR("MCP assert!\n");
3786 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3790 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3793 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3794 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3795 if (attn & BNX2X_GRC_TIMEOUT) {
3796 val = CHIP_IS_E1(bp) ? 0 :
3797 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3798 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3800 if (attn & BNX2X_GRC_RSV) {
3801 val = CHIP_IS_E1(bp) ? 0 :
3802 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3803 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3805 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3811 * 0-7 - Engine0 load counter.
3812 * 8-15 - Engine1 load counter.
3813 * 16 - Engine0 RESET_IN_PROGRESS bit.
3814 * 17 - Engine1 RESET_IN_PROGRESS bit.
3815 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3817 * 19 - Engine1 ONE_IS_LOADED.
3818 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3819 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3820 * just the one belonging to its engine).
3823 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3825 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3826 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3827 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3828 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3829 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3830 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3831 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3834 * Set the GLOBAL_RESET bit.
3836 * Should be run under rtnl lock
3838 void bnx2x_set_reset_global(struct bnx2x *bp)
3841 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3842 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3843 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3844 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3848 * Clear the GLOBAL_RESET bit.
3850 * Should be run under rtnl lock
3852 static void bnx2x_clear_reset_global(struct bnx2x *bp)
3855 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3856 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3857 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3858 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3862 * Checks the GLOBAL_RESET bit.
3864 * should be run under rtnl lock
3866 static bool bnx2x_reset_is_global(struct bnx2x *bp)
3868 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3870 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3871 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3875 * Clear RESET_IN_PROGRESS bit for the current engine.
3877 * Should be run under rtnl lock
3879 static void bnx2x_set_reset_done(struct bnx2x *bp)
3882 u32 bit = BP_PATH(bp) ?
3883 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3884 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3885 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3889 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3891 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3895 * Set RESET_IN_PROGRESS for the current engine.
3897 * should be run under rtnl lock
3899 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3902 u32 bit = BP_PATH(bp) ?
3903 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3904 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3905 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3909 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3910 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3914 * Checks the RESET_IN_PROGRESS bit for the given engine.
3915 * should be run under rtnl lock
3917 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3919 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3921 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3923 /* return false if bit is set */
3924 return (val & bit) ? false : true;
3928 * set pf load for the current pf.
3930 * should be run under rtnl lock
3932 void bnx2x_set_pf_load(struct bnx2x *bp)
3935 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3936 BNX2X_PATH0_LOAD_CNT_MASK;
3937 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3938 BNX2X_PATH0_LOAD_CNT_SHIFT;
3940 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3941 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3943 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
3945 /* get the current counter value */
3946 val1 = (val & mask) >> shift;
3948 /* set bit of that PF */
3949 val1 |= (1 << bp->pf_num);
3951 /* clear the old value */
3954 /* set the new one */
3955 val |= ((val1 << shift) & mask);
3957 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3958 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3962 * bnx2x_clear_pf_load - clear pf load mark
3964 * @bp: driver handle
3966 * Should be run under rtnl lock.
3967 * Decrements the load counter for the current engine. Returns
3968 * whether other functions are still loaded
3970 bool bnx2x_clear_pf_load(struct bnx2x *bp)
3973 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3974 BNX2X_PATH0_LOAD_CNT_MASK;
3975 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3976 BNX2X_PATH0_LOAD_CNT_SHIFT;
3978 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3979 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3980 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
3982 /* get the current counter value */
3983 val1 = (val & mask) >> shift;
3985 /* clear bit of that PF */
3986 val1 &= ~(1 << bp->pf_num);
3988 /* clear the old value */
3991 /* set the new one */
3992 val |= ((val1 << shift) & mask);
3994 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3995 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4000 * Read the load status for the current engine.
4002 * should be run under rtnl lock
4004 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4006 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4007 BNX2X_PATH0_LOAD_CNT_MASK);
4008 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4009 BNX2X_PATH0_LOAD_CNT_SHIFT);
4010 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4012 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4014 val = (val & mask) >> shift;
4016 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4023 * Reset the load status for the current engine.
4025 static void bnx2x_clear_load_status(struct bnx2x *bp)
4028 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4029 BNX2X_PATH0_LOAD_CNT_MASK);
4030 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4031 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4032 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
4033 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4036 static void _print_next_block(int idx, const char *blk)
4038 pr_cont("%s%s", idx ? ", " : "", blk);
4041 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4046 for (i = 0; sig; i++) {
4047 cur_bit = ((u32)0x1 << i);
4048 if (sig & cur_bit) {
4050 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4052 _print_next_block(par_num++, "BRB");
4054 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4056 _print_next_block(par_num++, "PARSER");
4058 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4060 _print_next_block(par_num++, "TSDM");
4062 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4064 _print_next_block(par_num++,
4067 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4069 _print_next_block(par_num++, "TCM");
4071 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4073 _print_next_block(par_num++, "TSEMI");
4075 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4077 _print_next_block(par_num++, "XPB");
4089 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4090 bool *global, bool print)
4094 for (i = 0; sig; i++) {
4095 cur_bit = ((u32)0x1 << i);
4096 if (sig & cur_bit) {
4098 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4100 _print_next_block(par_num++, "PBF");
4102 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4104 _print_next_block(par_num++, "QM");
4106 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4108 _print_next_block(par_num++, "TM");
4110 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4112 _print_next_block(par_num++, "XSDM");
4114 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4116 _print_next_block(par_num++, "XCM");
4118 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4120 _print_next_block(par_num++, "XSEMI");
4122 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4124 _print_next_block(par_num++,
4127 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4129 _print_next_block(par_num++, "NIG");
4131 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4133 _print_next_block(par_num++,
4137 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4139 _print_next_block(par_num++, "DEBUG");
4141 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4143 _print_next_block(par_num++, "USDM");
4145 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4147 _print_next_block(par_num++, "UCM");
4149 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4151 _print_next_block(par_num++, "USEMI");
4153 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4155 _print_next_block(par_num++, "UPB");
4157 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4159 _print_next_block(par_num++, "CSDM");
4161 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4163 _print_next_block(par_num++, "CCM");
4175 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4180 for (i = 0; sig; i++) {
4181 cur_bit = ((u32)0x1 << i);
4182 if (sig & cur_bit) {
4184 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4186 _print_next_block(par_num++, "CSEMI");
4188 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4190 _print_next_block(par_num++, "PXP");
4192 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4194 _print_next_block(par_num++,
4195 "PXPPCICLOCKCLIENT");
4197 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4199 _print_next_block(par_num++, "CFC");
4201 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4203 _print_next_block(par_num++, "CDU");
4205 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4207 _print_next_block(par_num++, "DMAE");
4209 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4211 _print_next_block(par_num++, "IGU");
4213 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4215 _print_next_block(par_num++, "MISC");
4227 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4228 bool *global, bool print)
4232 for (i = 0; sig; i++) {
4233 cur_bit = ((u32)0x1 << i);
4234 if (sig & cur_bit) {
4236 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4238 _print_next_block(par_num++, "MCP ROM");
4241 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4243 _print_next_block(par_num++,
4247 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4249 _print_next_block(par_num++,
4253 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4255 _print_next_block(par_num++,
4269 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4274 for (i = 0; sig; i++) {
4275 cur_bit = ((u32)0x1 << i);
4276 if (sig & cur_bit) {
4278 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4280 _print_next_block(par_num++, "PGLUE_B");
4282 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4284 _print_next_block(par_num++, "ATC");
4296 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4299 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4300 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4301 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4302 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4303 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4305 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4306 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4307 sig[0] & HW_PRTY_ASSERT_SET_0,
4308 sig[1] & HW_PRTY_ASSERT_SET_1,
4309 sig[2] & HW_PRTY_ASSERT_SET_2,
4310 sig[3] & HW_PRTY_ASSERT_SET_3,
4311 sig[4] & HW_PRTY_ASSERT_SET_4);
4314 "Parity errors detected in blocks: ");
4315 par_num = bnx2x_check_blocks_with_parity0(
4316 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4317 par_num = bnx2x_check_blocks_with_parity1(
4318 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4319 par_num = bnx2x_check_blocks_with_parity2(
4320 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4321 par_num = bnx2x_check_blocks_with_parity3(
4322 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4323 par_num = bnx2x_check_blocks_with_parity4(
4324 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4335 * bnx2x_chk_parity_attn - checks for parity attentions.
4337 * @bp: driver handle
4338 * @global: true if there was a global attention
4339 * @print: show parity attention in syslog
4341 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4343 struct attn_route attn = { {0} };
4344 int port = BP_PORT(bp);
4346 attn.sig[0] = REG_RD(bp,
4347 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4349 attn.sig[1] = REG_RD(bp,
4350 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4352 attn.sig[2] = REG_RD(bp,
4353 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4355 attn.sig[3] = REG_RD(bp,
4356 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4359 if (!CHIP_IS_E1x(bp))
4360 attn.sig[4] = REG_RD(bp,
4361 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4364 return bnx2x_parity_attn(bp, global, print, attn.sig);
4368 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4371 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4373 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4374 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4375 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4376 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4377 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4378 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4379 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4380 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4381 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4382 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4384 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4385 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4387 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4388 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4389 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4390 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4391 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4392 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4393 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4394 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4396 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4397 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4398 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4399 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4400 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4401 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4402 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4403 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4404 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4405 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4406 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4407 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4408 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4409 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4410 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4413 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4414 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4415 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4416 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4417 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4422 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4424 struct attn_route attn, *group_mask;
4425 int port = BP_PORT(bp);
4430 bool global = false;
4432 /* need to take HW lock because MCP or other port might also
4433 try to handle this event */
4434 bnx2x_acquire_alr(bp);
4436 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4437 #ifndef BNX2X_STOP_ON_ERROR
4438 bp->recovery_state = BNX2X_RECOVERY_INIT;
4439 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4440 /* Disable HW interrupts */
4441 bnx2x_int_disable(bp);
4442 /* In case of parity errors don't handle attentions so that
4443 * other function would "see" parity errors.
4448 bnx2x_release_alr(bp);
4452 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4453 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4454 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4455 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4456 if (!CHIP_IS_E1x(bp))
4458 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4462 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4463 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4465 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4466 if (deasserted & (1 << index)) {
4467 group_mask = &bp->attn_group[index];
4469 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4471 group_mask->sig[0], group_mask->sig[1],
4472 group_mask->sig[2], group_mask->sig[3],
4473 group_mask->sig[4]);
4475 bnx2x_attn_int_deasserted4(bp,
4476 attn.sig[4] & group_mask->sig[4]);
4477 bnx2x_attn_int_deasserted3(bp,
4478 attn.sig[3] & group_mask->sig[3]);
4479 bnx2x_attn_int_deasserted1(bp,
4480 attn.sig[1] & group_mask->sig[1]);
4481 bnx2x_attn_int_deasserted2(bp,
4482 attn.sig[2] & group_mask->sig[2]);
4483 bnx2x_attn_int_deasserted0(bp,
4484 attn.sig[0] & group_mask->sig[0]);
4488 bnx2x_release_alr(bp);
4490 if (bp->common.int_block == INT_BLOCK_HC)
4491 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4492 COMMAND_REG_ATTN_BITS_CLR);
4494 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4497 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4498 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4499 REG_WR(bp, reg_addr, val);
4501 if (~bp->attn_state & deasserted)
4502 BNX2X_ERR("IGU ERROR\n");
4504 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4505 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4507 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4508 aeu_mask = REG_RD(bp, reg_addr);
4510 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4511 aeu_mask, deasserted);
4512 aeu_mask |= (deasserted & 0x3ff);
4513 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4515 REG_WR(bp, reg_addr, aeu_mask);
4516 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4518 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4519 bp->attn_state &= ~deasserted;
4520 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4523 static void bnx2x_attn_int(struct bnx2x *bp)
4525 /* read local copy of bits */
4526 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4528 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4530 u32 attn_state = bp->attn_state;
4532 /* look for changed bits */
4533 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4534 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4537 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4538 attn_bits, attn_ack, asserted, deasserted);
4540 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4541 BNX2X_ERR("BAD attention state\n");
4543 /* handle bits that were raised */
4545 bnx2x_attn_int_asserted(bp, asserted);
4548 bnx2x_attn_int_deasserted(bp, deasserted);
4551 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4552 u16 index, u8 op, u8 update)
4554 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4556 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4560 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4562 /* No memory barriers */
4563 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4564 mmiowb(); /* keep prod updates ordered */
4568 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4569 union event_ring_elem *elem)
4571 u8 err = elem->message.error;
4573 if (!bp->cnic_eth_dev.starting_cid ||
4574 (cid < bp->cnic_eth_dev.starting_cid &&
4575 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4578 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4580 if (unlikely(err)) {
4582 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4584 bnx2x_panic_dump(bp);
4586 bnx2x_cnic_cfc_comp(bp, cid, err);
4591 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4593 struct bnx2x_mcast_ramrod_params rparam;
4596 memset(&rparam, 0, sizeof(rparam));
4598 rparam.mcast_obj = &bp->mcast_obj;
4600 netif_addr_lock_bh(bp->dev);
4602 /* Clear pending state for the last command */
4603 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4605 /* If there are pending mcast commands - send them */
4606 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4607 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4609 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4613 netif_addr_unlock_bh(bp->dev);
4616 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4617 union event_ring_elem *elem)
4619 unsigned long ramrod_flags = 0;
4621 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4622 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4624 /* Always push next commands out, don't wait here */
4625 __set_bit(RAMROD_CONT, &ramrod_flags);
4627 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4628 case BNX2X_FILTER_MAC_PENDING:
4629 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4631 if (cid == BNX2X_ISCSI_ETH_CID(bp))
4632 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4635 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4638 case BNX2X_FILTER_MCAST_PENDING:
4639 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4640 /* This is only relevant for 57710 where multicast MACs are
4641 * configured as unicast MACs using the same ramrod.
4643 bnx2x_handle_mcast_eqe(bp);
4646 BNX2X_ERR("Unsupported classification command: %d\n",
4647 elem->message.data.eth_event.echo);
4651 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4654 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4656 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4661 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4664 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4666 netif_addr_lock_bh(bp->dev);
4668 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4670 /* Send rx_mode command again if was requested */
4671 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4672 bnx2x_set_storm_rx_mode(bp);
4674 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4676 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4677 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4679 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4682 netif_addr_unlock_bh(bp->dev);
4685 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4686 union event_ring_elem *elem)
4688 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4690 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4691 elem->message.data.vif_list_event.func_bit_map);
4692 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4693 elem->message.data.vif_list_event.func_bit_map);
4694 } else if (elem->message.data.vif_list_event.echo ==
4695 VIF_LIST_RULE_SET) {
4696 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4697 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4701 /* called with rtnl_lock */
4702 static void bnx2x_after_function_update(struct bnx2x *bp)
4705 struct bnx2x_fastpath *fp;
4706 struct bnx2x_queue_state_params queue_params = {NULL};
4707 struct bnx2x_queue_update_params *q_update_params =
4708 &queue_params.params.update;
4710 /* Send Q update command with afex vlan removal values for all Qs */
4711 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4713 /* set silent vlan removal values according to vlan mode */
4714 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4715 &q_update_params->update_flags);
4716 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4717 &q_update_params->update_flags);
4718 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4720 /* in access mode mark mask and value are 0 to strip all vlans */
4721 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4722 q_update_params->silent_removal_value = 0;
4723 q_update_params->silent_removal_mask = 0;
4725 q_update_params->silent_removal_value =
4726 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4727 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4730 for_each_eth_queue(bp, q) {
4731 /* Set the appropriate Queue object */
4733 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4735 /* send the ramrod */
4736 rc = bnx2x_queue_state_change(bp, &queue_params);
4738 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4744 fp = &bp->fp[FCOE_IDX(bp)];
4745 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4747 /* clear pending completion bit */
4748 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4750 /* mark latest Q bit */
4751 smp_mb__before_clear_bit();
4752 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4753 smp_mb__after_clear_bit();
4755 /* send Q update ramrod for FCoE Q */
4756 rc = bnx2x_queue_state_change(bp, &queue_params);
4758 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4761 /* If no FCoE ring - ACK MCP now */
4762 bnx2x_link_report(bp);
4763 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4766 /* If no FCoE ring - ACK MCP now */
4767 bnx2x_link_report(bp);
4768 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4769 #endif /* BCM_CNIC */
4772 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4773 struct bnx2x *bp, u32 cid)
4775 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4777 if (cid == BNX2X_FCOE_ETH_CID(bp))
4778 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4781 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4784 static void bnx2x_eq_int(struct bnx2x *bp)
4786 u16 hw_cons, sw_cons, sw_prod;
4787 union event_ring_elem *elem;
4791 struct bnx2x_queue_sp_obj *q_obj;
4792 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4793 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4795 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4797 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4798 * when we get the the next-page we nned to adjust so the loop
4799 * condition below will be met. The next element is the size of a
4800 * regular element and hence incrementing by 1
4802 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4805 /* This function may never run in parallel with itself for a
4806 * specific bp, thus there is no need in "paired" read memory
4809 sw_cons = bp->eq_cons;
4810 sw_prod = bp->eq_prod;
4812 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4813 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4815 for (; sw_cons != hw_cons;
4816 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4819 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4821 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4822 opcode = elem->message.opcode;
4825 /* handle eq element */
4827 case EVENT_RING_OPCODE_STAT_QUERY:
4828 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4829 "got statistics comp event %d\n",
4831 /* nothing to do with stats comp */
4834 case EVENT_RING_OPCODE_CFC_DEL:
4835 /* handle according to cid range */
4837 * we may want to verify here that the bp state is
4841 "got delete ramrod for MULTI[%d]\n", cid);
4843 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4846 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4848 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4855 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4856 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
4857 if (f_obj->complete_cmd(bp, f_obj,
4858 BNX2X_F_CMD_TX_STOP))
4860 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4863 case EVENT_RING_OPCODE_START_TRAFFIC:
4864 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
4865 if (f_obj->complete_cmd(bp, f_obj,
4866 BNX2X_F_CMD_TX_START))
4868 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4870 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4871 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
4872 "AFEX: ramrod completed FUNCTION_UPDATE\n");
4873 f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_AFEX_UPDATE);
4875 /* We will perform the Queues update from sp_rtnl task
4876 * as all Queue SP operations should run under
4879 smp_mb__before_clear_bit();
4880 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
4881 &bp->sp_rtnl_state);
4882 smp_mb__after_clear_bit();
4884 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4887 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
4888 f_obj->complete_cmd(bp, f_obj,
4889 BNX2X_F_CMD_AFEX_VIFLISTS);
4890 bnx2x_after_afex_vif_lists(bp, elem);
4892 case EVENT_RING_OPCODE_FUNCTION_START:
4893 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4894 "got FUNC_START ramrod\n");
4895 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4900 case EVENT_RING_OPCODE_FUNCTION_STOP:
4901 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4902 "got FUNC_STOP ramrod\n");
4903 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4909 switch (opcode | bp->state) {
4910 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4912 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4913 BNX2X_STATE_OPENING_WAIT4_PORT):
4914 cid = elem->message.data.eth_event.echo &
4916 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4918 rss_raw->clear_pending(rss_raw);
4921 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4922 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4923 case (EVENT_RING_OPCODE_SET_MAC |
4924 BNX2X_STATE_CLOSING_WAIT4_HALT):
4925 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4927 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4929 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4930 BNX2X_STATE_CLOSING_WAIT4_HALT):
4931 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4932 bnx2x_handle_classification_eqe(bp, elem);
4935 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4937 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4939 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4940 BNX2X_STATE_CLOSING_WAIT4_HALT):
4941 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4942 bnx2x_handle_mcast_eqe(bp);
4945 case (EVENT_RING_OPCODE_FILTERS_RULES |
4947 case (EVENT_RING_OPCODE_FILTERS_RULES |
4949 case (EVENT_RING_OPCODE_FILTERS_RULES |
4950 BNX2X_STATE_CLOSING_WAIT4_HALT):
4951 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4952 bnx2x_handle_rx_mode_eqe(bp);
4955 /* unknown event log error and continue */
4956 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4957 elem->message.opcode, bp->state);
4963 smp_mb__before_atomic_inc();
4964 atomic_add(spqe_cnt, &bp->eq_spq_left);
4966 bp->eq_cons = sw_cons;
4967 bp->eq_prod = sw_prod;
4968 /* Make sure that above mem writes were issued towards the memory */
4971 /* update producer */
4972 bnx2x_update_eq_prod(bp, bp->eq_prod);
4975 static void bnx2x_sp_task(struct work_struct *work)
4977 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4980 status = bnx2x_update_dsb_idx(bp);
4981 /* if (status == 0) */
4982 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4984 DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
4987 if (status & BNX2X_DEF_SB_ATT_IDX) {
4989 status &= ~BNX2X_DEF_SB_ATT_IDX;
4992 /* SP events: STAT_QUERY and others */
4993 if (status & BNX2X_DEF_SB_IDX) {
4995 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4997 if ((!NO_FCOE(bp)) &&
4998 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5000 * Prevent local bottom-halves from running as
5001 * we are going to change the local NAPI list.
5004 napi_schedule(&bnx2x_fcoe(bp, napi));
5008 /* Handle EQ completions */
5011 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5012 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5014 status &= ~BNX2X_DEF_SB_IDX;
5017 if (unlikely(status))
5018 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
5021 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5022 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5024 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5025 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5027 bnx2x_link_report(bp);
5028 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5032 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5034 struct net_device *dev = dev_instance;
5035 struct bnx2x *bp = netdev_priv(dev);
5037 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5038 IGU_INT_DISABLE, 0);
5040 #ifdef BNX2X_STOP_ON_ERROR
5041 if (unlikely(bp->panic))
5047 struct cnic_ops *c_ops;
5050 c_ops = rcu_dereference(bp->cnic_ops);
5052 c_ops->cnic_handler(bp->cnic_data, NULL);
5056 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
5061 /* end of slow path */
5064 void bnx2x_drv_pulse(struct bnx2x *bp)
5066 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5067 bp->fw_drv_pulse_wr_seq);
5071 static void bnx2x_timer(unsigned long data)
5073 struct bnx2x *bp = (struct bnx2x *) data;
5075 if (!netif_running(bp->dev))
5078 if (!BP_NOMCP(bp)) {
5079 int mb_idx = BP_FW_MB_IDX(bp);
5083 ++bp->fw_drv_pulse_wr_seq;
5084 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5085 /* TBD - add SYSTEM_TIME */
5086 drv_pulse = bp->fw_drv_pulse_wr_seq;
5087 bnx2x_drv_pulse(bp);
5089 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5090 MCP_PULSE_SEQ_MASK);
5091 /* The delta between driver pulse and mcp response
5092 * should be 1 (before mcp response) or 0 (after mcp response)
5094 if ((drv_pulse != mcp_pulse) &&
5095 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5096 /* someone lost a heartbeat... */
5097 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5098 drv_pulse, mcp_pulse);
5102 if (bp->state == BNX2X_STATE_OPEN)
5103 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5105 mod_timer(&bp->timer, jiffies + bp->current_interval);
5108 /* end of Statistics */
5113 * nic init service functions
5116 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5119 if (!(len%4) && !(addr%4))
5120 for (i = 0; i < len; i += 4)
5121 REG_WR(bp, addr + i, fill);
5123 for (i = 0; i < len; i++)
5124 REG_WR8(bp, addr + i, fill);
5128 /* helper: writes FP SP data to FW - data_size in dwords */
5129 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5135 for (index = 0; index < data_size; index++)
5136 REG_WR(bp, BAR_CSTRORM_INTMEM +
5137 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5139 *(sb_data_p + index));
5142 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5146 struct hc_status_block_data_e2 sb_data_e2;
5147 struct hc_status_block_data_e1x sb_data_e1x;
5149 /* disable the function first */
5150 if (!CHIP_IS_E1x(bp)) {
5151 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5152 sb_data_e2.common.state = SB_DISABLED;
5153 sb_data_e2.common.p_func.vf_valid = false;
5154 sb_data_p = (u32 *)&sb_data_e2;
5155 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5157 memset(&sb_data_e1x, 0,
5158 sizeof(struct hc_status_block_data_e1x));
5159 sb_data_e1x.common.state = SB_DISABLED;
5160 sb_data_e1x.common.p_func.vf_valid = false;
5161 sb_data_p = (u32 *)&sb_data_e1x;
5162 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5164 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5166 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5167 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5168 CSTORM_STATUS_BLOCK_SIZE);
5169 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5170 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5171 CSTORM_SYNC_BLOCK_SIZE);
5174 /* helper: writes SP SB data to FW */
5175 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5176 struct hc_sp_status_block_data *sp_sb_data)
5178 int func = BP_FUNC(bp);
5180 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5181 REG_WR(bp, BAR_CSTRORM_INTMEM +
5182 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5184 *((u32 *)sp_sb_data + i));
5187 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5189 int func = BP_FUNC(bp);
5190 struct hc_sp_status_block_data sp_sb_data;
5191 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5193 sp_sb_data.state = SB_DISABLED;
5194 sp_sb_data.p_func.vf_valid = false;
5196 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5198 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5199 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5200 CSTORM_SP_STATUS_BLOCK_SIZE);
5201 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5202 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5203 CSTORM_SP_SYNC_BLOCK_SIZE);
5208 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5209 int igu_sb_id, int igu_seg_id)
5211 hc_sm->igu_sb_id = igu_sb_id;
5212 hc_sm->igu_seg_id = igu_seg_id;
5213 hc_sm->timer_value = 0xFF;
5214 hc_sm->time_to_expire = 0xFFFFFFFF;
5218 /* allocates state machine ids. */
5219 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5221 /* zero out state machine indices */
5223 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5226 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5227 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5228 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5229 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5233 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5234 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5237 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5238 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5239 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5240 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5241 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5242 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5243 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5244 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5247 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5248 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5252 struct hc_status_block_data_e2 sb_data_e2;
5253 struct hc_status_block_data_e1x sb_data_e1x;
5254 struct hc_status_block_sm *hc_sm_p;
5258 if (CHIP_INT_MODE_IS_BC(bp))
5259 igu_seg_id = HC_SEG_ACCESS_NORM;
5261 igu_seg_id = IGU_SEG_ACCESS_NORM;
5263 bnx2x_zero_fp_sb(bp, fw_sb_id);
5265 if (!CHIP_IS_E1x(bp)) {
5266 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5267 sb_data_e2.common.state = SB_ENABLED;
5268 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5269 sb_data_e2.common.p_func.vf_id = vfid;
5270 sb_data_e2.common.p_func.vf_valid = vf_valid;
5271 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5272 sb_data_e2.common.same_igu_sb_1b = true;
5273 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5274 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5275 hc_sm_p = sb_data_e2.common.state_machine;
5276 sb_data_p = (u32 *)&sb_data_e2;
5277 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5278 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5280 memset(&sb_data_e1x, 0,
5281 sizeof(struct hc_status_block_data_e1x));
5282 sb_data_e1x.common.state = SB_ENABLED;
5283 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5284 sb_data_e1x.common.p_func.vf_id = 0xff;
5285 sb_data_e1x.common.p_func.vf_valid = false;
5286 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5287 sb_data_e1x.common.same_igu_sb_1b = true;
5288 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5289 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5290 hc_sm_p = sb_data_e1x.common.state_machine;
5291 sb_data_p = (u32 *)&sb_data_e1x;
5292 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5293 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5296 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5297 igu_sb_id, igu_seg_id);
5298 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5299 igu_sb_id, igu_seg_id);
5301 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5303 /* write indecies to HW */
5304 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5307 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5308 u16 tx_usec, u16 rx_usec)
5310 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5312 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5313 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5315 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5316 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5318 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5319 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5323 static void bnx2x_init_def_sb(struct bnx2x *bp)
5325 struct host_sp_status_block *def_sb = bp->def_status_blk;
5326 dma_addr_t mapping = bp->def_status_blk_mapping;
5327 int igu_sp_sb_index;
5329 int port = BP_PORT(bp);
5330 int func = BP_FUNC(bp);
5331 int reg_offset, reg_offset_en5;
5334 struct hc_sp_status_block_data sp_sb_data;
5335 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5337 if (CHIP_INT_MODE_IS_BC(bp)) {
5338 igu_sp_sb_index = DEF_SB_IGU_ID;
5339 igu_seg_id = HC_SEG_ACCESS_DEF;
5341 igu_sp_sb_index = bp->igu_dsb_id;
5342 igu_seg_id = IGU_SEG_ACCESS_DEF;
5346 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5347 atten_status_block);
5348 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5352 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5353 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5354 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5355 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5356 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5358 /* take care of sig[0]..sig[4] */
5359 for (sindex = 0; sindex < 4; sindex++)
5360 bp->attn_group[index].sig[sindex] =
5361 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5363 if (!CHIP_IS_E1x(bp))
5365 * enable5 is separate from the rest of the registers,
5366 * and therefore the address skip is 4
5367 * and not 16 between the different groups
5369 bp->attn_group[index].sig[4] = REG_RD(bp,
5370 reg_offset_en5 + 0x4*index);
5372 bp->attn_group[index].sig[4] = 0;
5375 if (bp->common.int_block == INT_BLOCK_HC) {
5376 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5377 HC_REG_ATTN_MSG0_ADDR_L);
5379 REG_WR(bp, reg_offset, U64_LO(section));
5380 REG_WR(bp, reg_offset + 4, U64_HI(section));
5381 } else if (!CHIP_IS_E1x(bp)) {
5382 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5383 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5386 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5389 bnx2x_zero_sp_sb(bp);
5391 sp_sb_data.state = SB_ENABLED;
5392 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5393 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5394 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5395 sp_sb_data.igu_seg_id = igu_seg_id;
5396 sp_sb_data.p_func.pf_id = func;
5397 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5398 sp_sb_data.p_func.vf_id = 0xff;
5400 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5402 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5405 void bnx2x_update_coalesce(struct bnx2x *bp)
5409 for_each_eth_queue(bp, i)
5410 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5411 bp->tx_ticks, bp->rx_ticks);
5414 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5416 spin_lock_init(&bp->spq_lock);
5417 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5419 bp->spq_prod_idx = 0;
5420 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5421 bp->spq_prod_bd = bp->spq;
5422 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5425 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5428 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5429 union event_ring_elem *elem =
5430 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5432 elem->next_page.addr.hi =
5433 cpu_to_le32(U64_HI(bp->eq_mapping +
5434 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5435 elem->next_page.addr.lo =
5436 cpu_to_le32(U64_LO(bp->eq_mapping +
5437 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5440 bp->eq_prod = NUM_EQ_DESC;
5441 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5442 /* we want a warning message before it gets rought... */
5443 atomic_set(&bp->eq_spq_left,
5444 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5448 /* called with netif_addr_lock_bh() */
5449 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5450 unsigned long rx_mode_flags,
5451 unsigned long rx_accept_flags,
5452 unsigned long tx_accept_flags,
5453 unsigned long ramrod_flags)
5455 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5458 memset(&ramrod_param, 0, sizeof(ramrod_param));
5460 /* Prepare ramrod parameters */
5461 ramrod_param.cid = 0;
5462 ramrod_param.cl_id = cl_id;
5463 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5464 ramrod_param.func_id = BP_FUNC(bp);
5466 ramrod_param.pstate = &bp->sp_state;
5467 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5469 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5470 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5472 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5474 ramrod_param.ramrod_flags = ramrod_flags;
5475 ramrod_param.rx_mode_flags = rx_mode_flags;
5477 ramrod_param.rx_accept_flags = rx_accept_flags;
5478 ramrod_param.tx_accept_flags = tx_accept_flags;
5480 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5482 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5487 /* called with netif_addr_lock_bh() */
5488 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5490 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5491 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5496 /* Configure rx_mode of FCoE Queue */
5497 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5500 switch (bp->rx_mode) {
5501 case BNX2X_RX_MODE_NONE:
5503 * 'drop all' supersedes any accept flags that may have been
5504 * passed to the function.
5507 case BNX2X_RX_MODE_NORMAL:
5508 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5509 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5510 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5512 /* internal switching mode */
5513 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5514 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5515 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5518 case BNX2X_RX_MODE_ALLMULTI:
5519 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5520 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5521 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5523 /* internal switching mode */
5524 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5525 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5526 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5529 case BNX2X_RX_MODE_PROMISC:
5530 /* According to deffinition of SI mode, iface in promisc mode
5531 * should receive matched and unmatched (in resolution of port)
5534 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5535 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5536 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5537 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5539 /* internal switching mode */
5540 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5541 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5544 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5546 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5550 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5554 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5555 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5556 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5559 __set_bit(RAMROD_RX, &ramrod_flags);
5560 __set_bit(RAMROD_TX, &ramrod_flags);
5562 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5563 tx_accept_flags, ramrod_flags);
5566 static void bnx2x_init_internal_common(struct bnx2x *bp)
5572 * In switch independent mode, the TSTORM needs to accept
5573 * packets that failed classification, since approximate match
5574 * mac addresses aren't written to NIG LLH
5576 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5577 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5578 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5579 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5580 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5582 /* Zero this manually as its initialization is
5583 currently missing in the initTool */
5584 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5585 REG_WR(bp, BAR_USTRORM_INTMEM +
5586 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5587 if (!CHIP_IS_E1x(bp)) {
5588 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5589 CHIP_INT_MODE_IS_BC(bp) ?
5590 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5594 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5596 switch (load_code) {
5597 case FW_MSG_CODE_DRV_LOAD_COMMON:
5598 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5599 bnx2x_init_internal_common(bp);
5602 case FW_MSG_CODE_DRV_LOAD_PORT:
5606 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5607 /* internal memory per function is
5608 initialized inside bnx2x_pf_init */
5612 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5617 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5619 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5622 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5624 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5627 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5629 if (CHIP_IS_E1x(fp->bp))
5630 return BP_L_ID(fp->bp) + fp->index;
5631 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5632 return bnx2x_fp_igu_sb_id(fp);
5635 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5637 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5639 unsigned long q_type = 0;
5640 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5641 fp->rx_queue = fp_idx;
5643 fp->cl_id = bnx2x_fp_cl_id(fp);
5644 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5645 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5646 /* qZone id equals to FW (per path) client id */
5647 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5650 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5652 /* Setup SB indicies */
5653 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5655 /* Configure Queue State object */
5656 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5657 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5659 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5662 for_each_cos_in_tx_queue(fp, cos) {
5663 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5664 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5665 FP_COS_TO_TXQ(fp, cos, bp),
5666 BNX2X_TX_SB_INDEX_BASE + cos, fp);
5667 cids[cos] = fp->txdata_ptr[cos]->cid;
5670 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5671 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5672 bnx2x_sp_mapping(bp, q_rdata), q_type);
5675 * Configure classification DBs: Always enable Tx switching
5677 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5679 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5680 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5682 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5683 fp->fw_sb_id, fp->igu_sb_id);
5685 bnx2x_update_fpsb_idx(fp);
5688 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5692 for (i = 1; i <= NUM_TX_RINGS; i++) {
5693 struct eth_tx_next_bd *tx_next_bd =
5694 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5696 tx_next_bd->addr_hi =
5697 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5698 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5699 tx_next_bd->addr_lo =
5700 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5701 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5704 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5705 txdata->tx_db.data.zero_fill1 = 0;
5706 txdata->tx_db.data.prod = 0;
5708 txdata->tx_pkt_prod = 0;
5709 txdata->tx_pkt_cons = 0;
5710 txdata->tx_bd_prod = 0;
5711 txdata->tx_bd_cons = 0;
5715 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5720 for_each_tx_queue(bp, i)
5721 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5722 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5725 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5729 for_each_eth_queue(bp, i)
5730 bnx2x_init_eth_fp(bp, i);
5733 bnx2x_init_fcoe_fp(bp);
5735 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5736 BNX2X_VF_ID_INVALID, false,
5737 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5741 /* Initialize MOD_ABS interrupts */
5742 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5743 bp->common.shmem_base, bp->common.shmem2_base,
5745 /* ensure status block indices were read */
5748 bnx2x_init_def_sb(bp);
5749 bnx2x_update_dsb_idx(bp);
5750 bnx2x_init_rx_rings(bp);
5751 bnx2x_init_tx_rings(bp);
5752 bnx2x_init_sp_ring(bp);
5753 bnx2x_init_eq_ring(bp);
5754 bnx2x_init_internal(bp, load_code);
5756 bnx2x_stats_init(bp);
5758 /* flush all before enabling interrupts */
5762 bnx2x_int_enable(bp);
5764 /* Check for SPIO5 */
5765 bnx2x_attn_int_deasserted0(bp,
5766 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5767 AEU_INPUTS_ATTN_BITS_SPIO5);
5770 /* end of nic init */
5773 * gzip service functions
5776 static int bnx2x_gunzip_init(struct bnx2x *bp)
5778 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5779 &bp->gunzip_mapping, GFP_KERNEL);
5780 if (bp->gunzip_buf == NULL)
5783 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5784 if (bp->strm == NULL)
5787 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5788 if (bp->strm->workspace == NULL)
5798 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5799 bp->gunzip_mapping);
5800 bp->gunzip_buf = NULL;
5803 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5807 static void bnx2x_gunzip_end(struct bnx2x *bp)
5810 vfree(bp->strm->workspace);
5815 if (bp->gunzip_buf) {
5816 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5817 bp->gunzip_mapping);
5818 bp->gunzip_buf = NULL;
5822 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5826 /* check gzip header */
5827 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5828 BNX2X_ERR("Bad gzip header\n");
5836 if (zbuf[3] & FNAME)
5837 while ((zbuf[n++] != 0) && (n < len));
5839 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5840 bp->strm->avail_in = len - n;
5841 bp->strm->next_out = bp->gunzip_buf;
5842 bp->strm->avail_out = FW_BUF_SIZE;
5844 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5848 rc = zlib_inflate(bp->strm, Z_FINISH);
5849 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5850 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5853 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5854 if (bp->gunzip_outlen & 0x3)
5856 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5858 bp->gunzip_outlen >>= 2;
5860 zlib_inflateEnd(bp->strm);
5862 if (rc == Z_STREAM_END)
5868 /* nic load/unload */
5871 * General service functions
5874 /* send a NIG loopback debug packet */
5875 static void bnx2x_lb_pckt(struct bnx2x *bp)
5879 /* Ethernet source and destination addresses */
5880 wb_write[0] = 0x55555555;
5881 wb_write[1] = 0x55555555;
5882 wb_write[2] = 0x20; /* SOP */
5883 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5885 /* NON-IP protocol */
5886 wb_write[0] = 0x09000000;
5887 wb_write[1] = 0x55555555;
5888 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5889 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5892 /* some of the internal memories
5893 * are not directly readable from the driver
5894 * to test them we send debug packets
5896 static int bnx2x_int_mem_test(struct bnx2x *bp)
5902 if (CHIP_REV_IS_FPGA(bp))
5904 else if (CHIP_REV_IS_EMUL(bp))
5909 /* Disable inputs of parser neighbor blocks */
5910 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5911 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5912 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5913 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5915 /* Write 0 to parser credits for CFC search request */
5916 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5918 /* send Ethernet packet */
5921 /* TODO do i reset NIG statistic? */
5922 /* Wait until NIG register shows 1 packet of size 0x10 */
5923 count = 1000 * factor;
5926 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5927 val = *bnx2x_sp(bp, wb_data[0]);
5935 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5939 /* Wait until PRS register shows 1 packet */
5940 count = 1000 * factor;
5942 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5950 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5954 /* Reset and init BRB, PRS */
5955 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5957 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5959 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5960 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5962 DP(NETIF_MSG_HW, "part2\n");
5964 /* Disable inputs of parser neighbor blocks */
5965 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5966 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5967 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5968 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5970 /* Write 0 to parser credits for CFC search request */
5971 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5973 /* send 10 Ethernet packets */
5974 for (i = 0; i < 10; i++)
5977 /* Wait until NIG register shows 10 + 1
5978 packets of size 11*0x10 = 0xb0 */
5979 count = 1000 * factor;
5982 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5983 val = *bnx2x_sp(bp, wb_data[0]);
5991 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5995 /* Wait until PRS register shows 2 packets */
5996 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5998 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6000 /* Write 1 to parser credits for CFC search request */
6001 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6003 /* Wait until PRS register shows 3 packets */
6004 msleep(10 * factor);
6005 /* Wait until NIG register shows 1 packet of size 0x10 */
6006 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6008 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6010 /* clear NIG EOP FIFO */
6011 for (i = 0; i < 11; i++)
6012 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6013 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6015 BNX2X_ERR("clear of NIG failed\n");
6019 /* Reset and init BRB, PRS, NIG */
6020 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6022 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6024 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6025 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6028 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6031 /* Enable inputs of parser neighbor blocks */
6032 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6033 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6034 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6035 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6037 DP(NETIF_MSG_HW, "done\n");
6042 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6044 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6045 if (!CHIP_IS_E1x(bp))
6046 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6048 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6049 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6050 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6052 * mask read length error interrupts in brb for parser
6053 * (parsing unit and 'checksum and crc' unit)
6054 * these errors are legal (PU reads fixed length and CAC can cause
6055 * read length error on truncated packets)
6057 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6058 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6059 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6060 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6061 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6062 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6063 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6064 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6065 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6066 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6067 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6068 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6069 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6070 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6071 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6072 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6073 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6074 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6075 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6077 if (CHIP_REV_IS_FPGA(bp))
6078 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
6079 else if (!CHIP_IS_E1x(bp))
6080 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
6081 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
6082 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
6083 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
6084 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
6085 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
6087 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
6088 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6089 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6090 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6091 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6093 if (!CHIP_IS_E1x(bp))
6094 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6095 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6097 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6098 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6099 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6100 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6103 static void bnx2x_reset_common(struct bnx2x *bp)
6108 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6111 if (CHIP_IS_E3(bp)) {
6112 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6113 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6116 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6119 static void bnx2x_setup_dmae(struct bnx2x *bp)
6122 spin_lock_init(&bp->dmae_lock);
6125 static void bnx2x_init_pxp(struct bnx2x *bp)
6128 int r_order, w_order;
6130 pci_read_config_word(bp->pdev,
6131 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
6132 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6133 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6135 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6137 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6141 bnx2x_init_pxp_arb(bp, r_order, w_order);
6144 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6154 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6155 SHARED_HW_CFG_FAN_FAILURE_MASK;
6157 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6161 * The fan failure mechanism is usually related to the PHY type since
6162 * the power consumption of the board is affected by the PHY. Currently,
6163 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6165 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6166 for (port = PORT_0; port < PORT_MAX; port++) {
6168 bnx2x_fan_failure_det_req(
6170 bp->common.shmem_base,
6171 bp->common.shmem2_base,
6175 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6177 if (is_required == 0)
6180 /* Fan failure is indicated by SPIO 5 */
6181 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
6182 MISC_REGISTERS_SPIO_INPUT_HI_Z);
6184 /* set to active low mode */
6185 val = REG_RD(bp, MISC_REG_SPIO_INT);
6186 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
6187 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
6188 REG_WR(bp, MISC_REG_SPIO_INT, val);
6190 /* enable interrupt to signal the IGU */
6191 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6192 val |= (1 << MISC_REGISTERS_SPIO_5);
6193 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6196 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
6202 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
6205 switch (BP_ABS_FUNC(bp)) {
6207 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
6210 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
6213 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
6216 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
6219 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
6222 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
6225 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
6228 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
6234 REG_WR(bp, offset, pretend_func_num);
6236 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
6239 void bnx2x_pf_disable(struct bnx2x *bp)
6241 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6242 val &= ~IGU_PF_CONF_FUNC_EN;
6244 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6245 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6246 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6249 static void bnx2x__common_init_phy(struct bnx2x *bp)
6251 u32 shmem_base[2], shmem2_base[2];
6252 shmem_base[0] = bp->common.shmem_base;
6253 shmem2_base[0] = bp->common.shmem2_base;
6254 if (!CHIP_IS_E1x(bp)) {
6256 SHMEM2_RD(bp, other_shmem_base_addr);
6258 SHMEM2_RD(bp, other_shmem2_base_addr);
6260 bnx2x_acquire_phy_lock(bp);
6261 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6262 bp->common.chip_id);
6263 bnx2x_release_phy_lock(bp);
6267 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6269 * @bp: driver handle
6271 static int bnx2x_init_hw_common(struct bnx2x *bp)
6275 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6278 * take the UNDI lock to protect undi_unload flow from accessing
6279 * registers while we're resetting the chip
6281 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6283 bnx2x_reset_common(bp);
6284 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6287 if (CHIP_IS_E3(bp)) {
6288 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6289 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6291 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6293 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6295 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6297 if (!CHIP_IS_E1x(bp)) {
6301 * 4-port mode or 2-port mode we need to turn of master-enable
6302 * for everyone, after that, turn it back on for self.
6303 * so, we disregard multi-function or not, and always disable
6304 * for all functions on the given path, this means 0,2,4,6 for
6305 * path 0 and 1,3,5,7 for path 1
6307 for (abs_func_id = BP_PATH(bp);
6308 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6309 if (abs_func_id == BP_ABS_FUNC(bp)) {
6311 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6316 bnx2x_pretend_func(bp, abs_func_id);
6317 /* clear pf enable */
6318 bnx2x_pf_disable(bp);
6319 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6323 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6324 if (CHIP_IS_E1(bp)) {
6325 /* enable HW interrupt from PXP on USDM overflow
6326 bit 16 on INT_MASK_0 */
6327 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6330 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6334 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6335 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6336 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6337 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6338 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6339 /* make sure this value is 0 */
6340 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6342 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6343 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6344 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6345 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6346 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6349 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6351 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6352 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6354 /* let the HW do it's magic ... */
6356 /* finish PXP init */
6357 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6359 BNX2X_ERR("PXP2 CFG failed\n");
6362 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6364 BNX2X_ERR("PXP2 RD_INIT failed\n");
6368 /* Timers bug workaround E2 only. We need to set the entire ILT to
6369 * have entries with value "0" and valid bit on.
6370 * This needs to be done by the first PF that is loaded in a path
6371 * (i.e. common phase)
6373 if (!CHIP_IS_E1x(bp)) {
6374 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6375 * (i.e. vnic3) to start even if it is marked as "scan-off".
6376 * This occurs when a different function (func2,3) is being marked
6377 * as "scan-off". Real-life scenario for example: if a driver is being
6378 * load-unloaded while func6,7 are down. This will cause the timer to access
6379 * the ilt, translate to a logical address and send a request to read/write.
6380 * Since the ilt for the function that is down is not valid, this will cause
6381 * a translation error which is unrecoverable.
6382 * The Workaround is intended to make sure that when this happens nothing fatal
6383 * will occur. The workaround:
6384 * 1. First PF driver which loads on a path will:
6385 * a. After taking the chip out of reset, by using pretend,
6386 * it will write "0" to the following registers of
6388 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6389 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6390 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6391 * And for itself it will write '1' to
6392 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6393 * dmae-operations (writing to pram for example.)
6394 * note: can be done for only function 6,7 but cleaner this
6396 * b. Write zero+valid to the entire ILT.
6397 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6398 * VNIC3 (of that port). The range allocated will be the
6399 * entire ILT. This is needed to prevent ILT range error.
6400 * 2. Any PF driver load flow:
6401 * a. ILT update with the physical addresses of the allocated
6403 * b. Wait 20msec. - note that this timeout is needed to make
6404 * sure there are no requests in one of the PXP internal
6405 * queues with "old" ILT addresses.
6406 * c. PF enable in the PGLC.
6407 * d. Clear the was_error of the PF in the PGLC. (could have
6408 * occured while driver was down)
6409 * e. PF enable in the CFC (WEAK + STRONG)
6410 * f. Timers scan enable
6411 * 3. PF driver unload flow:
6412 * a. Clear the Timers scan_en.
6413 * b. Polling for scan_on=0 for that PF.
6414 * c. Clear the PF enable bit in the PXP.
6415 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6416 * e. Write zero+valid to all ILT entries (The valid bit must
6418 * f. If this is VNIC 3 of a port then also init
6419 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6420 * to the last enrty in the ILT.
6423 * Currently the PF error in the PGLC is non recoverable.
6424 * In the future the there will be a recovery routine for this error.
6425 * Currently attention is masked.
6426 * Having an MCP lock on the load/unload process does not guarantee that
6427 * there is no Timer disable during Func6/7 enable. This is because the
6428 * Timers scan is currently being cleared by the MCP on FLR.
6429 * Step 2.d can be done only for PF6/7 and the driver can also check if
6430 * there is error before clearing it. But the flow above is simpler and
6432 * All ILT entries are written by zero+valid and not just PF6/7
6433 * ILT entries since in the future the ILT entries allocation for
6434 * PF-s might be dynamic.
6436 struct ilt_client_info ilt_cli;
6437 struct bnx2x_ilt ilt;
6438 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6439 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6441 /* initialize dummy TM client */
6443 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6444 ilt_cli.client_num = ILT_CLIENT_TM;
6446 /* Step 1: set zeroes to all ilt page entries with valid bit on
6447 * Step 2: set the timers first/last ilt entry to point
6448 * to the entire range to prevent ILT range error for 3rd/4th
6449 * vnic (this code assumes existance of the vnic)
6451 * both steps performed by call to bnx2x_ilt_client_init_op()
6452 * with dummy TM client
6454 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6455 * and his brother are split registers
6457 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6458 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6459 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6461 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6462 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6463 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6467 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6468 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6470 if (!CHIP_IS_E1x(bp)) {
6471 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6472 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6473 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6475 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6477 /* let the HW do it's magic ... */
6480 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6481 } while (factor-- && (val != 1));
6484 BNX2X_ERR("ATC_INIT failed\n");
6489 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6491 /* clean the DMAE memory */
6493 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6495 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6497 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6499 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6501 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6503 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6504 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6505 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6506 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6508 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6511 /* QM queues pointers table */
6512 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6514 /* soft reset pulse */
6515 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6516 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6519 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6522 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6523 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6524 if (!CHIP_REV_IS_SLOW(bp))
6525 /* enable hw interrupt from doorbell Q */
6526 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6528 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6530 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6531 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6533 if (!CHIP_IS_E1(bp))
6534 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6536 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6537 if (IS_MF_AFEX(bp)) {
6538 /* configure that VNTag and VLAN headers must be
6539 * received in afex mode
6541 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6542 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6543 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6544 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6545 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6547 /* Bit-map indicating which L2 hdrs may appear
6548 * after the basic Ethernet header
6550 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6551 bp->path_has_ovlan ? 7 : 6);
6555 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6556 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6557 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6558 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6560 if (!CHIP_IS_E1x(bp)) {
6561 /* reset VFC memories */
6562 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6563 VFC_MEMORIES_RST_REG_CAM_RST |
6564 VFC_MEMORIES_RST_REG_RAM_RST);
6565 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6566 VFC_MEMORIES_RST_REG_CAM_RST |
6567 VFC_MEMORIES_RST_REG_RAM_RST);
6572 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6573 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6574 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6575 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6578 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6580 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6583 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6584 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6585 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6587 if (!CHIP_IS_E1x(bp)) {
6588 if (IS_MF_AFEX(bp)) {
6589 /* configure that VNTag and VLAN headers must be
6592 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6593 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6594 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6595 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6596 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6598 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6599 bp->path_has_ovlan ? 7 : 6);
6603 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6605 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6608 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6609 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6610 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6611 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6612 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6613 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6614 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6615 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6616 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6617 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6619 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6621 if (sizeof(union cdu_context) != 1024)
6622 /* we currently assume that a context is 1024 bytes */
6623 dev_alert(&bp->pdev->dev,
6624 "please adjust the size of cdu_context(%ld)\n",
6625 (long)sizeof(union cdu_context));
6627 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6628 val = (4 << 24) + (0 << 12) + 1024;
6629 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6631 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6632 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6633 /* enable context validation interrupt from CFC */
6634 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6636 /* set the thresholds to prevent CFC/CDU race */
6637 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6639 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6641 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6642 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6644 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6645 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6647 /* Reset PCIE errors for debug */
6648 REG_WR(bp, 0x2814, 0xffffffff);
6649 REG_WR(bp, 0x3820, 0xffffffff);
6651 if (!CHIP_IS_E1x(bp)) {
6652 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6653 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6654 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6655 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6656 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6657 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6658 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6659 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6660 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6661 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6662 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6665 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6666 if (!CHIP_IS_E1(bp)) {
6667 /* in E3 this done in per-port section */
6668 if (!CHIP_IS_E3(bp))
6669 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6671 if (CHIP_IS_E1H(bp))
6672 /* not applicable for E2 (and above ...) */
6673 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6675 if (CHIP_REV_IS_SLOW(bp))
6678 /* finish CFC init */
6679 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6681 BNX2X_ERR("CFC LL_INIT failed\n");
6684 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6686 BNX2X_ERR("CFC AC_INIT failed\n");
6689 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6691 BNX2X_ERR("CFC CAM_INIT failed\n");
6694 REG_WR(bp, CFC_REG_DEBUG0, 0);
6696 if (CHIP_IS_E1(bp)) {
6697 /* read NIG statistic
6698 to see if this is our first up since powerup */
6699 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6700 val = *bnx2x_sp(bp, wb_data[0]);
6702 /* do internal memory self test */
6703 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6704 BNX2X_ERR("internal mem self test failed\n");
6709 bnx2x_setup_fan_failure_detection(bp);
6711 /* clear PXP2 attentions */
6712 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6714 bnx2x_enable_blocks_attention(bp);
6715 bnx2x_enable_blocks_parity(bp);
6717 if (!BP_NOMCP(bp)) {
6718 if (CHIP_IS_E1x(bp))
6719 bnx2x__common_init_phy(bp);
6721 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6727 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6729 * @bp: driver handle
6731 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6733 int rc = bnx2x_init_hw_common(bp);
6738 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6740 bnx2x__common_init_phy(bp);
6745 static int bnx2x_init_hw_port(struct bnx2x *bp)
6747 int port = BP_PORT(bp);
6748 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6752 bnx2x__link_reset(bp);
6754 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
6756 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6758 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6759 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6760 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6762 /* Timers bug workaround: disables the pf_master bit in pglue at
6763 * common phase, we need to enable it here before any dmae access are
6764 * attempted. Therefore we manually added the enable-master to the
6765 * port phase (it also happens in the function phase)
6767 if (!CHIP_IS_E1x(bp))
6768 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6770 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6771 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6772 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6773 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6775 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6776 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6777 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6778 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6780 /* QM cid (connection) count */
6781 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6784 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6785 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6786 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6789 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6791 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6792 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6795 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6796 else if (bp->dev->mtu > 4096) {
6797 if (bp->flags & ONE_PORT_FLAG)
6801 /* (24*1024 + val*4)/256 */
6802 low = 96 + (val/64) +
6803 ((val % 64) ? 1 : 0);
6806 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6807 high = low + 56; /* 14*1024/256 */
6808 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6809 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6812 if (CHIP_MODE_IS_4_PORT(bp))
6813 REG_WR(bp, (BP_PORT(bp) ?
6814 BRB1_REG_MAC_GUARANTIED_1 :
6815 BRB1_REG_MAC_GUARANTIED_0), 40);
6818 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6819 if (CHIP_IS_E3B0(bp)) {
6820 if (IS_MF_AFEX(bp)) {
6821 /* configure headers for AFEX mode */
6822 REG_WR(bp, BP_PORT(bp) ?
6823 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6824 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
6825 REG_WR(bp, BP_PORT(bp) ?
6826 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
6827 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
6828 REG_WR(bp, BP_PORT(bp) ?
6829 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
6830 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
6832 /* Ovlan exists only if we are in multi-function +
6833 * switch-dependent mode, in switch-independent there
6834 * is no ovlan headers
6836 REG_WR(bp, BP_PORT(bp) ?
6837 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6838 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6839 (bp->path_has_ovlan ? 7 : 6));
6843 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6844 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6845 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6846 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6848 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6849 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6850 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6851 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6853 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6854 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6856 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6858 if (CHIP_IS_E1x(bp)) {
6859 /* configure PBF to work without PAUSE mtu 9000 */
6860 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6862 /* update threshold */
6863 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6864 /* update init credit */
6865 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6868 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6870 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6874 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6876 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6877 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6879 if (CHIP_IS_E1(bp)) {
6880 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6881 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6883 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6885 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6887 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6888 /* init aeu_mask_attn_func_0/1:
6889 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6890 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6891 * bits 4-7 are used for "per vn group attention" */
6892 val = IS_MF(bp) ? 0xF7 : 0x7;
6893 /* Enable DCBX attention for all but E1 */
6894 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6895 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6897 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6899 if (!CHIP_IS_E1x(bp)) {
6900 /* Bit-map indicating which L2 hdrs may appear after the
6901 * basic Ethernet header
6904 REG_WR(bp, BP_PORT(bp) ?
6905 NIG_REG_P1_HDRS_AFTER_BASIC :
6906 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
6908 REG_WR(bp, BP_PORT(bp) ?
6909 NIG_REG_P1_HDRS_AFTER_BASIC :
6910 NIG_REG_P0_HDRS_AFTER_BASIC,
6911 IS_MF_SD(bp) ? 7 : 6);
6914 REG_WR(bp, BP_PORT(bp) ?
6915 NIG_REG_LLH1_MF_MODE :
6916 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6918 if (!CHIP_IS_E3(bp))
6919 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6921 if (!CHIP_IS_E1(bp)) {
6922 /* 0x2 disable mf_ov, 0x1 enable */
6923 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6924 (IS_MF_SD(bp) ? 0x1 : 0x2));
6926 if (!CHIP_IS_E1x(bp)) {
6928 switch (bp->mf_mode) {
6929 case MULTI_FUNCTION_SD:
6932 case MULTI_FUNCTION_SI:
6933 case MULTI_FUNCTION_AFEX:
6938 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6939 NIG_REG_LLH0_CLS_TYPE), val);
6942 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6943 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6944 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6949 /* If SPIO5 is set to generate interrupts, enable it for this port */
6950 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6951 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6952 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6953 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6954 val = REG_RD(bp, reg_addr);
6955 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6956 REG_WR(bp, reg_addr, val);
6962 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6968 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6970 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6972 wb_write[0] = ONCHIP_ADDR1(addr);
6973 wb_write[1] = ONCHIP_ADDR2(addr);
6974 REG_WR_DMAE(bp, reg, wb_write, 2);
6977 static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
6978 u8 idu_sb_id, bool is_Pf)
6980 u32 data, ctl, cnt = 100;
6981 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
6982 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
6983 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
6984 u32 sb_bit = 1 << (idu_sb_id%32);
6985 u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
6986 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
6988 /* Not supported in BC mode */
6989 if (CHIP_INT_MODE_IS_BC(bp))
6992 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
6993 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
6994 IGU_REGULAR_CLEANUP_SET |
6995 IGU_REGULAR_BCLEANUP;
6997 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
6998 func_encode << IGU_CTRL_REG_FID_SHIFT |
6999 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7001 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7002 data, igu_addr_data);
7003 REG_WR(bp, igu_addr_data, data);
7006 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7008 REG_WR(bp, igu_addr_ctl, ctl);
7012 /* wait for clean up to finish */
7013 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7017 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7019 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7020 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7024 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7026 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7029 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7031 u32 i, base = FUNC_ILT_BASE(func);
7032 for (i = base; i < base + ILT_PER_FUNC; i++)
7033 bnx2x_ilt_wr(bp, i, 0);
7036 static int bnx2x_init_hw_func(struct bnx2x *bp)
7038 int port = BP_PORT(bp);
7039 int func = BP_FUNC(bp);
7040 int init_phase = PHASE_PF0 + func;
7041 struct bnx2x_ilt *ilt = BP_ILT(bp);
7044 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7045 int i, main_mem_width, rc;
7047 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7049 /* FLR cleanup - hmmm */
7050 if (!CHIP_IS_E1x(bp)) {
7051 rc = bnx2x_pf_flr_clnup(bp);
7056 /* set MSI reconfigure capability */
7057 if (bp->common.int_block == INT_BLOCK_HC) {
7058 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7059 val = REG_RD(bp, addr);
7060 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7061 REG_WR(bp, addr, val);
7064 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7065 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7068 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7070 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7071 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7072 ilt->lines[cdu_ilt_start + i].page_mapping =
7073 bp->context[i].cxt_mapping;
7074 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7076 bnx2x_ilt_init_op(bp, INITOP_SET);
7079 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7081 /* T1 hash bits value determines the T1 number of entries */
7082 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7087 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7088 #endif /* BCM_CNIC */
7090 if (!CHIP_IS_E1x(bp)) {
7091 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7093 /* Turn on a single ISR mode in IGU if driver is going to use
7096 if (!(bp->flags & USING_MSIX_FLAG))
7097 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7099 * Timers workaround bug: function init part.
7100 * Need to wait 20msec after initializing ILT,
7101 * needed to make sure there are no requests in
7102 * one of the PXP internal queues with "old" ILT addresses
7106 * Master enable - Due to WB DMAE writes performed before this
7107 * register is re-initialized as part of the regular function
7110 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7111 /* Enable the function in IGU */
7112 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7117 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7119 if (!CHIP_IS_E1x(bp))
7120 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7122 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7123 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7124 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7125 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7126 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7127 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7128 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7129 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7130 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7131 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7132 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7133 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7134 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7136 if (!CHIP_IS_E1x(bp))
7137 REG_WR(bp, QM_REG_PF_EN, 1);
7139 if (!CHIP_IS_E1x(bp)) {
7140 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7141 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7142 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7143 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7145 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7147 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7148 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7149 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7150 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7151 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7152 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7153 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7154 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7155 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7156 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7157 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7158 if (!CHIP_IS_E1x(bp))
7159 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7161 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7163 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7165 if (!CHIP_IS_E1x(bp))
7166 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7169 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7170 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7173 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7175 /* HC init per function */
7176 if (bp->common.int_block == INT_BLOCK_HC) {
7177 if (CHIP_IS_E1H(bp)) {
7178 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7180 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7181 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7183 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7186 int num_segs, sb_idx, prod_offset;
7188 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7190 if (!CHIP_IS_E1x(bp)) {
7191 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7192 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7195 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7197 if (!CHIP_IS_E1x(bp)) {
7201 * E2 mode: address 0-135 match to the mapping memory;
7202 * 136 - PF0 default prod; 137 - PF1 default prod;
7203 * 138 - PF2 default prod; 139 - PF3 default prod;
7204 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7205 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7208 * E1.5 mode - In backward compatible mode;
7209 * for non default SB; each even line in the memory
7210 * holds the U producer and each odd line hold
7211 * the C producer. The first 128 producers are for
7212 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7213 * producers are for the DSB for each PF.
7214 * Each PF has five segments: (the order inside each
7215 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7216 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7217 * 144-147 attn prods;
7219 /* non-default-status-blocks */
7220 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7221 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7222 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7223 prod_offset = (bp->igu_base_sb + sb_idx) *
7226 for (i = 0; i < num_segs; i++) {
7227 addr = IGU_REG_PROD_CONS_MEMORY +
7228 (prod_offset + i) * 4;
7229 REG_WR(bp, addr, 0);
7231 /* send consumer update with value 0 */
7232 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7233 USTORM_ID, 0, IGU_INT_NOP, 1);
7234 bnx2x_igu_clear_sb(bp,
7235 bp->igu_base_sb + sb_idx);
7238 /* default-status-blocks */
7239 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7240 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7242 if (CHIP_MODE_IS_4_PORT(bp))
7243 dsb_idx = BP_FUNC(bp);
7245 dsb_idx = BP_VN(bp);
7247 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7248 IGU_BC_BASE_DSB_PROD + dsb_idx :
7249 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7252 * igu prods come in chunks of E1HVN_MAX (4) -
7253 * does not matters what is the current chip mode
7255 for (i = 0; i < (num_segs * E1HVN_MAX);
7257 addr = IGU_REG_PROD_CONS_MEMORY +
7258 (prod_offset + i)*4;
7259 REG_WR(bp, addr, 0);
7261 /* send consumer update with 0 */
7262 if (CHIP_INT_MODE_IS_BC(bp)) {
7263 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7264 USTORM_ID, 0, IGU_INT_NOP, 1);
7265 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7266 CSTORM_ID, 0, IGU_INT_NOP, 1);
7267 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7268 XSTORM_ID, 0, IGU_INT_NOP, 1);
7269 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7270 TSTORM_ID, 0, IGU_INT_NOP, 1);
7271 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7272 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7274 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7275 USTORM_ID, 0, IGU_INT_NOP, 1);
7276 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7277 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7279 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7281 /* !!! these should become driver const once
7282 rf-tool supports split-68 const */
7283 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7284 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7285 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7286 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7287 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7288 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7292 /* Reset PCIE errors for debug */
7293 REG_WR(bp, 0x2114, 0xffffffff);
7294 REG_WR(bp, 0x2120, 0xffffffff);
7296 if (CHIP_IS_E1x(bp)) {
7297 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7298 main_mem_base = HC_REG_MAIN_MEMORY +
7299 BP_PORT(bp) * (main_mem_size * 4);
7300 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7303 val = REG_RD(bp, main_mem_prty_clr);
7306 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7309 /* Clear "false" parity errors in MSI-X table */
7310 for (i = main_mem_base;
7311 i < main_mem_base + main_mem_size * 4;
7312 i += main_mem_width) {
7313 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7314 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7315 i, main_mem_width / 4);
7317 /* Clear HC parity attention */
7318 REG_RD(bp, main_mem_prty_clr);
7321 #ifdef BNX2X_STOP_ON_ERROR
7322 /* Enable STORMs SP logging */
7323 REG_WR8(bp, BAR_USTRORM_INTMEM +
7324 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7325 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7326 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7327 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7328 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7329 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7330 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7333 bnx2x_phy_probe(&bp->link_params);
7339 void bnx2x_free_mem(struct bnx2x *bp)
7344 bnx2x_free_fp_mem(bp);
7345 /* end of fastpath */
7347 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7348 sizeof(struct host_sp_status_block));
7350 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7351 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7353 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7354 sizeof(struct bnx2x_slowpath));
7356 for (i = 0; i < L2_ILT_LINES(bp); i++)
7357 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7358 bp->context[i].size);
7359 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7361 BNX2X_FREE(bp->ilt->lines);
7364 if (!CHIP_IS_E1x(bp))
7365 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7366 sizeof(struct host_hc_status_block_e2));
7368 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7369 sizeof(struct host_hc_status_block_e1x));
7371 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7374 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7376 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7377 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7380 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7383 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
7385 /* number of queues for statistics is number of eth queues + FCoE */
7386 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
7388 /* Total number of FW statistics requests =
7389 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7392 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
7395 /* Request is built from stats_query_header and an array of
7396 * stats_query_cmd_group each of which contains
7397 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7398 * configured in the stats_query_header.
7400 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7401 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
7403 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7404 num_groups * sizeof(struct stats_query_cmd_group);
7406 /* Data for statistics requests + stats_conter
7408 * stats_counter holds per-STORM counters that are incremented
7409 * when STORM has finished with the current request.
7411 * memory for FCoE offloaded statistics are counted anyway,
7412 * even if they will not be sent.
7414 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7415 sizeof(struct per_pf_stats) +
7416 sizeof(struct fcoe_statistics_params) +
7417 sizeof(struct per_queue_stats) * num_queue_stats +
7418 sizeof(struct stats_counter);
7420 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7421 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7424 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7425 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7427 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7428 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7430 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7431 bp->fw_stats_req_sz;
7435 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7436 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7437 BNX2X_ERR("Can't allocate memory\n");
7442 int bnx2x_alloc_mem(struct bnx2x *bp)
7444 int i, allocated, context_size;
7447 if (!CHIP_IS_E1x(bp))
7448 /* size = the status block + ramrod buffers */
7449 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7450 sizeof(struct host_hc_status_block_e2));
7452 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
7453 sizeof(struct host_hc_status_block_e1x));
7455 /* allocate searcher T2 table */
7456 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7460 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7461 sizeof(struct host_sp_status_block));
7463 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7464 sizeof(struct bnx2x_slowpath));
7467 /* write address to which L5 should insert its values */
7468 bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp;
7471 /* Allocated memory for FW statistics */
7472 if (bnx2x_alloc_fw_stats_mem(bp))
7475 /* Allocate memory for CDU context:
7476 * This memory is allocated separately and not in the generic ILT
7477 * functions because CDU differs in few aspects:
7478 * 1. There are multiple entities allocating memory for context -
7479 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7480 * its own ILT lines.
7481 * 2. Since CDU page-size is not a single 4KB page (which is the case
7482 * for the other ILT clients), to be efficient we want to support
7483 * allocation of sub-page-size in the last entry.
7484 * 3. Context pointers are used by the driver to pass to FW / update
7485 * the context (for the other ILT clients the pointers are used just to
7486 * free the memory during unload).
7488 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7490 for (i = 0, allocated = 0; allocated < context_size; i++) {
7491 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7492 (context_size - allocated));
7493 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7494 &bp->context[i].cxt_mapping,
7495 bp->context[i].size);
7496 allocated += bp->context[i].size;
7498 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7500 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7503 /* Slow path ring */
7504 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7507 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7508 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7512 /* need to be done at the end, since it's self adjusting to amount
7513 * of memory available for RSS queues
7515 if (bnx2x_alloc_fp_mem(bp))
7521 BNX2X_ERR("Can't allocate memory\n");
7526 * Init service functions
7529 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7530 struct bnx2x_vlan_mac_obj *obj, bool set,
7531 int mac_type, unsigned long *ramrod_flags)
7534 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7536 memset(&ramrod_param, 0, sizeof(ramrod_param));
7538 /* Fill general parameters */
7539 ramrod_param.vlan_mac_obj = obj;
7540 ramrod_param.ramrod_flags = *ramrod_flags;
7542 /* Fill a user request section if needed */
7543 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7544 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7546 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7548 /* Set the command: ADD or DEL */
7550 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7552 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7555 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7557 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7561 int bnx2x_del_all_macs(struct bnx2x *bp,
7562 struct bnx2x_vlan_mac_obj *mac_obj,
7563 int mac_type, bool wait_for_comp)
7566 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7568 /* Wait for completion of requested */
7570 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7572 /* Set the mac type of addresses we want to clear */
7573 __set_bit(mac_type, &vlan_mac_flags);
7575 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7577 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7582 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7584 unsigned long ramrod_flags = 0;
7587 if (is_zero_ether_addr(bp->dev->dev_addr) &&
7588 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7589 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7590 "Ignoring Zero MAC for STORAGE SD mode\n");
7595 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7597 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7598 /* Eth MAC is set on RSS leading client (fp[0]) */
7599 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7600 set, BNX2X_ETH_MAC, &ramrod_flags);
7603 int bnx2x_setup_leading(struct bnx2x *bp)
7605 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7609 * bnx2x_set_int_mode - configure interrupt mode
7611 * @bp: driver handle
7613 * In case of MSI-X it will also try to enable MSI-X.
7615 void bnx2x_set_int_mode(struct bnx2x *bp)
7619 bnx2x_enable_msi(bp);
7620 /* falling through... */
7622 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7623 BNX2X_DEV_INFO("set number of queues to 1\n");
7626 /* if we can't use MSI-X we only need one fp,
7627 * so try to enable MSI-X with the requested number of fp's
7628 * and fallback to MSI or legacy INTx with one fp
7630 if (bnx2x_enable_msix(bp) ||
7631 bp->flags & USING_SINGLE_MSIX_FLAG) {
7632 /* failed to enable multiple MSI-X */
7633 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7634 bp->num_queues, 1 + NON_ETH_CONTEXT_USE);
7636 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7638 /* Try to enable MSI */
7639 if (!(bp->flags & USING_SINGLE_MSIX_FLAG) &&
7640 !(bp->flags & DISABLE_MSI_FLAG))
7641 bnx2x_enable_msi(bp);
7647 /* must be called prioir to any HW initializations */
7648 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7650 return L2_ILT_LINES(bp);
7653 void bnx2x_ilt_set_info(struct bnx2x *bp)
7655 struct ilt_client_info *ilt_client;
7656 struct bnx2x_ilt *ilt = BP_ILT(bp);
7659 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7660 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7663 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7664 ilt_client->client_num = ILT_CLIENT_CDU;
7665 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7666 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7667 ilt_client->start = line;
7668 line += bnx2x_cid_ilt_lines(bp);
7670 line += CNIC_ILT_LINES;
7672 ilt_client->end = line - 1;
7674 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7677 ilt_client->page_size,
7679 ilog2(ilt_client->page_size >> 12));
7682 if (QM_INIT(bp->qm_cid_count)) {
7683 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7684 ilt_client->client_num = ILT_CLIENT_QM;
7685 ilt_client->page_size = QM_ILT_PAGE_SZ;
7686 ilt_client->flags = 0;
7687 ilt_client->start = line;
7689 /* 4 bytes for each cid */
7690 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7693 ilt_client->end = line - 1;
7696 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7699 ilt_client->page_size,
7701 ilog2(ilt_client->page_size >> 12));
7705 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7707 ilt_client->client_num = ILT_CLIENT_SRC;
7708 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7709 ilt_client->flags = 0;
7710 ilt_client->start = line;
7711 line += SRC_ILT_LINES;
7712 ilt_client->end = line - 1;
7715 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7718 ilt_client->page_size,
7720 ilog2(ilt_client->page_size >> 12));
7723 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7727 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7729 ilt_client->client_num = ILT_CLIENT_TM;
7730 ilt_client->page_size = TM_ILT_PAGE_SZ;
7731 ilt_client->flags = 0;
7732 ilt_client->start = line;
7733 line += TM_ILT_LINES;
7734 ilt_client->end = line - 1;
7737 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7740 ilt_client->page_size,
7742 ilog2(ilt_client->page_size >> 12));
7745 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7747 BUG_ON(line > ILT_MAX_LINES);
7751 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7753 * @bp: driver handle
7754 * @fp: pointer to fastpath
7755 * @init_params: pointer to parameters structure
7757 * parameters configured:
7758 * - HC configuration
7759 * - Queue's CDU context
7761 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7762 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7766 int cxt_index, cxt_offset;
7768 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7769 if (!IS_FCOE_FP(fp)) {
7770 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7771 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7773 /* If HC is supporterd, enable host coalescing in the transition
7776 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7777 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7780 init_params->rx.hc_rate = bp->rx_ticks ?
7781 (1000000 / bp->rx_ticks) : 0;
7782 init_params->tx.hc_rate = bp->tx_ticks ?
7783 (1000000 / bp->tx_ticks) : 0;
7786 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7790 * CQ index among the SB indices: FCoE clients uses the default
7791 * SB, therefore it's different.
7793 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7794 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7797 /* set maximum number of COSs supported by this queue */
7798 init_params->max_cos = fp->max_cos;
7800 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
7801 fp->index, init_params->max_cos);
7803 /* set the context pointers queue object */
7804 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
7805 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
7806 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
7808 init_params->cxts[cos] =
7809 &bp->context[cxt_index].vcxt[cxt_offset].eth;
7813 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7814 struct bnx2x_queue_state_params *q_params,
7815 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7816 int tx_index, bool leading)
7818 memset(tx_only_params, 0, sizeof(*tx_only_params));
7820 /* Set the command */
7821 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7823 /* Set tx-only QUEUE flags: don't zero statistics */
7824 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7826 /* choose the index of the cid to send the slow path on */
7827 tx_only_params->cid_index = tx_index;
7829 /* Set general TX_ONLY_SETUP parameters */
7830 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7832 /* Set Tx TX_ONLY_SETUP parameters */
7833 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7836 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
7837 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7838 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7839 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7841 /* send the ramrod */
7842 return bnx2x_queue_state_change(bp, q_params);
7847 * bnx2x_setup_queue - setup queue
7849 * @bp: driver handle
7850 * @fp: pointer to fastpath
7851 * @leading: is leading
7853 * This function performs 2 steps in a Queue state machine
7854 * actually: 1) RESET->INIT 2) INIT->SETUP
7857 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7860 struct bnx2x_queue_state_params q_params = {NULL};
7861 struct bnx2x_queue_setup_params *setup_params =
7862 &q_params.params.setup;
7863 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7864 &q_params.params.tx_only;
7868 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
7870 /* reset IGU state skip FCoE L2 queue */
7871 if (!IS_FCOE_FP(fp))
7872 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7875 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
7876 /* We want to wait for completion in this context */
7877 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7879 /* Prepare the INIT parameters */
7880 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7882 /* Set the command */
7883 q_params.cmd = BNX2X_Q_CMD_INIT;
7885 /* Change the state to INIT */
7886 rc = bnx2x_queue_state_change(bp, &q_params);
7888 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7892 DP(NETIF_MSG_IFUP, "init complete\n");
7895 /* Now move the Queue to the SETUP state... */
7896 memset(setup_params, 0, sizeof(*setup_params));
7898 /* Set QUEUE flags */
7899 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7901 /* Set general SETUP parameters */
7902 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7903 FIRST_TX_COS_INDEX);
7905 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7906 &setup_params->rxq_params);
7908 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7909 FIRST_TX_COS_INDEX);
7911 /* Set the command */
7912 q_params.cmd = BNX2X_Q_CMD_SETUP;
7914 /* Change the state to SETUP */
7915 rc = bnx2x_queue_state_change(bp, &q_params);
7917 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7921 /* loop through the relevant tx-only indices */
7922 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7923 tx_index < fp->max_cos;
7926 /* prepare and send tx-only ramrod*/
7927 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7928 tx_only_params, tx_index, leading);
7930 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7931 fp->index, tx_index);
7939 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7941 struct bnx2x_fastpath *fp = &bp->fp[index];
7942 struct bnx2x_fp_txdata *txdata;
7943 struct bnx2x_queue_state_params q_params = {NULL};
7946 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
7948 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
7949 /* We want to wait for completion in this context */
7950 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7953 /* close tx-only connections */
7954 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7955 tx_index < fp->max_cos;
7958 /* ascertain this is a normal queue*/
7959 txdata = fp->txdata_ptr[tx_index];
7961 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
7964 /* send halt terminate on tx-only connection */
7965 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7966 memset(&q_params.params.terminate, 0,
7967 sizeof(q_params.params.terminate));
7968 q_params.params.terminate.cid_index = tx_index;
7970 rc = bnx2x_queue_state_change(bp, &q_params);
7974 /* send halt terminate on tx-only connection */
7975 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7976 memset(&q_params.params.cfc_del, 0,
7977 sizeof(q_params.params.cfc_del));
7978 q_params.params.cfc_del.cid_index = tx_index;
7979 rc = bnx2x_queue_state_change(bp, &q_params);
7983 /* Stop the primary connection: */
7984 /* ...halt the connection */
7985 q_params.cmd = BNX2X_Q_CMD_HALT;
7986 rc = bnx2x_queue_state_change(bp, &q_params);
7990 /* ...terminate the connection */
7991 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7992 memset(&q_params.params.terminate, 0,
7993 sizeof(q_params.params.terminate));
7994 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
7995 rc = bnx2x_queue_state_change(bp, &q_params);
7998 /* ...delete cfc entry */
7999 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8000 memset(&q_params.params.cfc_del, 0,
8001 sizeof(q_params.params.cfc_del));
8002 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8003 return bnx2x_queue_state_change(bp, &q_params);
8007 static void bnx2x_reset_func(struct bnx2x *bp)
8009 int port = BP_PORT(bp);
8010 int func = BP_FUNC(bp);
8013 /* Disable the function in the FW */
8014 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8015 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8016 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8017 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8020 for_each_eth_queue(bp, i) {
8021 struct bnx2x_fastpath *fp = &bp->fp[i];
8022 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8023 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8029 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8030 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
8034 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8035 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8038 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8039 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8043 if (bp->common.int_block == INT_BLOCK_HC) {
8044 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8045 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8047 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8048 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8052 /* Disable Timer scan */
8053 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8055 * Wait for at least 10ms and up to 2 second for the timers scan to
8058 for (i = 0; i < 200; i++) {
8060 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8065 bnx2x_clear_func_ilt(bp, func);
8067 /* Timers workaround bug for E2: if this is vnic-3,
8068 * we need to set the entire ilt range for this timers.
8070 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8071 struct ilt_client_info ilt_cli;
8072 /* use dummy TM client */
8073 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8075 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8076 ilt_cli.client_num = ILT_CLIENT_TM;
8078 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8081 /* this assumes that reset_port() called before reset_func()*/
8082 if (!CHIP_IS_E1x(bp))
8083 bnx2x_pf_disable(bp);
8088 static void bnx2x_reset_port(struct bnx2x *bp)
8090 int port = BP_PORT(bp);
8093 /* Reset physical Link */
8094 bnx2x__link_reset(bp);
8096 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8098 /* Do not rcv packets to BRB */
8099 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8100 /* Do not direct rcv packets that are not for MCP to the BRB */
8101 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8102 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8105 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8108 /* Check for BRB port occupancy */
8109 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8111 DP(NETIF_MSG_IFDOWN,
8112 "BRB1 is not empty %d blocks are occupied\n", val);
8114 /* TODO: Close Doorbell port? */
8117 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8119 struct bnx2x_func_state_params func_params = {NULL};
8121 /* Prepare parameters for function state transitions */
8122 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8124 func_params.f_obj = &bp->func_obj;
8125 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8127 func_params.params.hw_init.load_phase = load_code;
8129 return bnx2x_func_state_change(bp, &func_params);
8132 static int bnx2x_func_stop(struct bnx2x *bp)
8134 struct bnx2x_func_state_params func_params = {NULL};
8137 /* Prepare parameters for function state transitions */
8138 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8139 func_params.f_obj = &bp->func_obj;
8140 func_params.cmd = BNX2X_F_CMD_STOP;
8143 * Try to stop the function the 'good way'. If fails (in case
8144 * of a parity error during bnx2x_chip_cleanup()) and we are
8145 * not in a debug mode, perform a state transaction in order to
8146 * enable further HW_RESET transaction.
8148 rc = bnx2x_func_state_change(bp, &func_params);
8150 #ifdef BNX2X_STOP_ON_ERROR
8153 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8154 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8155 return bnx2x_func_state_change(bp, &func_params);
8163 * bnx2x_send_unload_req - request unload mode from the MCP.
8165 * @bp: driver handle
8166 * @unload_mode: requested function's unload mode
8168 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8170 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8173 int port = BP_PORT(bp);
8175 /* Select the UNLOAD request mode */
8176 if (unload_mode == UNLOAD_NORMAL)
8177 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8179 else if (bp->flags & NO_WOL_FLAG)
8180 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8183 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8184 u8 *mac_addr = bp->dev->dev_addr;
8188 /* The mac address is written to entries 1-4 to
8189 * preserve entry 0 which is used by the PMF
8191 u8 entry = (BP_VN(bp) + 1)*8;
8193 val = (mac_addr[0] << 8) | mac_addr[1];
8194 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8196 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8197 (mac_addr[4] << 8) | mac_addr[5];
8198 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8200 /* Enable the PME and clear the status */
8201 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8202 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8203 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8205 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8208 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8210 /* Send the request to the MCP */
8212 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8214 int path = BP_PATH(bp);
8216 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8217 path, load_count[path][0], load_count[path][1],
8218 load_count[path][2]);
8219 load_count[path][0]--;
8220 load_count[path][1 + port]--;
8221 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8222 path, load_count[path][0], load_count[path][1],
8223 load_count[path][2]);
8224 if (load_count[path][0] == 0)
8225 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8226 else if (load_count[path][1 + port] == 0)
8227 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8229 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8236 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8238 * @bp: driver handle
8240 void bnx2x_send_unload_done(struct bnx2x *bp)
8242 /* Report UNLOAD_DONE to MCP */
8244 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8247 static int bnx2x_func_wait_started(struct bnx2x *bp)
8250 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8256 * (assumption: No Attention from MCP at this stage)
8257 * PMF probably in the middle of TXdisable/enable transaction
8258 * 1. Sync IRS for default SB
8259 * 2. Sync SP queue - this guarantes us that attention handling started
8260 * 3. Wait, that TXdisable/enable transaction completes
8262 * 1+2 guranty that if DCBx attention was scheduled it already changed
8263 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8264 * received complettion for the transaction the state is TX_STOPPED.
8265 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8269 /* make sure default SB ISR is done */
8271 synchronize_irq(bp->msix_table[0].vector);
8273 synchronize_irq(bp->pdev->irq);
8275 flush_workqueue(bnx2x_wq);
8277 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8278 BNX2X_F_STATE_STARTED && tout--)
8281 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8282 BNX2X_F_STATE_STARTED) {
8283 #ifdef BNX2X_STOP_ON_ERROR
8284 BNX2X_ERR("Wrong function state\n");
8288 * Failed to complete the transaction in a "good way"
8289 * Force both transactions with CLR bit
8291 struct bnx2x_func_state_params func_params = {NULL};
8293 DP(NETIF_MSG_IFDOWN,
8294 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8296 func_params.f_obj = &bp->func_obj;
8297 __set_bit(RAMROD_DRV_CLR_ONLY,
8298 &func_params.ramrod_flags);
8300 /* STARTED-->TX_ST0PPED */
8301 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8302 bnx2x_func_state_change(bp, &func_params);
8304 /* TX_ST0PPED-->STARTED */
8305 func_params.cmd = BNX2X_F_CMD_TX_START;
8306 return bnx2x_func_state_change(bp, &func_params);
8313 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
8315 int port = BP_PORT(bp);
8318 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8321 /* Wait until tx fastpath tasks complete */
8322 for_each_tx_queue(bp, i) {
8323 struct bnx2x_fastpath *fp = &bp->fp[i];
8325 for_each_cos_in_tx_queue(fp, cos)
8326 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8327 #ifdef BNX2X_STOP_ON_ERROR
8333 /* Give HW time to discard old tx messages */
8334 usleep_range(1000, 1000);
8336 /* Clean all ETH MACs */
8337 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8340 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8342 /* Clean up UC list */
8343 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8346 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8350 if (!CHIP_IS_E1(bp))
8351 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8353 /* Set "drop all" (stop Rx).
8354 * We need to take a netif_addr_lock() here in order to prevent
8355 * a race between the completion code and this code.
8357 netif_addr_lock_bh(bp->dev);
8358 /* Schedule the rx_mode command */
8359 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8360 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8362 bnx2x_set_storm_rx_mode(bp);
8364 /* Cleanup multicast configuration */
8365 rparam.mcast_obj = &bp->mcast_obj;
8366 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8368 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8370 netif_addr_unlock_bh(bp->dev);
8375 * Send the UNLOAD_REQUEST to the MCP. This will return if
8376 * this function should perform FUNC, PORT or COMMON HW
8379 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8382 * (assumption: No Attention from MCP at this stage)
8383 * PMF probably in the middle of TXdisable/enable transaction
8385 rc = bnx2x_func_wait_started(bp);
8387 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8388 #ifdef BNX2X_STOP_ON_ERROR
8393 /* Close multi and leading connections
8394 * Completions for ramrods are collected in a synchronous way
8396 for_each_queue(bp, i)
8397 if (bnx2x_stop_queue(bp, i))
8398 #ifdef BNX2X_STOP_ON_ERROR
8403 /* If SP settings didn't get completed so far - something
8404 * very wrong has happen.
8406 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8407 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8409 #ifndef BNX2X_STOP_ON_ERROR
8412 rc = bnx2x_func_stop(bp);
8414 BNX2X_ERR("Function stop failed!\n");
8415 #ifdef BNX2X_STOP_ON_ERROR
8420 /* Disable HW interrupts, NAPI */
8421 bnx2x_netif_stop(bp, 1);
8426 /* Reset the chip */
8427 rc = bnx2x_reset_hw(bp, reset_code);
8429 BNX2X_ERR("HW_RESET failed\n");
8432 /* Report UNLOAD_DONE to MCP */
8433 bnx2x_send_unload_done(bp);
8436 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8440 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8442 if (CHIP_IS_E1(bp)) {
8443 int port = BP_PORT(bp);
8444 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8445 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8447 val = REG_RD(bp, addr);
8449 REG_WR(bp, addr, val);
8451 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8452 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8453 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8454 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8458 /* Close gates #2, #3 and #4: */
8459 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8463 /* Gates #2 and #4a are closed/opened for "not E1" only */
8464 if (!CHIP_IS_E1(bp)) {
8466 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8468 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8472 if (CHIP_IS_E1x(bp)) {
8473 /* Prevent interrupts from HC on both ports */
8474 val = REG_RD(bp, HC_REG_CONFIG_1);
8475 REG_WR(bp, HC_REG_CONFIG_1,
8476 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8477 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8479 val = REG_RD(bp, HC_REG_CONFIG_0);
8480 REG_WR(bp, HC_REG_CONFIG_0,
8481 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8482 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8484 /* Prevent incomming interrupts in IGU */
8485 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8487 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8489 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8490 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8493 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8494 close ? "closing" : "opening");
8498 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8500 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8502 /* Do some magic... */
8503 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8504 *magic_val = val & SHARED_MF_CLP_MAGIC;
8505 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8509 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8511 * @bp: driver handle
8512 * @magic_val: old value of the `magic' bit.
8514 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8516 /* Restore the `magic' bit value... */
8517 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8518 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8519 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8523 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8525 * @bp: driver handle
8526 * @magic_val: old value of 'magic' bit.
8528 * Takes care of CLP configurations.
8530 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8533 u32 validity_offset;
8535 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8537 /* Set `magic' bit in order to save MF config */
8538 if (!CHIP_IS_E1(bp))
8539 bnx2x_clp_reset_prep(bp, magic_val);
8541 /* Get shmem offset */
8542 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8543 validity_offset = offsetof(struct shmem_region, validity_map[0]);
8545 /* Clear validity map flags */
8547 REG_WR(bp, shmem + validity_offset, 0);
8550 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8551 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8554 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8556 * @bp: driver handle
8558 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8560 /* special handling for emulation and FPGA,
8561 wait 10 times longer */
8562 if (CHIP_REV_IS_SLOW(bp))
8563 msleep(MCP_ONE_TIMEOUT*10);
8565 msleep(MCP_ONE_TIMEOUT);
8569 * initializes bp->common.shmem_base and waits for validity signature to appear
8571 static int bnx2x_init_shmem(struct bnx2x *bp)
8577 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8578 if (bp->common.shmem_base) {
8579 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8580 if (val & SHR_MEM_VALIDITY_MB)
8584 bnx2x_mcp_wait_one(bp);
8586 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8588 BNX2X_ERR("BAD MCP validity signature\n");
8593 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8595 int rc = bnx2x_init_shmem(bp);
8597 /* Restore the `magic' bit value */
8598 if (!CHIP_IS_E1(bp))
8599 bnx2x_clp_reset_done(bp, magic_val);
8604 static void bnx2x_pxp_prep(struct bnx2x *bp)
8606 if (!CHIP_IS_E1(bp)) {
8607 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8608 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8614 * Reset the whole chip except for:
8616 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8619 * - MISC (including AEU)
8623 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8625 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8626 u32 global_bits2, stay_reset2;
8629 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8630 * (per chip) blocks.
8633 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8634 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8636 /* Don't reset the following blocks */
8638 MISC_REGISTERS_RESET_REG_1_RST_HC |
8639 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8640 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8643 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8644 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8645 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8646 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8647 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8648 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8649 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8650 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8651 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8652 MISC_REGISTERS_RESET_REG_2_PGLC;
8655 * Keep the following blocks in reset:
8656 * - all xxMACs are handled by the bnx2x_link code.
8659 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8660 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8661 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8662 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8663 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8664 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8665 MISC_REGISTERS_RESET_REG_2_XMAC |
8666 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8668 /* Full reset masks according to the chip */
8669 reset_mask1 = 0xffffffff;
8672 reset_mask2 = 0xffff;
8673 else if (CHIP_IS_E1H(bp))
8674 reset_mask2 = 0x1ffff;
8675 else if (CHIP_IS_E2(bp))
8676 reset_mask2 = 0xfffff;
8677 else /* CHIP_IS_E3 */
8678 reset_mask2 = 0x3ffffff;
8680 /* Don't reset global blocks unless we need to */
8682 reset_mask2 &= ~global_bits2;
8685 * In case of attention in the QM, we need to reset PXP
8686 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8687 * because otherwise QM reset would release 'close the gates' shortly
8688 * before resetting the PXP, then the PSWRQ would send a write
8689 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8690 * read the payload data from PSWWR, but PSWWR would not
8691 * respond. The write queue in PGLUE would stuck, dmae commands
8692 * would not return. Therefore it's important to reset the second
8693 * reset register (containing the
8694 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8695 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8698 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8699 reset_mask2 & (~not_reset_mask2));
8701 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8702 reset_mask1 & (~not_reset_mask1));
8707 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8708 reset_mask2 & (~stay_reset2));
8713 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8718 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8719 * It should get cleared in no more than 1s.
8721 * @bp: driver handle
8723 * It should get cleared in no more than 1s. Returns 0 if
8724 * pending writes bit gets cleared.
8726 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8732 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8737 usleep_range(1000, 1000);
8738 } while (cnt-- > 0);
8741 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8749 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8753 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8756 /* Empty the Tetris buffer, wait for 1s */
8758 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8759 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8760 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8761 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8762 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8763 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8764 ((port_is_idle_0 & 0x1) == 0x1) &&
8765 ((port_is_idle_1 & 0x1) == 0x1) &&
8766 (pgl_exp_rom2 == 0xffffffff))
8768 usleep_range(1000, 1000);
8769 } while (cnt-- > 0);
8772 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
8773 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8774 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8781 /* Close gates #2, #3 and #4 */
8782 bnx2x_set_234_gates(bp, true);
8784 /* Poll for IGU VQs for 57712 and newer chips */
8785 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8789 /* TBD: Indicate that "process kill" is in progress to MCP */
8791 /* Clear "unprepared" bit */
8792 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8795 /* Make sure all is written to the chip before the reset */
8798 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8799 * PSWHST, GRC and PSWRD Tetris buffer.
8801 usleep_range(1000, 1000);
8803 /* Prepare to chip reset: */
8806 bnx2x_reset_mcp_prep(bp, &val);
8812 /* reset the chip */
8813 bnx2x_process_kill_chip_reset(bp, global);
8816 /* Recover after reset: */
8818 if (global && bnx2x_reset_mcp_comp(bp, val))
8821 /* TBD: Add resetting the NO_MCP mode DB here */
8826 /* Open the gates #2, #3 and #4 */
8827 bnx2x_set_234_gates(bp, false);
8829 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8830 * reset state, re-enable attentions. */
8835 int bnx2x_leader_reset(struct bnx2x *bp)
8838 bool global = bnx2x_reset_is_global(bp);
8841 /* if not going to reset MCP - load "fake" driver to reset HW while
8842 * driver is owner of the HW
8844 if (!global && !BP_NOMCP(bp)) {
8845 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0);
8847 BNX2X_ERR("MCP response failure, aborting\n");
8849 goto exit_leader_reset;
8851 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
8852 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
8853 BNX2X_ERR("MCP unexpected resp, aborting\n");
8855 goto exit_leader_reset2;
8857 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
8859 BNX2X_ERR("MCP response failure, aborting\n");
8861 goto exit_leader_reset2;
8865 /* Try to recover after the failure */
8866 if (bnx2x_process_kill(bp, global)) {
8867 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
8870 goto exit_leader_reset2;
8874 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8877 bnx2x_set_reset_done(bp);
8879 bnx2x_clear_reset_global(bp);
8882 /* unload "fake driver" if it was loaded */
8883 if (!global && !BP_NOMCP(bp)) {
8884 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
8885 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8889 bnx2x_release_leader_lock(bp);
8894 static void bnx2x_recovery_failed(struct bnx2x *bp)
8896 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8898 /* Disconnect this device */
8899 netif_device_detach(bp->dev);
8902 * Block ifup for all function on this engine until "process kill"
8905 bnx2x_set_reset_in_progress(bp);
8907 /* Shut down the power */
8908 bnx2x_set_power_state(bp, PCI_D3hot);
8910 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8916 * Assumption: runs under rtnl lock. This together with the fact
8917 * that it's called only from bnx2x_sp_rtnl() ensure that it
8918 * will never be called when netif_running(bp->dev) is false.
8920 static void bnx2x_parity_recover(struct bnx2x *bp)
8922 bool global = false;
8923 u32 error_recovered, error_unrecovered;
8926 DP(NETIF_MSG_HW, "Handling parity\n");
8928 switch (bp->recovery_state) {
8929 case BNX2X_RECOVERY_INIT:
8930 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8931 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
8932 WARN_ON(!is_parity);
8934 /* Try to get a LEADER_LOCK HW lock */
8935 if (bnx2x_trylock_leader_lock(bp)) {
8936 bnx2x_set_reset_in_progress(bp);
8938 * Check if there is a global attention and if
8939 * there was a global attention, set the global
8944 bnx2x_set_reset_global(bp);
8949 /* Stop the driver */
8950 /* If interface has been removed - break */
8951 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8954 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8956 /* Ensure "is_leader", MCP command sequence and
8957 * "recovery_state" update values are seen on other
8963 case BNX2X_RECOVERY_WAIT:
8964 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8965 if (bp->is_leader) {
8966 int other_engine = BP_PATH(bp) ? 0 : 1;
8967 bool other_load_status =
8968 bnx2x_get_load_status(bp, other_engine);
8970 bnx2x_get_load_status(bp, BP_PATH(bp));
8971 global = bnx2x_reset_is_global(bp);
8974 * In case of a parity in a global block, let
8975 * the first leader that performs a
8976 * leader_reset() reset the global blocks in
8977 * order to clear global attentions. Otherwise
8978 * the the gates will remain closed for that
8982 (global && other_load_status)) {
8983 /* Wait until all other functions get
8986 schedule_delayed_work(&bp->sp_rtnl_task,
8990 /* If all other functions got down -
8991 * try to bring the chip back to
8992 * normal. In any case it's an exit
8993 * point for a leader.
8995 if (bnx2x_leader_reset(bp)) {
8996 bnx2x_recovery_failed(bp);
9000 /* If we are here, means that the
9001 * leader has succeeded and doesn't
9002 * want to be a leader any more. Try
9003 * to continue as a none-leader.
9007 } else { /* non-leader */
9008 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9009 /* Try to get a LEADER_LOCK HW lock as
9010 * long as a former leader may have
9011 * been unloaded by the user or
9012 * released a leadership by another
9015 if (bnx2x_trylock_leader_lock(bp)) {
9016 /* I'm a leader now! Restart a
9023 schedule_delayed_work(&bp->sp_rtnl_task,
9029 * If there was a global attention, wait
9030 * for it to be cleared.
9032 if (bnx2x_reset_is_global(bp)) {
9033 schedule_delayed_work(
9040 bp->eth_stats.recoverable_error;
9042 bp->eth_stats.unrecoverable_error;
9043 bp->recovery_state =
9044 BNX2X_RECOVERY_NIC_LOADING;
9045 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9046 error_unrecovered++;
9048 "Recovery failed. Power cycle needed\n");
9049 /* Disconnect this device */
9050 netif_device_detach(bp->dev);
9051 /* Shut down the power */
9052 bnx2x_set_power_state(
9056 bp->recovery_state =
9057 BNX2X_RECOVERY_DONE;
9061 bp->eth_stats.recoverable_error =
9063 bp->eth_stats.unrecoverable_error =
9075 static int bnx2x_close(struct net_device *dev);
9077 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9078 * scheduled on a general queue in order to prevent a dead lock.
9080 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9082 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9086 if (!netif_running(bp->dev))
9089 /* if stop on error is defined no recovery flows should be executed */
9090 #ifdef BNX2X_STOP_ON_ERROR
9091 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9092 "you will need to reboot when done\n");
9093 goto sp_rtnl_not_reset;
9096 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9098 * Clear all pending SP commands as we are going to reset the
9101 bp->sp_rtnl_state = 0;
9104 bnx2x_parity_recover(bp);
9109 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9111 * Clear all pending SP commands as we are going to reset the
9114 bp->sp_rtnl_state = 0;
9117 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9118 bnx2x_nic_load(bp, LOAD_NORMAL);
9122 #ifdef BNX2X_STOP_ON_ERROR
9125 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9126 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9127 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9128 bnx2x_after_function_update(bp);
9130 * in case of fan failure we need to reset id if the "stop on error"
9131 * debug flag is set, since we trying to prevent permanent overheating
9134 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9135 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9136 netif_device_detach(bp->dev);
9137 bnx2x_close(bp->dev);
9144 /* end of nic load/unload */
9146 static void bnx2x_period_task(struct work_struct *work)
9148 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9150 if (!netif_running(bp->dev))
9151 goto period_task_exit;
9153 if (CHIP_REV_IS_SLOW(bp)) {
9154 BNX2X_ERR("period task called on emulation, ignoring\n");
9155 goto period_task_exit;
9158 bnx2x_acquire_phy_lock(bp);
9160 * The barrier is needed to ensure the ordering between the writing to
9161 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9166 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9168 /* Re-queue task in 1 sec */
9169 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9172 bnx2x_release_phy_lock(bp);
9178 * Init service functions
9181 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9183 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9184 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9185 return base + (BP_ABS_FUNC(bp)) * stride;
9188 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9190 u32 reg = bnx2x_get_pretend_reg(bp);
9192 /* Flush all outstanding writes */
9195 /* Pretend to be function 0 */
9197 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
9199 /* From now we are in the "like-E1" mode */
9200 bnx2x_int_disable(bp);
9202 /* Flush all outstanding writes */
9205 /* Restore the original function */
9206 REG_WR(bp, reg, BP_ABS_FUNC(bp));
9210 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9213 bnx2x_int_disable(bp);
9215 bnx2x_undi_int_disable_e1h(bp);
9218 static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp)
9220 u32 val, base_addr, offset, mask, reset_reg;
9221 bool mac_stopped = false;
9222 u8 port = BP_PORT(bp);
9224 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9226 if (!CHIP_IS_E3(bp)) {
9227 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9228 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9229 if ((mask & reset_reg) && val) {
9231 BNX2X_DEV_INFO("Disable bmac Rx\n");
9232 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9233 : NIG_REG_INGRESS_BMAC0_MEM;
9234 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9235 : BIGMAC_REGISTER_BMAC_CONTROL;
9238 * use rd/wr since we cannot use dmae. This is safe
9239 * since MCP won't access the bus due to the request
9240 * to unload, and no function on the path can be
9241 * loaded at this time.
9243 wb_data[0] = REG_RD(bp, base_addr + offset);
9244 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9245 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9246 REG_WR(bp, base_addr + offset, wb_data[0]);
9247 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9250 BNX2X_DEV_INFO("Disable emac Rx\n");
9251 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9255 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9256 BNX2X_DEV_INFO("Disable xmac Rx\n");
9257 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9258 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9259 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9261 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9263 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9266 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9267 if (mask & reset_reg) {
9268 BNX2X_DEV_INFO("Disable umac Rx\n");
9269 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9270 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9280 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9281 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9282 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9283 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9285 static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port,
9289 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9291 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9292 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9294 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9295 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9297 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9301 static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp)
9303 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9305 BNX2X_ERR("MCP response failure, aborting\n");
9312 static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp)
9314 struct bnx2x_prev_path_list *tmp_list;
9317 if (down_trylock(&bnx2x_prev_sem))
9320 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9321 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9322 bp->pdev->bus->number == tmp_list->bus &&
9323 BP_PATH(bp) == tmp_list->path) {
9325 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9331 up(&bnx2x_prev_sem);
9336 static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
9338 struct bnx2x_prev_path_list *tmp_list;
9341 tmp_list = (struct bnx2x_prev_path_list *)
9342 kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9344 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9348 tmp_list->bus = bp->pdev->bus->number;
9349 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9350 tmp_list->path = BP_PATH(bp);
9352 rc = down_interruptible(&bnx2x_prev_sem);
9354 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9357 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9359 list_add(&tmp_list->list, &bnx2x_prev_list);
9360 up(&bnx2x_prev_sem);
9366 static bool __devinit bnx2x_can_flr(struct bnx2x *bp)
9370 struct pci_dev *dev = bp->pdev;
9372 pos = pci_pcie_cap(dev);
9376 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
9377 if (!(cap & PCI_EXP_DEVCAP_FLR))
9383 static int __devinit bnx2x_do_flr(struct bnx2x *bp)
9387 struct pci_dev *dev = bp->pdev;
9389 /* probe the capability first */
9390 if (bnx2x_can_flr(bp))
9393 pos = pci_pcie_cap(dev);
9397 /* Wait for Transaction Pending bit clean */
9398 for (i = 0; i < 4; i++) {
9400 msleep((1 << (i - 1)) * 100);
9402 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
9403 if (!(status & PCI_EXP_DEVSTA_TRPND))
9408 "transaction is not cleared; proceeding with reset anyway\n");
9411 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9412 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9417 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9422 static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9426 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9428 /* Test if previous unload process was already finished for this path */
9429 if (bnx2x_prev_is_path_marked(bp))
9430 return bnx2x_prev_mcp_done(bp);
9432 /* If function has FLR capabilities, and existing FW version matches
9433 * the one required, then FLR will be sufficient to clean any residue
9434 * left by previous driver
9436 if (bnx2x_test_firmware_version(bp, false) && bnx2x_can_flr(bp))
9437 return bnx2x_do_flr(bp);
9439 /* Close the MCP request, return failure*/
9440 rc = bnx2x_prev_mcp_done(bp);
9442 rc = BNX2X_PREV_WAIT_NEEDED;
9447 static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp)
9449 u32 reset_reg, tmp_reg = 0, rc;
9450 /* It is possible a previous function received 'common' answer,
9451 * but hasn't loaded yet, therefore creating a scenario of
9452 * multiple functions receiving 'common' on the same path.
9454 BNX2X_DEV_INFO("Common unload Flow\n");
9456 if (bnx2x_prev_is_path_marked(bp))
9457 return bnx2x_prev_mcp_done(bp);
9459 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9461 /* Reset should be performed after BRB is emptied */
9462 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9463 u32 timer_count = 1000;
9464 bool prev_undi = false;
9466 /* Close the MAC Rx to prevent BRB from filling up */
9467 bnx2x_prev_unload_close_mac(bp);
9469 /* Check if the UNDI driver was previously loaded
9470 * UNDI driver initializes CID offset for normal bell to 0x7
9472 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9473 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9474 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9475 if (tmp_reg == 0x7) {
9476 BNX2X_DEV_INFO("UNDI previously loaded\n");
9478 /* clear the UNDI indication */
9479 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9482 /* wait until BRB is empty */
9483 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9484 while (timer_count) {
9485 u32 prev_brb = tmp_reg;
9487 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9491 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9493 /* reset timer as long as BRB actually gets emptied */
9494 if (prev_brb > tmp_reg)
9499 /* If UNDI resides in memory, manually increment it */
9501 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9507 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9511 /* No packets are in the pipeline, path is ready for reset */
9512 bnx2x_reset_common(bp);
9514 rc = bnx2x_prev_mark_path(bp);
9516 bnx2x_prev_mcp_done(bp);
9520 return bnx2x_prev_mcp_done(bp);
9523 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9524 * and boot began, or when kdump kernel was loaded. Either case would invalidate
9525 * the addresses of the transaction, resulting in was-error bit set in the pci
9526 * causing all hw-to-host pcie transactions to timeout. If this happened we want
9527 * to clear the interrupt which detected this from the pglueb and the was done
9530 static void __devinit bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9532 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9533 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9534 BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9535 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << BP_FUNC(bp));
9539 static int __devinit bnx2x_prev_unload(struct bnx2x *bp)
9541 int time_counter = 10;
9542 u32 rc, fw, hw_lock_reg, hw_lock_val;
9543 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9545 /* clear hw from errors which may have resulted from an interrupted
9548 bnx2x_prev_interrupted_dmae(bp);
9550 /* Release previously held locks */
9551 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9552 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9553 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9555 hw_lock_val = (REG_RD(bp, hw_lock_reg));
9557 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9558 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9559 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9560 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9563 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9564 REG_WR(bp, hw_lock_reg, 0xffffffff);
9566 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9568 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9569 BNX2X_DEV_INFO("Release previously held alr\n");
9570 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9575 /* Lock MCP using an unload request */
9576 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9578 BNX2X_ERR("MCP response failure, aborting\n");
9583 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9584 rc = bnx2x_prev_unload_common(bp);
9588 /* non-common reply from MCP night require looping */
9589 rc = bnx2x_prev_unload_uncommon(bp);
9590 if (rc != BNX2X_PREV_WAIT_NEEDED)
9594 } while (--time_counter);
9596 if (!time_counter || rc) {
9597 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9601 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9606 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
9608 u32 val, val2, val3, val4, id, boot_mode;
9611 /* Get the chip revision id and number. */
9612 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9613 val = REG_RD(bp, MISC_REG_CHIP_NUM);
9614 id = ((val & 0xffff) << 16);
9615 val = REG_RD(bp, MISC_REG_CHIP_REV);
9616 id |= ((val & 0xf) << 12);
9617 val = REG_RD(bp, MISC_REG_CHIP_METAL);
9618 id |= ((val & 0xff) << 4);
9619 val = REG_RD(bp, MISC_REG_BOND_ID);
9621 bp->common.chip_id = id;
9623 /* force 57811 according to MISC register */
9624 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
9625 if (CHIP_IS_57810(bp))
9626 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
9627 (bp->common.chip_id & 0x0000FFFF);
9628 else if (CHIP_IS_57810_MF(bp))
9629 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
9630 (bp->common.chip_id & 0x0000FFFF);
9631 bp->common.chip_id |= 0x1;
9634 /* Set doorbell size */
9635 bp->db_size = (1 << BNX2X_DB_SHIFT);
9637 if (!CHIP_IS_E1x(bp)) {
9638 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
9640 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
9642 val = (val >> 1) & 1;
9643 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
9645 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
9648 if (CHIP_MODE_IS_4_PORT(bp))
9649 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
9651 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
9653 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
9654 bp->pfid = bp->pf_num; /* 0..7 */
9657 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
9659 bp->link_params.chip_id = bp->common.chip_id;
9660 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
9662 val = (REG_RD(bp, 0x2874) & 0x55);
9663 if ((bp->common.chip_id & 0x1) ||
9664 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9665 bp->flags |= ONE_PORT_FLAG;
9666 BNX2X_DEV_INFO("single port device\n");
9669 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
9670 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
9671 (val & MCPR_NVM_CFG4_FLASH_SIZE));
9672 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9673 bp->common.flash_size, bp->common.flash_size);
9675 bnx2x_init_shmem(bp);
9679 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9680 MISC_REG_GENERIC_CR_1 :
9681 MISC_REG_GENERIC_CR_0));
9683 bp->link_params.shmem_base = bp->common.shmem_base;
9684 bp->link_params.shmem2_base = bp->common.shmem2_base;
9685 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
9686 bp->common.shmem_base, bp->common.shmem2_base);
9688 if (!bp->common.shmem_base) {
9689 BNX2X_DEV_INFO("MCP not active\n");
9690 bp->flags |= NO_MCP_FLAG;
9694 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
9695 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
9697 bp->link_params.hw_led_mode = ((bp->common.hw_config &
9698 SHARED_HW_CFG_LED_MODE_MASK) >>
9699 SHARED_HW_CFG_LED_MODE_SHIFT);
9701 bp->link_params.feature_config_flags = 0;
9702 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
9703 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
9704 bp->link_params.feature_config_flags |=
9705 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9707 bp->link_params.feature_config_flags &=
9708 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9710 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9711 bp->common.bc_ver = val;
9712 BNX2X_DEV_INFO("bc_ver %X\n", val);
9713 if (val < BNX2X_BC_VER) {
9714 /* for now only warn
9715 * later we might need to enforce this */
9716 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9719 bp->link_params.feature_config_flags |=
9720 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
9721 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9723 bp->link_params.feature_config_flags |=
9724 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9725 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
9726 bp->link_params.feature_config_flags |=
9727 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
9728 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
9729 bp->link_params.feature_config_flags |=
9730 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9731 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
9732 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9733 BC_SUPPORTS_PFC_STATS : 0;
9735 boot_mode = SHMEM_RD(bp,
9736 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9737 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
9738 switch (boot_mode) {
9739 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
9740 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9742 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
9743 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9745 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
9746 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9748 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
9749 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9753 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9754 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9756 BNX2X_DEV_INFO("%sWoL capable\n",
9757 (bp->flags & NO_WOL_FLAG) ? "not " : "");
9759 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9760 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9761 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9762 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9764 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
9765 val, val2, val3, val4);
9768 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9769 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9771 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
9773 int pfid = BP_FUNC(bp);
9776 u8 fid, igu_sb_cnt = 0;
9778 bp->igu_base_sb = 0xff;
9779 if (CHIP_INT_MODE_IS_BC(bp)) {
9781 igu_sb_cnt = bp->igu_sb_cnt;
9782 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
9785 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
9786 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
9791 /* IGU in normal mode - read CAM */
9792 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
9794 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
9795 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
9798 if ((fid & IGU_FID_ENCODE_IS_PF)) {
9799 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
9801 if (IGU_VEC(val) == 0)
9802 /* default status block */
9803 bp->igu_dsb_id = igu_sb_id;
9805 if (bp->igu_base_sb == 0xff)
9806 bp->igu_base_sb = igu_sb_id;
9812 #ifdef CONFIG_PCI_MSI
9814 * It's expected that number of CAM entries for this functions is equal
9815 * to the number evaluated based on the MSI-X table size. We want a
9816 * harsh warning if these values are different!
9818 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
9821 if (igu_sb_cnt == 0)
9822 BNX2X_ERR("CAM configuration error\n");
9825 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9828 int cfg_size = 0, idx, port = BP_PORT(bp);
9830 /* Aggregation of supported attributes of all external phys */
9831 bp->port.supported[0] = 0;
9832 bp->port.supported[1] = 0;
9833 switch (bp->link_params.num_phys) {
9835 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
9839 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
9843 if (bp->link_params.multi_phy_config &
9844 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
9845 bp->port.supported[1] =
9846 bp->link_params.phy[EXT_PHY1].supported;
9847 bp->port.supported[0] =
9848 bp->link_params.phy[EXT_PHY2].supported;
9850 bp->port.supported[0] =
9851 bp->link_params.phy[EXT_PHY1].supported;
9852 bp->port.supported[1] =
9853 bp->link_params.phy[EXT_PHY2].supported;
9859 if (!(bp->port.supported[0] || bp->port.supported[1])) {
9860 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
9862 dev_info.port_hw_config[port].external_phy_config),
9864 dev_info.port_hw_config[port].external_phy_config2));
9869 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
9871 switch (switch_cfg) {
9873 bp->port.phy_addr = REG_RD(
9874 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
9876 case SWITCH_CFG_10G:
9877 bp->port.phy_addr = REG_RD(
9878 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
9881 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9882 bp->port.link_config[0]);
9886 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
9887 /* mask what we support according to speed_cap_mask per configuration */
9888 for (idx = 0; idx < cfg_size; idx++) {
9889 if (!(bp->link_params.speed_cap_mask[idx] &
9890 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
9891 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
9893 if (!(bp->link_params.speed_cap_mask[idx] &
9894 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
9895 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
9897 if (!(bp->link_params.speed_cap_mask[idx] &
9898 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
9899 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
9901 if (!(bp->link_params.speed_cap_mask[idx] &
9902 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
9903 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
9905 if (!(bp->link_params.speed_cap_mask[idx] &
9906 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
9907 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
9908 SUPPORTED_1000baseT_Full);
9910 if (!(bp->link_params.speed_cap_mask[idx] &
9911 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
9912 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
9914 if (!(bp->link_params.speed_cap_mask[idx] &
9915 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
9916 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
9920 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
9921 bp->port.supported[1]);
9924 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9926 u32 link_config, idx, cfg_size = 0;
9927 bp->port.advertising[0] = 0;
9928 bp->port.advertising[1] = 0;
9929 switch (bp->link_params.num_phys) {
9938 for (idx = 0; idx < cfg_size; idx++) {
9939 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9940 link_config = bp->port.link_config[idx];
9941 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
9942 case PORT_FEATURE_LINK_SPEED_AUTO:
9943 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9944 bp->link_params.req_line_speed[idx] =
9946 bp->port.advertising[idx] |=
9947 bp->port.supported[idx];
9948 if (bp->link_params.phy[EXT_PHY1].type ==
9949 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9950 bp->port.advertising[idx] |=
9951 (SUPPORTED_100baseT_Half |
9952 SUPPORTED_100baseT_Full);
9954 /* force 10G, no AN */
9955 bp->link_params.req_line_speed[idx] =
9957 bp->port.advertising[idx] |=
9958 (ADVERTISED_10000baseT_Full |
9964 case PORT_FEATURE_LINK_SPEED_10M_FULL:
9965 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9966 bp->link_params.req_line_speed[idx] =
9968 bp->port.advertising[idx] |=
9969 (ADVERTISED_10baseT_Full |
9972 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9974 bp->link_params.speed_cap_mask[idx]);
9979 case PORT_FEATURE_LINK_SPEED_10M_HALF:
9980 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9981 bp->link_params.req_line_speed[idx] =
9983 bp->link_params.req_duplex[idx] =
9985 bp->port.advertising[idx] |=
9986 (ADVERTISED_10baseT_Half |
9989 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9991 bp->link_params.speed_cap_mask[idx]);
9996 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9997 if (bp->port.supported[idx] &
9998 SUPPORTED_100baseT_Full) {
9999 bp->link_params.req_line_speed[idx] =
10001 bp->port.advertising[idx] |=
10002 (ADVERTISED_100baseT_Full |
10005 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10007 bp->link_params.speed_cap_mask[idx]);
10012 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10013 if (bp->port.supported[idx] &
10014 SUPPORTED_100baseT_Half) {
10015 bp->link_params.req_line_speed[idx] =
10017 bp->link_params.req_duplex[idx] =
10019 bp->port.advertising[idx] |=
10020 (ADVERTISED_100baseT_Half |
10023 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10025 bp->link_params.speed_cap_mask[idx]);
10030 case PORT_FEATURE_LINK_SPEED_1G:
10031 if (bp->port.supported[idx] &
10032 SUPPORTED_1000baseT_Full) {
10033 bp->link_params.req_line_speed[idx] =
10035 bp->port.advertising[idx] |=
10036 (ADVERTISED_1000baseT_Full |
10039 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10041 bp->link_params.speed_cap_mask[idx]);
10046 case PORT_FEATURE_LINK_SPEED_2_5G:
10047 if (bp->port.supported[idx] &
10048 SUPPORTED_2500baseX_Full) {
10049 bp->link_params.req_line_speed[idx] =
10051 bp->port.advertising[idx] |=
10052 (ADVERTISED_2500baseX_Full |
10055 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10057 bp->link_params.speed_cap_mask[idx]);
10062 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10063 if (bp->port.supported[idx] &
10064 SUPPORTED_10000baseT_Full) {
10065 bp->link_params.req_line_speed[idx] =
10067 bp->port.advertising[idx] |=
10068 (ADVERTISED_10000baseT_Full |
10071 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10073 bp->link_params.speed_cap_mask[idx]);
10077 case PORT_FEATURE_LINK_SPEED_20G:
10078 bp->link_params.req_line_speed[idx] = SPEED_20000;
10082 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10084 bp->link_params.req_line_speed[idx] =
10086 bp->port.advertising[idx] =
10087 bp->port.supported[idx];
10091 bp->link_params.req_flow_ctrl[idx] = (link_config &
10092 PORT_FEATURE_FLOW_CONTROL_MASK);
10093 if ((bp->link_params.req_flow_ctrl[idx] ==
10094 BNX2X_FLOW_CTRL_AUTO) &&
10095 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
10096 bp->link_params.req_flow_ctrl[idx] =
10097 BNX2X_FLOW_CTRL_NONE;
10100 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10101 bp->link_params.req_line_speed[idx],
10102 bp->link_params.req_duplex[idx],
10103 bp->link_params.req_flow_ctrl[idx],
10104 bp->port.advertising[idx]);
10108 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10110 mac_hi = cpu_to_be16(mac_hi);
10111 mac_lo = cpu_to_be32(mac_lo);
10112 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10113 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10116 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
10118 int port = BP_PORT(bp);
10120 u32 ext_phy_type, ext_phy_config, eee_mode;
10122 bp->link_params.bp = bp;
10123 bp->link_params.port = port;
10125 bp->link_params.lane_config =
10126 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10128 bp->link_params.speed_cap_mask[0] =
10130 dev_info.port_hw_config[port].speed_capability_mask);
10131 bp->link_params.speed_cap_mask[1] =
10133 dev_info.port_hw_config[port].speed_capability_mask2);
10134 bp->port.link_config[0] =
10135 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10137 bp->port.link_config[1] =
10138 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10140 bp->link_params.multi_phy_config =
10141 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10142 /* If the device is capable of WoL, set the default state according
10145 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10146 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10147 (config & PORT_FEATURE_WOL_ENABLED));
10149 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10150 bp->link_params.lane_config,
10151 bp->link_params.speed_cap_mask[0],
10152 bp->port.link_config[0]);
10154 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10155 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10156 bnx2x_phy_probe(&bp->link_params);
10157 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10159 bnx2x_link_settings_requested(bp);
10162 * If connected directly, work with the internal PHY, otherwise, work
10163 * with the external PHY
10167 dev_info.port_hw_config[port].external_phy_config);
10168 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10169 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10170 bp->mdio.prtad = bp->port.phy_addr;
10172 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10173 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10175 XGXS_EXT_PHY_ADDR(ext_phy_config);
10178 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
10179 * In MF mode, it is set to cover self test cases
10182 bp->port.need_hw_lock = 1;
10184 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
10185 bp->common.shmem_base,
10186 bp->common.shmem2_base);
10188 /* Configure link feature according to nvram value */
10189 eee_mode = (((SHMEM_RD(bp, dev_info.
10190 port_feature_config[port].eee_power_mode)) &
10191 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10192 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10193 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10194 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10195 EEE_MODE_ENABLE_LPI |
10196 EEE_MODE_OUTPUT_TIME;
10198 bp->link_params.eee_mode = 0;
10202 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10204 u32 no_flags = NO_ISCSI_FLAG;
10206 int port = BP_PORT(bp);
10208 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10209 drv_lic_key[port].max_iscsi_conn);
10211 /* Get the number of maximum allowed iSCSI connections */
10212 bp->cnic_eth_dev.max_iscsi_conn =
10213 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10214 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10216 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10217 bp->cnic_eth_dev.max_iscsi_conn);
10220 * If maximum allowed number of connections is zero -
10221 * disable the feature.
10223 if (!bp->cnic_eth_dev.max_iscsi_conn)
10224 bp->flags |= no_flags;
10226 bp->flags |= no_flags;
10231 static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10234 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10235 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10236 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10237 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10240 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10241 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10242 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10243 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10246 static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
10249 int port = BP_PORT(bp);
10250 int func = BP_ABS_FUNC(bp);
10252 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10253 drv_lic_key[port].max_fcoe_conn);
10255 /* Get the number of maximum allowed FCoE connections */
10256 bp->cnic_eth_dev.max_fcoe_conn =
10257 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10258 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10260 /* Read the WWN: */
10263 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10265 dev_info.port_hw_config[port].
10266 fcoe_wwn_port_name_upper);
10267 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10269 dev_info.port_hw_config[port].
10270 fcoe_wwn_port_name_lower);
10273 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10275 dev_info.port_hw_config[port].
10276 fcoe_wwn_node_name_upper);
10277 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10279 dev_info.port_hw_config[port].
10280 fcoe_wwn_node_name_lower);
10281 } else if (!IS_MF_SD(bp)) {
10282 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10285 * Read the WWN info only if the FCoE feature is enabled for
10288 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
10289 bnx2x_get_ext_wwn_info(bp, func);
10291 } else if (IS_MF_FCOE_SD(bp))
10292 bnx2x_get_ext_wwn_info(bp, func);
10294 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10297 * If maximum allowed number of connections is zero -
10298 * disable the feature.
10300 if (!bp->cnic_eth_dev.max_fcoe_conn)
10301 bp->flags |= NO_FCOE_FLAG;
10303 bp->flags |= NO_FCOE_FLAG;
10307 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
10310 * iSCSI may be dynamically disabled but reading
10311 * info here we will decrease memory usage by driver
10312 * if the feature is disabled for good
10314 bnx2x_get_iscsi_info(bp);
10315 bnx2x_get_fcoe_info(bp);
10318 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10321 int func = BP_ABS_FUNC(bp);
10322 int port = BP_PORT(bp);
10324 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10325 u8 *fip_mac = bp->fip_mac;
10328 /* Zero primary MAC configuration */
10329 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10331 if (BP_NOMCP(bp)) {
10332 BNX2X_ERROR("warning: random MAC workaround active\n");
10333 eth_hw_addr_random(bp->dev);
10334 } else if (IS_MF(bp)) {
10335 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10336 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10337 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10338 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10339 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10343 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10344 * FCoE MAC then the appropriate feature should be disabled.
10346 * In non SD mode features configuration comes from
10347 * struct func_ext_config.
10349 if (!IS_MF_SD(bp)) {
10350 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10351 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10352 val2 = MF_CFG_RD(bp, func_ext_config[func].
10353 iscsi_mac_addr_upper);
10354 val = MF_CFG_RD(bp, func_ext_config[func].
10355 iscsi_mac_addr_lower);
10356 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10357 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
10360 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10362 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10363 val2 = MF_CFG_RD(bp, func_ext_config[func].
10364 fcoe_mac_addr_upper);
10365 val = MF_CFG_RD(bp, func_ext_config[func].
10366 fcoe_mac_addr_lower);
10367 bnx2x_set_mac_buf(fip_mac, val, val2);
10368 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
10372 bp->flags |= NO_FCOE_FLAG;
10374 bp->mf_ext_config = cfg;
10376 } else { /* SD MODE */
10377 if (IS_MF_STORAGE_SD(bp)) {
10378 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10379 /* use primary mac as iscsi mac */
10380 memcpy(iscsi_mac, bp->dev->dev_addr,
10383 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10384 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
10386 } else { /* FCoE */
10387 memcpy(fip_mac, bp->dev->dev_addr,
10389 BNX2X_DEV_INFO("SD FCoE MODE\n");
10390 BNX2X_DEV_INFO("Read FIP MAC: %pM\n",
10393 /* Zero primary MAC configuration */
10394 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10398 if (IS_MF_FCOE_AFEX(bp))
10399 /* use FIP MAC as primary MAC */
10400 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10404 /* in SF read MACs from port configuration */
10405 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10406 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10407 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10410 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10412 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10414 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10416 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10417 fcoe_fip_mac_upper);
10418 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10419 fcoe_fip_mac_lower);
10420 bnx2x_set_mac_buf(fip_mac, val, val2);
10424 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10425 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
10428 /* Disable iSCSI if MAC configuration is
10431 if (!is_valid_ether_addr(iscsi_mac)) {
10432 bp->flags |= NO_ISCSI_FLAG;
10433 memset(iscsi_mac, 0, ETH_ALEN);
10436 /* Disable FCoE if MAC configuration is
10439 if (!is_valid_ether_addr(fip_mac)) {
10440 bp->flags |= NO_FCOE_FLAG;
10441 memset(bp->fip_mac, 0, ETH_ALEN);
10445 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10446 dev_err(&bp->pdev->dev,
10447 "bad Ethernet MAC address configuration: %pM\n"
10448 "change it manually before bringing up the appropriate network interface\n",
10449 bp->dev->dev_addr);
10454 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
10456 int /*abs*/func = BP_ABS_FUNC(bp);
10461 bnx2x_get_common_hwinfo(bp);
10464 * initialize IGU parameters
10466 if (CHIP_IS_E1x(bp)) {
10467 bp->common.int_block = INT_BLOCK_HC;
10469 bp->igu_dsb_id = DEF_SB_IGU_ID;
10470 bp->igu_base_sb = 0;
10472 bp->common.int_block = INT_BLOCK_IGU;
10474 /* do not allow device reset during IGU info preocessing */
10475 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10477 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10479 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10482 BNX2X_DEV_INFO("FORCING Normal Mode\n");
10484 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10485 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10486 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10488 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10490 usleep_range(1000, 1000);
10493 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10494 dev_err(&bp->pdev->dev,
10495 "FORCING Normal Mode failed!!!\n");
10500 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10501 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10502 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10504 BNX2X_DEV_INFO("IGU Normal Mode\n");
10506 bnx2x_get_igu_cam_info(bp);
10508 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10512 * set base FW non-default (fast path) status block id, this value is
10513 * used to initialize the fw_sb_id saved on the fp/queue structure to
10514 * determine the id used by the FW.
10516 if (CHIP_IS_E1x(bp))
10517 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10519 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10520 * the same queue are indicated on the same IGU SB). So we prefer
10521 * FW and IGU SBs to be the same value.
10523 bp->base_fw_ndsb = bp->igu_base_sb;
10525 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10526 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10527 bp->igu_sb_cnt, bp->base_fw_ndsb);
10530 * Initialize MF configuration
10537 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10538 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10539 bp->common.shmem2_base, SHMEM2_RD(bp, size),
10540 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10542 if (SHMEM2_HAS(bp, mf_cfg_addr))
10543 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10545 bp->common.mf_cfg_base = bp->common.shmem_base +
10546 offsetof(struct shmem_region, func_mb) +
10547 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
10549 * get mf configuration:
10550 * 1. existence of MF configuration
10551 * 2. MAC address must be legal (check only upper bytes)
10552 * for Switch-Independent mode;
10553 * OVLAN must be legal for Switch-Dependent mode
10554 * 3. SF_MODE configures specific MF mode
10556 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10557 /* get mf configuration */
10559 dev_info.shared_feature_config.config);
10560 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
10563 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
10564 val = MF_CFG_RD(bp, func_mf_config[func].
10566 /* check for legal mac (upper bytes)*/
10567 if (val != 0xffff) {
10568 bp->mf_mode = MULTI_FUNCTION_SI;
10569 bp->mf_config[vn] = MF_CFG_RD(bp,
10570 func_mf_config[func].config);
10572 BNX2X_DEV_INFO("illegal MAC address for SI\n");
10574 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
10575 if ((!CHIP_IS_E1x(bp)) &&
10576 (MF_CFG_RD(bp, func_mf_config[func].
10577 mac_upper) != 0xffff) &&
10579 afex_driver_support))) {
10580 bp->mf_mode = MULTI_FUNCTION_AFEX;
10581 bp->mf_config[vn] = MF_CFG_RD(bp,
10582 func_mf_config[func].config);
10584 BNX2X_DEV_INFO("can not configure afex mode\n");
10587 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
10588 /* get OV configuration */
10589 val = MF_CFG_RD(bp,
10590 func_mf_config[FUNC_0].e1hov_tag);
10591 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
10593 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10594 bp->mf_mode = MULTI_FUNCTION_SD;
10595 bp->mf_config[vn] = MF_CFG_RD(bp,
10596 func_mf_config[func].config);
10598 BNX2X_DEV_INFO("illegal OV for SD\n");
10601 /* Unknown configuration: reset mf_config */
10602 bp->mf_config[vn] = 0;
10603 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
10607 BNX2X_DEV_INFO("%s function mode\n",
10608 IS_MF(bp) ? "multi" : "single");
10610 switch (bp->mf_mode) {
10611 case MULTI_FUNCTION_SD:
10612 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
10613 FUNC_MF_CFG_E1HOV_TAG_MASK;
10614 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10616 bp->path_has_ovlan = true;
10618 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
10619 func, bp->mf_ov, bp->mf_ov);
10621 dev_err(&bp->pdev->dev,
10622 "No valid MF OV for func %d, aborting\n",
10627 case MULTI_FUNCTION_AFEX:
10628 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
10630 case MULTI_FUNCTION_SI:
10631 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
10636 dev_err(&bp->pdev->dev,
10637 "VN %d is in a single function mode, aborting\n",
10644 /* check if other port on the path needs ovlan:
10645 * Since MF configuration is shared between ports
10646 * Possible mixed modes are only
10647 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
10649 if (CHIP_MODE_IS_4_PORT(bp) &&
10650 !bp->path_has_ovlan &&
10652 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10653 u8 other_port = !BP_PORT(bp);
10654 u8 other_func = BP_PATH(bp) + 2*other_port;
10655 val = MF_CFG_RD(bp,
10656 func_mf_config[other_func].e1hov_tag);
10657 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
10658 bp->path_has_ovlan = true;
10662 /* adjust igu_sb_cnt to MF for E1x */
10663 if (CHIP_IS_E1x(bp) && IS_MF(bp))
10664 bp->igu_sb_cnt /= E1HVN_MAX;
10667 bnx2x_get_port_hwinfo(bp);
10669 /* Get MAC addresses */
10670 bnx2x_get_mac_hwinfo(bp);
10672 bnx2x_get_cnic_info(bp);
10677 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
10679 int cnt, i, block_end, rodi;
10680 char vpd_start[BNX2X_VPD_LEN+1];
10681 char str_id_reg[VENDOR_ID_LEN+1];
10682 char str_id_cap[VENDOR_ID_LEN+1];
10684 char *vpd_extended_data = NULL;
10687 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
10688 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
10690 if (cnt < BNX2X_VPD_LEN)
10691 goto out_not_found;
10693 /* VPD RO tag should be first tag after identifier string, hence
10694 * we should be able to find it in first BNX2X_VPD_LEN chars
10696 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
10697 PCI_VPD_LRDT_RO_DATA);
10699 goto out_not_found;
10701 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
10702 pci_vpd_lrdt_size(&vpd_start[i]);
10704 i += PCI_VPD_LRDT_TAG_SIZE;
10706 if (block_end > BNX2X_VPD_LEN) {
10707 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
10708 if (vpd_extended_data == NULL)
10709 goto out_not_found;
10711 /* read rest of vpd image into vpd_extended_data */
10712 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
10713 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
10714 block_end - BNX2X_VPD_LEN,
10715 vpd_extended_data + BNX2X_VPD_LEN);
10716 if (cnt < (block_end - BNX2X_VPD_LEN))
10717 goto out_not_found;
10718 vpd_data = vpd_extended_data;
10720 vpd_data = vpd_start;
10722 /* now vpd_data holds full vpd content in both cases */
10724 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10725 PCI_VPD_RO_KEYWORD_MFR_ID);
10727 goto out_not_found;
10729 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10731 if (len != VENDOR_ID_LEN)
10732 goto out_not_found;
10734 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10736 /* vendor specific info */
10737 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
10738 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
10739 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
10740 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
10742 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10743 PCI_VPD_RO_KEYWORD_VENDOR0);
10745 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10747 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10749 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
10750 memcpy(bp->fw_ver, &vpd_data[rodi], len);
10751 bp->fw_ver[len] = ' ';
10754 kfree(vpd_extended_data);
10758 kfree(vpd_extended_data);
10762 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
10766 if (CHIP_REV_IS_FPGA(bp))
10767 SET_FLAGS(flags, MODE_FPGA);
10768 else if (CHIP_REV_IS_EMUL(bp))
10769 SET_FLAGS(flags, MODE_EMUL);
10771 SET_FLAGS(flags, MODE_ASIC);
10773 if (CHIP_MODE_IS_4_PORT(bp))
10774 SET_FLAGS(flags, MODE_PORT4);
10776 SET_FLAGS(flags, MODE_PORT2);
10778 if (CHIP_IS_E2(bp))
10779 SET_FLAGS(flags, MODE_E2);
10780 else if (CHIP_IS_E3(bp)) {
10781 SET_FLAGS(flags, MODE_E3);
10782 if (CHIP_REV(bp) == CHIP_REV_Ax)
10783 SET_FLAGS(flags, MODE_E3_A0);
10784 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10785 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
10789 SET_FLAGS(flags, MODE_MF);
10790 switch (bp->mf_mode) {
10791 case MULTI_FUNCTION_SD:
10792 SET_FLAGS(flags, MODE_MF_SD);
10794 case MULTI_FUNCTION_SI:
10795 SET_FLAGS(flags, MODE_MF_SI);
10797 case MULTI_FUNCTION_AFEX:
10798 SET_FLAGS(flags, MODE_MF_AFEX);
10802 SET_FLAGS(flags, MODE_SF);
10804 #if defined(__LITTLE_ENDIAN)
10805 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
10806 #else /*(__BIG_ENDIAN)*/
10807 SET_FLAGS(flags, MODE_BIG_ENDIAN);
10809 INIT_MODE_FLAGS(bp) = flags;
10812 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10817 mutex_init(&bp->port.phy_mutex);
10818 mutex_init(&bp->fw_mb_mutex);
10819 spin_lock_init(&bp->stats_lock);
10821 mutex_init(&bp->cnic_mutex);
10824 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
10825 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
10826 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
10827 rc = bnx2x_get_hwinfo(bp);
10831 bnx2x_set_modes_bitmap(bp);
10833 rc = bnx2x_alloc_mem_bp(bp);
10837 bnx2x_read_fwinfo(bp);
10839 func = BP_FUNC(bp);
10841 /* need to reset chip if undi was active */
10842 if (!BP_NOMCP(bp)) {
10845 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10846 DRV_MSG_SEQ_NUMBER_MASK;
10847 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10849 bnx2x_prev_unload(bp);
10853 if (CHIP_REV_IS_FPGA(bp))
10854 dev_err(&bp->pdev->dev, "FPGA detected\n");
10856 if (BP_NOMCP(bp) && (func == 0))
10857 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
10859 bp->disable_tpa = disable_tpa;
10862 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
10865 /* Set TPA flags */
10866 if (bp->disable_tpa) {
10867 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
10868 bp->dev->features &= ~NETIF_F_LRO;
10870 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
10871 bp->dev->features |= NETIF_F_LRO;
10874 if (CHIP_IS_E1(bp))
10875 bp->dropless_fc = 0;
10877 bp->dropless_fc = dropless_fc;
10881 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
10883 /* make sure that the numbers are in the right granularity */
10884 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
10885 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
10887 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
10889 init_timer(&bp->timer);
10890 bp->timer.expires = jiffies + bp->current_interval;
10891 bp->timer.data = (unsigned long) bp;
10892 bp->timer.function = bnx2x_timer;
10894 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
10895 bnx2x_dcbx_init_params(bp);
10898 if (CHIP_IS_E1x(bp))
10899 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
10901 bp->cnic_base_cl_id = FP_SB_MAX_E2;
10904 /* multiple tx priority */
10905 if (CHIP_IS_E1x(bp))
10906 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
10907 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
10908 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
10909 if (CHIP_IS_E3B0(bp))
10910 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
10916 /****************************************************************************
10917 * General service functions
10918 ****************************************************************************/
10921 * net_device service functions
10924 /* called with rtnl_lock */
10925 static int bnx2x_open(struct net_device *dev)
10927 struct bnx2x *bp = netdev_priv(dev);
10928 bool global = false;
10929 int other_engine = BP_PATH(bp) ? 0 : 1;
10930 bool other_load_status, load_status;
10932 bp->stats_init = true;
10934 netif_carrier_off(dev);
10936 bnx2x_set_power_state(bp, PCI_D0);
10938 other_load_status = bnx2x_get_load_status(bp, other_engine);
10939 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
10942 * If parity had happen during the unload, then attentions
10943 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10944 * want the first function loaded on the current engine to
10945 * complete the recovery.
10947 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
10948 bnx2x_chk_parity_attn(bp, &global, true))
10951 * If there are attentions and they are in a global
10952 * blocks, set the GLOBAL_RESET bit regardless whether
10953 * it will be this function that will complete the
10957 bnx2x_set_reset_global(bp);
10960 * Only the first function on the current engine should
10961 * try to recover in open. In case of attentions in
10962 * global blocks only the first in the chip should try
10965 if ((!load_status &&
10966 (!global || !other_load_status)) &&
10967 bnx2x_trylock_leader_lock(bp) &&
10968 !bnx2x_leader_reset(bp)) {
10969 netdev_info(bp->dev, "Recovered in open\n");
10973 /* recovery has failed... */
10974 bnx2x_set_power_state(bp, PCI_D3hot);
10975 bp->recovery_state = BNX2X_RECOVERY_FAILED;
10977 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
10978 "If you still see this message after a few retries then power cycle is required.\n");
10983 bp->recovery_state = BNX2X_RECOVERY_DONE;
10984 return bnx2x_nic_load(bp, LOAD_OPEN);
10987 /* called with rtnl_lock */
10988 static int bnx2x_close(struct net_device *dev)
10990 struct bnx2x *bp = netdev_priv(dev);
10992 /* Unload the driver, release IRQs */
10993 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
10996 bnx2x_set_power_state(bp, PCI_D3hot);
11001 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11002 struct bnx2x_mcast_ramrod_params *p)
11004 int mc_count = netdev_mc_count(bp->dev);
11005 struct bnx2x_mcast_list_elem *mc_mac =
11006 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11007 struct netdev_hw_addr *ha;
11012 INIT_LIST_HEAD(&p->mcast_list);
11014 netdev_for_each_mc_addr(ha, bp->dev) {
11015 mc_mac->mac = bnx2x_mc_addr(ha);
11016 list_add_tail(&mc_mac->link, &p->mcast_list);
11020 p->mcast_list_len = mc_count;
11025 static void bnx2x_free_mcast_macs_list(
11026 struct bnx2x_mcast_ramrod_params *p)
11028 struct bnx2x_mcast_list_elem *mc_mac =
11029 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11037 * bnx2x_set_uc_list - configure a new unicast MACs list.
11039 * @bp: driver handle
11041 * We will use zero (0) as a MAC type for these MACs.
11043 static int bnx2x_set_uc_list(struct bnx2x *bp)
11046 struct net_device *dev = bp->dev;
11047 struct netdev_hw_addr *ha;
11048 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11049 unsigned long ramrod_flags = 0;
11051 /* First schedule a cleanup up of old configuration */
11052 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11054 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11058 netdev_for_each_uc_addr(ha, dev) {
11059 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11060 BNX2X_UC_LIST_MAC, &ramrod_flags);
11062 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11068 /* Execute the pending commands */
11069 __set_bit(RAMROD_CONT, &ramrod_flags);
11070 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11071 BNX2X_UC_LIST_MAC, &ramrod_flags);
11074 static int bnx2x_set_mc_list(struct bnx2x *bp)
11076 struct net_device *dev = bp->dev;
11077 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11080 rparam.mcast_obj = &bp->mcast_obj;
11082 /* first, clear all configured multicast MACs */
11083 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11085 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11089 /* then, configure a new MACs list */
11090 if (netdev_mc_count(dev)) {
11091 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11093 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11098 /* Now add the new MACs */
11099 rc = bnx2x_config_mcast(bp, &rparam,
11100 BNX2X_MCAST_CMD_ADD);
11102 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11105 bnx2x_free_mcast_macs_list(&rparam);
11112 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11113 void bnx2x_set_rx_mode(struct net_device *dev)
11115 struct bnx2x *bp = netdev_priv(dev);
11116 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11118 if (bp->state != BNX2X_STATE_OPEN) {
11119 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11123 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11125 if (dev->flags & IFF_PROMISC)
11126 rx_mode = BNX2X_RX_MODE_PROMISC;
11127 else if ((dev->flags & IFF_ALLMULTI) ||
11128 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11130 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11132 /* some multicasts */
11133 if (bnx2x_set_mc_list(bp) < 0)
11134 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11136 if (bnx2x_set_uc_list(bp) < 0)
11137 rx_mode = BNX2X_RX_MODE_PROMISC;
11140 bp->rx_mode = rx_mode;
11142 /* handle ISCSI SD mode */
11143 if (IS_MF_ISCSI_SD(bp))
11144 bp->rx_mode = BNX2X_RX_MODE_NONE;
11147 /* Schedule the rx_mode command */
11148 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11149 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11153 bnx2x_set_storm_rx_mode(bp);
11156 /* called with rtnl_lock */
11157 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11158 int devad, u16 addr)
11160 struct bnx2x *bp = netdev_priv(netdev);
11164 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11165 prtad, devad, addr);
11167 /* The HW expects different devad if CL22 is used */
11168 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11170 bnx2x_acquire_phy_lock(bp);
11171 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11172 bnx2x_release_phy_lock(bp);
11173 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11180 /* called with rtnl_lock */
11181 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11182 u16 addr, u16 value)
11184 struct bnx2x *bp = netdev_priv(netdev);
11188 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11189 prtad, devad, addr, value);
11191 /* The HW expects different devad if CL22 is used */
11192 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11194 bnx2x_acquire_phy_lock(bp);
11195 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11196 bnx2x_release_phy_lock(bp);
11200 /* called with rtnl_lock */
11201 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11203 struct bnx2x *bp = netdev_priv(dev);
11204 struct mii_ioctl_data *mdio = if_mii(ifr);
11206 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11207 mdio->phy_id, mdio->reg_num, mdio->val_in);
11209 if (!netif_running(dev))
11212 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11215 #ifdef CONFIG_NET_POLL_CONTROLLER
11216 static void poll_bnx2x(struct net_device *dev)
11218 struct bnx2x *bp = netdev_priv(dev);
11220 disable_irq(bp->pdev->irq);
11221 bnx2x_interrupt(bp->pdev->irq, dev);
11222 enable_irq(bp->pdev->irq);
11226 static int bnx2x_validate_addr(struct net_device *dev)
11228 struct bnx2x *bp = netdev_priv(dev);
11230 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11231 BNX2X_ERR("Non-valid Ethernet address\n");
11232 return -EADDRNOTAVAIL;
11237 static const struct net_device_ops bnx2x_netdev_ops = {
11238 .ndo_open = bnx2x_open,
11239 .ndo_stop = bnx2x_close,
11240 .ndo_start_xmit = bnx2x_start_xmit,
11241 .ndo_select_queue = bnx2x_select_queue,
11242 .ndo_set_rx_mode = bnx2x_set_rx_mode,
11243 .ndo_set_mac_address = bnx2x_change_mac_addr,
11244 .ndo_validate_addr = bnx2x_validate_addr,
11245 .ndo_do_ioctl = bnx2x_ioctl,
11246 .ndo_change_mtu = bnx2x_change_mtu,
11247 .ndo_fix_features = bnx2x_fix_features,
11248 .ndo_set_features = bnx2x_set_features,
11249 .ndo_tx_timeout = bnx2x_tx_timeout,
11250 #ifdef CONFIG_NET_POLL_CONTROLLER
11251 .ndo_poll_controller = poll_bnx2x,
11253 .ndo_setup_tc = bnx2x_setup_tc,
11255 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
11256 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11260 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11262 struct device *dev = &bp->pdev->dev;
11264 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11265 bp->flags |= USING_DAC_FLAG;
11266 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11267 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11270 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11271 dev_err(dev, "System does not support DMA, aborting\n");
11278 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
11279 struct net_device *dev,
11280 unsigned long board_type)
11285 bool chip_is_e1x = (board_type == BCM57710 ||
11286 board_type == BCM57711 ||
11287 board_type == BCM57711E);
11289 SET_NETDEV_DEV(dev, &pdev->dev);
11290 bp = netdev_priv(dev);
11296 rc = pci_enable_device(pdev);
11298 dev_err(&bp->pdev->dev,
11299 "Cannot enable PCI device, aborting\n");
11303 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11304 dev_err(&bp->pdev->dev,
11305 "Cannot find PCI device base address, aborting\n");
11307 goto err_out_disable;
11310 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11311 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
11312 " base address, aborting\n");
11314 goto err_out_disable;
11317 if (atomic_read(&pdev->enable_cnt) == 1) {
11318 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11320 dev_err(&bp->pdev->dev,
11321 "Cannot obtain PCI resources, aborting\n");
11322 goto err_out_disable;
11325 pci_set_master(pdev);
11326 pci_save_state(pdev);
11329 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11330 if (bp->pm_cap == 0) {
11331 dev_err(&bp->pdev->dev,
11332 "Cannot find power management capability, aborting\n");
11334 goto err_out_release;
11337 if (!pci_is_pcie(pdev)) {
11338 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11340 goto err_out_release;
11343 rc = bnx2x_set_coherency_mask(bp);
11345 goto err_out_release;
11347 dev->mem_start = pci_resource_start(pdev, 0);
11348 dev->base_addr = dev->mem_start;
11349 dev->mem_end = pci_resource_end(pdev, 0);
11351 dev->irq = pdev->irq;
11353 bp->regview = pci_ioremap_bar(pdev, 0);
11354 if (!bp->regview) {
11355 dev_err(&bp->pdev->dev,
11356 "Cannot map register space, aborting\n");
11358 goto err_out_release;
11361 /* In E1/E1H use pci device function given by kernel.
11362 * In E2/E3 read physical function from ME register since these chips
11363 * support Physical Device Assignment where kernel BDF maybe arbitrary
11364 * (depending on hypervisor).
11367 bp->pf_num = PCI_FUNC(pdev->devfn);
11368 else {/* chip is E2/3*/
11369 pci_read_config_dword(bp->pdev,
11370 PCICFG_ME_REGISTER, &pci_cfg_dword);
11371 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11372 ME_REG_ABS_PF_NUM_SHIFT);
11374 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11376 bnx2x_set_power_state(bp, PCI_D0);
11378 /* clean indirect addresses */
11379 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11380 PCICFG_VENDOR_ID_OFFSET);
11382 * Clean the following indirect addresses for all functions since it
11383 * is not used by the driver.
11385 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11386 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11387 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11388 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11391 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11392 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11393 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11394 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11398 * Enable internal target-read (in case we are probed after PF FLR).
11399 * Must be done prior to any BAR read access. Only for 57712 and up
11402 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11404 /* Reset the load counter */
11405 bnx2x_clear_load_status(bp);
11407 dev->watchdog_timeo = TX_TIMEOUT;
11409 dev->netdev_ops = &bnx2x_netdev_ops;
11410 bnx2x_set_ethtool_ops(dev);
11412 dev->priv_flags |= IFF_UNICAST_FLT;
11414 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11415 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11416 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11417 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11419 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11420 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11422 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11423 if (bp->flags & USING_DAC_FLAG)
11424 dev->features |= NETIF_F_HIGHDMA;
11426 /* Add Loopback capability to the device */
11427 dev->hw_features |= NETIF_F_LOOPBACK;
11430 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11433 /* get_port_hwinfo() will set prtad and mmds properly */
11434 bp->mdio.prtad = MDIO_PRTAD_NONE;
11436 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11437 bp->mdio.dev = dev;
11438 bp->mdio.mdio_read = bnx2x_mdio_read;
11439 bp->mdio.mdio_write = bnx2x_mdio_write;
11444 if (atomic_read(&pdev->enable_cnt) == 1)
11445 pci_release_regions(pdev);
11448 pci_disable_device(pdev);
11449 pci_set_drvdata(pdev, NULL);
11455 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
11456 int *width, int *speed)
11458 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
11460 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11462 /* return value of 1=2.5GHz 2=5GHz */
11463 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
11466 static int bnx2x_check_firmware(struct bnx2x *bp)
11468 const struct firmware *firmware = bp->firmware;
11469 struct bnx2x_fw_file_hdr *fw_hdr;
11470 struct bnx2x_fw_file_section *sections;
11471 u32 offset, len, num_ops;
11476 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
11477 BNX2X_ERR("Wrong FW size\n");
11481 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11482 sections = (struct bnx2x_fw_file_section *)fw_hdr;
11484 /* Make sure none of the offsets and sizes make us read beyond
11485 * the end of the firmware data */
11486 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11487 offset = be32_to_cpu(sections[i].offset);
11488 len = be32_to_cpu(sections[i].len);
11489 if (offset + len > firmware->size) {
11490 BNX2X_ERR("Section %d length is out of bounds\n", i);
11495 /* Likewise for the init_ops offsets */
11496 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11497 ops_offsets = (u16 *)(firmware->data + offset);
11498 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11500 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11501 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
11502 BNX2X_ERR("Section offset %d is out of bounds\n", i);
11507 /* Check FW version */
11508 offset = be32_to_cpu(fw_hdr->fw_version.offset);
11509 fw_ver = firmware->data + offset;
11510 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11511 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11512 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11513 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
11514 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
11515 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
11516 BCM_5710_FW_MAJOR_VERSION,
11517 BCM_5710_FW_MINOR_VERSION,
11518 BCM_5710_FW_REVISION_VERSION,
11519 BCM_5710_FW_ENGINEERING_VERSION);
11526 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11528 const __be32 *source = (const __be32 *)_source;
11529 u32 *target = (u32 *)_target;
11532 for (i = 0; i < n/4; i++)
11533 target[i] = be32_to_cpu(source[i]);
11537 Ops array is stored in the following format:
11538 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
11540 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
11542 const __be32 *source = (const __be32 *)_source;
11543 struct raw_op *target = (struct raw_op *)_target;
11546 for (i = 0, j = 0; i < n/8; i++, j += 2) {
11547 tmp = be32_to_cpu(source[j]);
11548 target[i].op = (tmp >> 24) & 0xff;
11549 target[i].offset = tmp & 0xffffff;
11550 target[i].raw_data = be32_to_cpu(source[j + 1]);
11555 * IRO array is stored in the following format:
11556 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
11558 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
11560 const __be32 *source = (const __be32 *)_source;
11561 struct iro *target = (struct iro *)_target;
11564 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
11565 target[i].base = be32_to_cpu(source[j]);
11567 tmp = be32_to_cpu(source[j]);
11568 target[i].m1 = (tmp >> 16) & 0xffff;
11569 target[i].m2 = tmp & 0xffff;
11571 tmp = be32_to_cpu(source[j]);
11572 target[i].m3 = (tmp >> 16) & 0xffff;
11573 target[i].size = tmp & 0xffff;
11578 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11580 const __be16 *source = (const __be16 *)_source;
11581 u16 *target = (u16 *)_target;
11584 for (i = 0; i < n/2; i++)
11585 target[i] = be16_to_cpu(source[i]);
11588 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
11590 u32 len = be32_to_cpu(fw_hdr->arr.len); \
11591 bp->arr = kmalloc(len, GFP_KERNEL); \
11594 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
11595 (u8 *)bp->arr, len); \
11598 static int bnx2x_init_firmware(struct bnx2x *bp)
11600 const char *fw_file_name;
11601 struct bnx2x_fw_file_hdr *fw_hdr;
11607 if (CHIP_IS_E1(bp))
11608 fw_file_name = FW_FILE_NAME_E1;
11609 else if (CHIP_IS_E1H(bp))
11610 fw_file_name = FW_FILE_NAME_E1H;
11611 else if (!CHIP_IS_E1x(bp))
11612 fw_file_name = FW_FILE_NAME_E2;
11614 BNX2X_ERR("Unsupported chip revision\n");
11617 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
11619 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
11621 BNX2X_ERR("Can't load firmware file %s\n",
11623 goto request_firmware_exit;
11626 rc = bnx2x_check_firmware(bp);
11628 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
11629 goto request_firmware_exit;
11632 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
11634 /* Initialize the pointers to the init arrays */
11636 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
11639 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
11642 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
11645 /* STORMs firmware */
11646 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11647 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
11648 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
11649 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
11650 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11651 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
11652 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
11653 be32_to_cpu(fw_hdr->usem_pram_data.offset);
11654 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11655 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
11656 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
11657 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
11658 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11659 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
11660 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
11661 be32_to_cpu(fw_hdr->csem_pram_data.offset);
11663 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
11668 kfree(bp->init_ops_offsets);
11669 init_offsets_alloc_err:
11670 kfree(bp->init_ops);
11671 init_ops_alloc_err:
11672 kfree(bp->init_data);
11673 request_firmware_exit:
11674 release_firmware(bp->firmware);
11675 bp->firmware = NULL;
11680 static void bnx2x_release_firmware(struct bnx2x *bp)
11682 kfree(bp->init_ops_offsets);
11683 kfree(bp->init_ops);
11684 kfree(bp->init_data);
11685 release_firmware(bp->firmware);
11686 bp->firmware = NULL;
11690 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
11691 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
11692 .init_hw_cmn = bnx2x_init_hw_common,
11693 .init_hw_port = bnx2x_init_hw_port,
11694 .init_hw_func = bnx2x_init_hw_func,
11696 .reset_hw_cmn = bnx2x_reset_common,
11697 .reset_hw_port = bnx2x_reset_port,
11698 .reset_hw_func = bnx2x_reset_func,
11700 .gunzip_init = bnx2x_gunzip_init,
11701 .gunzip_end = bnx2x_gunzip_end,
11703 .init_fw = bnx2x_init_firmware,
11704 .release_fw = bnx2x_release_firmware,
11707 void bnx2x__init_func_obj(struct bnx2x *bp)
11709 /* Prepare DMAE related driver resources */
11710 bnx2x_setup_dmae(bp);
11712 bnx2x_init_func_obj(bp, &bp->func_obj,
11713 bnx2x_sp(bp, func_rdata),
11714 bnx2x_sp_mapping(bp, func_rdata),
11715 bnx2x_sp(bp, func_afex_rdata),
11716 bnx2x_sp_mapping(bp, func_afex_rdata),
11717 &bnx2x_func_sp_drv);
11720 /* must be called after sriov-enable */
11721 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
11723 int cid_count = BNX2X_L2_MAX_CID(bp);
11726 cid_count += CNIC_CID_MAX;
11728 return roundup(cid_count, QM_CID_ROUND);
11732 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
11737 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
11742 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
11745 * If MSI-X is not supported - return number of SBs needed to support
11746 * one fast path queue: one FP queue + SB for CNIC
11749 return 1 + CNIC_PRESENT;
11752 * The value in the PCI configuration space is the index of the last
11753 * entry, namely one less than the actual size of the table, which is
11754 * exactly what we want to return from this function: number of all SBs
11755 * without the default SB.
11757 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
11758 return control & PCI_MSIX_FLAGS_QSIZE;
11761 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11762 const struct pci_device_id *ent)
11764 struct net_device *dev = NULL;
11766 int pcie_width, pcie_speed;
11767 int rc, max_non_def_sbs;
11768 int rx_count, tx_count, rss_count, doorbell_size;
11770 * An estimated maximum supported CoS number according to the chip
11772 * We will try to roughly estimate the maximum number of CoSes this chip
11773 * may support in order to minimize the memory allocated for Tx
11774 * netdev_queue's. This number will be accurately calculated during the
11775 * initialization of bp->max_cos based on the chip versions AND chip
11776 * revision in the bnx2x_init_bp().
11778 u8 max_cos_est = 0;
11780 switch (ent->driver_data) {
11784 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
11789 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
11800 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
11804 pr_err("Unknown board_type (%ld), aborting\n",
11809 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
11811 WARN_ON(!max_non_def_sbs);
11813 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11814 rss_count = max_non_def_sbs - CNIC_PRESENT;
11816 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11817 rx_count = rss_count + FCOE_PRESENT;
11820 * Maximum number of netdev Tx queues:
11821 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11823 tx_count = rss_count * max_cos_est + FCOE_PRESENT;
11825 /* dev zeroed in init_etherdev */
11826 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
11830 bp = netdev_priv(dev);
11832 bp->igu_sb_cnt = max_non_def_sbs;
11833 bp->msg_enable = debug;
11834 pci_set_drvdata(pdev, dev);
11836 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
11842 BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs);
11844 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
11845 tx_count, rx_count);
11847 rc = bnx2x_init_bp(bp);
11849 goto init_one_exit;
11852 * Map doorbels here as we need the real value of bp->max_cos which
11853 * is initialized in bnx2x_init_bp().
11855 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
11856 if (doorbell_size > pci_resource_len(pdev, 2)) {
11857 dev_err(&bp->pdev->dev,
11858 "Cannot map doorbells, bar size too small, aborting\n");
11860 goto init_one_exit;
11862 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
11864 if (!bp->doorbells) {
11865 dev_err(&bp->pdev->dev,
11866 "Cannot map doorbell space, aborting\n");
11868 goto init_one_exit;
11871 /* calc qm_cid_count */
11872 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
11875 /* disable FCOE L2 queue for E1x */
11876 if (CHIP_IS_E1x(bp))
11877 bp->flags |= NO_FCOE_FLAG;
11882 /* Set bp->num_queues for MSI-X mode*/
11883 bnx2x_set_num_queues(bp);
11885 /* Configure interrupt mode: try to enable MSI-X/MSI if
11888 bnx2x_set_int_mode(bp);
11890 /* Add all NAPI objects */
11891 bnx2x_add_all_napi(bp);
11893 rc = register_netdev(dev);
11895 dev_err(&pdev->dev, "Cannot register net device\n");
11896 goto init_one_exit;
11900 if (!NO_FCOE(bp)) {
11901 /* Add storage MAC address */
11903 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11908 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
11911 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11912 board_info[ent->driver_data].name,
11913 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11915 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
11916 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
11917 "5GHz (Gen2)" : "2.5GHz",
11918 dev->base_addr, bp->pdev->irq, dev->dev_addr);
11924 iounmap(bp->regview);
11927 iounmap(bp->doorbells);
11931 if (atomic_read(&pdev->enable_cnt) == 1)
11932 pci_release_regions(pdev);
11934 pci_disable_device(pdev);
11935 pci_set_drvdata(pdev, NULL);
11940 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
11942 struct net_device *dev = pci_get_drvdata(pdev);
11946 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
11949 bp = netdev_priv(dev);
11952 /* Delete storage MAC address */
11953 if (!NO_FCOE(bp)) {
11955 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11961 /* Delete app tlvs from dcbnl */
11962 bnx2x_dcbnl_update_applist(bp, true);
11965 unregister_netdev(dev);
11967 /* Delete all NAPI objects */
11968 bnx2x_del_all_napi(bp);
11970 /* Power on: we can't let PCI layer write to us while we are in D3 */
11971 bnx2x_set_power_state(bp, PCI_D0);
11973 /* Disable MSI/MSI-X */
11974 bnx2x_disable_msi(bp);
11977 bnx2x_set_power_state(bp, PCI_D3hot);
11979 /* Make sure RESET task is not scheduled before continuing */
11980 cancel_delayed_work_sync(&bp->sp_rtnl_task);
11983 iounmap(bp->regview);
11986 iounmap(bp->doorbells);
11988 bnx2x_release_firmware(bp);
11990 bnx2x_free_mem_bp(bp);
11994 if (atomic_read(&pdev->enable_cnt) == 1)
11995 pci_release_regions(pdev);
11997 pci_disable_device(pdev);
11998 pci_set_drvdata(pdev, NULL);
12001 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12005 bp->state = BNX2X_STATE_ERROR;
12007 bp->rx_mode = BNX2X_RX_MODE_NONE;
12010 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12013 bnx2x_tx_disable(bp);
12015 bnx2x_netif_stop(bp, 0);
12017 del_timer_sync(&bp->timer);
12019 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12022 bnx2x_free_irq(bp);
12024 /* Free SKBs, SGEs, TPA pool and driver internals */
12025 bnx2x_free_skbs(bp);
12027 for_each_rx_queue(bp, i)
12028 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12030 bnx2x_free_mem(bp);
12032 bp->state = BNX2X_STATE_CLOSED;
12034 netif_carrier_off(bp->dev);
12039 static void bnx2x_eeh_recover(struct bnx2x *bp)
12043 mutex_init(&bp->port.phy_mutex);
12046 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12047 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12048 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12049 BNX2X_ERR("BAD MCP validity signature\n");
12053 * bnx2x_io_error_detected - called when PCI error is detected
12054 * @pdev: Pointer to PCI device
12055 * @state: The current pci connection state
12057 * This function is called after a PCI bus error affecting
12058 * this device has been detected.
12060 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12061 pci_channel_state_t state)
12063 struct net_device *dev = pci_get_drvdata(pdev);
12064 struct bnx2x *bp = netdev_priv(dev);
12068 netif_device_detach(dev);
12070 if (state == pci_channel_io_perm_failure) {
12072 return PCI_ERS_RESULT_DISCONNECT;
12075 if (netif_running(dev))
12076 bnx2x_eeh_nic_unload(bp);
12078 pci_disable_device(pdev);
12082 /* Request a slot reset */
12083 return PCI_ERS_RESULT_NEED_RESET;
12087 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12088 * @pdev: Pointer to PCI device
12090 * Restart the card from scratch, as if from a cold-boot.
12092 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12094 struct net_device *dev = pci_get_drvdata(pdev);
12095 struct bnx2x *bp = netdev_priv(dev);
12099 if (pci_enable_device(pdev)) {
12100 dev_err(&pdev->dev,
12101 "Cannot re-enable PCI device after reset\n");
12103 return PCI_ERS_RESULT_DISCONNECT;
12106 pci_set_master(pdev);
12107 pci_restore_state(pdev);
12109 if (netif_running(dev))
12110 bnx2x_set_power_state(bp, PCI_D0);
12114 return PCI_ERS_RESULT_RECOVERED;
12118 * bnx2x_io_resume - called when traffic can start flowing again
12119 * @pdev: Pointer to PCI device
12121 * This callback is called when the error recovery driver tells us that
12122 * its OK to resume normal operation.
12124 static void bnx2x_io_resume(struct pci_dev *pdev)
12126 struct net_device *dev = pci_get_drvdata(pdev);
12127 struct bnx2x *bp = netdev_priv(dev);
12129 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12130 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12136 bnx2x_eeh_recover(bp);
12138 if (netif_running(dev))
12139 bnx2x_nic_load(bp, LOAD_NORMAL);
12141 netif_device_attach(dev);
12146 static struct pci_error_handlers bnx2x_err_handler = {
12147 .error_detected = bnx2x_io_error_detected,
12148 .slot_reset = bnx2x_io_slot_reset,
12149 .resume = bnx2x_io_resume,
12152 static struct pci_driver bnx2x_pci_driver = {
12153 .name = DRV_MODULE_NAME,
12154 .id_table = bnx2x_pci_tbl,
12155 .probe = bnx2x_init_one,
12156 .remove = __devexit_p(bnx2x_remove_one),
12157 .suspend = bnx2x_suspend,
12158 .resume = bnx2x_resume,
12159 .err_handler = &bnx2x_err_handler,
12162 static int __init bnx2x_init(void)
12166 pr_info("%s", version);
12168 bnx2x_wq = create_singlethread_workqueue("bnx2x");
12169 if (bnx2x_wq == NULL) {
12170 pr_err("Cannot create workqueue\n");
12174 ret = pci_register_driver(&bnx2x_pci_driver);
12176 pr_err("Cannot register driver\n");
12177 destroy_workqueue(bnx2x_wq);
12182 static void __exit bnx2x_cleanup(void)
12184 struct list_head *pos, *q;
12185 pci_unregister_driver(&bnx2x_pci_driver);
12187 destroy_workqueue(bnx2x_wq);
12189 /* Free globablly allocated resources */
12190 list_for_each_safe(pos, q, &bnx2x_prev_list) {
12191 struct bnx2x_prev_path_list *tmp =
12192 list_entry(pos, struct bnx2x_prev_path_list, list);
12198 void bnx2x_notify_link_changed(struct bnx2x *bp)
12200 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12203 module_init(bnx2x_init);
12204 module_exit(bnx2x_cleanup);
12208 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12210 * @bp: driver handle
12211 * @set: set or clear the CAM entry
12213 * This function will wait until the ramdord completion returns.
12214 * Return 0 if success, -ENODEV if ramrod doesn't return.
12216 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12218 unsigned long ramrod_flags = 0;
12220 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12221 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12222 &bp->iscsi_l2_mac_obj, true,
12223 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12226 /* count denotes the number of new completions we have seen */
12227 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12229 struct eth_spe *spe;
12230 int cxt_index, cxt_offset;
12232 #ifdef BNX2X_STOP_ON_ERROR
12233 if (unlikely(bp->panic))
12237 spin_lock_bh(&bp->spq_lock);
12238 BUG_ON(bp->cnic_spq_pending < count);
12239 bp->cnic_spq_pending -= count;
12242 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12243 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12244 & SPE_HDR_CONN_TYPE) >>
12245 SPE_HDR_CONN_TYPE_SHIFT;
12246 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12247 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12249 /* Set validation for iSCSI L2 client before sending SETUP
12252 if (type == ETH_CONNECTION_TYPE) {
12253 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12254 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12256 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12257 (cxt_index * ILT_PAGE_CIDS);
12258 bnx2x_set_ctx_validation(bp,
12259 &bp->context[cxt_index].
12260 vcxt[cxt_offset].eth,
12261 BNX2X_ISCSI_ETH_CID(bp));
12266 * There may be not more than 8 L2, not more than 8 L5 SPEs
12267 * and in the air. We also check that number of outstanding
12268 * COMMON ramrods is not more than the EQ and SPQ can
12271 if (type == ETH_CONNECTION_TYPE) {
12272 if (!atomic_read(&bp->cq_spq_left))
12275 atomic_dec(&bp->cq_spq_left);
12276 } else if (type == NONE_CONNECTION_TYPE) {
12277 if (!atomic_read(&bp->eq_spq_left))
12280 atomic_dec(&bp->eq_spq_left);
12281 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12282 (type == FCOE_CONNECTION_TYPE)) {
12283 if (bp->cnic_spq_pending >=
12284 bp->cnic_eth_dev.max_kwqe_pending)
12287 bp->cnic_spq_pending++;
12289 BNX2X_ERR("Unknown SPE type: %d\n", type);
12294 spe = bnx2x_sp_get_next(bp);
12295 *spe = *bp->cnic_kwq_cons;
12297 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12298 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12300 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12301 bp->cnic_kwq_cons = bp->cnic_kwq;
12303 bp->cnic_kwq_cons++;
12305 bnx2x_sp_prod_update(bp);
12306 spin_unlock_bh(&bp->spq_lock);
12309 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12310 struct kwqe_16 *kwqes[], u32 count)
12312 struct bnx2x *bp = netdev_priv(dev);
12315 #ifdef BNX2X_STOP_ON_ERROR
12316 if (unlikely(bp->panic)) {
12317 BNX2X_ERR("Can't post to SP queue while panic\n");
12322 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12323 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12324 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12328 spin_lock_bh(&bp->spq_lock);
12330 for (i = 0; i < count; i++) {
12331 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12333 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12336 *bp->cnic_kwq_prod = *spe;
12338 bp->cnic_kwq_pending++;
12340 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12341 spe->hdr.conn_and_cmd_data, spe->hdr.type,
12342 spe->data.update_data_addr.hi,
12343 spe->data.update_data_addr.lo,
12344 bp->cnic_kwq_pending);
12346 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12347 bp->cnic_kwq_prod = bp->cnic_kwq;
12349 bp->cnic_kwq_prod++;
12352 spin_unlock_bh(&bp->spq_lock);
12354 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12355 bnx2x_cnic_sp_post(bp, 0);
12360 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12362 struct cnic_ops *c_ops;
12365 mutex_lock(&bp->cnic_mutex);
12366 c_ops = rcu_dereference_protected(bp->cnic_ops,
12367 lockdep_is_held(&bp->cnic_mutex));
12369 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12370 mutex_unlock(&bp->cnic_mutex);
12375 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12377 struct cnic_ops *c_ops;
12381 c_ops = rcu_dereference(bp->cnic_ops);
12383 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12390 * for commands that have no data
12392 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
12394 struct cnic_ctl_info ctl = {0};
12398 return bnx2x_cnic_ctl_send(bp, &ctl);
12401 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
12403 struct cnic_ctl_info ctl = {0};
12405 /* first we tell CNIC and only then we count this as a completion */
12406 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
12407 ctl.data.comp.cid = cid;
12408 ctl.data.comp.error = err;
12410 bnx2x_cnic_ctl_send_bh(bp, &ctl);
12411 bnx2x_cnic_sp_post(bp, 0);
12415 /* Called with netif_addr_lock_bh() taken.
12416 * Sets an rx_mode config for an iSCSI ETH client.
12418 * Completion should be checked outside.
12420 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
12422 unsigned long accept_flags = 0, ramrod_flags = 0;
12423 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12424 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
12427 /* Start accepting on iSCSI L2 ring. Accept all multicasts
12428 * because it's the only way for UIO Queue to accept
12429 * multicasts (in non-promiscuous mode only one Queue per
12430 * function will receive multicast packets (leading in our
12433 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
12434 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
12435 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
12436 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
12438 /* Clear STOP_PENDING bit if START is requested */
12439 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
12441 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
12443 /* Clear START_PENDING bit if STOP is requested */
12444 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
12446 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
12447 set_bit(sched_state, &bp->sp_state);
12449 __set_bit(RAMROD_RX, &ramrod_flags);
12450 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
12456 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
12458 struct bnx2x *bp = netdev_priv(dev);
12461 switch (ctl->cmd) {
12462 case DRV_CTL_CTXTBL_WR_CMD: {
12463 u32 index = ctl->data.io.offset;
12464 dma_addr_t addr = ctl->data.io.dma_addr;
12466 bnx2x_ilt_wr(bp, index, addr);
12470 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
12471 int count = ctl->data.credit.credit_count;
12473 bnx2x_cnic_sp_post(bp, count);
12477 /* rtnl_lock is held. */
12478 case DRV_CTL_START_L2_CMD: {
12479 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12480 unsigned long sp_bits = 0;
12482 /* Configure the iSCSI classification object */
12483 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
12484 cp->iscsi_l2_client_id,
12485 cp->iscsi_l2_cid, BP_FUNC(bp),
12486 bnx2x_sp(bp, mac_rdata),
12487 bnx2x_sp_mapping(bp, mac_rdata),
12488 BNX2X_FILTER_MAC_PENDING,
12489 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
12492 /* Set iSCSI MAC address */
12493 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
12500 /* Start accepting on iSCSI L2 ring */
12502 netif_addr_lock_bh(dev);
12503 bnx2x_set_iscsi_eth_rx_mode(bp, true);
12504 netif_addr_unlock_bh(dev);
12506 /* bits to wait on */
12507 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12508 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
12510 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12511 BNX2X_ERR("rx_mode completion timed out!\n");
12516 /* rtnl_lock is held. */
12517 case DRV_CTL_STOP_L2_CMD: {
12518 unsigned long sp_bits = 0;
12520 /* Stop accepting on iSCSI L2 ring */
12521 netif_addr_lock_bh(dev);
12522 bnx2x_set_iscsi_eth_rx_mode(bp, false);
12523 netif_addr_unlock_bh(dev);
12525 /* bits to wait on */
12526 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12527 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
12529 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12530 BNX2X_ERR("rx_mode completion timed out!\n");
12535 /* Unset iSCSI L2 MAC */
12536 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
12537 BNX2X_ISCSI_ETH_MAC, true);
12540 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
12541 int count = ctl->data.credit.credit_count;
12543 smp_mb__before_atomic_inc();
12544 atomic_add(count, &bp->cq_spq_left);
12545 smp_mb__after_atomic_inc();
12548 case DRV_CTL_ULP_REGISTER_CMD: {
12549 int ulp_type = ctl->data.ulp_type;
12551 if (CHIP_IS_E3(bp)) {
12552 int idx = BP_FW_MB_IDX(bp);
12555 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12556 if (ulp_type == CNIC_ULP_ISCSI)
12557 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12558 else if (ulp_type == CNIC_ULP_FCOE)
12559 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12560 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12564 case DRV_CTL_ULP_UNREGISTER_CMD: {
12565 int ulp_type = ctl->data.ulp_type;
12567 if (CHIP_IS_E3(bp)) {
12568 int idx = BP_FW_MB_IDX(bp);
12571 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12572 if (ulp_type == CNIC_ULP_ISCSI)
12573 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12574 else if (ulp_type == CNIC_ULP_FCOE)
12575 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12576 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12582 BNX2X_ERR("unknown command %x\n", ctl->cmd);
12589 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
12591 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12593 if (bp->flags & USING_MSIX_FLAG) {
12594 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
12595 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
12596 cp->irq_arr[0].vector = bp->msix_table[1].vector;
12598 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
12599 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
12601 if (!CHIP_IS_E1x(bp))
12602 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
12604 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
12606 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
12607 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
12608 cp->irq_arr[1].status_blk = bp->def_status_blk;
12609 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
12610 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
12615 void bnx2x_setup_cnic_info(struct bnx2x *bp)
12617 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12620 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12621 bnx2x_cid_ilt_lines(bp);
12622 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12623 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12624 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12626 if (NO_ISCSI_OOO(bp))
12627 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12630 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
12633 struct bnx2x *bp = netdev_priv(dev);
12634 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12637 BNX2X_ERR("NULL ops received\n");
12641 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
12645 bp->cnic_kwq_cons = bp->cnic_kwq;
12646 bp->cnic_kwq_prod = bp->cnic_kwq;
12647 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
12649 bp->cnic_spq_pending = 0;
12650 bp->cnic_kwq_pending = 0;
12652 bp->cnic_data = data;
12655 cp->drv_state |= CNIC_DRV_STATE_REGD;
12656 cp->iro_arr = bp->iro_arr;
12658 bnx2x_setup_cnic_irq_info(bp);
12660 rcu_assign_pointer(bp->cnic_ops, ops);
12665 static int bnx2x_unregister_cnic(struct net_device *dev)
12667 struct bnx2x *bp = netdev_priv(dev);
12668 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12670 mutex_lock(&bp->cnic_mutex);
12672 RCU_INIT_POINTER(bp->cnic_ops, NULL);
12673 mutex_unlock(&bp->cnic_mutex);
12675 kfree(bp->cnic_kwq);
12676 bp->cnic_kwq = NULL;
12681 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
12683 struct bnx2x *bp = netdev_priv(dev);
12684 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12686 /* If both iSCSI and FCoE are disabled - return NULL in
12687 * order to indicate CNIC that it should not try to work
12688 * with this device.
12690 if (NO_ISCSI(bp) && NO_FCOE(bp))
12693 cp->drv_owner = THIS_MODULE;
12694 cp->chip_id = CHIP_ID(bp);
12695 cp->pdev = bp->pdev;
12696 cp->io_base = bp->regview;
12697 cp->io_base2 = bp->doorbells;
12698 cp->max_kwqe_pending = 8;
12699 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
12700 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12701 bnx2x_cid_ilt_lines(bp);
12702 cp->ctx_tbl_len = CNIC_ILT_LINES;
12703 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12704 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
12705 cp->drv_ctl = bnx2x_drv_ctl;
12706 cp->drv_register_cnic = bnx2x_register_cnic;
12707 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
12708 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12709 cp->iscsi_l2_client_id =
12710 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12711 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12713 if (NO_ISCSI_OOO(bp))
12714 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12717 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
12720 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
12723 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
12725 cp->ctx_tbl_offset,
12730 EXPORT_SYMBOL(bnx2x_cnic_probe);
12732 #endif /* BCM_CNIC */