drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/bitops.h>
  36 #include <linux/irq.h>
  37 #include <linux/delay.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/time.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/mii.h>
  42 #include <linux/if_vlan.h>
  43 #include <net/ip.h>
  44 #include <net/ipv6.h>
  45 #include <net/tcp.h>
  46 #include <net/checksum.h>
  47 #include <net/ip6_checksum.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/crc32.h>
  50 #include <linux/crc32c.h>
  51 #include <linux/prefetch.h>
  52 #include <linux/zlib.h>
  53 #include <linux/io.h>
  54 #include <linux/semaphore.h>
  55 #include <linux/stringify.h>
  56 #include <linux/vmalloc.h>
  57
  58 #include "bnx2x.h"
  59 #include "bnx2x_init.h"
  60 #include "bnx2x_init_ops.h"
  61 #include "bnx2x_cmn.h"
  62 #include "bnx2x_vfpf.h"
  63 #include "bnx2x_dcb.h"
  64 #include "bnx2x_sp.h"
  65
  66 #include <linux/firmware.h>
  67 #include "bnx2x_fw_file_hdr.h"
  68 /* FW files */
  69 #define FW_FILE_VERSION                                 \
  70         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  71         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  73         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  74 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  75 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  77
  78 /* Time in jiffies before concluding the transmitter is hung */
  79 #define TX_TIMEOUT              (5*HZ)
  80
  81 static char version[] =
  82         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  83         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  84
  85 MODULE_AUTHOR("Eliezer Tamir");
  86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  87                    "BCM57710/57711/57711E/"
  88                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  89                    "57840/57840_MF Driver");
  90 MODULE_LICENSE("GPL");
  91 MODULE_VERSION(DRV_MODULE_VERSION);
  92 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  93 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  95
  96
  97 int num_queues;
  98 module_param(num_queues, int, 0);
  99 MODULE_PARM_DESC(num_queues,
 100                  " Set number of queues (default is as a number of CPUs)");
 101
 102 static int disable_tpa;
 103 module_param(disable_tpa, int, 0);
 104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 105
 106 #define INT_MODE_INTx                   1
 107 #define INT_MODE_MSI                    2
 108 int int_mode;
 109 module_param(int_mode, int, 0);
 110 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 111                                 "(1 INT#x; 2 MSI)");
 112
 113 static int dropless_fc;
 114 module_param(dropless_fc, int, 0);
 115 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 116
 117 static int mrrs = -1;
 118 module_param(mrrs, int, 0);
 119 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 120
 121 static int debug;
 122 module_param(debug, int, 0);
 123 MODULE_PARM_DESC(debug, " Default debug msglevel");
 124
 125
 126
 127 struct workqueue_struct *bnx2x_wq;
 128
 129 struct bnx2x_mac_vals {
 130         u32 xmac_addr;
 131         u32 xmac_val;
 132         u32 emac_addr;
 133         u32 emac_val;
 134         u32 umac_addr;
 135         u32 umac_val;
 136         u32 bmac_addr;
 137         u32 bmac_val[2];
 138 };
 139
 140 enum bnx2x_board_type {
 141         BCM57710 = 0,
 142         BCM57711,
 143         BCM57711E,
 144         BCM57712,
 145         BCM57712_MF,
 146         BCM57712_VF,
 147         BCM57800,
 148         BCM57800_MF,
 149         BCM57800_VF,
 150         BCM57810,
 151         BCM57810_MF,
 152         BCM57810_VF,
 153         BCM57840_4_10,
 154         BCM57840_2_20,
 155         BCM57840_MF,
 156         BCM57840_VF,
 157         BCM57811,
 158         BCM57811_MF,
 159         BCM57840_O,
 160         BCM57840_MFO,
 161         BCM57811_VF
 162 };
 163
 164 /* indexed by board_type, above */
 165 static struct {
 166         char *name;
 167 } board_info[] = {
 168         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 169         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 170         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 171         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 172         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 173         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 174         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 175         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 176         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 177         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 178         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 179         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 180         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 181         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 182         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 183         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 184         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 185         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 186         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 187         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 188         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 189 };
 190
 191 #ifndef PCI_DEVICE_ID_NX2_57710
 192 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 193 #endif
 194 #ifndef PCI_DEVICE_ID_NX2_57711
 195 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 196 #endif
 197 #ifndef PCI_DEVICE_ID_NX2_57711E
 198 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 199 #endif
 200 #ifndef PCI_DEVICE_ID_NX2_57712
 201 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 202 #endif
 203 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 204 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 205 #endif
 206 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 207 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 208 #endif
 209 #ifndef PCI_DEVICE_ID_NX2_57800
 210 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 211 #endif
 212 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 213 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 214 #endif
 215 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 216 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 217 #endif
 218 #ifndef PCI_DEVICE_ID_NX2_57810
 219 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 220 #endif
 221 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 222 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 223 #endif
 224 #ifndef PCI_DEVICE_ID_NX2_57840_O
 225 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 226 #endif
 227 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 228 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 229 #endif
 230 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 231 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 232 #endif
 233 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 234 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 235 #endif
 236 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 237 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 238 #endif
 239 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 240 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 241 #endif
 242 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 243 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 244 #endif
 245 #ifndef PCI_DEVICE_ID_NX2_57811
 246 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 247 #endif
 248 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 249 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 250 #endif
 251 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 252 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 253 #endif
 254
 255 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 275         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 276         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 277         { 0 }
 278 };
 279
 280 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 281
 282 /* Global resources for unloading a previously loaded device */
 283 #define BNX2X_PREV_WAIT_NEEDED 1
 284 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 285 static LIST_HEAD(bnx2x_prev_list);
 286 /****************************************************************************
 287 * General service functions
 288 ****************************************************************************/
 289
 290 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 291                                        u32 addr, dma_addr_t mapping)
 292 {
 293         REG_WR(bp,  addr, U64_LO(mapping));
 294         REG_WR(bp,  addr + 4, U64_HI(mapping));
 295 }
 296
 297 static void storm_memset_spq_addr(struct bnx2x *bp,
 298                                   dma_addr_t mapping, u16 abs_fid)
 299 {
 300         u32 addr = XSEM_REG_FAST_MEMORY +
 301                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 302
 303         __storm_memset_dma_mapping(bp, addr, mapping);
 304 }
 305
 306 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 307                                   u16 pf_id)
 308 {
 309         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 310                 pf_id);
 311         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 312                 pf_id);
 313         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 314                 pf_id);
 315         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 316                 pf_id);
 317 }
 318
 319 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 320                                  u8 enable)
 321 {
 322         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 323                 enable);
 324         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 325                 enable);
 326         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 327                 enable);
 328         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 329                 enable);
 330 }
 331
 332 static void storm_memset_eq_data(struct bnx2x *bp,
 333                                  struct event_ring_data *eq_data,
 334                                 u16 pfid)
 335 {
 336         size_t size = sizeof(struct event_ring_data);
 337
 338         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 339
 340         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 341 }
 342
 343 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 344                                  u16 pfid)
 345 {
 346         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 347         REG_WR16(bp, addr, eq_prod);
 348 }
 349
 350 /* used only at init
 351  * locking is done by mcp
 352  */
 353 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 354 {
 355         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 356         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 357         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 358                                PCICFG_VENDOR_ID_OFFSET);
 359 }
 360
 361 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 362 {
 363         u32 val;
 364
 365         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 366         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 367         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 368                                PCICFG_VENDOR_ID_OFFSET);
 369
 370         return val;
 371 }
 372
 373 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 374 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 375 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 376 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 377 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 378
 379 void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl)
 380 {
 381         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 382
 383         switch (dmae->opcode & DMAE_COMMAND_DST) {
 384         case DMAE_CMD_DST_PCI:
 385                 if (src_type == DMAE_CMD_SRC_PCI)
 386                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 387                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 388                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 389                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 390                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 391                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 392                            dmae->comp_val);
 393                 else
 394                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 395                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 396                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 397                            dmae->opcode, dmae->src_addr_lo >> 2,
 398                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 399                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 400                            dmae->comp_val);
 401                 break;
 402         case DMAE_CMD_DST_GRC:
 403                 if (src_type == DMAE_CMD_SRC_PCI)
 404                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 405                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 406                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 407                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 408                            dmae->len, dmae->dst_addr_lo >> 2,
 409                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 410                            dmae->comp_val);
 411                 else
 412                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 413                            "src [%08x], len [%d*4], dst [%08x]\n"
 414                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 415                            dmae->opcode, dmae->src_addr_lo >> 2,
 416                            dmae->len, dmae->dst_addr_lo >> 2,
 417                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 418                            dmae->comp_val);
 419                 break;
 420         default:
 421                 if (src_type == DMAE_CMD_SRC_PCI)
 422                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 423                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 424                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 425                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 426                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 427                            dmae->comp_val);
 428                 else
 429                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 430                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 431                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 432                            dmae->opcode, dmae->src_addr_lo >> 2,
 433                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 434                            dmae->comp_val);
 435                 break;
 436         }
 437 }
 438
 439 /* copy command into DMAE command memory and set DMAE command go */
 440 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 441 {
 442         u32 cmd_offset;
 443         int i;
 444
 445         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 446         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 447                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 448         }
 449         REG_WR(bp, dmae_reg_go_c[idx], 1);
 450 }
 451
 452 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 453 {
 454         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 455                            DMAE_CMD_C_ENABLE);
 456 }
 457
 458 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 459 {
 460         return opcode & ~DMAE_CMD_SRC_RESET;
 461 }
 462
 463 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 464                              bool with_comp, u8 comp_type)
 465 {
 466         u32 opcode = 0;
 467
 468         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 469                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 470
 471         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 472
 473         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 474         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 475                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 476         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 477
 478 #ifdef __BIG_ENDIAN
 479         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 480 #else
 481         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 482 #endif
 483         if (with_comp)
 484                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 485         return opcode;
 486 }
 487
 488 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 489                                       struct dmae_command *dmae,
 490                                       u8 src_type, u8 dst_type)
 491 {
 492         memset(dmae, 0, sizeof(struct dmae_command));
 493
 494         /* set the opcode */
 495         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 496                                          true, DMAE_COMP_PCI);
 497
 498         /* fill in the completion parameters */
 499         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 500         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 501         dmae->comp_val = DMAE_COMP_VAL;
 502 }
 503
 504 /* issue a dmae command over the init-channel and wait for completion */
 505 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
 506 {
 507         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
 508         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 509         int rc = 0;
 510
 511         /*
 512          * Lock the dmae channel. Disable BHs to prevent a dead-lock
 513          * as long as this code is called both from syscall context and
 514          * from ndo_set_rx_mode() flow that may be called from BH.
 515          */
 516         spin_lock_bh(&bp->dmae_lock);
 517
 518         /* reset completion */
 519         *wb_comp = 0;
 520
 521         /* post the command on the channel used for initializations */
 522         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 523
 524         /* wait for completion */
 525         udelay(5);
 526         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 527
 528                 if (!cnt ||
 529                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 530                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 531                         BNX2X_ERR("DMAE timeout!\n");
 532                         rc = DMAE_TIMEOUT;
 533                         goto unlock;
 534                 }
 535                 cnt--;
 536                 udelay(50);
 537         }
 538         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 539                 BNX2X_ERR("DMAE PCI error!\n");
 540                 rc = DMAE_PCI_ERROR;
 541         }
 542
 543 unlock:
 544         spin_unlock_bh(&bp->dmae_lock);
 545         return rc;
 546 }
 547
 548 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 549                       u32 len32)
 550 {
 551         struct dmae_command dmae;
 552
 553         if (!bp->dmae_ready) {
 554                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 555
 556                 if (CHIP_IS_E1(bp))
 557                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 558                 else
 559                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 560                 return;
 561         }
 562
 563         /* set opcode and fixed command fields */
 564         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 565
 566         /* fill in addresses and len */
 567         dmae.src_addr_lo = U64_LO(dma_addr);
 568         dmae.src_addr_hi = U64_HI(dma_addr);
 569         dmae.dst_addr_lo = dst_addr >> 2;
 570         dmae.dst_addr_hi = 0;
 571         dmae.len = len32;
 572
 573         /* issue the command and wait for completion */
 574         bnx2x_issue_dmae_with_comp(bp, &dmae);
 575 }
 576
 577 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 578 {
 579         struct dmae_command dmae;
 580
 581         if (!bp->dmae_ready) {
 582                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 583                 int i;
 584
 585                 if (CHIP_IS_E1(bp))
 586                         for (i = 0; i < len32; i++)
 587                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 588                 else
 589                         for (i = 0; i < len32; i++)
 590                                 data[i] = REG_RD(bp, src_addr + i*4);
 591
 592                 return;
 593         }
 594
 595         /* set opcode and fixed command fields */
 596         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 597
 598         /* fill in addresses and len */
 599         dmae.src_addr_lo = src_addr >> 2;
 600         dmae.src_addr_hi = 0;
 601         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 602         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 603         dmae.len = len32;
 604
 605         /* issue the command and wait for completion */
 606         bnx2x_issue_dmae_with_comp(bp, &dmae);
 607 }
 608
 609 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 610                                       u32 addr, u32 len)
 611 {
 612         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 613         int offset = 0;
 614
 615         while (len > dmae_wr_max) {
 616                 bnx2x_write_dmae(bp, phys_addr + offset,
 617                                  addr + offset, dmae_wr_max);
 618                 offset += dmae_wr_max * 4;
 619                 len -= dmae_wr_max;
 620         }
 621
 622         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 623 }
 624
 625 static int bnx2x_mc_assert(struct bnx2x *bp)
 626 {
 627         char last_idx;
 628         int i, rc = 0;
 629         u32 row0, row1, row2, row3;
 630
 631         /* XSTORM */
 632         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 633                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 634         if (last_idx)
 635                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 636
 637         /* print the asserts */
 638         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 639
 640                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 641                               XSTORM_ASSERT_LIST_OFFSET(i));
 642                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 643                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 644                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 645                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 646                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 647                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 648
 649                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 650                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 651                                   i, row3, row2, row1, row0);
 652                         rc++;
 653                 } else {
 654                         break;
 655                 }
 656         }
 657
 658         /* TSTORM */
 659         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 660                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 661         if (last_idx)
 662                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 663
 664         /* print the asserts */
 665         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 666
 667                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 668                               TSTORM_ASSERT_LIST_OFFSET(i));
 669                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 670                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 671                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 672                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 673                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 674                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 675
 676                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 677                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 678                                   i, row3, row2, row1, row0);
 679                         rc++;
 680                 } else {
 681                         break;
 682                 }
 683         }
 684
 685         /* CSTORM */
 686         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 687                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 688         if (last_idx)
 689                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 690
 691         /* print the asserts */
 692         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 693
 694                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 695                               CSTORM_ASSERT_LIST_OFFSET(i));
 696                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 697                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 698                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 699                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 700                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 701                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 702
 703                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 704                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 705                                   i, row3, row2, row1, row0);
 706                         rc++;
 707                 } else {
 708                         break;
 709                 }
 710         }
 711
 712         /* USTORM */
 713         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 714                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 715         if (last_idx)
 716                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 717
 718         /* print the asserts */
 719         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 720
 721                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 722                               USTORM_ASSERT_LIST_OFFSET(i));
 723                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 724                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 725                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 726                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 727                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 728                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 729
 730                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 731                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 732                                   i, row3, row2, row1, row0);
 733                         rc++;
 734                 } else {
 735                         break;
 736                 }
 737         }
 738
 739         return rc;
 740 }
 741
 742 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 743 {
 744         u32 addr, val;
 745         u32 mark, offset;
 746         __be32 data[9];
 747         int word;
 748         u32 trace_shmem_base;
 749         if (BP_NOMCP(bp)) {
 750                 BNX2X_ERR("NO MCP - can not dump\n");
 751                 return;
 752         }
 753         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 754                 (bp->common.bc_ver & 0xff0000) >> 16,
 755                 (bp->common.bc_ver & 0xff00) >> 8,
 756                 (bp->common.bc_ver & 0xff));
 757
 758         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 759         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 760                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 761
 762         if (BP_PATH(bp) == 0)
 763                 trace_shmem_base = bp->common.shmem_base;
 764         else
 765                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 766         addr = trace_shmem_base - 0x800;
 767
 768         /* validate TRCB signature */
 769         mark = REG_RD(bp, addr);
 770         if (mark != MFW_TRACE_SIGNATURE) {
 771                 BNX2X_ERR("Trace buffer signature is missing.");
 772                 return ;
 773         }
 774
 775         /* read cyclic buffer pointer */
 776         addr += 4;
 777         mark = REG_RD(bp, addr);
 778         mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
 779                         + ((mark + 0x3) & ~0x3) - 0x08000000;
 780         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 781
 782         printk("%s", lvl);
 783
 784         /* dump buffer after the mark */
 785         for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
 786                 for (word = 0; word < 8; word++)
 787                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 788                 data[8] = 0x0;
 789                 pr_cont("%s", (char *)data);
 790         }
 791
 792         /* dump buffer before the mark */
 793         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 794                 for (word = 0; word < 8; word++)
 795                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 796                 data[8] = 0x0;
 797                 pr_cont("%s", (char *)data);
 798         }
 799         printk("%s" "end of fw dump\n", lvl);
 800 }
 801
 802 static void bnx2x_fw_dump(struct bnx2x *bp)
 803 {
 804         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 805 }
 806
 807 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 808 {
 809         int port = BP_PORT(bp);
 810         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 811         u32 val = REG_RD(bp, addr);
 812
 813         /* in E1 we must use only PCI configuration space to disable
 814          * MSI/MSIX capablility
 815          * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 816          */
 817         if (CHIP_IS_E1(bp)) {
 818                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 819                  * Use mask register to prevent from HC sending interrupts
 820                  * after we exit the function
 821                  */
 822                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 823
 824                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 825                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 826                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 827         } else
 828                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 829                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 830                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 831                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 832
 833         DP(NETIF_MSG_IFDOWN,
 834            "write %x to HC %d (addr 0x%x)\n",
 835            val, port, addr);
 836
 837         /* flush all outstanding writes */
 838         mmiowb();
 839
 840         REG_WR(bp, addr, val);
 841         if (REG_RD(bp, addr) != val)
 842                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
 843 }
 844
 845 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 846 {
 847         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 848
 849         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 850                  IGU_PF_CONF_INT_LINE_EN |
 851                  IGU_PF_CONF_ATTN_BIT_EN);
 852
 853         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 854
 855         /* flush all outstanding writes */
 856         mmiowb();
 857
 858         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 859         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 860                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
 861 }
 862
 863 static void bnx2x_int_disable(struct bnx2x *bp)
 864 {
 865         if (bp->common.int_block == INT_BLOCK_HC)
 866                 bnx2x_hc_int_disable(bp);
 867         else
 868                 bnx2x_igu_int_disable(bp);
 869 }
 870
 871 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 872 {
 873         int i;
 874         u16 j;
 875         struct hc_sp_status_block_data sp_sb_data;
 876         int func = BP_FUNC(bp);
 877 #ifdef BNX2X_STOP_ON_ERROR
 878         u16 start = 0, end = 0;
 879         u8 cos;
 880 #endif
 881         if (disable_int)
 882                 bnx2x_int_disable(bp);
 883
 884         bp->stats_state = STATS_STATE_DISABLED;
 885         bp->eth_stats.unrecoverable_error++;
 886         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 887
 888         BNX2X_ERR("begin crash dump -----------------\n");
 889
 890         /* Indices */
 891         /* Common */
 892         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 893                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 894                   bp->spq_prod_idx, bp->stats_counter);
 895         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 896                   bp->def_status_blk->atten_status_block.attn_bits,
 897                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 898                   bp->def_status_blk->atten_status_block.status_block_id,
 899                   bp->def_status_blk->atten_status_block.attn_bits_index);
 900         BNX2X_ERR("     def (");
 901         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 902                 pr_cont("0x%x%s",
 903                         bp->def_status_blk->sp_sb.index_values[i],
 904                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 905
 906         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 907                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 908                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 909                         i*sizeof(u32));
 910
 911         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 912                sp_sb_data.igu_sb_id,
 913                sp_sb_data.igu_seg_id,
 914                sp_sb_data.p_func.pf_id,
 915                sp_sb_data.p_func.vnic_id,
 916                sp_sb_data.p_func.vf_id,
 917                sp_sb_data.p_func.vf_valid,
 918                sp_sb_data.state);
 919
 920
 921         for_each_eth_queue(bp, i) {
 922                 struct bnx2x_fastpath *fp = &bp->fp[i];
 923                 int loop;
 924                 struct hc_status_block_data_e2 sb_data_e2;
 925                 struct hc_status_block_data_e1x sb_data_e1x;
 926                 struct hc_status_block_sm  *hc_sm_p =
 927                         CHIP_IS_E1x(bp) ?
 928                         sb_data_e1x.common.state_machine :
 929                         sb_data_e2.common.state_machine;
 930                 struct hc_index_data *hc_index_p =
 931                         CHIP_IS_E1x(bp) ?
 932                         sb_data_e1x.index_data :
 933                         sb_data_e2.index_data;
 934                 u8 data_size, cos;
 935                 u32 *sb_data_p;
 936                 struct bnx2x_fp_txdata txdata;
 937
 938                 /* Rx */
 939                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 940                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 941                           fp->rx_comp_prod,
 942                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 943                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 944                           fp->rx_sge_prod, fp->last_max_sge,
 945                           le16_to_cpu(fp->fp_hc_idx));
 946
 947                 /* Tx */
 948                 for_each_cos_in_tx_queue(fp, cos)
 949                 {
 950                         txdata = *fp->txdata_ptr[cos];
 951                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 952                                   i, txdata.tx_pkt_prod,
 953                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 954                                   txdata.tx_bd_cons,
 955                                   le16_to_cpu(*txdata.tx_cons_sb));
 956                 }
 957
 958                 loop = CHIP_IS_E1x(bp) ?
 959                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 960
 961                 /* host sb data */
 962
 963                 if (IS_FCOE_FP(fp))
 964                         continue;
 965
 966                 BNX2X_ERR("     run indexes (");
 967                 for (j = 0; j < HC_SB_MAX_SM; j++)
 968                         pr_cont("0x%x%s",
 969                                fp->sb_running_index[j],
 970                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
 971
 972                 BNX2X_ERR("     indexes (");
 973                 for (j = 0; j < loop; j++)
 974                         pr_cont("0x%x%s",
 975                                fp->sb_index_values[j],
 976                                (j == loop - 1) ? ")" : " ");
 977                 /* fw sb data */
 978                 data_size = CHIP_IS_E1x(bp) ?
 979                         sizeof(struct hc_status_block_data_e1x) :
 980                         sizeof(struct hc_status_block_data_e2);
 981                 data_size /= sizeof(u32);
 982                 sb_data_p = CHIP_IS_E1x(bp) ?
 983                         (u32 *)&sb_data_e1x :
 984                         (u32 *)&sb_data_e2;
 985                 /* copy sb data in here */
 986                 for (j = 0; j < data_size; j++)
 987                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 988                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
 989                                 j * sizeof(u32));
 990
 991                 if (!CHIP_IS_E1x(bp)) {
 992                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
 993                                 sb_data_e2.common.p_func.pf_id,
 994                                 sb_data_e2.common.p_func.vf_id,
 995                                 sb_data_e2.common.p_func.vf_valid,
 996                                 sb_data_e2.common.p_func.vnic_id,
 997                                 sb_data_e2.common.same_igu_sb_1b,
 998                                 sb_data_e2.common.state);
 999                 } else {
1000                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1001                                 sb_data_e1x.common.p_func.pf_id,
1002                                 sb_data_e1x.common.p_func.vf_id,
1003                                 sb_data_e1x.common.p_func.vf_valid,
1004                                 sb_data_e1x.common.p_func.vnic_id,
1005                                 sb_data_e1x.common.same_igu_sb_1b,
1006                                 sb_data_e1x.common.state);
1007                 }
1008
1009                 /* SB_SMs data */
1010                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1011                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1012                                 j, hc_sm_p[j].__flags,
1013                                 hc_sm_p[j].igu_sb_id,
1014                                 hc_sm_p[j].igu_seg_id,
1015                                 hc_sm_p[j].time_to_expire,
1016                                 hc_sm_p[j].timer_value);
1017                 }
1018
1019                 /* Indecies data */
1020                 for (j = 0; j < loop; j++) {
1021                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1022                                hc_index_p[j].flags,
1023                                hc_index_p[j].timeout);
1024                 }
1025         }
1026
1027 #ifdef BNX2X_STOP_ON_ERROR
1028
1029         /* event queue */
1030         for (i = 0; i < NUM_EQ_DESC; i++) {
1031                 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1032
1033                 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1034                           i, bp->eq_ring[i].message.opcode,
1035                           bp->eq_ring[i].message.error);
1036                 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1037         }
1038
1039         /* Rings */
1040         /* Rx */
1041         for_each_valid_rx_queue(bp, i) {
1042                 struct bnx2x_fastpath *fp = &bp->fp[i];
1043
1044                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1045                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1046                 for (j = start; j != end; j = RX_BD(j + 1)) {
1047                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1048                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1049
1050                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1051                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1052                 }
1053
1054                 start = RX_SGE(fp->rx_sge_prod);
1055                 end = RX_SGE(fp->last_max_sge);
1056                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1057                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1058                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1059
1060                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1061                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1062                 }
1063
1064                 start = RCQ_BD(fp->rx_comp_cons - 10);
1065                 end = RCQ_BD(fp->rx_comp_cons + 503);
1066                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1067                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1068
1069                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1070                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1071                 }
1072         }
1073
1074         /* Tx */
1075         for_each_valid_tx_queue(bp, i) {
1076                 struct bnx2x_fastpath *fp = &bp->fp[i];
1077                 for_each_cos_in_tx_queue(fp, cos) {
1078                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1079
1080                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1081                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1082                         for (j = start; j != end; j = TX_BD(j + 1)) {
1083                                 struct sw_tx_bd *sw_bd =
1084                                         &txdata->tx_buf_ring[j];
1085
1086                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1087                                           i, cos, j, sw_bd->skb,
1088                                           sw_bd->first_bd);
1089                         }
1090
1091                         start = TX_BD(txdata->tx_bd_cons - 10);
1092                         end = TX_BD(txdata->tx_bd_cons + 254);
1093                         for (j = start; j != end; j = TX_BD(j + 1)) {
1094                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1095
1096                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1097                                           i, cos, j, tx_bd[0], tx_bd[1],
1098                                           tx_bd[2], tx_bd[3]);
1099                         }
1100                 }
1101         }
1102 #endif
1103         bnx2x_fw_dump(bp);
1104         bnx2x_mc_assert(bp);
1105         BNX2X_ERR("end crash dump -----------------\n");
1106 }
1107
1108 /*
1109  * FLR Support for E2
1110  *
1111  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1112  * initialization.
1113  */
1114 #define FLR_WAIT_USEC           10000   /* 10 miliseconds */
1115 #define FLR_WAIT_INTERVAL       50      /* usec */
1116 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1117
1118 struct pbf_pN_buf_regs {
1119         int pN;
1120         u32 init_crd;
1121         u32 crd;
1122         u32 crd_freed;
1123 };
1124
1125 struct pbf_pN_cmd_regs {
1126         int pN;
1127         u32 lines_occup;
1128         u32 lines_freed;
1129 };
1130
1131 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1132                                      struct pbf_pN_buf_regs *regs,
1133                                      u32 poll_count)
1134 {
1135         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1136         u32 cur_cnt = poll_count;
1137
1138         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1139         crd = crd_start = REG_RD(bp, regs->crd);
1140         init_crd = REG_RD(bp, regs->init_crd);
1141
1142         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1143         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1144         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1145
1146         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1147                (init_crd - crd_start))) {
1148                 if (cur_cnt--) {
1149                         udelay(FLR_WAIT_INTERVAL);
1150                         crd = REG_RD(bp, regs->crd);
1151                         crd_freed = REG_RD(bp, regs->crd_freed);
1152                 } else {
1153                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1154                            regs->pN);
1155                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1156                            regs->pN, crd);
1157                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1158                            regs->pN, crd_freed);
1159                         break;
1160                 }
1161         }
1162         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1163            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1164 }
1165
1166 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1167                                      struct pbf_pN_cmd_regs *regs,
1168                                      u32 poll_count)
1169 {
1170         u32 occup, to_free, freed, freed_start;
1171         u32 cur_cnt = poll_count;
1172
1173         occup = to_free = REG_RD(bp, regs->lines_occup);
1174         freed = freed_start = REG_RD(bp, regs->lines_freed);
1175
1176         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1177         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1178
1179         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1180                 if (cur_cnt--) {
1181                         udelay(FLR_WAIT_INTERVAL);
1182                         occup = REG_RD(bp, regs->lines_occup);
1183                         freed = REG_RD(bp, regs->lines_freed);
1184                 } else {
1185                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1186                            regs->pN);
1187                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1188                            regs->pN, occup);
1189                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1190                            regs->pN, freed);
1191                         break;
1192                 }
1193         }
1194         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1195            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1196 }
1197
1198 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1199                                     u32 expected, u32 poll_count)
1200 {
1201         u32 cur_cnt = poll_count;
1202         u32 val;
1203
1204         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1205                 udelay(FLR_WAIT_INTERVAL);
1206
1207         return val;
1208 }
1209
1210 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1211                                     char *msg, u32 poll_cnt)
1212 {
1213         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1214         if (val != 0) {
1215                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1216                 return 1;
1217         }
1218         return 0;
1219 }
1220
1221 /* Common routines with VF FLR cleanup */
1222 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1223 {
1224         /* adjust polling timeout */
1225         if (CHIP_REV_IS_EMUL(bp))
1226                 return FLR_POLL_CNT * 2000;
1227
1228         if (CHIP_REV_IS_FPGA(bp))
1229                 return FLR_POLL_CNT * 120;
1230
1231         return FLR_POLL_CNT;
1232 }
1233
1234 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1235 {
1236         struct pbf_pN_cmd_regs cmd_regs[] = {
1237                 {0, (CHIP_IS_E3B0(bp)) ?
1238                         PBF_REG_TQ_OCCUPANCY_Q0 :
1239                         PBF_REG_P0_TQ_OCCUPANCY,
1240                     (CHIP_IS_E3B0(bp)) ?
1241                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1242                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1243                 {1, (CHIP_IS_E3B0(bp)) ?
1244                         PBF_REG_TQ_OCCUPANCY_Q1 :
1245                         PBF_REG_P1_TQ_OCCUPANCY,
1246                     (CHIP_IS_E3B0(bp)) ?
1247                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1248                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1249                 {4, (CHIP_IS_E3B0(bp)) ?
1250                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1251                         PBF_REG_P4_TQ_OCCUPANCY,
1252                     (CHIP_IS_E3B0(bp)) ?
1253                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1254                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1255         };
1256
1257         struct pbf_pN_buf_regs buf_regs[] = {
1258                 {0, (CHIP_IS_E3B0(bp)) ?
1259                         PBF_REG_INIT_CRD_Q0 :
1260                         PBF_REG_P0_INIT_CRD ,
1261                     (CHIP_IS_E3B0(bp)) ?
1262                         PBF_REG_CREDIT_Q0 :
1263                         PBF_REG_P0_CREDIT,
1264                     (CHIP_IS_E3B0(bp)) ?
1265                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1266                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1267                 {1, (CHIP_IS_E3B0(bp)) ?
1268                         PBF_REG_INIT_CRD_Q1 :
1269                         PBF_REG_P1_INIT_CRD,
1270                     (CHIP_IS_E3B0(bp)) ?
1271                         PBF_REG_CREDIT_Q1 :
1272                         PBF_REG_P1_CREDIT,
1273                     (CHIP_IS_E3B0(bp)) ?
1274                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1275                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1276                 {4, (CHIP_IS_E3B0(bp)) ?
1277                         PBF_REG_INIT_CRD_LB_Q :
1278                         PBF_REG_P4_INIT_CRD,
1279                     (CHIP_IS_E3B0(bp)) ?
1280                         PBF_REG_CREDIT_LB_Q :
1281                         PBF_REG_P4_CREDIT,
1282                     (CHIP_IS_E3B0(bp)) ?
1283                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1284                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1285         };
1286
1287         int i;
1288
1289         /* Verify the command queues are flushed P0, P1, P4 */
1290         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1291                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1292
1293
1294         /* Verify the transmission buffers are flushed P0, P1, P4 */
1295         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1296                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1297 }
1298
1299 #define OP_GEN_PARAM(param) \
1300         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1301
1302 #define OP_GEN_TYPE(type) \
1303         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1304
1305 #define OP_GEN_AGG_VECT(index) \
1306         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1307
1308
1309 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1310 {
1311         u32 op_gen_command = 0;
1312
1313         u32 comp_addr = BAR_CSTRORM_INTMEM +
1314                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1315         int ret = 0;
1316
1317         if (REG_RD(bp, comp_addr)) {
1318                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1319                 return 1;
1320         }
1321
1322         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1323         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1324         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1325         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1326
1327         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1328         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1329
1330         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1331                 BNX2X_ERR("FW final cleanup did not succeed\n");
1332                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1333                    (REG_RD(bp, comp_addr)));
1334                 bnx2x_panic();
1335                 return 1;
1336         }
1337         /* Zero completion for nxt FLR */
1338         REG_WR(bp, comp_addr, 0);
1339
1340         return ret;
1341 }
1342
1343 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1344 {
1345         u16 status;
1346
1347         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1348         return status & PCI_EXP_DEVSTA_TRPND;
1349 }
1350
1351 /* PF FLR specific routines
1352 */
1353 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1354 {
1355
1356         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1357         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1358                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1359                         "CFC PF usage counter timed out",
1360                         poll_cnt))
1361                 return 1;
1362
1363
1364         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1365         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1366                         DORQ_REG_PF_USAGE_CNT,
1367                         "DQ PF usage counter timed out",
1368                         poll_cnt))
1369                 return 1;
1370
1371         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1372         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1373                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1374                         "QM PF usage counter timed out",
1375                         poll_cnt))
1376                 return 1;
1377
1378         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1379         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1380                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1381                         "Timers VNIC usage counter timed out",
1382                         poll_cnt))
1383                 return 1;
1384         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1385                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1386                         "Timers NUM_SCANS usage counter timed out",
1387                         poll_cnt))
1388                 return 1;
1389
1390         /* Wait DMAE PF usage counter to zero */
1391         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1392                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1393                         "DMAE dommand register timed out",
1394                         poll_cnt))
1395                 return 1;
1396
1397         return 0;
1398 }
1399
1400 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1401 {
1402         u32 val;
1403
1404         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1405         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1406
1407         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1408         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1409
1410         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1411         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1412
1413         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1414         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1415
1416         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1417         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1418
1419         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1420         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1421
1422         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1423         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1424
1425         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1426         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1427            val);
1428 }
1429
1430 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1431 {
1432         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1433
1434         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1435
1436         /* Re-enable PF target read access */
1437         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1438
1439         /* Poll HW usage counters */
1440         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1441         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1442                 return -EBUSY;
1443
1444         /* Zero the igu 'trailing edge' and 'leading edge' */
1445
1446         /* Send the FW cleanup command */
1447         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1448                 return -EBUSY;
1449
1450         /* ATC cleanup */
1451
1452         /* Verify TX hw is flushed */
1453         bnx2x_tx_hw_flushed(bp, poll_cnt);
1454
1455         /* Wait 100ms (not adjusted according to platform) */
1456         msleep(100);
1457
1458         /* Verify no pending pci transactions */
1459         if (bnx2x_is_pcie_pending(bp->pdev))
1460                 BNX2X_ERR("PCIE Transactions still pending\n");
1461
1462         /* Debug */
1463         bnx2x_hw_enable_status(bp);
1464
1465         /*
1466          * Master enable - Due to WB DMAE writes performed before this
1467          * register is re-initialized as part of the regular function init
1468          */
1469         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1470
1471         return 0;
1472 }
1473
1474 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1475 {
1476         int port = BP_PORT(bp);
1477         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1478         u32 val = REG_RD(bp, addr);
1479         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1480         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1481         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1482
1483         if (msix) {
1484                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1485                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1486                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1487                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1488                 if (single_msix)
1489                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1490         } else if (msi) {
1491                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1492                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1493                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1494                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1495         } else {
1496                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1497                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1498                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1499                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1500
1501                 if (!CHIP_IS_E1(bp)) {
1502                         DP(NETIF_MSG_IFUP,
1503                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1504
1505                         REG_WR(bp, addr, val);
1506
1507                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1508                 }
1509         }
1510
1511         if (CHIP_IS_E1(bp))
1512                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1513
1514         DP(NETIF_MSG_IFUP,
1515            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1516            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1517
1518         REG_WR(bp, addr, val);
1519         /*
1520          * Ensure that HC_CONFIG is written before leading/trailing edge config
1521          */
1522         mmiowb();
1523         barrier();
1524
1525         if (!CHIP_IS_E1(bp)) {
1526                 /* init leading/trailing edge */
1527                 if (IS_MF(bp)) {
1528                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1529                         if (bp->port.pmf)
1530                                 /* enable nig and gpio3 attention */
1531                                 val |= 0x1100;
1532                 } else
1533                         val = 0xffff;
1534
1535                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1536                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1537         }
1538
1539         /* Make sure that interrupts are indeed enabled from here on */
1540         mmiowb();
1541 }
1542
1543 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1544 {
1545         u32 val;
1546         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1547         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1548         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1549
1550         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1551
1552         if (msix) {
1553                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1554                          IGU_PF_CONF_SINGLE_ISR_EN);
1555                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1556                         IGU_PF_CONF_ATTN_BIT_EN);
1557
1558                 if (single_msix)
1559                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1560         } else if (msi) {
1561                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1562                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1563                         IGU_PF_CONF_ATTN_BIT_EN |
1564                         IGU_PF_CONF_SINGLE_ISR_EN);
1565         } else {
1566                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1567                 val |= (IGU_PF_CONF_INT_LINE_EN |
1568                         IGU_PF_CONF_ATTN_BIT_EN |
1569                         IGU_PF_CONF_SINGLE_ISR_EN);
1570         }
1571
1572         /* Clean previous status - need to configure igu prior to ack*/
1573         if ((!msix) || single_msix) {
1574                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1575                 bnx2x_ack_int(bp);
1576         }
1577
1578         val |= IGU_PF_CONF_FUNC_EN;
1579
1580         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1581            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1582
1583         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1584
1585         if (val & IGU_PF_CONF_INT_LINE_EN)
1586                 pci_intx(bp->pdev, true);
1587
1588         barrier();
1589
1590         /* init leading/trailing edge */
1591         if (IS_MF(bp)) {
1592                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1593                 if (bp->port.pmf)
1594                         /* enable nig and gpio3 attention */
1595                         val |= 0x1100;
1596         } else
1597                 val = 0xffff;
1598
1599         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1600         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1601
1602         /* Make sure that interrupts are indeed enabled from here on */
1603         mmiowb();
1604 }
1605
1606 void bnx2x_int_enable(struct bnx2x *bp)
1607 {
1608         if (bp->common.int_block == INT_BLOCK_HC)
1609                 bnx2x_hc_int_enable(bp);
1610         else
1611                 bnx2x_igu_int_enable(bp);
1612 }
1613
1614 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1615 {
1616         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1617         int i, offset;
1618
1619         if (disable_hw)
1620                 /* prevent the HW from sending interrupts */
1621                 bnx2x_int_disable(bp);
1622
1623         /* make sure all ISRs are done */
1624         if (msix) {
1625                 synchronize_irq(bp->msix_table[0].vector);
1626                 offset = 1;
1627                 if (CNIC_SUPPORT(bp))
1628                         offset++;
1629                 for_each_eth_queue(bp, i)
1630                         synchronize_irq(bp->msix_table[offset++].vector);
1631         } else
1632                 synchronize_irq(bp->pdev->irq);
1633
1634         /* make sure sp_task is not running */
1635         cancel_delayed_work(&bp->sp_task);
1636         cancel_delayed_work(&bp->period_task);
1637         flush_workqueue(bnx2x_wq);
1638 }
1639
1640 /* fast path */
1641
1642 /*
1643  * General service functions
1644  */
1645
1646 /* Return true if succeeded to acquire the lock */
1647 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1648 {
1649         u32 lock_status;
1650         u32 resource_bit = (1 << resource);
1651         int func = BP_FUNC(bp);
1652         u32 hw_lock_control_reg;
1653
1654         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1655            "Trying to take a lock on resource %d\n", resource);
1656
1657         /* Validating that the resource is within range */
1658         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1659                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1660                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1661                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1662                 return false;
1663         }
1664
1665         if (func <= 5)
1666                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1667         else
1668                 hw_lock_control_reg =
1669                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1670
1671         /* Try to acquire the lock */
1672         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1673         lock_status = REG_RD(bp, hw_lock_control_reg);
1674         if (lock_status & resource_bit)
1675                 return true;
1676
1677         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1678            "Failed to get a lock on resource %d\n", resource);
1679         return false;
1680 }
1681
1682 /**
1683  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1684  *
1685  * @bp: driver handle
1686  *
1687  * Returns the recovery leader resource id according to the engine this function
1688  * belongs to. Currently only only 2 engines is supported.
1689  */
1690 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1691 {
1692         if (BP_PATH(bp))
1693                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1694         else
1695                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1696 }
1697
1698 /**
1699  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1700  *
1701  * @bp: driver handle
1702  *
1703  * Tries to acquire a leader lock for current engine.
1704  */
1705 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1706 {
1707         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1708 }
1709
1710 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1711
1712 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1713 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1714 {
1715         /* Set the interrupt occurred bit for the sp-task to recognize it
1716          * must ack the interrupt and transition according to the IGU
1717          * state machine.
1718          */
1719         atomic_set(&bp->interrupt_occurred, 1);
1720
1721         /* The sp_task must execute only after this bit
1722          * is set, otherwise we will get out of sync and miss all
1723          * further interrupts. Hence, the barrier.
1724          */
1725         smp_wmb();
1726
1727         /* schedule sp_task to workqueue */
1728         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1729 }
1730
1731 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1732 {
1733         struct bnx2x *bp = fp->bp;
1734         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1735         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1736         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1737         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1738
1739         DP(BNX2X_MSG_SP,
1740            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1741            fp->index, cid, command, bp->state,
1742            rr_cqe->ramrod_cqe.ramrod_type);
1743
1744         /* If cid is within VF range, replace the slowpath object with the
1745          * one corresponding to this VF
1746          */
1747         if (cid >= BNX2X_FIRST_VF_CID  &&
1748             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1749                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1750
1751         switch (command) {
1752         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1753                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1754                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1755                 break;
1756
1757         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1758                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1759                 drv_cmd = BNX2X_Q_CMD_SETUP;
1760                 break;
1761
1762         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1763                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1764                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1765                 break;
1766
1767         case (RAMROD_CMD_ID_ETH_HALT):
1768                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1769                 drv_cmd = BNX2X_Q_CMD_HALT;
1770                 break;
1771
1772         case (RAMROD_CMD_ID_ETH_TERMINATE):
1773                 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1774                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1775                 break;
1776
1777         case (RAMROD_CMD_ID_ETH_EMPTY):
1778                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1779                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1780                 break;
1781
1782         default:
1783                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1784                           command, fp->index);
1785                 return;
1786         }
1787
1788         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1789             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1790                 /* q_obj->complete_cmd() failure means that this was
1791                  * an unexpected completion.
1792                  *
1793                  * In this case we don't want to increase the bp->spq_left
1794                  * because apparently we haven't sent this command the first
1795                  * place.
1796                  */
1797 #ifdef BNX2X_STOP_ON_ERROR
1798                 bnx2x_panic();
1799 #else
1800                 return;
1801 #endif
1802         /* SRIOV: reschedule any 'in_progress' operations */
1803         bnx2x_iov_sp_event(bp, cid, true);
1804
1805         smp_mb__before_atomic_inc();
1806         atomic_inc(&bp->cq_spq_left);
1807         /* push the change in bp->spq_left and towards the memory */
1808         smp_mb__after_atomic_inc();
1809
1810         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1811
1812         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1813             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1814                 /* if Q update ramrod is completed for last Q in AFEX vif set
1815                  * flow, then ACK MCP at the end
1816                  *
1817                  * mark pending ACK to MCP bit.
1818                  * prevent case that both bits are cleared.
1819                  * At the end of load/unload driver checks that
1820                  * sp_state is cleared, and this order prevents
1821                  * races
1822                  */
1823                 smp_mb__before_clear_bit();
1824                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1825                 wmb();
1826                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1827                 smp_mb__after_clear_bit();
1828
1829                 /* schedule the sp task as mcp ack is required */
1830                 bnx2x_schedule_sp_task(bp);
1831         }
1832
1833         return;
1834 }
1835
1836 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1837 {
1838         struct bnx2x *bp = netdev_priv(dev_instance);
1839         u16 status = bnx2x_ack_int(bp);
1840         u16 mask;
1841         int i;
1842         u8 cos;
1843
1844         /* Return here if interrupt is shared and it's not for us */
1845         if (unlikely(status == 0)) {
1846                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1847                 return IRQ_NONE;
1848         }
1849         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1850
1851 #ifdef BNX2X_STOP_ON_ERROR
1852         if (unlikely(bp->panic))
1853                 return IRQ_HANDLED;
1854 #endif
1855
1856         for_each_eth_queue(bp, i) {
1857                 struct bnx2x_fastpath *fp = &bp->fp[i];
1858
1859                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1860                 if (status & mask) {
1861                         /* Handle Rx or Tx according to SB id */
1862                         prefetch(fp->rx_cons_sb);
1863                         for_each_cos_in_tx_queue(fp, cos)
1864                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1865                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1866                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1867                         status &= ~mask;
1868                 }
1869         }
1870
1871         if (CNIC_SUPPORT(bp)) {
1872                 mask = 0x2;
1873                 if (status & (mask | 0x1)) {
1874                         struct cnic_ops *c_ops = NULL;
1875
1876                         rcu_read_lock();
1877                         c_ops = rcu_dereference(bp->cnic_ops);
1878                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1879                                       CNIC_DRV_STATE_HANDLES_IRQ))
1880                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1881                         rcu_read_unlock();
1882
1883                         status &= ~mask;
1884                 }
1885         }
1886
1887         if (unlikely(status & 0x1)) {
1888
1889                 /* schedule sp task to perform default status block work, ack
1890                  * attentions and enable interrupts.
1891                  */
1892                 bnx2x_schedule_sp_task(bp);
1893
1894                 status &= ~0x1;
1895                 if (!status)
1896                         return IRQ_HANDLED;
1897         }
1898
1899         if (unlikely(status))
1900                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1901                    status);
1902
1903         return IRQ_HANDLED;
1904 }
1905
1906 /* Link */
1907
1908 /*
1909  * General service functions
1910  */
1911
1912 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1913 {
1914         u32 lock_status;
1915         u32 resource_bit = (1 << resource);
1916         int func = BP_FUNC(bp);
1917         u32 hw_lock_control_reg;
1918         int cnt;
1919
1920         /* Validating that the resource is within range */
1921         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1922                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1923                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1924                 return -EINVAL;
1925         }
1926
1927         if (func <= 5) {
1928                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1929         } else {
1930                 hw_lock_control_reg =
1931                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1932         }
1933
1934         /* Validating that the resource is not already taken */
1935         lock_status = REG_RD(bp, hw_lock_control_reg);
1936         if (lock_status & resource_bit) {
1937                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1938                    lock_status, resource_bit);
1939                 return -EEXIST;
1940         }
1941
1942         /* Try for 5 second every 5ms */
1943         for (cnt = 0; cnt < 1000; cnt++) {
1944                 /* Try to acquire the lock */
1945                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1946                 lock_status = REG_RD(bp, hw_lock_control_reg);
1947                 if (lock_status & resource_bit)
1948                         return 0;
1949
1950                 msleep(5);
1951         }
1952         BNX2X_ERR("Timeout\n");
1953         return -EAGAIN;
1954 }
1955
1956 int bnx2x_release_leader_lock(struct bnx2x *bp)
1957 {
1958         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1959 }
1960
1961 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1962 {
1963         u32 lock_status;
1964         u32 resource_bit = (1 << resource);
1965         int func = BP_FUNC(bp);
1966         u32 hw_lock_control_reg;
1967
1968         /* Validating that the resource is within range */
1969         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1970                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1971                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1972                 return -EINVAL;
1973         }
1974
1975         if (func <= 5) {
1976                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1977         } else {
1978                 hw_lock_control_reg =
1979                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1980         }
1981
1982         /* Validating that the resource is currently taken */
1983         lock_status = REG_RD(bp, hw_lock_control_reg);
1984         if (!(lock_status & resource_bit)) {
1985                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1986                    lock_status, resource_bit);
1987                 return -EFAULT;
1988         }
1989
1990         REG_WR(bp, hw_lock_control_reg, resource_bit);
1991         return 0;
1992 }
1993
1994
1995 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1996 {
1997         /* The GPIO should be swapped if swap register is set and active */
1998         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1999                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2000         int gpio_shift = gpio_num +
2001                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2002         u32 gpio_mask = (1 << gpio_shift);
2003         u32 gpio_reg;
2004         int value;
2005
2006         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2007                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2008                 return -EINVAL;
2009         }
2010
2011         /* read GPIO value */
2012         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2013
2014         /* get the requested pin value */
2015         if ((gpio_reg & gpio_mask) == gpio_mask)
2016                 value = 1;
2017         else
2018                 value = 0;
2019
2020         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
2021
2022         return value;
2023 }
2024
2025 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2026 {
2027         /* The GPIO should be swapped if swap register is set and active */
2028         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2029                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2030         int gpio_shift = gpio_num +
2031                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2032         u32 gpio_mask = (1 << gpio_shift);
2033         u32 gpio_reg;
2034
2035         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2036                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2037                 return -EINVAL;
2038         }
2039
2040         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2041         /* read GPIO and mask except the float bits */
2042         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2043
2044         switch (mode) {
2045         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2046                 DP(NETIF_MSG_LINK,
2047                    "Set GPIO %d (shift %d) -> output low\n",
2048                    gpio_num, gpio_shift);
2049                 /* clear FLOAT and set CLR */
2050                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2051                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2052                 break;
2053
2054         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2055                 DP(NETIF_MSG_LINK,
2056                    "Set GPIO %d (shift %d) -> output high\n",
2057                    gpio_num, gpio_shift);
2058                 /* clear FLOAT and set SET */
2059                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2060                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2061                 break;
2062
2063         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2064                 DP(NETIF_MSG_LINK,
2065                    "Set GPIO %d (shift %d) -> input\n",
2066                    gpio_num, gpio_shift);
2067                 /* set FLOAT */
2068                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2069                 break;
2070
2071         default:
2072                 break;
2073         }
2074
2075         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2076         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2077
2078         return 0;
2079 }
2080
2081 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2082 {
2083         u32 gpio_reg = 0;
2084         int rc = 0;
2085
2086         /* Any port swapping should be handled by caller. */
2087
2088         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2089         /* read GPIO and mask except the float bits */
2090         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2091         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2092         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2093         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2094
2095         switch (mode) {
2096         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2097                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2098                 /* set CLR */
2099                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2100                 break;
2101
2102         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2103                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2104                 /* set SET */
2105                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2106                 break;
2107
2108         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2109                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2110                 /* set FLOAT */
2111                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2112                 break;
2113
2114         default:
2115                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2116                 rc = -EINVAL;
2117                 break;
2118         }
2119
2120         if (rc == 0)
2121                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2122
2123         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2124
2125         return rc;
2126 }
2127
2128 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2129 {
2130         /* The GPIO should be swapped if swap register is set and active */
2131         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2132                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2133         int gpio_shift = gpio_num +
2134                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2135         u32 gpio_mask = (1 << gpio_shift);
2136         u32 gpio_reg;
2137
2138         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2139                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2140                 return -EINVAL;
2141         }
2142
2143         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2144         /* read GPIO int */
2145         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2146
2147         switch (mode) {
2148         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2149                 DP(NETIF_MSG_LINK,
2150                    "Clear GPIO INT %d (shift %d) -> output low\n",
2151                    gpio_num, gpio_shift);
2152                 /* clear SET and set CLR */
2153                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2154                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2155                 break;
2156
2157         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2158                 DP(NETIF_MSG_LINK,
2159                    "Set GPIO INT %d (shift %d) -> output high\n",
2160                    gpio_num, gpio_shift);
2161                 /* clear CLR and set SET */
2162                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2163                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2164                 break;
2165
2166         default:
2167                 break;
2168         }
2169
2170         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2171         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2172
2173         return 0;
2174 }
2175
2176 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2177 {
2178         u32 spio_reg;
2179
2180         /* Only 2 SPIOs are configurable */
2181         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2182                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2183                 return -EINVAL;
2184         }
2185
2186         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2187         /* read SPIO and mask except the float bits */
2188         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2189
2190         switch (mode) {
2191         case MISC_SPIO_OUTPUT_LOW:
2192                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2193                 /* clear FLOAT and set CLR */
2194                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2195                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2196                 break;
2197
2198         case MISC_SPIO_OUTPUT_HIGH:
2199                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2200                 /* clear FLOAT and set SET */
2201                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2202                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2203                 break;
2204
2205         case MISC_SPIO_INPUT_HI_Z:
2206                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2207                 /* set FLOAT */
2208                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2209                 break;
2210
2211         default:
2212                 break;
2213         }
2214
2215         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2216         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2217
2218         return 0;
2219 }
2220
2221 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2222 {
2223         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2224         switch (bp->link_vars.ieee_fc &
2225                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2226         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2227                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2228                                                    ADVERTISED_Pause);
2229                 break;
2230
2231         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2232                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2233                                                   ADVERTISED_Pause);
2234                 break;
2235
2236         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2237                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2238                 break;
2239
2240         default:
2241                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2242                                                    ADVERTISED_Pause);
2243                 break;
2244         }
2245 }
2246
2247 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2248 {
2249         /* Initialize link parameters structure variables
2250          * It is recommended to turn off RX FC for jumbo frames
2251          *  for better performance
2252          */
2253         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2254                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2255         else
2256                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2257 }
2258
2259 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2260 {
2261         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2262         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2263
2264         if (!BP_NOMCP(bp)) {
2265                 bnx2x_set_requested_fc(bp);
2266                 bnx2x_acquire_phy_lock(bp);
2267
2268                 if (load_mode == LOAD_DIAG) {
2269                         struct link_params *lp = &bp->link_params;
2270                         lp->loopback_mode = LOOPBACK_XGXS;
2271                         /* do PHY loopback at 10G speed, if possible */
2272                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2273                                 if (lp->speed_cap_mask[cfx_idx] &
2274                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2275                                         lp->req_line_speed[cfx_idx] =
2276                                         SPEED_10000;
2277                                 else
2278                                         lp->req_line_speed[cfx_idx] =
2279                                         SPEED_1000;
2280                         }
2281                 }
2282
2283                 if (load_mode == LOAD_LOOPBACK_EXT) {
2284                         struct link_params *lp = &bp->link_params;
2285                         lp->loopback_mode = LOOPBACK_EXT;
2286                 }
2287
2288                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2289
2290                 bnx2x_release_phy_lock(bp);
2291
2292                 bnx2x_calc_fc_adv(bp);
2293
2294                 if (bp->link_vars.link_up) {
2295                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2296                         bnx2x_link_report(bp);
2297                 }
2298                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2299                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2300                 return rc;
2301         }
2302         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2303         return -EINVAL;
2304 }
2305
2306 void bnx2x_link_set(struct bnx2x *bp)
2307 {
2308         if (!BP_NOMCP(bp)) {
2309                 bnx2x_acquire_phy_lock(bp);
2310                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2311                 bnx2x_release_phy_lock(bp);
2312
2313                 bnx2x_calc_fc_adv(bp);
2314         } else
2315                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2316 }
2317
2318 static void bnx2x__link_reset(struct bnx2x *bp)
2319 {
2320         if (!BP_NOMCP(bp)) {
2321                 bnx2x_acquire_phy_lock(bp);
2322                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2323                 bnx2x_release_phy_lock(bp);
2324         } else
2325                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2326 }
2327
2328 void bnx2x_force_link_reset(struct bnx2x *bp)
2329 {
2330         bnx2x_acquire_phy_lock(bp);
2331         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2332         bnx2x_release_phy_lock(bp);
2333 }
2334
2335 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2336 {
2337         u8 rc = 0;
2338
2339         if (!BP_NOMCP(bp)) {
2340                 bnx2x_acquire_phy_lock(bp);
2341                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2342                                      is_serdes);
2343                 bnx2x_release_phy_lock(bp);
2344         } else
2345                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2346
2347         return rc;
2348 }
2349
2350
2351 /* Calculates the sum of vn_min_rates.
2352    It's needed for further normalizing of the min_rates.
2353    Returns:
2354      sum of vn_min_rates.
2355        or
2356      0 - if all the min_rates are 0.
2357      In the later case fainess algorithm should be deactivated.
2358      If not all min_rates are zero then those that are zeroes will be set to 1.
2359  */
2360 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2361                                       struct cmng_init_input *input)
2362 {
2363         int all_zero = 1;
2364         int vn;
2365
2366         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2367                 u32 vn_cfg = bp->mf_config[vn];
2368                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2369                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2370
2371                 /* Skip hidden vns */
2372                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2373                         vn_min_rate = 0;
2374                 /* If min rate is zero - set it to 1 */
2375                 else if (!vn_min_rate)
2376                         vn_min_rate = DEF_MIN_RATE;
2377                 else
2378                         all_zero = 0;
2379
2380                 input->vnic_min_rate[vn] = vn_min_rate;
2381         }
2382
2383         /* if ETS or all min rates are zeros - disable fairness */
2384         if (BNX2X_IS_ETS_ENABLED(bp)) {
2385                 input->flags.cmng_enables &=
2386                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2387                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2388         } else if (all_zero) {
2389                 input->flags.cmng_enables &=
2390                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2391                 DP(NETIF_MSG_IFUP,
2392                    "All MIN values are zeroes fairness will be disabled\n");
2393         } else
2394                 input->flags.cmng_enables |=
2395                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2396 }
2397
2398 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2399                                     struct cmng_init_input *input)
2400 {
2401         u16 vn_max_rate;
2402         u32 vn_cfg = bp->mf_config[vn];
2403
2404         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2405                 vn_max_rate = 0;
2406         else {
2407                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2408
2409                 if (IS_MF_SI(bp)) {
2410                         /* maxCfg in percents of linkspeed */
2411                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2412                 } else /* SD modes */
2413                         /* maxCfg is absolute in 100Mb units */
2414                         vn_max_rate = maxCfg * 100;
2415         }
2416
2417         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2418
2419         input->vnic_max_rate[vn] = vn_max_rate;
2420 }
2421
2422
2423 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2424 {
2425         if (CHIP_REV_IS_SLOW(bp))
2426                 return CMNG_FNS_NONE;
2427         if (IS_MF(bp))
2428                 return CMNG_FNS_MINMAX;
2429
2430         return CMNG_FNS_NONE;
2431 }
2432
2433 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2434 {
2435         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2436
2437         if (BP_NOMCP(bp))
2438                 return; /* what should be the default bvalue in this case */
2439
2440         /* For 2 port configuration the absolute function number formula
2441          * is:
2442          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2443          *
2444          *      and there are 4 functions per port
2445          *
2446          * For 4 port configuration it is
2447          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2448          *
2449          *      and there are 2 functions per port
2450          */
2451         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2452                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2453
2454                 if (func >= E1H_FUNC_MAX)
2455                         break;
2456
2457                 bp->mf_config[vn] =
2458                         MF_CFG_RD(bp, func_mf_config[func].config);
2459         }
2460         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2461                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2462                 bp->flags |= MF_FUNC_DIS;
2463         } else {
2464                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2465                 bp->flags &= ~MF_FUNC_DIS;
2466         }
2467 }
2468
2469 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2470 {
2471         struct cmng_init_input input;
2472         memset(&input, 0, sizeof(struct cmng_init_input));
2473
2474         input.port_rate = bp->link_vars.line_speed;
2475
2476         if (cmng_type == CMNG_FNS_MINMAX) {
2477                 int vn;
2478
2479                 /* read mf conf from shmem */
2480                 if (read_cfg)
2481                         bnx2x_read_mf_cfg(bp);
2482
2483                 /* vn_weight_sum and enable fairness if not 0 */
2484                 bnx2x_calc_vn_min(bp, &input);
2485
2486                 /* calculate and set min-max rate for each vn */
2487                 if (bp->port.pmf)
2488                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2489                                 bnx2x_calc_vn_max(bp, vn, &input);
2490
2491                 /* always enable rate shaping and fairness */
2492                 input.flags.cmng_enables |=
2493                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2494
2495                 bnx2x_init_cmng(&input, &bp->cmng);
2496                 return;
2497         }
2498
2499         /* rate shaping and fairness are disabled */
2500         DP(NETIF_MSG_IFUP,
2501            "rate shaping and fairness are disabled\n");
2502 }
2503
2504 static void storm_memset_cmng(struct bnx2x *bp,
2505                               struct cmng_init *cmng,
2506                               u8 port)
2507 {
2508         int vn;
2509         size_t size = sizeof(struct cmng_struct_per_port);
2510
2511         u32 addr = BAR_XSTRORM_INTMEM +
2512                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2513
2514         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2515
2516         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2517                 int func = func_by_vn(bp, vn);
2518
2519                 addr = BAR_XSTRORM_INTMEM +
2520                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2521                 size = sizeof(struct rate_shaping_vars_per_vn);
2522                 __storm_memset_struct(bp, addr, size,
2523                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2524
2525                 addr = BAR_XSTRORM_INTMEM +
2526                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2527                 size = sizeof(struct fairness_vars_per_vn);
2528                 __storm_memset_struct(bp, addr, size,
2529                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2530         }
2531 }
2532
2533 /* This function is called upon link interrupt */
2534 static void bnx2x_link_attn(struct bnx2x *bp)
2535 {
2536         /* Make sure that we are synced with the current statistics */
2537         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2538
2539         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2540
2541         if (bp->link_vars.link_up) {
2542
2543                 /* dropless flow control */
2544                 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2545                         int port = BP_PORT(bp);
2546                         u32 pause_enabled = 0;
2547
2548                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2549                                 pause_enabled = 1;
2550
2551                         REG_WR(bp, BAR_USTRORM_INTMEM +
2552                                USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2553                                pause_enabled);
2554                 }
2555
2556                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2557                         struct host_port_stats *pstats;
2558
2559                         pstats = bnx2x_sp(bp, port_stats);
2560                         /* reset old mac stats */
2561                         memset(&(pstats->mac_stx[0]), 0,
2562                                sizeof(struct mac_stx));
2563                 }
2564                 if (bp->state == BNX2X_STATE_OPEN)
2565                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2566         }
2567
2568         if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2569                 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2570
2571                 if (cmng_fns != CMNG_FNS_NONE) {
2572                         bnx2x_cmng_fns_init(bp, false, cmng_fns);
2573                         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2574                 } else
2575                         /* rate shaping and fairness are disabled */
2576                         DP(NETIF_MSG_IFUP,
2577                            "single function mode without fairness\n");
2578         }
2579
2580         __bnx2x_link_report(bp);
2581
2582         if (IS_MF(bp))
2583                 bnx2x_link_sync_notify(bp);
2584 }
2585
2586 void bnx2x__link_status_update(struct bnx2x *bp)
2587 {
2588         if (bp->state != BNX2X_STATE_OPEN)
2589                 return;
2590
2591         /* read updated dcb configuration */
2592         if (IS_PF(bp)) {
2593                 bnx2x_dcbx_pmf_update(bp);
2594                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2595                 if (bp->link_vars.link_up)
2596                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2597                 else
2598                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2599                         /* indicate link status */
2600                 bnx2x_link_report(bp);
2601
2602         } else { /* VF */
2603                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2604                                           SUPPORTED_10baseT_Full |
2605                                           SUPPORTED_100baseT_Half |
2606                                           SUPPORTED_100baseT_Full |
2607                                           SUPPORTED_1000baseT_Full |
2608                                           SUPPORTED_2500baseX_Full |
2609                                           SUPPORTED_10000baseT_Full |
2610                                           SUPPORTED_TP |
2611                                           SUPPORTED_FIBRE |
2612                                           SUPPORTED_Autoneg |
2613                                           SUPPORTED_Pause |
2614                                           SUPPORTED_Asym_Pause);
2615                 bp->port.advertising[0] = bp->port.supported[0];
2616
2617                 bp->link_params.bp = bp;
2618                 bp->link_params.port = BP_PORT(bp);
2619                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2620                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2621                 bp->link_params.req_line_speed[0] = SPEED_10000;
2622                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2623                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2624                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2625                 bp->link_vars.line_speed = SPEED_10000;
2626                 bp->link_vars.link_status =
2627                         (LINK_STATUS_LINK_UP |
2628                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2629                 bp->link_vars.link_up = 1;
2630                 bp->link_vars.duplex = DUPLEX_FULL;
2631                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2632                 __bnx2x_link_report(bp);
2633                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2634         }
2635 }
2636
2637 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2638                                   u16 vlan_val, u8 allowed_prio)
2639 {
2640         struct bnx2x_func_state_params func_params = {NULL};
2641         struct bnx2x_func_afex_update_params *f_update_params =
2642                 &func_params.params.afex_update;
2643
2644         func_params.f_obj = &bp->func_obj;
2645         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2646
2647         /* no need to wait for RAMROD completion, so don't
2648          * set RAMROD_COMP_WAIT flag
2649          */
2650
2651         f_update_params->vif_id = vifid;
2652         f_update_params->afex_default_vlan = vlan_val;
2653         f_update_params->allowed_priorities = allowed_prio;
2654
2655         /* if ramrod can not be sent, response to MCP immediately */
2656         if (bnx2x_func_state_change(bp, &func_params) < 0)
2657                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2658
2659         return 0;
2660 }
2661
2662 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2663                                           u16 vif_index, u8 func_bit_map)
2664 {
2665         struct bnx2x_func_state_params func_params = {NULL};
2666         struct bnx2x_func_afex_viflists_params *update_params =
2667                 &func_params.params.afex_viflists;
2668         int rc;
2669         u32 drv_msg_code;
2670
2671         /* validate only LIST_SET and LIST_GET are received from switch */
2672         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2673                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2674                           cmd_type);
2675
2676         func_params.f_obj = &bp->func_obj;
2677         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2678
2679         /* set parameters according to cmd_type */
2680         update_params->afex_vif_list_command = cmd_type;
2681         update_params->vif_list_index = vif_index;
2682         update_params->func_bit_map =
2683                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2684         update_params->func_to_clear = 0;
2685         drv_msg_code =
2686                 (cmd_type == VIF_LIST_RULE_GET) ?
2687                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2688                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2689
2690         /* if ramrod can not be sent, respond to MCP immediately for
2691          * SET and GET requests (other are not triggered from MCP)
2692          */
2693         rc = bnx2x_func_state_change(bp, &func_params);
2694         if (rc < 0)
2695                 bnx2x_fw_command(bp, drv_msg_code, 0);
2696
2697         return 0;
2698 }
2699
2700 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2701 {
2702         struct afex_stats afex_stats;
2703         u32 func = BP_ABS_FUNC(bp);
2704         u32 mf_config;
2705         u16 vlan_val;
2706         u32 vlan_prio;
2707         u16 vif_id;
2708         u8 allowed_prio;
2709         u8 vlan_mode;
2710         u32 addr_to_write, vifid, addrs, stats_type, i;
2711
2712         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2713                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2714                 DP(BNX2X_MSG_MCP,
2715                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2716                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2717         }
2718
2719         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2720                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2721                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2722                 DP(BNX2X_MSG_MCP,
2723                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2724                    vifid, addrs);
2725                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2726                                                addrs);
2727         }
2728
2729         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2730                 addr_to_write = SHMEM2_RD(bp,
2731                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2732                 stats_type = SHMEM2_RD(bp,
2733                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2734
2735                 DP(BNX2X_MSG_MCP,
2736                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2737                    addr_to_write);
2738
2739                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2740
2741                 /* write response to scratchpad, for MCP */
2742                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2743                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2744                                *(((u32 *)(&afex_stats))+i));
2745
2746                 /* send ack message to MCP */
2747                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2748         }
2749
2750         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2751                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2752                 bp->mf_config[BP_VN(bp)] = mf_config;
2753                 DP(BNX2X_MSG_MCP,
2754                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2755                    mf_config);
2756
2757                 /* if VIF_SET is "enabled" */
2758                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2759                         /* set rate limit directly to internal RAM */
2760                         struct cmng_init_input cmng_input;
2761                         struct rate_shaping_vars_per_vn m_rs_vn;
2762                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2763                         u32 addr = BAR_XSTRORM_INTMEM +
2764                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2765
2766                         bp->mf_config[BP_VN(bp)] = mf_config;
2767
2768                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2769                         m_rs_vn.vn_counter.rate =
2770                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2771                         m_rs_vn.vn_counter.quota =
2772                                 (m_rs_vn.vn_counter.rate *
2773                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2774
2775                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2776
2777                         /* read relevant values from mf_cfg struct in shmem */
2778                         vif_id =
2779                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2780                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2781                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2782                         vlan_val =
2783                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2784                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2785                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2786                         vlan_prio = (mf_config &
2787                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2788                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2789                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2790                         vlan_mode =
2791                                 (MF_CFG_RD(bp,
2792                                            func_mf_config[func].afex_config) &
2793                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2794                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2795                         allowed_prio =
2796                                 (MF_CFG_RD(bp,
2797                                            func_mf_config[func].afex_config) &
2798                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2799                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2800
2801                         /* send ramrod to FW, return in case of failure */
2802                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2803                                                    allowed_prio))
2804                                 return;
2805
2806                         bp->afex_def_vlan_tag = vlan_val;
2807                         bp->afex_vlan_mode = vlan_mode;
2808                 } else {
2809                         /* notify link down because BP->flags is disabled */
2810                         bnx2x_link_report(bp);
2811
2812                         /* send INVALID VIF ramrod to FW */
2813                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2814
2815                         /* Reset the default afex VLAN */
2816                         bp->afex_def_vlan_tag = -1;
2817                 }
2818         }
2819 }
2820
2821 static void bnx2x_pmf_update(struct bnx2x *bp)
2822 {
2823         int port = BP_PORT(bp);
2824         u32 val;
2825
2826         bp->port.pmf = 1;
2827         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2828
2829         /*
2830          * We need the mb() to ensure the ordering between the writing to
2831          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2832          */
2833         smp_mb();
2834
2835         /* queue a periodic task */
2836         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2837
2838         bnx2x_dcbx_pmf_update(bp);
2839
2840         /* enable nig attention */
2841         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2842         if (bp->common.int_block == INT_BLOCK_HC) {
2843                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2844                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2845         } else if (!CHIP_IS_E1x(bp)) {
2846                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2847                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2848         }
2849
2850         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2851 }
2852
2853 /* end of Link */
2854
2855 /* slow path */
2856
2857 /*
2858  * General service functions
2859  */
2860
2861 /* send the MCP a request, block until there is a reply */
2862 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2863 {
2864         int mb_idx = BP_FW_MB_IDX(bp);
2865         u32 seq;
2866         u32 rc = 0;
2867         u32 cnt = 1;
2868         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2869
2870         mutex_lock(&bp->fw_mb_mutex);
2871         seq = ++bp->fw_seq;
2872         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2873         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2874
2875         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2876                         (command | seq), param);
2877
2878         do {
2879                 /* let the FW do it's magic ... */
2880                 msleep(delay);
2881
2882                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2883
2884                 /* Give the FW up to 5 second (500*10ms) */
2885         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2886
2887         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2888            cnt*delay, rc, seq);
2889
2890         /* is this a reply to our command? */
2891         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2892                 rc &= FW_MSG_CODE_MASK;
2893         else {
2894                 /* FW BUG! */
2895                 BNX2X_ERR("FW failed to respond!\n");
2896                 bnx2x_fw_dump(bp);
2897                 rc = 0;
2898         }
2899         mutex_unlock(&bp->fw_mb_mutex);
2900
2901         return rc;
2902 }
2903
2904
2905 static void storm_memset_func_cfg(struct bnx2x *bp,
2906                                  struct tstorm_eth_function_common_config *tcfg,
2907                                  u16 abs_fid)
2908 {
2909         size_t size = sizeof(struct tstorm_eth_function_common_config);
2910
2911         u32 addr = BAR_TSTRORM_INTMEM +
2912                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2913
2914         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2915 }
2916
2917 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2918 {
2919         if (CHIP_IS_E1x(bp)) {
2920                 struct tstorm_eth_function_common_config tcfg = {0};
2921
2922                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2923         }
2924
2925         /* Enable the function in the FW */
2926         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2927         storm_memset_func_en(bp, p->func_id, 1);
2928
2929         /* spq */
2930         if (p->func_flgs & FUNC_FLG_SPQ) {
2931                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2932                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2933                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2934         }
2935 }
2936
2937 /**
2938  * bnx2x_get_tx_only_flags - Return common flags
2939  *
2940  * @bp          device handle
2941  * @fp          queue handle
2942  * @zero_stats  TRUE if statistics zeroing is needed
2943  *
2944  * Return the flags that are common for the Tx-only and not normal connections.
2945  */
2946 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2947                                             struct bnx2x_fastpath *fp,
2948                                             bool zero_stats)
2949 {
2950         unsigned long flags = 0;
2951
2952         /* PF driver will always initialize the Queue to an ACTIVE state */
2953         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2954
2955         /* tx only connections collect statistics (on the same index as the
2956          * parent connection). The statistics are zeroed when the parent
2957          * connection is initialized.
2958          */
2959
2960         __set_bit(BNX2X_Q_FLG_STATS, &flags);
2961         if (zero_stats)
2962                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2963
2964         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
2965         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
2966
2967 #ifdef BNX2X_STOP_ON_ERROR
2968         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
2969 #endif
2970
2971         return flags;
2972 }
2973
2974 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2975                                        struct bnx2x_fastpath *fp,
2976                                        bool leading)
2977 {
2978         unsigned long flags = 0;
2979
2980         /* calculate other queue flags */
2981         if (IS_MF_SD(bp))
2982                 __set_bit(BNX2X_Q_FLG_OV, &flags);
2983
2984         if (IS_FCOE_FP(fp)) {
2985                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2986                 /* For FCoE - force usage of default priority (for afex) */
2987                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2988         }
2989
2990         if (!fp->disable_tpa) {
2991                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2992                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2993                 if (fp->mode == TPA_MODE_GRO)
2994                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2995         }
2996
2997         if (leading) {
2998                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2999                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3000         }
3001
3002         /* Always set HW VLAN stripping */
3003         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3004
3005         /* configure silent vlan removal */
3006         if (IS_MF_AFEX(bp))
3007                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3008
3009
3010         return flags | bnx2x_get_common_flags(bp, fp, true);
3011 }
3012
3013 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3014         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3015         u8 cos)
3016 {
3017         gen_init->stat_id = bnx2x_stats_id(fp);
3018         gen_init->spcl_id = fp->cl_id;
3019
3020         /* Always use mini-jumbo MTU for FCoE L2 ring */
3021         if (IS_FCOE_FP(fp))
3022                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3023         else
3024                 gen_init->mtu = bp->dev->mtu;
3025
3026         gen_init->cos = cos;
3027 }
3028
3029 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3030         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3031         struct bnx2x_rxq_setup_params *rxq_init)
3032 {
3033         u8 max_sge = 0;
3034         u16 sge_sz = 0;
3035         u16 tpa_agg_size = 0;
3036
3037         if (!fp->disable_tpa) {
3038                 pause->sge_th_lo = SGE_TH_LO(bp);
3039                 pause->sge_th_hi = SGE_TH_HI(bp);
3040
3041                 /* validate SGE ring has enough to cross high threshold */
3042                 WARN_ON(bp->dropless_fc &&
3043                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3044                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3045
3046                 tpa_agg_size = TPA_AGG_SIZE;
3047                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3048                         SGE_PAGE_SHIFT;
3049                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3050                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3051                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3052         }
3053
3054         /* pause - not for e1 */
3055         if (!CHIP_IS_E1(bp)) {
3056                 pause->bd_th_lo = BD_TH_LO(bp);
3057                 pause->bd_th_hi = BD_TH_HI(bp);
3058
3059                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3060                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3061                 /*
3062                  * validate that rings have enough entries to cross
3063                  * high thresholds
3064                  */
3065                 WARN_ON(bp->dropless_fc &&
3066                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3067                                 bp->rx_ring_size);
3068                 WARN_ON(bp->dropless_fc &&
3069                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3070                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3071
3072                 pause->pri_map = 1;
3073         }
3074
3075         /* rxq setup */
3076         rxq_init->dscr_map = fp->rx_desc_mapping;
3077         rxq_init->sge_map = fp->rx_sge_mapping;
3078         rxq_init->rcq_map = fp->rx_comp_mapping;
3079         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3080
3081         /* This should be a maximum number of data bytes that may be
3082          * placed on the BD (not including paddings).
3083          */
3084         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3085                 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3086
3087         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3088         rxq_init->tpa_agg_sz = tpa_agg_size;
3089         rxq_init->sge_buf_sz = sge_sz;
3090         rxq_init->max_sges_pkt = max_sge;
3091         rxq_init->rss_engine_id = BP_FUNC(bp);
3092         rxq_init->mcast_engine_id = BP_FUNC(bp);
3093
3094         /* Maximum number or simultaneous TPA aggregation for this Queue.
3095          *
3096          * For PF Clients it should be the maximum available number.
3097          * VF driver(s) may want to define it to a smaller value.
3098          */
3099         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3100
3101         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3102         rxq_init->fw_sb_id = fp->fw_sb_id;
3103
3104         if (IS_FCOE_FP(fp))
3105                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3106         else
3107                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3108         /* configure silent vlan removal
3109          * if multi function mode is afex, then mask default vlan
3110          */
3111         if (IS_MF_AFEX(bp)) {
3112                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3113                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3114         }
3115 }
3116
3117 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3118         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3119         u8 cos)
3120 {
3121         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3122         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3123         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3124         txq_init->fw_sb_id = fp->fw_sb_id;
3125
3126         /*
3127          * set the tss leading client id for TX classfication ==
3128          * leading RSS client id
3129          */
3130         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3131
3132         if (IS_FCOE_FP(fp)) {
3133                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3134                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3135         }
3136 }
3137
3138 static void bnx2x_pf_init(struct bnx2x *bp)
3139 {
3140         struct bnx2x_func_init_params func_init = {0};
3141         struct event_ring_data eq_data = { {0} };
3142         u16 flags;
3143
3144         if (!CHIP_IS_E1x(bp)) {
3145                 /* reset IGU PF statistics: MSIX + ATTN */
3146                 /* PF */
3147                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3148                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3149                            (CHIP_MODE_IS_4_PORT(bp) ?
3150                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3151                 /* ATTN */
3152                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3153                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3154                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3155                            (CHIP_MODE_IS_4_PORT(bp) ?
3156                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3157         }
3158
3159         /* function setup flags */
3160         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3161
3162         /* This flag is relevant for E1x only.
3163          * E2 doesn't have a TPA configuration in a function level.
3164          */
3165         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3166
3167         func_init.func_flgs = flags;
3168         func_init.pf_id = BP_FUNC(bp);
3169         func_init.func_id = BP_FUNC(bp);
3170         func_init.spq_map = bp->spq_mapping;
3171         func_init.spq_prod = bp->spq_prod_idx;
3172
3173         bnx2x_func_init(bp, &func_init);
3174
3175         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3176
3177         /*
3178          * Congestion management values depend on the link rate
3179          * There is no active link so initial link rate is set to 10 Gbps.
3180          * When the link comes up The congestion management values are
3181          * re-calculated according to the actual link rate.
3182          */
3183         bp->link_vars.line_speed = SPEED_10000;
3184         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3185
3186         /* Only the PMF sets the HW */
3187         if (bp->port.pmf)
3188                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3189
3190         /* init Event Queue - PCI bus guarantees correct endianity*/
3191         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3192         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3193         eq_data.producer = bp->eq_prod;
3194         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3195         eq_data.sb_id = DEF_SB_ID;
3196         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3197 }
3198
3199
3200 static void bnx2x_e1h_disable(struct bnx2x *bp)
3201 {
3202         int port = BP_PORT(bp);
3203
3204         bnx2x_tx_disable(bp);
3205
3206         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3207 }
3208
3209 static void bnx2x_e1h_enable(struct bnx2x *bp)
3210 {
3211         int port = BP_PORT(bp);
3212
3213         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3214
3215         /* Tx queue should be only reenabled */
3216         netif_tx_wake_all_queues(bp->dev);
3217
3218         /*
3219          * Should not call netif_carrier_on since it will be called if the link
3220          * is up when checking for link state
3221          */
3222 }
3223
3224 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3225
3226 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3227 {
3228         struct eth_stats_info *ether_stat =
3229                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3230         struct bnx2x_vlan_mac_obj *mac_obj =
3231                 &bp->sp_objs->mac_obj;
3232         int i;
3233
3234         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3235                 ETH_STAT_INFO_VERSION_LEN);
3236
3237         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3238          * mac_local field in ether_stat struct. The base address is offset by 2
3239          * bytes to account for the field being 8 bytes but a mac address is
3240          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3241          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3242          * allocated by the ether_stat struct, so the macs will land in their
3243          * proper positions.
3244          */
3245         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3246                 memset(ether_stat->mac_local + i, 0,
3247                        sizeof(ether_stat->mac_local[0]));
3248         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3249                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3250                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3251                                 ETH_ALEN);
3252         ether_stat->mtu_size = bp->dev->mtu;
3253         if (bp->dev->features & NETIF_F_RXCSUM)
3254                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3255         if (bp->dev->features & NETIF_F_TSO)
3256                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3257         ether_stat->feature_flags |= bp->common.boot_mode;
3258
3259         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3260
3261         ether_stat->txq_size = bp->tx_ring_size;
3262         ether_stat->rxq_size = bp->rx_ring_size;
3263 }
3264
3265 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3266 {
3267         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3268         struct fcoe_stats_info *fcoe_stat =
3269                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3270
3271         if (!CNIC_LOADED(bp))
3272                 return;
3273
3274         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3275
3276         fcoe_stat->qos_priority =
3277                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3278
3279         /* insert FCoE stats from ramrod response */
3280         if (!NO_FCOE(bp)) {
3281                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3282                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3283                         tstorm_queue_statistics;
3284
3285                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3286                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3287                         xstorm_queue_statistics;
3288
3289                 struct fcoe_statistics_params *fw_fcoe_stat =
3290                         &bp->fw_stats_data->fcoe;
3291
3292                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3293                           fcoe_stat->rx_bytes_lo,
3294                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3295
3296                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3297                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3298                           fcoe_stat->rx_bytes_lo,
3299                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3300
3301                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3302                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3303                           fcoe_stat->rx_bytes_lo,
3304                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3305
3306                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3307                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3308                           fcoe_stat->rx_bytes_lo,
3309                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3310
3311                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3312                           fcoe_stat->rx_frames_lo,
3313                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3314
3315                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3316                           fcoe_stat->rx_frames_lo,
3317                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3318
3319                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3320                           fcoe_stat->rx_frames_lo,
3321                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3322
3323                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3324                           fcoe_stat->rx_frames_lo,
3325                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3326
3327                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3328                           fcoe_stat->tx_bytes_lo,
3329                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3330
3331                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3332                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3333                           fcoe_stat->tx_bytes_lo,
3334                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3335
3336                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3337                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3338                           fcoe_stat->tx_bytes_lo,
3339                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3340
3341                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3342                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3343                           fcoe_stat->tx_bytes_lo,
3344                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3345
3346                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3347                           fcoe_stat->tx_frames_lo,
3348                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3349
3350                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3351                           fcoe_stat->tx_frames_lo,
3352                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3353
3354                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3355                           fcoe_stat->tx_frames_lo,
3356                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3357
3358                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3359                           fcoe_stat->tx_frames_lo,
3360                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3361         }
3362
3363         /* ask L5 driver to add data to the struct */
3364         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3365 }
3366
3367 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3368 {
3369         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3370         struct iscsi_stats_info *iscsi_stat =
3371                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3372
3373         if (!CNIC_LOADED(bp))
3374                 return;
3375
3376         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3377                ETH_ALEN);
3378
3379         iscsi_stat->qos_priority =
3380                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3381
3382         /* ask L5 driver to add data to the struct */
3383         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3384 }
3385
3386 /* called due to MCP event (on pmf):
3387  *      reread new bandwidth configuration
3388  *      configure FW
3389  *      notify others function about the change
3390  */
3391 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3392 {
3393         if (bp->link_vars.link_up) {
3394                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3395                 bnx2x_link_sync_notify(bp);
3396         }
3397         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3398 }
3399
3400 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3401 {
3402         bnx2x_config_mf_bw(bp);
3403         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3404 }
3405
3406 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3407 {
3408         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3409         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3410 }
3411
3412 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3413 {
3414         enum drv_info_opcode op_code;
3415         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3416
3417         /* if drv_info version supported by MFW doesn't match - send NACK */
3418         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3419                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3420                 return;
3421         }
3422
3423         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3424                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3425
3426         memset(&bp->slowpath->drv_info_to_mcp, 0,
3427                sizeof(union drv_info_to_mcp));
3428
3429         switch (op_code) {
3430         case ETH_STATS_OPCODE:
3431                 bnx2x_drv_info_ether_stat(bp);
3432                 break;
3433         case FCOE_STATS_OPCODE:
3434                 bnx2x_drv_info_fcoe_stat(bp);
3435                 break;
3436         case ISCSI_STATS_OPCODE:
3437                 bnx2x_drv_info_iscsi_stat(bp);
3438                 break;
3439         default:
3440                 /* if op code isn't supported - send NACK */
3441                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3442                 return;
3443         }
3444
3445         /* if we got drv_info attn from MFW then these fields are defined in
3446          * shmem2 for sure
3447          */
3448         SHMEM2_WR(bp, drv_info_host_addr_lo,
3449                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3450         SHMEM2_WR(bp, drv_info_host_addr_hi,
3451                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3452
3453         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3454 }
3455
3456 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3457 {
3458         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3459
3460         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3461
3462                 /*
3463                  * This is the only place besides the function initialization
3464                  * where the bp->flags can change so it is done without any
3465                  * locks
3466                  */
3467                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3468                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3469                         bp->flags |= MF_FUNC_DIS;
3470
3471                         bnx2x_e1h_disable(bp);
3472                 } else {
3473                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3474                         bp->flags &= ~MF_FUNC_DIS;
3475
3476                         bnx2x_e1h_enable(bp);
3477                 }
3478                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3479         }
3480         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3481                 bnx2x_config_mf_bw(bp);
3482                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3483         }
3484
3485         /* Report results to MCP */
3486         if (dcc_event)
3487                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3488         else
3489                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3490 }
3491
3492 /* must be called under the spq lock */
3493 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3494 {
3495         struct eth_spe *next_spe = bp->spq_prod_bd;
3496
3497         if (bp->spq_prod_bd == bp->spq_last_bd) {
3498                 bp->spq_prod_bd = bp->spq;
3499                 bp->spq_prod_idx = 0;
3500                 DP(BNX2X_MSG_SP, "end of spq\n");
3501         } else {
3502                 bp->spq_prod_bd++;
3503                 bp->spq_prod_idx++;
3504         }
3505         return next_spe;
3506 }
3507
3508 /* must be called under the spq lock */
3509 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3510 {
3511         int func = BP_FUNC(bp);
3512
3513         /*
3514          * Make sure that BD data is updated before writing the producer:
3515          * BD data is written to the memory, the producer is read from the
3516          * memory, thus we need a full memory barrier to ensure the ordering.
3517          */
3518         mb();
3519
3520         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3521                  bp->spq_prod_idx);
3522         mmiowb();
3523 }
3524
3525 /**
3526  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3527  *
3528  * @cmd:        command to check
3529  * @cmd_type:   command type
3530  */
3531 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3532 {
3533         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3534             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3535             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3536             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3537             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3538             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3539             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3540                 return true;
3541         else
3542                 return false;
3543
3544 }
3545
3546
3547 /**
3548  * bnx2x_sp_post - place a single command on an SP ring
3549  *
3550  * @bp:         driver handle
3551  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3552  * @cid:        SW CID the command is related to
3553  * @data_hi:    command private data address (high 32 bits)
3554  * @data_lo:    command private data address (low 32 bits)
3555  * @cmd_type:   command type (e.g. NONE, ETH)
3556  *
3557  * SP data is handled as if it's always an address pair, thus data fields are
3558  * not swapped to little endian in upper functions. Instead this function swaps
3559  * data as if it's two u32 fields.
3560  */
3561 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3562                   u32 data_hi, u32 data_lo, int cmd_type)
3563 {
3564         struct eth_spe *spe;
3565         u16 type;
3566         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3567
3568 #ifdef BNX2X_STOP_ON_ERROR
3569         if (unlikely(bp->panic)) {
3570                 BNX2X_ERR("Can't post SP when there is panic\n");
3571                 return -EIO;
3572         }
3573 #endif
3574
3575         spin_lock_bh(&bp->spq_lock);
3576
3577         if (common) {
3578                 if (!atomic_read(&bp->eq_spq_left)) {
3579                         BNX2X_ERR("BUG! EQ ring full!\n");
3580                         spin_unlock_bh(&bp->spq_lock);
3581                         bnx2x_panic();
3582                         return -EBUSY;
3583                 }
3584         } else if (!atomic_read(&bp->cq_spq_left)) {
3585                         BNX2X_ERR("BUG! SPQ ring full!\n");
3586                         spin_unlock_bh(&bp->spq_lock);
3587                         bnx2x_panic();
3588                         return -EBUSY;
3589         }
3590
3591         spe = bnx2x_sp_get_next(bp);
3592
3593         /* CID needs port number to be encoded int it */
3594         spe->hdr.conn_and_cmd_data =
3595                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3596                                     HW_CID(bp, cid));
3597
3598         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3599
3600         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3601                  SPE_HDR_FUNCTION_ID);
3602
3603         spe->hdr.type = cpu_to_le16(type);
3604
3605         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3606         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3607
3608         /*
3609          * It's ok if the actual decrement is issued towards the memory
3610          * somewhere between the spin_lock and spin_unlock. Thus no
3611          * more explict memory barrier is needed.
3612          */
3613         if (common)
3614                 atomic_dec(&bp->eq_spq_left);
3615         else
3616                 atomic_dec(&bp->cq_spq_left);
3617
3618
3619         DP(BNX2X_MSG_SP,
3620            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3621            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3622            (u32)(U64_LO(bp->spq_mapping) +
3623            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3624            HW_CID(bp, cid), data_hi, data_lo, type,
3625            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3626
3627         bnx2x_sp_prod_update(bp);
3628         spin_unlock_bh(&bp->spq_lock);
3629         return 0;
3630 }
3631
3632 /* acquire split MCP access lock register */
3633 static int bnx2x_acquire_alr(struct bnx2x *bp)
3634 {
3635         u32 j, val;
3636         int rc = 0;
3637
3638         might_sleep();
3639         for (j = 0; j < 1000; j++) {
3640                 val = (1UL << 31);
3641                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3642                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3643                 if (val & (1L << 31))
3644                         break;
3645
3646                 msleep(5);
3647         }
3648         if (!(val & (1L << 31))) {
3649                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3650                 rc = -EBUSY;
3651         }
3652
3653         return rc;
3654 }
3655
3656 /* release split MCP access lock register */
3657 static void bnx2x_release_alr(struct bnx2x *bp)
3658 {
3659         REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3660 }
3661
3662 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3663 #define BNX2X_DEF_SB_IDX        0x0002
3664
3665 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3666 {
3667         struct host_sp_status_block *def_sb = bp->def_status_blk;
3668         u16 rc = 0;
3669
3670         barrier(); /* status block is written to by the chip */
3671         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3672                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3673                 rc |= BNX2X_DEF_SB_ATT_IDX;
3674         }
3675
3676         if (bp->def_idx != def_sb->sp_sb.running_index) {
3677                 bp->def_idx = def_sb->sp_sb.running_index;
3678                 rc |= BNX2X_DEF_SB_IDX;
3679         }
3680
3681         /* Do not reorder: indecies reading should complete before handling */
3682         barrier();
3683         return rc;
3684 }
3685
3686 /*
3687  * slow path service functions
3688  */
3689
3690 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3691 {
3692         int port = BP_PORT(bp);
3693         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3694                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3695         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3696                                        NIG_REG_MASK_INTERRUPT_PORT0;
3697         u32 aeu_mask;
3698         u32 nig_mask = 0;
3699         u32 reg_addr;
3700
3701         if (bp->attn_state & asserted)
3702                 BNX2X_ERR("IGU ERROR\n");
3703
3704         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3705         aeu_mask = REG_RD(bp, aeu_addr);
3706
3707         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3708            aeu_mask, asserted);
3709         aeu_mask &= ~(asserted & 0x3ff);
3710         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3711
3712         REG_WR(bp, aeu_addr, aeu_mask);
3713         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3714
3715         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3716         bp->attn_state |= asserted;
3717         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3718
3719         if (asserted & ATTN_HARD_WIRED_MASK) {
3720                 if (asserted & ATTN_NIG_FOR_FUNC) {
3721
3722                         bnx2x_acquire_phy_lock(bp);
3723
3724                         /* save nig interrupt mask */
3725                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3726
3727                         /* If nig_mask is not set, no need to call the update
3728                          * function.
3729                          */
3730                         if (nig_mask) {
3731                                 REG_WR(bp, nig_int_mask_addr, 0);
3732
3733                                 bnx2x_link_attn(bp);
3734                         }
3735
3736                         /* handle unicore attn? */
3737                 }
3738                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3739                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3740
3741                 if (asserted & GPIO_2_FUNC)
3742                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3743
3744                 if (asserted & GPIO_3_FUNC)
3745                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3746
3747                 if (asserted & GPIO_4_FUNC)
3748                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3749
3750                 if (port == 0) {
3751                         if (asserted & ATTN_GENERAL_ATTN_1) {
3752                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3753                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3754                         }
3755                         if (asserted & ATTN_GENERAL_ATTN_2) {
3756                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3757                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3758                         }
3759                         if (asserted & ATTN_GENERAL_ATTN_3) {
3760                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3761                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3762                         }
3763                 } else {
3764                         if (asserted & ATTN_GENERAL_ATTN_4) {
3765                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3766                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3767                         }
3768                         if (asserted & ATTN_GENERAL_ATTN_5) {
3769                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3770                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3771                         }
3772                         if (asserted & ATTN_GENERAL_ATTN_6) {
3773                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3774                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3775                         }
3776                 }
3777
3778         } /* if hardwired */
3779
3780         if (bp->common.int_block == INT_BLOCK_HC)
3781                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3782                             COMMAND_REG_ATTN_BITS_SET);
3783         else
3784                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3785
3786         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3787            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3788         REG_WR(bp, reg_addr, asserted);
3789
3790         /* now set back the mask */
3791         if (asserted & ATTN_NIG_FOR_FUNC) {
3792                 /* Verify that IGU ack through BAR was written before restoring
3793                  * NIG mask. This loop should exit after 2-3 iterations max.
3794                  */
3795                 if (bp->common.int_block != INT_BLOCK_HC) {
3796                         u32 cnt = 0, igu_acked;
3797                         do {
3798                                 igu_acked = REG_RD(bp,
3799                                                    IGU_REG_ATTENTION_ACK_BITS);
3800                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3801                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3802                         if (!igu_acked)
3803                                 DP(NETIF_MSG_HW,
3804                                    "Failed to verify IGU ack on time\n");
3805                         barrier();
3806                 }
3807                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3808                 bnx2x_release_phy_lock(bp);
3809         }
3810 }
3811
3812 static void bnx2x_fan_failure(struct bnx2x *bp)
3813 {
3814         int port = BP_PORT(bp);
3815         u32 ext_phy_config;
3816         /* mark the failure */
3817         ext_phy_config =
3818                 SHMEM_RD(bp,
3819                          dev_info.port_hw_config[port].external_phy_config);
3820
3821         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3822         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3823         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3824                  ext_phy_config);
3825
3826         /* log the failure */
3827         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3828                             "Please contact OEM Support for assistance\n");
3829
3830         /*
3831          * Schedule device reset (unload)
3832          * This is due to some boards consuming sufficient power when driver is
3833          * up to overheat if fan fails.
3834          */
3835         smp_mb__before_clear_bit();
3836         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3837         smp_mb__after_clear_bit();
3838         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3839
3840 }
3841
3842 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3843 {
3844         int port = BP_PORT(bp);
3845         int reg_offset;
3846         u32 val;
3847
3848         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3849                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3850
3851         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3852
3853                 val = REG_RD(bp, reg_offset);
3854                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3855                 REG_WR(bp, reg_offset, val);
3856
3857                 BNX2X_ERR("SPIO5 hw attention\n");
3858
3859                 /* Fan failure attention */
3860                 bnx2x_hw_reset_phy(&bp->link_params);
3861                 bnx2x_fan_failure(bp);
3862         }
3863
3864         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3865                 bnx2x_acquire_phy_lock(bp);
3866                 bnx2x_handle_module_detect_int(&bp->link_params);
3867                 bnx2x_release_phy_lock(bp);
3868         }
3869
3870         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3871
3872                 val = REG_RD(bp, reg_offset);
3873                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3874                 REG_WR(bp, reg_offset, val);
3875
3876                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3877                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3878                 bnx2x_panic();
3879         }
3880 }
3881
3882 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3883 {
3884         u32 val;
3885
3886         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3887
3888                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3889                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3890                 /* DORQ discard attention */
3891                 if (val & 0x2)
3892                         BNX2X_ERR("FATAL error from DORQ\n");
3893         }
3894
3895         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3896
3897                 int port = BP_PORT(bp);
3898                 int reg_offset;
3899
3900                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3901                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3902
3903                 val = REG_RD(bp, reg_offset);
3904                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3905                 REG_WR(bp, reg_offset, val);
3906
3907                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3908                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3909                 bnx2x_panic();
3910         }
3911 }
3912
3913 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3914 {
3915         u32 val;
3916
3917         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3918
3919                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3920                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3921                 /* CFC error attention */
3922                 if (val & 0x2)
3923                         BNX2X_ERR("FATAL error from CFC\n");
3924         }
3925
3926         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3927                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3928                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3929                 /* RQ_USDMDP_FIFO_OVERFLOW */
3930                 if (val & 0x18000)
3931                         BNX2X_ERR("FATAL error from PXP\n");
3932
3933                 if (!CHIP_IS_E1x(bp)) {
3934                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3935                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3936                 }
3937         }
3938
3939         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3940
3941                 int port = BP_PORT(bp);
3942                 int reg_offset;
3943
3944                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3945                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3946
3947                 val = REG_RD(bp, reg_offset);
3948                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3949                 REG_WR(bp, reg_offset, val);
3950
3951                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3952                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3953                 bnx2x_panic();
3954         }
3955 }
3956
3957 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3958 {
3959         u32 val;
3960
3961         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3962
3963                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3964                         int func = BP_FUNC(bp);
3965
3966                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3967                         bnx2x_read_mf_cfg(bp);
3968                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3969                                         func_mf_config[BP_ABS_FUNC(bp)].config);
3970                         val = SHMEM_RD(bp,
3971                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
3972                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3973                                 bnx2x_dcc_event(bp,
3974                                             (val & DRV_STATUS_DCC_EVENT_MASK));
3975
3976                         if (val & DRV_STATUS_SET_MF_BW)
3977                                 bnx2x_set_mf_bw(bp);
3978
3979                         if (val & DRV_STATUS_DRV_INFO_REQ)
3980                                 bnx2x_handle_drv_info_req(bp);
3981
3982                         if (val & DRV_STATUS_VF_DISABLED)
3983                                 bnx2x_vf_handle_flr_event(bp);
3984
3985                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3986                                 bnx2x_pmf_update(bp);
3987
3988                         if (bp->port.pmf &&
3989                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3990                                 bp->dcbx_enabled > 0)
3991                                 /* start dcbx state machine */
3992                                 bnx2x_dcbx_set_params(bp,
3993                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
3994                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
3995                                 bnx2x_handle_afex_cmd(bp,
3996                                         val & DRV_STATUS_AFEX_EVENT_MASK);
3997                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3998                                 bnx2x_handle_eee_event(bp);
3999                         if (bp->link_vars.periodic_flags &
4000                             PERIODIC_FLAGS_LINK_EVENT) {
4001                                 /*  sync with link */
4002                                 bnx2x_acquire_phy_lock(bp);
4003                                 bp->link_vars.periodic_flags &=
4004                                         ~PERIODIC_FLAGS_LINK_EVENT;
4005                                 bnx2x_release_phy_lock(bp);
4006                                 if (IS_MF(bp))
4007                                         bnx2x_link_sync_notify(bp);
4008                                 bnx2x_link_report(bp);
4009                         }
4010                         /* Always call it here: bnx2x_link_report() will
4011                          * prevent the link indication duplication.
4012                          */
4013                         bnx2x__link_status_update(bp);
4014                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4015
4016                         BNX2X_ERR("MC assert!\n");
4017                         bnx2x_mc_assert(bp);
4018                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4019                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4020                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4021                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4022                         bnx2x_panic();
4023
4024                 } else if (attn & BNX2X_MCP_ASSERT) {
4025
4026                         BNX2X_ERR("MCP assert!\n");
4027                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4028                         bnx2x_fw_dump(bp);
4029
4030                 } else
4031                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4032         }
4033
4034         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4035                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4036                 if (attn & BNX2X_GRC_TIMEOUT) {
4037                         val = CHIP_IS_E1(bp) ? 0 :
4038                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4039                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4040                 }
4041                 if (attn & BNX2X_GRC_RSV) {
4042                         val = CHIP_IS_E1(bp) ? 0 :
4043                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4044                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4045                 }
4046                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4047         }
4048 }
4049
4050 /*
4051  * Bits map:
4052  * 0-7   - Engine0 load counter.
4053  * 8-15  - Engine1 load counter.
4054  * 16    - Engine0 RESET_IN_PROGRESS bit.
4055  * 17    - Engine1 RESET_IN_PROGRESS bit.
4056  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4057  *         on the engine
4058  * 19    - Engine1 ONE_IS_LOADED.
4059  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4060  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4061  *         just the one belonging to its engine).
4062  *
4063  */
4064 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4065
4066 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4067 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4068 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4069 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4070 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4071 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4072 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4073
4074 /*
4075  * Set the GLOBAL_RESET bit.
4076  *
4077  * Should be run under rtnl lock
4078  */
4079 void bnx2x_set_reset_global(struct bnx2x *bp)
4080 {
4081         u32 val;
4082         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4083         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4084         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4085         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4086 }
4087
4088 /*
4089  * Clear the GLOBAL_RESET bit.
4090  *
4091  * Should be run under rtnl lock
4092  */
4093 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4094 {
4095         u32 val;
4096         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4097         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4098         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4099         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4100 }
4101
4102 /*
4103  * Checks the GLOBAL_RESET bit.
4104  *
4105  * should be run under rtnl lock
4106  */
4107 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4108 {
4109         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4110
4111         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4112         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4113 }
4114
4115 /*
4116  * Clear RESET_IN_PROGRESS bit for the current engine.
4117  *
4118  * Should be run under rtnl lock
4119  */
4120 static void bnx2x_set_reset_done(struct bnx2x *bp)
4121 {
4122         u32 val;
4123         u32 bit = BP_PATH(bp) ?
4124                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4125         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4126         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4127
4128         /* Clear the bit */
4129         val &= ~bit;
4130         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4131
4132         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4133 }
4134
4135 /*
4136  * Set RESET_IN_PROGRESS for the current engine.
4137  *
4138  * should be run under rtnl lock
4139  */
4140 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4141 {
4142         u32 val;
4143         u32 bit = BP_PATH(bp) ?
4144                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4145         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4146         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4147
4148         /* Set the bit */
4149         val |= bit;
4150         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4151         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4152 }
4153
4154 /*
4155  * Checks the RESET_IN_PROGRESS bit for the given engine.
4156  * should be run under rtnl lock
4157  */
4158 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4159 {
4160         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4161         u32 bit = engine ?
4162                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4163
4164         /* return false if bit is set */
4165         return (val & bit) ? false : true;
4166 }
4167
4168 /*
4169  * set pf load for the current pf.
4170  *
4171  * should be run under rtnl lock
4172  */
4173 void bnx2x_set_pf_load(struct bnx2x *bp)
4174 {
4175         u32 val1, val;
4176         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4177                              BNX2X_PATH0_LOAD_CNT_MASK;
4178         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4179                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4180
4181         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4182         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4183
4184         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4185
4186         /* get the current counter value */
4187         val1 = (val & mask) >> shift;
4188
4189         /* set bit of that PF */
4190         val1 |= (1 << bp->pf_num);
4191
4192         /* clear the old value */
4193         val &= ~mask;
4194
4195         /* set the new one */
4196         val |= ((val1 << shift) & mask);
4197
4198         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4199         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4200 }
4201
4202 /**
4203  * bnx2x_clear_pf_load - clear pf load mark
4204  *
4205  * @bp:         driver handle
4206  *
4207  * Should be run under rtnl lock.
4208  * Decrements the load counter for the current engine. Returns
4209  * whether other functions are still loaded
4210  */
4211 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4212 {
4213         u32 val1, val;
4214         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4215                              BNX2X_PATH0_LOAD_CNT_MASK;
4216         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4217                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4218
4219         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4220         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4221         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4222
4223         /* get the current counter value */
4224         val1 = (val & mask) >> shift;
4225
4226         /* clear bit of that PF */
4227         val1 &= ~(1 << bp->pf_num);
4228
4229         /* clear the old value */
4230         val &= ~mask;
4231
4232         /* set the new one */
4233         val |= ((val1 << shift) & mask);
4234
4235         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4236         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4237         return val1 != 0;
4238 }
4239
4240 /*
4241  * Read the load status for the current engine.
4242  *
4243  * should be run under rtnl lock
4244  */
4245 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4246 {
4247         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4248                              BNX2X_PATH0_LOAD_CNT_MASK);
4249         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4250                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4251         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4252
4253         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4254
4255         val = (val & mask) >> shift;
4256
4257         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4258            engine, val);
4259
4260         return val != 0;
4261 }
4262
4263 static void _print_next_block(int idx, const char *blk)
4264 {
4265         pr_cont("%s%s", idx ? ", " : "", blk);
4266 }
4267
4268 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4269                                            bool print)
4270 {
4271         int i = 0;
4272         u32 cur_bit = 0;
4273         for (i = 0; sig; i++) {
4274                 cur_bit = ((u32)0x1 << i);
4275                 if (sig & cur_bit) {
4276                         switch (cur_bit) {
4277                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4278                                 if (print)
4279                                         _print_next_block(par_num++, "BRB");
4280                                 break;
4281                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4282                                 if (print)
4283                                         _print_next_block(par_num++, "PARSER");
4284                                 break;
4285                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4286                                 if (print)
4287                                         _print_next_block(par_num++, "TSDM");
4288                                 break;
4289                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4290                                 if (print)
4291                                         _print_next_block(par_num++,
4292                                                           "SEARCHER");
4293                                 break;
4294                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4295                                 if (print)
4296                                         _print_next_block(par_num++, "TCM");
4297                                 break;
4298                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4299                                 if (print)
4300                                         _print_next_block(par_num++, "TSEMI");
4301                                 break;
4302                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4303                                 if (print)
4304                                         _print_next_block(par_num++, "XPB");
4305                                 break;
4306                         }
4307
4308                         /* Clear the bit */
4309                         sig &= ~cur_bit;
4310                 }
4311         }
4312
4313         return par_num;
4314 }
4315
4316 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4317                                            bool *global, bool print)
4318 {
4319         int i = 0;
4320         u32 cur_bit = 0;
4321         for (i = 0; sig; i++) {
4322                 cur_bit = ((u32)0x1 << i);
4323                 if (sig & cur_bit) {
4324                         switch (cur_bit) {
4325                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4326                                 if (print)
4327                                         _print_next_block(par_num++, "PBF");
4328                                 break;
4329                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4330                                 if (print)
4331                                         _print_next_block(par_num++, "QM");
4332                                 break;
4333                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4334                                 if (print)
4335                                         _print_next_block(par_num++, "TM");
4336                                 break;
4337                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4338                                 if (print)
4339                                         _print_next_block(par_num++, "XSDM");
4340                                 break;
4341                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4342                                 if (print)
4343                                         _print_next_block(par_num++, "XCM");
4344                                 break;
4345                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4346                                 if (print)
4347                                         _print_next_block(par_num++, "XSEMI");
4348                                 break;
4349                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4350                                 if (print)
4351                                         _print_next_block(par_num++,
4352                                                           "DOORBELLQ");
4353                                 break;
4354                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4355                                 if (print)
4356                                         _print_next_block(par_num++, "NIG");
4357                                 break;
4358                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4359                                 if (print)
4360                                         _print_next_block(par_num++,
4361                                                           "VAUX PCI CORE");
4362                                 *global = true;
4363                                 break;
4364                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4365                                 if (print)
4366                                         _print_next_block(par_num++, "DEBUG");
4367                                 break;
4368                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4369                                 if (print)
4370                                         _print_next_block(par_num++, "USDM");
4371                                 break;
4372                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4373                                 if (print)
4374                                         _print_next_block(par_num++, "UCM");
4375                                 break;
4376                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4377                                 if (print)
4378                                         _print_next_block(par_num++, "USEMI");
4379                                 break;
4380                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4381                                 if (print)
4382                                         _print_next_block(par_num++, "UPB");
4383                                 break;
4384                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4385                                 if (print)
4386                                         _print_next_block(par_num++, "CSDM");
4387                                 break;
4388                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4389                                 if (print)
4390                                         _print_next_block(par_num++, "CCM");
4391                                 break;
4392                         }
4393
4394                         /* Clear the bit */
4395                         sig &= ~cur_bit;
4396                 }
4397         }
4398
4399         return par_num;
4400 }
4401
4402 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4403                                            bool print)
4404 {
4405         int i = 0;
4406         u32 cur_bit = 0;
4407         for (i = 0; sig; i++) {
4408                 cur_bit = ((u32)0x1 << i);
4409                 if (sig & cur_bit) {
4410                         switch (cur_bit) {
4411                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4412                                 if (print)
4413                                         _print_next_block(par_num++, "CSEMI");
4414                                 break;
4415                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4416                                 if (print)
4417                                         _print_next_block(par_num++, "PXP");
4418                                 break;
4419                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4420                                 if (print)
4421                                         _print_next_block(par_num++,
4422                                         "PXPPCICLOCKCLIENT");
4423                                 break;
4424                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4425                                 if (print)
4426                                         _print_next_block(par_num++, "CFC");
4427                                 break;
4428                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4429                                 if (print)
4430                                         _print_next_block(par_num++, "CDU");
4431                                 break;
4432                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4433                                 if (print)
4434                                         _print_next_block(par_num++, "DMAE");
4435                                 break;
4436                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4437                                 if (print)
4438                                         _print_next_block(par_num++, "IGU");
4439                                 break;
4440                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4441                                 if (print)
4442                                         _print_next_block(par_num++, "MISC");
4443                                 break;
4444                         }
4445
4446                         /* Clear the bit */
4447                         sig &= ~cur_bit;
4448                 }
4449         }
4450
4451         return par_num;
4452 }
4453
4454 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4455                                            bool *global, bool print)
4456 {
4457         int i = 0;
4458         u32 cur_bit = 0;
4459         for (i = 0; sig; i++) {
4460                 cur_bit = ((u32)0x1 << i);
4461                 if (sig & cur_bit) {
4462                         switch (cur_bit) {
4463                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4464                                 if (print)
4465                                         _print_next_block(par_num++, "MCP ROM");
4466                                 *global = true;
4467                                 break;
4468                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4469                                 if (print)
4470                                         _print_next_block(par_num++,
4471                                                           "MCP UMP RX");
4472                                 *global = true;
4473                                 break;
4474                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4475                                 if (print)
4476                                         _print_next_block(par_num++,
4477                                                           "MCP UMP TX");
4478                                 *global = true;
4479                                 break;
4480                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4481                                 if (print)
4482                                         _print_next_block(par_num++,
4483                                                           "MCP SCPAD");
4484                                 *global = true;
4485                                 break;
4486                         }
4487
4488                         /* Clear the bit */
4489                         sig &= ~cur_bit;
4490                 }
4491         }
4492
4493         return par_num;
4494 }
4495
4496 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4497                                            bool print)
4498 {
4499         int i = 0;
4500         u32 cur_bit = 0;
4501         for (i = 0; sig; i++) {
4502                 cur_bit = ((u32)0x1 << i);
4503                 if (sig & cur_bit) {
4504                         switch (cur_bit) {
4505                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4506                                 if (print)
4507                                         _print_next_block(par_num++, "PGLUE_B");
4508                                 break;
4509                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4510                                 if (print)
4511                                         _print_next_block(par_num++, "ATC");
4512                                 break;
4513                         }
4514
4515                         /* Clear the bit */
4516                         sig &= ~cur_bit;
4517                 }
4518         }
4519
4520         return par_num;
4521 }
4522
4523 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4524                               u32 *sig)
4525 {
4526         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4527             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4528             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4529             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4530             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4531                 int par_num = 0;
4532                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4533                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4534                           sig[0] & HW_PRTY_ASSERT_SET_0,
4535                           sig[1] & HW_PRTY_ASSERT_SET_1,
4536                           sig[2] & HW_PRTY_ASSERT_SET_2,
4537                           sig[3] & HW_PRTY_ASSERT_SET_3,
4538                           sig[4] & HW_PRTY_ASSERT_SET_4);
4539                 if (print)
4540                         netdev_err(bp->dev,
4541                                    "Parity errors detected in blocks: ");
4542                 par_num = bnx2x_check_blocks_with_parity0(
4543                         sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4544                 par_num = bnx2x_check_blocks_with_parity1(
4545                         sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4546                 par_num = bnx2x_check_blocks_with_parity2(
4547                         sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4548                 par_num = bnx2x_check_blocks_with_parity3(
4549                         sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4550                 par_num = bnx2x_check_blocks_with_parity4(
4551                         sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4552
4553                 if (print)
4554                         pr_cont("\n");
4555
4556                 return true;
4557         } else
4558                 return false;
4559 }
4560
4561 /**
4562  * bnx2x_chk_parity_attn - checks for parity attentions.
4563  *
4564  * @bp:         driver handle
4565  * @global:     true if there was a global attention
4566  * @print:      show parity attention in syslog
4567  */
4568 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4569 {
4570         struct attn_route attn = { {0} };
4571         int port = BP_PORT(bp);
4572
4573         attn.sig[0] = REG_RD(bp,
4574                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4575                              port*4);
4576         attn.sig[1] = REG_RD(bp,
4577                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4578                              port*4);
4579         attn.sig[2] = REG_RD(bp,
4580                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4581                              port*4);
4582         attn.sig[3] = REG_RD(bp,
4583                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4584                              port*4);
4585
4586         if (!CHIP_IS_E1x(bp))
4587                 attn.sig[4] = REG_RD(bp,
4588                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4589                                      port*4);
4590
4591         return bnx2x_parity_attn(bp, global, print, attn.sig);
4592 }
4593
4594
4595 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4596 {
4597         u32 val;
4598         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4599
4600                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4601                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4602                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4603                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4604                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4605                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4606                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4607                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4608                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4609                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4610                 if (val &
4611                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4612                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4613                 if (val &
4614                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4615                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4616                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4617                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4618                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4619                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4620                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4621                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4622         }
4623         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4624                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4625                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4626                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4627                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4628                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4629                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4630                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4631                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4632                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4633                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4634                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4635                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4636                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4637                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4638         }
4639
4640         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4641                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4642                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4643                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4644                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4645         }
4646
4647 }
4648
4649 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4650 {
4651         struct attn_route attn, *group_mask;
4652         int port = BP_PORT(bp);
4653         int index;
4654         u32 reg_addr;
4655         u32 val;
4656         u32 aeu_mask;
4657         bool global = false;
4658
4659         /* need to take HW lock because MCP or other port might also
4660            try to handle this event */
4661         bnx2x_acquire_alr(bp);
4662
4663         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4664 #ifndef BNX2X_STOP_ON_ERROR
4665                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4666                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4667                 /* Disable HW interrupts */
4668                 bnx2x_int_disable(bp);
4669                 /* In case of parity errors don't handle attentions so that
4670                  * other function would "see" parity errors.
4671                  */
4672 #else
4673                 bnx2x_panic();
4674 #endif
4675                 bnx2x_release_alr(bp);
4676                 return;
4677         }
4678
4679         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4680         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4681         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4682         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4683         if (!CHIP_IS_E1x(bp))
4684                 attn.sig[4] =
4685                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4686         else
4687                 attn.sig[4] = 0;
4688
4689         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4690            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4691
4692         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4693                 if (deasserted & (1 << index)) {
4694                         group_mask = &bp->attn_group[index];
4695
4696                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4697                            index,
4698                            group_mask->sig[0], group_mask->sig[1],
4699                            group_mask->sig[2], group_mask->sig[3],
4700                            group_mask->sig[4]);
4701
4702                         bnx2x_attn_int_deasserted4(bp,
4703                                         attn.sig[4] & group_mask->sig[4]);
4704                         bnx2x_attn_int_deasserted3(bp,
4705                                         attn.sig[3] & group_mask->sig[3]);
4706                         bnx2x_attn_int_deasserted1(bp,
4707                                         attn.sig[1] & group_mask->sig[1]);
4708                         bnx2x_attn_int_deasserted2(bp,
4709                                         attn.sig[2] & group_mask->sig[2]);
4710                         bnx2x_attn_int_deasserted0(bp,
4711                                         attn.sig[0] & group_mask->sig[0]);
4712                 }
4713         }
4714
4715         bnx2x_release_alr(bp);
4716
4717         if (bp->common.int_block == INT_BLOCK_HC)
4718                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4719                             COMMAND_REG_ATTN_BITS_CLR);
4720         else
4721                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4722
4723         val = ~deasserted;
4724         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4725            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4726         REG_WR(bp, reg_addr, val);
4727
4728         if (~bp->attn_state & deasserted)
4729                 BNX2X_ERR("IGU ERROR\n");
4730
4731         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4732                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4733
4734         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4735         aeu_mask = REG_RD(bp, reg_addr);
4736
4737         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4738            aeu_mask, deasserted);
4739         aeu_mask |= (deasserted & 0x3ff);
4740         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4741
4742         REG_WR(bp, reg_addr, aeu_mask);
4743         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4744
4745         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4746         bp->attn_state &= ~deasserted;
4747         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4748 }
4749
4750 static void bnx2x_attn_int(struct bnx2x *bp)
4751 {
4752         /* read local copy of bits */
4753         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4754                                                                 attn_bits);
4755         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4756                                                                 attn_bits_ack);
4757         u32 attn_state = bp->attn_state;
4758
4759         /* look for changed bits */
4760         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4761         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4762
4763         DP(NETIF_MSG_HW,
4764            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4765            attn_bits, attn_ack, asserted, deasserted);
4766
4767         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4768                 BNX2X_ERR("BAD attention state\n");
4769
4770         /* handle bits that were raised */
4771         if (asserted)
4772                 bnx2x_attn_int_asserted(bp, asserted);
4773
4774         if (deasserted)
4775                 bnx2x_attn_int_deasserted(bp, deasserted);
4776 }
4777
4778 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4779                       u16 index, u8 op, u8 update)
4780 {
4781         u32 igu_addr = bp->igu_base_addr;
4782         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4783         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4784                              igu_addr);
4785 }
4786
4787 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4788 {
4789         /* No memory barriers */
4790         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4791         mmiowb(); /* keep prod updates ordered */
4792 }
4793
4794 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4795                                       union event_ring_elem *elem)
4796 {
4797         u8 err = elem->message.error;
4798
4799         if (!bp->cnic_eth_dev.starting_cid  ||
4800             (cid < bp->cnic_eth_dev.starting_cid &&
4801             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4802                 return 1;
4803
4804         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4805
4806         if (unlikely(err)) {
4807
4808                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4809                           cid);
4810                 bnx2x_panic_dump(bp, false);
4811         }
4812         bnx2x_cnic_cfc_comp(bp, cid, err);
4813         return 0;
4814 }
4815
4816 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4817 {
4818         struct bnx2x_mcast_ramrod_params rparam;
4819         int rc;
4820
4821         memset(&rparam, 0, sizeof(rparam));
4822
4823         rparam.mcast_obj = &bp->mcast_obj;
4824
4825         netif_addr_lock_bh(bp->dev);
4826
4827         /* Clear pending state for the last command */
4828         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4829
4830         /* If there are pending mcast commands - send them */
4831         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4832                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4833                 if (rc < 0)
4834                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4835                                   rc);
4836         }
4837
4838         netif_addr_unlock_bh(bp->dev);
4839 }
4840
4841 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4842                                             union event_ring_elem *elem)
4843 {
4844         unsigned long ramrod_flags = 0;
4845         int rc = 0;
4846         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4847         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4848
4849         /* Always push next commands out, don't wait here */
4850         __set_bit(RAMROD_CONT, &ramrod_flags);
4851
4852         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
4853                             >> BNX2X_SWCID_SHIFT) {
4854         case BNX2X_FILTER_MAC_PENDING:
4855                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4856                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4857                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4858                 else
4859                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4860
4861                 break;
4862         case BNX2X_FILTER_MCAST_PENDING:
4863                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4864                 /* This is only relevant for 57710 where multicast MACs are
4865                  * configured as unicast MACs using the same ramrod.
4866                  */
4867                 bnx2x_handle_mcast_eqe(bp);
4868                 return;
4869         default:
4870                 BNX2X_ERR("Unsupported classification command: %d\n",
4871                           elem->message.data.eth_event.echo);
4872                 return;
4873         }
4874
4875         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4876
4877         if (rc < 0)
4878                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4879         else if (rc > 0)
4880                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4881
4882 }
4883
4884 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4885
4886 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4887 {
4888         netif_addr_lock_bh(bp->dev);
4889
4890         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4891
4892         /* Send rx_mode command again if was requested */
4893         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4894                 bnx2x_set_storm_rx_mode(bp);
4895         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4896                                     &bp->sp_state))
4897                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4898         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4899                                     &bp->sp_state))
4900                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4901
4902         netif_addr_unlock_bh(bp->dev);
4903 }
4904
4905 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4906                                               union event_ring_elem *elem)
4907 {
4908         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4909                 DP(BNX2X_MSG_SP,
4910                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4911                    elem->message.data.vif_list_event.func_bit_map);
4912                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4913                         elem->message.data.vif_list_event.func_bit_map);
4914         } else if (elem->message.data.vif_list_event.echo ==
4915                    VIF_LIST_RULE_SET) {
4916                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4917                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4918         }
4919 }
4920
4921 /* called with rtnl_lock */
4922 static void bnx2x_after_function_update(struct bnx2x *bp)
4923 {
4924         int q, rc;
4925         struct bnx2x_fastpath *fp;
4926         struct bnx2x_queue_state_params queue_params = {NULL};
4927         struct bnx2x_queue_update_params *q_update_params =
4928                 &queue_params.params.update;
4929
4930         /* Send Q update command with afex vlan removal values for all Qs */
4931         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4932
4933         /* set silent vlan removal values according to vlan mode */
4934         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4935                   &q_update_params->update_flags);
4936         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4937                   &q_update_params->update_flags);
4938         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4939
4940         /* in access mode mark mask and value are 0 to strip all vlans */
4941         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4942                 q_update_params->silent_removal_value = 0;
4943                 q_update_params->silent_removal_mask = 0;
4944         } else {
4945                 q_update_params->silent_removal_value =
4946                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4947                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4948         }
4949
4950         for_each_eth_queue(bp, q) {
4951                 /* Set the appropriate Queue object */
4952                 fp = &bp->fp[q];
4953                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4954
4955                 /* send the ramrod */
4956                 rc = bnx2x_queue_state_change(bp, &queue_params);
4957                 if (rc < 0)
4958                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4959                                   q);
4960         }
4961
4962         if (!NO_FCOE(bp)) {
4963                 fp = &bp->fp[FCOE_IDX(bp)];
4964                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4965
4966                 /* clear pending completion bit */
4967                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4968
4969                 /* mark latest Q bit */
4970                 smp_mb__before_clear_bit();
4971                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4972                 smp_mb__after_clear_bit();
4973
4974                 /* send Q update ramrod for FCoE Q */
4975                 rc = bnx2x_queue_state_change(bp, &queue_params);
4976                 if (rc < 0)
4977                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4978                                   q);
4979         } else {
4980                 /* If no FCoE ring - ACK MCP now */
4981                 bnx2x_link_report(bp);
4982                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4983         }
4984 }
4985
4986 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4987         struct bnx2x *bp, u32 cid)
4988 {
4989         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4990
4991         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
4992                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4993         else
4994                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4995 }
4996
4997 static void bnx2x_eq_int(struct bnx2x *bp)
4998 {
4999         u16 hw_cons, sw_cons, sw_prod;
5000         union event_ring_elem *elem;
5001         u8 echo;
5002         u32 cid;
5003         u8 opcode;
5004         int rc, spqe_cnt = 0;
5005         struct bnx2x_queue_sp_obj *q_obj;
5006         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5007         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5008
5009         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5010
5011         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5012          * when we get the the next-page we nned to adjust so the loop
5013          * condition below will be met. The next element is the size of a
5014          * regular element and hence incrementing by 1
5015          */
5016         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5017                 hw_cons++;
5018
5019         /* This function may never run in parallel with itself for a
5020          * specific bp, thus there is no need in "paired" read memory
5021          * barrier here.
5022          */
5023         sw_cons = bp->eq_cons;
5024         sw_prod = bp->eq_prod;
5025
5026         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5027                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5028
5029         for (; sw_cons != hw_cons;
5030               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5031
5032                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5033
5034                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5035                 if (!rc) {
5036                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5037                            rc);
5038                         goto next_spqe;
5039                 }
5040
5041                 /* elem CID originates from FW; actually LE */
5042                 cid = SW_CID((__force __le32)
5043                              elem->message.data.cfc_del_event.cid);
5044                 opcode = elem->message.opcode;
5045
5046                 /* handle eq element */
5047                 switch (opcode) {
5048                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5049                         DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5050                         bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5051                         continue;
5052
5053                 case EVENT_RING_OPCODE_STAT_QUERY:
5054                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5055                            "got statistics comp event %d\n",
5056                            bp->stats_comp++);
5057                         /* nothing to do with stats comp */
5058                         goto next_spqe;
5059
5060                 case EVENT_RING_OPCODE_CFC_DEL:
5061                         /* handle according to cid range */
5062                         /*
5063                          * we may want to verify here that the bp state is
5064                          * HALTING
5065                          */
5066                         DP(BNX2X_MSG_SP,
5067                            "got delete ramrod for MULTI[%d]\n", cid);
5068
5069                         if (CNIC_LOADED(bp) &&
5070                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5071                                 goto next_spqe;
5072
5073                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5074
5075                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5076                                 break;
5077
5078
5079
5080                         goto next_spqe;
5081
5082                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5083                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5084                         if (f_obj->complete_cmd(bp, f_obj,
5085                                                 BNX2X_F_CMD_TX_STOP))
5086                                 break;
5087                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5088                         goto next_spqe;
5089
5090                 case EVENT_RING_OPCODE_START_TRAFFIC:
5091                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5092                         if (f_obj->complete_cmd(bp, f_obj,
5093                                                 BNX2X_F_CMD_TX_START))
5094                                 break;
5095                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5096                         goto next_spqe;
5097
5098                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5099                         echo = elem->message.data.function_update_event.echo;
5100                         if (echo == SWITCH_UPDATE) {
5101                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5102                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5103                                 if (f_obj->complete_cmd(
5104                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5105                                         break;
5106
5107                         } else {
5108                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5109                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5110                                 f_obj->complete_cmd(bp, f_obj,
5111                                                     BNX2X_F_CMD_AFEX_UPDATE);
5112
5113                                 /* We will perform the Queues update from
5114                                  * sp_rtnl task as all Queue SP operations
5115                                  * should run under rtnl_lock.
5116                                  */
5117                                 smp_mb__before_clear_bit();
5118                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5119                                         &bp->sp_rtnl_state);
5120                                 smp_mb__after_clear_bit();
5121
5122                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5123                         }
5124
5125                         goto next_spqe;
5126
5127                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5128                         f_obj->complete_cmd(bp, f_obj,
5129                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5130                         bnx2x_after_afex_vif_lists(bp, elem);
5131                         goto next_spqe;
5132                 case EVENT_RING_OPCODE_FUNCTION_START:
5133                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5134                            "got FUNC_START ramrod\n");
5135                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5136                                 break;
5137
5138                         goto next_spqe;
5139
5140                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5141                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5142                            "got FUNC_STOP ramrod\n");
5143                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5144                                 break;
5145
5146                         goto next_spqe;
5147                 }
5148
5149                 switch (opcode | bp->state) {
5150                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5151                       BNX2X_STATE_OPEN):
5152                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5153                       BNX2X_STATE_OPENING_WAIT4_PORT):
5154                         cid = elem->message.data.eth_event.echo &
5155                                 BNX2X_SWCID_MASK;
5156                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5157                            cid);
5158                         rss_raw->clear_pending(rss_raw);
5159                         break;
5160
5161                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5162                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5163                 case (EVENT_RING_OPCODE_SET_MAC |
5164                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5165                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5166                       BNX2X_STATE_OPEN):
5167                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5168                       BNX2X_STATE_DIAG):
5169                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5170                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5171                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5172                         bnx2x_handle_classification_eqe(bp, elem);
5173                         break;
5174
5175                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5176                       BNX2X_STATE_OPEN):
5177                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5178                       BNX2X_STATE_DIAG):
5179                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5180                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5181                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5182                         bnx2x_handle_mcast_eqe(bp);
5183                         break;
5184
5185                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5186                       BNX2X_STATE_OPEN):
5187                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5188                       BNX2X_STATE_DIAG):
5189                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5190                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5191                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5192                         bnx2x_handle_rx_mode_eqe(bp);
5193                         break;
5194                 default:
5195                         /* unknown event log error and continue */
5196                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5197                                   elem->message.opcode, bp->state);
5198                 }
5199 next_spqe:
5200                 spqe_cnt++;
5201         } /* for */
5202
5203         smp_mb__before_atomic_inc();
5204         atomic_add(spqe_cnt, &bp->eq_spq_left);
5205
5206         bp->eq_cons = sw_cons;
5207         bp->eq_prod = sw_prod;
5208         /* Make sure that above mem writes were issued towards the memory */
5209         smp_wmb();
5210
5211         /* update producer */
5212         bnx2x_update_eq_prod(bp, bp->eq_prod);
5213 }
5214
5215 static void bnx2x_sp_task(struct work_struct *work)
5216 {
5217         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5218
5219         DP(BNX2X_MSG_SP, "sp task invoked\n");
5220
5221         /* make sure the atomic interupt_occurred has been written */
5222         smp_rmb();
5223         if (atomic_read(&bp->interrupt_occurred)) {
5224
5225                 /* what work needs to be performed? */
5226                 u16 status = bnx2x_update_dsb_idx(bp);
5227
5228                 DP(BNX2X_MSG_SP, "status %x\n", status);
5229                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5230                 atomic_set(&bp->interrupt_occurred, 0);
5231
5232                 /* HW attentions */
5233                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5234                         bnx2x_attn_int(bp);
5235                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5236                 }
5237
5238                 /* SP events: STAT_QUERY and others */
5239                 if (status & BNX2X_DEF_SB_IDX) {
5240                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5241
5242                 if (FCOE_INIT(bp) &&
5243                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5244                                 /* Prevent local bottom-halves from running as
5245                                  * we are going to change the local NAPI list.
5246                                  */
5247                                 local_bh_disable();
5248                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5249                                 local_bh_enable();
5250                         }
5251
5252                         /* Handle EQ completions */
5253                         bnx2x_eq_int(bp);
5254                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5255                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5256
5257                         status &= ~BNX2X_DEF_SB_IDX;
5258                 }
5259
5260                 /* if status is non zero then perhaps something went wrong */
5261                 if (unlikely(status))
5262                         DP(BNX2X_MSG_SP,
5263                            "got an unknown interrupt! (status 0x%x)\n", status);
5264
5265                 /* ack status block only if something was actually handled */
5266                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5267                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5268
5269         }
5270
5271         /* must be called after the EQ processing (since eq leads to sriov
5272          * ramrod completion flows).
5273          * This flow may have been scheduled by the arrival of a ramrod
5274          * completion, or by the sriov code rescheduling itself.
5275          */
5276         bnx2x_iov_sp_task(bp);
5277
5278         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5279         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5280                                &bp->sp_state)) {
5281                 bnx2x_link_report(bp);
5282                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5283         }
5284 }
5285
5286 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5287 {
5288         struct net_device *dev = dev_instance;
5289         struct bnx2x *bp = netdev_priv(dev);
5290
5291         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5292                      IGU_INT_DISABLE, 0);
5293
5294 #ifdef BNX2X_STOP_ON_ERROR
5295         if (unlikely(bp->panic))
5296                 return IRQ_HANDLED;
5297 #endif
5298
5299         if (CNIC_LOADED(bp)) {
5300                 struct cnic_ops *c_ops;
5301
5302                 rcu_read_lock();
5303                 c_ops = rcu_dereference(bp->cnic_ops);
5304                 if (c_ops)
5305                         c_ops->cnic_handler(bp->cnic_data, NULL);
5306                 rcu_read_unlock();
5307         }
5308
5309         /* schedule sp task to perform default status block work, ack
5310          * attentions and enable interrupts.
5311          */
5312         bnx2x_schedule_sp_task(bp);
5313
5314         return IRQ_HANDLED;
5315 }
5316
5317 /* end of slow path */
5318
5319
5320 void bnx2x_drv_pulse(struct bnx2x *bp)
5321 {
5322         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5323                  bp->fw_drv_pulse_wr_seq);
5324 }
5325
5326 static void bnx2x_timer(unsigned long data)
5327 {
5328         struct bnx2x *bp = (struct bnx2x *) data;
5329
5330         if (!netif_running(bp->dev))
5331                 return;
5332
5333         if (IS_PF(bp) &&
5334             !BP_NOMCP(bp)) {
5335                 int mb_idx = BP_FW_MB_IDX(bp);
5336                 u32 drv_pulse;
5337                 u32 mcp_pulse;
5338
5339                 ++bp->fw_drv_pulse_wr_seq;
5340                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5341                 /* TBD - add SYSTEM_TIME */
5342                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5343                 bnx2x_drv_pulse(bp);
5344
5345                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5346                              MCP_PULSE_SEQ_MASK);
5347                 /* The delta between driver pulse and mcp response
5348                  * should be 1 (before mcp response) or 0 (after mcp response)
5349                  */
5350                 if ((drv_pulse != mcp_pulse) &&
5351                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5352                         /* someone lost a heartbeat... */
5353                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5354                                   drv_pulse, mcp_pulse);
5355                 }
5356         }
5357
5358         if (bp->state == BNX2X_STATE_OPEN)
5359                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5360
5361         /* sample pf vf bulletin board for new posts from pf */
5362         if (IS_VF(bp))
5363                 bnx2x_sample_bulletin(bp);
5364
5365         mod_timer(&bp->timer, jiffies + bp->current_interval);
5366 }
5367
5368 /* end of Statistics */
5369
5370 /* nic init */
5371
5372 /*
5373  * nic init service functions
5374  */
5375
5376 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5377 {
5378         u32 i;
5379         if (!(len%4) && !(addr%4))
5380                 for (i = 0; i < len; i += 4)
5381                         REG_WR(bp, addr + i, fill);
5382         else
5383                 for (i = 0; i < len; i++)
5384                         REG_WR8(bp, addr + i, fill);
5385
5386 }
5387
5388 /* helper: writes FP SP data to FW - data_size in dwords */
5389 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5390                                 int fw_sb_id,
5391                                 u32 *sb_data_p,
5392                                 u32 data_size)
5393 {
5394         int index;
5395         for (index = 0; index < data_size; index++)
5396                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5397                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5398                         sizeof(u32)*index,
5399                         *(sb_data_p + index));
5400 }
5401
5402 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5403 {
5404         u32 *sb_data_p;
5405         u32 data_size = 0;
5406         struct hc_status_block_data_e2 sb_data_e2;
5407         struct hc_status_block_data_e1x sb_data_e1x;
5408
5409         /* disable the function first */
5410         if (!CHIP_IS_E1x(bp)) {
5411                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5412                 sb_data_e2.common.state = SB_DISABLED;
5413                 sb_data_e2.common.p_func.vf_valid = false;
5414                 sb_data_p = (u32 *)&sb_data_e2;
5415                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5416         } else {
5417                 memset(&sb_data_e1x, 0,
5418                        sizeof(struct hc_status_block_data_e1x));
5419                 sb_data_e1x.common.state = SB_DISABLED;
5420                 sb_data_e1x.common.p_func.vf_valid = false;
5421                 sb_data_p = (u32 *)&sb_data_e1x;
5422                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5423         }
5424         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5425
5426         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5427                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5428                         CSTORM_STATUS_BLOCK_SIZE);
5429         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5430                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5431                         CSTORM_SYNC_BLOCK_SIZE);
5432 }
5433
5434 /* helper:  writes SP SB data to FW */
5435 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5436                 struct hc_sp_status_block_data *sp_sb_data)
5437 {
5438         int func = BP_FUNC(bp);
5439         int i;
5440         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5441                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5442                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5443                         i*sizeof(u32),
5444                         *((u32 *)sp_sb_data + i));
5445 }
5446
5447 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5448 {
5449         int func = BP_FUNC(bp);
5450         struct hc_sp_status_block_data sp_sb_data;
5451         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5452
5453         sp_sb_data.state = SB_DISABLED;
5454         sp_sb_data.p_func.vf_valid = false;
5455
5456         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5457
5458         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5459                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5460                         CSTORM_SP_STATUS_BLOCK_SIZE);
5461         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5462                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5463                         CSTORM_SP_SYNC_BLOCK_SIZE);
5464
5465 }
5466
5467
5468 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5469                                            int igu_sb_id, int igu_seg_id)
5470 {
5471         hc_sm->igu_sb_id = igu_sb_id;
5472         hc_sm->igu_seg_id = igu_seg_id;
5473         hc_sm->timer_value = 0xFF;
5474         hc_sm->time_to_expire = 0xFFFFFFFF;
5475 }
5476
5477
5478 /* allocates state machine ids. */
5479 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5480 {
5481         /* zero out state machine indices */
5482         /* rx indices */
5483         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5484
5485         /* tx indices */
5486         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5487         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5488         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5489         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5490
5491         /* map indices */
5492         /* rx indices */
5493         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5494                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5495
5496         /* tx indices */
5497         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5498                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5499         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5500                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5501         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5502                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5503         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5504                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5505 }
5506
5507 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5508                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5509 {
5510         int igu_seg_id;
5511
5512         struct hc_status_block_data_e2 sb_data_e2;
5513         struct hc_status_block_data_e1x sb_data_e1x;
5514         struct hc_status_block_sm  *hc_sm_p;
5515         int data_size;
5516         u32 *sb_data_p;
5517
5518         if (CHIP_INT_MODE_IS_BC(bp))
5519                 igu_seg_id = HC_SEG_ACCESS_NORM;
5520         else
5521                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5522
5523         bnx2x_zero_fp_sb(bp, fw_sb_id);
5524
5525         if (!CHIP_IS_E1x(bp)) {
5526                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5527                 sb_data_e2.common.state = SB_ENABLED;
5528                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5529                 sb_data_e2.common.p_func.vf_id = vfid;
5530                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5531                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5532                 sb_data_e2.common.same_igu_sb_1b = true;
5533                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5534                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5535                 hc_sm_p = sb_data_e2.common.state_machine;
5536                 sb_data_p = (u32 *)&sb_data_e2;
5537                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5538                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5539         } else {
5540                 memset(&sb_data_e1x, 0,
5541                        sizeof(struct hc_status_block_data_e1x));
5542                 sb_data_e1x.common.state = SB_ENABLED;
5543                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5544                 sb_data_e1x.common.p_func.vf_id = 0xff;
5545                 sb_data_e1x.common.p_func.vf_valid = false;
5546                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5547                 sb_data_e1x.common.same_igu_sb_1b = true;
5548                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5549                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5550                 hc_sm_p = sb_data_e1x.common.state_machine;
5551                 sb_data_p = (u32 *)&sb_data_e1x;
5552                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5553                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5554         }
5555
5556         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5557                                        igu_sb_id, igu_seg_id);
5558         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5559                                        igu_sb_id, igu_seg_id);
5560
5561         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5562
5563         /* write indices to HW - PCI guarantees endianity of regpairs */
5564         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5565 }
5566
5567 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5568                                      u16 tx_usec, u16 rx_usec)
5569 {
5570         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5571                                     false, rx_usec);
5572         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5573                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5574                                        tx_usec);
5575         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5576                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5577                                        tx_usec);
5578         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5579                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5580                                        tx_usec);
5581 }
5582
5583 static void bnx2x_init_def_sb(struct bnx2x *bp)
5584 {
5585         struct host_sp_status_block *def_sb = bp->def_status_blk;
5586         dma_addr_t mapping = bp->def_status_blk_mapping;
5587         int igu_sp_sb_index;
5588         int igu_seg_id;
5589         int port = BP_PORT(bp);
5590         int func = BP_FUNC(bp);
5591         int reg_offset, reg_offset_en5;
5592         u64 section;
5593         int index;
5594         struct hc_sp_status_block_data sp_sb_data;
5595         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5596
5597         if (CHIP_INT_MODE_IS_BC(bp)) {
5598                 igu_sp_sb_index = DEF_SB_IGU_ID;
5599                 igu_seg_id = HC_SEG_ACCESS_DEF;
5600         } else {
5601                 igu_sp_sb_index = bp->igu_dsb_id;
5602                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5603         }
5604
5605         /* ATTN */
5606         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5607                                             atten_status_block);
5608         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5609
5610         bp->attn_state = 0;
5611
5612         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5613                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5614         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5615                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5616         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5617                 int sindex;
5618                 /* take care of sig[0]..sig[4] */
5619                 for (sindex = 0; sindex < 4; sindex++)
5620                         bp->attn_group[index].sig[sindex] =
5621                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5622
5623                 if (!CHIP_IS_E1x(bp))
5624                         /*
5625                          * enable5 is separate from the rest of the registers,
5626                          * and therefore the address skip is 4
5627                          * and not 16 between the different groups
5628                          */
5629                         bp->attn_group[index].sig[4] = REG_RD(bp,
5630                                         reg_offset_en5 + 0x4*index);
5631                 else
5632                         bp->attn_group[index].sig[4] = 0;
5633         }
5634
5635         if (bp->common.int_block == INT_BLOCK_HC) {
5636                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5637                                      HC_REG_ATTN_MSG0_ADDR_L);
5638
5639                 REG_WR(bp, reg_offset, U64_LO(section));
5640                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5641         } else if (!CHIP_IS_E1x(bp)) {
5642                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5643                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5644         }
5645
5646         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5647                                             sp_sb);
5648
5649         bnx2x_zero_sp_sb(bp);
5650
5651         /* PCI guarantees endianity of regpairs */
5652         sp_sb_data.state                = SB_ENABLED;
5653         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5654         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5655         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5656         sp_sb_data.igu_seg_id           = igu_seg_id;
5657         sp_sb_data.p_func.pf_id         = func;
5658         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5659         sp_sb_data.p_func.vf_id         = 0xff;
5660
5661         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5662
5663         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5664 }
5665
5666 void bnx2x_update_coalesce(struct bnx2x *bp)
5667 {
5668         int i;
5669
5670         for_each_eth_queue(bp, i)
5671                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5672                                          bp->tx_ticks, bp->rx_ticks);
5673 }
5674
5675 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5676 {
5677         spin_lock_init(&bp->spq_lock);
5678         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5679
5680         bp->spq_prod_idx = 0;
5681         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5682         bp->spq_prod_bd = bp->spq;
5683         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5684 }
5685
5686 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5687 {
5688         int i;
5689         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5690                 union event_ring_elem *elem =
5691                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5692
5693                 elem->next_page.addr.hi =
5694                         cpu_to_le32(U64_HI(bp->eq_mapping +
5695                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5696                 elem->next_page.addr.lo =
5697                         cpu_to_le32(U64_LO(bp->eq_mapping +
5698                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5699         }
5700         bp->eq_cons = 0;
5701         bp->eq_prod = NUM_EQ_DESC;
5702         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5703         /* we want a warning message before it gets rought... */
5704         atomic_set(&bp->eq_spq_left,
5705                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5706 }
5707
5708 /* called with netif_addr_lock_bh() */
5709 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5710                         unsigned long rx_mode_flags,
5711                         unsigned long rx_accept_flags,
5712                         unsigned long tx_accept_flags,
5713                         unsigned long ramrod_flags)
5714 {
5715         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5716         int rc;
5717
5718         memset(&ramrod_param, 0, sizeof(ramrod_param));
5719
5720         /* Prepare ramrod parameters */
5721         ramrod_param.cid = 0;
5722         ramrod_param.cl_id = cl_id;
5723         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5724         ramrod_param.func_id = BP_FUNC(bp);
5725
5726         ramrod_param.pstate = &bp->sp_state;
5727         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5728
5729         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5730         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5731
5732         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5733
5734         ramrod_param.ramrod_flags = ramrod_flags;
5735         ramrod_param.rx_mode_flags = rx_mode_flags;
5736
5737         ramrod_param.rx_accept_flags = rx_accept_flags;
5738         ramrod_param.tx_accept_flags = tx_accept_flags;
5739
5740         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5741         if (rc < 0) {
5742                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5743                 return rc;
5744         }
5745
5746         return 0;
5747 }
5748
5749 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5750                                    unsigned long *rx_accept_flags,
5751                                    unsigned long *tx_accept_flags)
5752 {
5753         /* Clear the flags first */
5754         *rx_accept_flags = 0;
5755         *tx_accept_flags = 0;
5756
5757         switch (rx_mode) {
5758         case BNX2X_RX_MODE_NONE:
5759                 /*
5760                  * 'drop all' supersedes any accept flags that may have been
5761                  * passed to the function.
5762                  */
5763                 break;
5764         case BNX2X_RX_MODE_NORMAL:
5765                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5766                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5767                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5768
5769                 /* internal switching mode */
5770                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5771                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5772                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5773
5774                 break;
5775         case BNX2X_RX_MODE_ALLMULTI:
5776                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5777                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5778                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5779
5780                 /* internal switching mode */
5781                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5782                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5783                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5784
5785                 break;
5786         case BNX2X_RX_MODE_PROMISC:
5787                 /* According to deffinition of SI mode, iface in promisc mode
5788                  * should receive matched and unmatched (in resolution of port)
5789                  * unicast packets.
5790                  */
5791                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5792                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5793                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5794                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5795
5796                 /* internal switching mode */
5797                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5798                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5799
5800                 if (IS_MF_SI(bp))
5801                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5802                 else
5803                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5804
5805                 break;
5806         default:
5807                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5808                 return -EINVAL;
5809         }
5810
5811         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5812         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5813                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5814                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5815         }
5816
5817         return 0;
5818 }
5819
5820 /* called with netif_addr_lock_bh() */
5821 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5822 {
5823         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5824         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5825         int rc;
5826
5827         if (!NO_FCOE(bp))
5828                 /* Configure rx_mode of FCoE Queue */
5829                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5830
5831         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5832                                      &tx_accept_flags);
5833         if (rc)
5834                 return rc;
5835
5836         __set_bit(RAMROD_RX, &ramrod_flags);
5837         __set_bit(RAMROD_TX, &ramrod_flags);
5838
5839         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5840                                    rx_accept_flags, tx_accept_flags,
5841                                    ramrod_flags);
5842 }
5843
5844 static void bnx2x_init_internal_common(struct bnx2x *bp)
5845 {
5846         int i;
5847
5848         if (IS_MF_SI(bp))
5849                 /*
5850                  * In switch independent mode, the TSTORM needs to accept
5851                  * packets that failed classification, since approximate match
5852                  * mac addresses aren't written to NIG LLH
5853                  */
5854                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5855                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5856         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5857                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5858                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5859
5860         /* Zero this manually as its initialization is
5861            currently missing in the initTool */
5862         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5863                 REG_WR(bp, BAR_USTRORM_INTMEM +
5864                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
5865         if (!CHIP_IS_E1x(bp)) {
5866                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5867                         CHIP_INT_MODE_IS_BC(bp) ?
5868                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5869         }
5870 }
5871
5872 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5873 {
5874         switch (load_code) {
5875         case FW_MSG_CODE_DRV_LOAD_COMMON:
5876         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5877                 bnx2x_init_internal_common(bp);
5878                 /* no break */
5879
5880         case FW_MSG_CODE_DRV_LOAD_PORT:
5881                 /* nothing to do */
5882                 /* no break */
5883
5884         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5885                 /* internal memory per function is
5886                    initialized inside bnx2x_pf_init */
5887                 break;
5888
5889         default:
5890                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5891                 break;
5892         }
5893 }
5894
5895 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5896 {
5897         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5898 }
5899
5900 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5901 {
5902         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5903 }
5904
5905 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5906 {
5907         if (CHIP_IS_E1x(fp->bp))
5908                 return BP_L_ID(fp->bp) + fp->index;
5909         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
5910                 return bnx2x_fp_igu_sb_id(fp);
5911 }
5912
5913 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5914 {
5915         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5916         u8 cos;
5917         unsigned long q_type = 0;
5918         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5919         fp->rx_queue = fp_idx;
5920         fp->cid = fp_idx;
5921         fp->cl_id = bnx2x_fp_cl_id(fp);
5922         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5923         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5924         /* qZone id equals to FW (per path) client id */
5925         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
5926
5927         /* init shortcut */
5928         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5929
5930         /* Setup SB indicies */
5931         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5932
5933         /* Configure Queue State object */
5934         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5935         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5936
5937         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5938
5939         /* init tx data */
5940         for_each_cos_in_tx_queue(fp, cos) {
5941                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5942                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5943                                   FP_COS_TO_TXQ(fp, cos, bp),
5944                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
5945                 cids[cos] = fp->txdata_ptr[cos]->cid;
5946         }
5947
5948         /* nothing more for vf to do here */
5949         if (IS_VF(bp))
5950                 return;
5951
5952         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5953                       fp->fw_sb_id, fp->igu_sb_id);
5954         bnx2x_update_fpsb_idx(fp);
5955         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5956                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5957                              bnx2x_sp_mapping(bp, q_rdata), q_type);
5958
5959         /**
5960          * Configure classification DBs: Always enable Tx switching
5961          */
5962         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5963
5964         DP(NETIF_MSG_IFUP,
5965            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
5966            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5967            fp->igu_sb_id);
5968 }
5969
5970 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5971 {
5972         int i;
5973
5974         for (i = 1; i <= NUM_TX_RINGS; i++) {
5975                 struct eth_tx_next_bd *tx_next_bd =
5976                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5977
5978                 tx_next_bd->addr_hi =
5979                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5980                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5981                 tx_next_bd->addr_lo =
5982                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5983                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5984         }
5985
5986         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5987         txdata->tx_db.data.zero_fill1 = 0;
5988         txdata->tx_db.data.prod = 0;
5989
5990         txdata->tx_pkt_prod = 0;
5991         txdata->tx_pkt_cons = 0;
5992         txdata->tx_bd_prod = 0;
5993         txdata->tx_bd_cons = 0;
5994         txdata->tx_pkt = 0;
5995 }
5996
5997 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5998 {
5999         int i;
6000
6001         for_each_tx_queue_cnic(bp, i)
6002                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6003 }
6004 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6005 {
6006         int i;
6007         u8 cos;
6008
6009         for_each_eth_queue(bp, i)
6010                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6011                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6012 }
6013
6014 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6015 {
6016         if (!NO_FCOE(bp))
6017                 bnx2x_init_fcoe_fp(bp);
6018
6019         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6020                       BNX2X_VF_ID_INVALID, false,
6021                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6022
6023         /* ensure status block indices were read */
6024         rmb();
6025         bnx2x_init_rx_rings_cnic(bp);
6026         bnx2x_init_tx_rings_cnic(bp);
6027
6028         /* flush all */
6029         mb();
6030         mmiowb();
6031 }
6032
6033 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
6034 {
6035         int i;
6036
6037         for_each_eth_queue(bp, i)
6038                 bnx2x_init_eth_fp(bp, i);
6039
6040         /* ensure status block indices were read */
6041         rmb();
6042         bnx2x_init_rx_rings(bp);
6043         bnx2x_init_tx_rings(bp);
6044
6045         if (IS_VF(bp))
6046                 return;
6047
6048         /* Initialize MOD_ABS interrupts */
6049         bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6050                                bp->common.shmem_base, bp->common.shmem2_base,
6051                                BP_PORT(bp));
6052
6053         bnx2x_init_def_sb(bp);
6054         bnx2x_update_dsb_idx(bp);
6055         bnx2x_init_sp_ring(bp);
6056         bnx2x_init_eq_ring(bp);
6057         bnx2x_init_internal(bp, load_code);
6058         bnx2x_pf_init(bp);
6059         bnx2x_stats_init(bp);
6060
6061         /* flush all before enabling interrupts */
6062         mb();
6063         mmiowb();
6064
6065         bnx2x_int_enable(bp);
6066
6067         /* Check for SPIO5 */
6068         bnx2x_attn_int_deasserted0(bp,
6069                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6070                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6071 }
6072
6073 /* end of nic init */
6074
6075 /*
6076  * gzip service functions
6077  */
6078
6079 static int bnx2x_gunzip_init(struct bnx2x *bp)
6080 {
6081         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6082                                             &bp->gunzip_mapping, GFP_KERNEL);
6083         if (bp->gunzip_buf  == NULL)
6084                 goto gunzip_nomem1;
6085
6086         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6087         if (bp->strm  == NULL)
6088                 goto gunzip_nomem2;
6089
6090         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6091         if (bp->strm->workspace == NULL)
6092                 goto gunzip_nomem3;
6093
6094         return 0;
6095
6096 gunzip_nomem3:
6097         kfree(bp->strm);
6098         bp->strm = NULL;
6099
6100 gunzip_nomem2:
6101         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6102                           bp->gunzip_mapping);
6103         bp->gunzip_buf = NULL;
6104
6105 gunzip_nomem1:
6106         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6107         return -ENOMEM;
6108 }
6109
6110 static void bnx2x_gunzip_end(struct bnx2x *bp)
6111 {
6112         if (bp->strm) {
6113                 vfree(bp->strm->workspace);
6114                 kfree(bp->strm);
6115                 bp->strm = NULL;
6116         }
6117
6118         if (bp->gunzip_buf) {
6119                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6120                                   bp->gunzip_mapping);
6121                 bp->gunzip_buf = NULL;
6122         }
6123 }
6124
6125 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6126 {
6127         int n, rc;
6128
6129         /* check gzip header */
6130         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6131                 BNX2X_ERR("Bad gzip header\n");
6132                 return -EINVAL;
6133         }
6134
6135         n = 10;
6136
6137 #define FNAME                           0x8
6138
6139         if (zbuf[3] & FNAME)
6140                 while ((zbuf[n++] != 0) && (n < len));
6141
6142         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6143         bp->strm->avail_in = len - n;
6144         bp->strm->next_out = bp->gunzip_buf;
6145         bp->strm->avail_out = FW_BUF_SIZE;
6146
6147         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6148         if (rc != Z_OK)
6149                 return rc;
6150
6151         rc = zlib_inflate(bp->strm, Z_FINISH);
6152         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6153                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6154                            bp->strm->msg);
6155
6156         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6157         if (bp->gunzip_outlen & 0x3)
6158                 netdev_err(bp->dev,
6159                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6160                                 bp->gunzip_outlen);
6161         bp->gunzip_outlen >>= 2;
6162
6163         zlib_inflateEnd(bp->strm);
6164
6165         if (rc == Z_STREAM_END)
6166                 return 0;
6167
6168         return rc;
6169 }
6170
6171 /* nic load/unload */
6172
6173 /*
6174  * General service functions
6175  */
6176
6177 /* send a NIG loopback debug packet */
6178 static void bnx2x_lb_pckt(struct bnx2x *bp)
6179 {
6180         u32 wb_write[3];
6181
6182         /* Ethernet source and destination addresses */
6183         wb_write[0] = 0x55555555;
6184         wb_write[1] = 0x55555555;
6185         wb_write[2] = 0x20;             /* SOP */
6186         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6187
6188         /* NON-IP protocol */
6189         wb_write[0] = 0x09000000;
6190         wb_write[1] = 0x55555555;
6191         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6192         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6193 }
6194
6195 /* some of the internal memories
6196  * are not directly readable from the driver
6197  * to test them we send debug packets
6198  */
6199 static int bnx2x_int_mem_test(struct bnx2x *bp)
6200 {
6201         int factor;
6202         int count, i;
6203         u32 val = 0;
6204
6205         if (CHIP_REV_IS_FPGA(bp))
6206                 factor = 120;
6207         else if (CHIP_REV_IS_EMUL(bp))
6208                 factor = 200;
6209         else
6210                 factor = 1;
6211
6212         /* Disable inputs of parser neighbor blocks */
6213         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6214         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6215         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6216         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6217
6218         /*  Write 0 to parser credits for CFC search request */
6219         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6220
6221         /* send Ethernet packet */
6222         bnx2x_lb_pckt(bp);
6223
6224         /* TODO do i reset NIG statistic? */
6225         /* Wait until NIG register shows 1 packet of size 0x10 */
6226         count = 1000 * factor;
6227         while (count) {
6228
6229                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6230                 val = *bnx2x_sp(bp, wb_data[0]);
6231                 if (val == 0x10)
6232                         break;
6233
6234                 msleep(10);
6235                 count--;
6236         }
6237         if (val != 0x10) {
6238                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6239                 return -1;
6240         }
6241
6242         /* Wait until PRS register shows 1 packet */
6243         count = 1000 * factor;
6244         while (count) {
6245                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6246                 if (val == 1)
6247                         break;
6248
6249                 msleep(10);
6250                 count--;
6251         }
6252         if (val != 0x1) {
6253                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6254                 return -2;
6255         }
6256
6257         /* Reset and init BRB, PRS */
6258         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6259         msleep(50);
6260         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6261         msleep(50);
6262         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6263         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6264
6265         DP(NETIF_MSG_HW, "part2\n");
6266
6267         /* Disable inputs of parser neighbor blocks */
6268         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6269         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6270         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6271         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6272
6273         /* Write 0 to parser credits for CFC search request */
6274         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6275
6276         /* send 10 Ethernet packets */
6277         for (i = 0; i < 10; i++)
6278                 bnx2x_lb_pckt(bp);
6279
6280         /* Wait until NIG register shows 10 + 1
6281            packets of size 11*0x10 = 0xb0 */
6282         count = 1000 * factor;
6283         while (count) {
6284
6285                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6286                 val = *bnx2x_sp(bp, wb_data[0]);
6287                 if (val == 0xb0)
6288                         break;
6289
6290                 msleep(10);
6291                 count--;
6292         }
6293         if (val != 0xb0) {
6294                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6295                 return -3;
6296         }
6297
6298         /* Wait until PRS register shows 2 packets */
6299         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6300         if (val != 2)
6301                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6302
6303         /* Write 1 to parser credits for CFC search request */
6304         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6305
6306         /* Wait until PRS register shows 3 packets */
6307         msleep(10 * factor);
6308         /* Wait until NIG register shows 1 packet of size 0x10 */
6309         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6310         if (val != 3)
6311                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6312
6313         /* clear NIG EOP FIFO */
6314         for (i = 0; i < 11; i++)
6315                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6316         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6317         if (val != 1) {
6318                 BNX2X_ERR("clear of NIG failed\n");
6319                 return -4;
6320         }
6321
6322         /* Reset and init BRB, PRS, NIG */
6323         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6324         msleep(50);
6325         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6326         msleep(50);
6327         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6328         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6329         if (!CNIC_SUPPORT(bp))
6330                 /* set NIC mode */
6331                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6332
6333         /* Enable inputs of parser neighbor blocks */
6334         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6335         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6336         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6337         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6338
6339         DP(NETIF_MSG_HW, "done\n");
6340
6341         return 0; /* OK */
6342 }
6343
6344 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6345 {
6346         u32 val;
6347
6348         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6349         if (!CHIP_IS_E1x(bp))
6350                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6351         else
6352                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6353         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6354         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6355         /*
6356          * mask read length error interrupts in brb for parser
6357          * (parsing unit and 'checksum and crc' unit)
6358          * these errors are legal (PU reads fixed length and CAC can cause
6359          * read length error on truncated packets)
6360          */
6361         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6362         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6363         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6364         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6365         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6366         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6367 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6368 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6369         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6370         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6371         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6372 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6373 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6374         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6375         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6376         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6377         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6378 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6379 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6380
6381         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6382                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6383                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6384         if (!CHIP_IS_E1x(bp))
6385                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6386                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6387         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6388
6389         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6390         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6391         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6392 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6393
6394         if (!CHIP_IS_E1x(bp))
6395                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6396                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6397
6398         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6399         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6400 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6401         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6402 }
6403
6404 static void bnx2x_reset_common(struct bnx2x *bp)
6405 {
6406         u32 val = 0x1400;
6407
6408         /* reset_common */
6409         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6410                0xd3ffff7f);
6411
6412         if (CHIP_IS_E3(bp)) {
6413                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6414                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6415         }
6416
6417         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6418 }
6419
6420 static void bnx2x_setup_dmae(struct bnx2x *bp)
6421 {
6422         bp->dmae_ready = 0;
6423         spin_lock_init(&bp->dmae_lock);
6424 }
6425
6426 static void bnx2x_init_pxp(struct bnx2x *bp)
6427 {
6428         u16 devctl;
6429         int r_order, w_order;
6430
6431         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6432         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6433         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6434         if (bp->mrrs == -1)
6435                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6436         else {
6437                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6438                 r_order = bp->mrrs;
6439         }
6440
6441         bnx2x_init_pxp_arb(bp, r_order, w_order);
6442 }
6443
6444 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6445 {
6446         int is_required;
6447         u32 val;
6448         int port;
6449
6450         if (BP_NOMCP(bp))
6451                 return;
6452
6453         is_required = 0;
6454         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6455               SHARED_HW_CFG_FAN_FAILURE_MASK;
6456
6457         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6458                 is_required = 1;
6459
6460         /*
6461          * The fan failure mechanism is usually related to the PHY type since
6462          * the power consumption of the board is affected by the PHY. Currently,
6463          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6464          */
6465         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6466                 for (port = PORT_0; port < PORT_MAX; port++) {
6467                         is_required |=
6468                                 bnx2x_fan_failure_det_req(
6469                                         bp,
6470                                         bp->common.shmem_base,
6471                                         bp->common.shmem2_base,
6472                                         port);
6473                 }
6474
6475         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6476
6477         if (is_required == 0)
6478                 return;
6479
6480         /* Fan failure is indicated by SPIO 5 */
6481         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6482
6483         /* set to active low mode */
6484         val = REG_RD(bp, MISC_REG_SPIO_INT);
6485         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6486         REG_WR(bp, MISC_REG_SPIO_INT, val);
6487
6488         /* enable interrupt to signal the IGU */
6489         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6490         val |= MISC_SPIO_SPIO5;
6491         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6492 }
6493
6494 void bnx2x_pf_disable(struct bnx2x *bp)
6495 {
6496         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6497         val &= ~IGU_PF_CONF_FUNC_EN;
6498
6499         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6500         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6501         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6502 }
6503
6504 static void bnx2x__common_init_phy(struct bnx2x *bp)
6505 {
6506         u32 shmem_base[2], shmem2_base[2];
6507         /* Avoid common init in case MFW supports LFA */
6508         if (SHMEM2_RD(bp, size) >
6509             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6510                 return;
6511         shmem_base[0] =  bp->common.shmem_base;
6512         shmem2_base[0] = bp->common.shmem2_base;
6513         if (!CHIP_IS_E1x(bp)) {
6514                 shmem_base[1] =
6515                         SHMEM2_RD(bp, other_shmem_base_addr);
6516                 shmem2_base[1] =
6517                         SHMEM2_RD(bp, other_shmem2_base_addr);
6518         }
6519         bnx2x_acquire_phy_lock(bp);
6520         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6521                               bp->common.chip_id);
6522         bnx2x_release_phy_lock(bp);
6523 }
6524
6525 /**
6526  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6527  *
6528  * @bp:         driver handle
6529  */
6530 static int bnx2x_init_hw_common(struct bnx2x *bp)
6531 {
6532         u32 val;
6533
6534         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6535
6536         /*
6537          * take the RESET lock to protect undi_unload flow from accessing
6538          * registers while we're resetting the chip
6539          */
6540         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6541
6542         bnx2x_reset_common(bp);
6543         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6544
6545         val = 0xfffc;
6546         if (CHIP_IS_E3(bp)) {
6547                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6548                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6549         }
6550         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6551
6552         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6553
6554         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6555
6556         if (!CHIP_IS_E1x(bp)) {
6557                 u8 abs_func_id;
6558
6559                 /**
6560                  * 4-port mode or 2-port mode we need to turn of master-enable
6561                  * for everyone, after that, turn it back on for self.
6562                  * so, we disregard multi-function or not, and always disable
6563                  * for all functions on the given path, this means 0,2,4,6 for
6564                  * path 0 and 1,3,5,7 for path 1
6565                  */
6566                 for (abs_func_id = BP_PATH(bp);
6567                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6568                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6569                                 REG_WR(bp,
6570                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6571                                     1);
6572                                 continue;
6573                         }
6574
6575                         bnx2x_pretend_func(bp, abs_func_id);
6576                         /* clear pf enable */
6577                         bnx2x_pf_disable(bp);
6578                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6579                 }
6580         }
6581
6582         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6583         if (CHIP_IS_E1(bp)) {
6584                 /* enable HW interrupt from PXP on USDM overflow
6585                    bit 16 on INT_MASK_0 */
6586                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6587         }
6588
6589         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6590         bnx2x_init_pxp(bp);
6591
6592 #ifdef __BIG_ENDIAN
6593         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6594         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6595         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6596         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6597         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6598         /* make sure this value is 0 */
6599         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6600
6601 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6602         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6603         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6604         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6605         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6606 #endif
6607
6608         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6609
6610         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6611                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6612
6613         /* let the HW do it's magic ... */
6614         msleep(100);
6615         /* finish PXP init */
6616         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6617         if (val != 1) {
6618                 BNX2X_ERR("PXP2 CFG failed\n");
6619                 return -EBUSY;
6620         }
6621         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6622         if (val != 1) {
6623                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6624                 return -EBUSY;
6625         }
6626
6627         /* Timers bug workaround E2 only. We need to set the entire ILT to
6628          * have entries with value "0" and valid bit on.
6629          * This needs to be done by the first PF that is loaded in a path
6630          * (i.e. common phase)
6631          */
6632         if (!CHIP_IS_E1x(bp)) {
6633 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6634  * (i.e. vnic3) to start even if it is marked as "scan-off".
6635  * This occurs when a different function (func2,3) is being marked
6636  * as "scan-off". Real-life scenario for example: if a driver is being
6637  * load-unloaded while func6,7 are down. This will cause the timer to access
6638  * the ilt, translate to a logical address and send a request to read/write.
6639  * Since the ilt for the function that is down is not valid, this will cause
6640  * a translation error which is unrecoverable.
6641  * The Workaround is intended to make sure that when this happens nothing fatal
6642  * will occur. The workaround:
6643  *      1.  First PF driver which loads on a path will:
6644  *              a.  After taking the chip out of reset, by using pretend,
6645  *                  it will write "0" to the following registers of
6646  *                  the other vnics.
6647  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6648  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6649  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6650  *                  And for itself it will write '1' to
6651  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6652  *                  dmae-operations (writing to pram for example.)
6653  *                  note: can be done for only function 6,7 but cleaner this
6654  *                        way.
6655  *              b.  Write zero+valid to the entire ILT.
6656  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6657  *                  VNIC3 (of that port). The range allocated will be the
6658  *                  entire ILT. This is needed to prevent  ILT range error.
6659  *      2.  Any PF driver load flow:
6660  *              a.  ILT update with the physical addresses of the allocated
6661  *                  logical pages.
6662  *              b.  Wait 20msec. - note that this timeout is needed to make
6663  *                  sure there are no requests in one of the PXP internal
6664  *                  queues with "old" ILT addresses.
6665  *              c.  PF enable in the PGLC.
6666  *              d.  Clear the was_error of the PF in the PGLC. (could have
6667  *                  occurred while driver was down)
6668  *              e.  PF enable in the CFC (WEAK + STRONG)
6669  *              f.  Timers scan enable
6670  *      3.  PF driver unload flow:
6671  *              a.  Clear the Timers scan_en.
6672  *              b.  Polling for scan_on=0 for that PF.
6673  *              c.  Clear the PF enable bit in the PXP.
6674  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6675  *              e.  Write zero+valid to all ILT entries (The valid bit must
6676  *                  stay set)
6677  *              f.  If this is VNIC 3 of a port then also init
6678  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6679  *                  to the last enrty in the ILT.
6680  *
6681  *      Notes:
6682  *      Currently the PF error in the PGLC is non recoverable.
6683  *      In the future the there will be a recovery routine for this error.
6684  *      Currently attention is masked.
6685  *      Having an MCP lock on the load/unload process does not guarantee that
6686  *      there is no Timer disable during Func6/7 enable. This is because the
6687  *      Timers scan is currently being cleared by the MCP on FLR.
6688  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6689  *      there is error before clearing it. But the flow above is simpler and
6690  *      more general.
6691  *      All ILT entries are written by zero+valid and not just PF6/7
6692  *      ILT entries since in the future the ILT entries allocation for
6693  *      PF-s might be dynamic.
6694  */
6695                 struct ilt_client_info ilt_cli;
6696                 struct bnx2x_ilt ilt;
6697                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6698                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6699
6700                 /* initialize dummy TM client */
6701                 ilt_cli.start = 0;
6702                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6703                 ilt_cli.client_num = ILT_CLIENT_TM;
6704
6705                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6706                  * Step 2: set the timers first/last ilt entry to point
6707                  * to the entire range to prevent ILT range error for 3rd/4th
6708                  * vnic (this code assumes existence of the vnic)
6709                  *
6710                  * both steps performed by call to bnx2x_ilt_client_init_op()
6711                  * with dummy TM client
6712                  *
6713                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6714                  * and his brother are split registers
6715                  */
6716                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6717                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6718                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6719
6720                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6721                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6722                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6723         }
6724
6725         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6726         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6727
6728         if (!CHIP_IS_E1x(bp)) {
6729                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6730                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6731                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6732
6733                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6734
6735                 /* let the HW do it's magic ... */
6736                 do {
6737                         msleep(200);
6738                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6739                 } while (factor-- && (val != 1));
6740
6741                 if (val != 1) {
6742                         BNX2X_ERR("ATC_INIT failed\n");
6743                         return -EBUSY;
6744                 }
6745         }
6746
6747         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6748
6749         bnx2x_iov_init_dmae(bp);
6750
6751         /* clean the DMAE memory */
6752         bp->dmae_ready = 1;
6753         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6754
6755         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6756
6757         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6758
6759         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6760
6761         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6762
6763         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6764         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6765         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6766         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6767
6768         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6769
6770
6771         /* QM queues pointers table */
6772         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6773
6774         /* soft reset pulse */
6775         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6776         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6777
6778         if (CNIC_SUPPORT(bp))
6779                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6780
6781         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6782         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6783         if (!CHIP_REV_IS_SLOW(bp))
6784                 /* enable hw interrupt from doorbell Q */
6785                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6786
6787         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6788
6789         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6790         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6791
6792         if (!CHIP_IS_E1(bp))
6793                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6794
6795         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6796                 if (IS_MF_AFEX(bp)) {
6797                         /* configure that VNTag and VLAN headers must be
6798                          * received in afex mode
6799                          */
6800                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6801                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6802                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6803                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6804                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6805                 } else {
6806                         /* Bit-map indicating which L2 hdrs may appear
6807                          * after the basic Ethernet header
6808                          */
6809                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6810                                bp->path_has_ovlan ? 7 : 6);
6811                 }
6812         }
6813
6814         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6815         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6816         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6817         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6818
6819         if (!CHIP_IS_E1x(bp)) {
6820                 /* reset VFC memories */
6821                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6822                            VFC_MEMORIES_RST_REG_CAM_RST |
6823                            VFC_MEMORIES_RST_REG_RAM_RST);
6824                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6825                            VFC_MEMORIES_RST_REG_CAM_RST |
6826                            VFC_MEMORIES_RST_REG_RAM_RST);
6827
6828                 msleep(20);
6829         }
6830
6831         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6832         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6833         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6834         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6835
6836         /* sync semi rtc */
6837         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6838                0x80000000);
6839         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6840                0x80000000);
6841
6842         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6843         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6844         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6845
6846         if (!CHIP_IS_E1x(bp)) {
6847                 if (IS_MF_AFEX(bp)) {
6848                         /* configure that VNTag and VLAN headers must be
6849                          * sent in afex mode
6850                          */
6851                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6852                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6853                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6854                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6855                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6856                 } else {
6857                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6858                                bp->path_has_ovlan ? 7 : 6);
6859                 }
6860         }
6861
6862         REG_WR(bp, SRC_REG_SOFT_RST, 1);
6863
6864         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6865
6866         if (CNIC_SUPPORT(bp)) {
6867                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6868                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6869                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6870                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6871                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6872                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6873                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6874                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6875                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6876                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6877         }
6878         REG_WR(bp, SRC_REG_SOFT_RST, 0);
6879
6880         if (sizeof(union cdu_context) != 1024)
6881                 /* we currently assume that a context is 1024 bytes */
6882                 dev_alert(&bp->pdev->dev,
6883                           "please adjust the size of cdu_context(%ld)\n",
6884                           (long)sizeof(union cdu_context));
6885
6886         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6887         val = (4 << 24) + (0 << 12) + 1024;
6888         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6889
6890         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6891         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6892         /* enable context validation interrupt from CFC */
6893         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6894
6895         /* set the thresholds to prevent CFC/CDU race */
6896         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6897
6898         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6899
6900         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6901                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6902
6903         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6904         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6905
6906         /* Reset PCIE errors for debug */
6907         REG_WR(bp, 0x2814, 0xffffffff);
6908         REG_WR(bp, 0x3820, 0xffffffff);
6909
6910         if (!CHIP_IS_E1x(bp)) {
6911                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6912                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6913                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6914                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6915                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6916                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6917                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6918                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6919                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6920                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6921                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6922         }
6923
6924         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6925         if (!CHIP_IS_E1(bp)) {
6926                 /* in E3 this done in per-port section */
6927                 if (!CHIP_IS_E3(bp))
6928                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6929         }
6930         if (CHIP_IS_E1H(bp))
6931                 /* not applicable for E2 (and above ...) */
6932                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6933
6934         if (CHIP_REV_IS_SLOW(bp))
6935                 msleep(200);
6936
6937         /* finish CFC init */
6938         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6939         if (val != 1) {
6940                 BNX2X_ERR("CFC LL_INIT failed\n");
6941                 return -EBUSY;
6942         }
6943         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6944         if (val != 1) {
6945                 BNX2X_ERR("CFC AC_INIT failed\n");
6946                 return -EBUSY;
6947         }
6948         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6949         if (val != 1) {
6950                 BNX2X_ERR("CFC CAM_INIT failed\n");
6951                 return -EBUSY;
6952         }
6953         REG_WR(bp, CFC_REG_DEBUG0, 0);
6954
6955         if (CHIP_IS_E1(bp)) {
6956                 /* read NIG statistic
6957                    to see if this is our first up since powerup */
6958                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6959                 val = *bnx2x_sp(bp, wb_data[0]);
6960
6961                 /* do internal memory self test */
6962                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6963                         BNX2X_ERR("internal mem self test failed\n");
6964                         return -EBUSY;
6965                 }
6966         }
6967
6968         bnx2x_setup_fan_failure_detection(bp);
6969
6970         /* clear PXP2 attentions */
6971         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6972
6973         bnx2x_enable_blocks_attention(bp);
6974         bnx2x_enable_blocks_parity(bp);
6975
6976         if (!BP_NOMCP(bp)) {
6977                 if (CHIP_IS_E1x(bp))
6978                         bnx2x__common_init_phy(bp);
6979         } else
6980                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6981
6982         return 0;
6983 }
6984
6985 /**
6986  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6987  *
6988  * @bp:         driver handle
6989  */
6990 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6991 {
6992         int rc = bnx2x_init_hw_common(bp);
6993
6994         if (rc)
6995                 return rc;
6996
6997         /* In E2 2-PORT mode, same ext phy is used for the two paths */
6998         if (!BP_NOMCP(bp))
6999                 bnx2x__common_init_phy(bp);
7000
7001         return 0;
7002 }
7003
7004 static int bnx2x_init_hw_port(struct bnx2x *bp)
7005 {
7006         int port = BP_PORT(bp);
7007         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7008         u32 low, high;
7009         u32 val;
7010
7011
7012         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7013
7014         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7015
7016         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7017         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7018         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7019
7020         /* Timers bug workaround: disables the pf_master bit in pglue at
7021          * common phase, we need to enable it here before any dmae access are
7022          * attempted. Therefore we manually added the enable-master to the
7023          * port phase (it also happens in the function phase)
7024          */
7025         if (!CHIP_IS_E1x(bp))
7026                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7027
7028         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7029         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7030         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7031         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7032
7033         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7034         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7035         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7036         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7037
7038         /* QM cid (connection) count */
7039         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7040
7041         if (CNIC_SUPPORT(bp)) {
7042                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7043                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7044                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7045         }
7046
7047         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7048
7049         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7050
7051         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7052
7053                 if (IS_MF(bp))
7054                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7055                 else if (bp->dev->mtu > 4096) {
7056                         if (bp->flags & ONE_PORT_FLAG)
7057                                 low = 160;
7058                         else {
7059                                 val = bp->dev->mtu;
7060                                 /* (24*1024 + val*4)/256 */
7061                                 low = 96 + (val/64) +
7062                                                 ((val % 64) ? 1 : 0);
7063                         }
7064                 } else
7065                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7066                 high = low + 56;        /* 14*1024/256 */
7067                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7068                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7069         }
7070
7071         if (CHIP_MODE_IS_4_PORT(bp))
7072                 REG_WR(bp, (BP_PORT(bp) ?
7073                             BRB1_REG_MAC_GUARANTIED_1 :
7074                             BRB1_REG_MAC_GUARANTIED_0), 40);
7075
7076
7077         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7078         if (CHIP_IS_E3B0(bp)) {
7079                 if (IS_MF_AFEX(bp)) {
7080                         /* configure headers for AFEX mode */
7081                         REG_WR(bp, BP_PORT(bp) ?
7082                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7083                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7084                         REG_WR(bp, BP_PORT(bp) ?
7085                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7086                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7087                         REG_WR(bp, BP_PORT(bp) ?
7088                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7089                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7090                 } else {
7091                         /* Ovlan exists only if we are in multi-function +
7092                          * switch-dependent mode, in switch-independent there
7093                          * is no ovlan headers
7094                          */
7095                         REG_WR(bp, BP_PORT(bp) ?
7096                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7097                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7098                                (bp->path_has_ovlan ? 7 : 6));
7099                 }
7100         }
7101
7102         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7103         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7104         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7105         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7106
7107         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7108         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7109         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7110         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7111
7112         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7113         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7114
7115         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7116
7117         if (CHIP_IS_E1x(bp)) {
7118                 /* configure PBF to work without PAUSE mtu 9000 */
7119                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7120
7121                 /* update threshold */
7122                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7123                 /* update init credit */
7124                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7125
7126                 /* probe changes */
7127                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7128                 udelay(50);
7129                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7130         }
7131
7132         if (CNIC_SUPPORT(bp))
7133                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7134
7135         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7136         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7137
7138         if (CHIP_IS_E1(bp)) {
7139                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7140                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7141         }
7142         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7143
7144         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7145
7146         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7147         /* init aeu_mask_attn_func_0/1:
7148          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
7149          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
7150          *             bits 4-7 are used for "per vn group attention" */
7151         val = IS_MF(bp) ? 0xF7 : 0x7;
7152         /* Enable DCBX attention for all but E1 */
7153         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7154         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7155
7156         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7157
7158         if (!CHIP_IS_E1x(bp)) {
7159                 /* Bit-map indicating which L2 hdrs may appear after the
7160                  * basic Ethernet header
7161                  */
7162                 if (IS_MF_AFEX(bp))
7163                         REG_WR(bp, BP_PORT(bp) ?
7164                                NIG_REG_P1_HDRS_AFTER_BASIC :
7165                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7166                 else
7167                         REG_WR(bp, BP_PORT(bp) ?
7168                                NIG_REG_P1_HDRS_AFTER_BASIC :
7169                                NIG_REG_P0_HDRS_AFTER_BASIC,
7170                                IS_MF_SD(bp) ? 7 : 6);
7171
7172                 if (CHIP_IS_E3(bp))
7173                         REG_WR(bp, BP_PORT(bp) ?
7174                                    NIG_REG_LLH1_MF_MODE :
7175                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7176         }
7177         if (!CHIP_IS_E3(bp))
7178                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7179
7180         if (!CHIP_IS_E1(bp)) {
7181                 /* 0x2 disable mf_ov, 0x1 enable */
7182                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7183                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7184
7185                 if (!CHIP_IS_E1x(bp)) {
7186                         val = 0;
7187                         switch (bp->mf_mode) {
7188                         case MULTI_FUNCTION_SD:
7189                                 val = 1;
7190                                 break;
7191                         case MULTI_FUNCTION_SI:
7192                         case MULTI_FUNCTION_AFEX:
7193                                 val = 2;
7194                                 break;
7195                         }
7196
7197                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7198                                                   NIG_REG_LLH0_CLS_TYPE), val);
7199                 }
7200                 {
7201                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7202                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7203                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7204                 }
7205         }
7206
7207         /* If SPIO5 is set to generate interrupts, enable it for this port */
7208         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7209         if (val & MISC_SPIO_SPIO5) {
7210                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7211                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7212                 val = REG_RD(bp, reg_addr);
7213                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7214                 REG_WR(bp, reg_addr, val);
7215         }
7216
7217         return 0;
7218 }
7219
7220 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7221 {
7222         int reg;
7223         u32 wb_write[2];
7224
7225         if (CHIP_IS_E1(bp))
7226                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7227         else
7228                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7229
7230         wb_write[0] = ONCHIP_ADDR1(addr);
7231         wb_write[1] = ONCHIP_ADDR2(addr);
7232         REG_WR_DMAE(bp, reg, wb_write, 2);
7233 }
7234
7235 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7236 {
7237         u32 data, ctl, cnt = 100;
7238         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7239         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7240         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7241         u32 sb_bit =  1 << (idu_sb_id%32);
7242         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7243         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7244
7245         /* Not supported in BC mode */
7246         if (CHIP_INT_MODE_IS_BC(bp))
7247                 return;
7248
7249         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7250                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7251                 IGU_REGULAR_CLEANUP_SET                         |
7252                 IGU_REGULAR_BCLEANUP;
7253
7254         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7255               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7256               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7257
7258         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7259                          data, igu_addr_data);
7260         REG_WR(bp, igu_addr_data, data);
7261         mmiowb();
7262         barrier();
7263         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7264                           ctl, igu_addr_ctl);
7265         REG_WR(bp, igu_addr_ctl, ctl);
7266         mmiowb();
7267         barrier();
7268
7269         /* wait for clean up to finish */
7270         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7271                 msleep(20);
7272
7273
7274         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7275                 DP(NETIF_MSG_HW,
7276                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7277                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7278         }
7279 }
7280
7281 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7282 {
7283         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7284 }
7285
7286 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7287 {
7288         u32 i, base = FUNC_ILT_BASE(func);
7289         for (i = base; i < base + ILT_PER_FUNC; i++)
7290                 bnx2x_ilt_wr(bp, i, 0);
7291 }
7292
7293
7294 static void bnx2x_init_searcher(struct bnx2x *bp)
7295 {
7296         int port = BP_PORT(bp);
7297         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7298         /* T1 hash bits value determines the T1 number of entries */
7299         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7300 }
7301
7302 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7303 {
7304         int rc;
7305         struct bnx2x_func_state_params func_params = {NULL};
7306         struct bnx2x_func_switch_update_params *switch_update_params =
7307                 &func_params.params.switch_update;
7308
7309         /* Prepare parameters for function state transitions */
7310         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7311         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7312
7313         func_params.f_obj = &bp->func_obj;
7314         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7315
7316         /* Function parameters */
7317         switch_update_params->suspend = suspend;
7318
7319         rc = bnx2x_func_state_change(bp, &func_params);
7320
7321         return rc;
7322 }
7323
7324 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7325 {
7326         int rc, i, port = BP_PORT(bp);
7327         int vlan_en = 0, mac_en[NUM_MACS];
7328
7329
7330         /* Close input from network */
7331         if (bp->mf_mode == SINGLE_FUNCTION) {
7332                 bnx2x_set_rx_filter(&bp->link_params, 0);
7333         } else {
7334                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7335                                    NIG_REG_LLH0_FUNC_EN);
7336                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7337                           NIG_REG_LLH0_FUNC_EN, 0);
7338                 for (i = 0; i < NUM_MACS; i++) {
7339                         mac_en[i] = REG_RD(bp, port ?
7340                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7341                                               4 * i) :
7342                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7343                                               4 * i));
7344                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7345                                               4 * i) :
7346                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7347                 }
7348         }
7349
7350         /* Close BMC to host */
7351         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7352                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7353
7354         /* Suspend Tx switching to the PF. Completion of this ramrod
7355          * further guarantees that all the packets of that PF / child
7356          * VFs in BRB were processed by the Parser, so it is safe to
7357          * change the NIC_MODE register.
7358          */
7359         rc = bnx2x_func_switch_update(bp, 1);
7360         if (rc) {
7361                 BNX2X_ERR("Can't suspend tx-switching!\n");
7362                 return rc;
7363         }
7364
7365         /* Change NIC_MODE register */
7366         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7367
7368         /* Open input from network */
7369         if (bp->mf_mode == SINGLE_FUNCTION) {
7370                 bnx2x_set_rx_filter(&bp->link_params, 1);
7371         } else {
7372                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7373                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7374                 for (i = 0; i < NUM_MACS; i++) {
7375                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7376                                               4 * i) :
7377                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7378                                   mac_en[i]);
7379                 }
7380         }
7381
7382         /* Enable BMC to host */
7383         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7384                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7385
7386         /* Resume Tx switching to the PF */
7387         rc = bnx2x_func_switch_update(bp, 0);
7388         if (rc) {
7389                 BNX2X_ERR("Can't resume tx-switching!\n");
7390                 return rc;
7391         }
7392
7393         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7394         return 0;
7395 }
7396
7397 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7398 {
7399         int rc;
7400
7401         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7402
7403         if (CONFIGURE_NIC_MODE(bp)) {
7404                 /* Configrue searcher as part of function hw init */
7405                 bnx2x_init_searcher(bp);
7406
7407                 /* Reset NIC mode */
7408                 rc = bnx2x_reset_nic_mode(bp);
7409                 if (rc)
7410                         BNX2X_ERR("Can't change NIC mode!\n");
7411                 return rc;
7412         }
7413
7414         return 0;
7415 }
7416
7417 static int bnx2x_init_hw_func(struct bnx2x *bp)
7418 {
7419         int port = BP_PORT(bp);
7420         int func = BP_FUNC(bp);
7421         int init_phase = PHASE_PF0 + func;
7422         struct bnx2x_ilt *ilt = BP_ILT(bp);
7423         u16 cdu_ilt_start;
7424         u32 addr, val;
7425         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7426         int i, main_mem_width, rc;
7427
7428         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7429
7430         /* FLR cleanup - hmmm */
7431         if (!CHIP_IS_E1x(bp)) {
7432                 rc = bnx2x_pf_flr_clnup(bp);
7433                 if (rc) {
7434                         bnx2x_fw_dump(bp);
7435                         return rc;
7436                 }
7437         }
7438
7439         /* set MSI reconfigure capability */
7440         if (bp->common.int_block == INT_BLOCK_HC) {
7441                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7442                 val = REG_RD(bp, addr);
7443                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7444                 REG_WR(bp, addr, val);
7445         }
7446
7447         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7448         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7449
7450         ilt = BP_ILT(bp);
7451         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7452
7453         if (IS_SRIOV(bp))
7454                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7455         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7456
7457         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7458          * those of the VFs, so start line should be reset
7459          */
7460         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7461         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7462                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7463                 ilt->lines[cdu_ilt_start + i].page_mapping =
7464                         bp->context[i].cxt_mapping;
7465                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7466         }
7467
7468         bnx2x_ilt_init_op(bp, INITOP_SET);
7469
7470         if (!CONFIGURE_NIC_MODE(bp)) {
7471                 bnx2x_init_searcher(bp);
7472                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7473                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7474         } else {
7475                 /* Set NIC mode */
7476                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7477                 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
7478
7479         }
7480
7481         if (!CHIP_IS_E1x(bp)) {
7482                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7483
7484                 /* Turn on a single ISR mode in IGU if driver is going to use
7485                  * INT#x or MSI
7486                  */
7487                 if (!(bp->flags & USING_MSIX_FLAG))
7488                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7489                 /*
7490                  * Timers workaround bug: function init part.
7491                  * Need to wait 20msec after initializing ILT,
7492                  * needed to make sure there are no requests in
7493                  * one of the PXP internal queues with "old" ILT addresses
7494                  */
7495                 msleep(20);
7496                 /*
7497                  * Master enable - Due to WB DMAE writes performed before this
7498                  * register is re-initialized as part of the regular function
7499                  * init
7500                  */
7501                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7502                 /* Enable the function in IGU */
7503                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7504         }
7505
7506         bp->dmae_ready = 1;
7507
7508         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7509
7510         if (!CHIP_IS_E1x(bp))
7511                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7512
7513         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7514         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7515         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7516         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7517         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7518         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7519         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7520         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7521         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7522         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7523         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7524         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7525         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7526
7527         if (!CHIP_IS_E1x(bp))
7528                 REG_WR(bp, QM_REG_PF_EN, 1);
7529
7530         if (!CHIP_IS_E1x(bp)) {
7531                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7532                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7533                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7534                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7535         }
7536         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7537
7538         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7539         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7540
7541         bnx2x_iov_init_dq(bp);
7542
7543         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7544         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7545         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7546         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7547         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7548         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7549         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7550         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7551         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7552         if (!CHIP_IS_E1x(bp))
7553                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7554
7555         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7556
7557         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7558
7559         if (!CHIP_IS_E1x(bp))
7560                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7561
7562         if (IS_MF(bp)) {
7563                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7564                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7565         }
7566
7567         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7568
7569         /* HC init per function */
7570         if (bp->common.int_block == INT_BLOCK_HC) {
7571                 if (CHIP_IS_E1H(bp)) {
7572                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7573
7574                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7575                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7576                 }
7577                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7578
7579         } else {
7580                 int num_segs, sb_idx, prod_offset;
7581
7582                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7583
7584                 if (!CHIP_IS_E1x(bp)) {
7585                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7586                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7587                 }
7588
7589                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7590
7591                 if (!CHIP_IS_E1x(bp)) {
7592                         int dsb_idx = 0;
7593                         /**
7594                          * Producer memory:
7595                          * E2 mode: address 0-135 match to the mapping memory;
7596                          * 136 - PF0 default prod; 137 - PF1 default prod;
7597                          * 138 - PF2 default prod; 139 - PF3 default prod;
7598                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7599                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7600                          * 144-147 reserved.
7601                          *
7602                          * E1.5 mode - In backward compatible mode;
7603                          * for non default SB; each even line in the memory
7604                          * holds the U producer and each odd line hold
7605                          * the C producer. The first 128 producers are for
7606                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7607                          * producers are for the DSB for each PF.
7608                          * Each PF has five segments: (the order inside each
7609                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7610                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7611                          * 144-147 attn prods;
7612                          */
7613                         /* non-default-status-blocks */
7614                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7615                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7616                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7617                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7618                                         num_segs;
7619
7620                                 for (i = 0; i < num_segs; i++) {
7621                                         addr = IGU_REG_PROD_CONS_MEMORY +
7622                                                         (prod_offset + i) * 4;
7623                                         REG_WR(bp, addr, 0);
7624                                 }
7625                                 /* send consumer update with value 0 */
7626                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7627                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7628                                 bnx2x_igu_clear_sb(bp,
7629                                                    bp->igu_base_sb + sb_idx);
7630                         }
7631
7632                         /* default-status-blocks */
7633                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7634                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7635
7636                         if (CHIP_MODE_IS_4_PORT(bp))
7637                                 dsb_idx = BP_FUNC(bp);
7638                         else
7639                                 dsb_idx = BP_VN(bp);
7640
7641                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7642                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7643                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7644
7645                         /*
7646                          * igu prods come in chunks of E1HVN_MAX (4) -
7647                          * does not matters what is the current chip mode
7648                          */
7649                         for (i = 0; i < (num_segs * E1HVN_MAX);
7650                              i += E1HVN_MAX) {
7651                                 addr = IGU_REG_PROD_CONS_MEMORY +
7652                                                         (prod_offset + i)*4;
7653                                 REG_WR(bp, addr, 0);
7654                         }
7655                         /* send consumer update with 0 */
7656                         if (CHIP_INT_MODE_IS_BC(bp)) {
7657                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7658                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7659                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7660                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7661                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7662                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7663                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7664                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7665                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7666                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7667                         } else {
7668                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7669                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7670                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7671                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7672                         }
7673                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7674
7675                         /* !!! these should become driver const once
7676                            rf-tool supports split-68 const */
7677                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7678                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7679                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7680                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7681                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7682                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7683                 }
7684         }
7685
7686         /* Reset PCIE errors for debug */
7687         REG_WR(bp, 0x2114, 0xffffffff);
7688         REG_WR(bp, 0x2120, 0xffffffff);
7689
7690         if (CHIP_IS_E1x(bp)) {
7691                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7692                 main_mem_base = HC_REG_MAIN_MEMORY +
7693                                 BP_PORT(bp) * (main_mem_size * 4);
7694                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7695                 main_mem_width = 8;
7696
7697                 val = REG_RD(bp, main_mem_prty_clr);
7698                 if (val)
7699                         DP(NETIF_MSG_HW,
7700                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7701                            val);
7702
7703                 /* Clear "false" parity errors in MSI-X table */
7704                 for (i = main_mem_base;
7705                      i < main_mem_base + main_mem_size * 4;
7706                      i += main_mem_width) {
7707                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7708                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7709                                          i, main_mem_width / 4);
7710                 }
7711                 /* Clear HC parity attention */
7712                 REG_RD(bp, main_mem_prty_clr);
7713         }
7714
7715 #ifdef BNX2X_STOP_ON_ERROR
7716         /* Enable STORMs SP logging */
7717         REG_WR8(bp, BAR_USTRORM_INTMEM +
7718                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7719         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7720                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7721         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7722                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7723         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7724                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7725 #endif
7726
7727         bnx2x_phy_probe(&bp->link_params);
7728
7729         return 0;
7730 }
7731
7732
7733 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7734 {
7735         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7736
7737         if (!CHIP_IS_E1x(bp))
7738                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7739                                sizeof(struct host_hc_status_block_e2));
7740         else
7741                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7742                                sizeof(struct host_hc_status_block_e1x));
7743
7744         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7745 }
7746
7747 void bnx2x_free_mem(struct bnx2x *bp)
7748 {
7749         int i;
7750
7751         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7752                        sizeof(struct host_sp_status_block));
7753
7754         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7755                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7756
7757         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7758                        sizeof(struct bnx2x_slowpath));
7759
7760         for (i = 0; i < L2_ILT_LINES(bp); i++)
7761                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7762                                bp->context[i].size);
7763         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7764
7765         BNX2X_FREE(bp->ilt->lines);
7766
7767         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7768
7769         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7770                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7771
7772         bnx2x_iov_free_mem(bp);
7773 }
7774
7775
7776 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7777 {
7778         if (!CHIP_IS_E1x(bp))
7779                 /* size = the status block + ramrod buffers */
7780                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7781                                 sizeof(struct host_hc_status_block_e2));
7782         else
7783                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7784                                 &bp->cnic_sb_mapping,
7785                                 sizeof(struct
7786                                        host_hc_status_block_e1x));
7787
7788         if (CONFIGURE_NIC_MODE(bp))
7789                 /* allocate searcher T2 table, as it wan't allocated before */
7790                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7791
7792         /* write address to which L5 should insert its values */
7793         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7794                 &bp->slowpath->drv_info_to_mcp;
7795
7796         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7797                 goto alloc_mem_err;
7798
7799         return 0;
7800
7801 alloc_mem_err:
7802         bnx2x_free_mem_cnic(bp);
7803         BNX2X_ERR("Can't allocate memory\n");
7804         return -ENOMEM;
7805 }
7806
7807 int bnx2x_alloc_mem(struct bnx2x *bp)
7808 {
7809         int i, allocated, context_size;
7810
7811         if (!CONFIGURE_NIC_MODE(bp))
7812                 /* allocate searcher T2 table */
7813                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7814
7815         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7816                         sizeof(struct host_sp_status_block));
7817
7818         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7819                         sizeof(struct bnx2x_slowpath));
7820
7821         /* Allocate memory for CDU context:
7822          * This memory is allocated separately and not in the generic ILT
7823          * functions because CDU differs in few aspects:
7824          * 1. There are multiple entities allocating memory for context -
7825          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7826          * its own ILT lines.
7827          * 2. Since CDU page-size is not a single 4KB page (which is the case
7828          * for the other ILT clients), to be efficient we want to support
7829          * allocation of sub-page-size in the last entry.
7830          * 3. Context pointers are used by the driver to pass to FW / update
7831          * the context (for the other ILT clients the pointers are used just to
7832          * free the memory during unload).
7833          */
7834         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7835
7836         for (i = 0, allocated = 0; allocated < context_size; i++) {
7837                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7838                                           (context_size - allocated));
7839                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7840                                 &bp->context[i].cxt_mapping,
7841                                 bp->context[i].size);
7842                 allocated += bp->context[i].size;
7843         }
7844         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7845
7846         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7847                 goto alloc_mem_err;
7848
7849         if (bnx2x_iov_alloc_mem(bp))
7850                 goto alloc_mem_err;
7851
7852         /* Slow path ring */
7853         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7854
7855         /* EQ */
7856         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7857                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
7858
7859         return 0;
7860
7861 alloc_mem_err:
7862         bnx2x_free_mem(bp);
7863         BNX2X_ERR("Can't allocate memory\n");
7864         return -ENOMEM;
7865 }
7866
7867 /*
7868  * Init service functions
7869  */
7870
7871 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7872                       struct bnx2x_vlan_mac_obj *obj, bool set,
7873                       int mac_type, unsigned long *ramrod_flags)
7874 {
7875         int rc;
7876         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7877
7878         memset(&ramrod_param, 0, sizeof(ramrod_param));
7879
7880         /* Fill general parameters */
7881         ramrod_param.vlan_mac_obj = obj;
7882         ramrod_param.ramrod_flags = *ramrod_flags;
7883
7884         /* Fill a user request section if needed */
7885         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7886                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7887
7888                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7889
7890                 /* Set the command: ADD or DEL */
7891                 if (set)
7892                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7893                 else
7894                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7895         }
7896
7897         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7898
7899         if (rc == -EEXIST) {
7900                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7901                 /* do not treat adding same MAC as error */
7902                 rc = 0;
7903         } else if (rc < 0)
7904                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7905
7906         return rc;
7907 }
7908
7909 int bnx2x_del_all_macs(struct bnx2x *bp,
7910                        struct bnx2x_vlan_mac_obj *mac_obj,
7911                        int mac_type, bool wait_for_comp)
7912 {
7913         int rc;
7914         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7915
7916         /* Wait for completion of requested */
7917         if (wait_for_comp)
7918                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7919
7920         /* Set the mac type of addresses we want to clear */
7921         __set_bit(mac_type, &vlan_mac_flags);
7922
7923         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7924         if (rc < 0)
7925                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7926
7927         return rc;
7928 }
7929
7930 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7931 {
7932         unsigned long ramrod_flags = 0;
7933
7934         if (is_zero_ether_addr(bp->dev->dev_addr) &&
7935             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7936                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7937                    "Ignoring Zero MAC for STORAGE SD mode\n");
7938                 return 0;
7939         }
7940
7941         DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7942
7943         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7944         /* Eth MAC is set on RSS leading client (fp[0]) */
7945         return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7946                                  set, BNX2X_ETH_MAC, &ramrod_flags);
7947 }
7948
7949 int bnx2x_setup_leading(struct bnx2x *bp)
7950 {
7951         return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7952 }
7953
7954 /**
7955  * bnx2x_set_int_mode - configure interrupt mode
7956  *
7957  * @bp:         driver handle
7958  *
7959  * In case of MSI-X it will also try to enable MSI-X.
7960  */
7961 int bnx2x_set_int_mode(struct bnx2x *bp)
7962 {
7963         int rc = 0;
7964
7965         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
7966                 return -EINVAL;
7967
7968         switch (int_mode) {
7969         case BNX2X_INT_MODE_MSIX:
7970                 /* attempt to enable msix */
7971                 rc = bnx2x_enable_msix(bp);
7972
7973                 /* msix attained */
7974                 if (!rc)
7975                         return 0;
7976
7977                 /* vfs use only msix */
7978                 if (rc && IS_VF(bp))
7979                         return rc;
7980
7981                 /* failed to enable multiple MSI-X */
7982                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7983                                bp->num_queues,
7984                                1 + bp->num_cnic_queues);
7985
7986                 /* falling through... */
7987         case BNX2X_INT_MODE_MSI:
7988                 bnx2x_enable_msi(bp);
7989
7990                 /* falling through... */
7991         case BNX2X_INT_MODE_INTX:
7992                 bp->num_ethernet_queues = 1;
7993                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
7994                 BNX2X_DEV_INFO("set number of queues to 1\n");
7995                 break;
7996         default:
7997                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7998                 return -EINVAL;
7999         }
8000         return 0;
8001 }
8002
8003 /* must be called prior to any HW initializations */
8004 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8005 {
8006         if (IS_SRIOV(bp))
8007                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8008         return L2_ILT_LINES(bp);
8009 }
8010
8011 void bnx2x_ilt_set_info(struct bnx2x *bp)
8012 {
8013         struct ilt_client_info *ilt_client;
8014         struct bnx2x_ilt *ilt = BP_ILT(bp);
8015         u16 line = 0;
8016
8017         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8018         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8019
8020         /* CDU */
8021         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8022         ilt_client->client_num = ILT_CLIENT_CDU;
8023         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8024         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8025         ilt_client->start = line;
8026         line += bnx2x_cid_ilt_lines(bp);
8027
8028         if (CNIC_SUPPORT(bp))
8029                 line += CNIC_ILT_LINES;
8030         ilt_client->end = line - 1;
8031
8032         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8033            ilt_client->start,
8034            ilt_client->end,
8035            ilt_client->page_size,
8036            ilt_client->flags,
8037            ilog2(ilt_client->page_size >> 12));
8038
8039         /* QM */
8040         if (QM_INIT(bp->qm_cid_count)) {
8041                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8042                 ilt_client->client_num = ILT_CLIENT_QM;
8043                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8044                 ilt_client->flags = 0;
8045                 ilt_client->start = line;
8046
8047                 /* 4 bytes for each cid */
8048                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8049                                                          QM_ILT_PAGE_SZ);
8050
8051                 ilt_client->end = line - 1;
8052
8053                 DP(NETIF_MSG_IFUP,
8054                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8055                    ilt_client->start,
8056                    ilt_client->end,
8057                    ilt_client->page_size,
8058                    ilt_client->flags,
8059                    ilog2(ilt_client->page_size >> 12));
8060
8061         }
8062
8063         if (CNIC_SUPPORT(bp)) {
8064                 /* SRC */
8065                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8066                 ilt_client->client_num = ILT_CLIENT_SRC;
8067                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8068                 ilt_client->flags = 0;
8069                 ilt_client->start = line;
8070                 line += SRC_ILT_LINES;
8071                 ilt_client->end = line - 1;
8072
8073                 DP(NETIF_MSG_IFUP,
8074                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8075                    ilt_client->start,
8076                    ilt_client->end,
8077                    ilt_client->page_size,
8078                    ilt_client->flags,
8079                    ilog2(ilt_client->page_size >> 12));
8080
8081                 /* TM */
8082                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8083                 ilt_client->client_num = ILT_CLIENT_TM;
8084                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8085                 ilt_client->flags = 0;
8086                 ilt_client->start = line;
8087                 line += TM_ILT_LINES;
8088                 ilt_client->end = line - 1;
8089
8090                 DP(NETIF_MSG_IFUP,
8091                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8092                    ilt_client->start,
8093                    ilt_client->end,
8094                    ilt_client->page_size,
8095                    ilt_client->flags,
8096                    ilog2(ilt_client->page_size >> 12));
8097         }
8098
8099         BUG_ON(line > ILT_MAX_LINES);
8100 }
8101
8102 /**
8103  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8104  *
8105  * @bp:                 driver handle
8106  * @fp:                 pointer to fastpath
8107  * @init_params:        pointer to parameters structure
8108  *
8109  * parameters configured:
8110  *      - HC configuration
8111  *      - Queue's CDU context
8112  */
8113 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8114         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8115 {
8116
8117         u8 cos;
8118         int cxt_index, cxt_offset;
8119
8120         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8121         if (!IS_FCOE_FP(fp)) {
8122                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8123                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8124
8125                 /* If HC is supporterd, enable host coalescing in the transition
8126                  * to INIT state.
8127                  */
8128                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8129                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8130
8131                 /* HC rate */
8132                 init_params->rx.hc_rate = bp->rx_ticks ?
8133                         (1000000 / bp->rx_ticks) : 0;
8134                 init_params->tx.hc_rate = bp->tx_ticks ?
8135                         (1000000 / bp->tx_ticks) : 0;
8136
8137                 /* FW SB ID */
8138                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8139                         fp->fw_sb_id;
8140
8141                 /*
8142                  * CQ index among the SB indices: FCoE clients uses the default
8143                  * SB, therefore it's different.
8144                  */
8145                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8146                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8147         }
8148
8149         /* set maximum number of COSs supported by this queue */
8150         init_params->max_cos = fp->max_cos;
8151
8152         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8153             fp->index, init_params->max_cos);
8154
8155         /* set the context pointers queue object */
8156         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8157                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8158                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8159                                 ILT_PAGE_CIDS);
8160                 init_params->cxts[cos] =
8161                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8162         }
8163 }
8164
8165 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8166                         struct bnx2x_queue_state_params *q_params,
8167                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8168                         int tx_index, bool leading)
8169 {
8170         memset(tx_only_params, 0, sizeof(*tx_only_params));
8171
8172         /* Set the command */
8173         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8174
8175         /* Set tx-only QUEUE flags: don't zero statistics */
8176         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8177
8178         /* choose the index of the cid to send the slow path on */
8179         tx_only_params->cid_index = tx_index;
8180
8181         /* Set general TX_ONLY_SETUP parameters */
8182         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8183
8184         /* Set Tx TX_ONLY_SETUP parameters */
8185         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8186
8187         DP(NETIF_MSG_IFUP,
8188            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8189            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8190            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8191            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8192
8193         /* send the ramrod */
8194         return bnx2x_queue_state_change(bp, q_params);
8195 }
8196
8197
8198 /**
8199  * bnx2x_setup_queue - setup queue
8200  *
8201  * @bp:         driver handle
8202  * @fp:         pointer to fastpath
8203  * @leading:    is leading
8204  *
8205  * This function performs 2 steps in a Queue state machine
8206  *      actually: 1) RESET->INIT 2) INIT->SETUP
8207  */
8208
8209 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8210                        bool leading)
8211 {
8212         struct bnx2x_queue_state_params q_params = {NULL};
8213         struct bnx2x_queue_setup_params *setup_params =
8214                                                 &q_params.params.setup;
8215         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8216                                                 &q_params.params.tx_only;
8217         int rc;
8218         u8 tx_index;
8219
8220         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8221
8222         /* reset IGU state skip FCoE L2 queue */
8223         if (!IS_FCOE_FP(fp))
8224                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8225                              IGU_INT_ENABLE, 0);
8226
8227         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8228         /* We want to wait for completion in this context */
8229         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8230
8231         /* Prepare the INIT parameters */
8232         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8233
8234         /* Set the command */
8235         q_params.cmd = BNX2X_Q_CMD_INIT;
8236
8237         /* Change the state to INIT */
8238         rc = bnx2x_queue_state_change(bp, &q_params);
8239         if (rc) {
8240                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8241                 return rc;
8242         }
8243
8244         DP(NETIF_MSG_IFUP, "init complete\n");
8245
8246
8247         /* Now move the Queue to the SETUP state... */
8248         memset(setup_params, 0, sizeof(*setup_params));
8249
8250         /* Set QUEUE flags */
8251         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8252
8253         /* Set general SETUP parameters */
8254         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8255                                 FIRST_TX_COS_INDEX);
8256
8257         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8258                             &setup_params->rxq_params);
8259
8260         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8261                            FIRST_TX_COS_INDEX);
8262
8263         /* Set the command */
8264         q_params.cmd = BNX2X_Q_CMD_SETUP;
8265
8266         if (IS_FCOE_FP(fp))
8267                 bp->fcoe_init = true;
8268
8269         /* Change the state to SETUP */
8270         rc = bnx2x_queue_state_change(bp, &q_params);
8271         if (rc) {
8272                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8273                 return rc;
8274         }
8275
8276         /* loop through the relevant tx-only indices */
8277         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8278               tx_index < fp->max_cos;
8279               tx_index++) {
8280
8281                 /* prepare and send tx-only ramrod*/
8282                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8283                                           tx_only_params, tx_index, leading);
8284                 if (rc) {
8285                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8286                                   fp->index, tx_index);
8287                         return rc;
8288                 }
8289         }
8290
8291         return rc;
8292 }
8293
8294 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8295 {
8296         struct bnx2x_fastpath *fp = &bp->fp[index];
8297         struct bnx2x_fp_txdata *txdata;
8298         struct bnx2x_queue_state_params q_params = {NULL};
8299         int rc, tx_index;
8300
8301         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8302
8303         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8304         /* We want to wait for completion in this context */
8305         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8306
8307
8308         /* close tx-only connections */
8309         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8310              tx_index < fp->max_cos;
8311              tx_index++){
8312
8313                 /* ascertain this is a normal queue*/
8314                 txdata = fp->txdata_ptr[tx_index];
8315
8316                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8317                                                         txdata->txq_index);
8318
8319                 /* send halt terminate on tx-only connection */
8320                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8321                 memset(&q_params.params.terminate, 0,
8322                        sizeof(q_params.params.terminate));
8323                 q_params.params.terminate.cid_index = tx_index;
8324
8325                 rc = bnx2x_queue_state_change(bp, &q_params);
8326                 if (rc)
8327                         return rc;
8328
8329                 /* send halt terminate on tx-only connection */
8330                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8331                 memset(&q_params.params.cfc_del, 0,
8332                        sizeof(q_params.params.cfc_del));
8333                 q_params.params.cfc_del.cid_index = tx_index;
8334                 rc = bnx2x_queue_state_change(bp, &q_params);
8335                 if (rc)
8336                         return rc;
8337         }
8338         /* Stop the primary connection: */
8339         /* ...halt the connection */
8340         q_params.cmd = BNX2X_Q_CMD_HALT;
8341         rc = bnx2x_queue_state_change(bp, &q_params);
8342         if (rc)
8343                 return rc;
8344
8345         /* ...terminate the connection */
8346         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8347         memset(&q_params.params.terminate, 0,
8348                sizeof(q_params.params.terminate));
8349         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8350         rc = bnx2x_queue_state_change(bp, &q_params);
8351         if (rc)
8352                 return rc;
8353         /* ...delete cfc entry */
8354         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8355         memset(&q_params.params.cfc_del, 0,
8356                sizeof(q_params.params.cfc_del));
8357         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8358         return bnx2x_queue_state_change(bp, &q_params);
8359 }
8360
8361
8362 static void bnx2x_reset_func(struct bnx2x *bp)
8363 {
8364         int port = BP_PORT(bp);
8365         int func = BP_FUNC(bp);
8366         int i;
8367
8368         /* Disable the function in the FW */
8369         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8370         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8371         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8372         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8373
8374         /* FP SBs */
8375         for_each_eth_queue(bp, i) {
8376                 struct bnx2x_fastpath *fp = &bp->fp[i];
8377                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8378                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8379                            SB_DISABLED);
8380         }
8381
8382         if (CNIC_LOADED(bp))
8383                 /* CNIC SB */
8384                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8385                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8386                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8387
8388         /* SP SB */
8389         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8390                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8391                 SB_DISABLED);
8392
8393         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8394                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8395                        0);
8396
8397         /* Configure IGU */
8398         if (bp->common.int_block == INT_BLOCK_HC) {
8399                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8400                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8401         } else {
8402                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8403                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8404         }
8405
8406         if (CNIC_LOADED(bp)) {
8407                 /* Disable Timer scan */
8408                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8409                 /*
8410                  * Wait for at least 10ms and up to 2 second for the timers
8411                  * scan to complete
8412                  */
8413                 for (i = 0; i < 200; i++) {
8414                         msleep(10);
8415                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8416                                 break;
8417                 }
8418         }
8419         /* Clear ILT */
8420         bnx2x_clear_func_ilt(bp, func);
8421
8422         /* Timers workaround bug for E2: if this is vnic-3,
8423          * we need to set the entire ilt range for this timers.
8424          */
8425         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8426                 struct ilt_client_info ilt_cli;
8427                 /* use dummy TM client */
8428                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8429                 ilt_cli.start = 0;
8430                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8431                 ilt_cli.client_num = ILT_CLIENT_TM;
8432
8433                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8434         }
8435
8436         /* this assumes that reset_port() called before reset_func()*/
8437         if (!CHIP_IS_E1x(bp))
8438                 bnx2x_pf_disable(bp);
8439
8440         bp->dmae_ready = 0;
8441 }
8442
8443 static void bnx2x_reset_port(struct bnx2x *bp)
8444 {
8445         int port = BP_PORT(bp);
8446         u32 val;
8447
8448         /* Reset physical Link */
8449         bnx2x__link_reset(bp);
8450
8451         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8452
8453         /* Do not rcv packets to BRB */
8454         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8455         /* Do not direct rcv packets that are not for MCP to the BRB */
8456         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8457                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8458
8459         /* Configure AEU */
8460         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8461
8462         msleep(100);
8463         /* Check for BRB port occupancy */
8464         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8465         if (val)
8466                 DP(NETIF_MSG_IFDOWN,
8467                    "BRB1 is not empty  %d blocks are occupied\n", val);
8468
8469         /* TODO: Close Doorbell port? */
8470 }
8471
8472 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8473 {
8474         struct bnx2x_func_state_params func_params = {NULL};
8475
8476         /* Prepare parameters for function state transitions */
8477         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8478
8479         func_params.f_obj = &bp->func_obj;
8480         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8481
8482         func_params.params.hw_init.load_phase = load_code;
8483
8484         return bnx2x_func_state_change(bp, &func_params);
8485 }
8486
8487 static int bnx2x_func_stop(struct bnx2x *bp)
8488 {
8489         struct bnx2x_func_state_params func_params = {NULL};
8490         int rc;
8491
8492         /* Prepare parameters for function state transitions */
8493         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8494         func_params.f_obj = &bp->func_obj;
8495         func_params.cmd = BNX2X_F_CMD_STOP;
8496
8497         /*
8498          * Try to stop the function the 'good way'. If fails (in case
8499          * of a parity error during bnx2x_chip_cleanup()) and we are
8500          * not in a debug mode, perform a state transaction in order to
8501          * enable further HW_RESET transaction.
8502          */
8503         rc = bnx2x_func_state_change(bp, &func_params);
8504         if (rc) {
8505 #ifdef BNX2X_STOP_ON_ERROR
8506                 return rc;
8507 #else
8508                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8509                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8510                 return bnx2x_func_state_change(bp, &func_params);
8511 #endif
8512         }
8513
8514         return 0;
8515 }
8516
8517 /**
8518  * bnx2x_send_unload_req - request unload mode from the MCP.
8519  *
8520  * @bp:                 driver handle
8521  * @unload_mode:        requested function's unload mode
8522  *
8523  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8524  */
8525 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8526 {
8527         u32 reset_code = 0;
8528         int port = BP_PORT(bp);
8529
8530         /* Select the UNLOAD request mode */
8531         if (unload_mode == UNLOAD_NORMAL)
8532                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8533
8534         else if (bp->flags & NO_WOL_FLAG)
8535                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8536
8537         else if (bp->wol) {
8538                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8539                 u8 *mac_addr = bp->dev->dev_addr;
8540                 u32 val;
8541                 u16 pmc;
8542
8543                 /* The mac address is written to entries 1-4 to
8544                  * preserve entry 0 which is used by the PMF
8545                  */
8546                 u8 entry = (BP_VN(bp) + 1)*8;
8547
8548                 val = (mac_addr[0] << 8) | mac_addr[1];
8549                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8550
8551                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8552                       (mac_addr[4] << 8) | mac_addr[5];
8553                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8554
8555                 /* Enable the PME and clear the status */
8556                 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8557                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8558                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8559
8560                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8561
8562         } else
8563                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8564
8565         /* Send the request to the MCP */
8566         if (!BP_NOMCP(bp))
8567                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8568         else {
8569                 int path = BP_PATH(bp);
8570
8571                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8572                    path, load_count[path][0], load_count[path][1],
8573                    load_count[path][2]);
8574                 load_count[path][0]--;
8575                 load_count[path][1 + port]--;
8576                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8577                    path, load_count[path][0], load_count[path][1],
8578                    load_count[path][2]);
8579                 if (load_count[path][0] == 0)
8580                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8581                 else if (load_count[path][1 + port] == 0)
8582                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8583                 else
8584                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8585         }
8586
8587         return reset_code;
8588 }
8589
8590 /**
8591  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8592  *
8593  * @bp:         driver handle
8594  * @keep_link:          true iff link should be kept up
8595  */
8596 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8597 {
8598         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8599
8600         /* Report UNLOAD_DONE to MCP */
8601         if (!BP_NOMCP(bp))
8602                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8603 }
8604
8605 static int bnx2x_func_wait_started(struct bnx2x *bp)
8606 {
8607         int tout = 50;
8608         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8609
8610         if (!bp->port.pmf)
8611                 return 0;
8612
8613         /*
8614          * (assumption: No Attention from MCP at this stage)
8615          * PMF probably in the middle of TXdisable/enable transaction
8616          * 1. Sync IRS for default SB
8617          * 2. Sync SP queue - this guarantes us that attention handling started
8618          * 3. Wait, that TXdisable/enable transaction completes
8619          *
8620          * 1+2 guranty that if DCBx attention was scheduled it already changed
8621          * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8622          * received complettion for the transaction the state is TX_STOPPED.
8623          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8624          * transaction.
8625          */
8626
8627         /* make sure default SB ISR is done */
8628         if (msix)
8629                 synchronize_irq(bp->msix_table[0].vector);
8630         else
8631                 synchronize_irq(bp->pdev->irq);
8632
8633         flush_workqueue(bnx2x_wq);
8634
8635         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8636                                 BNX2X_F_STATE_STARTED && tout--)
8637                 msleep(20);
8638
8639         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8640                                                 BNX2X_F_STATE_STARTED) {
8641 #ifdef BNX2X_STOP_ON_ERROR
8642                 BNX2X_ERR("Wrong function state\n");
8643                 return -EBUSY;
8644 #else
8645                 /*
8646                  * Failed to complete the transaction in a "good way"
8647                  * Force both transactions with CLR bit
8648                  */
8649                 struct bnx2x_func_state_params func_params = {NULL};
8650
8651                 DP(NETIF_MSG_IFDOWN,
8652                    "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8653
8654                 func_params.f_obj = &bp->func_obj;
8655                 __set_bit(RAMROD_DRV_CLR_ONLY,
8656                                         &func_params.ramrod_flags);
8657
8658                 /* STARTED-->TX_ST0PPED */
8659                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8660                 bnx2x_func_state_change(bp, &func_params);
8661
8662                 /* TX_ST0PPED-->STARTED */
8663                 func_params.cmd = BNX2X_F_CMD_TX_START;
8664                 return bnx2x_func_state_change(bp, &func_params);
8665 #endif
8666         }
8667
8668         return 0;
8669 }
8670
8671 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8672 {
8673         int port = BP_PORT(bp);
8674         int i, rc = 0;
8675         u8 cos;
8676         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8677         u32 reset_code;
8678
8679         /* Wait until tx fastpath tasks complete */
8680         for_each_tx_queue(bp, i) {
8681                 struct bnx2x_fastpath *fp = &bp->fp[i];
8682
8683                 for_each_cos_in_tx_queue(fp, cos)
8684                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8685 #ifdef BNX2X_STOP_ON_ERROR
8686                 if (rc)
8687                         return;
8688 #endif
8689         }
8690
8691         /* Give HW time to discard old tx messages */
8692         usleep_range(1000, 2000);
8693
8694         /* Clean all ETH MACs */
8695         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8696                                 false);
8697         if (rc < 0)
8698                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8699
8700         /* Clean up UC list  */
8701         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8702                                 true);
8703         if (rc < 0)
8704                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8705                           rc);
8706
8707         /* Disable LLH */
8708         if (!CHIP_IS_E1(bp))
8709                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8710
8711         /* Set "drop all" (stop Rx).
8712          * We need to take a netif_addr_lock() here in order to prevent
8713          * a race between the completion code and this code.
8714          */
8715         netif_addr_lock_bh(bp->dev);
8716         /* Schedule the rx_mode command */
8717         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8718                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8719         else
8720                 bnx2x_set_storm_rx_mode(bp);
8721
8722         /* Cleanup multicast configuration */
8723         rparam.mcast_obj = &bp->mcast_obj;
8724         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8725         if (rc < 0)
8726                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8727
8728         netif_addr_unlock_bh(bp->dev);
8729
8730         bnx2x_iov_chip_cleanup(bp);
8731
8732
8733         /*
8734          * Send the UNLOAD_REQUEST to the MCP. This will return if
8735          * this function should perform FUNC, PORT or COMMON HW
8736          * reset.
8737          */
8738         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8739
8740         /*
8741          * (assumption: No Attention from MCP at this stage)
8742          * PMF probably in the middle of TXdisable/enable transaction
8743          */
8744         rc = bnx2x_func_wait_started(bp);
8745         if (rc) {
8746                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8747 #ifdef BNX2X_STOP_ON_ERROR
8748                 return;
8749 #endif
8750         }
8751
8752         /* Close multi and leading connections
8753          * Completions for ramrods are collected in a synchronous way
8754          */
8755         for_each_eth_queue(bp, i)
8756                 if (bnx2x_stop_queue(bp, i))
8757 #ifdef BNX2X_STOP_ON_ERROR
8758                         return;
8759 #else
8760                         goto unload_error;
8761 #endif
8762
8763         if (CNIC_LOADED(bp)) {
8764                 for_each_cnic_queue(bp, i)
8765                         if (bnx2x_stop_queue(bp, i))
8766 #ifdef BNX2X_STOP_ON_ERROR
8767                                 return;
8768 #else
8769                                 goto unload_error;
8770 #endif
8771         }
8772
8773         /* If SP settings didn't get completed so far - something
8774          * very wrong has happen.
8775          */
8776         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8777                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8778
8779 #ifndef BNX2X_STOP_ON_ERROR
8780 unload_error:
8781 #endif
8782         rc = bnx2x_func_stop(bp);
8783         if (rc) {
8784                 BNX2X_ERR("Function stop failed!\n");
8785 #ifdef BNX2X_STOP_ON_ERROR
8786                 return;
8787 #endif
8788         }
8789
8790         /* Disable HW interrupts, NAPI */
8791         bnx2x_netif_stop(bp, 1);
8792         /* Delete all NAPI objects */
8793         bnx2x_del_all_napi(bp);
8794         if (CNIC_LOADED(bp))
8795                 bnx2x_del_all_napi_cnic(bp);
8796
8797         /* Release IRQs */
8798         bnx2x_free_irq(bp);
8799
8800         /* Reset the chip */
8801         rc = bnx2x_reset_hw(bp, reset_code);
8802         if (rc)
8803                 BNX2X_ERR("HW_RESET failed\n");
8804
8805
8806         /* Report UNLOAD_DONE to MCP */
8807         bnx2x_send_unload_done(bp, keep_link);
8808 }
8809
8810 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8811 {
8812         u32 val;
8813
8814         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8815
8816         if (CHIP_IS_E1(bp)) {
8817                 int port = BP_PORT(bp);
8818                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8819                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8820
8821                 val = REG_RD(bp, addr);
8822                 val &= ~(0x300);
8823                 REG_WR(bp, addr, val);
8824         } else {
8825                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8826                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8827                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8828                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8829         }
8830 }
8831
8832 /* Close gates #2, #3 and #4: */
8833 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8834 {
8835         u32 val;
8836
8837         /* Gates #2 and #4a are closed/opened for "not E1" only */
8838         if (!CHIP_IS_E1(bp)) {
8839                 /* #4 */
8840                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8841                 /* #2 */
8842                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8843         }
8844
8845         /* #3 */
8846         if (CHIP_IS_E1x(bp)) {
8847                 /* Prevent interrupts from HC on both ports */
8848                 val = REG_RD(bp, HC_REG_CONFIG_1);
8849                 REG_WR(bp, HC_REG_CONFIG_1,
8850                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8851                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8852
8853                 val = REG_RD(bp, HC_REG_CONFIG_0);
8854                 REG_WR(bp, HC_REG_CONFIG_0,
8855                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8856                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8857         } else {
8858                 /* Prevent incoming interrupts in IGU */
8859                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8860
8861                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8862                        (!close) ?
8863                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8864                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8865         }
8866
8867         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8868                 close ? "closing" : "opening");
8869         mmiowb();
8870 }
8871
8872 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
8873
8874 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8875 {
8876         /* Do some magic... */
8877         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8878         *magic_val = val & SHARED_MF_CLP_MAGIC;
8879         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8880 }
8881
8882 /**
8883  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8884  *
8885  * @bp:         driver handle
8886  * @magic_val:  old value of the `magic' bit.
8887  */
8888 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8889 {
8890         /* Restore the `magic' bit value... */
8891         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8892         MF_CFG_WR(bp, shared_mf_config.clp_mb,
8893                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8894 }
8895
8896 /**
8897  * bnx2x_reset_mcp_prep - prepare for MCP reset.
8898  *
8899  * @bp:         driver handle
8900  * @magic_val:  old value of 'magic' bit.
8901  *
8902  * Takes care of CLP configurations.
8903  */
8904 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8905 {
8906         u32 shmem;
8907         u32 validity_offset;
8908
8909         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8910
8911         /* Set `magic' bit in order to save MF config */
8912         if (!CHIP_IS_E1(bp))
8913                 bnx2x_clp_reset_prep(bp, magic_val);
8914
8915         /* Get shmem offset */
8916         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8917         validity_offset =
8918                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
8919
8920         /* Clear validity map flags */
8921         if (shmem > 0)
8922                 REG_WR(bp, shmem + validity_offset, 0);
8923 }
8924
8925 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
8926 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
8927
8928 /**
8929  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8930  *
8931  * @bp: driver handle
8932  */
8933 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8934 {
8935         /* special handling for emulation and FPGA,
8936            wait 10 times longer */
8937         if (CHIP_REV_IS_SLOW(bp))
8938                 msleep(MCP_ONE_TIMEOUT*10);
8939         else
8940                 msleep(MCP_ONE_TIMEOUT);
8941 }
8942
8943 /*
8944  * initializes bp->common.shmem_base and waits for validity signature to appear
8945  */
8946 static int bnx2x_init_shmem(struct bnx2x *bp)
8947 {
8948         int cnt = 0;
8949         u32 val = 0;
8950
8951         do {
8952                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8953                 if (bp->common.shmem_base) {
8954                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8955                         if (val & SHR_MEM_VALIDITY_MB)
8956                                 return 0;
8957                 }
8958
8959                 bnx2x_mcp_wait_one(bp);
8960
8961         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8962
8963         BNX2X_ERR("BAD MCP validity signature\n");
8964
8965         return -ENODEV;
8966 }
8967
8968 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8969 {
8970         int rc = bnx2x_init_shmem(bp);
8971
8972         /* Restore the `magic' bit value */
8973         if (!CHIP_IS_E1(bp))
8974                 bnx2x_clp_reset_done(bp, magic_val);
8975
8976         return rc;
8977 }
8978
8979 static void bnx2x_pxp_prep(struct bnx2x *bp)
8980 {
8981         if (!CHIP_IS_E1(bp)) {
8982                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8983                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8984                 mmiowb();
8985         }
8986 }
8987
8988 /*
8989  * Reset the whole chip except for:
8990  *      - PCIE core
8991  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8992  *              one reset bit)
8993  *      - IGU
8994  *      - MISC (including AEU)
8995  *      - GRC
8996  *      - RBCN, RBCP
8997  */
8998 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8999 {
9000         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9001         u32 global_bits2, stay_reset2;
9002
9003         /*
9004          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9005          * (per chip) blocks.
9006          */
9007         global_bits2 =
9008                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9009                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9010
9011         /* Don't reset the following blocks.
9012          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9013          *            reset, as in 4 port device they might still be owned
9014          *            by the MCP (there is only one leader per path).
9015          */
9016         not_reset_mask1 =
9017                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9018                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9019                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9020
9021         not_reset_mask2 =
9022                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9023                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9024                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9025                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9026                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9027                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9028                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9029                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9030                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9031                 MISC_REGISTERS_RESET_REG_2_PGLC |
9032                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9033                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9034                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9035                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9036                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9037                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9038
9039         /*
9040          * Keep the following blocks in reset:
9041          *  - all xxMACs are handled by the bnx2x_link code.
9042          */
9043         stay_reset2 =
9044                 MISC_REGISTERS_RESET_REG_2_XMAC |
9045                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9046
9047         /* Full reset masks according to the chip */
9048         reset_mask1 = 0xffffffff;
9049
9050         if (CHIP_IS_E1(bp))
9051                 reset_mask2 = 0xffff;
9052         else if (CHIP_IS_E1H(bp))
9053                 reset_mask2 = 0x1ffff;
9054         else if (CHIP_IS_E2(bp))
9055                 reset_mask2 = 0xfffff;
9056         else /* CHIP_IS_E3 */
9057                 reset_mask2 = 0x3ffffff;
9058
9059         /* Don't reset global blocks unless we need to */
9060         if (!global)
9061                 reset_mask2 &= ~global_bits2;
9062
9063         /*
9064          * In case of attention in the QM, we need to reset PXP
9065          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9066          * because otherwise QM reset would release 'close the gates' shortly
9067          * before resetting the PXP, then the PSWRQ would send a write
9068          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9069          * read the payload data from PSWWR, but PSWWR would not
9070          * respond. The write queue in PGLUE would stuck, dmae commands
9071          * would not return. Therefore it's important to reset the second
9072          * reset register (containing the
9073          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9074          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9075          * bit).
9076          */
9077         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9078                reset_mask2 & (~not_reset_mask2));
9079
9080         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9081                reset_mask1 & (~not_reset_mask1));
9082
9083         barrier();
9084         mmiowb();
9085
9086         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9087                reset_mask2 & (~stay_reset2));
9088
9089         barrier();
9090         mmiowb();
9091
9092         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9093         mmiowb();
9094 }
9095
9096 /**
9097  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9098  * It should get cleared in no more than 1s.
9099  *
9100  * @bp: driver handle
9101  *
9102  * It should get cleared in no more than 1s. Returns 0 if
9103  * pending writes bit gets cleared.
9104  */
9105 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9106 {
9107         u32 cnt = 1000;
9108         u32 pend_bits = 0;
9109
9110         do {
9111                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9112
9113                 if (pend_bits == 0)
9114                         break;
9115
9116                 usleep_range(1000, 2000);
9117         } while (cnt-- > 0);
9118
9119         if (cnt <= 0) {
9120                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9121                           pend_bits);
9122                 return -EBUSY;
9123         }
9124
9125         return 0;
9126 }
9127
9128 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9129 {
9130         int cnt = 1000;
9131         u32 val = 0;
9132         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9133         u32 tags_63_32 = 0;
9134
9135         /* Empty the Tetris buffer, wait for 1s */
9136         do {
9137                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9138                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9139                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9140                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9141                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9142                 if (CHIP_IS_E3(bp))
9143                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9144
9145                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9146                     ((port_is_idle_0 & 0x1) == 0x1) &&
9147                     ((port_is_idle_1 & 0x1) == 0x1) &&
9148                     (pgl_exp_rom2 == 0xffffffff) &&
9149                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9150                         break;
9151                 usleep_range(1000, 2000);
9152         } while (cnt-- > 0);
9153
9154         if (cnt <= 0) {
9155                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9156                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9157                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9158                           pgl_exp_rom2);
9159                 return -EAGAIN;
9160         }
9161
9162         barrier();
9163
9164         /* Close gates #2, #3 and #4 */
9165         bnx2x_set_234_gates(bp, true);
9166
9167         /* Poll for IGU VQs for 57712 and newer chips */
9168         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9169                 return -EAGAIN;
9170
9171
9172         /* TBD: Indicate that "process kill" is in progress to MCP */
9173
9174         /* Clear "unprepared" bit */
9175         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9176         barrier();
9177
9178         /* Make sure all is written to the chip before the reset */
9179         mmiowb();
9180
9181         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9182          * PSWHST, GRC and PSWRD Tetris buffer.
9183          */
9184         usleep_range(1000, 2000);
9185
9186         /* Prepare to chip reset: */
9187         /* MCP */
9188         if (global)
9189                 bnx2x_reset_mcp_prep(bp, &val);
9190
9191         /* PXP */
9192         bnx2x_pxp_prep(bp);
9193         barrier();
9194
9195         /* reset the chip */
9196         bnx2x_process_kill_chip_reset(bp, global);
9197         barrier();
9198
9199         /* Recover after reset: */
9200         /* MCP */
9201         if (global && bnx2x_reset_mcp_comp(bp, val))
9202                 return -EAGAIN;
9203
9204         /* TBD: Add resetting the NO_MCP mode DB here */
9205
9206         /* Open the gates #2, #3 and #4 */
9207         bnx2x_set_234_gates(bp, false);
9208
9209         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9210          * reset state, re-enable attentions. */
9211
9212         return 0;
9213 }
9214
9215 static int bnx2x_leader_reset(struct bnx2x *bp)
9216 {
9217         int rc = 0;
9218         bool global = bnx2x_reset_is_global(bp);
9219         u32 load_code;
9220
9221         /* if not going to reset MCP - load "fake" driver to reset HW while
9222          * driver is owner of the HW
9223          */
9224         if (!global && !BP_NOMCP(bp)) {
9225                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9226                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9227                 if (!load_code) {
9228                         BNX2X_ERR("MCP response failure, aborting\n");
9229                         rc = -EAGAIN;
9230                         goto exit_leader_reset;
9231                 }
9232                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9233                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9234                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9235                         rc = -EAGAIN;
9236                         goto exit_leader_reset2;
9237                 }
9238                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9239                 if (!load_code) {
9240                         BNX2X_ERR("MCP response failure, aborting\n");
9241                         rc = -EAGAIN;
9242                         goto exit_leader_reset2;
9243                 }
9244         }
9245
9246         /* Try to recover after the failure */
9247         if (bnx2x_process_kill(bp, global)) {
9248                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9249                           BP_PATH(bp));
9250                 rc = -EAGAIN;
9251                 goto exit_leader_reset2;
9252         }
9253
9254         /*
9255          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9256          * state.
9257          */
9258         bnx2x_set_reset_done(bp);
9259         if (global)
9260                 bnx2x_clear_reset_global(bp);
9261
9262 exit_leader_reset2:
9263         /* unload "fake driver" if it was loaded */
9264         if (!global && !BP_NOMCP(bp)) {
9265                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9266                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9267         }
9268 exit_leader_reset:
9269         bp->is_leader = 0;
9270         bnx2x_release_leader_lock(bp);
9271         smp_mb();
9272         return rc;
9273 }
9274
9275 static void bnx2x_recovery_failed(struct bnx2x *bp)
9276 {
9277         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9278
9279         /* Disconnect this device */
9280         netif_device_detach(bp->dev);
9281
9282         /*
9283          * Block ifup for all function on this engine until "process kill"
9284          * or power cycle.
9285          */
9286         bnx2x_set_reset_in_progress(bp);
9287
9288         /* Shut down the power */
9289         bnx2x_set_power_state(bp, PCI_D3hot);
9290
9291         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9292
9293         smp_mb();
9294 }
9295
9296 /*
9297  * Assumption: runs under rtnl lock. This together with the fact
9298  * that it's called only from bnx2x_sp_rtnl() ensure that it
9299  * will never be called when netif_running(bp->dev) is false.
9300  */
9301 static void bnx2x_parity_recover(struct bnx2x *bp)
9302 {
9303         bool global = false;
9304         u32 error_recovered, error_unrecovered;
9305         bool is_parity;
9306
9307         DP(NETIF_MSG_HW, "Handling parity\n");
9308         while (1) {
9309                 switch (bp->recovery_state) {
9310                 case BNX2X_RECOVERY_INIT:
9311                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9312                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9313                         WARN_ON(!is_parity);
9314
9315                         /* Try to get a LEADER_LOCK HW lock */
9316                         if (bnx2x_trylock_leader_lock(bp)) {
9317                                 bnx2x_set_reset_in_progress(bp);
9318                                 /*
9319                                  * Check if there is a global attention and if
9320                                  * there was a global attention, set the global
9321                                  * reset bit.
9322                                  */
9323
9324                                 if (global)
9325                                         bnx2x_set_reset_global(bp);
9326
9327                                 bp->is_leader = 1;
9328                         }
9329
9330                         /* Stop the driver */
9331                         /* If interface has been removed - break */
9332                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9333                                 return;
9334
9335                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9336
9337                         /* Ensure "is_leader", MCP command sequence and
9338                          * "recovery_state" update values are seen on other
9339                          * CPUs.
9340                          */
9341                         smp_mb();
9342                         break;
9343
9344                 case BNX2X_RECOVERY_WAIT:
9345                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9346                         if (bp->is_leader) {
9347                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9348                                 bool other_load_status =
9349                                         bnx2x_get_load_status(bp, other_engine);
9350                                 bool load_status =
9351                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9352                                 global = bnx2x_reset_is_global(bp);
9353
9354                                 /*
9355                                  * In case of a parity in a global block, let
9356                                  * the first leader that performs a
9357                                  * leader_reset() reset the global blocks in
9358                                  * order to clear global attentions. Otherwise
9359                                  * the the gates will remain closed for that
9360                                  * engine.
9361                                  */
9362                                 if (load_status ||
9363                                     (global && other_load_status)) {
9364                                         /* Wait until all other functions get
9365                                          * down.
9366                                          */
9367                                         schedule_delayed_work(&bp->sp_rtnl_task,
9368                                                                 HZ/10);
9369                                         return;
9370                                 } else {
9371                                         /* If all other functions got down -
9372                                          * try to bring the chip back to
9373                                          * normal. In any case it's an exit
9374                                          * point for a leader.
9375                                          */
9376                                         if (bnx2x_leader_reset(bp)) {
9377                                                 bnx2x_recovery_failed(bp);
9378                                                 return;
9379                                         }
9380
9381                                         /* If we are here, means that the
9382                                          * leader has succeeded and doesn't
9383                                          * want to be a leader any more. Try
9384                                          * to continue as a none-leader.
9385                                          */
9386                                         break;
9387                                 }
9388                         } else { /* non-leader */
9389                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9390                                         /* Try to get a LEADER_LOCK HW lock as
9391                                          * long as a former leader may have
9392                                          * been unloaded by the user or
9393                                          * released a leadership by another
9394                                          * reason.
9395                                          */
9396                                         if (bnx2x_trylock_leader_lock(bp)) {
9397                                                 /* I'm a leader now! Restart a
9398                                                  * switch case.
9399                                                  */
9400                                                 bp->is_leader = 1;
9401                                                 break;
9402                                         }
9403
9404                                         schedule_delayed_work(&bp->sp_rtnl_task,
9405                                                                 HZ/10);
9406                                         return;
9407
9408                                 } else {
9409                                         /*
9410                                          * If there was a global attention, wait
9411                                          * for it to be cleared.
9412                                          */
9413                                         if (bnx2x_reset_is_global(bp)) {
9414                                                 schedule_delayed_work(
9415                                                         &bp->sp_rtnl_task,
9416                                                         HZ/10);
9417                                                 return;
9418                                         }
9419
9420                                         error_recovered =
9421                                           bp->eth_stats.recoverable_error;
9422                                         error_unrecovered =
9423                                           bp->eth_stats.unrecoverable_error;
9424                                         bp->recovery_state =
9425                                                 BNX2X_RECOVERY_NIC_LOADING;
9426                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9427                                                 error_unrecovered++;
9428                                                 netdev_err(bp->dev,
9429                                                            "Recovery failed. Power cycle needed\n");
9430                                                 /* Disconnect this device */
9431                                                 netif_device_detach(bp->dev);
9432                                                 /* Shut down the power */
9433                                                 bnx2x_set_power_state(
9434                                                         bp, PCI_D3hot);
9435                                                 smp_mb();
9436                                         } else {
9437                                                 bp->recovery_state =
9438                                                         BNX2X_RECOVERY_DONE;
9439                                                 error_recovered++;
9440                                                 smp_mb();
9441                                         }
9442                                         bp->eth_stats.recoverable_error =
9443                                                 error_recovered;
9444                                         bp->eth_stats.unrecoverable_error =
9445                                                 error_unrecovered;
9446
9447                                         return;
9448                                 }
9449                         }
9450                 default:
9451                         return;
9452                 }
9453         }
9454 }
9455
9456 static int bnx2x_close(struct net_device *dev);
9457
9458 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9459  * scheduled on a general queue in order to prevent a dead lock.
9460  */
9461 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9462 {
9463         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9464
9465         rtnl_lock();
9466
9467         if (!netif_running(bp->dev)) {
9468                 rtnl_unlock();
9469                 return;
9470         }
9471
9472         /* if stop on error is defined no recovery flows should be executed */
9473 #ifdef BNX2X_STOP_ON_ERROR
9474         BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9475                   "you will need to reboot when done\n");
9476         goto sp_rtnl_not_reset;
9477 #endif
9478
9479         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9480                 /*
9481                  * Clear all pending SP commands as we are going to reset the
9482                  * function anyway.
9483                  */
9484                 bp->sp_rtnl_state = 0;
9485                 smp_mb();
9486
9487                 bnx2x_parity_recover(bp);
9488
9489                 rtnl_unlock();
9490                 return;
9491         }
9492
9493         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9494                 /*
9495                  * Clear all pending SP commands as we are going to reset the
9496                  * function anyway.
9497                  */
9498                 bp->sp_rtnl_state = 0;
9499                 smp_mb();
9500
9501                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9502                 bnx2x_nic_load(bp, LOAD_NORMAL);
9503
9504                 rtnl_unlock();
9505                 return;
9506         }
9507 #ifdef BNX2X_STOP_ON_ERROR
9508 sp_rtnl_not_reset:
9509 #endif
9510         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9511                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9512         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9513                 bnx2x_after_function_update(bp);
9514         /*
9515          * in case of fan failure we need to reset id if the "stop on error"
9516          * debug flag is set, since we trying to prevent permanent overheating
9517          * damage
9518          */
9519         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9520                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9521                 netif_device_detach(bp->dev);
9522                 bnx2x_close(bp->dev);
9523                 rtnl_unlock();
9524                 return;
9525         }
9526
9527         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9528                 DP(BNX2X_MSG_SP,
9529                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9530                 bnx2x_vfpf_set_mcast(bp->dev);
9531         }
9532
9533         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9534                                &bp->sp_rtnl_state)) {
9535                 DP(BNX2X_MSG_SP,
9536                    "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9537                 bnx2x_vfpf_storm_rx_mode(bp);
9538         }
9539
9540         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9541                                &bp->sp_rtnl_state))
9542                 bnx2x_pf_set_vfs_vlan(bp);
9543
9544         /* work which needs rtnl lock not-taken (as it takes the lock itself and
9545          * can be called from other contexts as well)
9546          */
9547         rtnl_unlock();
9548
9549         /* enable SR-IOV if applicable */
9550         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9551                                                &bp->sp_rtnl_state)) {
9552                 bnx2x_disable_sriov(bp);
9553                 bnx2x_enable_sriov(bp);
9554         }
9555 }
9556
9557 static void bnx2x_period_task(struct work_struct *work)
9558 {
9559         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9560
9561         if (!netif_running(bp->dev))
9562                 goto period_task_exit;
9563
9564         if (CHIP_REV_IS_SLOW(bp)) {
9565                 BNX2X_ERR("period task called on emulation, ignoring\n");
9566                 goto period_task_exit;
9567         }
9568
9569         bnx2x_acquire_phy_lock(bp);
9570         /*
9571          * The barrier is needed to ensure the ordering between the writing to
9572          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9573          * the reading here.
9574          */
9575         smp_mb();
9576         if (bp->port.pmf) {
9577                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9578
9579                 /* Re-queue task in 1 sec */
9580                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9581         }
9582
9583         bnx2x_release_phy_lock(bp);
9584 period_task_exit:
9585         return;
9586 }
9587
9588 /*
9589  * Init service functions
9590  */
9591
9592 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9593 {
9594         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9595         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9596         return base + (BP_ABS_FUNC(bp)) * stride;
9597 }
9598
9599 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9600                                         struct bnx2x_mac_vals *vals)
9601 {
9602         u32 val, base_addr, offset, mask, reset_reg;
9603         bool mac_stopped = false;
9604         u8 port = BP_PORT(bp);
9605
9606         /* reset addresses as they also mark which values were changed */
9607         vals->bmac_addr = 0;
9608         vals->umac_addr = 0;
9609         vals->xmac_addr = 0;
9610         vals->emac_addr = 0;
9611
9612         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9613
9614         if (!CHIP_IS_E3(bp)) {
9615                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9616                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9617                 if ((mask & reset_reg) && val) {
9618                         u32 wb_data[2];
9619                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9620                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9621                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9622                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9623                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9624
9625                         /*
9626                          * use rd/wr since we cannot use dmae. This is safe
9627                          * since MCP won't access the bus due to the request
9628                          * to unload, and no function on the path can be
9629                          * loaded at this time.
9630                          */
9631                         wb_data[0] = REG_RD(bp, base_addr + offset);
9632                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9633                         vals->bmac_addr = base_addr + offset;
9634                         vals->bmac_val[0] = wb_data[0];
9635                         vals->bmac_val[1] = wb_data[1];
9636                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9637                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
9638                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9639
9640                 }
9641                 BNX2X_DEV_INFO("Disable emac Rx\n");
9642                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9643                 vals->emac_val = REG_RD(bp, vals->emac_addr);
9644                 REG_WR(bp, vals->emac_addr, 0);
9645                 mac_stopped = true;
9646         } else {
9647                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9648                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9649                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9650                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9651                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9652                                val & ~(1 << 1));
9653                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9654                                val | (1 << 1));
9655                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9656                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9657                         REG_WR(bp, vals->xmac_addr, 0);
9658                         mac_stopped = true;
9659                 }
9660                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9661                 if (mask & reset_reg) {
9662                         BNX2X_DEV_INFO("Disable umac Rx\n");
9663                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9664                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9665                         vals->umac_val = REG_RD(bp, vals->umac_addr);
9666                         REG_WR(bp, vals->umac_addr, 0);
9667                         mac_stopped = true;
9668                 }
9669         }
9670
9671         if (mac_stopped)
9672                 msleep(20);
9673
9674 }
9675
9676 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9677 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9678 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9679 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9680
9681 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9682 {
9683         u16 rcq, bd;
9684         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9685
9686         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9687         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9688
9689         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9690         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9691
9692         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9693                        port, bd, rcq);
9694 }
9695
9696 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9697 {
9698         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9699                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9700         if (!rc) {
9701                 BNX2X_ERR("MCP response failure, aborting\n");
9702                 return -EBUSY;
9703         }
9704
9705         return 0;
9706 }
9707
9708 static struct bnx2x_prev_path_list *
9709                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9710 {
9711         struct bnx2x_prev_path_list *tmp_list;
9712
9713         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9714                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9715                     bp->pdev->bus->number == tmp_list->bus &&
9716                     BP_PATH(bp) == tmp_list->path)
9717                         return tmp_list;
9718
9719         return NULL;
9720 }
9721
9722 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9723 {
9724         struct bnx2x_prev_path_list *tmp_list;
9725         int rc;
9726
9727         rc = down_interruptible(&bnx2x_prev_sem);
9728         if (rc) {
9729                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9730                 return rc;
9731         }
9732
9733         tmp_list = bnx2x_prev_path_get_entry(bp);
9734         if (tmp_list) {
9735                 tmp_list->aer = 1;
9736                 rc = 0;
9737         } else {
9738                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9739                           BP_PATH(bp));
9740         }
9741
9742         up(&bnx2x_prev_sem);
9743
9744         return rc;
9745 }
9746
9747 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9748 {
9749         struct bnx2x_prev_path_list *tmp_list;
9750         int rc = false;
9751
9752         if (down_trylock(&bnx2x_prev_sem))
9753                 return false;
9754
9755         tmp_list = bnx2x_prev_path_get_entry(bp);
9756         if (tmp_list) {
9757                 if (tmp_list->aer) {
9758                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9759                            BP_PATH(bp));
9760                 } else {
9761                         rc = true;
9762                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9763                                        BP_PATH(bp));
9764                 }
9765         }
9766
9767         up(&bnx2x_prev_sem);
9768
9769         return rc;
9770 }
9771
9772 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9773 {
9774         struct bnx2x_prev_path_list *tmp_list;
9775         int rc;
9776
9777         rc = down_interruptible(&bnx2x_prev_sem);
9778         if (rc) {
9779                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9780                 return rc;
9781         }
9782
9783         /* Check whether the entry for this path already exists */
9784         tmp_list = bnx2x_prev_path_get_entry(bp);
9785         if (tmp_list) {
9786                 if (!tmp_list->aer) {
9787                         BNX2X_ERR("Re-Marking the path.\n");
9788                 } else {
9789                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
9790                            BP_PATH(bp));
9791                         tmp_list->aer = 0;
9792                 }
9793                 up(&bnx2x_prev_sem);
9794                 return 0;
9795         }
9796         up(&bnx2x_prev_sem);
9797
9798         /* Create an entry for this path and add it */
9799         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9800         if (!tmp_list) {
9801                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9802                 return -ENOMEM;
9803         }
9804
9805         tmp_list->bus = bp->pdev->bus->number;
9806         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9807         tmp_list->path = BP_PATH(bp);
9808         tmp_list->aer = 0;
9809         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9810
9811         rc = down_interruptible(&bnx2x_prev_sem);
9812         if (rc) {
9813                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9814                 kfree(tmp_list);
9815         } else {
9816                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
9817                    BP_PATH(bp));
9818                 list_add(&tmp_list->list, &bnx2x_prev_list);
9819                 up(&bnx2x_prev_sem);
9820         }
9821
9822         return rc;
9823 }
9824
9825 static int bnx2x_do_flr(struct bnx2x *bp)
9826 {
9827         int i;
9828         u16 status;
9829         struct pci_dev *dev = bp->pdev;
9830
9831
9832         if (CHIP_IS_E1x(bp)) {
9833                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9834                 return -EINVAL;
9835         }
9836
9837         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9838         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9839                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9840                           bp->common.bc_ver);
9841                 return -EINVAL;
9842         }
9843
9844         /* Wait for Transaction Pending bit clean */
9845         for (i = 0; i < 4; i++) {
9846                 if (i)
9847                         msleep((1 << (i - 1)) * 100);
9848
9849                 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9850                 if (!(status & PCI_EXP_DEVSTA_TRPND))
9851                         goto clear;
9852         }
9853
9854         dev_err(&dev->dev,
9855                 "transaction is not cleared; proceeding with reset anyway\n");
9856
9857 clear:
9858
9859         BNX2X_DEV_INFO("Initiating FLR\n");
9860         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9861
9862         return 0;
9863 }
9864
9865 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9866 {
9867         int rc;
9868
9869         BNX2X_DEV_INFO("Uncommon unload Flow\n");
9870
9871         /* Test if previous unload process was already finished for this path */
9872         if (bnx2x_prev_is_path_marked(bp))
9873                 return bnx2x_prev_mcp_done(bp);
9874
9875         BNX2X_DEV_INFO("Path is unmarked\n");
9876
9877         /* If function has FLR capabilities, and existing FW version matches
9878          * the one required, then FLR will be sufficient to clean any residue
9879          * left by previous driver
9880          */
9881         rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9882
9883         if (!rc) {
9884                 /* fw version is good */
9885                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9886                 rc = bnx2x_do_flr(bp);
9887         }
9888
9889         if (!rc) {
9890                 /* FLR was performed */
9891                 BNX2X_DEV_INFO("FLR successful\n");
9892                 return 0;
9893         }
9894
9895         BNX2X_DEV_INFO("Could not FLR\n");
9896
9897         /* Close the MCP request, return failure*/
9898         rc = bnx2x_prev_mcp_done(bp);
9899         if (!rc)
9900                 rc = BNX2X_PREV_WAIT_NEEDED;
9901
9902         return rc;
9903 }
9904
9905 static int bnx2x_prev_unload_common(struct bnx2x *bp)
9906 {
9907         u32 reset_reg, tmp_reg = 0, rc;
9908         bool prev_undi = false;
9909         struct bnx2x_mac_vals mac_vals;
9910
9911         /* It is possible a previous function received 'common' answer,
9912          * but hasn't loaded yet, therefore creating a scenario of
9913          * multiple functions receiving 'common' on the same path.
9914          */
9915         BNX2X_DEV_INFO("Common unload Flow\n");
9916
9917         memset(&mac_vals, 0, sizeof(mac_vals));
9918
9919         if (bnx2x_prev_is_path_marked(bp))
9920                 return bnx2x_prev_mcp_done(bp);
9921
9922         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9923
9924         /* Reset should be performed after BRB is emptied */
9925         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9926                 u32 timer_count = 1000;
9927
9928                 /* Close the MAC Rx to prevent BRB from filling up */
9929                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
9930
9931                 /* close LLH filters towards the BRB */
9932                 bnx2x_set_rx_filter(&bp->link_params, 0);
9933
9934                 /* Check if the UNDI driver was previously loaded
9935                  * UNDI driver initializes CID offset for normal bell to 0x7
9936                  */
9937                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9938                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9939                         if (tmp_reg == 0x7) {
9940                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
9941                                 prev_undi = true;
9942                                 /* clear the UNDI indication */
9943                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9944                                 /* clear possible idle check errors */
9945                                 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
9946                         }
9947                 }
9948                 /* wait until BRB is empty */
9949                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9950                 while (timer_count) {
9951                         u32 prev_brb = tmp_reg;
9952
9953                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9954                         if (!tmp_reg)
9955                                 break;
9956
9957                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9958
9959                         /* reset timer as long as BRB actually gets emptied */
9960                         if (prev_brb > tmp_reg)
9961                                 timer_count = 1000;
9962                         else
9963                                 timer_count--;
9964
9965                         /* If UNDI resides in memory, manually increment it */
9966                         if (prev_undi)
9967                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9968
9969                         udelay(10);
9970                 }
9971
9972                 if (!timer_count)
9973                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9974
9975         }
9976
9977         /* No packets are in the pipeline, path is ready for reset */
9978         bnx2x_reset_common(bp);
9979
9980         if (mac_vals.xmac_addr)
9981                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
9982         if (mac_vals.umac_addr)
9983                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
9984         if (mac_vals.emac_addr)
9985                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
9986         if (mac_vals.bmac_addr) {
9987                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9988                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9989         }
9990
9991         rc = bnx2x_prev_mark_path(bp, prev_undi);
9992         if (rc) {
9993                 bnx2x_prev_mcp_done(bp);
9994                 return rc;
9995         }
9996
9997         return bnx2x_prev_mcp_done(bp);
9998 }
9999
10000 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10001  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10002  * the addresses of the transaction, resulting in was-error bit set in the pci
10003  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10004  * to clear the interrupt which detected this from the pglueb and the was done
10005  * bit
10006  */
10007 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10008 {
10009         if (!CHIP_IS_E1x(bp)) {
10010                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10011                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10012                         DP(BNX2X_MSG_SP,
10013                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10014                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10015                                1 << BP_FUNC(bp));
10016                 }
10017         }
10018 }
10019
10020 static int bnx2x_prev_unload(struct bnx2x *bp)
10021 {
10022         int time_counter = 10;
10023         u32 rc, fw, hw_lock_reg, hw_lock_val;
10024         struct bnx2x_prev_path_list *prev_list;
10025         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10026
10027         /* clear hw from errors which may have resulted from an interrupted
10028          * dmae transaction.
10029          */
10030         bnx2x_prev_interrupted_dmae(bp);
10031
10032         /* Release previously held locks */
10033         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10034                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10035                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10036
10037         hw_lock_val = (REG_RD(bp, hw_lock_reg));
10038         if (hw_lock_val) {
10039                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10040                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10041                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10042                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10043                 }
10044
10045                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10046                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10047         } else
10048                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10049
10050         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10051                 BNX2X_DEV_INFO("Release previously held alr\n");
10052                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
10053         }
10054
10055         do {
10056                 int aer = 0;
10057                 /* Lock MCP using an unload request */
10058                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10059                 if (!fw) {
10060                         BNX2X_ERR("MCP response failure, aborting\n");
10061                         rc = -EBUSY;
10062                         break;
10063                 }
10064
10065                 rc = down_interruptible(&bnx2x_prev_sem);
10066                 if (rc) {
10067                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10068                                   rc);
10069                 } else {
10070                         /* If Path is marked by EEH, ignore unload status */
10071                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10072                                  bnx2x_prev_path_get_entry(bp)->aer);
10073                 }
10074                 up(&bnx2x_prev_sem);
10075
10076                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10077                         rc = bnx2x_prev_unload_common(bp);
10078                         break;
10079                 }
10080
10081                 /* non-common reply from MCP night require looping */
10082                 rc = bnx2x_prev_unload_uncommon(bp);
10083                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10084                         break;
10085
10086                 msleep(20);
10087         } while (--time_counter);
10088
10089         if (!time_counter || rc) {
10090                 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10091                 rc = -EBUSY;
10092         }
10093
10094         /* Mark function if its port was used to boot from SAN */
10095         prev_list = bnx2x_prev_path_get_entry(bp);
10096         if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
10097                 bp->link_params.feature_config_flags |=
10098                         FEATURE_CONFIG_BOOT_FROM_SAN;
10099
10100         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10101
10102         return rc;
10103 }
10104
10105 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10106 {
10107         u32 val, val2, val3, val4, id, boot_mode;
10108         u16 pmc;
10109
10110         /* Get the chip revision id and number. */
10111         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10112         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10113         id = ((val & 0xffff) << 16);
10114         val = REG_RD(bp, MISC_REG_CHIP_REV);
10115         id |= ((val & 0xf) << 12);
10116
10117         /* Metal is read from PCI regs, but we can't access >=0x400 from
10118          * the configuration space (so we need to reg_rd)
10119          */
10120         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10121         id |= (((val >> 24) & 0xf) << 4);
10122         val = REG_RD(bp, MISC_REG_BOND_ID);
10123         id |= (val & 0xf);
10124         bp->common.chip_id = id;
10125
10126         /* force 57811 according to MISC register */
10127         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10128                 if (CHIP_IS_57810(bp))
10129                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10130                                 (bp->common.chip_id & 0x0000FFFF);
10131                 else if (CHIP_IS_57810_MF(bp))
10132                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10133                                 (bp->common.chip_id & 0x0000FFFF);
10134                 bp->common.chip_id |= 0x1;
10135         }
10136
10137         /* Set doorbell size */
10138         bp->db_size = (1 << BNX2X_DB_SHIFT);
10139
10140         if (!CHIP_IS_E1x(bp)) {
10141                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10142                 if ((val & 1) == 0)
10143                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10144                 else
10145                         val = (val >> 1) & 1;
10146                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10147                                                        "2_PORT_MODE");
10148                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10149                                                  CHIP_2_PORT_MODE;
10150
10151                 if (CHIP_MODE_IS_4_PORT(bp))
10152                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10153                 else
10154                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10155         } else {
10156                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10157                 bp->pfid = bp->pf_num;                  /* 0..7 */
10158         }
10159
10160         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10161
10162         bp->link_params.chip_id = bp->common.chip_id;
10163         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10164
10165         val = (REG_RD(bp, 0x2874) & 0x55);
10166         if ((bp->common.chip_id & 0x1) ||
10167             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10168                 bp->flags |= ONE_PORT_FLAG;
10169                 BNX2X_DEV_INFO("single port device\n");
10170         }
10171
10172         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10173         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10174                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10175         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10176                        bp->common.flash_size, bp->common.flash_size);
10177
10178         bnx2x_init_shmem(bp);
10179
10180
10181
10182         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10183                                         MISC_REG_GENERIC_CR_1 :
10184                                         MISC_REG_GENERIC_CR_0));
10185
10186         bp->link_params.shmem_base = bp->common.shmem_base;
10187         bp->link_params.shmem2_base = bp->common.shmem2_base;
10188         if (SHMEM2_RD(bp, size) >
10189             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10190                 bp->link_params.lfa_base =
10191                 REG_RD(bp, bp->common.shmem2_base +
10192                        (u32)offsetof(struct shmem2_region,
10193                                      lfa_host_addr[BP_PORT(bp)]));
10194         else
10195                 bp->link_params.lfa_base = 0;
10196         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10197                        bp->common.shmem_base, bp->common.shmem2_base);
10198
10199         if (!bp->common.shmem_base) {
10200                 BNX2X_DEV_INFO("MCP not active\n");
10201                 bp->flags |= NO_MCP_FLAG;
10202                 return;
10203         }
10204
10205         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10206         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10207
10208         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10209                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10210                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10211
10212         bp->link_params.feature_config_flags = 0;
10213         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10214         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10215                 bp->link_params.feature_config_flags |=
10216                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10217         else
10218                 bp->link_params.feature_config_flags &=
10219                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10220
10221         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10222         bp->common.bc_ver = val;
10223         BNX2X_DEV_INFO("bc_ver %X\n", val);
10224         if (val < BNX2X_BC_VER) {
10225                 /* for now only warn
10226                  * later we might need to enforce this */
10227                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10228                           BNX2X_BC_VER, val);
10229         }
10230         bp->link_params.feature_config_flags |=
10231                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10232                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10233
10234         bp->link_params.feature_config_flags |=
10235                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10236                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10237         bp->link_params.feature_config_flags |=
10238                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10239                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10240         bp->link_params.feature_config_flags |=
10241                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10242                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10243
10244         bp->link_params.feature_config_flags |=
10245                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10246                 FEATURE_CONFIG_MT_SUPPORT : 0;
10247
10248         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10249                         BC_SUPPORTS_PFC_STATS : 0;
10250
10251         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10252                         BC_SUPPORTS_FCOE_FEATURES : 0;
10253
10254         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10255                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10256         boot_mode = SHMEM_RD(bp,
10257                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10258                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10259         switch (boot_mode) {
10260         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10261                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10262                 break;
10263         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10264                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10265                 break;
10266         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10267                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10268                 break;
10269         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10270                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10271                 break;
10272         }
10273
10274         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10275         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10276
10277         BNX2X_DEV_INFO("%sWoL capable\n",
10278                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10279
10280         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10281         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10282         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10283         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10284
10285         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10286                  val, val2, val3, val4);
10287 }
10288
10289 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10290 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10291
10292 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10293 {
10294         int pfid = BP_FUNC(bp);
10295         int igu_sb_id;
10296         u32 val;
10297         u8 fid, igu_sb_cnt = 0;
10298
10299         bp->igu_base_sb = 0xff;
10300         if (CHIP_INT_MODE_IS_BC(bp)) {
10301                 int vn = BP_VN(bp);
10302                 igu_sb_cnt = bp->igu_sb_cnt;
10303                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10304                         FP_SB_MAX_E1x;
10305
10306                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10307                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10308
10309                 return 0;
10310         }
10311
10312         /* IGU in normal mode - read CAM */
10313         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10314              igu_sb_id++) {
10315                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10316                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10317                         continue;
10318                 fid = IGU_FID(val);
10319                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10320                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10321                                 continue;
10322                         if (IGU_VEC(val) == 0)
10323                                 /* default status block */
10324                                 bp->igu_dsb_id = igu_sb_id;
10325                         else {
10326                                 if (bp->igu_base_sb == 0xff)
10327                                         bp->igu_base_sb = igu_sb_id;
10328                                 igu_sb_cnt++;
10329                         }
10330                 }
10331         }
10332
10333 #ifdef CONFIG_PCI_MSI
10334         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10335          * optional that number of CAM entries will not be equal to the value
10336          * advertised in PCI.
10337          * Driver should use the minimal value of both as the actual status
10338          * block count
10339          */
10340         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10341 #endif
10342
10343         if (igu_sb_cnt == 0) {
10344                 BNX2X_ERR("CAM configuration error\n");
10345                 return -EINVAL;
10346         }
10347
10348         return 0;
10349 }
10350
10351 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10352 {
10353         int cfg_size = 0, idx, port = BP_PORT(bp);
10354
10355         /* Aggregation of supported attributes of all external phys */
10356         bp->port.supported[0] = 0;
10357         bp->port.supported[1] = 0;
10358         switch (bp->link_params.num_phys) {
10359         case 1:
10360                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10361                 cfg_size = 1;
10362                 break;
10363         case 2:
10364                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10365                 cfg_size = 1;
10366                 break;
10367         case 3:
10368                 if (bp->link_params.multi_phy_config &
10369                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10370                         bp->port.supported[1] =
10371                                 bp->link_params.phy[EXT_PHY1].supported;
10372                         bp->port.supported[0] =
10373                                 bp->link_params.phy[EXT_PHY2].supported;
10374                 } else {
10375                         bp->port.supported[0] =
10376                                 bp->link_params.phy[EXT_PHY1].supported;
10377                         bp->port.supported[1] =
10378                                 bp->link_params.phy[EXT_PHY2].supported;
10379                 }
10380                 cfg_size = 2;
10381                 break;
10382         }
10383
10384         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10385                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10386                            SHMEM_RD(bp,
10387                            dev_info.port_hw_config[port].external_phy_config),
10388                            SHMEM_RD(bp,
10389                            dev_info.port_hw_config[port].external_phy_config2));
10390                         return;
10391         }
10392
10393         if (CHIP_IS_E3(bp))
10394                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10395         else {
10396                 switch (switch_cfg) {
10397                 case SWITCH_CFG_1G:
10398                         bp->port.phy_addr = REG_RD(
10399                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10400                         break;
10401                 case SWITCH_CFG_10G:
10402                         bp->port.phy_addr = REG_RD(
10403                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10404                         break;
10405                 default:
10406                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10407                                   bp->port.link_config[0]);
10408                         return;
10409                 }
10410         }
10411         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10412         /* mask what we support according to speed_cap_mask per configuration */
10413         for (idx = 0; idx < cfg_size; idx++) {
10414                 if (!(bp->link_params.speed_cap_mask[idx] &
10415                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10416                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10417
10418                 if (!(bp->link_params.speed_cap_mask[idx] &
10419                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10420                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10421
10422                 if (!(bp->link_params.speed_cap_mask[idx] &
10423                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10424                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10425
10426                 if (!(bp->link_params.speed_cap_mask[idx] &
10427                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10428                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10429
10430                 if (!(bp->link_params.speed_cap_mask[idx] &
10431                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10432                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10433                                                      SUPPORTED_1000baseT_Full);
10434
10435                 if (!(bp->link_params.speed_cap_mask[idx] &
10436                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10437                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10438
10439                 if (!(bp->link_params.speed_cap_mask[idx] &
10440                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10441                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10442
10443         }
10444
10445         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10446                        bp->port.supported[1]);
10447 }
10448
10449 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10450 {
10451         u32 link_config, idx, cfg_size = 0;
10452         bp->port.advertising[0] = 0;
10453         bp->port.advertising[1] = 0;
10454         switch (bp->link_params.num_phys) {
10455         case 1:
10456         case 2:
10457                 cfg_size = 1;
10458                 break;
10459         case 3:
10460                 cfg_size = 2;
10461                 break;
10462         }
10463         for (idx = 0; idx < cfg_size; idx++) {
10464                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10465                 link_config = bp->port.link_config[idx];
10466                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10467                 case PORT_FEATURE_LINK_SPEED_AUTO:
10468                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10469                                 bp->link_params.req_line_speed[idx] =
10470                                         SPEED_AUTO_NEG;
10471                                 bp->port.advertising[idx] |=
10472                                         bp->port.supported[idx];
10473                                 if (bp->link_params.phy[EXT_PHY1].type ==
10474                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10475                                         bp->port.advertising[idx] |=
10476                                         (SUPPORTED_100baseT_Half |
10477                                          SUPPORTED_100baseT_Full);
10478                         } else {
10479                                 /* force 10G, no AN */
10480                                 bp->link_params.req_line_speed[idx] =
10481                                         SPEED_10000;
10482                                 bp->port.advertising[idx] |=
10483                                         (ADVERTISED_10000baseT_Full |
10484                                          ADVERTISED_FIBRE);
10485                                 continue;
10486                         }
10487                         break;
10488
10489                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10490                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10491                                 bp->link_params.req_line_speed[idx] =
10492                                         SPEED_10;
10493                                 bp->port.advertising[idx] |=
10494                                         (ADVERTISED_10baseT_Full |
10495                                          ADVERTISED_TP);
10496                         } else {
10497                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10498                                             link_config,
10499                                     bp->link_params.speed_cap_mask[idx]);
10500                                 return;
10501                         }
10502                         break;
10503
10504                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10505                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10506                                 bp->link_params.req_line_speed[idx] =
10507                                         SPEED_10;
10508                                 bp->link_params.req_duplex[idx] =
10509                                         DUPLEX_HALF;
10510                                 bp->port.advertising[idx] |=
10511                                         (ADVERTISED_10baseT_Half |
10512                                          ADVERTISED_TP);
10513                         } else {
10514                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10515                                             link_config,
10516                                           bp->link_params.speed_cap_mask[idx]);
10517                                 return;
10518                         }
10519                         break;
10520
10521                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10522                         if (bp->port.supported[idx] &
10523                             SUPPORTED_100baseT_Full) {
10524                                 bp->link_params.req_line_speed[idx] =
10525                                         SPEED_100;
10526                                 bp->port.advertising[idx] |=
10527                                         (ADVERTISED_100baseT_Full |
10528                                          ADVERTISED_TP);
10529                         } else {
10530                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10531                                             link_config,
10532                                           bp->link_params.speed_cap_mask[idx]);
10533                                 return;
10534                         }
10535                         break;
10536
10537                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10538                         if (bp->port.supported[idx] &
10539                             SUPPORTED_100baseT_Half) {
10540                                 bp->link_params.req_line_speed[idx] =
10541                                                                 SPEED_100;
10542                                 bp->link_params.req_duplex[idx] =
10543                                                                 DUPLEX_HALF;
10544                                 bp->port.advertising[idx] |=
10545                                         (ADVERTISED_100baseT_Half |
10546                                          ADVERTISED_TP);
10547                         } else {
10548                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10549                                     link_config,
10550                                     bp->link_params.speed_cap_mask[idx]);
10551                                 return;
10552                         }
10553                         break;
10554
10555                 case PORT_FEATURE_LINK_SPEED_1G:
10556                         if (bp->port.supported[idx] &
10557                             SUPPORTED_1000baseT_Full) {
10558                                 bp->link_params.req_line_speed[idx] =
10559                                         SPEED_1000;
10560                                 bp->port.advertising[idx] |=
10561                                         (ADVERTISED_1000baseT_Full |
10562                                          ADVERTISED_TP);
10563                         } else {
10564                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10565                                     link_config,
10566                                     bp->link_params.speed_cap_mask[idx]);
10567                                 return;
10568                         }
10569                         break;
10570
10571                 case PORT_FEATURE_LINK_SPEED_2_5G:
10572                         if (bp->port.supported[idx] &
10573                             SUPPORTED_2500baseX_Full) {
10574                                 bp->link_params.req_line_speed[idx] =
10575                                         SPEED_2500;
10576                                 bp->port.advertising[idx] |=
10577                                         (ADVERTISED_2500baseX_Full |
10578                                                 ADVERTISED_TP);
10579                         } else {
10580                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10581                                     link_config,
10582                                     bp->link_params.speed_cap_mask[idx]);
10583                                 return;
10584                         }
10585                         break;
10586
10587                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10588                         if (bp->port.supported[idx] &
10589                             SUPPORTED_10000baseT_Full) {
10590                                 bp->link_params.req_line_speed[idx] =
10591                                         SPEED_10000;
10592                                 bp->port.advertising[idx] |=
10593                                         (ADVERTISED_10000baseT_Full |
10594                                                 ADVERTISED_FIBRE);
10595                         } else {
10596                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10597                                     link_config,
10598                                     bp->link_params.speed_cap_mask[idx]);
10599                                 return;
10600                         }
10601                         break;
10602                 case PORT_FEATURE_LINK_SPEED_20G:
10603                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10604
10605                         break;
10606                 default:
10607                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10608                                   link_config);
10609                                 bp->link_params.req_line_speed[idx] =
10610                                                         SPEED_AUTO_NEG;
10611                                 bp->port.advertising[idx] =
10612                                                 bp->port.supported[idx];
10613                         break;
10614                 }
10615
10616                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10617                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10618                 if (bp->link_params.req_flow_ctrl[idx] ==
10619                     BNX2X_FLOW_CTRL_AUTO) {
10620                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10621                                 bp->link_params.req_flow_ctrl[idx] =
10622                                                         BNX2X_FLOW_CTRL_NONE;
10623                         else
10624                                 bnx2x_set_requested_fc(bp);
10625                 }
10626
10627                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10628                                bp->link_params.req_line_speed[idx],
10629                                bp->link_params.req_duplex[idx],
10630                                bp->link_params.req_flow_ctrl[idx],
10631                                bp->port.advertising[idx]);
10632         }
10633 }
10634
10635 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10636 {
10637         __be16 mac_hi_be = cpu_to_be16(mac_hi);
10638         __be32 mac_lo_be = cpu_to_be32(mac_lo);
10639         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10640         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10641 }
10642
10643 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10644 {
10645         int port = BP_PORT(bp);
10646         u32 config;
10647         u32 ext_phy_type, ext_phy_config, eee_mode;
10648
10649         bp->link_params.bp = bp;
10650         bp->link_params.port = port;
10651
10652         bp->link_params.lane_config =
10653                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10654
10655         bp->link_params.speed_cap_mask[0] =
10656                 SHMEM_RD(bp,
10657                          dev_info.port_hw_config[port].speed_capability_mask);
10658         bp->link_params.speed_cap_mask[1] =
10659                 SHMEM_RD(bp,
10660                          dev_info.port_hw_config[port].speed_capability_mask2);
10661         bp->port.link_config[0] =
10662                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10663
10664         bp->port.link_config[1] =
10665                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10666
10667         bp->link_params.multi_phy_config =
10668                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10669         /* If the device is capable of WoL, set the default state according
10670          * to the HW
10671          */
10672         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10673         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10674                    (config & PORT_FEATURE_WOL_ENABLED));
10675
10676         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10677             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10678                 bp->flags |= NO_ISCSI_FLAG;
10679         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10680             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10681                 bp->flags |= NO_FCOE_FLAG;
10682
10683         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10684                        bp->link_params.lane_config,
10685                        bp->link_params.speed_cap_mask[0],
10686                        bp->port.link_config[0]);
10687
10688         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10689                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10690         bnx2x_phy_probe(&bp->link_params);
10691         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10692
10693         bnx2x_link_settings_requested(bp);
10694
10695         /*
10696          * If connected directly, work with the internal PHY, otherwise, work
10697          * with the external PHY
10698          */
10699         ext_phy_config =
10700                 SHMEM_RD(bp,
10701                          dev_info.port_hw_config[port].external_phy_config);
10702         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10703         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10704                 bp->mdio.prtad = bp->port.phy_addr;
10705
10706         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10707                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10708                 bp->mdio.prtad =
10709                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10710
10711         /* Configure link feature according to nvram value */
10712         eee_mode = (((SHMEM_RD(bp, dev_info.
10713                       port_feature_config[port].eee_power_mode)) &
10714                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10715                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10716         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10717                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10718                                            EEE_MODE_ENABLE_LPI |
10719                                            EEE_MODE_OUTPUT_TIME;
10720         } else {
10721                 bp->link_params.eee_mode = 0;
10722         }
10723 }
10724
10725 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10726 {
10727         u32 no_flags = NO_ISCSI_FLAG;
10728         int port = BP_PORT(bp);
10729         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10730                                 drv_lic_key[port].max_iscsi_conn);
10731
10732         if (!CNIC_SUPPORT(bp)) {
10733                 bp->flags |= no_flags;
10734                 return;
10735         }
10736
10737         /* Get the number of maximum allowed iSCSI connections */
10738         bp->cnic_eth_dev.max_iscsi_conn =
10739                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10740                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10741
10742         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10743                        bp->cnic_eth_dev.max_iscsi_conn);
10744
10745         /*
10746          * If maximum allowed number of connections is zero -
10747          * disable the feature.
10748          */
10749         if (!bp->cnic_eth_dev.max_iscsi_conn)
10750                 bp->flags |= no_flags;
10751
10752 }
10753
10754 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10755 {
10756         /* Port info */
10757         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10758                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10759         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10760                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10761
10762         /* Node info */
10763         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10764                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10765         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10766                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10767 }
10768 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10769 {
10770         int port = BP_PORT(bp);
10771         int func = BP_ABS_FUNC(bp);
10772         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10773                                 drv_lic_key[port].max_fcoe_conn);
10774
10775         if (!CNIC_SUPPORT(bp)) {
10776                 bp->flags |= NO_FCOE_FLAG;
10777                 return;
10778         }
10779
10780         /* Get the number of maximum allowed FCoE connections */
10781         bp->cnic_eth_dev.max_fcoe_conn =
10782                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10783                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10784
10785         /* Read the WWN: */
10786         if (!IS_MF(bp)) {
10787                 /* Port info */
10788                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10789                         SHMEM_RD(bp,
10790                                  dev_info.port_hw_config[port].
10791                                  fcoe_wwn_port_name_upper);
10792                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10793                         SHMEM_RD(bp,
10794                                  dev_info.port_hw_config[port].
10795                                  fcoe_wwn_port_name_lower);
10796
10797                 /* Node info */
10798                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10799                         SHMEM_RD(bp,
10800                                  dev_info.port_hw_config[port].
10801                                  fcoe_wwn_node_name_upper);
10802                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10803                         SHMEM_RD(bp,
10804                                  dev_info.port_hw_config[port].
10805                                  fcoe_wwn_node_name_lower);
10806         } else if (!IS_MF_SD(bp)) {
10807                 /*
10808                  * Read the WWN info only if the FCoE feature is enabled for
10809                  * this function.
10810                  */
10811                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10812                         bnx2x_get_ext_wwn_info(bp, func);
10813
10814         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10815                 bnx2x_get_ext_wwn_info(bp, func);
10816         }
10817
10818         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10819
10820         /*
10821          * If maximum allowed number of connections is zero -
10822          * disable the feature.
10823          */
10824         if (!bp->cnic_eth_dev.max_fcoe_conn)
10825                 bp->flags |= NO_FCOE_FLAG;
10826 }
10827
10828 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10829 {
10830         /*
10831          * iSCSI may be dynamically disabled but reading
10832          * info here we will decrease memory usage by driver
10833          * if the feature is disabled for good
10834          */
10835         bnx2x_get_iscsi_info(bp);
10836         bnx2x_get_fcoe_info(bp);
10837 }
10838
10839 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10840 {
10841         u32 val, val2;
10842         int func = BP_ABS_FUNC(bp);
10843         int port = BP_PORT(bp);
10844         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10845         u8 *fip_mac = bp->fip_mac;
10846
10847         if (IS_MF(bp)) {
10848                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10849                  * FCoE MAC then the appropriate feature should be disabled.
10850                  * In non SD mode features configuration comes from struct
10851                  * func_ext_config.
10852                  */
10853                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
10854                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10855                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10856                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10857                                                  iscsi_mac_addr_upper);
10858                                 val = MF_CFG_RD(bp, func_ext_config[func].
10859                                                 iscsi_mac_addr_lower);
10860                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10861                                 BNX2X_DEV_INFO
10862                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10863                         } else {
10864                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10865                         }
10866
10867                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10868                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10869                                                  fcoe_mac_addr_upper);
10870                                 val = MF_CFG_RD(bp, func_ext_config[func].
10871                                                 fcoe_mac_addr_lower);
10872                                 bnx2x_set_mac_buf(fip_mac, val, val2);
10873                                 BNX2X_DEV_INFO
10874                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
10875                         } else {
10876                                 bp->flags |= NO_FCOE_FLAG;
10877                         }
10878
10879                         bp->mf_ext_config = cfg;
10880
10881                 } else { /* SD MODE */
10882                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10883                                 /* use primary mac as iscsi mac */
10884                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10885
10886                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10887                                 BNX2X_DEV_INFO
10888                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10889                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10890                                 /* use primary mac as fip mac */
10891                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10892                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
10893                                 BNX2X_DEV_INFO
10894                                         ("Read FIP MAC: %pM\n", fip_mac);
10895                         }
10896                 }
10897
10898                 /* If this is a storage-only interface, use SAN mac as
10899                  * primary MAC. Notice that for SD this is already the case,
10900                  * as the SAN mac was copied from the primary MAC.
10901                  */
10902                 if (IS_MF_FCOE_AFEX(bp))
10903                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10904         } else {
10905                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10906                                 iscsi_mac_upper);
10907                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10908                                iscsi_mac_lower);
10909                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10910
10911                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10912                                 fcoe_fip_mac_upper);
10913                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10914                                fcoe_fip_mac_lower);
10915                 bnx2x_set_mac_buf(fip_mac, val, val2);
10916         }
10917
10918         /* Disable iSCSI OOO if MAC configuration is invalid. */
10919         if (!is_valid_ether_addr(iscsi_mac)) {
10920                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10921                 memset(iscsi_mac, 0, ETH_ALEN);
10922         }
10923
10924         /* Disable FCoE if MAC configuration is invalid. */
10925         if (!is_valid_ether_addr(fip_mac)) {
10926                 bp->flags |= NO_FCOE_FLAG;
10927                 memset(bp->fip_mac, 0, ETH_ALEN);
10928         }
10929 }
10930
10931 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10932 {
10933         u32 val, val2;
10934         int func = BP_ABS_FUNC(bp);
10935         int port = BP_PORT(bp);
10936
10937         /* Zero primary MAC configuration */
10938         memset(bp->dev->dev_addr, 0, ETH_ALEN);
10939
10940         if (BP_NOMCP(bp)) {
10941                 BNX2X_ERROR("warning: random MAC workaround active\n");
10942                 eth_hw_addr_random(bp->dev);
10943         } else if (IS_MF(bp)) {
10944                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10945                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10946                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10947                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10948                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10949
10950                 if (CNIC_SUPPORT(bp))
10951                         bnx2x_get_cnic_mac_hwinfo(bp);
10952         } else {
10953                 /* in SF read MACs from port configuration */
10954                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10955                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10956                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10957
10958                 if (CNIC_SUPPORT(bp))
10959                         bnx2x_get_cnic_mac_hwinfo(bp);
10960         }
10961
10962         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10963
10964         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10965                 dev_err(&bp->pdev->dev,
10966                         "bad Ethernet MAC address configuration: %pM\n"
10967                         "change it manually before bringing up the appropriate network interface\n",
10968                         bp->dev->dev_addr);
10969 }
10970
10971 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
10972 {
10973         int tmp;
10974         u32 cfg;
10975
10976         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10977                 /* Take function: tmp = func */
10978                 tmp = BP_ABS_FUNC(bp);
10979                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10980                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10981         } else {
10982                 /* Take port: tmp = port */
10983                 tmp = BP_PORT(bp);
10984                 cfg = SHMEM_RD(bp,
10985                                dev_info.port_hw_config[tmp].generic_features);
10986                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10987         }
10988         return cfg;
10989 }
10990
10991 static int bnx2x_get_hwinfo(struct bnx2x *bp)
10992 {
10993         int /*abs*/func = BP_ABS_FUNC(bp);
10994         int vn;
10995         u32 val = 0;
10996         int rc = 0;
10997
10998         bnx2x_get_common_hwinfo(bp);
10999
11000         /*
11001          * initialize IGU parameters
11002          */
11003         if (CHIP_IS_E1x(bp)) {
11004                 bp->common.int_block = INT_BLOCK_HC;
11005
11006                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11007                 bp->igu_base_sb = 0;
11008         } else {
11009                 bp->common.int_block = INT_BLOCK_IGU;
11010
11011                 /* do not allow device reset during IGU info preocessing */
11012                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11013
11014                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11015
11016                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11017                         int tout = 5000;
11018
11019                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11020
11021                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11022                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11023                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11024
11025                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11026                                 tout--;
11027                                 usleep_range(1000, 2000);
11028                         }
11029
11030                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11031                                 dev_err(&bp->pdev->dev,
11032                                         "FORCING Normal Mode failed!!!\n");
11033                                 bnx2x_release_hw_lock(bp,
11034                                                       HW_LOCK_RESOURCE_RESET);
11035                                 return -EPERM;
11036                         }
11037                 }
11038
11039                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11040                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11041                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11042                 } else
11043                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11044
11045                 rc = bnx2x_get_igu_cam_info(bp);
11046                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11047                 if (rc)
11048                         return rc;
11049         }
11050
11051         /*
11052          * set base FW non-default (fast path) status block id, this value is
11053          * used to initialize the fw_sb_id saved on the fp/queue structure to
11054          * determine the id used by the FW.
11055          */
11056         if (CHIP_IS_E1x(bp))
11057                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11058         else /*
11059               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11060               * the same queue are indicated on the same IGU SB). So we prefer
11061               * FW and IGU SBs to be the same value.
11062               */
11063                 bp->base_fw_ndsb = bp->igu_base_sb;
11064
11065         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11066                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11067                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11068
11069         /*
11070          * Initialize MF configuration
11071          */
11072
11073         bp->mf_ov = 0;
11074         bp->mf_mode = 0;
11075         vn = BP_VN(bp);
11076
11077         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11078                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11079                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11080                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11081
11082                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11083                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11084                 else
11085                         bp->common.mf_cfg_base = bp->common.shmem_base +
11086                                 offsetof(struct shmem_region, func_mb) +
11087                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11088                 /*
11089                  * get mf configuration:
11090                  * 1. existence of MF configuration
11091                  * 2. MAC address must be legal (check only upper bytes)
11092                  *    for  Switch-Independent mode;
11093                  *    OVLAN must be legal for Switch-Dependent mode
11094                  * 3. SF_MODE configures specific MF mode
11095                  */
11096                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11097                         /* get mf configuration */
11098                         val = SHMEM_RD(bp,
11099                                        dev_info.shared_feature_config.config);
11100                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11101
11102                         switch (val) {
11103                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11104                                 val = MF_CFG_RD(bp, func_mf_config[func].
11105                                                 mac_upper);
11106                                 /* check for legal mac (upper bytes)*/
11107                                 if (val != 0xffff) {
11108                                         bp->mf_mode = MULTI_FUNCTION_SI;
11109                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11110                                                    func_mf_config[func].config);
11111                                 } else
11112                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11113                                 break;
11114                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11115                                 if ((!CHIP_IS_E1x(bp)) &&
11116                                     (MF_CFG_RD(bp, func_mf_config[func].
11117                                                mac_upper) != 0xffff) &&
11118                                     (SHMEM2_HAS(bp,
11119                                                 afex_driver_support))) {
11120                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11121                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11122                                                 func_mf_config[func].config);
11123                                 } else {
11124                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11125                                 }
11126                                 break;
11127                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11128                                 /* get OV configuration */
11129                                 val = MF_CFG_RD(bp,
11130                                         func_mf_config[FUNC_0].e1hov_tag);
11131                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11132
11133                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11134                                         bp->mf_mode = MULTI_FUNCTION_SD;
11135                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11136                                                 func_mf_config[func].config);
11137                                 } else
11138                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11139                                 break;
11140                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11141                                 bp->mf_config[vn] = 0;
11142                                 break;
11143                         default:
11144                                 /* Unknown configuration: reset mf_config */
11145                                 bp->mf_config[vn] = 0;
11146                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11147                         }
11148                 }
11149
11150                 BNX2X_DEV_INFO("%s function mode\n",
11151                                IS_MF(bp) ? "multi" : "single");
11152
11153                 switch (bp->mf_mode) {
11154                 case MULTI_FUNCTION_SD:
11155                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11156                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11157                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11158                                 bp->mf_ov = val;
11159                                 bp->path_has_ovlan = true;
11160
11161                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11162                                                func, bp->mf_ov, bp->mf_ov);
11163                         } else {
11164                                 dev_err(&bp->pdev->dev,
11165                                         "No valid MF OV for func %d, aborting\n",
11166                                         func);
11167                                 return -EPERM;
11168                         }
11169                         break;
11170                 case MULTI_FUNCTION_AFEX:
11171                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11172                         break;
11173                 case MULTI_FUNCTION_SI:
11174                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11175                                        func);
11176                         break;
11177                 default:
11178                         if (vn) {
11179                                 dev_err(&bp->pdev->dev,
11180                                         "VN %d is in a single function mode, aborting\n",
11181                                         vn);
11182                                 return -EPERM;
11183                         }
11184                         break;
11185                 }
11186
11187                 /* check if other port on the path needs ovlan:
11188                  * Since MF configuration is shared between ports
11189                  * Possible mixed modes are only
11190                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11191                  */
11192                 if (CHIP_MODE_IS_4_PORT(bp) &&
11193                     !bp->path_has_ovlan &&
11194                     !IS_MF(bp) &&
11195                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11196                         u8 other_port = !BP_PORT(bp);
11197                         u8 other_func = BP_PATH(bp) + 2*other_port;
11198                         val = MF_CFG_RD(bp,
11199                                         func_mf_config[other_func].e1hov_tag);
11200                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11201                                 bp->path_has_ovlan = true;
11202                 }
11203         }
11204
11205         /* adjust igu_sb_cnt to MF for E1x */
11206         if (CHIP_IS_E1x(bp) && IS_MF(bp))
11207                 bp->igu_sb_cnt /= E1HVN_MAX;
11208
11209         /* port info */
11210         bnx2x_get_port_hwinfo(bp);
11211
11212         /* Get MAC addresses */
11213         bnx2x_get_mac_hwinfo(bp);
11214
11215         bnx2x_get_cnic_info(bp);
11216
11217         return rc;
11218 }
11219
11220 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11221 {
11222         int cnt, i, block_end, rodi;
11223         char vpd_start[BNX2X_VPD_LEN+1];
11224         char str_id_reg[VENDOR_ID_LEN+1];
11225         char str_id_cap[VENDOR_ID_LEN+1];
11226         char *vpd_data;
11227         char *vpd_extended_data = NULL;
11228         u8 len;
11229
11230         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11231         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11232
11233         if (cnt < BNX2X_VPD_LEN)
11234                 goto out_not_found;
11235
11236         /* VPD RO tag should be first tag after identifier string, hence
11237          * we should be able to find it in first BNX2X_VPD_LEN chars
11238          */
11239         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11240                              PCI_VPD_LRDT_RO_DATA);
11241         if (i < 0)
11242                 goto out_not_found;
11243
11244         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11245                     pci_vpd_lrdt_size(&vpd_start[i]);
11246
11247         i += PCI_VPD_LRDT_TAG_SIZE;
11248
11249         if (block_end > BNX2X_VPD_LEN) {
11250                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11251                 if (vpd_extended_data  == NULL)
11252                         goto out_not_found;
11253
11254                 /* read rest of vpd image into vpd_extended_data */
11255                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11256                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11257                                    block_end - BNX2X_VPD_LEN,
11258                                    vpd_extended_data + BNX2X_VPD_LEN);
11259                 if (cnt < (block_end - BNX2X_VPD_LEN))
11260                         goto out_not_found;
11261                 vpd_data = vpd_extended_data;
11262         } else
11263                 vpd_data = vpd_start;
11264
11265         /* now vpd_data holds full vpd content in both cases */
11266
11267         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11268                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11269         if (rodi < 0)
11270                 goto out_not_found;
11271
11272         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11273
11274         if (len != VENDOR_ID_LEN)
11275                 goto out_not_found;
11276
11277         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11278
11279         /* vendor specific info */
11280         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11281         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11282         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11283             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11284
11285                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11286                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11287                 if (rodi >= 0) {
11288                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11289
11290                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11291
11292                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11293                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11294                                 bp->fw_ver[len] = ' ';
11295                         }
11296                 }
11297                 kfree(vpd_extended_data);
11298                 return;
11299         }
11300 out_not_found:
11301         kfree(vpd_extended_data);
11302         return;
11303 }
11304
11305 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11306 {
11307         u32 flags = 0;
11308
11309         if (CHIP_REV_IS_FPGA(bp))
11310                 SET_FLAGS(flags, MODE_FPGA);
11311         else if (CHIP_REV_IS_EMUL(bp))
11312                 SET_FLAGS(flags, MODE_EMUL);
11313         else
11314                 SET_FLAGS(flags, MODE_ASIC);
11315
11316         if (CHIP_MODE_IS_4_PORT(bp))
11317                 SET_FLAGS(flags, MODE_PORT4);
11318         else
11319                 SET_FLAGS(flags, MODE_PORT2);
11320
11321         if (CHIP_IS_E2(bp))
11322                 SET_FLAGS(flags, MODE_E2);
11323         else if (CHIP_IS_E3(bp)) {
11324                 SET_FLAGS(flags, MODE_E3);
11325                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11326                         SET_FLAGS(flags, MODE_E3_A0);
11327                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11328                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11329         }
11330
11331         if (IS_MF(bp)) {
11332                 SET_FLAGS(flags, MODE_MF);
11333                 switch (bp->mf_mode) {
11334                 case MULTI_FUNCTION_SD:
11335                         SET_FLAGS(flags, MODE_MF_SD);
11336                         break;
11337                 case MULTI_FUNCTION_SI:
11338                         SET_FLAGS(flags, MODE_MF_SI);
11339                         break;
11340                 case MULTI_FUNCTION_AFEX:
11341                         SET_FLAGS(flags, MODE_MF_AFEX);
11342                         break;
11343                 }
11344         } else
11345                 SET_FLAGS(flags, MODE_SF);
11346
11347 #if defined(__LITTLE_ENDIAN)
11348         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11349 #else /*(__BIG_ENDIAN)*/
11350         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11351 #endif
11352         INIT_MODE_FLAGS(bp) = flags;
11353 }
11354
11355 static int bnx2x_init_bp(struct bnx2x *bp)
11356 {
11357         int func;
11358         int rc;
11359
11360         mutex_init(&bp->port.phy_mutex);
11361         mutex_init(&bp->fw_mb_mutex);
11362         spin_lock_init(&bp->stats_lock);
11363
11364
11365         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11366         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11367         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11368         if (IS_PF(bp)) {
11369                 rc = bnx2x_get_hwinfo(bp);
11370                 if (rc)
11371                         return rc;
11372         } else {
11373                 random_ether_addr(bp->dev->dev_addr);
11374         }
11375
11376         bnx2x_set_modes_bitmap(bp);
11377
11378         rc = bnx2x_alloc_mem_bp(bp);
11379         if (rc)
11380                 return rc;
11381
11382         bnx2x_read_fwinfo(bp);
11383
11384         func = BP_FUNC(bp);
11385
11386         /* need to reset chip if undi was active */
11387         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11388                 /* init fw_seq */
11389                 bp->fw_seq =
11390                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11391                                                         DRV_MSG_SEQ_NUMBER_MASK;
11392                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11393
11394                 bnx2x_prev_unload(bp);
11395         }
11396
11397
11398         if (CHIP_REV_IS_FPGA(bp))
11399                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11400
11401         if (BP_NOMCP(bp) && (func == 0))
11402                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11403
11404         bp->disable_tpa = disable_tpa;
11405         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11406
11407         /* Set TPA flags */
11408         if (bp->disable_tpa) {
11409                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11410                 bp->dev->features &= ~NETIF_F_LRO;
11411         } else {
11412                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11413                 bp->dev->features |= NETIF_F_LRO;
11414         }
11415
11416         if (CHIP_IS_E1(bp))
11417                 bp->dropless_fc = 0;
11418         else
11419                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11420
11421         bp->mrrs = mrrs;
11422
11423         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11424         if (IS_VF(bp))
11425                 bp->rx_ring_size = MAX_RX_AVAIL;
11426
11427         /* make sure that the numbers are in the right granularity */
11428         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11429         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11430
11431         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11432
11433         init_timer(&bp->timer);
11434         bp->timer.expires = jiffies + bp->current_interval;
11435         bp->timer.data = (unsigned long) bp;
11436         bp->timer.function = bnx2x_timer;
11437
11438         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11439             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11440             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11441             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11442                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11443                 bnx2x_dcbx_init_params(bp);
11444         } else {
11445                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11446         }
11447
11448         if (CHIP_IS_E1x(bp))
11449                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11450         else
11451                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11452
11453         /* multiple tx priority */
11454         if (IS_VF(bp))
11455                 bp->max_cos = 1;
11456         else if (CHIP_IS_E1x(bp))
11457                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11458         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11459                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11460         else if (CHIP_IS_E3B0(bp))
11461                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11462         else
11463                 BNX2X_ERR("unknown chip %x revision %x\n",
11464                           CHIP_NUM(bp), CHIP_REV(bp));
11465         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11466
11467         /* We need at least one default status block for slow-path events,
11468          * second status block for the L2 queue, and a third status block for
11469          * CNIC if supproted.
11470          */
11471         if (CNIC_SUPPORT(bp))
11472                 bp->min_msix_vec_cnt = 3;
11473         else
11474                 bp->min_msix_vec_cnt = 2;
11475         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11476
11477         return rc;
11478 }
11479
11480
11481 /****************************************************************************
11482 * General service functions
11483 ****************************************************************************/
11484
11485 /*
11486  * net_device service functions
11487  */
11488
11489 /* called with rtnl_lock */
11490 static int bnx2x_open(struct net_device *dev)
11491 {
11492         struct bnx2x *bp = netdev_priv(dev);
11493         bool global = false;
11494         int other_engine = BP_PATH(bp) ? 0 : 1;
11495         bool other_load_status, load_status;
11496         int rc;
11497
11498         bp->stats_init = true;
11499
11500         netif_carrier_off(dev);
11501
11502         bnx2x_set_power_state(bp, PCI_D0);
11503
11504         /* If parity had happen during the unload, then attentions
11505          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11506          * want the first function loaded on the current engine to
11507          * complete the recovery.
11508          * Parity recovery is only relevant for PF driver.
11509          */
11510         if (IS_PF(bp)) {
11511                 other_load_status = bnx2x_get_load_status(bp, other_engine);
11512                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11513                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11514                     bnx2x_chk_parity_attn(bp, &global, true)) {
11515                         do {
11516                                 /* If there are attentions and they are in a
11517                                  * global blocks, set the GLOBAL_RESET bit
11518                                  * regardless whether it will be this function
11519                                  * that will complete the recovery or not.
11520                                  */
11521                                 if (global)
11522                                         bnx2x_set_reset_global(bp);
11523
11524                                 /* Only the first function on the current
11525                                  * engine should try to recover in open. In case
11526                                  * of attentions in global blocks only the first
11527                                  * in the chip should try to recover.
11528                                  */
11529                                 if ((!load_status &&
11530                                      (!global || !other_load_status)) &&
11531                                       bnx2x_trylock_leader_lock(bp) &&
11532                                       !bnx2x_leader_reset(bp)) {
11533                                         netdev_info(bp->dev,
11534                                                     "Recovered in open\n");
11535                                         break;
11536                                 }
11537
11538                                 /* recovery has failed... */
11539                                 bnx2x_set_power_state(bp, PCI_D3hot);
11540                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11541
11542                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11543                                           "If you still see this message after a few retries then power cycle is required.\n");
11544
11545                                 return -EAGAIN;
11546                         } while (0);
11547                 }
11548         }
11549
11550         bp->recovery_state = BNX2X_RECOVERY_DONE;
11551         rc = bnx2x_nic_load(bp, LOAD_OPEN);
11552         if (rc)
11553                 return rc;
11554         return bnx2x_open_epilog(bp);
11555 }
11556
11557 /* called with rtnl_lock */
11558 static int bnx2x_close(struct net_device *dev)
11559 {
11560         struct bnx2x *bp = netdev_priv(dev);
11561
11562         /* Unload the driver, release IRQs */
11563         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11564
11565         /* Power off */
11566         bnx2x_set_power_state(bp, PCI_D3hot);
11567
11568         return 0;
11569 }
11570
11571 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11572                                       struct bnx2x_mcast_ramrod_params *p)
11573 {
11574         int mc_count = netdev_mc_count(bp->dev);
11575         struct bnx2x_mcast_list_elem *mc_mac =
11576                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11577         struct netdev_hw_addr *ha;
11578
11579         if (!mc_mac)
11580                 return -ENOMEM;
11581
11582         INIT_LIST_HEAD(&p->mcast_list);
11583
11584         netdev_for_each_mc_addr(ha, bp->dev) {
11585                 mc_mac->mac = bnx2x_mc_addr(ha);
11586                 list_add_tail(&mc_mac->link, &p->mcast_list);
11587                 mc_mac++;
11588         }
11589
11590         p->mcast_list_len = mc_count;
11591
11592         return 0;
11593 }
11594
11595 static void bnx2x_free_mcast_macs_list(
11596         struct bnx2x_mcast_ramrod_params *p)
11597 {
11598         struct bnx2x_mcast_list_elem *mc_mac =
11599                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11600                                  link);
11601
11602         WARN_ON(!mc_mac);
11603         kfree(mc_mac);
11604 }
11605
11606 /**
11607  * bnx2x_set_uc_list - configure a new unicast MACs list.
11608  *
11609  * @bp: driver handle
11610  *
11611  * We will use zero (0) as a MAC type for these MACs.
11612  */
11613 static int bnx2x_set_uc_list(struct bnx2x *bp)
11614 {
11615         int rc;
11616         struct net_device *dev = bp->dev;
11617         struct netdev_hw_addr *ha;
11618         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11619         unsigned long ramrod_flags = 0;
11620
11621         /* First schedule a cleanup up of old configuration */
11622         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11623         if (rc < 0) {
11624                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11625                 return rc;
11626         }
11627
11628         netdev_for_each_uc_addr(ha, dev) {
11629                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11630                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11631                 if (rc == -EEXIST) {
11632                         DP(BNX2X_MSG_SP,
11633                            "Failed to schedule ADD operations: %d\n", rc);
11634                         /* do not treat adding same MAC as error */
11635                         rc = 0;
11636
11637                 } else if (rc < 0) {
11638
11639                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11640                                   rc);
11641                         return rc;
11642                 }
11643         }
11644
11645         /* Execute the pending commands */
11646         __set_bit(RAMROD_CONT, &ramrod_flags);
11647         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11648                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11649 }
11650
11651 static int bnx2x_set_mc_list(struct bnx2x *bp)
11652 {
11653         struct net_device *dev = bp->dev;
11654         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11655         int rc = 0;
11656
11657         rparam.mcast_obj = &bp->mcast_obj;
11658
11659         /* first, clear all configured multicast MACs */
11660         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11661         if (rc < 0) {
11662                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11663                 return rc;
11664         }
11665
11666         /* then, configure a new MACs list */
11667         if (netdev_mc_count(dev)) {
11668                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11669                 if (rc) {
11670                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11671                                   rc);
11672                         return rc;
11673                 }
11674
11675                 /* Now add the new MACs */
11676                 rc = bnx2x_config_mcast(bp, &rparam,
11677                                         BNX2X_MCAST_CMD_ADD);
11678                 if (rc < 0)
11679                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11680                                   rc);
11681
11682                 bnx2x_free_mcast_macs_list(&rparam);
11683         }
11684
11685         return rc;
11686 }
11687
11688 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11689 void bnx2x_set_rx_mode(struct net_device *dev)
11690 {
11691         struct bnx2x *bp = netdev_priv(dev);
11692         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11693
11694         if (bp->state != BNX2X_STATE_OPEN) {
11695                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11696                 return;
11697         }
11698
11699         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11700
11701         if (dev->flags & IFF_PROMISC)
11702                 rx_mode = BNX2X_RX_MODE_PROMISC;
11703         else if ((dev->flags & IFF_ALLMULTI) ||
11704                  ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11705                   CHIP_IS_E1(bp)))
11706                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11707         else {
11708                 if (IS_PF(bp)) {
11709                         /* some multicasts */
11710                         if (bnx2x_set_mc_list(bp) < 0)
11711                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11712
11713                         if (bnx2x_set_uc_list(bp) < 0)
11714                                 rx_mode = BNX2X_RX_MODE_PROMISC;
11715                 } else {
11716                         /* configuring mcast to a vf involves sleeping (when we
11717                          * wait for the pf's response). Since this function is
11718                          * called from non sleepable context we must schedule
11719                          * a work item for this purpose
11720                          */
11721                         smp_mb__before_clear_bit();
11722                         set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11723                                 &bp->sp_rtnl_state);
11724                         smp_mb__after_clear_bit();
11725                         schedule_delayed_work(&bp->sp_rtnl_task, 0);
11726                 }
11727         }
11728
11729         bp->rx_mode = rx_mode;
11730         /* handle ISCSI SD mode */
11731         if (IS_MF_ISCSI_SD(bp))
11732                 bp->rx_mode = BNX2X_RX_MODE_NONE;
11733
11734         /* Schedule the rx_mode command */
11735         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11736                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11737                 return;
11738         }
11739
11740         if (IS_PF(bp)) {
11741                 bnx2x_set_storm_rx_mode(bp);
11742         } else {
11743                 /* configuring rx mode to storms in a vf involves sleeping (when
11744                  * we wait for the pf's response). Since this function is
11745                  * called from non sleepable context we must schedule
11746                  * a work item for this purpose
11747                  */
11748                 smp_mb__before_clear_bit();
11749                 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11750                         &bp->sp_rtnl_state);
11751                 smp_mb__after_clear_bit();
11752                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11753         }
11754 }
11755
11756 /* called with rtnl_lock */
11757 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11758                            int devad, u16 addr)
11759 {
11760         struct bnx2x *bp = netdev_priv(netdev);
11761         u16 value;
11762         int rc;
11763
11764         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11765            prtad, devad, addr);
11766
11767         /* The HW expects different devad if CL22 is used */
11768         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11769
11770         bnx2x_acquire_phy_lock(bp);
11771         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11772         bnx2x_release_phy_lock(bp);
11773         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11774
11775         if (!rc)
11776                 rc = value;
11777         return rc;
11778 }
11779
11780 /* called with rtnl_lock */
11781 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11782                             u16 addr, u16 value)
11783 {
11784         struct bnx2x *bp = netdev_priv(netdev);
11785         int rc;
11786
11787         DP(NETIF_MSG_LINK,
11788            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11789            prtad, devad, addr, value);
11790
11791         /* The HW expects different devad if CL22 is used */
11792         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11793
11794         bnx2x_acquire_phy_lock(bp);
11795         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11796         bnx2x_release_phy_lock(bp);
11797         return rc;
11798 }
11799
11800 /* called with rtnl_lock */
11801 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11802 {
11803         struct bnx2x *bp = netdev_priv(dev);
11804         struct mii_ioctl_data *mdio = if_mii(ifr);
11805
11806         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11807            mdio->phy_id, mdio->reg_num, mdio->val_in);
11808
11809         if (!netif_running(dev))
11810                 return -EAGAIN;
11811
11812         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11813 }
11814
11815 #ifdef CONFIG_NET_POLL_CONTROLLER
11816 static void poll_bnx2x(struct net_device *dev)
11817 {
11818         struct bnx2x *bp = netdev_priv(dev);
11819         int i;
11820
11821         for_each_eth_queue(bp, i) {
11822                 struct bnx2x_fastpath *fp = &bp->fp[i];
11823                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11824         }
11825 }
11826 #endif
11827
11828 static int bnx2x_validate_addr(struct net_device *dev)
11829 {
11830         struct bnx2x *bp = netdev_priv(dev);
11831
11832         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11833                 BNX2X_ERR("Non-valid Ethernet address\n");
11834                 return -EADDRNOTAVAIL;
11835         }
11836         return 0;
11837 }
11838
11839 static const struct net_device_ops bnx2x_netdev_ops = {
11840         .ndo_open               = bnx2x_open,
11841         .ndo_stop               = bnx2x_close,
11842         .ndo_start_xmit         = bnx2x_start_xmit,
11843         .ndo_select_queue       = bnx2x_select_queue,
11844         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
11845         .ndo_set_mac_address    = bnx2x_change_mac_addr,
11846         .ndo_validate_addr      = bnx2x_validate_addr,
11847         .ndo_do_ioctl           = bnx2x_ioctl,
11848         .ndo_change_mtu         = bnx2x_change_mtu,
11849         .ndo_fix_features       = bnx2x_fix_features,
11850         .ndo_set_features       = bnx2x_set_features,
11851         .ndo_tx_timeout         = bnx2x_tx_timeout,
11852 #ifdef CONFIG_NET_POLL_CONTROLLER
11853         .ndo_poll_controller    = poll_bnx2x,
11854 #endif
11855         .ndo_setup_tc           = bnx2x_setup_tc,
11856 #ifdef CONFIG_BNX2X_SRIOV
11857         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
11858         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
11859         .ndo_get_vf_config      = bnx2x_get_vf_config,
11860 #endif
11861 #ifdef NETDEV_FCOE_WWNN
11862         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
11863 #endif
11864 };
11865
11866 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11867 {
11868         struct device *dev = &bp->pdev->dev;
11869
11870         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11871                 bp->flags |= USING_DAC_FLAG;
11872                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11873                         dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11874                         return -EIO;
11875                 }
11876         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11877                 dev_err(dev, "System does not support DMA, aborting\n");
11878                 return -EIO;
11879         }
11880
11881         return 0;
11882 }
11883
11884 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
11885                           struct net_device *dev, unsigned long board_type)
11886 {
11887         int rc;
11888         u32 pci_cfg_dword;
11889         bool chip_is_e1x = (board_type == BCM57710 ||
11890                             board_type == BCM57711 ||
11891                             board_type == BCM57711E);
11892
11893         SET_NETDEV_DEV(dev, &pdev->dev);
11894
11895         bp->dev = dev;
11896         bp->pdev = pdev;
11897
11898         rc = pci_enable_device(pdev);
11899         if (rc) {
11900                 dev_err(&bp->pdev->dev,
11901                         "Cannot enable PCI device, aborting\n");
11902                 goto err_out;
11903         }
11904
11905         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11906                 dev_err(&bp->pdev->dev,
11907                         "Cannot find PCI device base address, aborting\n");
11908                 rc = -ENODEV;
11909                 goto err_out_disable;
11910         }
11911
11912         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11913                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
11914                 rc = -ENODEV;
11915                 goto err_out_disable;
11916         }
11917
11918         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11919         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11920             PCICFG_REVESION_ID_ERROR_VAL) {
11921                 pr_err("PCI device error, probably due to fan failure, aborting\n");
11922                 rc = -ENODEV;
11923                 goto err_out_disable;
11924         }
11925
11926         if (atomic_read(&pdev->enable_cnt) == 1) {
11927                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11928                 if (rc) {
11929                         dev_err(&bp->pdev->dev,
11930                                 "Cannot obtain PCI resources, aborting\n");
11931                         goto err_out_disable;
11932                 }
11933
11934                 pci_set_master(pdev);
11935                 pci_save_state(pdev);
11936         }
11937
11938         if (IS_PF(bp)) {
11939                 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11940                 if (bp->pm_cap == 0) {
11941                         dev_err(&bp->pdev->dev,
11942                                 "Cannot find power management capability, aborting\n");
11943                         rc = -EIO;
11944                         goto err_out_release;
11945                 }
11946         }
11947
11948         if (!pci_is_pcie(pdev)) {
11949                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11950                 rc = -EIO;
11951                 goto err_out_release;
11952         }
11953
11954         rc = bnx2x_set_coherency_mask(bp);
11955         if (rc)
11956                 goto err_out_release;
11957
11958         dev->mem_start = pci_resource_start(pdev, 0);
11959         dev->base_addr = dev->mem_start;
11960         dev->mem_end = pci_resource_end(pdev, 0);
11961
11962         dev->irq = pdev->irq;
11963
11964         bp->regview = pci_ioremap_bar(pdev, 0);
11965         if (!bp->regview) {
11966                 dev_err(&bp->pdev->dev,
11967                         "Cannot map register space, aborting\n");
11968                 rc = -ENOMEM;
11969                 goto err_out_release;
11970         }
11971
11972         /* In E1/E1H use pci device function given by kernel.
11973          * In E2/E3 read physical function from ME register since these chips
11974          * support Physical Device Assignment where kernel BDF maybe arbitrary
11975          * (depending on hypervisor).
11976          */
11977         if (chip_is_e1x) {
11978                 bp->pf_num = PCI_FUNC(pdev->devfn);
11979         } else {
11980                 /* chip is E2/3*/
11981                 pci_read_config_dword(bp->pdev,
11982                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
11983                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11984                                   ME_REG_ABS_PF_NUM_SHIFT);
11985         }
11986         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11987
11988         bnx2x_set_power_state(bp, PCI_D0);
11989
11990         /* clean indirect addresses */
11991         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11992                                PCICFG_VENDOR_ID_OFFSET);
11993         /*
11994          * Clean the following indirect addresses for all functions since it
11995          * is not used by the driver.
11996          */
11997         if (IS_PF(bp)) {
11998                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11999                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12000                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12001                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12002
12003                 if (chip_is_e1x) {
12004                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12005                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12006                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12007                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12008                 }
12009
12010                 /* Enable internal target-read (in case we are probed after PF
12011                  * FLR). Must be done prior to any BAR read access. Only for
12012                  * 57712 and up
12013                  */
12014                 if (!chip_is_e1x)
12015                         REG_WR(bp,
12016                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12017         }
12018
12019         dev->watchdog_timeo = TX_TIMEOUT;
12020
12021         dev->netdev_ops = &bnx2x_netdev_ops;
12022         bnx2x_set_ethtool_ops(bp, dev);
12023
12024         dev->priv_flags |= IFF_UNICAST_FLT;
12025
12026         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12027                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12028                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12029                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
12030         if (!CHIP_IS_E1x(bp)) {
12031                 dev->hw_features |= NETIF_F_GSO_GRE;
12032                 dev->hw_enc_features =
12033                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12034                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12035                         NETIF_F_GSO_GRE;
12036         }
12037
12038         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12039                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12040
12041         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
12042         if (bp->flags & USING_DAC_FLAG)
12043                 dev->features |= NETIF_F_HIGHDMA;
12044
12045         /* Add Loopback capability to the device */
12046         dev->hw_features |= NETIF_F_LOOPBACK;
12047
12048 #ifdef BCM_DCBNL
12049         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12050 #endif
12051
12052         /* get_port_hwinfo() will set prtad and mmds properly */
12053         bp->mdio.prtad = MDIO_PRTAD_NONE;
12054         bp->mdio.mmds = 0;
12055         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12056         bp->mdio.dev = dev;
12057         bp->mdio.mdio_read = bnx2x_mdio_read;
12058         bp->mdio.mdio_write = bnx2x_mdio_write;
12059
12060         return 0;
12061
12062 err_out_release:
12063         if (atomic_read(&pdev->enable_cnt) == 1)
12064                 pci_release_regions(pdev);
12065
12066 err_out_disable:
12067         pci_disable_device(pdev);
12068         pci_set_drvdata(pdev, NULL);
12069
12070 err_out:
12071         return rc;
12072 }
12073
12074 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
12075 {
12076         u32 val = 0;
12077
12078         pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
12079         *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12080
12081         /* return value of 1=2.5GHz 2=5GHz */
12082         *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12083 }
12084
12085 static int bnx2x_check_firmware(struct bnx2x *bp)
12086 {
12087         const struct firmware *firmware = bp->firmware;
12088         struct bnx2x_fw_file_hdr *fw_hdr;
12089         struct bnx2x_fw_file_section *sections;
12090         u32 offset, len, num_ops;
12091         __be16 *ops_offsets;
12092         int i;
12093         const u8 *fw_ver;
12094
12095         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12096                 BNX2X_ERR("Wrong FW size\n");
12097                 return -EINVAL;
12098         }
12099
12100         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12101         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12102
12103         /* Make sure none of the offsets and sizes make us read beyond
12104          * the end of the firmware data */
12105         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12106                 offset = be32_to_cpu(sections[i].offset);
12107                 len = be32_to_cpu(sections[i].len);
12108                 if (offset + len > firmware->size) {
12109                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12110                         return -EINVAL;
12111                 }
12112         }
12113
12114         /* Likewise for the init_ops offsets */
12115         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12116         ops_offsets = (__force __be16 *)(firmware->data + offset);
12117         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12118
12119         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12120                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12121                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12122                         return -EINVAL;
12123                 }
12124         }
12125
12126         /* Check FW version */
12127         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12128         fw_ver = firmware->data + offset;
12129         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12130             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12131             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12132             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12133                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12134                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12135                        BCM_5710_FW_MAJOR_VERSION,
12136                        BCM_5710_FW_MINOR_VERSION,
12137                        BCM_5710_FW_REVISION_VERSION,
12138                        BCM_5710_FW_ENGINEERING_VERSION);
12139                 return -EINVAL;
12140         }
12141
12142         return 0;
12143 }
12144
12145 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12146 {
12147         const __be32 *source = (const __be32 *)_source;
12148         u32 *target = (u32 *)_target;
12149         u32 i;
12150
12151         for (i = 0; i < n/4; i++)
12152                 target[i] = be32_to_cpu(source[i]);
12153 }
12154
12155 /*
12156    Ops array is stored in the following format:
12157    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12158  */
12159 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12160 {
12161         const __be32 *source = (const __be32 *)_source;
12162         struct raw_op *target = (struct raw_op *)_target;
12163         u32 i, j, tmp;
12164
12165         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12166                 tmp = be32_to_cpu(source[j]);
12167                 target[i].op = (tmp >> 24) & 0xff;
12168                 target[i].offset = tmp & 0xffffff;
12169                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12170         }
12171 }
12172
12173 /* IRO array is stored in the following format:
12174  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12175  */
12176 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12177 {
12178         const __be32 *source = (const __be32 *)_source;
12179         struct iro *target = (struct iro *)_target;
12180         u32 i, j, tmp;
12181
12182         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12183                 target[i].base = be32_to_cpu(source[j]);
12184                 j++;
12185                 tmp = be32_to_cpu(source[j]);
12186                 target[i].m1 = (tmp >> 16) & 0xffff;
12187                 target[i].m2 = tmp & 0xffff;
12188                 j++;
12189                 tmp = be32_to_cpu(source[j]);
12190                 target[i].m3 = (tmp >> 16) & 0xffff;
12191                 target[i].size = tmp & 0xffff;
12192                 j++;
12193         }
12194 }
12195
12196 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12197 {
12198         const __be16 *source = (const __be16 *)_source;
12199         u16 *target = (u16 *)_target;
12200         u32 i;
12201
12202         for (i = 0; i < n/2; i++)
12203                 target[i] = be16_to_cpu(source[i]);
12204 }
12205
12206 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12207 do {                                                                    \
12208         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12209         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12210         if (!bp->arr)                                                   \
12211                 goto lbl;                                               \
12212         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12213              (u8 *)bp->arr, len);                                       \
12214 } while (0)
12215
12216 static int bnx2x_init_firmware(struct bnx2x *bp)
12217 {
12218         const char *fw_file_name;
12219         struct bnx2x_fw_file_hdr *fw_hdr;
12220         int rc;
12221
12222         if (bp->firmware)
12223                 return 0;
12224
12225         if (CHIP_IS_E1(bp))
12226                 fw_file_name = FW_FILE_NAME_E1;
12227         else if (CHIP_IS_E1H(bp))
12228                 fw_file_name = FW_FILE_NAME_E1H;
12229         else if (!CHIP_IS_E1x(bp))
12230                 fw_file_name = FW_FILE_NAME_E2;
12231         else {
12232                 BNX2X_ERR("Unsupported chip revision\n");
12233                 return -EINVAL;
12234         }
12235         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12236
12237         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12238         if (rc) {
12239                 BNX2X_ERR("Can't load firmware file %s\n",
12240                           fw_file_name);
12241                 goto request_firmware_exit;
12242         }
12243
12244         rc = bnx2x_check_firmware(bp);
12245         if (rc) {
12246                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12247                 goto request_firmware_exit;
12248         }
12249
12250         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12251
12252         /* Initialize the pointers to the init arrays */
12253         /* Blob */
12254         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12255
12256         /* Opcodes */
12257         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12258
12259         /* Offsets */
12260         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12261                             be16_to_cpu_n);
12262
12263         /* STORMs firmware */
12264         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12265                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12266         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12267                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12268         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12269                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12270         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12271                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12272         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12273                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12274         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12275                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12276         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12277                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12278         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12279                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12280         /* IRO */
12281         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12282
12283         return 0;
12284
12285 iro_alloc_err:
12286         kfree(bp->init_ops_offsets);
12287 init_offsets_alloc_err:
12288         kfree(bp->init_ops);
12289 init_ops_alloc_err:
12290         kfree(bp->init_data);
12291 request_firmware_exit:
12292         release_firmware(bp->firmware);
12293         bp->firmware = NULL;
12294
12295         return rc;
12296 }
12297
12298 static void bnx2x_release_firmware(struct bnx2x *bp)
12299 {
12300         kfree(bp->init_ops_offsets);
12301         kfree(bp->init_ops);
12302         kfree(bp->init_data);
12303         release_firmware(bp->firmware);
12304         bp->firmware = NULL;
12305 }
12306
12307
12308 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12309         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12310         .init_hw_cmn      = bnx2x_init_hw_common,
12311         .init_hw_port     = bnx2x_init_hw_port,
12312         .init_hw_func     = bnx2x_init_hw_func,
12313
12314         .reset_hw_cmn     = bnx2x_reset_common,
12315         .reset_hw_port    = bnx2x_reset_port,
12316         .reset_hw_func    = bnx2x_reset_func,
12317
12318         .gunzip_init      = bnx2x_gunzip_init,
12319         .gunzip_end       = bnx2x_gunzip_end,
12320
12321         .init_fw          = bnx2x_init_firmware,
12322         .release_fw       = bnx2x_release_firmware,
12323 };
12324
12325 void bnx2x__init_func_obj(struct bnx2x *bp)
12326 {
12327         /* Prepare DMAE related driver resources */
12328         bnx2x_setup_dmae(bp);
12329
12330         bnx2x_init_func_obj(bp, &bp->func_obj,
12331                             bnx2x_sp(bp, func_rdata),
12332                             bnx2x_sp_mapping(bp, func_rdata),
12333                             bnx2x_sp(bp, func_afex_rdata),
12334                             bnx2x_sp_mapping(bp, func_afex_rdata),
12335                             &bnx2x_func_sp_drv);
12336 }
12337
12338 /* must be called after sriov-enable */
12339 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12340 {
12341         int cid_count = BNX2X_L2_MAX_CID(bp);
12342
12343         if (IS_SRIOV(bp))
12344                 cid_count += BNX2X_VF_CIDS;
12345
12346         if (CNIC_SUPPORT(bp))
12347                 cid_count += CNIC_CID_MAX;
12348
12349         return roundup(cid_count, QM_CID_ROUND);
12350 }
12351
12352 /**
12353  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12354  *
12355  * @dev:        pci device
12356  *
12357  */
12358 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12359                                      int cnic_cnt, bool is_vf)
12360 {
12361         int pos, index;
12362         u16 control = 0;
12363
12364         pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12365
12366         /*
12367          * If MSI-X is not supported - return number of SBs needed to support
12368          * one fast path queue: one FP queue + SB for CNIC
12369          */
12370         if (!pos) {
12371                 dev_info(&pdev->dev, "no msix capability found\n");
12372                 return 1 + cnic_cnt;
12373         }
12374         dev_info(&pdev->dev, "msix capability found\n");
12375
12376         /*
12377          * The value in the PCI configuration space is the index of the last
12378          * entry, namely one less than the actual size of the table, which is
12379          * exactly what we want to return from this function: number of all SBs
12380          * without the default SB.
12381          * For VFs there is no default SB, then we return (index+1).
12382          */
12383         pci_read_config_word(pdev, pos  + PCI_MSI_FLAGS, &control);
12384
12385         index = control & PCI_MSIX_FLAGS_QSIZE;
12386
12387         return is_vf ? index + 1 : index;
12388 }
12389
12390 static int set_max_cos_est(int chip_id)
12391 {
12392         switch (chip_id) {
12393         case BCM57710:
12394         case BCM57711:
12395         case BCM57711E:
12396                 return BNX2X_MULTI_TX_COS_E1X;
12397         case BCM57712:
12398         case BCM57712_MF:
12399         case BCM57712_VF:
12400                 return BNX2X_MULTI_TX_COS_E2_E3A0;
12401         case BCM57800:
12402         case BCM57800_MF:
12403         case BCM57800_VF:
12404         case BCM57810:
12405         case BCM57810_MF:
12406         case BCM57840_4_10:
12407         case BCM57840_2_20:
12408         case BCM57840_O:
12409         case BCM57840_MFO:
12410         case BCM57810_VF:
12411         case BCM57840_MF:
12412         case BCM57840_VF:
12413         case BCM57811:
12414         case BCM57811_MF:
12415         case BCM57811_VF:
12416                 return BNX2X_MULTI_TX_COS_E3B0;
12417                 return 1;
12418         default:
12419                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12420                 return -ENODEV;
12421         }
12422 }
12423
12424 static int set_is_vf(int chip_id)
12425 {
12426         switch (chip_id) {
12427         case BCM57712_VF:
12428         case BCM57800_VF:
12429         case BCM57810_VF:
12430         case BCM57840_VF:
12431         case BCM57811_VF:
12432                 return true;
12433         default:
12434                 return false;
12435         }
12436 }
12437
12438 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12439
12440 static int bnx2x_init_one(struct pci_dev *pdev,
12441                                     const struct pci_device_id *ent)
12442 {
12443         struct net_device *dev = NULL;
12444         struct bnx2x *bp;
12445         int pcie_width, pcie_speed;
12446         int rc, max_non_def_sbs;
12447         int rx_count, tx_count, rss_count, doorbell_size;
12448         int max_cos_est;
12449         bool is_vf;
12450         int cnic_cnt;
12451
12452         /* An estimated maximum supported CoS number according to the chip
12453          * version.
12454          * We will try to roughly estimate the maximum number of CoSes this chip
12455          * may support in order to minimize the memory allocated for Tx
12456          * netdev_queue's. This number will be accurately calculated during the
12457          * initialization of bp->max_cos based on the chip versions AND chip
12458          * revision in the bnx2x_init_bp().
12459          */
12460         max_cos_est = set_max_cos_est(ent->driver_data);
12461         if (max_cos_est < 0)
12462                 return max_cos_est;
12463         is_vf = set_is_vf(ent->driver_data);
12464         cnic_cnt = is_vf ? 0 : 1;
12465
12466         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12467
12468         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12469         rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12470
12471         if (rss_count < 1)
12472                 return -EINVAL;
12473
12474         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12475         rx_count = rss_count + cnic_cnt;
12476
12477         /* Maximum number of netdev Tx queues:
12478          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12479          */
12480         tx_count = rss_count * max_cos_est + cnic_cnt;
12481
12482         /* dev zeroed in init_etherdev */
12483         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12484         if (!dev)
12485                 return -ENOMEM;
12486
12487         bp = netdev_priv(dev);
12488
12489         bp->flags = 0;
12490         if (is_vf)
12491                 bp->flags |= IS_VF_FLAG;
12492
12493         bp->igu_sb_cnt = max_non_def_sbs;
12494         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12495         bp->msg_enable = debug;
12496         bp->cnic_support = cnic_cnt;
12497         bp->cnic_probe = bnx2x_cnic_probe;
12498
12499         pci_set_drvdata(pdev, dev);
12500
12501         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12502         if (rc < 0) {
12503                 free_netdev(dev);
12504                 return rc;
12505         }
12506
12507         BNX2X_DEV_INFO("This is a %s function\n",
12508                        IS_PF(bp) ? "physical" : "virtual");
12509         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12510         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12511         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12512                        tx_count, rx_count);
12513
12514         rc = bnx2x_init_bp(bp);
12515         if (rc)
12516                 goto init_one_exit;
12517
12518         /* Map doorbells here as we need the real value of bp->max_cos which
12519          * is initialized in bnx2x_init_bp() to determine the number of
12520          * l2 connections.
12521          */
12522         if (IS_VF(bp)) {
12523                 bnx2x_vf_map_doorbells(bp);
12524                 rc = bnx2x_vf_pci_alloc(bp);
12525                 if (rc)
12526                         goto init_one_exit;
12527         } else {
12528                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12529                 if (doorbell_size > pci_resource_len(pdev, 2)) {
12530                         dev_err(&bp->pdev->dev,
12531                                 "Cannot map doorbells, bar size too small, aborting\n");
12532                         rc = -ENOMEM;
12533                         goto init_one_exit;
12534                 }
12535                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12536                                                 doorbell_size);
12537         }
12538         if (!bp->doorbells) {
12539                 dev_err(&bp->pdev->dev,
12540                         "Cannot map doorbell space, aborting\n");
12541                 rc = -ENOMEM;
12542                 goto init_one_exit;
12543         }
12544
12545         if (IS_VF(bp)) {
12546                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12547                 if (rc)
12548                         goto init_one_exit;
12549         }
12550
12551         /* Enable SRIOV if capability found in configuration space */
12552         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12553         if (rc)
12554                 goto init_one_exit;
12555
12556         /* calc qm_cid_count */
12557         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12558         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12559
12560         /* disable FCOE L2 queue for E1x*/
12561         if (CHIP_IS_E1x(bp))
12562                 bp->flags |= NO_FCOE_FLAG;
12563
12564         /* Set bp->num_queues for MSI-X mode*/
12565         bnx2x_set_num_queues(bp);
12566
12567         /* Configure interrupt mode: try to enable MSI-X/MSI if
12568          * needed.
12569          */
12570         rc = bnx2x_set_int_mode(bp);
12571         if (rc) {
12572                 dev_err(&pdev->dev, "Cannot set interrupts\n");
12573                 goto init_one_exit;
12574         }
12575         BNX2X_DEV_INFO("set interrupts successfully\n");
12576
12577         /* register the net device */
12578         rc = register_netdev(dev);
12579         if (rc) {
12580                 dev_err(&pdev->dev, "Cannot register net device\n");
12581                 goto init_one_exit;
12582         }
12583         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12584
12585
12586         if (!NO_FCOE(bp)) {
12587                 /* Add storage MAC address */
12588                 rtnl_lock();
12589                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12590                 rtnl_unlock();
12591         }
12592
12593         bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12594         BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12595                        pcie_width, pcie_speed);
12596
12597         BNX2X_DEV_INFO(
12598                 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12599                     board_info[ent->driver_data].name,
12600                     (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12601                     pcie_width,
12602                     ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12603                      (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12604                     "5GHz (Gen2)" : "2.5GHz",
12605                     dev->base_addr, bp->pdev->irq, dev->dev_addr);
12606
12607         return 0;
12608
12609 init_one_exit:
12610         if (bp->regview)
12611                 iounmap(bp->regview);
12612
12613         if (IS_PF(bp) && bp->doorbells)
12614                 iounmap(bp->doorbells);
12615
12616         free_netdev(dev);
12617
12618         if (atomic_read(&pdev->enable_cnt) == 1)
12619                 pci_release_regions(pdev);
12620
12621         pci_disable_device(pdev);
12622         pci_set_drvdata(pdev, NULL);
12623
12624         return rc;
12625 }
12626
12627 static void bnx2x_remove_one(struct pci_dev *pdev)
12628 {
12629         struct net_device *dev = pci_get_drvdata(pdev);
12630         struct bnx2x *bp;
12631
12632         if (!dev) {
12633                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12634                 return;
12635         }
12636         bp = netdev_priv(dev);
12637
12638         /* Delete storage MAC address */
12639         if (!NO_FCOE(bp)) {
12640                 rtnl_lock();
12641                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12642                 rtnl_unlock();
12643         }
12644
12645 #ifdef BCM_DCBNL
12646         /* Delete app tlvs from dcbnl */
12647         bnx2x_dcbnl_update_applist(bp, true);
12648 #endif
12649
12650         unregister_netdev(dev);
12651
12652         /* Power on: we can't let PCI layer write to us while we are in D3 */
12653         if (IS_PF(bp))
12654                 bnx2x_set_power_state(bp, PCI_D0);
12655
12656         /* Disable MSI/MSI-X */
12657         bnx2x_disable_msi(bp);
12658
12659         /* Power off */
12660         if (IS_PF(bp))
12661                 bnx2x_set_power_state(bp, PCI_D3hot);
12662
12663         /* Make sure RESET task is not scheduled before continuing */
12664         cancel_delayed_work_sync(&bp->sp_rtnl_task);
12665
12666         bnx2x_iov_remove_one(bp);
12667
12668         /* send message via vfpf channel to release the resources of this vf */
12669         if (IS_VF(bp))
12670                 bnx2x_vfpf_release(bp);
12671
12672         if (bp->regview)
12673                 iounmap(bp->regview);
12674
12675         /* for vf doorbells are part of the regview and were unmapped along with
12676          * it. FW is only loaded by PF.
12677          */
12678         if (IS_PF(bp)) {
12679                 if (bp->doorbells)
12680                         iounmap(bp->doorbells);
12681
12682                 bnx2x_release_firmware(bp);
12683         }
12684         bnx2x_free_mem_bp(bp);
12685
12686         free_netdev(dev);
12687
12688         if (atomic_read(&pdev->enable_cnt) == 1)
12689                 pci_release_regions(pdev);
12690
12691         pci_disable_device(pdev);
12692         pci_set_drvdata(pdev, NULL);
12693 }
12694
12695 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12696 {
12697         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
12698
12699         bp->rx_mode = BNX2X_RX_MODE_NONE;
12700
12701         if (CNIC_LOADED(bp))
12702                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12703
12704         /* Stop Tx */
12705         bnx2x_tx_disable(bp);
12706         /* Delete all NAPI objects */
12707         bnx2x_del_all_napi(bp);
12708         if (CNIC_LOADED(bp))
12709                 bnx2x_del_all_napi_cnic(bp);
12710         netdev_reset_tc(bp->dev);
12711
12712         del_timer_sync(&bp->timer);
12713         cancel_delayed_work(&bp->sp_task);
12714         cancel_delayed_work(&bp->period_task);
12715
12716         spin_lock_bh(&bp->stats_lock);
12717         bp->stats_state = STATS_STATE_DISABLED;
12718         spin_unlock_bh(&bp->stats_lock);
12719
12720         bnx2x_save_statistics(bp);
12721
12722         netif_carrier_off(bp->dev);
12723
12724         return 0;
12725 }
12726
12727 static void bnx2x_eeh_recover(struct bnx2x *bp)
12728 {
12729         u32 val;
12730
12731         mutex_init(&bp->port.phy_mutex);
12732
12733
12734         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12735         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12736                 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12737                 BNX2X_ERR("BAD MCP validity signature\n");
12738 }
12739
12740 /**
12741  * bnx2x_io_error_detected - called when PCI error is detected
12742  * @pdev: Pointer to PCI device
12743  * @state: The current pci connection state
12744  *
12745  * This function is called after a PCI bus error affecting
12746  * this device has been detected.
12747  */
12748 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12749                                                 pci_channel_state_t state)
12750 {
12751         struct net_device *dev = pci_get_drvdata(pdev);
12752         struct bnx2x *bp = netdev_priv(dev);
12753
12754         rtnl_lock();
12755
12756         BNX2X_ERR("IO error detected\n");
12757
12758         netif_device_detach(dev);
12759
12760         if (state == pci_channel_io_perm_failure) {
12761                 rtnl_unlock();
12762                 return PCI_ERS_RESULT_DISCONNECT;
12763         }
12764
12765         if (netif_running(dev))
12766                 bnx2x_eeh_nic_unload(bp);
12767
12768         bnx2x_prev_path_mark_eeh(bp);
12769
12770         pci_disable_device(pdev);
12771
12772         rtnl_unlock();
12773
12774         /* Request a slot reset */
12775         return PCI_ERS_RESULT_NEED_RESET;
12776 }
12777
12778 /**
12779  * bnx2x_io_slot_reset - called after the PCI bus has been reset
12780  * @pdev: Pointer to PCI device
12781  *
12782  * Restart the card from scratch, as if from a cold-boot.
12783  */
12784 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12785 {
12786         struct net_device *dev = pci_get_drvdata(pdev);
12787         struct bnx2x *bp = netdev_priv(dev);
12788         int i;
12789
12790         rtnl_lock();
12791         BNX2X_ERR("IO slot reset initializing...\n");
12792         if (pci_enable_device(pdev)) {
12793                 dev_err(&pdev->dev,
12794                         "Cannot re-enable PCI device after reset\n");
12795                 rtnl_unlock();
12796                 return PCI_ERS_RESULT_DISCONNECT;
12797         }
12798
12799         pci_set_master(pdev);
12800         pci_restore_state(pdev);
12801
12802         if (netif_running(dev))
12803                 bnx2x_set_power_state(bp, PCI_D0);
12804
12805         if (netif_running(dev)) {
12806                 BNX2X_ERR("IO slot reset --> driver unload\n");
12807                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
12808                         u32 v;
12809
12810                         v = SHMEM2_RD(bp,
12811                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
12812                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
12813                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
12814                 }
12815                 bnx2x_drain_tx_queues(bp);
12816                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
12817                 bnx2x_netif_stop(bp, 1);
12818                 bnx2x_free_irq(bp);
12819
12820                 /* Report UNLOAD_DONE to MCP */
12821                 bnx2x_send_unload_done(bp, true);
12822
12823                 bp->sp_state = 0;
12824                 bp->port.pmf = 0;
12825
12826                 bnx2x_prev_unload(bp);
12827
12828                 /* We should have resetted the engine, so It's fair to
12829                  * assume the FW will no longer write to the bnx2x driver.
12830                  */
12831                 bnx2x_squeeze_objects(bp);
12832                 bnx2x_free_skbs(bp);
12833                 for_each_rx_queue(bp, i)
12834                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12835                 bnx2x_free_fp_mem(bp);
12836                 bnx2x_free_mem(bp);
12837
12838                 bp->state = BNX2X_STATE_CLOSED;
12839         }
12840
12841         rtnl_unlock();
12842
12843         return PCI_ERS_RESULT_RECOVERED;
12844 }
12845
12846 /**
12847  * bnx2x_io_resume - called when traffic can start flowing again
12848  * @pdev: Pointer to PCI device
12849  *
12850  * This callback is called when the error recovery driver tells us that
12851  * its OK to resume normal operation.
12852  */
12853 static void bnx2x_io_resume(struct pci_dev *pdev)
12854 {
12855         struct net_device *dev = pci_get_drvdata(pdev);
12856         struct bnx2x *bp = netdev_priv(dev);
12857
12858         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12859                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12860                 return;
12861         }
12862
12863         rtnl_lock();
12864
12865         bnx2x_eeh_recover(bp);
12866
12867         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12868                                                         DRV_MSG_SEQ_NUMBER_MASK;
12869
12870         if (netif_running(dev))
12871                 bnx2x_nic_load(bp, LOAD_NORMAL);
12872
12873         netif_device_attach(dev);
12874
12875         rtnl_unlock();
12876 }
12877
12878 static const struct pci_error_handlers bnx2x_err_handler = {
12879         .error_detected = bnx2x_io_error_detected,
12880         .slot_reset     = bnx2x_io_slot_reset,
12881         .resume         = bnx2x_io_resume,
12882 };
12883
12884 static struct pci_driver bnx2x_pci_driver = {
12885         .name        = DRV_MODULE_NAME,
12886         .id_table    = bnx2x_pci_tbl,
12887         .probe       = bnx2x_init_one,
12888         .remove      = bnx2x_remove_one,
12889         .suspend     = bnx2x_suspend,
12890         .resume      = bnx2x_resume,
12891         .err_handler = &bnx2x_err_handler,
12892 #ifdef CONFIG_BNX2X_SRIOV
12893         .sriov_configure = bnx2x_sriov_configure,
12894 #endif
12895 };
12896
12897 static int __init bnx2x_init(void)
12898 {
12899         int ret;
12900
12901         pr_info("%s", version);
12902
12903         bnx2x_wq = create_singlethread_workqueue("bnx2x");
12904         if (bnx2x_wq == NULL) {
12905                 pr_err("Cannot create workqueue\n");
12906                 return -ENOMEM;
12907         }
12908
12909         ret = pci_register_driver(&bnx2x_pci_driver);
12910         if (ret) {
12911                 pr_err("Cannot register driver\n");
12912                 destroy_workqueue(bnx2x_wq);
12913         }
12914         return ret;
12915 }
12916
12917 static void __exit bnx2x_cleanup(void)
12918 {
12919         struct list_head *pos, *q;
12920         pci_unregister_driver(&bnx2x_pci_driver);
12921
12922         destroy_workqueue(bnx2x_wq);
12923
12924         /* Free globablly allocated resources */
12925         list_for_each_safe(pos, q, &bnx2x_prev_list) {
12926                 struct bnx2x_prev_path_list *tmp =
12927                         list_entry(pos, struct bnx2x_prev_path_list, list);
12928                 list_del(pos);
12929                 kfree(tmp);
12930         }
12931 }
12932
12933 void bnx2x_notify_link_changed(struct bnx2x *bp)
12934 {
12935         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12936 }
12937
12938 module_init(bnx2x_init);
12939 module_exit(bnx2x_cleanup);
12940
12941 /**
12942  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12943  *
12944  * @bp:         driver handle
12945  * @set:        set or clear the CAM entry
12946  *
12947  * This function will wait until the ramdord completion returns.
12948  * Return 0 if success, -ENODEV if ramrod doesn't return.
12949  */
12950 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12951 {
12952         unsigned long ramrod_flags = 0;
12953
12954         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12955         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12956                                  &bp->iscsi_l2_mac_obj, true,
12957                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12958 }
12959
12960 /* count denotes the number of new completions we have seen */
12961 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12962 {
12963         struct eth_spe *spe;
12964         int cxt_index, cxt_offset;
12965
12966 #ifdef BNX2X_STOP_ON_ERROR
12967         if (unlikely(bp->panic))
12968                 return;
12969 #endif
12970
12971         spin_lock_bh(&bp->spq_lock);
12972         BUG_ON(bp->cnic_spq_pending < count);
12973         bp->cnic_spq_pending -= count;
12974
12975
12976         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12977                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12978                                 & SPE_HDR_CONN_TYPE) >>
12979                                 SPE_HDR_CONN_TYPE_SHIFT;
12980                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12981                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12982
12983                 /* Set validation for iSCSI L2 client before sending SETUP
12984                  *  ramrod
12985                  */
12986                 if (type == ETH_CONNECTION_TYPE) {
12987                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12988                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12989                                         ILT_PAGE_CIDS;
12990                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12991                                         (cxt_index * ILT_PAGE_CIDS);
12992                                 bnx2x_set_ctx_validation(bp,
12993                                         &bp->context[cxt_index].
12994                                                          vcxt[cxt_offset].eth,
12995                                         BNX2X_ISCSI_ETH_CID(bp));
12996                         }
12997                 }
12998
12999                 /*
13000                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13001                  * and in the air. We also check that number of outstanding
13002                  * COMMON ramrods is not more than the EQ and SPQ can
13003                  * accommodate.
13004                  */
13005                 if (type == ETH_CONNECTION_TYPE) {
13006                         if (!atomic_read(&bp->cq_spq_left))
13007                                 break;
13008                         else
13009                                 atomic_dec(&bp->cq_spq_left);
13010                 } else if (type == NONE_CONNECTION_TYPE) {
13011                         if (!atomic_read(&bp->eq_spq_left))
13012                                 break;
13013                         else
13014                                 atomic_dec(&bp->eq_spq_left);
13015                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13016                            (type == FCOE_CONNECTION_TYPE)) {
13017                         if (bp->cnic_spq_pending >=
13018                             bp->cnic_eth_dev.max_kwqe_pending)
13019                                 break;
13020                         else
13021                                 bp->cnic_spq_pending++;
13022                 } else {
13023                         BNX2X_ERR("Unknown SPE type: %d\n", type);
13024                         bnx2x_panic();
13025                         break;
13026                 }
13027
13028                 spe = bnx2x_sp_get_next(bp);
13029                 *spe = *bp->cnic_kwq_cons;
13030
13031                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13032                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13033
13034                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13035                         bp->cnic_kwq_cons = bp->cnic_kwq;
13036                 else
13037                         bp->cnic_kwq_cons++;
13038         }
13039         bnx2x_sp_prod_update(bp);
13040         spin_unlock_bh(&bp->spq_lock);
13041 }
13042
13043 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13044                                struct kwqe_16 *kwqes[], u32 count)
13045 {
13046         struct bnx2x *bp = netdev_priv(dev);
13047         int i;
13048
13049 #ifdef BNX2X_STOP_ON_ERROR
13050         if (unlikely(bp->panic)) {
13051                 BNX2X_ERR("Can't post to SP queue while panic\n");
13052                 return -EIO;
13053         }
13054 #endif
13055
13056         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13057             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13058                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13059                 return -EAGAIN;
13060         }
13061
13062         spin_lock_bh(&bp->spq_lock);
13063
13064         for (i = 0; i < count; i++) {
13065                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13066
13067                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13068                         break;
13069
13070                 *bp->cnic_kwq_prod = *spe;
13071
13072                 bp->cnic_kwq_pending++;
13073
13074                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13075                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
13076                    spe->data.update_data_addr.hi,
13077                    spe->data.update_data_addr.lo,
13078                    bp->cnic_kwq_pending);
13079
13080                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13081                         bp->cnic_kwq_prod = bp->cnic_kwq;
13082                 else
13083                         bp->cnic_kwq_prod++;
13084         }
13085
13086         spin_unlock_bh(&bp->spq_lock);
13087
13088         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13089                 bnx2x_cnic_sp_post(bp, 0);
13090
13091         return i;
13092 }
13093
13094 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13095 {
13096         struct cnic_ops *c_ops;
13097         int rc = 0;
13098
13099         mutex_lock(&bp->cnic_mutex);
13100         c_ops = rcu_dereference_protected(bp->cnic_ops,
13101                                           lockdep_is_held(&bp->cnic_mutex));
13102         if (c_ops)
13103                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13104         mutex_unlock(&bp->cnic_mutex);
13105
13106         return rc;
13107 }
13108
13109 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13110 {
13111         struct cnic_ops *c_ops;
13112         int rc = 0;
13113
13114         rcu_read_lock();
13115         c_ops = rcu_dereference(bp->cnic_ops);
13116         if (c_ops)
13117                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13118         rcu_read_unlock();
13119
13120         return rc;
13121 }
13122
13123 /*
13124  * for commands that have no data
13125  */
13126 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13127 {
13128         struct cnic_ctl_info ctl = {0};
13129
13130         ctl.cmd = cmd;
13131
13132         return bnx2x_cnic_ctl_send(bp, &ctl);
13133 }
13134
13135 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13136 {
13137         struct cnic_ctl_info ctl = {0};
13138
13139         /* first we tell CNIC and only then we count this as a completion */
13140         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13141         ctl.data.comp.cid = cid;
13142         ctl.data.comp.error = err;
13143
13144         bnx2x_cnic_ctl_send_bh(bp, &ctl);
13145         bnx2x_cnic_sp_post(bp, 0);
13146 }
13147
13148
13149 /* Called with netif_addr_lock_bh() taken.
13150  * Sets an rx_mode config for an iSCSI ETH client.
13151  * Doesn't block.
13152  * Completion should be checked outside.
13153  */
13154 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13155 {
13156         unsigned long accept_flags = 0, ramrod_flags = 0;
13157         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13158         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13159
13160         if (start) {
13161                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13162                  * because it's the only way for UIO Queue to accept
13163                  * multicasts (in non-promiscuous mode only one Queue per
13164                  * function will receive multicast packets (leading in our
13165                  * case).
13166                  */
13167                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13168                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13169                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13170                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13171
13172                 /* Clear STOP_PENDING bit if START is requested */
13173                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13174
13175                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13176         } else
13177                 /* Clear START_PENDING bit if STOP is requested */
13178                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13179
13180         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13181                 set_bit(sched_state, &bp->sp_state);
13182         else {
13183                 __set_bit(RAMROD_RX, &ramrod_flags);
13184                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13185                                     ramrod_flags);
13186         }
13187 }
13188
13189
13190 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13191 {
13192         struct bnx2x *bp = netdev_priv(dev);
13193         int rc = 0;
13194
13195         switch (ctl->cmd) {
13196         case DRV_CTL_CTXTBL_WR_CMD: {
13197                 u32 index = ctl->data.io.offset;
13198                 dma_addr_t addr = ctl->data.io.dma_addr;
13199
13200                 bnx2x_ilt_wr(bp, index, addr);
13201                 break;
13202         }
13203
13204         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13205                 int count = ctl->data.credit.credit_count;
13206
13207                 bnx2x_cnic_sp_post(bp, count);
13208                 break;
13209         }
13210
13211         /* rtnl_lock is held.  */
13212         case DRV_CTL_START_L2_CMD: {
13213                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13214                 unsigned long sp_bits = 0;
13215
13216                 /* Configure the iSCSI classification object */
13217                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13218                                    cp->iscsi_l2_client_id,
13219                                    cp->iscsi_l2_cid, BP_FUNC(bp),
13220                                    bnx2x_sp(bp, mac_rdata),
13221                                    bnx2x_sp_mapping(bp, mac_rdata),
13222                                    BNX2X_FILTER_MAC_PENDING,
13223                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13224                                    &bp->macs_pool);
13225
13226                 /* Set iSCSI MAC address */
13227                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13228                 if (rc)
13229                         break;
13230
13231                 mmiowb();
13232                 barrier();
13233
13234                 /* Start accepting on iSCSI L2 ring */
13235
13236                 netif_addr_lock_bh(dev);
13237                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13238                 netif_addr_unlock_bh(dev);
13239
13240                 /* bits to wait on */
13241                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13242                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13243
13244                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13245                         BNX2X_ERR("rx_mode completion timed out!\n");
13246
13247                 break;
13248         }
13249
13250         /* rtnl_lock is held.  */
13251         case DRV_CTL_STOP_L2_CMD: {
13252                 unsigned long sp_bits = 0;
13253
13254                 /* Stop accepting on iSCSI L2 ring */
13255                 netif_addr_lock_bh(dev);
13256                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13257                 netif_addr_unlock_bh(dev);
13258
13259                 /* bits to wait on */
13260                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13261                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13262
13263                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13264                         BNX2X_ERR("rx_mode completion timed out!\n");
13265
13266                 mmiowb();
13267                 barrier();
13268
13269                 /* Unset iSCSI L2 MAC */
13270                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13271                                         BNX2X_ISCSI_ETH_MAC, true);
13272                 break;
13273         }
13274         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13275                 int count = ctl->data.credit.credit_count;
13276
13277                 smp_mb__before_atomic_inc();
13278                 atomic_add(count, &bp->cq_spq_left);
13279                 smp_mb__after_atomic_inc();
13280                 break;
13281         }
13282         case DRV_CTL_ULP_REGISTER_CMD: {
13283                 int ulp_type = ctl->data.register_data.ulp_type;
13284
13285                 if (CHIP_IS_E3(bp)) {
13286                         int idx = BP_FW_MB_IDX(bp);
13287                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13288                         int path = BP_PATH(bp);
13289                         int port = BP_PORT(bp);
13290                         int i;
13291                         u32 scratch_offset;
13292                         u32 *host_addr;
13293
13294                         /* first write capability to shmem2 */
13295                         if (ulp_type == CNIC_ULP_ISCSI)
13296                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13297                         else if (ulp_type == CNIC_ULP_FCOE)
13298                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13299                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13300
13301                         if ((ulp_type != CNIC_ULP_FCOE) ||
13302                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13303                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
13304                                 break;
13305
13306                         /* if reached here - should write fcoe capabilities */
13307                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13308                         if (!scratch_offset)
13309                                 break;
13310                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
13311                                                    fcoe_features[path][port]);
13312                         host_addr = (u32 *) &(ctl->data.register_data.
13313                                               fcoe_features);
13314                         for (i = 0; i < sizeof(struct fcoe_capabilities);
13315                              i += 4)
13316                                 REG_WR(bp, scratch_offset + i,
13317                                        *(host_addr + i/4));
13318                 }
13319                 break;
13320         }
13321
13322         case DRV_CTL_ULP_UNREGISTER_CMD: {
13323                 int ulp_type = ctl->data.ulp_type;
13324
13325                 if (CHIP_IS_E3(bp)) {
13326                         int idx = BP_FW_MB_IDX(bp);
13327                         u32 cap;
13328
13329                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13330                         if (ulp_type == CNIC_ULP_ISCSI)
13331                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13332                         else if (ulp_type == CNIC_ULP_FCOE)
13333                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13334                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13335                 }
13336                 break;
13337         }
13338
13339         default:
13340                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13341                 rc = -EINVAL;
13342         }
13343
13344         return rc;
13345 }
13346
13347 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13348 {
13349         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13350
13351         if (bp->flags & USING_MSIX_FLAG) {
13352                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13353                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13354                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13355         } else {
13356                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13357                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13358         }
13359         if (!CHIP_IS_E1x(bp))
13360                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13361         else
13362                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13363
13364         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
13365         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13366         cp->irq_arr[1].status_blk = bp->def_status_blk;
13367         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13368         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13369
13370         cp->num_irq = 2;
13371 }
13372
13373 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13374 {
13375         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13376
13377
13378         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13379                              bnx2x_cid_ilt_lines(bp);
13380         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13381         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13382         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13383
13384         if (NO_ISCSI_OOO(bp))
13385                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13386 }
13387
13388 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13389                                void *data)
13390 {
13391         struct bnx2x *bp = netdev_priv(dev);
13392         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13393         int rc;
13394
13395         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13396
13397         if (ops == NULL) {
13398                 BNX2X_ERR("NULL ops received\n");
13399                 return -EINVAL;
13400         }
13401
13402         if (!CNIC_SUPPORT(bp)) {
13403                 BNX2X_ERR("Can't register CNIC when not supported\n");
13404                 return -EOPNOTSUPP;
13405         }
13406
13407         if (!CNIC_LOADED(bp)) {
13408                 rc = bnx2x_load_cnic(bp);
13409                 if (rc) {
13410                         BNX2X_ERR("CNIC-related load failed\n");
13411                         return rc;
13412                 }
13413
13414         }
13415
13416         bp->cnic_enabled = true;
13417
13418         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13419         if (!bp->cnic_kwq)
13420                 return -ENOMEM;
13421
13422         bp->cnic_kwq_cons = bp->cnic_kwq;
13423         bp->cnic_kwq_prod = bp->cnic_kwq;
13424         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13425
13426         bp->cnic_spq_pending = 0;
13427         bp->cnic_kwq_pending = 0;
13428
13429         bp->cnic_data = data;
13430
13431         cp->num_irq = 0;
13432         cp->drv_state |= CNIC_DRV_STATE_REGD;
13433         cp->iro_arr = bp->iro_arr;
13434
13435         bnx2x_setup_cnic_irq_info(bp);
13436
13437         rcu_assign_pointer(bp->cnic_ops, ops);
13438
13439         return 0;
13440 }
13441
13442 static int bnx2x_unregister_cnic(struct net_device *dev)
13443 {
13444         struct bnx2x *bp = netdev_priv(dev);
13445         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13446
13447         mutex_lock(&bp->cnic_mutex);
13448         cp->drv_state = 0;
13449         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13450         mutex_unlock(&bp->cnic_mutex);
13451         synchronize_rcu();
13452         kfree(bp->cnic_kwq);
13453         bp->cnic_kwq = NULL;
13454
13455         return 0;
13456 }
13457
13458 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13459 {
13460         struct bnx2x *bp = netdev_priv(dev);
13461         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13462
13463         /* If both iSCSI and FCoE are disabled - return NULL in
13464          * order to indicate CNIC that it should not try to work
13465          * with this device.
13466          */
13467         if (NO_ISCSI(bp) && NO_FCOE(bp))
13468                 return NULL;
13469
13470         cp->drv_owner = THIS_MODULE;
13471         cp->chip_id = CHIP_ID(bp);
13472         cp->pdev = bp->pdev;
13473         cp->io_base = bp->regview;
13474         cp->io_base2 = bp->doorbells;
13475         cp->max_kwqe_pending = 8;
13476         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13477         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13478                              bnx2x_cid_ilt_lines(bp);
13479         cp->ctx_tbl_len = CNIC_ILT_LINES;
13480         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13481         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13482         cp->drv_ctl = bnx2x_drv_ctl;
13483         cp->drv_register_cnic = bnx2x_register_cnic;
13484         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13485         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13486         cp->iscsi_l2_client_id =
13487                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13488         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13489
13490         if (NO_ISCSI_OOO(bp))
13491                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13492
13493         if (NO_ISCSI(bp))
13494                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13495
13496         if (NO_FCOE(bp))
13497                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13498
13499         BNX2X_DEV_INFO(
13500                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13501            cp->ctx_blk_size,
13502            cp->ctx_tbl_offset,
13503            cp->ctx_tbl_len,
13504            cp->starting_cid);
13505         return cp;
13506 }
13507
13508 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13509 {
13510         struct bnx2x *bp = fp->bp;
13511         u32 offset = BAR_USTRORM_INTMEM;
13512
13513         if (IS_VF(bp))
13514                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13515         else if (!CHIP_IS_E1x(bp))
13516                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13517         else
13518                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13519
13520         return offset;
13521 }
13522
13523 /* called only on E1H or E2.
13524  * When pretending to be PF, the pretend value is the function number 0...7
13525  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13526  * combination
13527  */
13528 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13529 {
13530         u32 pretend_reg;
13531
13532         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13533                 return -1;
13534
13535         /* get my own pretend register */
13536         pretend_reg = bnx2x_get_pretend_reg(bp);
13537         REG_WR(bp, pretend_reg, pretend_func_val);
13538         REG_RD(bp, pretend_reg);
13539         return 0;
13540 }