drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/aer.h>
  31 #include <linux/init.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/bitops.h>
  37 #include <linux/irq.h>
  38 #include <linux/delay.h>
  39 #include <asm/byteorder.h>
  40 #include <linux/time.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mii.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/crash_dump.h>
  45 #include <net/ip.h>
  46 #include <net/ipv6.h>
  47 #include <net/tcp.h>
  48 #include <net/vxlan.h>
  49 #include <net/checksum.h>
  50 #include <net/ip6_checksum.h>
  51 #include <linux/workqueue.h>
  52 #include <linux/crc32.h>
  53 #include <linux/crc32c.h>
  54 #include <linux/prefetch.h>
  55 #include <linux/zlib.h>
  56 #include <linux/io.h>
  57 #include <linux/semaphore.h>
  58 #include <linux/stringify.h>
  59 #include <linux/vmalloc.h>
  60
  61 #include "bnx2x.h"
  62 #include "bnx2x_init.h"
  63 #include "bnx2x_init_ops.h"
  64 #include "bnx2x_cmn.h"
  65 #include "bnx2x_vfpf.h"
  66 #include "bnx2x_dcb.h"
  67 #include "bnx2x_sp.h"
  68 #include <linux/firmware.h>
  69 #include "bnx2x_fw_file_hdr.h"
  70 /* FW files */
  71 #define FW_FILE_VERSION                                 \
  72         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  73         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  74         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  75         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  76 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  77 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  78 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  79
  80 /* Time in jiffies before concluding the transmitter is hung */
  81 #define TX_TIMEOUT              (5*HZ)
  82
  83 static char version[] =
  84         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  85         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  86
  87 MODULE_AUTHOR("Eliezer Tamir");
  88 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  89                    "BCM57710/57711/57711E/"
  90                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  91                    "57840/57840_MF Driver");
  92 MODULE_LICENSE("GPL");
  93 MODULE_VERSION(DRV_MODULE_VERSION);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  96 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  97
  98 int bnx2x_num_queues;
  99 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
 100 MODULE_PARM_DESC(num_queues,
 101                  " Set number of queues (default is as a number of CPUs)");
 102
 103 static int disable_tpa;
 104 module_param(disable_tpa, int, S_IRUGO);
 105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 106
 107 static int int_mode;
 108 module_param(int_mode, int, S_IRUGO);
 109 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 110                                 "(1 INT#x; 2 MSI)");
 111
 112 static int dropless_fc;
 113 module_param(dropless_fc, int, S_IRUGO);
 114 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 115
 116 static int mrrs = -1;
 117 module_param(mrrs, int, S_IRUGO);
 118 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 119
 120 static int debug;
 121 module_param(debug, int, S_IRUGO);
 122 MODULE_PARM_DESC(debug, " Default debug msglevel");
 123
 124 static struct workqueue_struct *bnx2x_wq;
 125 struct workqueue_struct *bnx2x_iov_wq;
 126
 127 struct bnx2x_mac_vals {
 128         u32 xmac_addr;
 129         u32 xmac_val;
 130         u32 emac_addr;
 131         u32 emac_val;
 132         u32 umac_addr[2];
 133         u32 umac_val[2];
 134         u32 bmac_addr;
 135         u32 bmac_val[2];
 136 };
 137
 138 enum bnx2x_board_type {
 139         BCM57710 = 0,
 140         BCM57711,
 141         BCM57711E,
 142         BCM57712,
 143         BCM57712_MF,
 144         BCM57712_VF,
 145         BCM57800,
 146         BCM57800_MF,
 147         BCM57800_VF,
 148         BCM57810,
 149         BCM57810_MF,
 150         BCM57810_VF,
 151         BCM57840_4_10,
 152         BCM57840_2_20,
 153         BCM57840_MF,
 154         BCM57840_VF,
 155         BCM57811,
 156         BCM57811_MF,
 157         BCM57840_O,
 158         BCM57840_MFO,
 159         BCM57811_VF
 160 };
 161
 162 /* indexed by board_type, above */
 163 static struct {
 164         char *name;
 165 } board_info[] = {
 166         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 167         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 168         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 169         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 170         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 171         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 172         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 173         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 174         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 175         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 176         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 177         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 178         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 179         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 180         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 181         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 182         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 183         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 184         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 185         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 186         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 187 };
 188
 189 #ifndef PCI_DEVICE_ID_NX2_57710
 190 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 191 #endif
 192 #ifndef PCI_DEVICE_ID_NX2_57711
 193 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 194 #endif
 195 #ifndef PCI_DEVICE_ID_NX2_57711E
 196 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 197 #endif
 198 #ifndef PCI_DEVICE_ID_NX2_57712
 199 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 200 #endif
 201 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 202 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 203 #endif
 204 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 205 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 206 #endif
 207 #ifndef PCI_DEVICE_ID_NX2_57800
 208 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 209 #endif
 210 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 211 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 212 #endif
 213 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 214 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 215 #endif
 216 #ifndef PCI_DEVICE_ID_NX2_57810
 217 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 218 #endif
 219 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 220 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 221 #endif
 222 #ifndef PCI_DEVICE_ID_NX2_57840_O
 223 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 224 #endif
 225 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 226 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 227 #endif
 228 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 229 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 230 #endif
 231 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 232 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 233 #endif
 234 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 235 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 236 #endif
 237 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 238 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 239 #endif
 240 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 241 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 242 #endif
 243 #ifndef PCI_DEVICE_ID_NX2_57811
 244 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 245 #endif
 246 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 247 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 248 #endif
 249 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 250 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 251 #endif
 252
 253 static const struct pci_device_id bnx2x_pci_tbl[] = {
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 275         { 0 }
 276 };
 277
 278 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 279
 280 /* Global resources for unloading a previously loaded device */
 281 #define BNX2X_PREV_WAIT_NEEDED 1
 282 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 283 static LIST_HEAD(bnx2x_prev_list);
 284
 285 /* Forward declaration */
 286 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 287 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 288 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 289
 290 /****************************************************************************
 291 * General service functions
 292 ****************************************************************************/
 293
 294 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 295
 296 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 297                                        u32 addr, dma_addr_t mapping)
 298 {
 299         REG_WR(bp,  addr, U64_LO(mapping));
 300         REG_WR(bp,  addr + 4, U64_HI(mapping));
 301 }
 302
 303 static void storm_memset_spq_addr(struct bnx2x *bp,
 304                                   dma_addr_t mapping, u16 abs_fid)
 305 {
 306         u32 addr = XSEM_REG_FAST_MEMORY +
 307                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 308
 309         __storm_memset_dma_mapping(bp, addr, mapping);
 310 }
 311
 312 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 313                                   u16 pf_id)
 314 {
 315         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 316                 pf_id);
 317         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 318                 pf_id);
 319         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 320                 pf_id);
 321         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 322                 pf_id);
 323 }
 324
 325 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 326                                  u8 enable)
 327 {
 328         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 329                 enable);
 330         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 331                 enable);
 332         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 333                 enable);
 334         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 335                 enable);
 336 }
 337
 338 static void storm_memset_eq_data(struct bnx2x *bp,
 339                                  struct event_ring_data *eq_data,
 340                                 u16 pfid)
 341 {
 342         size_t size = sizeof(struct event_ring_data);
 343
 344         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 345
 346         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 347 }
 348
 349 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 350                                  u16 pfid)
 351 {
 352         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 353         REG_WR16(bp, addr, eq_prod);
 354 }
 355
 356 /* used only at init
 357  * locking is done by mcp
 358  */
 359 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 360 {
 361         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 362         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 363         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 364                                PCICFG_VENDOR_ID_OFFSET);
 365 }
 366
 367 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 368 {
 369         u32 val;
 370
 371         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 372         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 373         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 374                                PCICFG_VENDOR_ID_OFFSET);
 375
 376         return val;
 377 }
 378
 379 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 380 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 381 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 382 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 383 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 384
 385 static void bnx2x_dp_dmae(struct bnx2x *bp,
 386                           struct dmae_command *dmae, int msglvl)
 387 {
 388         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 389         int i;
 390
 391         switch (dmae->opcode & DMAE_COMMAND_DST) {
 392         case DMAE_CMD_DST_PCI:
 393                 if (src_type == DMAE_CMD_SRC_PCI)
 394                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 395                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 396                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 397                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 398                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 399                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 400                            dmae->comp_val);
 401                 else
 402                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 403                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 404                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 405                            dmae->opcode, dmae->src_addr_lo >> 2,
 406                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 407                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 408                            dmae->comp_val);
 409                 break;
 410         case DMAE_CMD_DST_GRC:
 411                 if (src_type == DMAE_CMD_SRC_PCI)
 412                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 413                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 414                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 415                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 416                            dmae->len, dmae->dst_addr_lo >> 2,
 417                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 418                            dmae->comp_val);
 419                 else
 420                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 421                            "src [%08x], len [%d*4], dst [%08x]\n"
 422                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 423                            dmae->opcode, dmae->src_addr_lo >> 2,
 424                            dmae->len, dmae->dst_addr_lo >> 2,
 425                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 426                            dmae->comp_val);
 427                 break;
 428         default:
 429                 if (src_type == DMAE_CMD_SRC_PCI)
 430                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 431                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 432                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 433                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 434                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 435                            dmae->comp_val);
 436                 else
 437                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 438                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 439                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 440                            dmae->opcode, dmae->src_addr_lo >> 2,
 441                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 442                            dmae->comp_val);
 443                 break;
 444         }
 445
 446         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 447                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 448                    i, *(((u32 *)dmae) + i));
 449 }
 450
 451 /* copy command into DMAE command memory and set DMAE command go */
 452 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 453 {
 454         u32 cmd_offset;
 455         int i;
 456
 457         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 458         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 459                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 460         }
 461         REG_WR(bp, dmae_reg_go_c[idx], 1);
 462 }
 463
 464 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 465 {
 466         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 467                            DMAE_CMD_C_ENABLE);
 468 }
 469
 470 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 471 {
 472         return opcode & ~DMAE_CMD_SRC_RESET;
 473 }
 474
 475 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 476                              bool with_comp, u8 comp_type)
 477 {
 478         u32 opcode = 0;
 479
 480         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 481                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 482
 483         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 484
 485         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 486         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 487                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 488         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 489
 490 #ifdef __BIG_ENDIAN
 491         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 492 #else
 493         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 494 #endif
 495         if (with_comp)
 496                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 497         return opcode;
 498 }
 499
 500 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 501                                       struct dmae_command *dmae,
 502                                       u8 src_type, u8 dst_type)
 503 {
 504         memset(dmae, 0, sizeof(struct dmae_command));
 505
 506         /* set the opcode */
 507         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 508                                          true, DMAE_COMP_PCI);
 509
 510         /* fill in the completion parameters */
 511         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 512         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 513         dmae->comp_val = DMAE_COMP_VAL;
 514 }
 515
 516 /* issue a dmae command over the init-channel and wait for completion */
 517 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 518                                u32 *comp)
 519 {
 520         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 521         int rc = 0;
 522
 523         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 524
 525         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 526          * as long as this code is called both from syscall context and
 527          * from ndo_set_rx_mode() flow that may be called from BH.
 528          */
 529
 530         spin_lock_bh(&bp->dmae_lock);
 531
 532         /* reset completion */
 533         *comp = 0;
 534
 535         /* post the command on the channel used for initializations */
 536         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 537
 538         /* wait for completion */
 539         udelay(5);
 540         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 541
 542                 if (!cnt ||
 543                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 544                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 545                         BNX2X_ERR("DMAE timeout!\n");
 546                         rc = DMAE_TIMEOUT;
 547                         goto unlock;
 548                 }
 549                 cnt--;
 550                 udelay(50);
 551         }
 552         if (*comp & DMAE_PCI_ERR_FLAG) {
 553                 BNX2X_ERR("DMAE PCI error!\n");
 554                 rc = DMAE_PCI_ERROR;
 555         }
 556
 557 unlock:
 558
 559         spin_unlock_bh(&bp->dmae_lock);
 560
 561         return rc;
 562 }
 563
 564 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 565                       u32 len32)
 566 {
 567         int rc;
 568         struct dmae_command dmae;
 569
 570         if (!bp->dmae_ready) {
 571                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 572
 573                 if (CHIP_IS_E1(bp))
 574                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 575                 else
 576                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 577                 return;
 578         }
 579
 580         /* set opcode and fixed command fields */
 581         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 582
 583         /* fill in addresses and len */
 584         dmae.src_addr_lo = U64_LO(dma_addr);
 585         dmae.src_addr_hi = U64_HI(dma_addr);
 586         dmae.dst_addr_lo = dst_addr >> 2;
 587         dmae.dst_addr_hi = 0;
 588         dmae.len = len32;
 589
 590         /* issue the command and wait for completion */
 591         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 592         if (rc) {
 593                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 594 #ifdef BNX2X_STOP_ON_ERROR
 595                 bnx2x_panic();
 596 #endif
 597         }
 598 }
 599
 600 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 601 {
 602         int rc;
 603         struct dmae_command dmae;
 604
 605         if (!bp->dmae_ready) {
 606                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 607                 int i;
 608
 609                 if (CHIP_IS_E1(bp))
 610                         for (i = 0; i < len32; i++)
 611                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 612                 else
 613                         for (i = 0; i < len32; i++)
 614                                 data[i] = REG_RD(bp, src_addr + i*4);
 615
 616                 return;
 617         }
 618
 619         /* set opcode and fixed command fields */
 620         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 621
 622         /* fill in addresses and len */
 623         dmae.src_addr_lo = src_addr >> 2;
 624         dmae.src_addr_hi = 0;
 625         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 626         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 627         dmae.len = len32;
 628
 629         /* issue the command and wait for completion */
 630         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 631         if (rc) {
 632                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 633 #ifdef BNX2X_STOP_ON_ERROR
 634                 bnx2x_panic();
 635 #endif
 636         }
 637 }
 638
 639 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 640                                       u32 addr, u32 len)
 641 {
 642         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 643         int offset = 0;
 644
 645         while (len > dmae_wr_max) {
 646                 bnx2x_write_dmae(bp, phys_addr + offset,
 647                                  addr + offset, dmae_wr_max);
 648                 offset += dmae_wr_max * 4;
 649                 len -= dmae_wr_max;
 650         }
 651
 652         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 653 }
 654
 655 enum storms {
 656            XSTORM,
 657            TSTORM,
 658            CSTORM,
 659            USTORM,
 660            MAX_STORMS
 661 };
 662
 663 #define STORMS_NUM 4
 664 #define REGS_IN_ENTRY 4
 665
 666 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 667                                               enum storms storm,
 668                                               int entry)
 669 {
 670         switch (storm) {
 671         case XSTORM:
 672                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 673         case TSTORM:
 674                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 675         case CSTORM:
 676                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 677         case USTORM:
 678                 return USTORM_ASSERT_LIST_OFFSET(entry);
 679         case MAX_STORMS:
 680         default:
 681                 BNX2X_ERR("unknown storm\n");
 682         }
 683         return -EINVAL;
 684 }
 685
 686 static int bnx2x_mc_assert(struct bnx2x *bp)
 687 {
 688         char last_idx;
 689         int i, j, rc = 0;
 690         enum storms storm;
 691         u32 regs[REGS_IN_ENTRY];
 692         u32 bar_storm_intmem[STORMS_NUM] = {
 693                 BAR_XSTRORM_INTMEM,
 694                 BAR_TSTRORM_INTMEM,
 695                 BAR_CSTRORM_INTMEM,
 696                 BAR_USTRORM_INTMEM
 697         };
 698         u32 storm_assert_list_index[STORMS_NUM] = {
 699                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 700                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 701                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 702                 USTORM_ASSERT_LIST_INDEX_OFFSET
 703         };
 704         char *storms_string[STORMS_NUM] = {
 705                 "XSTORM",
 706                 "TSTORM",
 707                 "CSTORM",
 708                 "USTORM"
 709         };
 710
 711         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 712                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 713                                    storm_assert_list_index[storm]);
 714                 if (last_idx)
 715                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 716                                   storms_string[storm], last_idx);
 717
 718                 /* print the asserts */
 719                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 720                         /* read a single assert entry */
 721                         for (j = 0; j < REGS_IN_ENTRY; j++)
 722                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 723                                           bnx2x_get_assert_list_entry(bp,
 724                                                                       storm,
 725                                                                       i) +
 726                                           sizeof(u32) * j);
 727
 728                         /* log entry if it contains a valid assert */
 729                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 730                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 731                                           storms_string[storm], i, regs[3],
 732                                           regs[2], regs[1], regs[0]);
 733                                 rc++;
 734                         } else {
 735                                 break;
 736                         }
 737                 }
 738         }
 739
 740         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
 741                   CHIP_IS_E1(bp) ? "everest1" :
 742                   CHIP_IS_E1H(bp) ? "everest1h" :
 743                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
 744                   BCM_5710_FW_MAJOR_VERSION,
 745                   BCM_5710_FW_MINOR_VERSION,
 746                   BCM_5710_FW_REVISION_VERSION);
 747
 748         return rc;
 749 }
 750
 751 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 752 #define SCRATCH_BUFFER_SIZE(bp) \
 753         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 754
 755 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 756 {
 757         u32 addr, val;
 758         u32 mark, offset;
 759         __be32 data[9];
 760         int word;
 761         u32 trace_shmem_base;
 762         if (BP_NOMCP(bp)) {
 763                 BNX2X_ERR("NO MCP - can not dump\n");
 764                 return;
 765         }
 766         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 767                 (bp->common.bc_ver & 0xff0000) >> 16,
 768                 (bp->common.bc_ver & 0xff00) >> 8,
 769                 (bp->common.bc_ver & 0xff));
 770
 771         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 772         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 773                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 774
 775         if (BP_PATH(bp) == 0)
 776                 trace_shmem_base = bp->common.shmem_base;
 777         else
 778                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 779
 780         /* sanity */
 781         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 782             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 783                                 SCRATCH_BUFFER_SIZE(bp)) {
 784                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 785                           trace_shmem_base);
 786                 return;
 787         }
 788
 789         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 790
 791         /* validate TRCB signature */
 792         mark = REG_RD(bp, addr);
 793         if (mark != MFW_TRACE_SIGNATURE) {
 794                 BNX2X_ERR("Trace buffer signature is missing.");
 795                 return ;
 796         }
 797
 798         /* read cyclic buffer pointer */
 799         addr += 4;
 800         mark = REG_RD(bp, addr);
 801         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 802         if (mark >= trace_shmem_base || mark < addr + 4) {
 803                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 804                 return;
 805         }
 806         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 807
 808         printk("%s", lvl);
 809
 810         /* dump buffer after the mark */
 811         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 812                 for (word = 0; word < 8; word++)
 813                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 814                 data[8] = 0x0;
 815                 pr_cont("%s", (char *)data);
 816         }
 817
 818         /* dump buffer before the mark */
 819         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 820                 for (word = 0; word < 8; word++)
 821                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 822                 data[8] = 0x0;
 823                 pr_cont("%s", (char *)data);
 824         }
 825         printk("%s" "end of fw dump\n", lvl);
 826 }
 827
 828 static void bnx2x_fw_dump(struct bnx2x *bp)
 829 {
 830         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 831 }
 832
 833 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 834 {
 835         int port = BP_PORT(bp);
 836         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 837         u32 val = REG_RD(bp, addr);
 838
 839         /* in E1 we must use only PCI configuration space to disable
 840          * MSI/MSIX capability
 841          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 842          */
 843         if (CHIP_IS_E1(bp)) {
 844                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 845                  * Use mask register to prevent from HC sending interrupts
 846                  * after we exit the function
 847                  */
 848                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 849
 850                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 851                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 852                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 853         } else
 854                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 855                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 856                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 857                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 858
 859         DP(NETIF_MSG_IFDOWN,
 860            "write %x to HC %d (addr 0x%x)\n",
 861            val, port, addr);
 862
 863         /* flush all outstanding writes */
 864         mmiowb();
 865
 866         REG_WR(bp, addr, val);
 867         if (REG_RD(bp, addr) != val)
 868                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 869 }
 870
 871 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 872 {
 873         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 874
 875         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 876                  IGU_PF_CONF_INT_LINE_EN |
 877                  IGU_PF_CONF_ATTN_BIT_EN);
 878
 879         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 880
 881         /* flush all outstanding writes */
 882         mmiowb();
 883
 884         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 885         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 886                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 887 }
 888
 889 static void bnx2x_int_disable(struct bnx2x *bp)
 890 {
 891         if (bp->common.int_block == INT_BLOCK_HC)
 892                 bnx2x_hc_int_disable(bp);
 893         else
 894                 bnx2x_igu_int_disable(bp);
 895 }
 896
 897 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 898 {
 899         int i;
 900         u16 j;
 901         struct hc_sp_status_block_data sp_sb_data;
 902         int func = BP_FUNC(bp);
 903 #ifdef BNX2X_STOP_ON_ERROR
 904         u16 start = 0, end = 0;
 905         u8 cos;
 906 #endif
 907         if (IS_PF(bp) && disable_int)
 908                 bnx2x_int_disable(bp);
 909
 910         bp->stats_state = STATS_STATE_DISABLED;
 911         bp->eth_stats.unrecoverable_error++;
 912         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 913
 914         BNX2X_ERR("begin crash dump -----------------\n");
 915
 916         /* Indices */
 917         /* Common */
 918         if (IS_PF(bp)) {
 919                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 920                 int data_size, cstorm_offset;
 921
 922                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 923                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 924                           bp->spq_prod_idx, bp->stats_counter);
 925                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 926                           def_sb->atten_status_block.attn_bits,
 927                           def_sb->atten_status_block.attn_bits_ack,
 928                           def_sb->atten_status_block.status_block_id,
 929                           def_sb->atten_status_block.attn_bits_index);
 930                 BNX2X_ERR("     def (");
 931                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 932                         pr_cont("0x%x%s",
 933                                 def_sb->sp_sb.index_values[i],
 934                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 935
 936                 data_size = sizeof(struct hc_sp_status_block_data) /
 937                             sizeof(u32);
 938                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 939                 for (i = 0; i < data_size; i++)
 940                         *((u32 *)&sp_sb_data + i) =
 941                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 942                                            i * sizeof(u32));
 943
 944                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 945                         sp_sb_data.igu_sb_id,
 946                         sp_sb_data.igu_seg_id,
 947                         sp_sb_data.p_func.pf_id,
 948                         sp_sb_data.p_func.vnic_id,
 949                         sp_sb_data.p_func.vf_id,
 950                         sp_sb_data.p_func.vf_valid,
 951                         sp_sb_data.state);
 952         }
 953
 954         for_each_eth_queue(bp, i) {
 955                 struct bnx2x_fastpath *fp = &bp->fp[i];
 956                 int loop;
 957                 struct hc_status_block_data_e2 sb_data_e2;
 958                 struct hc_status_block_data_e1x sb_data_e1x;
 959                 struct hc_status_block_sm  *hc_sm_p =
 960                         CHIP_IS_E1x(bp) ?
 961                         sb_data_e1x.common.state_machine :
 962                         sb_data_e2.common.state_machine;
 963                 struct hc_index_data *hc_index_p =
 964                         CHIP_IS_E1x(bp) ?
 965                         sb_data_e1x.index_data :
 966                         sb_data_e2.index_data;
 967                 u8 data_size, cos;
 968                 u32 *sb_data_p;
 969                 struct bnx2x_fp_txdata txdata;
 970
 971                 if (!bp->fp)
 972                         break;
 973
 974                 if (!fp->rx_cons_sb)
 975                         continue;
 976
 977                 /* Rx */
 978                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 979                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 980                           fp->rx_comp_prod,
 981                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 982                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 983                           fp->rx_sge_prod, fp->last_max_sge,
 984                           le16_to_cpu(fp->fp_hc_idx));
 985
 986                 /* Tx */
 987                 for_each_cos_in_tx_queue(fp, cos)
 988                 {
 989                         if (!fp->txdata_ptr[cos])
 990                                 break;
 991
 992                         txdata = *fp->txdata_ptr[cos];
 993
 994                         if (!txdata.tx_cons_sb)
 995                                 continue;
 996
 997                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 998                                   i, txdata.tx_pkt_prod,
 999                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1000                                   txdata.tx_bd_cons,
1001                                   le16_to_cpu(*txdata.tx_cons_sb));
1002                 }
1003
1004                 loop = CHIP_IS_E1x(bp) ?
1005                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1006
1007                 /* host sb data */
1008
1009                 if (IS_FCOE_FP(fp))
1010                         continue;
1011
1012                 BNX2X_ERR("     run indexes (");
1013                 for (j = 0; j < HC_SB_MAX_SM; j++)
1014                         pr_cont("0x%x%s",
1015                                fp->sb_running_index[j],
1016                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1017
1018                 BNX2X_ERR("     indexes (");
1019                 for (j = 0; j < loop; j++)
1020                         pr_cont("0x%x%s",
1021                                fp->sb_index_values[j],
1022                                (j == loop - 1) ? ")" : " ");
1023
1024                 /* VF cannot access FW refelection for status block */
1025                 if (IS_VF(bp))
1026                         continue;
1027
1028                 /* fw sb data */
1029                 data_size = CHIP_IS_E1x(bp) ?
1030                         sizeof(struct hc_status_block_data_e1x) :
1031                         sizeof(struct hc_status_block_data_e2);
1032                 data_size /= sizeof(u32);
1033                 sb_data_p = CHIP_IS_E1x(bp) ?
1034                         (u32 *)&sb_data_e1x :
1035                         (u32 *)&sb_data_e2;
1036                 /* copy sb data in here */
1037                 for (j = 0; j < data_size; j++)
1038                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1039                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1040                                 j * sizeof(u32));
1041
1042                 if (!CHIP_IS_E1x(bp)) {
1043                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1044                                 sb_data_e2.common.p_func.pf_id,
1045                                 sb_data_e2.common.p_func.vf_id,
1046                                 sb_data_e2.common.p_func.vf_valid,
1047                                 sb_data_e2.common.p_func.vnic_id,
1048                                 sb_data_e2.common.same_igu_sb_1b,
1049                                 sb_data_e2.common.state);
1050                 } else {
1051                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1052                                 sb_data_e1x.common.p_func.pf_id,
1053                                 sb_data_e1x.common.p_func.vf_id,
1054                                 sb_data_e1x.common.p_func.vf_valid,
1055                                 sb_data_e1x.common.p_func.vnic_id,
1056                                 sb_data_e1x.common.same_igu_sb_1b,
1057                                 sb_data_e1x.common.state);
1058                 }
1059
1060                 /* SB_SMs data */
1061                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1062                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1063                                 j, hc_sm_p[j].__flags,
1064                                 hc_sm_p[j].igu_sb_id,
1065                                 hc_sm_p[j].igu_seg_id,
1066                                 hc_sm_p[j].time_to_expire,
1067                                 hc_sm_p[j].timer_value);
1068                 }
1069
1070                 /* Indices data */
1071                 for (j = 0; j < loop; j++) {
1072                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1073                                hc_index_p[j].flags,
1074                                hc_index_p[j].timeout);
1075                 }
1076         }
1077
1078 #ifdef BNX2X_STOP_ON_ERROR
1079         if (IS_PF(bp)) {
1080                 /* event queue */
1081                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1082                 for (i = 0; i < NUM_EQ_DESC; i++) {
1083                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1084
1085                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1086                                   i, bp->eq_ring[i].message.opcode,
1087                                   bp->eq_ring[i].message.error);
1088                         BNX2X_ERR("data: %x %x %x\n",
1089                                   data[0], data[1], data[2]);
1090                 }
1091         }
1092
1093         /* Rings */
1094         /* Rx */
1095         for_each_valid_rx_queue(bp, i) {
1096                 struct bnx2x_fastpath *fp = &bp->fp[i];
1097
1098                 if (!bp->fp)
1099                         break;
1100
1101                 if (!fp->rx_cons_sb)
1102                         continue;
1103
1104                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1105                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1106                 for (j = start; j != end; j = RX_BD(j + 1)) {
1107                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1108                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1109
1110                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1111                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1112                 }
1113
1114                 start = RX_SGE(fp->rx_sge_prod);
1115                 end = RX_SGE(fp->last_max_sge);
1116                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1117                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1118                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1119
1120                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1121                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1122                 }
1123
1124                 start = RCQ_BD(fp->rx_comp_cons - 10);
1125                 end = RCQ_BD(fp->rx_comp_cons + 503);
1126                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1127                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1128
1129                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1130                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1131                 }
1132         }
1133
1134         /* Tx */
1135         for_each_valid_tx_queue(bp, i) {
1136                 struct bnx2x_fastpath *fp = &bp->fp[i];
1137
1138                 if (!bp->fp)
1139                         break;
1140
1141                 for_each_cos_in_tx_queue(fp, cos) {
1142                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1143
1144                         if (!fp->txdata_ptr[cos])
1145                                 break;
1146
1147                         if (!txdata->tx_cons_sb)
1148                                 continue;
1149
1150                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1151                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1152                         for (j = start; j != end; j = TX_BD(j + 1)) {
1153                                 struct sw_tx_bd *sw_bd =
1154                                         &txdata->tx_buf_ring[j];
1155
1156                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1157                                           i, cos, j, sw_bd->skb,
1158                                           sw_bd->first_bd);
1159                         }
1160
1161                         start = TX_BD(txdata->tx_bd_cons - 10);
1162                         end = TX_BD(txdata->tx_bd_cons + 254);
1163                         for (j = start; j != end; j = TX_BD(j + 1)) {
1164                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1165
1166                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1167                                           i, cos, j, tx_bd[0], tx_bd[1],
1168                                           tx_bd[2], tx_bd[3]);
1169                         }
1170                 }
1171         }
1172 #endif
1173         if (IS_PF(bp)) {
1174                 bnx2x_fw_dump(bp);
1175                 bnx2x_mc_assert(bp);
1176         }
1177         BNX2X_ERR("end crash dump -----------------\n");
1178 }
1179
1180 /*
1181  * FLR Support for E2
1182  *
1183  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1184  * initialization.
1185  */
1186 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1187 #define FLR_WAIT_INTERVAL       50      /* usec */
1188 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1189
1190 struct pbf_pN_buf_regs {
1191         int pN;
1192         u32 init_crd;
1193         u32 crd;
1194         u32 crd_freed;
1195 };
1196
1197 struct pbf_pN_cmd_regs {
1198         int pN;
1199         u32 lines_occup;
1200         u32 lines_freed;
1201 };
1202
1203 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1204                                      struct pbf_pN_buf_regs *regs,
1205                                      u32 poll_count)
1206 {
1207         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1208         u32 cur_cnt = poll_count;
1209
1210         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1211         crd = crd_start = REG_RD(bp, regs->crd);
1212         init_crd = REG_RD(bp, regs->init_crd);
1213
1214         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1215         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1216         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1217
1218         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1219                (init_crd - crd_start))) {
1220                 if (cur_cnt--) {
1221                         udelay(FLR_WAIT_INTERVAL);
1222                         crd = REG_RD(bp, regs->crd);
1223                         crd_freed = REG_RD(bp, regs->crd_freed);
1224                 } else {
1225                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1226                            regs->pN);
1227                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1228                            regs->pN, crd);
1229                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1230                            regs->pN, crd_freed);
1231                         break;
1232                 }
1233         }
1234         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1235            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1236 }
1237
1238 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1239                                      struct pbf_pN_cmd_regs *regs,
1240                                      u32 poll_count)
1241 {
1242         u32 occup, to_free, freed, freed_start;
1243         u32 cur_cnt = poll_count;
1244
1245         occup = to_free = REG_RD(bp, regs->lines_occup);
1246         freed = freed_start = REG_RD(bp, regs->lines_freed);
1247
1248         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1249         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1250
1251         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1252                 if (cur_cnt--) {
1253                         udelay(FLR_WAIT_INTERVAL);
1254                         occup = REG_RD(bp, regs->lines_occup);
1255                         freed = REG_RD(bp, regs->lines_freed);
1256                 } else {
1257                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1258                            regs->pN);
1259                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1260                            regs->pN, occup);
1261                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1262                            regs->pN, freed);
1263                         break;
1264                 }
1265         }
1266         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1267            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1268 }
1269
1270 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1271                                     u32 expected, u32 poll_count)
1272 {
1273         u32 cur_cnt = poll_count;
1274         u32 val;
1275
1276         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1277                 udelay(FLR_WAIT_INTERVAL);
1278
1279         return val;
1280 }
1281
1282 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1283                                     char *msg, u32 poll_cnt)
1284 {
1285         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1286         if (val != 0) {
1287                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1288                 return 1;
1289         }
1290         return 0;
1291 }
1292
1293 /* Common routines with VF FLR cleanup */
1294 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1295 {
1296         /* adjust polling timeout */
1297         if (CHIP_REV_IS_EMUL(bp))
1298                 return FLR_POLL_CNT * 2000;
1299
1300         if (CHIP_REV_IS_FPGA(bp))
1301                 return FLR_POLL_CNT * 120;
1302
1303         return FLR_POLL_CNT;
1304 }
1305
1306 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1307 {
1308         struct pbf_pN_cmd_regs cmd_regs[] = {
1309                 {0, (CHIP_IS_E3B0(bp)) ?
1310                         PBF_REG_TQ_OCCUPANCY_Q0 :
1311                         PBF_REG_P0_TQ_OCCUPANCY,
1312                     (CHIP_IS_E3B0(bp)) ?
1313                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1314                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1315                 {1, (CHIP_IS_E3B0(bp)) ?
1316                         PBF_REG_TQ_OCCUPANCY_Q1 :
1317                         PBF_REG_P1_TQ_OCCUPANCY,
1318                     (CHIP_IS_E3B0(bp)) ?
1319                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1320                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1321                 {4, (CHIP_IS_E3B0(bp)) ?
1322                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1323                         PBF_REG_P4_TQ_OCCUPANCY,
1324                     (CHIP_IS_E3B0(bp)) ?
1325                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1326                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1327         };
1328
1329         struct pbf_pN_buf_regs buf_regs[] = {
1330                 {0, (CHIP_IS_E3B0(bp)) ?
1331                         PBF_REG_INIT_CRD_Q0 :
1332                         PBF_REG_P0_INIT_CRD ,
1333                     (CHIP_IS_E3B0(bp)) ?
1334                         PBF_REG_CREDIT_Q0 :
1335                         PBF_REG_P0_CREDIT,
1336                     (CHIP_IS_E3B0(bp)) ?
1337                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1338                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1339                 {1, (CHIP_IS_E3B0(bp)) ?
1340                         PBF_REG_INIT_CRD_Q1 :
1341                         PBF_REG_P1_INIT_CRD,
1342                     (CHIP_IS_E3B0(bp)) ?
1343                         PBF_REG_CREDIT_Q1 :
1344                         PBF_REG_P1_CREDIT,
1345                     (CHIP_IS_E3B0(bp)) ?
1346                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1347                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1348                 {4, (CHIP_IS_E3B0(bp)) ?
1349                         PBF_REG_INIT_CRD_LB_Q :
1350                         PBF_REG_P4_INIT_CRD,
1351                     (CHIP_IS_E3B0(bp)) ?
1352                         PBF_REG_CREDIT_LB_Q :
1353                         PBF_REG_P4_CREDIT,
1354                     (CHIP_IS_E3B0(bp)) ?
1355                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1356                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1357         };
1358
1359         int i;
1360
1361         /* Verify the command queues are flushed P0, P1, P4 */
1362         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1363                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1364
1365         /* Verify the transmission buffers are flushed P0, P1, P4 */
1366         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1367                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1368 }
1369
1370 #define OP_GEN_PARAM(param) \
1371         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1372
1373 #define OP_GEN_TYPE(type) \
1374         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1375
1376 #define OP_GEN_AGG_VECT(index) \
1377         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1378
1379 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1380 {
1381         u32 op_gen_command = 0;
1382         u32 comp_addr = BAR_CSTRORM_INTMEM +
1383                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1384         int ret = 0;
1385
1386         if (REG_RD(bp, comp_addr)) {
1387                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1388                 return 1;
1389         }
1390
1391         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1392         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1393         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1394         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1395
1396         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1397         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1398
1399         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1400                 BNX2X_ERR("FW final cleanup did not succeed\n");
1401                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1402                    (REG_RD(bp, comp_addr)));
1403                 bnx2x_panic();
1404                 return 1;
1405         }
1406         /* Zero completion for next FLR */
1407         REG_WR(bp, comp_addr, 0);
1408
1409         return ret;
1410 }
1411
1412 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1413 {
1414         u16 status;
1415
1416         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1417         return status & PCI_EXP_DEVSTA_TRPND;
1418 }
1419
1420 /* PF FLR specific routines
1421 */
1422 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1423 {
1424         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1425         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1426                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1427                         "CFC PF usage counter timed out",
1428                         poll_cnt))
1429                 return 1;
1430
1431         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1432         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1433                         DORQ_REG_PF_USAGE_CNT,
1434                         "DQ PF usage counter timed out",
1435                         poll_cnt))
1436                 return 1;
1437
1438         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1439         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1440                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1441                         "QM PF usage counter timed out",
1442                         poll_cnt))
1443                 return 1;
1444
1445         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1446         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1447                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1448                         "Timers VNIC usage counter timed out",
1449                         poll_cnt))
1450                 return 1;
1451         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1452                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1453                         "Timers NUM_SCANS usage counter timed out",
1454                         poll_cnt))
1455                 return 1;
1456
1457         /* Wait DMAE PF usage counter to zero */
1458         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1459                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1460                         "DMAE command register timed out",
1461                         poll_cnt))
1462                 return 1;
1463
1464         return 0;
1465 }
1466
1467 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1468 {
1469         u32 val;
1470
1471         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1472         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1473
1474         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1475         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1476
1477         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1478         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1479
1480         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1481         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1482
1483         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1484         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1485
1486         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1487         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1488
1489         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1490         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1491
1492         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1493         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1494            val);
1495 }
1496
1497 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1498 {
1499         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1500
1501         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1502
1503         /* Re-enable PF target read access */
1504         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1505
1506         /* Poll HW usage counters */
1507         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1508         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1509                 return -EBUSY;
1510
1511         /* Zero the igu 'trailing edge' and 'leading edge' */
1512
1513         /* Send the FW cleanup command */
1514         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1515                 return -EBUSY;
1516
1517         /* ATC cleanup */
1518
1519         /* Verify TX hw is flushed */
1520         bnx2x_tx_hw_flushed(bp, poll_cnt);
1521
1522         /* Wait 100ms (not adjusted according to platform) */
1523         msleep(100);
1524
1525         /* Verify no pending pci transactions */
1526         if (bnx2x_is_pcie_pending(bp->pdev))
1527                 BNX2X_ERR("PCIE Transactions still pending\n");
1528
1529         /* Debug */
1530         bnx2x_hw_enable_status(bp);
1531
1532         /*
1533          * Master enable - Due to WB DMAE writes performed before this
1534          * register is re-initialized as part of the regular function init
1535          */
1536         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1537
1538         return 0;
1539 }
1540
1541 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1542 {
1543         int port = BP_PORT(bp);
1544         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1545         u32 val = REG_RD(bp, addr);
1546         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1547         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1548         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1549
1550         if (msix) {
1551                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1552                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1553                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1554                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1555                 if (single_msix)
1556                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1557         } else if (msi) {
1558                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1559                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1560                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1561                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1562         } else {
1563                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1564                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1565                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1566                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1567
1568                 if (!CHIP_IS_E1(bp)) {
1569                         DP(NETIF_MSG_IFUP,
1570                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1571
1572                         REG_WR(bp, addr, val);
1573
1574                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1575                 }
1576         }
1577
1578         if (CHIP_IS_E1(bp))
1579                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1580
1581         DP(NETIF_MSG_IFUP,
1582            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1583            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1584
1585         REG_WR(bp, addr, val);
1586         /*
1587          * Ensure that HC_CONFIG is written before leading/trailing edge config
1588          */
1589         mmiowb();
1590         barrier();
1591
1592         if (!CHIP_IS_E1(bp)) {
1593                 /* init leading/trailing edge */
1594                 if (IS_MF(bp)) {
1595                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1596                         if (bp->port.pmf)
1597                                 /* enable nig and gpio3 attention */
1598                                 val |= 0x1100;
1599                 } else
1600                         val = 0xffff;
1601
1602                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1603                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1604         }
1605
1606         /* Make sure that interrupts are indeed enabled from here on */
1607         mmiowb();
1608 }
1609
1610 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1611 {
1612         u32 val;
1613         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1614         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1615         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1616
1617         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1618
1619         if (msix) {
1620                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1621                          IGU_PF_CONF_SINGLE_ISR_EN);
1622                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1623                         IGU_PF_CONF_ATTN_BIT_EN);
1624
1625                 if (single_msix)
1626                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1627         } else if (msi) {
1628                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1629                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1630                         IGU_PF_CONF_ATTN_BIT_EN |
1631                         IGU_PF_CONF_SINGLE_ISR_EN);
1632         } else {
1633                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1634                 val |= (IGU_PF_CONF_INT_LINE_EN |
1635                         IGU_PF_CONF_ATTN_BIT_EN |
1636                         IGU_PF_CONF_SINGLE_ISR_EN);
1637         }
1638
1639         /* Clean previous status - need to configure igu prior to ack*/
1640         if ((!msix) || single_msix) {
1641                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1642                 bnx2x_ack_int(bp);
1643         }
1644
1645         val |= IGU_PF_CONF_FUNC_EN;
1646
1647         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1648            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1649
1650         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1651
1652         if (val & IGU_PF_CONF_INT_LINE_EN)
1653                 pci_intx(bp->pdev, true);
1654
1655         barrier();
1656
1657         /* init leading/trailing edge */
1658         if (IS_MF(bp)) {
1659                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1660                 if (bp->port.pmf)
1661                         /* enable nig and gpio3 attention */
1662                         val |= 0x1100;
1663         } else
1664                 val = 0xffff;
1665
1666         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1667         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1668
1669         /* Make sure that interrupts are indeed enabled from here on */
1670         mmiowb();
1671 }
1672
1673 void bnx2x_int_enable(struct bnx2x *bp)
1674 {
1675         if (bp->common.int_block == INT_BLOCK_HC)
1676                 bnx2x_hc_int_enable(bp);
1677         else
1678                 bnx2x_igu_int_enable(bp);
1679 }
1680
1681 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1682 {
1683         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1684         int i, offset;
1685
1686         if (disable_hw)
1687                 /* prevent the HW from sending interrupts */
1688                 bnx2x_int_disable(bp);
1689
1690         /* make sure all ISRs are done */
1691         if (msix) {
1692                 synchronize_irq(bp->msix_table[0].vector);
1693                 offset = 1;
1694                 if (CNIC_SUPPORT(bp))
1695                         offset++;
1696                 for_each_eth_queue(bp, i)
1697                         synchronize_irq(bp->msix_table[offset++].vector);
1698         } else
1699                 synchronize_irq(bp->pdev->irq);
1700
1701         /* make sure sp_task is not running */
1702         cancel_delayed_work(&bp->sp_task);
1703         cancel_delayed_work(&bp->period_task);
1704         flush_workqueue(bnx2x_wq);
1705 }
1706
1707 /* fast path */
1708
1709 /*
1710  * General service functions
1711  */
1712
1713 /* Return true if succeeded to acquire the lock */
1714 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1715 {
1716         u32 lock_status;
1717         u32 resource_bit = (1 << resource);
1718         int func = BP_FUNC(bp);
1719         u32 hw_lock_control_reg;
1720
1721         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1722            "Trying to take a lock on resource %d\n", resource);
1723
1724         /* Validating that the resource is within range */
1725         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1726                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1727                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1728                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1729                 return false;
1730         }
1731
1732         if (func <= 5)
1733                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1734         else
1735                 hw_lock_control_reg =
1736                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1737
1738         /* Try to acquire the lock */
1739         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1740         lock_status = REG_RD(bp, hw_lock_control_reg);
1741         if (lock_status & resource_bit)
1742                 return true;
1743
1744         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1745            "Failed to get a lock on resource %d\n", resource);
1746         return false;
1747 }
1748
1749 /**
1750  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1751  *
1752  * @bp: driver handle
1753  *
1754  * Returns the recovery leader resource id according to the engine this function
1755  * belongs to. Currently only only 2 engines is supported.
1756  */
1757 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1758 {
1759         if (BP_PATH(bp))
1760                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1761         else
1762                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1763 }
1764
1765 /**
1766  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1767  *
1768  * @bp: driver handle
1769  *
1770  * Tries to acquire a leader lock for current engine.
1771  */
1772 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1773 {
1774         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1775 }
1776
1777 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1778
1779 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1780 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1781 {
1782         /* Set the interrupt occurred bit for the sp-task to recognize it
1783          * must ack the interrupt and transition according to the IGU
1784          * state machine.
1785          */
1786         atomic_set(&bp->interrupt_occurred, 1);
1787
1788         /* The sp_task must execute only after this bit
1789          * is set, otherwise we will get out of sync and miss all
1790          * further interrupts. Hence, the barrier.
1791          */
1792         smp_wmb();
1793
1794         /* schedule sp_task to workqueue */
1795         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1796 }
1797
1798 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1799 {
1800         struct bnx2x *bp = fp->bp;
1801         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1802         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1803         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1804         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1805
1806         DP(BNX2X_MSG_SP,
1807            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1808            fp->index, cid, command, bp->state,
1809            rr_cqe->ramrod_cqe.ramrod_type);
1810
1811         /* If cid is within VF range, replace the slowpath object with the
1812          * one corresponding to this VF
1813          */
1814         if (cid >= BNX2X_FIRST_VF_CID  &&
1815             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1816                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1817
1818         switch (command) {
1819         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1820                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1821                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1822                 break;
1823
1824         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1825                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1826                 drv_cmd = BNX2X_Q_CMD_SETUP;
1827                 break;
1828
1829         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1830                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1831                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1832                 break;
1833
1834         case (RAMROD_CMD_ID_ETH_HALT):
1835                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1836                 drv_cmd = BNX2X_Q_CMD_HALT;
1837                 break;
1838
1839         case (RAMROD_CMD_ID_ETH_TERMINATE):
1840                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1841                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1842                 break;
1843
1844         case (RAMROD_CMD_ID_ETH_EMPTY):
1845                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1846                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1847                 break;
1848
1849         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1850                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1851                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1852                 break;
1853
1854         default:
1855                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1856                           command, fp->index);
1857                 return;
1858         }
1859
1860         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1861             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1862                 /* q_obj->complete_cmd() failure means that this was
1863                  * an unexpected completion.
1864                  *
1865                  * In this case we don't want to increase the bp->spq_left
1866                  * because apparently we haven't sent this command the first
1867                  * place.
1868                  */
1869 #ifdef BNX2X_STOP_ON_ERROR
1870                 bnx2x_panic();
1871 #else
1872                 return;
1873 #endif
1874
1875         smp_mb__before_atomic();
1876         atomic_inc(&bp->cq_spq_left);
1877         /* push the change in bp->spq_left and towards the memory */
1878         smp_mb__after_atomic();
1879
1880         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1881
1882         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1883             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1884                 /* if Q update ramrod is completed for last Q in AFEX vif set
1885                  * flow, then ACK MCP at the end
1886                  *
1887                  * mark pending ACK to MCP bit.
1888                  * prevent case that both bits are cleared.
1889                  * At the end of load/unload driver checks that
1890                  * sp_state is cleared, and this order prevents
1891                  * races
1892                  */
1893                 smp_mb__before_atomic();
1894                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1895                 wmb();
1896                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1897                 smp_mb__after_atomic();
1898
1899                 /* schedule the sp task as mcp ack is required */
1900                 bnx2x_schedule_sp_task(bp);
1901         }
1902
1903         return;
1904 }
1905
1906 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1907 {
1908         struct bnx2x *bp = netdev_priv(dev_instance);
1909         u16 status = bnx2x_ack_int(bp);
1910         u16 mask;
1911         int i;
1912         u8 cos;
1913
1914         /* Return here if interrupt is shared and it's not for us */
1915         if (unlikely(status == 0)) {
1916                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1917                 return IRQ_NONE;
1918         }
1919         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1920
1921 #ifdef BNX2X_STOP_ON_ERROR
1922         if (unlikely(bp->panic))
1923                 return IRQ_HANDLED;
1924 #endif
1925
1926         for_each_eth_queue(bp, i) {
1927                 struct bnx2x_fastpath *fp = &bp->fp[i];
1928
1929                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1930                 if (status & mask) {
1931                         /* Handle Rx or Tx according to SB id */
1932                         for_each_cos_in_tx_queue(fp, cos)
1933                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1934                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1935                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1936                         status &= ~mask;
1937                 }
1938         }
1939
1940         if (CNIC_SUPPORT(bp)) {
1941                 mask = 0x2;
1942                 if (status & (mask | 0x1)) {
1943                         struct cnic_ops *c_ops = NULL;
1944
1945                         rcu_read_lock();
1946                         c_ops = rcu_dereference(bp->cnic_ops);
1947                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1948                                       CNIC_DRV_STATE_HANDLES_IRQ))
1949                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1950                         rcu_read_unlock();
1951
1952                         status &= ~mask;
1953                 }
1954         }
1955
1956         if (unlikely(status & 0x1)) {
1957
1958                 /* schedule sp task to perform default status block work, ack
1959                  * attentions and enable interrupts.
1960                  */
1961                 bnx2x_schedule_sp_task(bp);
1962
1963                 status &= ~0x1;
1964                 if (!status)
1965                         return IRQ_HANDLED;
1966         }
1967
1968         if (unlikely(status))
1969                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1970                    status);
1971
1972         return IRQ_HANDLED;
1973 }
1974
1975 /* Link */
1976
1977 /*
1978  * General service functions
1979  */
1980
1981 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1982 {
1983         u32 lock_status;
1984         u32 resource_bit = (1 << resource);
1985         int func = BP_FUNC(bp);
1986         u32 hw_lock_control_reg;
1987         int cnt;
1988
1989         /* Validating that the resource is within range */
1990         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1991                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1992                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1993                 return -EINVAL;
1994         }
1995
1996         if (func <= 5) {
1997                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1998         } else {
1999                 hw_lock_control_reg =
2000                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2001         }
2002
2003         /* Validating that the resource is not already taken */
2004         lock_status = REG_RD(bp, hw_lock_control_reg);
2005         if (lock_status & resource_bit) {
2006                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2007                    lock_status, resource_bit);
2008                 return -EEXIST;
2009         }
2010
2011         /* Try for 5 second every 5ms */
2012         for (cnt = 0; cnt < 1000; cnt++) {
2013                 /* Try to acquire the lock */
2014                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2015                 lock_status = REG_RD(bp, hw_lock_control_reg);
2016                 if (lock_status & resource_bit)
2017                         return 0;
2018
2019                 usleep_range(5000, 10000);
2020         }
2021         BNX2X_ERR("Timeout\n");
2022         return -EAGAIN;
2023 }
2024
2025 int bnx2x_release_leader_lock(struct bnx2x *bp)
2026 {
2027         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2028 }
2029
2030 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2031 {
2032         u32 lock_status;
2033         u32 resource_bit = (1 << resource);
2034         int func = BP_FUNC(bp);
2035         u32 hw_lock_control_reg;
2036
2037         /* Validating that the resource is within range */
2038         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2039                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2040                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2041                 return -EINVAL;
2042         }
2043
2044         if (func <= 5) {
2045                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2046         } else {
2047                 hw_lock_control_reg =
2048                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2049         }
2050
2051         /* Validating that the resource is currently taken */
2052         lock_status = REG_RD(bp, hw_lock_control_reg);
2053         if (!(lock_status & resource_bit)) {
2054                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2055                           lock_status, resource_bit);
2056                 return -EFAULT;
2057         }
2058
2059         REG_WR(bp, hw_lock_control_reg, resource_bit);
2060         return 0;
2061 }
2062
2063 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2064 {
2065         /* The GPIO should be swapped if swap register is set and active */
2066         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2067                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2068         int gpio_shift = gpio_num +
2069                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2070         u32 gpio_mask = (1 << gpio_shift);
2071         u32 gpio_reg;
2072         int value;
2073
2074         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2075                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2076                 return -EINVAL;
2077         }
2078
2079         /* read GPIO value */
2080         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2081
2082         /* get the requested pin value */
2083         if ((gpio_reg & gpio_mask) == gpio_mask)
2084                 value = 1;
2085         else
2086                 value = 0;
2087
2088         return value;
2089 }
2090
2091 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2092 {
2093         /* The GPIO should be swapped if swap register is set and active */
2094         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2095                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2096         int gpio_shift = gpio_num +
2097                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2098         u32 gpio_mask = (1 << gpio_shift);
2099         u32 gpio_reg;
2100
2101         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2102                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2103                 return -EINVAL;
2104         }
2105
2106         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2107         /* read GPIO and mask except the float bits */
2108         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2109
2110         switch (mode) {
2111         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2112                 DP(NETIF_MSG_LINK,
2113                    "Set GPIO %d (shift %d) -> output low\n",
2114                    gpio_num, gpio_shift);
2115                 /* clear FLOAT and set CLR */
2116                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2117                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2118                 break;
2119
2120         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2121                 DP(NETIF_MSG_LINK,
2122                    "Set GPIO %d (shift %d) -> output high\n",
2123                    gpio_num, gpio_shift);
2124                 /* clear FLOAT and set SET */
2125                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2126                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2127                 break;
2128
2129         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2130                 DP(NETIF_MSG_LINK,
2131                    "Set GPIO %d (shift %d) -> input\n",
2132                    gpio_num, gpio_shift);
2133                 /* set FLOAT */
2134                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2135                 break;
2136
2137         default:
2138                 break;
2139         }
2140
2141         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2142         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2143
2144         return 0;
2145 }
2146
2147 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2148 {
2149         u32 gpio_reg = 0;
2150         int rc = 0;
2151
2152         /* Any port swapping should be handled by caller. */
2153
2154         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2155         /* read GPIO and mask except the float bits */
2156         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2157         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2158         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2159         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2160
2161         switch (mode) {
2162         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2163                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2164                 /* set CLR */
2165                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2166                 break;
2167
2168         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2169                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2170                 /* set SET */
2171                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2172                 break;
2173
2174         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2175                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2176                 /* set FLOAT */
2177                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2178                 break;
2179
2180         default:
2181                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2182                 rc = -EINVAL;
2183                 break;
2184         }
2185
2186         if (rc == 0)
2187                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2188
2189         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2190
2191         return rc;
2192 }
2193
2194 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2195 {
2196         /* The GPIO should be swapped if swap register is set and active */
2197         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2198                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2199         int gpio_shift = gpio_num +
2200                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2201         u32 gpio_mask = (1 << gpio_shift);
2202         u32 gpio_reg;
2203
2204         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2205                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2206                 return -EINVAL;
2207         }
2208
2209         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2210         /* read GPIO int */
2211         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2212
2213         switch (mode) {
2214         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2215                 DP(NETIF_MSG_LINK,
2216                    "Clear GPIO INT %d (shift %d) -> output low\n",
2217                    gpio_num, gpio_shift);
2218                 /* clear SET and set CLR */
2219                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2220                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2221                 break;
2222
2223         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2224                 DP(NETIF_MSG_LINK,
2225                    "Set GPIO INT %d (shift %d) -> output high\n",
2226                    gpio_num, gpio_shift);
2227                 /* clear CLR and set SET */
2228                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2229                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2230                 break;
2231
2232         default:
2233                 break;
2234         }
2235
2236         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2237         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2238
2239         return 0;
2240 }
2241
2242 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2243 {
2244         u32 spio_reg;
2245
2246         /* Only 2 SPIOs are configurable */
2247         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2248                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2249                 return -EINVAL;
2250         }
2251
2252         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2253         /* read SPIO and mask except the float bits */
2254         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2255
2256         switch (mode) {
2257         case MISC_SPIO_OUTPUT_LOW:
2258                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2259                 /* clear FLOAT and set CLR */
2260                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2261                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2262                 break;
2263
2264         case MISC_SPIO_OUTPUT_HIGH:
2265                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2266                 /* clear FLOAT and set SET */
2267                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2268                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2269                 break;
2270
2271         case MISC_SPIO_INPUT_HI_Z:
2272                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2273                 /* set FLOAT */
2274                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2275                 break;
2276
2277         default:
2278                 break;
2279         }
2280
2281         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2282         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2283
2284         return 0;
2285 }
2286
2287 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2288 {
2289         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2290
2291         bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2292                                            ADVERTISED_Pause);
2293         switch (bp->link_vars.ieee_fc &
2294                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2295         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2296                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2297                                                   ADVERTISED_Pause);
2298                 break;
2299
2300         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2301                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2302                 break;
2303
2304         default:
2305                 break;
2306         }
2307 }
2308
2309 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2310 {
2311         /* Initialize link parameters structure variables
2312          * It is recommended to turn off RX FC for jumbo frames
2313          *  for better performance
2314          */
2315         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2316                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2317         else
2318                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2319 }
2320
2321 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2322 {
2323         u32 pause_enabled = 0;
2324
2325         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2326                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2327                         pause_enabled = 1;
2328
2329                 REG_WR(bp, BAR_USTRORM_INTMEM +
2330                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2331                        pause_enabled);
2332         }
2333
2334         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2335            pause_enabled ? "enabled" : "disabled");
2336 }
2337
2338 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2339 {
2340         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2341         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2342
2343         if (!BP_NOMCP(bp)) {
2344                 bnx2x_set_requested_fc(bp);
2345                 bnx2x_acquire_phy_lock(bp);
2346
2347                 if (load_mode == LOAD_DIAG) {
2348                         struct link_params *lp = &bp->link_params;
2349                         lp->loopback_mode = LOOPBACK_XGXS;
2350                         /* do PHY loopback at 10G speed, if possible */
2351                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2352                                 if (lp->speed_cap_mask[cfx_idx] &
2353                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2354                                         lp->req_line_speed[cfx_idx] =
2355                                         SPEED_10000;
2356                                 else
2357                                         lp->req_line_speed[cfx_idx] =
2358                                         SPEED_1000;
2359                         }
2360                 }
2361
2362                 if (load_mode == LOAD_LOOPBACK_EXT) {
2363                         struct link_params *lp = &bp->link_params;
2364                         lp->loopback_mode = LOOPBACK_EXT;
2365                 }
2366
2367                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2368
2369                 bnx2x_release_phy_lock(bp);
2370
2371                 bnx2x_init_dropless_fc(bp);
2372
2373                 bnx2x_calc_fc_adv(bp);
2374
2375                 if (bp->link_vars.link_up) {
2376                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2377                         bnx2x_link_report(bp);
2378                 }
2379                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2380                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2381                 return rc;
2382         }
2383         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2384         return -EINVAL;
2385 }
2386
2387 void bnx2x_link_set(struct bnx2x *bp)
2388 {
2389         if (!BP_NOMCP(bp)) {
2390                 bnx2x_acquire_phy_lock(bp);
2391                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2392                 bnx2x_release_phy_lock(bp);
2393
2394                 bnx2x_init_dropless_fc(bp);
2395
2396                 bnx2x_calc_fc_adv(bp);
2397         } else
2398                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2399 }
2400
2401 static void bnx2x__link_reset(struct bnx2x *bp)
2402 {
2403         if (!BP_NOMCP(bp)) {
2404                 bnx2x_acquire_phy_lock(bp);
2405                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2406                 bnx2x_release_phy_lock(bp);
2407         } else
2408                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2409 }
2410
2411 void bnx2x_force_link_reset(struct bnx2x *bp)
2412 {
2413         bnx2x_acquire_phy_lock(bp);
2414         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2415         bnx2x_release_phy_lock(bp);
2416 }
2417
2418 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2419 {
2420         u8 rc = 0;
2421
2422         if (!BP_NOMCP(bp)) {
2423                 bnx2x_acquire_phy_lock(bp);
2424                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2425                                      is_serdes);
2426                 bnx2x_release_phy_lock(bp);
2427         } else
2428                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2429
2430         return rc;
2431 }
2432
2433 /* Calculates the sum of vn_min_rates.
2434    It's needed for further normalizing of the min_rates.
2435    Returns:
2436      sum of vn_min_rates.
2437        or
2438      0 - if all the min_rates are 0.
2439      In the later case fairness algorithm should be deactivated.
2440      If not all min_rates are zero then those that are zeroes will be set to 1.
2441  */
2442 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2443                                       struct cmng_init_input *input)
2444 {
2445         int all_zero = 1;
2446         int vn;
2447
2448         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2449                 u32 vn_cfg = bp->mf_config[vn];
2450                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2451                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2452
2453                 /* Skip hidden vns */
2454                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2455                         vn_min_rate = 0;
2456                 /* If min rate is zero - set it to 1 */
2457                 else if (!vn_min_rate)
2458                         vn_min_rate = DEF_MIN_RATE;
2459                 else
2460                         all_zero = 0;
2461
2462                 input->vnic_min_rate[vn] = vn_min_rate;
2463         }
2464
2465         /* if ETS or all min rates are zeros - disable fairness */
2466         if (BNX2X_IS_ETS_ENABLED(bp)) {
2467                 input->flags.cmng_enables &=
2468                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2469                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2470         } else if (all_zero) {
2471                 input->flags.cmng_enables &=
2472                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2473                 DP(NETIF_MSG_IFUP,
2474                    "All MIN values are zeroes fairness will be disabled\n");
2475         } else
2476                 input->flags.cmng_enables |=
2477                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2478 }
2479
2480 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2481                                     struct cmng_init_input *input)
2482 {
2483         u16 vn_max_rate;
2484         u32 vn_cfg = bp->mf_config[vn];
2485
2486         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2487                 vn_max_rate = 0;
2488         else {
2489                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2490
2491                 if (IS_MF_SI(bp)) {
2492                         /* maxCfg in percents of linkspeed */
2493                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2494                 } else /* SD modes */
2495                         /* maxCfg is absolute in 100Mb units */
2496                         vn_max_rate = maxCfg * 100;
2497         }
2498
2499         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2500
2501         input->vnic_max_rate[vn] = vn_max_rate;
2502 }
2503
2504 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2505 {
2506         if (CHIP_REV_IS_SLOW(bp))
2507                 return CMNG_FNS_NONE;
2508         if (IS_MF(bp))
2509                 return CMNG_FNS_MINMAX;
2510
2511         return CMNG_FNS_NONE;
2512 }
2513
2514 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2515 {
2516         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2517
2518         if (BP_NOMCP(bp))
2519                 return; /* what should be the default value in this case */
2520
2521         /* For 2 port configuration the absolute function number formula
2522          * is:
2523          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2524          *
2525          *      and there are 4 functions per port
2526          *
2527          * For 4 port configuration it is
2528          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2529          *
2530          *      and there are 2 functions per port
2531          */
2532         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2533                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2534
2535                 if (func >= E1H_FUNC_MAX)
2536                         break;
2537
2538                 bp->mf_config[vn] =
2539                         MF_CFG_RD(bp, func_mf_config[func].config);
2540         }
2541         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2542                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2543                 bp->flags |= MF_FUNC_DIS;
2544         } else {
2545                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2546                 bp->flags &= ~MF_FUNC_DIS;
2547         }
2548 }
2549
2550 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2551 {
2552         struct cmng_init_input input;
2553         memset(&input, 0, sizeof(struct cmng_init_input));
2554
2555         input.port_rate = bp->link_vars.line_speed;
2556
2557         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2558                 int vn;
2559
2560                 /* read mf conf from shmem */
2561                 if (read_cfg)
2562                         bnx2x_read_mf_cfg(bp);
2563
2564                 /* vn_weight_sum and enable fairness if not 0 */
2565                 bnx2x_calc_vn_min(bp, &input);
2566
2567                 /* calculate and set min-max rate for each vn */
2568                 if (bp->port.pmf)
2569                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2570                                 bnx2x_calc_vn_max(bp, vn, &input);
2571
2572                 /* always enable rate shaping and fairness */
2573                 input.flags.cmng_enables |=
2574                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2575
2576                 bnx2x_init_cmng(&input, &bp->cmng);
2577                 return;
2578         }
2579
2580         /* rate shaping and fairness are disabled */
2581         DP(NETIF_MSG_IFUP,
2582            "rate shaping and fairness are disabled\n");
2583 }
2584
2585 static void storm_memset_cmng(struct bnx2x *bp,
2586                               struct cmng_init *cmng,
2587                               u8 port)
2588 {
2589         int vn;
2590         size_t size = sizeof(struct cmng_struct_per_port);
2591
2592         u32 addr = BAR_XSTRORM_INTMEM +
2593                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2594
2595         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2596
2597         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2598                 int func = func_by_vn(bp, vn);
2599
2600                 addr = BAR_XSTRORM_INTMEM +
2601                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2602                 size = sizeof(struct rate_shaping_vars_per_vn);
2603                 __storm_memset_struct(bp, addr, size,
2604                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2605
2606                 addr = BAR_XSTRORM_INTMEM +
2607                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2608                 size = sizeof(struct fairness_vars_per_vn);
2609                 __storm_memset_struct(bp, addr, size,
2610                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2611         }
2612 }
2613
2614 /* init cmng mode in HW according to local configuration */
2615 void bnx2x_set_local_cmng(struct bnx2x *bp)
2616 {
2617         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2618
2619         if (cmng_fns != CMNG_FNS_NONE) {
2620                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2621                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2622         } else {
2623                 /* rate shaping and fairness are disabled */
2624                 DP(NETIF_MSG_IFUP,
2625                    "single function mode without fairness\n");
2626         }
2627 }
2628
2629 /* This function is called upon link interrupt */
2630 static void bnx2x_link_attn(struct bnx2x *bp)
2631 {
2632         /* Make sure that we are synced with the current statistics */
2633         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2634
2635         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2636
2637         bnx2x_init_dropless_fc(bp);
2638
2639         if (bp->link_vars.link_up) {
2640
2641                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2642                         struct host_port_stats *pstats;
2643
2644                         pstats = bnx2x_sp(bp, port_stats);
2645                         /* reset old mac stats */
2646                         memset(&(pstats->mac_stx[0]), 0,
2647                                sizeof(struct mac_stx));
2648                 }
2649                 if (bp->state == BNX2X_STATE_OPEN)
2650                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2651         }
2652
2653         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2654                 bnx2x_set_local_cmng(bp);
2655
2656         __bnx2x_link_report(bp);
2657
2658         if (IS_MF(bp))
2659                 bnx2x_link_sync_notify(bp);
2660 }
2661
2662 void bnx2x__link_status_update(struct bnx2x *bp)
2663 {
2664         if (bp->state != BNX2X_STATE_OPEN)
2665                 return;
2666
2667         /* read updated dcb configuration */
2668         if (IS_PF(bp)) {
2669                 bnx2x_dcbx_pmf_update(bp);
2670                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2671                 if (bp->link_vars.link_up)
2672                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2673                 else
2674                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2675                         /* indicate link status */
2676                 bnx2x_link_report(bp);
2677
2678         } else { /* VF */
2679                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2680                                           SUPPORTED_10baseT_Full |
2681                                           SUPPORTED_100baseT_Half |
2682                                           SUPPORTED_100baseT_Full |
2683                                           SUPPORTED_1000baseT_Full |
2684                                           SUPPORTED_2500baseX_Full |
2685                                           SUPPORTED_10000baseT_Full |
2686                                           SUPPORTED_TP |
2687                                           SUPPORTED_FIBRE |
2688                                           SUPPORTED_Autoneg |
2689                                           SUPPORTED_Pause |
2690                                           SUPPORTED_Asym_Pause);
2691                 bp->port.advertising[0] = bp->port.supported[0];
2692
2693                 bp->link_params.bp = bp;
2694                 bp->link_params.port = BP_PORT(bp);
2695                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2696                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2697                 bp->link_params.req_line_speed[0] = SPEED_10000;
2698                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2699                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2700                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2701                 bp->link_vars.line_speed = SPEED_10000;
2702                 bp->link_vars.link_status =
2703                         (LINK_STATUS_LINK_UP |
2704                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2705                 bp->link_vars.link_up = 1;
2706                 bp->link_vars.duplex = DUPLEX_FULL;
2707                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2708                 __bnx2x_link_report(bp);
2709
2710                 bnx2x_sample_bulletin(bp);
2711
2712                 /* if bulletin board did not have an update for link status
2713                  * __bnx2x_link_report will report current status
2714                  * but it will NOT duplicate report in case of already reported
2715                  * during sampling bulletin board.
2716                  */
2717                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2718         }
2719 }
2720
2721 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2722                                   u16 vlan_val, u8 allowed_prio)
2723 {
2724         struct bnx2x_func_state_params func_params = {NULL};
2725         struct bnx2x_func_afex_update_params *f_update_params =
2726                 &func_params.params.afex_update;
2727
2728         func_params.f_obj = &bp->func_obj;
2729         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2730
2731         /* no need to wait for RAMROD completion, so don't
2732          * set RAMROD_COMP_WAIT flag
2733          */
2734
2735         f_update_params->vif_id = vifid;
2736         f_update_params->afex_default_vlan = vlan_val;
2737         f_update_params->allowed_priorities = allowed_prio;
2738
2739         /* if ramrod can not be sent, response to MCP immediately */
2740         if (bnx2x_func_state_change(bp, &func_params) < 0)
2741                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2742
2743         return 0;
2744 }
2745
2746 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2747                                           u16 vif_index, u8 func_bit_map)
2748 {
2749         struct bnx2x_func_state_params func_params = {NULL};
2750         struct bnx2x_func_afex_viflists_params *update_params =
2751                 &func_params.params.afex_viflists;
2752         int rc;
2753         u32 drv_msg_code;
2754
2755         /* validate only LIST_SET and LIST_GET are received from switch */
2756         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2757                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2758                           cmd_type);
2759
2760         func_params.f_obj = &bp->func_obj;
2761         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2762
2763         /* set parameters according to cmd_type */
2764         update_params->afex_vif_list_command = cmd_type;
2765         update_params->vif_list_index = vif_index;
2766         update_params->func_bit_map =
2767                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2768         update_params->func_to_clear = 0;
2769         drv_msg_code =
2770                 (cmd_type == VIF_LIST_RULE_GET) ?
2771                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2772                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2773
2774         /* if ramrod can not be sent, respond to MCP immediately for
2775          * SET and GET requests (other are not triggered from MCP)
2776          */
2777         rc = bnx2x_func_state_change(bp, &func_params);
2778         if (rc < 0)
2779                 bnx2x_fw_command(bp, drv_msg_code, 0);
2780
2781         return 0;
2782 }
2783
2784 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2785 {
2786         struct afex_stats afex_stats;
2787         u32 func = BP_ABS_FUNC(bp);
2788         u32 mf_config;
2789         u16 vlan_val;
2790         u32 vlan_prio;
2791         u16 vif_id;
2792         u8 allowed_prio;
2793         u8 vlan_mode;
2794         u32 addr_to_write, vifid, addrs, stats_type, i;
2795
2796         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2797                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2798                 DP(BNX2X_MSG_MCP,
2799                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2800                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2801         }
2802
2803         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2804                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2805                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2806                 DP(BNX2X_MSG_MCP,
2807                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2808                    vifid, addrs);
2809                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2810                                                addrs);
2811         }
2812
2813         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2814                 addr_to_write = SHMEM2_RD(bp,
2815                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2816                 stats_type = SHMEM2_RD(bp,
2817                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2818
2819                 DP(BNX2X_MSG_MCP,
2820                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2821                    addr_to_write);
2822
2823                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2824
2825                 /* write response to scratchpad, for MCP */
2826                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2827                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2828                                *(((u32 *)(&afex_stats))+i));
2829
2830                 /* send ack message to MCP */
2831                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2832         }
2833
2834         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2835                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2836                 bp->mf_config[BP_VN(bp)] = mf_config;
2837                 DP(BNX2X_MSG_MCP,
2838                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2839                    mf_config);
2840
2841                 /* if VIF_SET is "enabled" */
2842                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2843                         /* set rate limit directly to internal RAM */
2844                         struct cmng_init_input cmng_input;
2845                         struct rate_shaping_vars_per_vn m_rs_vn;
2846                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2847                         u32 addr = BAR_XSTRORM_INTMEM +
2848                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2849
2850                         bp->mf_config[BP_VN(bp)] = mf_config;
2851
2852                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2853                         m_rs_vn.vn_counter.rate =
2854                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2855                         m_rs_vn.vn_counter.quota =
2856                                 (m_rs_vn.vn_counter.rate *
2857                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2858
2859                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2860
2861                         /* read relevant values from mf_cfg struct in shmem */
2862                         vif_id =
2863                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2864                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2865                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2866                         vlan_val =
2867                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2868                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2869                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2870                         vlan_prio = (mf_config &
2871                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2872                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2873                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2874                         vlan_mode =
2875                                 (MF_CFG_RD(bp,
2876                                            func_mf_config[func].afex_config) &
2877                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2878                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2879                         allowed_prio =
2880                                 (MF_CFG_RD(bp,
2881                                            func_mf_config[func].afex_config) &
2882                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2883                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2884
2885                         /* send ramrod to FW, return in case of failure */
2886                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2887                                                    allowed_prio))
2888                                 return;
2889
2890                         bp->afex_def_vlan_tag = vlan_val;
2891                         bp->afex_vlan_mode = vlan_mode;
2892                 } else {
2893                         /* notify link down because BP->flags is disabled */
2894                         bnx2x_link_report(bp);
2895
2896                         /* send INVALID VIF ramrod to FW */
2897                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2898
2899                         /* Reset the default afex VLAN */
2900                         bp->afex_def_vlan_tag = -1;
2901                 }
2902         }
2903 }
2904
2905 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2906 {
2907         struct bnx2x_func_switch_update_params *switch_update_params;
2908         struct bnx2x_func_state_params func_params;
2909
2910         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2911         switch_update_params = &func_params.params.switch_update;
2912         func_params.f_obj = &bp->func_obj;
2913         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2914
2915         if (IS_MF_UFP(bp)) {
2916                 int func = BP_ABS_FUNC(bp);
2917                 u32 val;
2918
2919                 /* Re-learn the S-tag from shmem */
2920                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2921                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2922                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2923                         bp->mf_ov = val;
2924                 } else {
2925                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2926                         goto fail;
2927                 }
2928
2929                 /* Configure new S-tag in LLH */
2930                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2931                        bp->mf_ov);
2932
2933                 /* Send Ramrod to update FW of change */
2934                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2935                           &switch_update_params->changes);
2936                 switch_update_params->vlan = bp->mf_ov;
2937
2938                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2939                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2940                                   bp->mf_ov);
2941                         goto fail;
2942                 }
2943
2944                 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov);
2945
2946                 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2947
2948                 return;
2949         }
2950
2951         /* not supported by SW yet */
2952 fail:
2953         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2954 }
2955
2956 static void bnx2x_pmf_update(struct bnx2x *bp)
2957 {
2958         int port = BP_PORT(bp);
2959         u32 val;
2960
2961         bp->port.pmf = 1;
2962         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2963
2964         /*
2965          * We need the mb() to ensure the ordering between the writing to
2966          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2967          */
2968         smp_mb();
2969
2970         /* queue a periodic task */
2971         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2972
2973         bnx2x_dcbx_pmf_update(bp);
2974
2975         /* enable nig attention */
2976         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2977         if (bp->common.int_block == INT_BLOCK_HC) {
2978                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2979                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2980         } else if (!CHIP_IS_E1x(bp)) {
2981                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2982                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2983         }
2984
2985         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2986 }
2987
2988 /* end of Link */
2989
2990 /* slow path */
2991
2992 /*
2993  * General service functions
2994  */
2995
2996 /* send the MCP a request, block until there is a reply */
2997 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2998 {
2999         int mb_idx = BP_FW_MB_IDX(bp);
3000         u32 seq;
3001         u32 rc = 0;
3002         u32 cnt = 1;
3003         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3004
3005         mutex_lock(&bp->fw_mb_mutex);
3006         seq = ++bp->fw_seq;
3007         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3008         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3009
3010         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3011                         (command | seq), param);
3012
3013         do {
3014                 /* let the FW do it's magic ... */
3015                 msleep(delay);
3016
3017                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3018
3019                 /* Give the FW up to 5 second (500*10ms) */
3020         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3021
3022         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3023            cnt*delay, rc, seq);
3024
3025         /* is this a reply to our command? */
3026         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3027                 rc &= FW_MSG_CODE_MASK;
3028         else {
3029                 /* FW BUG! */
3030                 BNX2X_ERR("FW failed to respond!\n");
3031                 bnx2x_fw_dump(bp);
3032                 rc = 0;
3033         }
3034         mutex_unlock(&bp->fw_mb_mutex);
3035
3036         return rc;
3037 }
3038
3039 static void storm_memset_func_cfg(struct bnx2x *bp,
3040                                  struct tstorm_eth_function_common_config *tcfg,
3041                                  u16 abs_fid)
3042 {
3043         size_t size = sizeof(struct tstorm_eth_function_common_config);
3044
3045         u32 addr = BAR_TSTRORM_INTMEM +
3046                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3047
3048         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3049 }
3050
3051 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3052 {
3053         if (CHIP_IS_E1x(bp)) {
3054                 struct tstorm_eth_function_common_config tcfg = {0};
3055
3056                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3057         }
3058
3059         /* Enable the function in the FW */
3060         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3061         storm_memset_func_en(bp, p->func_id, 1);
3062
3063         /* spq */
3064         if (p->func_flgs & FUNC_FLG_SPQ) {
3065                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3066                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3067                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3068         }
3069 }
3070
3071 /**
3072  * bnx2x_get_common_flags - Return common flags
3073  *
3074  * @bp          device handle
3075  * @fp          queue handle
3076  * @zero_stats  TRUE if statistics zeroing is needed
3077  *
3078  * Return the flags that are common for the Tx-only and not normal connections.
3079  */
3080 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3081                                             struct bnx2x_fastpath *fp,
3082                                             bool zero_stats)
3083 {
3084         unsigned long flags = 0;
3085
3086         /* PF driver will always initialize the Queue to an ACTIVE state */
3087         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3088
3089         /* tx only connections collect statistics (on the same index as the
3090          * parent connection). The statistics are zeroed when the parent
3091          * connection is initialized.
3092          */
3093
3094         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3095         if (zero_stats)
3096                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3097
3098         if (bp->flags & TX_SWITCHING)
3099                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3100
3101         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3102         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3103
3104 #ifdef BNX2X_STOP_ON_ERROR
3105         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3106 #endif
3107
3108         return flags;
3109 }
3110
3111 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3112                                        struct bnx2x_fastpath *fp,
3113                                        bool leading)
3114 {
3115         unsigned long flags = 0;
3116
3117         /* calculate other queue flags */
3118         if (IS_MF_SD(bp))
3119                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3120
3121         if (IS_FCOE_FP(fp)) {
3122                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3123                 /* For FCoE - force usage of default priority (for afex) */
3124                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3125         }
3126
3127         if (fp->mode != TPA_MODE_DISABLED) {
3128                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3129                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3130                 if (fp->mode == TPA_MODE_GRO)
3131                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3132         }
3133
3134         if (leading) {
3135                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3136                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3137         }
3138
3139         /* Always set HW VLAN stripping */
3140         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3141
3142         /* configure silent vlan removal */
3143         if (IS_MF_AFEX(bp))
3144                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3145
3146         return flags | bnx2x_get_common_flags(bp, fp, true);
3147 }
3148
3149 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3150         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3151         u8 cos)
3152 {
3153         gen_init->stat_id = bnx2x_stats_id(fp);
3154         gen_init->spcl_id = fp->cl_id;
3155
3156         /* Always use mini-jumbo MTU for FCoE L2 ring */
3157         if (IS_FCOE_FP(fp))
3158                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3159         else
3160                 gen_init->mtu = bp->dev->mtu;
3161
3162         gen_init->cos = cos;
3163
3164         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3165 }
3166
3167 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3168         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3169         struct bnx2x_rxq_setup_params *rxq_init)
3170 {
3171         u8 max_sge = 0;
3172         u16 sge_sz = 0;
3173         u16 tpa_agg_size = 0;
3174
3175         if (fp->mode != TPA_MODE_DISABLED) {
3176                 pause->sge_th_lo = SGE_TH_LO(bp);
3177                 pause->sge_th_hi = SGE_TH_HI(bp);
3178
3179                 /* validate SGE ring has enough to cross high threshold */
3180                 WARN_ON(bp->dropless_fc &&
3181                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3182                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3183
3184                 tpa_agg_size = TPA_AGG_SIZE;
3185                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3186                         SGE_PAGE_SHIFT;
3187                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3188                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3189                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3190         }
3191
3192         /* pause - not for e1 */
3193         if (!CHIP_IS_E1(bp)) {
3194                 pause->bd_th_lo = BD_TH_LO(bp);
3195                 pause->bd_th_hi = BD_TH_HI(bp);
3196
3197                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3198                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3199                 /*
3200                  * validate that rings have enough entries to cross
3201                  * high thresholds
3202                  */
3203                 WARN_ON(bp->dropless_fc &&
3204                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3205                                 bp->rx_ring_size);
3206                 WARN_ON(bp->dropless_fc &&
3207                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3208                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3209
3210                 pause->pri_map = 1;
3211         }
3212
3213         /* rxq setup */
3214         rxq_init->dscr_map = fp->rx_desc_mapping;
3215         rxq_init->sge_map = fp->rx_sge_mapping;
3216         rxq_init->rcq_map = fp->rx_comp_mapping;
3217         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3218
3219         /* This should be a maximum number of data bytes that may be
3220          * placed on the BD (not including paddings).
3221          */
3222         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3223                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3224
3225         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3226         rxq_init->tpa_agg_sz = tpa_agg_size;
3227         rxq_init->sge_buf_sz = sge_sz;
3228         rxq_init->max_sges_pkt = max_sge;
3229         rxq_init->rss_engine_id = BP_FUNC(bp);
3230         rxq_init->mcast_engine_id = BP_FUNC(bp);
3231
3232         /* Maximum number or simultaneous TPA aggregation for this Queue.
3233          *
3234          * For PF Clients it should be the maximum available number.
3235          * VF driver(s) may want to define it to a smaller value.
3236          */
3237         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3238
3239         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3240         rxq_init->fw_sb_id = fp->fw_sb_id;
3241
3242         if (IS_FCOE_FP(fp))
3243                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3244         else
3245                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3246         /* configure silent vlan removal
3247          * if multi function mode is afex, then mask default vlan
3248          */
3249         if (IS_MF_AFEX(bp)) {
3250                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3251                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3252         }
3253 }
3254
3255 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3256         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3257         u8 cos)
3258 {
3259         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3260         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3261         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3262         txq_init->fw_sb_id = fp->fw_sb_id;
3263
3264         /*
3265          * set the tss leading client id for TX classification ==
3266          * leading RSS client id
3267          */
3268         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3269
3270         if (IS_FCOE_FP(fp)) {
3271                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3272                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3273         }
3274 }
3275
3276 static void bnx2x_pf_init(struct bnx2x *bp)
3277 {
3278         struct bnx2x_func_init_params func_init = {0};
3279         struct event_ring_data eq_data = { {0} };
3280         u16 flags;
3281
3282         if (!CHIP_IS_E1x(bp)) {
3283                 /* reset IGU PF statistics: MSIX + ATTN */
3284                 /* PF */
3285                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3286                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3287                            (CHIP_MODE_IS_4_PORT(bp) ?
3288                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3289                 /* ATTN */
3290                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3291                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3292                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3293                            (CHIP_MODE_IS_4_PORT(bp) ?
3294                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3295         }
3296
3297         /* function setup flags */
3298         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3299
3300         /* This flag is relevant for E1x only.
3301          * E2 doesn't have a TPA configuration in a function level.
3302          */
3303         flags |= (bp->dev->features & NETIF_F_LRO) ? FUNC_FLG_TPA : 0;
3304
3305         func_init.func_flgs = flags;
3306         func_init.pf_id = BP_FUNC(bp);
3307         func_init.func_id = BP_FUNC(bp);
3308         func_init.spq_map = bp->spq_mapping;
3309         func_init.spq_prod = bp->spq_prod_idx;
3310
3311         bnx2x_func_init(bp, &func_init);
3312
3313         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3314
3315         /*
3316          * Congestion management values depend on the link rate
3317          * There is no active link so initial link rate is set to 10 Gbps.
3318          * When the link comes up The congestion management values are
3319          * re-calculated according to the actual link rate.
3320          */
3321         bp->link_vars.line_speed = SPEED_10000;
3322         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3323
3324         /* Only the PMF sets the HW */
3325         if (bp->port.pmf)
3326                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3327
3328         /* init Event Queue - PCI bus guarantees correct endianity*/
3329         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3330         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3331         eq_data.producer = bp->eq_prod;
3332         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3333         eq_data.sb_id = DEF_SB_ID;
3334         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3335 }
3336
3337 static void bnx2x_e1h_disable(struct bnx2x *bp)
3338 {
3339         int port = BP_PORT(bp);
3340
3341         bnx2x_tx_disable(bp);
3342
3343         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3344 }
3345
3346 static void bnx2x_e1h_enable(struct bnx2x *bp)
3347 {
3348         int port = BP_PORT(bp);
3349
3350         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3351                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3352
3353         /* Tx queue should be only re-enabled */
3354         netif_tx_wake_all_queues(bp->dev);
3355
3356         /*
3357          * Should not call netif_carrier_on since it will be called if the link
3358          * is up when checking for link state
3359          */
3360 }
3361
3362 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3363
3364 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3365 {
3366         struct eth_stats_info *ether_stat =
3367                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3368         struct bnx2x_vlan_mac_obj *mac_obj =
3369                 &bp->sp_objs->mac_obj;
3370         int i;
3371
3372         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3373                 ETH_STAT_INFO_VERSION_LEN);
3374
3375         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3376          * mac_local field in ether_stat struct. The base address is offset by 2
3377          * bytes to account for the field being 8 bytes but a mac address is
3378          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3379          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3380          * allocated by the ether_stat struct, so the macs will land in their
3381          * proper positions.
3382          */
3383         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3384                 memset(ether_stat->mac_local + i, 0,
3385                        sizeof(ether_stat->mac_local[0]));
3386         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3387                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3388                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3389                                 ETH_ALEN);
3390         ether_stat->mtu_size = bp->dev->mtu;
3391         if (bp->dev->features & NETIF_F_RXCSUM)
3392                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3393         if (bp->dev->features & NETIF_F_TSO)
3394                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3395         ether_stat->feature_flags |= bp->common.boot_mode;
3396
3397         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3398
3399         ether_stat->txq_size = bp->tx_ring_size;
3400         ether_stat->rxq_size = bp->rx_ring_size;
3401
3402 #ifdef CONFIG_BNX2X_SRIOV
3403         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3404 #endif
3405 }
3406
3407 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3408 {
3409         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3410         struct fcoe_stats_info *fcoe_stat =
3411                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3412
3413         if (!CNIC_LOADED(bp))
3414                 return;
3415
3416         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3417
3418         fcoe_stat->qos_priority =
3419                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3420
3421         /* insert FCoE stats from ramrod response */
3422         if (!NO_FCOE(bp)) {
3423                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3424                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3425                         tstorm_queue_statistics;
3426
3427                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3428                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3429                         xstorm_queue_statistics;
3430
3431                 struct fcoe_statistics_params *fw_fcoe_stat =
3432                         &bp->fw_stats_data->fcoe;
3433
3434                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3435                           fcoe_stat->rx_bytes_lo,
3436                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3437
3438                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3439                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3440                           fcoe_stat->rx_bytes_lo,
3441                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3442
3443                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3444                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3445                           fcoe_stat->rx_bytes_lo,
3446                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3447
3448                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3449                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3450                           fcoe_stat->rx_bytes_lo,
3451                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3452
3453                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3454                           fcoe_stat->rx_frames_lo,
3455                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3456
3457                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458                           fcoe_stat->rx_frames_lo,
3459                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3460
3461                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462                           fcoe_stat->rx_frames_lo,
3463                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3464
3465                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466                           fcoe_stat->rx_frames_lo,
3467                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3468
3469                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3470                           fcoe_stat->tx_bytes_lo,
3471                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3472
3473                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3474                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3475                           fcoe_stat->tx_bytes_lo,
3476                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3477
3478                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3479                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3480                           fcoe_stat->tx_bytes_lo,
3481                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3482
3483                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3484                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3485                           fcoe_stat->tx_bytes_lo,
3486                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3487
3488                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3489                           fcoe_stat->tx_frames_lo,
3490                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3491
3492                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493                           fcoe_stat->tx_frames_lo,
3494                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3495
3496                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497                           fcoe_stat->tx_frames_lo,
3498                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3499
3500                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501                           fcoe_stat->tx_frames_lo,
3502                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3503         }
3504
3505         /* ask L5 driver to add data to the struct */
3506         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3507 }
3508
3509 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3510 {
3511         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3512         struct iscsi_stats_info *iscsi_stat =
3513                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3514
3515         if (!CNIC_LOADED(bp))
3516                 return;
3517
3518         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3519                ETH_ALEN);
3520
3521         iscsi_stat->qos_priority =
3522                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3523
3524         /* ask L5 driver to add data to the struct */
3525         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3526 }
3527
3528 /* called due to MCP event (on pmf):
3529  *      reread new bandwidth configuration
3530  *      configure FW
3531  *      notify others function about the change
3532  */
3533 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3534 {
3535         if (bp->link_vars.link_up) {
3536                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3537                 bnx2x_link_sync_notify(bp);
3538         }
3539         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3540 }
3541
3542 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3543 {
3544         bnx2x_config_mf_bw(bp);
3545         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3546 }
3547
3548 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3549 {
3550         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3551         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3552 }
3553
3554 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3555 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3556
3557 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3558 {
3559         enum drv_info_opcode op_code;
3560         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3561         bool release = false;
3562         int wait;
3563
3564         /* if drv_info version supported by MFW doesn't match - send NACK */
3565         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3566                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3567                 return;
3568         }
3569
3570         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3571                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3572
3573         /* Must prevent other flows from accessing drv_info_to_mcp */
3574         mutex_lock(&bp->drv_info_mutex);
3575
3576         memset(&bp->slowpath->drv_info_to_mcp, 0,
3577                sizeof(union drv_info_to_mcp));
3578
3579         switch (op_code) {
3580         case ETH_STATS_OPCODE:
3581                 bnx2x_drv_info_ether_stat(bp);
3582                 break;
3583         case FCOE_STATS_OPCODE:
3584                 bnx2x_drv_info_fcoe_stat(bp);
3585                 break;
3586         case ISCSI_STATS_OPCODE:
3587                 bnx2x_drv_info_iscsi_stat(bp);
3588                 break;
3589         default:
3590                 /* if op code isn't supported - send NACK */
3591                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3592                 goto out;
3593         }
3594
3595         /* if we got drv_info attn from MFW then these fields are defined in
3596          * shmem2 for sure
3597          */
3598         SHMEM2_WR(bp, drv_info_host_addr_lo,
3599                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3600         SHMEM2_WR(bp, drv_info_host_addr_hi,
3601                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3602
3603         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3604
3605         /* Since possible management wants both this and get_driver_version
3606          * need to wait until management notifies us it finished utilizing
3607          * the buffer.
3608          */
3609         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3610                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3611         } else if (!bp->drv_info_mng_owner) {
3612                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3613
3614                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3615                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3616
3617                         /* Management is done; need to clear indication */
3618                         if (indication & bit) {
3619                                 SHMEM2_WR(bp, mfw_drv_indication,
3620                                           indication & ~bit);
3621                                 release = true;
3622                                 break;
3623                         }
3624
3625                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3626                 }
3627         }
3628         if (!release) {
3629                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3630                 bp->drv_info_mng_owner = true;
3631         }
3632
3633 out:
3634         mutex_unlock(&bp->drv_info_mutex);
3635 }
3636
3637 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3638 {
3639         u8 vals[4];
3640         int i = 0;
3641
3642         if (bnx2x_format) {
3643                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3644                            &vals[0], &vals[1], &vals[2], &vals[3]);
3645                 if (i > 0)
3646                         vals[0] -= '0';
3647         } else {
3648                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3649                            &vals[0], &vals[1], &vals[2], &vals[3]);
3650         }
3651
3652         while (i < 4)
3653                 vals[i++] = 0;
3654
3655         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3656 }
3657
3658 void bnx2x_update_mng_version(struct bnx2x *bp)
3659 {
3660         u32 iscsiver = DRV_VER_NOT_LOADED;
3661         u32 fcoever = DRV_VER_NOT_LOADED;
3662         u32 ethver = DRV_VER_NOT_LOADED;
3663         int idx = BP_FW_MB_IDX(bp);
3664         u8 *version;
3665
3666         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3667                 return;
3668
3669         mutex_lock(&bp->drv_info_mutex);
3670         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3671         if (bp->drv_info_mng_owner)
3672                 goto out;
3673
3674         if (bp->state != BNX2X_STATE_OPEN)
3675                 goto out;
3676
3677         /* Parse ethernet driver version */
3678         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3679         if (!CNIC_LOADED(bp))
3680                 goto out;
3681
3682         /* Try getting storage driver version via cnic */
3683         memset(&bp->slowpath->drv_info_to_mcp, 0,
3684                sizeof(union drv_info_to_mcp));
3685         bnx2x_drv_info_iscsi_stat(bp);
3686         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3687         iscsiver = bnx2x_update_mng_version_utility(version, false);
3688
3689         memset(&bp->slowpath->drv_info_to_mcp, 0,
3690                sizeof(union drv_info_to_mcp));
3691         bnx2x_drv_info_fcoe_stat(bp);
3692         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3693         fcoever = bnx2x_update_mng_version_utility(version, false);
3694
3695 out:
3696         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3697         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3698         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3699
3700         mutex_unlock(&bp->drv_info_mutex);
3701
3702         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3703            ethver, iscsiver, fcoever);
3704 }
3705
3706 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3707 {
3708         u32 cmd_ok, cmd_fail;
3709
3710         /* sanity */
3711         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3712             event & DRV_STATUS_OEM_EVENT_MASK) {
3713                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3714                 return;
3715         }
3716
3717         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3718                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3719                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3720         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3721                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3722                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3723         }
3724
3725         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3726
3727         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3728                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3729                 /* This is the only place besides the function initialization
3730                  * where the bp->flags can change so it is done without any
3731                  * locks
3732                  */
3733                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3734                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3735                         bp->flags |= MF_FUNC_DIS;
3736
3737                         bnx2x_e1h_disable(bp);
3738                 } else {
3739                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3740                         bp->flags &= ~MF_FUNC_DIS;
3741
3742                         bnx2x_e1h_enable(bp);
3743                 }
3744                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3745                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3746         }
3747
3748         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3749                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3750                 bnx2x_config_mf_bw(bp);
3751                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3752                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3753         }
3754
3755         /* Report results to MCP */
3756         if (event)
3757                 bnx2x_fw_command(bp, cmd_fail, 0);
3758         else
3759                 bnx2x_fw_command(bp, cmd_ok, 0);
3760 }
3761
3762 /* must be called under the spq lock */
3763 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3764 {
3765         struct eth_spe *next_spe = bp->spq_prod_bd;
3766
3767         if (bp->spq_prod_bd == bp->spq_last_bd) {
3768                 bp->spq_prod_bd = bp->spq;
3769                 bp->spq_prod_idx = 0;
3770                 DP(BNX2X_MSG_SP, "end of spq\n");
3771         } else {
3772                 bp->spq_prod_bd++;
3773                 bp->spq_prod_idx++;
3774         }
3775         return next_spe;
3776 }
3777
3778 /* must be called under the spq lock */
3779 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3780 {
3781         int func = BP_FUNC(bp);
3782
3783         /*
3784          * Make sure that BD data is updated before writing the producer:
3785          * BD data is written to the memory, the producer is read from the
3786          * memory, thus we need a full memory barrier to ensure the ordering.
3787          */
3788         mb();
3789
3790         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3791                  bp->spq_prod_idx);
3792         mmiowb();
3793 }
3794
3795 /**
3796  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3797  *
3798  * @cmd:        command to check
3799  * @cmd_type:   command type
3800  */
3801 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3802 {
3803         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3804             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3805             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3806             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3807             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3808             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3809             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3810                 return true;
3811         else
3812                 return false;
3813 }
3814
3815 /**
3816  * bnx2x_sp_post - place a single command on an SP ring
3817  *
3818  * @bp:         driver handle
3819  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3820  * @cid:        SW CID the command is related to
3821  * @data_hi:    command private data address (high 32 bits)
3822  * @data_lo:    command private data address (low 32 bits)
3823  * @cmd_type:   command type (e.g. NONE, ETH)
3824  *
3825  * SP data is handled as if it's always an address pair, thus data fields are
3826  * not swapped to little endian in upper functions. Instead this function swaps
3827  * data as if it's two u32 fields.
3828  */
3829 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3830                   u32 data_hi, u32 data_lo, int cmd_type)
3831 {
3832         struct eth_spe *spe;
3833         u16 type;
3834         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3835
3836 #ifdef BNX2X_STOP_ON_ERROR
3837         if (unlikely(bp->panic)) {
3838                 BNX2X_ERR("Can't post SP when there is panic\n");
3839                 return -EIO;
3840         }
3841 #endif
3842
3843         spin_lock_bh(&bp->spq_lock);
3844
3845         if (common) {
3846                 if (!atomic_read(&bp->eq_spq_left)) {
3847                         BNX2X_ERR("BUG! EQ ring full!\n");
3848                         spin_unlock_bh(&bp->spq_lock);
3849                         bnx2x_panic();
3850                         return -EBUSY;
3851                 }
3852         } else if (!atomic_read(&bp->cq_spq_left)) {
3853                         BNX2X_ERR("BUG! SPQ ring full!\n");
3854                         spin_unlock_bh(&bp->spq_lock);
3855                         bnx2x_panic();
3856                         return -EBUSY;
3857         }
3858
3859         spe = bnx2x_sp_get_next(bp);
3860
3861         /* CID needs port number to be encoded int it */
3862         spe->hdr.conn_and_cmd_data =
3863                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3864                                     HW_CID(bp, cid));
3865
3866         /* In some cases, type may already contain the func-id
3867          * mainly in SRIOV related use cases, so we add it here only
3868          * if it's not already set.
3869          */
3870         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3871                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3872                         SPE_HDR_CONN_TYPE;
3873                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3874                          SPE_HDR_FUNCTION_ID);
3875         } else {
3876                 type = cmd_type;
3877         }
3878
3879         spe->hdr.type = cpu_to_le16(type);
3880
3881         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3882         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3883
3884         /*
3885          * It's ok if the actual decrement is issued towards the memory
3886          * somewhere between the spin_lock and spin_unlock. Thus no
3887          * more explicit memory barrier is needed.
3888          */
3889         if (common)
3890                 atomic_dec(&bp->eq_spq_left);
3891         else
3892                 atomic_dec(&bp->cq_spq_left);
3893
3894         DP(BNX2X_MSG_SP,
3895            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3896            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3897            (u32)(U64_LO(bp->spq_mapping) +
3898            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3899            HW_CID(bp, cid), data_hi, data_lo, type,
3900            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3901
3902         bnx2x_sp_prod_update(bp);
3903         spin_unlock_bh(&bp->spq_lock);
3904         return 0;
3905 }
3906
3907 /* acquire split MCP access lock register */
3908 static int bnx2x_acquire_alr(struct bnx2x *bp)
3909 {
3910         u32 j, val;
3911         int rc = 0;
3912
3913         might_sleep();
3914         for (j = 0; j < 1000; j++) {
3915                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3916                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3917                 if (val & MCPR_ACCESS_LOCK_LOCK)
3918                         break;
3919
3920                 usleep_range(5000, 10000);
3921         }
3922         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3923                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3924                 rc = -EBUSY;
3925         }
3926
3927         return rc;
3928 }
3929
3930 /* release split MCP access lock register */
3931 static void bnx2x_release_alr(struct bnx2x *bp)
3932 {
3933         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3934 }
3935
3936 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3937 #define BNX2X_DEF_SB_IDX        0x0002
3938
3939 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3940 {
3941         struct host_sp_status_block *def_sb = bp->def_status_blk;
3942         u16 rc = 0;
3943
3944         barrier(); /* status block is written to by the chip */
3945         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3946                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3947                 rc |= BNX2X_DEF_SB_ATT_IDX;
3948         }
3949
3950         if (bp->def_idx != def_sb->sp_sb.running_index) {
3951                 bp->def_idx = def_sb->sp_sb.running_index;
3952                 rc |= BNX2X_DEF_SB_IDX;
3953         }
3954
3955         /* Do not reorder: indices reading should complete before handling */
3956         barrier();
3957         return rc;
3958 }
3959
3960 /*
3961  * slow path service functions
3962  */
3963
3964 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3965 {
3966         int port = BP_PORT(bp);
3967         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3968                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3969         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3970                                        NIG_REG_MASK_INTERRUPT_PORT0;
3971         u32 aeu_mask;
3972         u32 nig_mask = 0;
3973         u32 reg_addr;
3974
3975         if (bp->attn_state & asserted)
3976                 BNX2X_ERR("IGU ERROR\n");
3977
3978         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3979         aeu_mask = REG_RD(bp, aeu_addr);
3980
3981         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3982            aeu_mask, asserted);
3983         aeu_mask &= ~(asserted & 0x3ff);
3984         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3985
3986         REG_WR(bp, aeu_addr, aeu_mask);
3987         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3988
3989         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3990         bp->attn_state |= asserted;
3991         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3992
3993         if (asserted & ATTN_HARD_WIRED_MASK) {
3994                 if (asserted & ATTN_NIG_FOR_FUNC) {
3995
3996                         bnx2x_acquire_phy_lock(bp);
3997
3998                         /* save nig interrupt mask */
3999                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4000
4001                         /* If nig_mask is not set, no need to call the update
4002                          * function.
4003                          */
4004                         if (nig_mask) {
4005                                 REG_WR(bp, nig_int_mask_addr, 0);
4006
4007                                 bnx2x_link_attn(bp);
4008                         }
4009
4010                         /* handle unicore attn? */
4011                 }
4012                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4013                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4014
4015                 if (asserted & GPIO_2_FUNC)
4016                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4017
4018                 if (asserted & GPIO_3_FUNC)
4019                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4020
4021                 if (asserted & GPIO_4_FUNC)
4022                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4023
4024                 if (port == 0) {
4025                         if (asserted & ATTN_GENERAL_ATTN_1) {
4026                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4027                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4028                         }
4029                         if (asserted & ATTN_GENERAL_ATTN_2) {
4030                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4031                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4032                         }
4033                         if (asserted & ATTN_GENERAL_ATTN_3) {
4034                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4035                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4036                         }
4037                 } else {
4038                         if (asserted & ATTN_GENERAL_ATTN_4) {
4039                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4040                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4041                         }
4042                         if (asserted & ATTN_GENERAL_ATTN_5) {
4043                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4044                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4045                         }
4046                         if (asserted & ATTN_GENERAL_ATTN_6) {
4047                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4048                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4049                         }
4050                 }
4051
4052         } /* if hardwired */
4053
4054         if (bp->common.int_block == INT_BLOCK_HC)
4055                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4056                             COMMAND_REG_ATTN_BITS_SET);
4057         else
4058                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4059
4060         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4061            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4062         REG_WR(bp, reg_addr, asserted);
4063
4064         /* now set back the mask */
4065         if (asserted & ATTN_NIG_FOR_FUNC) {
4066                 /* Verify that IGU ack through BAR was written before restoring
4067                  * NIG mask. This loop should exit after 2-3 iterations max.
4068                  */
4069                 if (bp->common.int_block != INT_BLOCK_HC) {
4070                         u32 cnt = 0, igu_acked;
4071                         do {
4072                                 igu_acked = REG_RD(bp,
4073                                                    IGU_REG_ATTENTION_ACK_BITS);
4074                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4075                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4076                         if (!igu_acked)
4077                                 DP(NETIF_MSG_HW,
4078                                    "Failed to verify IGU ack on time\n");
4079                         barrier();
4080                 }
4081                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4082                 bnx2x_release_phy_lock(bp);
4083         }
4084 }
4085
4086 static void bnx2x_fan_failure(struct bnx2x *bp)
4087 {
4088         int port = BP_PORT(bp);
4089         u32 ext_phy_config;
4090         /* mark the failure */
4091         ext_phy_config =
4092                 SHMEM_RD(bp,
4093                          dev_info.port_hw_config[port].external_phy_config);
4094
4095         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4096         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4097         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4098                  ext_phy_config);
4099
4100         /* log the failure */
4101         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4102                             "Please contact OEM Support for assistance\n");
4103
4104         /* Schedule device reset (unload)
4105          * This is due to some boards consuming sufficient power when driver is
4106          * up to overheat if fan fails.
4107          */
4108         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4109 }
4110
4111 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4112 {
4113         int port = BP_PORT(bp);
4114         int reg_offset;
4115         u32 val;
4116
4117         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4118                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4119
4120         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4121
4122                 val = REG_RD(bp, reg_offset);
4123                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4124                 REG_WR(bp, reg_offset, val);
4125
4126                 BNX2X_ERR("SPIO5 hw attention\n");
4127
4128                 /* Fan failure attention */
4129                 bnx2x_hw_reset_phy(&bp->link_params);
4130                 bnx2x_fan_failure(bp);
4131         }
4132
4133         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4134                 bnx2x_acquire_phy_lock(bp);
4135                 bnx2x_handle_module_detect_int(&bp->link_params);
4136                 bnx2x_release_phy_lock(bp);
4137         }
4138
4139         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4140
4141                 val = REG_RD(bp, reg_offset);
4142                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4143                 REG_WR(bp, reg_offset, val);
4144
4145                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4146                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4147                 bnx2x_panic();
4148         }
4149 }
4150
4151 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4152 {
4153         u32 val;
4154
4155         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4156
4157                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4158                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4159                 /* DORQ discard attention */
4160                 if (val & 0x2)
4161                         BNX2X_ERR("FATAL error from DORQ\n");
4162         }
4163
4164         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4165
4166                 int port = BP_PORT(bp);
4167                 int reg_offset;
4168
4169                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4170                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4171
4172                 val = REG_RD(bp, reg_offset);
4173                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4174                 REG_WR(bp, reg_offset, val);
4175
4176                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4177                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4178                 bnx2x_panic();
4179         }
4180 }
4181
4182 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4183 {
4184         u32 val;
4185
4186         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4187
4188                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4189                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4190                 /* CFC error attention */
4191                 if (val & 0x2)
4192                         BNX2X_ERR("FATAL error from CFC\n");
4193         }
4194
4195         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4196                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4197                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4198                 /* RQ_USDMDP_FIFO_OVERFLOW */
4199                 if (val & 0x18000)
4200                         BNX2X_ERR("FATAL error from PXP\n");
4201
4202                 if (!CHIP_IS_E1x(bp)) {
4203                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4204                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4205                 }
4206         }
4207
4208         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4209
4210                 int port = BP_PORT(bp);
4211                 int reg_offset;
4212
4213                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4214                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4215
4216                 val = REG_RD(bp, reg_offset);
4217                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4218                 REG_WR(bp, reg_offset, val);
4219
4220                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4221                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4222                 bnx2x_panic();
4223         }
4224 }
4225
4226 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4227 {
4228         u32 val;
4229
4230         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4231
4232                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4233                         int func = BP_FUNC(bp);
4234
4235                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4236                         bnx2x_read_mf_cfg(bp);
4237                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4238                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4239                         val = SHMEM_RD(bp,
4240                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4241
4242                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4243                                    DRV_STATUS_OEM_EVENT_MASK))
4244                                 bnx2x_oem_event(bp,
4245                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4246                                                 DRV_STATUS_OEM_EVENT_MASK)));
4247
4248                         if (val & DRV_STATUS_SET_MF_BW)
4249                                 bnx2x_set_mf_bw(bp);
4250
4251                         if (val & DRV_STATUS_DRV_INFO_REQ)
4252                                 bnx2x_handle_drv_info_req(bp);
4253
4254                         if (val & DRV_STATUS_VF_DISABLED)
4255                                 bnx2x_schedule_iov_task(bp,
4256                                                         BNX2X_IOV_HANDLE_FLR);
4257
4258                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4259                                 bnx2x_pmf_update(bp);
4260
4261                         if (bp->port.pmf &&
4262                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4263                                 bp->dcbx_enabled > 0)
4264                                 /* start dcbx state machine */
4265                                 bnx2x_dcbx_set_params(bp,
4266                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4267                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4268                                 bnx2x_handle_afex_cmd(bp,
4269                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4270                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4271                                 bnx2x_handle_eee_event(bp);
4272
4273                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4274                                 bnx2x_handle_update_svid_cmd(bp);
4275
4276                         if (bp->link_vars.periodic_flags &
4277                             PERIODIC_FLAGS_LINK_EVENT) {
4278                                 /*  sync with link */
4279                                 bnx2x_acquire_phy_lock(bp);
4280                                 bp->link_vars.periodic_flags &=
4281                                         ~PERIODIC_FLAGS_LINK_EVENT;
4282                                 bnx2x_release_phy_lock(bp);
4283                                 if (IS_MF(bp))
4284                                         bnx2x_link_sync_notify(bp);
4285                                 bnx2x_link_report(bp);
4286                         }
4287                         /* Always call it here: bnx2x_link_report() will
4288                          * prevent the link indication duplication.
4289                          */
4290                         bnx2x__link_status_update(bp);
4291                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4292
4293                         BNX2X_ERR("MC assert!\n");
4294                         bnx2x_mc_assert(bp);
4295                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4296                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4297                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4298                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4299                         bnx2x_panic();
4300
4301                 } else if (attn & BNX2X_MCP_ASSERT) {
4302
4303                         BNX2X_ERR("MCP assert!\n");
4304                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4305                         bnx2x_fw_dump(bp);
4306
4307                 } else
4308                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4309         }
4310
4311         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4312                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4313                 if (attn & BNX2X_GRC_TIMEOUT) {
4314                         val = CHIP_IS_E1(bp) ? 0 :
4315                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4316                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4317                 }
4318                 if (attn & BNX2X_GRC_RSV) {
4319                         val = CHIP_IS_E1(bp) ? 0 :
4320                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4321                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4322                 }
4323                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4324         }
4325 }
4326
4327 /*
4328  * Bits map:
4329  * 0-7   - Engine0 load counter.
4330  * 8-15  - Engine1 load counter.
4331  * 16    - Engine0 RESET_IN_PROGRESS bit.
4332  * 17    - Engine1 RESET_IN_PROGRESS bit.
4333  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4334  *         on the engine
4335  * 19    - Engine1 ONE_IS_LOADED.
4336  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4337  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4338  *         just the one belonging to its engine).
4339  *
4340  */
4341 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4342
4343 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4344 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4345 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4346 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4347 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4348 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4349 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4350
4351 /*
4352  * Set the GLOBAL_RESET bit.
4353  *
4354  * Should be run under rtnl lock
4355  */
4356 void bnx2x_set_reset_global(struct bnx2x *bp)
4357 {
4358         u32 val;
4359         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4360         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4361         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4362         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4363 }
4364
4365 /*
4366  * Clear the GLOBAL_RESET bit.
4367  *
4368  * Should be run under rtnl lock
4369  */
4370 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4371 {
4372         u32 val;
4373         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4374         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4375         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4376         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4377 }
4378
4379 /*
4380  * Checks the GLOBAL_RESET bit.
4381  *
4382  * should be run under rtnl lock
4383  */
4384 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4385 {
4386         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4387
4388         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4389         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4390 }
4391
4392 /*
4393  * Clear RESET_IN_PROGRESS bit for the current engine.
4394  *
4395  * Should be run under rtnl lock
4396  */
4397 static void bnx2x_set_reset_done(struct bnx2x *bp)
4398 {
4399         u32 val;
4400         u32 bit = BP_PATH(bp) ?
4401                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4402         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4403         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4404
4405         /* Clear the bit */
4406         val &= ~bit;
4407         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4408
4409         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4410 }
4411
4412 /*
4413  * Set RESET_IN_PROGRESS for the current engine.
4414  *
4415  * should be run under rtnl lock
4416  */
4417 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4418 {
4419         u32 val;
4420         u32 bit = BP_PATH(bp) ?
4421                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4422         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4423         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4424
4425         /* Set the bit */
4426         val |= bit;
4427         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4428         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4429 }
4430
4431 /*
4432  * Checks the RESET_IN_PROGRESS bit for the given engine.
4433  * should be run under rtnl lock
4434  */
4435 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4436 {
4437         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4438         u32 bit = engine ?
4439                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4440
4441         /* return false if bit is set */
4442         return (val & bit) ? false : true;
4443 }
4444
4445 /*
4446  * set pf load for the current pf.
4447  *
4448  * should be run under rtnl lock
4449  */
4450 void bnx2x_set_pf_load(struct bnx2x *bp)
4451 {
4452         u32 val1, val;
4453         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4454                              BNX2X_PATH0_LOAD_CNT_MASK;
4455         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4456                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4457
4458         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4459         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4460
4461         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4462
4463         /* get the current counter value */
4464         val1 = (val & mask) >> shift;
4465
4466         /* set bit of that PF */
4467         val1 |= (1 << bp->pf_num);
4468
4469         /* clear the old value */
4470         val &= ~mask;
4471
4472         /* set the new one */
4473         val |= ((val1 << shift) & mask);
4474
4475         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4476         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4477 }
4478
4479 /**
4480  * bnx2x_clear_pf_load - clear pf load mark
4481  *
4482  * @bp:         driver handle
4483  *
4484  * Should be run under rtnl lock.
4485  * Decrements the load counter for the current engine. Returns
4486  * whether other functions are still loaded
4487  */
4488 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4489 {
4490         u32 val1, val;
4491         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4492                              BNX2X_PATH0_LOAD_CNT_MASK;
4493         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4494                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4495
4496         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4497         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4498         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4499
4500         /* get the current counter value */
4501         val1 = (val & mask) >> shift;
4502
4503         /* clear bit of that PF */
4504         val1 &= ~(1 << bp->pf_num);
4505
4506         /* clear the old value */
4507         val &= ~mask;
4508
4509         /* set the new one */
4510         val |= ((val1 << shift) & mask);
4511
4512         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4513         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4514         return val1 != 0;
4515 }
4516
4517 /*
4518  * Read the load status for the current engine.
4519  *
4520  * should be run under rtnl lock
4521  */
4522 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4523 {
4524         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4525                              BNX2X_PATH0_LOAD_CNT_MASK);
4526         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4527                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4528         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4529
4530         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4531
4532         val = (val & mask) >> shift;
4533
4534         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4535            engine, val);
4536
4537         return val != 0;
4538 }
4539
4540 static void _print_parity(struct bnx2x *bp, u32 reg)
4541 {
4542         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4543 }
4544
4545 static void _print_next_block(int idx, const char *blk)
4546 {
4547         pr_cont("%s%s", idx ? ", " : "", blk);
4548 }
4549
4550 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4551                                             int *par_num, bool print)
4552 {
4553         u32 cur_bit;
4554         bool res;
4555         int i;
4556
4557         res = false;
4558
4559         for (i = 0; sig; i++) {
4560                 cur_bit = (0x1UL << i);
4561                 if (sig & cur_bit) {
4562                         res |= true; /* Each bit is real error! */
4563
4564                         if (print) {
4565                                 switch (cur_bit) {
4566                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4567                                         _print_next_block((*par_num)++, "BRB");
4568                                         _print_parity(bp,
4569                                                       BRB1_REG_BRB1_PRTY_STS);
4570                                         break;
4571                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4572                                         _print_next_block((*par_num)++,
4573                                                           "PARSER");
4574                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4575                                         break;
4576                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4577                                         _print_next_block((*par_num)++, "TSDM");
4578                                         _print_parity(bp,
4579                                                       TSDM_REG_TSDM_PRTY_STS);
4580                                         break;
4581                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4582                                         _print_next_block((*par_num)++,
4583                                                           "SEARCHER");
4584                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4585                                         break;
4586                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4587                                         _print_next_block((*par_num)++, "TCM");
4588                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4589                                         break;
4590                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4591                                         _print_next_block((*par_num)++,
4592                                                           "TSEMI");
4593                                         _print_parity(bp,
4594                                                       TSEM_REG_TSEM_PRTY_STS_0);
4595                                         _print_parity(bp,
4596                                                       TSEM_REG_TSEM_PRTY_STS_1);
4597                                         break;
4598                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4599                                         _print_next_block((*par_num)++, "XPB");
4600                                         _print_parity(bp, GRCBASE_XPB +
4601                                                           PB_REG_PB_PRTY_STS);
4602                                         break;
4603                                 }
4604                         }
4605
4606                         /* Clear the bit */
4607                         sig &= ~cur_bit;
4608                 }
4609         }
4610
4611         return res;
4612 }
4613
4614 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4615                                             int *par_num, bool *global,
4616                                             bool print)
4617 {
4618         u32 cur_bit;
4619         bool res;
4620         int i;
4621
4622         res = false;
4623
4624         for (i = 0; sig; i++) {
4625                 cur_bit = (0x1UL << i);
4626                 if (sig & cur_bit) {
4627                         res |= true; /* Each bit is real error! */
4628                         switch (cur_bit) {
4629                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4630                                 if (print) {
4631                                         _print_next_block((*par_num)++, "PBF");
4632                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4633                                 }
4634                                 break;
4635                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4636                                 if (print) {
4637                                         _print_next_block((*par_num)++, "QM");
4638                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4639                                 }
4640                                 break;
4641                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4642                                 if (print) {
4643                                         _print_next_block((*par_num)++, "TM");
4644                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4645                                 }
4646                                 break;
4647                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4648                                 if (print) {
4649                                         _print_next_block((*par_num)++, "XSDM");
4650                                         _print_parity(bp,
4651                                                       XSDM_REG_XSDM_PRTY_STS);
4652                                 }
4653                                 break;
4654                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4655                                 if (print) {
4656                                         _print_next_block((*par_num)++, "XCM");
4657                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4658                                 }
4659                                 break;
4660                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4661                                 if (print) {
4662                                         _print_next_block((*par_num)++,
4663                                                           "XSEMI");
4664                                         _print_parity(bp,
4665                                                       XSEM_REG_XSEM_PRTY_STS_0);
4666                                         _print_parity(bp,
4667                                                       XSEM_REG_XSEM_PRTY_STS_1);
4668                                 }
4669                                 break;
4670                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4671                                 if (print) {
4672                                         _print_next_block((*par_num)++,
4673                                                           "DOORBELLQ");
4674                                         _print_parity(bp,
4675                                                       DORQ_REG_DORQ_PRTY_STS);
4676                                 }
4677                                 break;
4678                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4679                                 if (print) {
4680                                         _print_next_block((*par_num)++, "NIG");
4681                                         if (CHIP_IS_E1x(bp)) {
4682                                                 _print_parity(bp,
4683                                                         NIG_REG_NIG_PRTY_STS);
4684                                         } else {
4685                                                 _print_parity(bp,
4686                                                         NIG_REG_NIG_PRTY_STS_0);
4687                                                 _print_parity(bp,
4688                                                         NIG_REG_NIG_PRTY_STS_1);
4689                                         }
4690                                 }
4691                                 break;
4692                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4693                                 if (print)
4694                                         _print_next_block((*par_num)++,
4695                                                           "VAUX PCI CORE");
4696                                 *global = true;
4697                                 break;
4698                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4699                                 if (print) {
4700                                         _print_next_block((*par_num)++,
4701                                                           "DEBUG");
4702                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4703                                 }
4704                                 break;
4705                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4706                                 if (print) {
4707                                         _print_next_block((*par_num)++, "USDM");
4708                                         _print_parity(bp,
4709                                                       USDM_REG_USDM_PRTY_STS);
4710                                 }
4711                                 break;
4712                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4713                                 if (print) {
4714                                         _print_next_block((*par_num)++, "UCM");
4715                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4716                                 }
4717                                 break;
4718                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4719                                 if (print) {
4720                                         _print_next_block((*par_num)++,
4721                                                           "USEMI");
4722                                         _print_parity(bp,
4723                                                       USEM_REG_USEM_PRTY_STS_0);
4724                                         _print_parity(bp,
4725                                                       USEM_REG_USEM_PRTY_STS_1);
4726                                 }
4727                                 break;
4728                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4729                                 if (print) {
4730                                         _print_next_block((*par_num)++, "UPB");
4731                                         _print_parity(bp, GRCBASE_UPB +
4732                                                           PB_REG_PB_PRTY_STS);
4733                                 }
4734                                 break;
4735                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4736                                 if (print) {
4737                                         _print_next_block((*par_num)++, "CSDM");
4738                                         _print_parity(bp,
4739                                                       CSDM_REG_CSDM_PRTY_STS);
4740                                 }
4741                                 break;
4742                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4743                                 if (print) {
4744                                         _print_next_block((*par_num)++, "CCM");
4745                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4746                                 }
4747                                 break;
4748                         }
4749
4750                         /* Clear the bit */
4751                         sig &= ~cur_bit;
4752                 }
4753         }
4754
4755         return res;
4756 }
4757
4758 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4759                                             int *par_num, bool print)
4760 {
4761         u32 cur_bit;
4762         bool res;
4763         int i;
4764
4765         res = false;
4766
4767         for (i = 0; sig; i++) {
4768                 cur_bit = (0x1UL << i);
4769                 if (sig & cur_bit) {
4770                         res = true; /* Each bit is real error! */
4771                         if (print) {
4772                                 switch (cur_bit) {
4773                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4774                                         _print_next_block((*par_num)++,
4775                                                           "CSEMI");
4776                                         _print_parity(bp,
4777                                                       CSEM_REG_CSEM_PRTY_STS_0);
4778                                         _print_parity(bp,
4779                                                       CSEM_REG_CSEM_PRTY_STS_1);
4780                                         break;
4781                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4782                                         _print_next_block((*par_num)++, "PXP");
4783                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4784                                         _print_parity(bp,
4785                                                       PXP2_REG_PXP2_PRTY_STS_0);
4786                                         _print_parity(bp,
4787                                                       PXP2_REG_PXP2_PRTY_STS_1);
4788                                         break;
4789                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4790                                         _print_next_block((*par_num)++,
4791                                                           "PXPPCICLOCKCLIENT");
4792                                         break;
4793                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4794                                         _print_next_block((*par_num)++, "CFC");
4795                                         _print_parity(bp,
4796                                                       CFC_REG_CFC_PRTY_STS);
4797                                         break;
4798                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4799                                         _print_next_block((*par_num)++, "CDU");
4800                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4801                                         break;
4802                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4803                                         _print_next_block((*par_num)++, "DMAE");
4804                                         _print_parity(bp,
4805                                                       DMAE_REG_DMAE_PRTY_STS);
4806                                         break;
4807                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4808                                         _print_next_block((*par_num)++, "IGU");
4809                                         if (CHIP_IS_E1x(bp))
4810                                                 _print_parity(bp,
4811                                                         HC_REG_HC_PRTY_STS);
4812                                         else
4813                                                 _print_parity(bp,
4814                                                         IGU_REG_IGU_PRTY_STS);
4815                                         break;
4816                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4817                                         _print_next_block((*par_num)++, "MISC");
4818                                         _print_parity(bp,
4819                                                       MISC_REG_MISC_PRTY_STS);
4820                                         break;
4821                                 }
4822                         }
4823
4824                         /* Clear the bit */
4825                         sig &= ~cur_bit;
4826                 }
4827         }
4828
4829         return res;
4830 }
4831
4832 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4833                                             int *par_num, bool *global,
4834                                             bool print)
4835 {
4836         bool res = false;
4837         u32 cur_bit;
4838         int i;
4839
4840         for (i = 0; sig; i++) {
4841                 cur_bit = (0x1UL << i);
4842                 if (sig & cur_bit) {
4843                         switch (cur_bit) {
4844                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4845                                 if (print)
4846                                         _print_next_block((*par_num)++,
4847                                                           "MCP ROM");
4848                                 *global = true;
4849                                 res = true;
4850                                 break;
4851                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4852                                 if (print)
4853                                         _print_next_block((*par_num)++,
4854                                                           "MCP UMP RX");
4855                                 *global = true;
4856                                 res = true;
4857                                 break;
4858                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4859                                 if (print)
4860                                         _print_next_block((*par_num)++,
4861                                                           "MCP UMP TX");
4862                                 *global = true;
4863                                 res = true;
4864                                 break;
4865                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4866                                 (*par_num)++;
4867                                 /* clear latched SCPAD PATIRY from MCP */
4868                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4869                                        1UL << 10);
4870                                 break;
4871                         }
4872
4873                         /* Clear the bit */
4874                         sig &= ~cur_bit;
4875                 }
4876         }
4877
4878         return res;
4879 }
4880
4881 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4882                                             int *par_num, bool print)
4883 {
4884         u32 cur_bit;
4885         bool res;
4886         int i;
4887
4888         res = false;
4889
4890         for (i = 0; sig; i++) {
4891                 cur_bit = (0x1UL << i);
4892                 if (sig & cur_bit) {
4893                         res = true; /* Each bit is real error! */
4894                         if (print) {
4895                                 switch (cur_bit) {
4896                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4897                                         _print_next_block((*par_num)++,
4898                                                           "PGLUE_B");
4899                                         _print_parity(bp,
4900                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4901                                         break;
4902                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4903                                         _print_next_block((*par_num)++, "ATC");
4904                                         _print_parity(bp,
4905                                                       ATC_REG_ATC_PRTY_STS);
4906                                         break;
4907                                 }
4908                         }
4909                         /* Clear the bit */
4910                         sig &= ~cur_bit;
4911                 }
4912         }
4913
4914         return res;
4915 }
4916
4917 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4918                               u32 *sig)
4919 {
4920         bool res = false;
4921
4922         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4923             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4924             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4925             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4926             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4927                 int par_num = 0;
4928
4929                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4930                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4931                           sig[0] & HW_PRTY_ASSERT_SET_0,
4932                           sig[1] & HW_PRTY_ASSERT_SET_1,
4933                           sig[2] & HW_PRTY_ASSERT_SET_2,
4934                           sig[3] & HW_PRTY_ASSERT_SET_3,
4935                           sig[4] & HW_PRTY_ASSERT_SET_4);
4936                 if (print) {
4937                         if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4938                              (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4939                              (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4940                              (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4941                              (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4942                                 netdev_err(bp->dev,
4943                                            "Parity errors detected in blocks: ");
4944                         } else {
4945                                 print = false;
4946                         }
4947                 }
4948                 res |= bnx2x_check_blocks_with_parity0(bp,
4949                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4950                 res |= bnx2x_check_blocks_with_parity1(bp,
4951                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4952                 res |= bnx2x_check_blocks_with_parity2(bp,
4953                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4954                 res |= bnx2x_check_blocks_with_parity3(bp,
4955                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4956                 res |= bnx2x_check_blocks_with_parity4(bp,
4957                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4958
4959                 if (print)
4960                         pr_cont("\n");
4961         }
4962
4963         return res;
4964 }
4965
4966 /**
4967  * bnx2x_chk_parity_attn - checks for parity attentions.
4968  *
4969  * @bp:         driver handle
4970  * @global:     true if there was a global attention
4971  * @print:      show parity attention in syslog
4972  */
4973 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4974 {
4975         struct attn_route attn = { {0} };
4976         int port = BP_PORT(bp);
4977
4978         attn.sig[0] = REG_RD(bp,
4979                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4980                              port*4);
4981         attn.sig[1] = REG_RD(bp,
4982                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4983                              port*4);
4984         attn.sig[2] = REG_RD(bp,
4985                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4986                              port*4);
4987         attn.sig[3] = REG_RD(bp,
4988                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4989                              port*4);
4990         /* Since MCP attentions can't be disabled inside the block, we need to
4991          * read AEU registers to see whether they're currently disabled
4992          */
4993         attn.sig[3] &= ((REG_RD(bp,
4994                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4995                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4996                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4997                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4998
4999         if (!CHIP_IS_E1x(bp))
5000                 attn.sig[4] = REG_RD(bp,
5001                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5002                                      port*4);
5003
5004         return bnx2x_parity_attn(bp, global, print, attn.sig);
5005 }
5006
5007 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5008 {
5009         u32 val;
5010         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5011
5012                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5013                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5014                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5015                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5016                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5017                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5018                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5019                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5020                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5021                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5022                 if (val &
5023                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5024                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5025                 if (val &
5026                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5027                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5028                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5029                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5030                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5031                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5032                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5033                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5034         }
5035         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5036                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5037                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5038                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5039                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5040                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5041                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5042                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5043                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5044                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5045                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5046                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5047                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5048                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5049                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5050         }
5051
5052         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5053                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5054                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5055                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5056                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5057         }
5058 }
5059
5060 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5061 {
5062         struct attn_route attn, *group_mask;
5063         int port = BP_PORT(bp);
5064         int index;
5065         u32 reg_addr;
5066         u32 val;
5067         u32 aeu_mask;
5068         bool global = false;
5069
5070         /* need to take HW lock because MCP or other port might also
5071            try to handle this event */
5072         bnx2x_acquire_alr(bp);
5073
5074         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5075 #ifndef BNX2X_STOP_ON_ERROR
5076                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5077                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5078                 /* Disable HW interrupts */
5079                 bnx2x_int_disable(bp);
5080                 /* In case of parity errors don't handle attentions so that
5081                  * other function would "see" parity errors.
5082                  */
5083 #else
5084                 bnx2x_panic();
5085 #endif
5086                 bnx2x_release_alr(bp);
5087                 return;
5088         }
5089
5090         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5091         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5092         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5093         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5094         if (!CHIP_IS_E1x(bp))
5095                 attn.sig[4] =
5096                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5097         else
5098                 attn.sig[4] = 0;
5099
5100         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5101            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5102
5103         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5104                 if (deasserted & (1 << index)) {
5105                         group_mask = &bp->attn_group[index];
5106
5107                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5108                            index,
5109                            group_mask->sig[0], group_mask->sig[1],
5110                            group_mask->sig[2], group_mask->sig[3],
5111                            group_mask->sig[4]);
5112
5113                         bnx2x_attn_int_deasserted4(bp,
5114                                         attn.sig[4] & group_mask->sig[4]);
5115                         bnx2x_attn_int_deasserted3(bp,
5116                                         attn.sig[3] & group_mask->sig[3]);
5117                         bnx2x_attn_int_deasserted1(bp,
5118                                         attn.sig[1] & group_mask->sig[1]);
5119                         bnx2x_attn_int_deasserted2(bp,
5120                                         attn.sig[2] & group_mask->sig[2]);
5121                         bnx2x_attn_int_deasserted0(bp,
5122                                         attn.sig[0] & group_mask->sig[0]);
5123                 }
5124         }
5125
5126         bnx2x_release_alr(bp);
5127
5128         if (bp->common.int_block == INT_BLOCK_HC)
5129                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5130                             COMMAND_REG_ATTN_BITS_CLR);
5131         else
5132                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5133
5134         val = ~deasserted;
5135         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5136            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5137         REG_WR(bp, reg_addr, val);
5138
5139         if (~bp->attn_state & deasserted)
5140                 BNX2X_ERR("IGU ERROR\n");
5141
5142         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5143                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5144
5145         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5146         aeu_mask = REG_RD(bp, reg_addr);
5147
5148         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5149            aeu_mask, deasserted);
5150         aeu_mask |= (deasserted & 0x3ff);
5151         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5152
5153         REG_WR(bp, reg_addr, aeu_mask);
5154         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5155
5156         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5157         bp->attn_state &= ~deasserted;
5158         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5159 }
5160
5161 static void bnx2x_attn_int(struct bnx2x *bp)
5162 {
5163         /* read local copy of bits */
5164         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5165                                                                 attn_bits);
5166         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5167                                                                 attn_bits_ack);
5168         u32 attn_state = bp->attn_state;
5169
5170         /* look for changed bits */
5171         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5172         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5173
5174         DP(NETIF_MSG_HW,
5175            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5176            attn_bits, attn_ack, asserted, deasserted);
5177
5178         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5179                 BNX2X_ERR("BAD attention state\n");
5180
5181         /* handle bits that were raised */
5182         if (asserted)
5183                 bnx2x_attn_int_asserted(bp, asserted);
5184
5185         if (deasserted)
5186                 bnx2x_attn_int_deasserted(bp, deasserted);
5187 }
5188
5189 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5190                       u16 index, u8 op, u8 update)
5191 {
5192         u32 igu_addr = bp->igu_base_addr;
5193         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5194         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5195                              igu_addr);
5196 }
5197
5198 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5199 {
5200         /* No memory barriers */
5201         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5202         mmiowb(); /* keep prod updates ordered */
5203 }
5204
5205 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5206                                       union event_ring_elem *elem)
5207 {
5208         u8 err = elem->message.error;
5209
5210         if (!bp->cnic_eth_dev.starting_cid  ||
5211             (cid < bp->cnic_eth_dev.starting_cid &&
5212             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5213                 return 1;
5214
5215         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5216
5217         if (unlikely(err)) {
5218
5219                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5220                           cid);
5221                 bnx2x_panic_dump(bp, false);
5222         }
5223         bnx2x_cnic_cfc_comp(bp, cid, err);
5224         return 0;
5225 }
5226
5227 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5228 {
5229         struct bnx2x_mcast_ramrod_params rparam;
5230         int rc;
5231
5232         memset(&rparam, 0, sizeof(rparam));
5233
5234         rparam.mcast_obj = &bp->mcast_obj;
5235
5236         netif_addr_lock_bh(bp->dev);
5237
5238         /* Clear pending state for the last command */
5239         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5240
5241         /* If there are pending mcast commands - send them */
5242         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5243                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5244                 if (rc < 0)
5245                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5246                                   rc);
5247         }
5248
5249         netif_addr_unlock_bh(bp->dev);
5250 }
5251
5252 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5253                                             union event_ring_elem *elem)
5254 {
5255         unsigned long ramrod_flags = 0;
5256         int rc = 0;
5257         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5258         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5259
5260         /* Always push next commands out, don't wait here */
5261         __set_bit(RAMROD_CONT, &ramrod_flags);
5262
5263         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5264                             >> BNX2X_SWCID_SHIFT) {
5265         case BNX2X_FILTER_MAC_PENDING:
5266                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5267                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5268                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5269                 else
5270                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5271
5272                 break;
5273         case BNX2X_FILTER_MCAST_PENDING:
5274                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5275                 /* This is only relevant for 57710 where multicast MACs are
5276                  * configured as unicast MACs using the same ramrod.
5277                  */
5278                 bnx2x_handle_mcast_eqe(bp);
5279                 return;
5280         default:
5281                 BNX2X_ERR("Unsupported classification command: %d\n",
5282                           elem->message.data.eth_event.echo);
5283                 return;
5284         }
5285
5286         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5287
5288         if (rc < 0)
5289                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5290         else if (rc > 0)
5291                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5292 }
5293
5294 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5295
5296 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5297 {
5298         netif_addr_lock_bh(bp->dev);
5299
5300         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5301
5302         /* Send rx_mode command again if was requested */
5303         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5304                 bnx2x_set_storm_rx_mode(bp);
5305         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5306                                     &bp->sp_state))
5307                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5308         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5309                                     &bp->sp_state))
5310                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5311
5312         netif_addr_unlock_bh(bp->dev);
5313 }
5314
5315 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5316                                               union event_ring_elem *elem)
5317 {
5318         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5319                 DP(BNX2X_MSG_SP,
5320                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5321                    elem->message.data.vif_list_event.func_bit_map);
5322                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5323                         elem->message.data.vif_list_event.func_bit_map);
5324         } else if (elem->message.data.vif_list_event.echo ==
5325                    VIF_LIST_RULE_SET) {
5326                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5327                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5328         }
5329 }
5330
5331 /* called with rtnl_lock */
5332 static void bnx2x_after_function_update(struct bnx2x *bp)
5333 {
5334         int q, rc;
5335         struct bnx2x_fastpath *fp;
5336         struct bnx2x_queue_state_params queue_params = {NULL};
5337         struct bnx2x_queue_update_params *q_update_params =
5338                 &queue_params.params.update;
5339
5340         /* Send Q update command with afex vlan removal values for all Qs */
5341         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5342
5343         /* set silent vlan removal values according to vlan mode */
5344         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5345                   &q_update_params->update_flags);
5346         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5347                   &q_update_params->update_flags);
5348         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5349
5350         /* in access mode mark mask and value are 0 to strip all vlans */
5351         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5352                 q_update_params->silent_removal_value = 0;
5353                 q_update_params->silent_removal_mask = 0;
5354         } else {
5355                 q_update_params->silent_removal_value =
5356                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5357                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5358         }
5359
5360         for_each_eth_queue(bp, q) {
5361                 /* Set the appropriate Queue object */
5362                 fp = &bp->fp[q];
5363                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5364
5365                 /* send the ramrod */
5366                 rc = bnx2x_queue_state_change(bp, &queue_params);
5367                 if (rc < 0)
5368                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5369                                   q);
5370         }
5371
5372         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5373                 fp = &bp->fp[FCOE_IDX(bp)];
5374                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5375
5376                 /* clear pending completion bit */
5377                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5378
5379                 /* mark latest Q bit */
5380                 smp_mb__before_atomic();
5381                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5382                 smp_mb__after_atomic();
5383
5384                 /* send Q update ramrod for FCoE Q */
5385                 rc = bnx2x_queue_state_change(bp, &queue_params);
5386                 if (rc < 0)
5387                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5388                                   q);
5389         } else {
5390                 /* If no FCoE ring - ACK MCP now */
5391                 bnx2x_link_report(bp);
5392                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5393         }
5394 }
5395
5396 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5397         struct bnx2x *bp, u32 cid)
5398 {
5399         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5400
5401         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5402                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5403         else
5404                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5405 }
5406
5407 static void bnx2x_eq_int(struct bnx2x *bp)
5408 {
5409         u16 hw_cons, sw_cons, sw_prod;
5410         union event_ring_elem *elem;
5411         u8 echo;
5412         u32 cid;
5413         u8 opcode;
5414         int rc, spqe_cnt = 0;
5415         struct bnx2x_queue_sp_obj *q_obj;
5416         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5417         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5418
5419         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5420
5421         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5422          * when we get the next-page we need to adjust so the loop
5423          * condition below will be met. The next element is the size of a
5424          * regular element and hence incrementing by 1
5425          */
5426         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5427                 hw_cons++;
5428
5429         /* This function may never run in parallel with itself for a
5430          * specific bp, thus there is no need in "paired" read memory
5431          * barrier here.
5432          */
5433         sw_cons = bp->eq_cons;
5434         sw_prod = bp->eq_prod;
5435
5436         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5437                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5438
5439         for (; sw_cons != hw_cons;
5440               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5441
5442                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5443
5444                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5445                 if (!rc) {
5446                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5447                            rc);
5448                         goto next_spqe;
5449                 }
5450
5451                 /* elem CID originates from FW; actually LE */
5452                 cid = SW_CID((__force __le32)
5453                              elem->message.data.cfc_del_event.cid);
5454                 opcode = elem->message.opcode;
5455
5456                 /* handle eq element */
5457                 switch (opcode) {
5458                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5459                         bnx2x_vf_mbx_schedule(bp,
5460                                               &elem->message.data.vf_pf_event);
5461                         continue;
5462
5463                 case EVENT_RING_OPCODE_STAT_QUERY:
5464                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5465                                "got statistics comp event %d\n",
5466                                bp->stats_comp++);
5467                         /* nothing to do with stats comp */
5468                         goto next_spqe;
5469
5470                 case EVENT_RING_OPCODE_CFC_DEL:
5471                         /* handle according to cid range */
5472                         /*
5473                          * we may want to verify here that the bp state is
5474                          * HALTING
5475                          */
5476                         DP(BNX2X_MSG_SP,
5477                            "got delete ramrod for MULTI[%d]\n", cid);
5478
5479                         if (CNIC_LOADED(bp) &&
5480                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5481                                 goto next_spqe;
5482
5483                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5484
5485                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5486                                 break;
5487
5488                         goto next_spqe;
5489
5490                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5491                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5492                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5493                         if (f_obj->complete_cmd(bp, f_obj,
5494                                                 BNX2X_F_CMD_TX_STOP))
5495                                 break;
5496                         goto next_spqe;
5497
5498                 case EVENT_RING_OPCODE_START_TRAFFIC:
5499                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5500                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5501                         if (f_obj->complete_cmd(bp, f_obj,
5502                                                 BNX2X_F_CMD_TX_START))
5503                                 break;
5504                         goto next_spqe;
5505
5506                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5507                         echo = elem->message.data.function_update_event.echo;
5508                         if (echo == SWITCH_UPDATE) {
5509                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5510                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5511                                 if (f_obj->complete_cmd(
5512                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5513                                         break;
5514
5515                         } else {
5516                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5517
5518                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5519                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5520                                 f_obj->complete_cmd(bp, f_obj,
5521                                                     BNX2X_F_CMD_AFEX_UPDATE);
5522
5523                                 /* We will perform the Queues update from
5524                                  * sp_rtnl task as all Queue SP operations
5525                                  * should run under rtnl_lock.
5526                                  */
5527                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5528                         }
5529
5530                         goto next_spqe;
5531
5532                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5533                         f_obj->complete_cmd(bp, f_obj,
5534                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5535                         bnx2x_after_afex_vif_lists(bp, elem);
5536                         goto next_spqe;
5537                 case EVENT_RING_OPCODE_FUNCTION_START:
5538                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5539                            "got FUNC_START ramrod\n");
5540                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5541                                 break;
5542
5543                         goto next_spqe;
5544
5545                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5546                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5547                            "got FUNC_STOP ramrod\n");
5548                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5549                                 break;
5550
5551                         goto next_spqe;
5552
5553                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5554                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5555                            "got set_timesync ramrod completion\n");
5556                         if (f_obj->complete_cmd(bp, f_obj,
5557                                                 BNX2X_F_CMD_SET_TIMESYNC))
5558                                 break;
5559                         goto next_spqe;
5560                 }
5561
5562                 switch (opcode | bp->state) {
5563                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5564                       BNX2X_STATE_OPEN):
5565                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5566                       BNX2X_STATE_OPENING_WAIT4_PORT):
5567                         cid = elem->message.data.eth_event.echo &
5568                                 BNX2X_SWCID_MASK;
5569                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5570                            cid);
5571                         rss_raw->clear_pending(rss_raw);
5572                         break;
5573
5574                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5575                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5576                 case (EVENT_RING_OPCODE_SET_MAC |
5577                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5578                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5579                       BNX2X_STATE_OPEN):
5580                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5581                       BNX2X_STATE_DIAG):
5582                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5583                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5584                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5585                         bnx2x_handle_classification_eqe(bp, elem);
5586                         break;
5587
5588                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5589                       BNX2X_STATE_OPEN):
5590                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5591                       BNX2X_STATE_DIAG):
5592                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5593                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5594                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5595                         bnx2x_handle_mcast_eqe(bp);
5596                         break;
5597
5598                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5599                       BNX2X_STATE_OPEN):
5600                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5601                       BNX2X_STATE_DIAG):
5602                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5603                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5604                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5605                         bnx2x_handle_rx_mode_eqe(bp);
5606                         break;
5607                 default:
5608                         /* unknown event log error and continue */
5609                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5610                                   elem->message.opcode, bp->state);
5611                 }
5612 next_spqe:
5613                 spqe_cnt++;
5614         } /* for */
5615
5616         smp_mb__before_atomic();
5617         atomic_add(spqe_cnt, &bp->eq_spq_left);
5618
5619         bp->eq_cons = sw_cons;
5620         bp->eq_prod = sw_prod;
5621         /* Make sure that above mem writes were issued towards the memory */
5622         smp_wmb();
5623
5624         /* update producer */
5625         bnx2x_update_eq_prod(bp, bp->eq_prod);
5626 }
5627
5628 static void bnx2x_sp_task(struct work_struct *work)
5629 {
5630         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5631
5632         DP(BNX2X_MSG_SP, "sp task invoked\n");
5633
5634         /* make sure the atomic interrupt_occurred has been written */
5635         smp_rmb();
5636         if (atomic_read(&bp->interrupt_occurred)) {
5637
5638                 /* what work needs to be performed? */
5639                 u16 status = bnx2x_update_dsb_idx(bp);
5640
5641                 DP(BNX2X_MSG_SP, "status %x\n", status);
5642                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5643                 atomic_set(&bp->interrupt_occurred, 0);
5644
5645                 /* HW attentions */
5646                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5647                         bnx2x_attn_int(bp);
5648                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5649                 }
5650
5651                 /* SP events: STAT_QUERY and others */
5652                 if (status & BNX2X_DEF_SB_IDX) {
5653                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5654
5655                 if (FCOE_INIT(bp) &&
5656                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5657                                 /* Prevent local bottom-halves from running as
5658                                  * we are going to change the local NAPI list.
5659                                  */
5660                                 local_bh_disable();
5661                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5662                                 local_bh_enable();
5663                         }
5664
5665                         /* Handle EQ completions */
5666                         bnx2x_eq_int(bp);
5667                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5668                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5669
5670                         status &= ~BNX2X_DEF_SB_IDX;
5671                 }
5672
5673                 /* if status is non zero then perhaps something went wrong */
5674                 if (unlikely(status))
5675                         DP(BNX2X_MSG_SP,
5676                            "got an unknown interrupt! (status 0x%x)\n", status);
5677
5678                 /* ack status block only if something was actually handled */
5679                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5680                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5681         }
5682
5683         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5684         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5685                                &bp->sp_state)) {
5686                 bnx2x_link_report(bp);
5687                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5688         }
5689 }
5690
5691 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5692 {
5693         struct net_device *dev = dev_instance;
5694         struct bnx2x *bp = netdev_priv(dev);
5695
5696         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5697                      IGU_INT_DISABLE, 0);
5698
5699 #ifdef BNX2X_STOP_ON_ERROR
5700         if (unlikely(bp->panic))
5701                 return IRQ_HANDLED;
5702 #endif
5703
5704         if (CNIC_LOADED(bp)) {
5705                 struct cnic_ops *c_ops;
5706
5707                 rcu_read_lock();
5708                 c_ops = rcu_dereference(bp->cnic_ops);
5709                 if (c_ops)
5710                         c_ops->cnic_handler(bp->cnic_data, NULL);
5711                 rcu_read_unlock();
5712         }
5713
5714         /* schedule sp task to perform default status block work, ack
5715          * attentions and enable interrupts.
5716          */
5717         bnx2x_schedule_sp_task(bp);
5718
5719         return IRQ_HANDLED;
5720 }
5721
5722 /* end of slow path */
5723
5724 void bnx2x_drv_pulse(struct bnx2x *bp)
5725 {
5726         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5727                  bp->fw_drv_pulse_wr_seq);
5728 }
5729
5730 static void bnx2x_timer(unsigned long data)
5731 {
5732         struct bnx2x *bp = (struct bnx2x *) data;
5733
5734         if (!netif_running(bp->dev))
5735                 return;
5736
5737         if (IS_PF(bp) &&
5738             !BP_NOMCP(bp)) {
5739                 int mb_idx = BP_FW_MB_IDX(bp);
5740                 u16 drv_pulse;
5741                 u16 mcp_pulse;
5742
5743                 ++bp->fw_drv_pulse_wr_seq;
5744                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5745                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5746                 bnx2x_drv_pulse(bp);
5747
5748                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5749                              MCP_PULSE_SEQ_MASK);
5750                 /* The delta between driver pulse and mcp response
5751                  * should not get too big. If the MFW is more than 5 pulses
5752                  * behind, we should worry about it enough to generate an error
5753                  * log.
5754                  */
5755                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5756                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5757                                   drv_pulse, mcp_pulse);
5758         }
5759
5760         if (bp->state == BNX2X_STATE_OPEN)
5761                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5762
5763         /* sample pf vf bulletin board for new posts from pf */
5764         if (IS_VF(bp))
5765                 bnx2x_timer_sriov(bp);
5766
5767         mod_timer(&bp->timer, jiffies + bp->current_interval);
5768 }
5769
5770 /* end of Statistics */
5771
5772 /* nic init */
5773
5774 /*
5775  * nic init service functions
5776  */
5777
5778 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5779 {
5780         u32 i;
5781         if (!(len%4) && !(addr%4))
5782                 for (i = 0; i < len; i += 4)
5783                         REG_WR(bp, addr + i, fill);
5784         else
5785                 for (i = 0; i < len; i++)
5786                         REG_WR8(bp, addr + i, fill);
5787 }
5788
5789 /* helper: writes FP SP data to FW - data_size in dwords */
5790 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5791                                 int fw_sb_id,
5792                                 u32 *sb_data_p,
5793                                 u32 data_size)
5794 {
5795         int index;
5796         for (index = 0; index < data_size; index++)
5797                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5798                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5799                         sizeof(u32)*index,
5800                         *(sb_data_p + index));
5801 }
5802
5803 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5804 {
5805         u32 *sb_data_p;
5806         u32 data_size = 0;
5807         struct hc_status_block_data_e2 sb_data_e2;
5808         struct hc_status_block_data_e1x sb_data_e1x;
5809
5810         /* disable the function first */
5811         if (!CHIP_IS_E1x(bp)) {
5812                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5813                 sb_data_e2.common.state = SB_DISABLED;
5814                 sb_data_e2.common.p_func.vf_valid = false;
5815                 sb_data_p = (u32 *)&sb_data_e2;
5816                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5817         } else {
5818                 memset(&sb_data_e1x, 0,
5819                        sizeof(struct hc_status_block_data_e1x));
5820                 sb_data_e1x.common.state = SB_DISABLED;
5821                 sb_data_e1x.common.p_func.vf_valid = false;
5822                 sb_data_p = (u32 *)&sb_data_e1x;
5823                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5824         }
5825         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5826
5827         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5828                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5829                         CSTORM_STATUS_BLOCK_SIZE);
5830         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5831                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5832                         CSTORM_SYNC_BLOCK_SIZE);
5833 }
5834
5835 /* helper:  writes SP SB data to FW */
5836 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5837                 struct hc_sp_status_block_data *sp_sb_data)
5838 {
5839         int func = BP_FUNC(bp);
5840         int i;
5841         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5842                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5843                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5844                         i*sizeof(u32),
5845                         *((u32 *)sp_sb_data + i));
5846 }
5847
5848 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5849 {
5850         int func = BP_FUNC(bp);
5851         struct hc_sp_status_block_data sp_sb_data;
5852         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5853
5854         sp_sb_data.state = SB_DISABLED;
5855         sp_sb_data.p_func.vf_valid = false;
5856
5857         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5858
5859         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5860                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5861                         CSTORM_SP_STATUS_BLOCK_SIZE);
5862         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5863                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5864                         CSTORM_SP_SYNC_BLOCK_SIZE);
5865 }
5866
5867 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5868                                            int igu_sb_id, int igu_seg_id)
5869 {
5870         hc_sm->igu_sb_id = igu_sb_id;
5871         hc_sm->igu_seg_id = igu_seg_id;
5872         hc_sm->timer_value = 0xFF;
5873         hc_sm->time_to_expire = 0xFFFFFFFF;
5874 }
5875
5876 /* allocates state machine ids. */
5877 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5878 {
5879         /* zero out state machine indices */
5880         /* rx indices */
5881         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5882
5883         /* tx indices */
5884         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5885         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5886         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5887         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5888
5889         /* map indices */
5890         /* rx indices */
5891         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5892                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5893
5894         /* tx indices */
5895         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5896                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5897         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5898                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5899         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5900                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5901         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5902                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5903 }
5904
5905 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5906                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5907 {
5908         int igu_seg_id;
5909
5910         struct hc_status_block_data_e2 sb_data_e2;
5911         struct hc_status_block_data_e1x sb_data_e1x;
5912         struct hc_status_block_sm  *hc_sm_p;
5913         int data_size;
5914         u32 *sb_data_p;
5915
5916         if (CHIP_INT_MODE_IS_BC(bp))
5917                 igu_seg_id = HC_SEG_ACCESS_NORM;
5918         else
5919                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5920
5921         bnx2x_zero_fp_sb(bp, fw_sb_id);
5922
5923         if (!CHIP_IS_E1x(bp)) {
5924                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5925                 sb_data_e2.common.state = SB_ENABLED;
5926                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5927                 sb_data_e2.common.p_func.vf_id = vfid;
5928                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5929                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5930                 sb_data_e2.common.same_igu_sb_1b = true;
5931                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5932                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5933                 hc_sm_p = sb_data_e2.common.state_machine;
5934                 sb_data_p = (u32 *)&sb_data_e2;
5935                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5936                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5937         } else {
5938                 memset(&sb_data_e1x, 0,
5939                        sizeof(struct hc_status_block_data_e1x));
5940                 sb_data_e1x.common.state = SB_ENABLED;
5941                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5942                 sb_data_e1x.common.p_func.vf_id = 0xff;
5943                 sb_data_e1x.common.p_func.vf_valid = false;
5944                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5945                 sb_data_e1x.common.same_igu_sb_1b = true;
5946                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5947                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5948                 hc_sm_p = sb_data_e1x.common.state_machine;
5949                 sb_data_p = (u32 *)&sb_data_e1x;
5950                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5951                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5952         }
5953
5954         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5955                                        igu_sb_id, igu_seg_id);
5956         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5957                                        igu_sb_id, igu_seg_id);
5958
5959         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5960
5961         /* write indices to HW - PCI guarantees endianity of regpairs */
5962         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5963 }
5964
5965 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5966                                      u16 tx_usec, u16 rx_usec)
5967 {
5968         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5969                                     false, rx_usec);
5970         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5971                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5972                                        tx_usec);
5973         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5974                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5975                                        tx_usec);
5976         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5977                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5978                                        tx_usec);
5979 }
5980
5981 static void bnx2x_init_def_sb(struct bnx2x *bp)
5982 {
5983         struct host_sp_status_block *def_sb = bp->def_status_blk;
5984         dma_addr_t mapping = bp->def_status_blk_mapping;
5985         int igu_sp_sb_index;
5986         int igu_seg_id;
5987         int port = BP_PORT(bp);
5988         int func = BP_FUNC(bp);
5989         int reg_offset, reg_offset_en5;
5990         u64 section;
5991         int index;
5992         struct hc_sp_status_block_data sp_sb_data;
5993         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5994
5995         if (CHIP_INT_MODE_IS_BC(bp)) {
5996                 igu_sp_sb_index = DEF_SB_IGU_ID;
5997                 igu_seg_id = HC_SEG_ACCESS_DEF;
5998         } else {
5999                 igu_sp_sb_index = bp->igu_dsb_id;
6000                 igu_seg_id = IGU_SEG_ACCESS_DEF;
6001         }
6002
6003         /* ATTN */
6004         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6005                                             atten_status_block);
6006         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6007
6008         bp->attn_state = 0;
6009
6010         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6011                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6012         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6013                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6014         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6015                 int sindex;
6016                 /* take care of sig[0]..sig[4] */
6017                 for (sindex = 0; sindex < 4; sindex++)
6018                         bp->attn_group[index].sig[sindex] =
6019                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6020
6021                 if (!CHIP_IS_E1x(bp))
6022                         /*
6023                          * enable5 is separate from the rest of the registers,
6024                          * and therefore the address skip is 4
6025                          * and not 16 between the different groups
6026                          */
6027                         bp->attn_group[index].sig[4] = REG_RD(bp,
6028                                         reg_offset_en5 + 0x4*index);
6029                 else
6030                         bp->attn_group[index].sig[4] = 0;
6031         }
6032
6033         if (bp->common.int_block == INT_BLOCK_HC) {
6034                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6035                                      HC_REG_ATTN_MSG0_ADDR_L);
6036
6037                 REG_WR(bp, reg_offset, U64_LO(section));
6038                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6039         } else if (!CHIP_IS_E1x(bp)) {
6040                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6041                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6042         }
6043
6044         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6045                                             sp_sb);
6046
6047         bnx2x_zero_sp_sb(bp);
6048
6049         /* PCI guarantees endianity of regpairs */
6050         sp_sb_data.state                = SB_ENABLED;
6051         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6052         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6053         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6054         sp_sb_data.igu_seg_id           = igu_seg_id;
6055         sp_sb_data.p_func.pf_id         = func;
6056         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6057         sp_sb_data.p_func.vf_id         = 0xff;
6058
6059         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6060
6061         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6062 }
6063
6064 void bnx2x_update_coalesce(struct bnx2x *bp)
6065 {
6066         int i;
6067
6068         for_each_eth_queue(bp, i)
6069                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6070                                          bp->tx_ticks, bp->rx_ticks);
6071 }
6072
6073 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6074 {
6075         spin_lock_init(&bp->spq_lock);
6076         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6077
6078         bp->spq_prod_idx = 0;
6079         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6080         bp->spq_prod_bd = bp->spq;
6081         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6082 }
6083
6084 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6085 {
6086         int i;
6087         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6088                 union event_ring_elem *elem =
6089                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6090
6091                 elem->next_page.addr.hi =
6092                         cpu_to_le32(U64_HI(bp->eq_mapping +
6093                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6094                 elem->next_page.addr.lo =
6095                         cpu_to_le32(U64_LO(bp->eq_mapping +
6096                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6097         }
6098         bp->eq_cons = 0;
6099         bp->eq_prod = NUM_EQ_DESC;
6100         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6101         /* we want a warning message before it gets wrought... */
6102         atomic_set(&bp->eq_spq_left,
6103                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6104 }
6105
6106 /* called with netif_addr_lock_bh() */
6107 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6108                                unsigned long rx_mode_flags,
6109                                unsigned long rx_accept_flags,
6110                                unsigned long tx_accept_flags,
6111                                unsigned long ramrod_flags)
6112 {
6113         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6114         int rc;
6115
6116         memset(&ramrod_param, 0, sizeof(ramrod_param));
6117
6118         /* Prepare ramrod parameters */
6119         ramrod_param.cid = 0;
6120         ramrod_param.cl_id = cl_id;
6121         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6122         ramrod_param.func_id = BP_FUNC(bp);
6123
6124         ramrod_param.pstate = &bp->sp_state;
6125         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6126
6127         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6128         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6129
6130         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6131
6132         ramrod_param.ramrod_flags = ramrod_flags;
6133         ramrod_param.rx_mode_flags = rx_mode_flags;
6134
6135         ramrod_param.rx_accept_flags = rx_accept_flags;
6136         ramrod_param.tx_accept_flags = tx_accept_flags;
6137
6138         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6139         if (rc < 0) {
6140                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6141                 return rc;
6142         }
6143
6144         return 0;
6145 }
6146
6147 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6148                                    unsigned long *rx_accept_flags,
6149                                    unsigned long *tx_accept_flags)
6150 {
6151         /* Clear the flags first */
6152         *rx_accept_flags = 0;
6153         *tx_accept_flags = 0;
6154
6155         switch (rx_mode) {
6156         case BNX2X_RX_MODE_NONE:
6157                 /*
6158                  * 'drop all' supersedes any accept flags that may have been
6159                  * passed to the function.
6160                  */
6161                 break;
6162         case BNX2X_RX_MODE_NORMAL:
6163                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6164                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6165                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6166
6167                 /* internal switching mode */
6168                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6169                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6170                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6171
6172                 break;
6173         case BNX2X_RX_MODE_ALLMULTI:
6174                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6175                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6176                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6177
6178                 /* internal switching mode */
6179                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6180                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6181                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6182
6183                 break;
6184         case BNX2X_RX_MODE_PROMISC:
6185                 /* According to definition of SI mode, iface in promisc mode
6186                  * should receive matched and unmatched (in resolution of port)
6187                  * unicast packets.
6188                  */
6189                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6190                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6191                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6192                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6193
6194                 /* internal switching mode */
6195                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6196                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6197
6198                 if (IS_MF_SI(bp))
6199                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6200                 else
6201                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6202
6203                 break;
6204         default:
6205                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6206                 return -EINVAL;
6207         }
6208
6209         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6210         if (rx_mode != BNX2X_RX_MODE_NONE) {
6211                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6212                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6213         }
6214
6215         return 0;
6216 }
6217
6218 /* called with netif_addr_lock_bh() */
6219 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6220 {
6221         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6222         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6223         int rc;
6224
6225         if (!NO_FCOE(bp))
6226                 /* Configure rx_mode of FCoE Queue */
6227                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6228
6229         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6230                                      &tx_accept_flags);
6231         if (rc)
6232                 return rc;
6233
6234         __set_bit(RAMROD_RX, &ramrod_flags);
6235         __set_bit(RAMROD_TX, &ramrod_flags);
6236
6237         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6238                                    rx_accept_flags, tx_accept_flags,
6239                                    ramrod_flags);
6240 }
6241
6242 static void bnx2x_init_internal_common(struct bnx2x *bp)
6243 {
6244         int i;
6245
6246         /* Zero this manually as its initialization is
6247            currently missing in the initTool */
6248         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6249                 REG_WR(bp, BAR_USTRORM_INTMEM +
6250                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6251         if (!CHIP_IS_E1x(bp)) {
6252                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6253                         CHIP_INT_MODE_IS_BC(bp) ?
6254                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6255         }
6256 }
6257
6258 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6259 {
6260         switch (load_code) {
6261         case FW_MSG_CODE_DRV_LOAD_COMMON:
6262         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6263                 bnx2x_init_internal_common(bp);
6264                 /* no break */
6265
6266         case FW_MSG_CODE_DRV_LOAD_PORT:
6267                 /* nothing to do */
6268                 /* no break */
6269
6270         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6271                 /* internal memory per function is
6272                    initialized inside bnx2x_pf_init */
6273                 break;
6274
6275         default:
6276                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6277                 break;
6278         }
6279 }
6280
6281 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6282 {
6283         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6284 }
6285
6286 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6287 {
6288         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6289 }
6290
6291 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6292 {
6293         if (CHIP_IS_E1x(fp->bp))
6294                 return BP_L_ID(fp->bp) + fp->index;
6295         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6296                 return bnx2x_fp_igu_sb_id(fp);
6297 }
6298
6299 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6300 {
6301         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6302         u8 cos;
6303         unsigned long q_type = 0;
6304         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6305         fp->rx_queue = fp_idx;
6306         fp->cid = fp_idx;
6307         fp->cl_id = bnx2x_fp_cl_id(fp);
6308         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6309         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6310         /* qZone id equals to FW (per path) client id */
6311         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6312
6313         /* init shortcut */
6314         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6315
6316         /* Setup SB indices */
6317         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6318
6319         /* Configure Queue State object */
6320         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6321         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6322
6323         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6324
6325         /* init tx data */
6326         for_each_cos_in_tx_queue(fp, cos) {
6327                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6328                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6329                                   FP_COS_TO_TXQ(fp, cos, bp),
6330                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6331                 cids[cos] = fp->txdata_ptr[cos]->cid;
6332         }
6333
6334         /* nothing more for vf to do here */
6335         if (IS_VF(bp))
6336                 return;
6337
6338         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6339                       fp->fw_sb_id, fp->igu_sb_id);
6340         bnx2x_update_fpsb_idx(fp);
6341         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6342                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6343                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6344
6345         /**
6346          * Configure classification DBs: Always enable Tx switching
6347          */
6348         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6349
6350         DP(NETIF_MSG_IFUP,
6351            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6352            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6353            fp->igu_sb_id);
6354 }
6355
6356 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6357 {
6358         int i;
6359
6360         for (i = 1; i <= NUM_TX_RINGS; i++) {
6361                 struct eth_tx_next_bd *tx_next_bd =
6362                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6363
6364                 tx_next_bd->addr_hi =
6365                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6366                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6367                 tx_next_bd->addr_lo =
6368                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6369                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6370         }
6371
6372         *txdata->tx_cons_sb = cpu_to_le16(0);
6373
6374         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6375         txdata->tx_db.data.zero_fill1 = 0;
6376         txdata->tx_db.data.prod = 0;
6377
6378         txdata->tx_pkt_prod = 0;
6379         txdata->tx_pkt_cons = 0;
6380         txdata->tx_bd_prod = 0;
6381         txdata->tx_bd_cons = 0;
6382         txdata->tx_pkt = 0;
6383 }
6384
6385 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6386 {
6387         int i;
6388
6389         for_each_tx_queue_cnic(bp, i)
6390                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6391 }
6392
6393 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6394 {
6395         int i;
6396         u8 cos;
6397
6398         for_each_eth_queue(bp, i)
6399                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6400                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6401 }
6402
6403 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6404 {
6405         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6406         unsigned long q_type = 0;
6407
6408         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6409         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6410                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6411         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6412         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6413         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6414         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6415         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6416                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6417                           fp);
6418
6419         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6420
6421         /* qZone id equals to FW (per path) client id */
6422         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6423         /* init shortcut */
6424         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6425                 bnx2x_rx_ustorm_prods_offset(fp);
6426
6427         /* Configure Queue State object */
6428         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6429         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6430
6431         /* No multi-CoS for FCoE L2 client */
6432         BUG_ON(fp->max_cos != 1);
6433
6434         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6435                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6436                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6437
6438         DP(NETIF_MSG_IFUP,
6439            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6440            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6441            fp->igu_sb_id);
6442 }
6443
6444 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6445 {
6446         if (!NO_FCOE(bp))
6447                 bnx2x_init_fcoe_fp(bp);
6448
6449         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6450                       BNX2X_VF_ID_INVALID, false,
6451                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6452
6453         /* ensure status block indices were read */
6454         rmb();
6455         bnx2x_init_rx_rings_cnic(bp);
6456         bnx2x_init_tx_rings_cnic(bp);
6457
6458         /* flush all */
6459         mb();
6460         mmiowb();
6461 }
6462
6463 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6464 {
6465         int i;
6466
6467         /* Setup NIC internals and enable interrupts */
6468         for_each_eth_queue(bp, i)
6469                 bnx2x_init_eth_fp(bp, i);
6470
6471         /* ensure status block indices were read */
6472         rmb();
6473         bnx2x_init_rx_rings(bp);
6474         bnx2x_init_tx_rings(bp);
6475
6476         if (IS_PF(bp)) {
6477                 /* Initialize MOD_ABS interrupts */
6478                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6479                                        bp->common.shmem_base,
6480                                        bp->common.shmem2_base, BP_PORT(bp));
6481
6482                 /* initialize the default status block and sp ring */
6483                 bnx2x_init_def_sb(bp);
6484                 bnx2x_update_dsb_idx(bp);
6485                 bnx2x_init_sp_ring(bp);
6486         } else {
6487                 bnx2x_memset_stats(bp);
6488         }
6489 }
6490
6491 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6492 {
6493         bnx2x_init_eq_ring(bp);
6494         bnx2x_init_internal(bp, load_code);
6495         bnx2x_pf_init(bp);
6496         bnx2x_stats_init(bp);
6497
6498         /* flush all before enabling interrupts */
6499         mb();
6500         mmiowb();
6501
6502         bnx2x_int_enable(bp);
6503
6504         /* Check for SPIO5 */
6505         bnx2x_attn_int_deasserted0(bp,
6506                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6507                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6508 }
6509
6510 /* gzip service functions */
6511 static int bnx2x_gunzip_init(struct bnx2x *bp)
6512 {
6513         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6514                                             &bp->gunzip_mapping, GFP_KERNEL);
6515         if (bp->gunzip_buf  == NULL)
6516                 goto gunzip_nomem1;
6517
6518         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6519         if (bp->strm  == NULL)
6520                 goto gunzip_nomem2;
6521
6522         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6523         if (bp->strm->workspace == NULL)
6524                 goto gunzip_nomem3;
6525
6526         return 0;
6527
6528 gunzip_nomem3:
6529         kfree(bp->strm);
6530         bp->strm = NULL;
6531
6532 gunzip_nomem2:
6533         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6534                           bp->gunzip_mapping);
6535         bp->gunzip_buf = NULL;
6536
6537 gunzip_nomem1:
6538         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6539         return -ENOMEM;
6540 }
6541
6542 static void bnx2x_gunzip_end(struct bnx2x *bp)
6543 {
6544         if (bp->strm) {
6545                 vfree(bp->strm->workspace);
6546                 kfree(bp->strm);
6547                 bp->strm = NULL;
6548         }
6549
6550         if (bp->gunzip_buf) {
6551                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6552                                   bp->gunzip_mapping);
6553                 bp->gunzip_buf = NULL;
6554         }
6555 }
6556
6557 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6558 {
6559         int n, rc;
6560
6561         /* check gzip header */
6562         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6563                 BNX2X_ERR("Bad gzip header\n");
6564                 return -EINVAL;
6565         }
6566
6567         n = 10;
6568
6569 #define FNAME                           0x8
6570
6571         if (zbuf[3] & FNAME)
6572                 while ((zbuf[n++] != 0) && (n < len));
6573
6574         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6575         bp->strm->avail_in = len - n;
6576         bp->strm->next_out = bp->gunzip_buf;
6577         bp->strm->avail_out = FW_BUF_SIZE;
6578
6579         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6580         if (rc != Z_OK)
6581                 return rc;
6582
6583         rc = zlib_inflate(bp->strm, Z_FINISH);
6584         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6585                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6586                            bp->strm->msg);
6587
6588         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6589         if (bp->gunzip_outlen & 0x3)
6590                 netdev_err(bp->dev,
6591                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6592                                 bp->gunzip_outlen);
6593         bp->gunzip_outlen >>= 2;
6594
6595         zlib_inflateEnd(bp->strm);
6596
6597         if (rc == Z_STREAM_END)
6598                 return 0;
6599
6600         return rc;
6601 }
6602
6603 /* nic load/unload */
6604
6605 /*
6606  * General service functions
6607  */
6608
6609 /* send a NIG loopback debug packet */
6610 static void bnx2x_lb_pckt(struct bnx2x *bp)
6611 {
6612         u32 wb_write[3];
6613
6614         /* Ethernet source and destination addresses */
6615         wb_write[0] = 0x55555555;
6616         wb_write[1] = 0x55555555;
6617         wb_write[2] = 0x20;             /* SOP */
6618         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6619
6620         /* NON-IP protocol */
6621         wb_write[0] = 0x09000000;
6622         wb_write[1] = 0x55555555;
6623         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6624         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6625 }
6626
6627 /* some of the internal memories
6628  * are not directly readable from the driver
6629  * to test them we send debug packets
6630  */
6631 static int bnx2x_int_mem_test(struct bnx2x *bp)
6632 {
6633         int factor;
6634         int count, i;
6635         u32 val = 0;
6636
6637         if (CHIP_REV_IS_FPGA(bp))
6638                 factor = 120;
6639         else if (CHIP_REV_IS_EMUL(bp))
6640                 factor = 200;
6641         else
6642                 factor = 1;
6643
6644         /* Disable inputs of parser neighbor blocks */
6645         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6646         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6647         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6648         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6649
6650         /*  Write 0 to parser credits for CFC search request */
6651         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6652
6653         /* send Ethernet packet */
6654         bnx2x_lb_pckt(bp);
6655
6656         /* TODO do i reset NIG statistic? */
6657         /* Wait until NIG register shows 1 packet of size 0x10 */
6658         count = 1000 * factor;
6659         while (count) {
6660
6661                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6662                 val = *bnx2x_sp(bp, wb_data[0]);
6663                 if (val == 0x10)
6664                         break;
6665
6666                 usleep_range(10000, 20000);
6667                 count--;
6668         }
6669         if (val != 0x10) {
6670                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6671                 return -1;
6672         }
6673
6674         /* Wait until PRS register shows 1 packet */
6675         count = 1000 * factor;
6676         while (count) {
6677                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6678                 if (val == 1)
6679                         break;
6680
6681                 usleep_range(10000, 20000);
6682                 count--;
6683         }
6684         if (val != 0x1) {
6685                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6686                 return -2;
6687         }
6688
6689         /* Reset and init BRB, PRS */
6690         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6691         msleep(50);
6692         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6693         msleep(50);
6694         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6695         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6696
6697         DP(NETIF_MSG_HW, "part2\n");
6698
6699         /* Disable inputs of parser neighbor blocks */
6700         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6701         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6702         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6703         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6704
6705         /* Write 0 to parser credits for CFC search request */
6706         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6707
6708         /* send 10 Ethernet packets */
6709         for (i = 0; i < 10; i++)
6710                 bnx2x_lb_pckt(bp);
6711
6712         /* Wait until NIG register shows 10 + 1
6713            packets of size 11*0x10 = 0xb0 */
6714         count = 1000 * factor;
6715         while (count) {
6716
6717                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6718                 val = *bnx2x_sp(bp, wb_data[0]);
6719                 if (val == 0xb0)
6720                         break;
6721
6722                 usleep_range(10000, 20000);
6723                 count--;
6724         }
6725         if (val != 0xb0) {
6726                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6727                 return -3;
6728         }
6729
6730         /* Wait until PRS register shows 2 packets */
6731         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6732         if (val != 2)
6733                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6734
6735         /* Write 1 to parser credits for CFC search request */
6736         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6737
6738         /* Wait until PRS register shows 3 packets */
6739         msleep(10 * factor);
6740         /* Wait until NIG register shows 1 packet of size 0x10 */
6741         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6742         if (val != 3)
6743                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6744
6745         /* clear NIG EOP FIFO */
6746         for (i = 0; i < 11; i++)
6747                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6748         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6749         if (val != 1) {
6750                 BNX2X_ERR("clear of NIG failed\n");
6751                 return -4;
6752         }
6753
6754         /* Reset and init BRB, PRS, NIG */
6755         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6756         msleep(50);
6757         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6758         msleep(50);
6759         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6760         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6761         if (!CNIC_SUPPORT(bp))
6762                 /* set NIC mode */
6763                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6764
6765         /* Enable inputs of parser neighbor blocks */
6766         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6767         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6768         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6769         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6770
6771         DP(NETIF_MSG_HW, "done\n");
6772
6773         return 0; /* OK */
6774 }
6775
6776 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6777 {
6778         u32 val;
6779
6780         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6781         if (!CHIP_IS_E1x(bp))
6782                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6783         else
6784                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6785         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6786         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6787         /*
6788          * mask read length error interrupts in brb for parser
6789          * (parsing unit and 'checksum and crc' unit)
6790          * these errors are legal (PU reads fixed length and CAC can cause
6791          * read length error on truncated packets)
6792          */
6793         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6794         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6795         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6796         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6797         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6798         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6799 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6800 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6801         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6802         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6803         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6804 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6805 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6806         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6807         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6808         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6809         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6810 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6811 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6812
6813         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6814                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6815                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6816         if (!CHIP_IS_E1x(bp))
6817                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6818                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6819         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6820
6821         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6822         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6823         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6824 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6825
6826         if (!CHIP_IS_E1x(bp))
6827                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6828                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6829
6830         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6831         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6832 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6833         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6834 }
6835
6836 static void bnx2x_reset_common(struct bnx2x *bp)
6837 {
6838         u32 val = 0x1400;
6839
6840         /* reset_common */
6841         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6842                0xd3ffff7f);
6843
6844         if (CHIP_IS_E3(bp)) {
6845                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6846                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6847         }
6848
6849         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6850 }
6851
6852 static void bnx2x_setup_dmae(struct bnx2x *bp)
6853 {
6854         bp->dmae_ready = 0;
6855         spin_lock_init(&bp->dmae_lock);
6856 }
6857
6858 static void bnx2x_init_pxp(struct bnx2x *bp)
6859 {
6860         u16 devctl;
6861         int r_order, w_order;
6862
6863         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6864         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6865         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6866         if (bp->mrrs == -1)
6867                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6868         else {
6869                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6870                 r_order = bp->mrrs;
6871         }
6872
6873         bnx2x_init_pxp_arb(bp, r_order, w_order);
6874 }
6875
6876 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6877 {
6878         int is_required;
6879         u32 val;
6880         int port;
6881
6882         if (BP_NOMCP(bp))
6883                 return;
6884
6885         is_required = 0;
6886         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6887               SHARED_HW_CFG_FAN_FAILURE_MASK;
6888
6889         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6890                 is_required = 1;
6891
6892         /*
6893          * The fan failure mechanism is usually related to the PHY type since
6894          * the power consumption of the board is affected by the PHY. Currently,
6895          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6896          */
6897         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6898                 for (port = PORT_0; port < PORT_MAX; port++) {
6899                         is_required |=
6900                                 bnx2x_fan_failure_det_req(
6901                                         bp,
6902                                         bp->common.shmem_base,
6903                                         bp->common.shmem2_base,
6904                                         port);
6905                 }
6906
6907         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6908
6909         if (is_required == 0)
6910                 return;
6911
6912         /* Fan failure is indicated by SPIO 5 */
6913         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6914
6915         /* set to active low mode */
6916         val = REG_RD(bp, MISC_REG_SPIO_INT);
6917         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6918         REG_WR(bp, MISC_REG_SPIO_INT, val);
6919
6920         /* enable interrupt to signal the IGU */
6921         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6922         val |= MISC_SPIO_SPIO5;
6923         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6924 }
6925
6926 void bnx2x_pf_disable(struct bnx2x *bp)
6927 {
6928         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6929         val &= ~IGU_PF_CONF_FUNC_EN;
6930
6931         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6932         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6933         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6934 }
6935
6936 static void bnx2x__common_init_phy(struct bnx2x *bp)
6937 {
6938         u32 shmem_base[2], shmem2_base[2];
6939         /* Avoid common init in case MFW supports LFA */
6940         if (SHMEM2_RD(bp, size) >
6941             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6942                 return;
6943         shmem_base[0] =  bp->common.shmem_base;
6944         shmem2_base[0] = bp->common.shmem2_base;
6945         if (!CHIP_IS_E1x(bp)) {
6946                 shmem_base[1] =
6947                         SHMEM2_RD(bp, other_shmem_base_addr);
6948                 shmem2_base[1] =
6949                         SHMEM2_RD(bp, other_shmem2_base_addr);
6950         }
6951         bnx2x_acquire_phy_lock(bp);
6952         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6953                               bp->common.chip_id);
6954         bnx2x_release_phy_lock(bp);
6955 }
6956
6957 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6958 {
6959         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6960         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6961         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6962         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6963         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6964
6965         /* make sure this value is 0 */
6966         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6967
6968         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
6969         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
6970         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
6971         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
6972 }
6973
6974 static void bnx2x_set_endianity(struct bnx2x *bp)
6975 {
6976 #ifdef __BIG_ENDIAN
6977         bnx2x_config_endianity(bp, 1);
6978 #else
6979         bnx2x_config_endianity(bp, 0);
6980 #endif
6981 }
6982
6983 static void bnx2x_reset_endianity(struct bnx2x *bp)
6984 {
6985         bnx2x_config_endianity(bp, 0);
6986 }
6987
6988 /**
6989  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6990  *
6991  * @bp:         driver handle
6992  */
6993 static int bnx2x_init_hw_common(struct bnx2x *bp)
6994 {
6995         u32 val;
6996
6997         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6998
6999         /*
7000          * take the RESET lock to protect undi_unload flow from accessing
7001          * registers while we're resetting the chip
7002          */
7003         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7004
7005         bnx2x_reset_common(bp);
7006         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7007
7008         val = 0xfffc;
7009         if (CHIP_IS_E3(bp)) {
7010                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7011                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7012         }
7013         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7014
7015         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7016
7017         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7018
7019         if (!CHIP_IS_E1x(bp)) {
7020                 u8 abs_func_id;
7021
7022                 /**
7023                  * 4-port mode or 2-port mode we need to turn of master-enable
7024                  * for everyone, after that, turn it back on for self.
7025                  * so, we disregard multi-function or not, and always disable
7026                  * for all functions on the given path, this means 0,2,4,6 for
7027                  * path 0 and 1,3,5,7 for path 1
7028                  */
7029                 for (abs_func_id = BP_PATH(bp);
7030                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7031                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7032                                 REG_WR(bp,
7033                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7034                                     1);
7035                                 continue;
7036                         }
7037
7038                         bnx2x_pretend_func(bp, abs_func_id);
7039                         /* clear pf enable */
7040                         bnx2x_pf_disable(bp);
7041                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7042                 }
7043         }
7044
7045         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7046         if (CHIP_IS_E1(bp)) {
7047                 /* enable HW interrupt from PXP on USDM overflow
7048                    bit 16 on INT_MASK_0 */
7049                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7050         }
7051
7052         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7053         bnx2x_init_pxp(bp);
7054         bnx2x_set_endianity(bp);
7055         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7056
7057         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7058                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7059
7060         /* let the HW do it's magic ... */
7061         msleep(100);
7062         /* finish PXP init */
7063         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7064         if (val != 1) {
7065                 BNX2X_ERR("PXP2 CFG failed\n");
7066                 return -EBUSY;
7067         }
7068         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7069         if (val != 1) {
7070                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7071                 return -EBUSY;
7072         }
7073
7074         /* Timers bug workaround E2 only. We need to set the entire ILT to
7075          * have entries with value "0" and valid bit on.
7076          * This needs to be done by the first PF that is loaded in a path
7077          * (i.e. common phase)
7078          */
7079         if (!CHIP_IS_E1x(bp)) {
7080 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7081  * (i.e. vnic3) to start even if it is marked as "scan-off".
7082  * This occurs when a different function (func2,3) is being marked
7083  * as "scan-off". Real-life scenario for example: if a driver is being
7084  * load-unloaded while func6,7 are down. This will cause the timer to access
7085  * the ilt, translate to a logical address and send a request to read/write.
7086  * Since the ilt for the function that is down is not valid, this will cause
7087  * a translation error which is unrecoverable.
7088  * The Workaround is intended to make sure that when this happens nothing fatal
7089  * will occur. The workaround:
7090  *      1.  First PF driver which loads on a path will:
7091  *              a.  After taking the chip out of reset, by using pretend,
7092  *                  it will write "0" to the following registers of
7093  *                  the other vnics.
7094  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7095  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7096  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7097  *                  And for itself it will write '1' to
7098  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7099  *                  dmae-operations (writing to pram for example.)
7100  *                  note: can be done for only function 6,7 but cleaner this
7101  *                        way.
7102  *              b.  Write zero+valid to the entire ILT.
7103  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7104  *                  VNIC3 (of that port). The range allocated will be the
7105  *                  entire ILT. This is needed to prevent  ILT range error.
7106  *      2.  Any PF driver load flow:
7107  *              a.  ILT update with the physical addresses of the allocated
7108  *                  logical pages.
7109  *              b.  Wait 20msec. - note that this timeout is needed to make
7110  *                  sure there are no requests in one of the PXP internal
7111  *                  queues with "old" ILT addresses.
7112  *              c.  PF enable in the PGLC.
7113  *              d.  Clear the was_error of the PF in the PGLC. (could have
7114  *                  occurred while driver was down)
7115  *              e.  PF enable in the CFC (WEAK + STRONG)
7116  *              f.  Timers scan enable
7117  *      3.  PF driver unload flow:
7118  *              a.  Clear the Timers scan_en.
7119  *              b.  Polling for scan_on=0 for that PF.
7120  *              c.  Clear the PF enable bit in the PXP.
7121  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7122  *              e.  Write zero+valid to all ILT entries (The valid bit must
7123  *                  stay set)
7124  *              f.  If this is VNIC 3 of a port then also init
7125  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7126  *                  to the last entry in the ILT.
7127  *
7128  *      Notes:
7129  *      Currently the PF error in the PGLC is non recoverable.
7130  *      In the future the there will be a recovery routine for this error.
7131  *      Currently attention is masked.
7132  *      Having an MCP lock on the load/unload process does not guarantee that
7133  *      there is no Timer disable during Func6/7 enable. This is because the
7134  *      Timers scan is currently being cleared by the MCP on FLR.
7135  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7136  *      there is error before clearing it. But the flow above is simpler and
7137  *      more general.
7138  *      All ILT entries are written by zero+valid and not just PF6/7
7139  *      ILT entries since in the future the ILT entries allocation for
7140  *      PF-s might be dynamic.
7141  */
7142                 struct ilt_client_info ilt_cli;
7143                 struct bnx2x_ilt ilt;
7144                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7145                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7146
7147                 /* initialize dummy TM client */
7148                 ilt_cli.start = 0;
7149                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7150                 ilt_cli.client_num = ILT_CLIENT_TM;
7151
7152                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7153                  * Step 2: set the timers first/last ilt entry to point
7154                  * to the entire range to prevent ILT range error for 3rd/4th
7155                  * vnic (this code assumes existence of the vnic)
7156                  *
7157                  * both steps performed by call to bnx2x_ilt_client_init_op()
7158                  * with dummy TM client
7159                  *
7160                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7161                  * and his brother are split registers
7162                  */
7163                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7164                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7165                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7166
7167                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7168                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7169                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7170         }
7171
7172         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7173         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7174
7175         if (!CHIP_IS_E1x(bp)) {
7176                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7177                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7178                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7179
7180                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7181
7182                 /* let the HW do it's magic ... */
7183                 do {
7184                         msleep(200);
7185                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7186                 } while (factor-- && (val != 1));
7187
7188                 if (val != 1) {
7189                         BNX2X_ERR("ATC_INIT failed\n");
7190                         return -EBUSY;
7191                 }
7192         }
7193
7194         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7195
7196         bnx2x_iov_init_dmae(bp);
7197
7198         /* clean the DMAE memory */
7199         bp->dmae_ready = 1;
7200         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7201
7202         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7203
7204         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7205
7206         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7207
7208         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7209
7210         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7211         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7212         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7213         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7214
7215         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7216
7217         /* QM queues pointers table */
7218         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7219
7220         /* soft reset pulse */
7221         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7222         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7223
7224         if (CNIC_SUPPORT(bp))
7225                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7226
7227         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7228
7229         if (!CHIP_REV_IS_SLOW(bp))
7230                 /* enable hw interrupt from doorbell Q */
7231                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7232
7233         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7234
7235         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7236         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7237
7238         if (!CHIP_IS_E1(bp))
7239                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7240
7241         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7242                 if (IS_MF_AFEX(bp)) {
7243                         /* configure that VNTag and VLAN headers must be
7244                          * received in afex mode
7245                          */
7246                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7247                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7248                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7249                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7250                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7251                 } else {
7252                         /* Bit-map indicating which L2 hdrs may appear
7253                          * after the basic Ethernet header
7254                          */
7255                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7256                                bp->path_has_ovlan ? 7 : 6);
7257                 }
7258         }
7259
7260         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7261         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7262         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7263         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7264
7265         if (!CHIP_IS_E1x(bp)) {
7266                 /* reset VFC memories */
7267                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7268                            VFC_MEMORIES_RST_REG_CAM_RST |
7269                            VFC_MEMORIES_RST_REG_RAM_RST);
7270                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7271                            VFC_MEMORIES_RST_REG_CAM_RST |
7272                            VFC_MEMORIES_RST_REG_RAM_RST);
7273
7274                 msleep(20);
7275         }
7276
7277         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7278         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7279         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7280         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7281
7282         /* sync semi rtc */
7283         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7284                0x80000000);
7285         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7286                0x80000000);
7287
7288         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7289         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7290         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7291
7292         if (!CHIP_IS_E1x(bp)) {
7293                 if (IS_MF_AFEX(bp)) {
7294                         /* configure that VNTag and VLAN headers must be
7295                          * sent in afex mode
7296                          */
7297                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7298                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7299                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7300                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7301                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7302                 } else {
7303                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7304                                bp->path_has_ovlan ? 7 : 6);
7305                 }
7306         }
7307
7308         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7309
7310         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7311
7312         if (CNIC_SUPPORT(bp)) {
7313                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7314                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7315                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7316                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7317                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7318                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7319                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7320                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7321                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7322                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7323         }
7324         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7325
7326         if (sizeof(union cdu_context) != 1024)
7327                 /* we currently assume that a context is 1024 bytes */
7328                 dev_alert(&bp->pdev->dev,
7329                           "please adjust the size of cdu_context(%ld)\n",
7330                           (long)sizeof(union cdu_context));
7331
7332         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7333         val = (4 << 24) + (0 << 12) + 1024;
7334         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7335
7336         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7337         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7338         /* enable context validation interrupt from CFC */
7339         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7340
7341         /* set the thresholds to prevent CFC/CDU race */
7342         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7343
7344         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7345
7346         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7347                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7348
7349         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7350         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7351
7352         /* Reset PCIE errors for debug */
7353         REG_WR(bp, 0x2814, 0xffffffff);
7354         REG_WR(bp, 0x3820, 0xffffffff);
7355
7356         if (!CHIP_IS_E1x(bp)) {
7357                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7358                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7359                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7360                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7361                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7362                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7363                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7364                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7365                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7366                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7367                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7368         }
7369
7370         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7371         if (!CHIP_IS_E1(bp)) {
7372                 /* in E3 this done in per-port section */
7373                 if (!CHIP_IS_E3(bp))
7374                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7375         }
7376         if (CHIP_IS_E1H(bp))
7377                 /* not applicable for E2 (and above ...) */
7378                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7379
7380         if (CHIP_REV_IS_SLOW(bp))
7381                 msleep(200);
7382
7383         /* finish CFC init */
7384         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7385         if (val != 1) {
7386                 BNX2X_ERR("CFC LL_INIT failed\n");
7387                 return -EBUSY;
7388         }
7389         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7390         if (val != 1) {
7391                 BNX2X_ERR("CFC AC_INIT failed\n");
7392                 return -EBUSY;
7393         }
7394         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7395         if (val != 1) {
7396                 BNX2X_ERR("CFC CAM_INIT failed\n");
7397                 return -EBUSY;
7398         }
7399         REG_WR(bp, CFC_REG_DEBUG0, 0);
7400
7401         if (CHIP_IS_E1(bp)) {
7402                 /* read NIG statistic
7403                    to see if this is our first up since powerup */
7404                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7405                 val = *bnx2x_sp(bp, wb_data[0]);
7406
7407                 /* do internal memory self test */
7408                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7409                         BNX2X_ERR("internal mem self test failed\n");
7410                         return -EBUSY;
7411                 }
7412         }
7413
7414         bnx2x_setup_fan_failure_detection(bp);
7415
7416         /* clear PXP2 attentions */
7417         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7418
7419         bnx2x_enable_blocks_attention(bp);
7420         bnx2x_enable_blocks_parity(bp);
7421
7422         if (!BP_NOMCP(bp)) {
7423                 if (CHIP_IS_E1x(bp))
7424                         bnx2x__common_init_phy(bp);
7425         } else
7426                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7427
7428         return 0;
7429 }
7430
7431 /**
7432  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7433  *
7434  * @bp:         driver handle
7435  */
7436 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7437 {
7438         int rc = bnx2x_init_hw_common(bp);
7439
7440         if (rc)
7441                 return rc;
7442
7443         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7444         if (!BP_NOMCP(bp))
7445                 bnx2x__common_init_phy(bp);
7446
7447         return 0;
7448 }
7449
7450 static int bnx2x_init_hw_port(struct bnx2x *bp)
7451 {
7452         int port = BP_PORT(bp);
7453         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7454         u32 low, high;
7455         u32 val, reg;
7456
7457         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7458
7459         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7460
7461         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7462         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7463         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7464
7465         /* Timers bug workaround: disables the pf_master bit in pglue at
7466          * common phase, we need to enable it here before any dmae access are
7467          * attempted. Therefore we manually added the enable-master to the
7468          * port phase (it also happens in the function phase)
7469          */
7470         if (!CHIP_IS_E1x(bp))
7471                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7472
7473         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7474         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7475         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7476         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7477
7478         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7479         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7480         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7481         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7482
7483         /* QM cid (connection) count */
7484         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7485
7486         if (CNIC_SUPPORT(bp)) {
7487                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7488                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7489                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7490         }
7491
7492         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7493
7494         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7495
7496         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7497
7498                 if (IS_MF(bp))
7499                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7500                 else if (bp->dev->mtu > 4096) {
7501                         if (bp->flags & ONE_PORT_FLAG)
7502                                 low = 160;
7503                         else {
7504                                 val = bp->dev->mtu;
7505                                 /* (24*1024 + val*4)/256 */
7506                                 low = 96 + (val/64) +
7507                                                 ((val % 64) ? 1 : 0);
7508                         }
7509                 } else
7510                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7511                 high = low + 56;        /* 14*1024/256 */
7512                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7513                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7514         }
7515
7516         if (CHIP_MODE_IS_4_PORT(bp))
7517                 REG_WR(bp, (BP_PORT(bp) ?
7518                             BRB1_REG_MAC_GUARANTIED_1 :
7519                             BRB1_REG_MAC_GUARANTIED_0), 40);
7520
7521         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7522         if (CHIP_IS_E3B0(bp)) {
7523                 if (IS_MF_AFEX(bp)) {
7524                         /* configure headers for AFEX mode */
7525                         REG_WR(bp, BP_PORT(bp) ?
7526                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7527                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7528                         REG_WR(bp, BP_PORT(bp) ?
7529                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7530                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7531                         REG_WR(bp, BP_PORT(bp) ?
7532                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7533                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7534                 } else {
7535                         /* Ovlan exists only if we are in multi-function +
7536                          * switch-dependent mode, in switch-independent there
7537                          * is no ovlan headers
7538                          */
7539                         REG_WR(bp, BP_PORT(bp) ?
7540                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7541                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7542                                (bp->path_has_ovlan ? 7 : 6));
7543                 }
7544         }
7545
7546         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7547         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7548         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7549         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7550
7551         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7552         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7553         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7554         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7555
7556         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7557         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7558
7559         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7560
7561         if (CHIP_IS_E1x(bp)) {
7562                 /* configure PBF to work without PAUSE mtu 9000 */
7563                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7564
7565                 /* update threshold */
7566                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7567                 /* update init credit */
7568                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7569
7570                 /* probe changes */
7571                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7572                 udelay(50);
7573                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7574         }
7575
7576         if (CNIC_SUPPORT(bp))
7577                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7578
7579         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7580         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7581
7582         if (CHIP_IS_E1(bp)) {
7583                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7584                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7585         }
7586         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7587
7588         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7589
7590         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7591         /* init aeu_mask_attn_func_0/1:
7592          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7593          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7594          *             bits 4-7 are used for "per vn group attention" */
7595         val = IS_MF(bp) ? 0xF7 : 0x7;
7596         /* Enable DCBX attention for all but E1 */
7597         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7598         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7599
7600         /* SCPAD_PARITY should NOT trigger close the gates */
7601         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7602         REG_WR(bp, reg,
7603                REG_RD(bp, reg) &
7604                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7605
7606         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7607         REG_WR(bp, reg,
7608                REG_RD(bp, reg) &
7609                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7610
7611         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7612
7613         if (!CHIP_IS_E1x(bp)) {
7614                 /* Bit-map indicating which L2 hdrs may appear after the
7615                  * basic Ethernet header
7616                  */
7617                 if (IS_MF_AFEX(bp))
7618                         REG_WR(bp, BP_PORT(bp) ?
7619                                NIG_REG_P1_HDRS_AFTER_BASIC :
7620                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7621                 else
7622                         REG_WR(bp, BP_PORT(bp) ?
7623                                NIG_REG_P1_HDRS_AFTER_BASIC :
7624                                NIG_REG_P0_HDRS_AFTER_BASIC,
7625                                IS_MF_SD(bp) ? 7 : 6);
7626
7627                 if (CHIP_IS_E3(bp))
7628                         REG_WR(bp, BP_PORT(bp) ?
7629                                    NIG_REG_LLH1_MF_MODE :
7630                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7631         }
7632         if (!CHIP_IS_E3(bp))
7633                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7634
7635         if (!CHIP_IS_E1(bp)) {
7636                 /* 0x2 disable mf_ov, 0x1 enable */
7637                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7638                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7639
7640                 if (!CHIP_IS_E1x(bp)) {
7641                         val = 0;
7642                         switch (bp->mf_mode) {
7643                         case MULTI_FUNCTION_SD:
7644                                 val = 1;
7645                                 break;
7646                         case MULTI_FUNCTION_SI:
7647                         case MULTI_FUNCTION_AFEX:
7648                                 val = 2;
7649                                 break;
7650                         }
7651
7652                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7653                                                   NIG_REG_LLH0_CLS_TYPE), val);
7654                 }
7655                 {
7656                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7657                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7658                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7659                 }
7660         }
7661
7662         /* If SPIO5 is set to generate interrupts, enable it for this port */
7663         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7664         if (val & MISC_SPIO_SPIO5) {
7665                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7666                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7667                 val = REG_RD(bp, reg_addr);
7668                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7669                 REG_WR(bp, reg_addr, val);
7670         }
7671
7672         return 0;
7673 }
7674
7675 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7676 {
7677         int reg;
7678         u32 wb_write[2];
7679
7680         if (CHIP_IS_E1(bp))
7681                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7682         else
7683                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7684
7685         wb_write[0] = ONCHIP_ADDR1(addr);
7686         wb_write[1] = ONCHIP_ADDR2(addr);
7687         REG_WR_DMAE(bp, reg, wb_write, 2);
7688 }
7689
7690 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7691 {
7692         u32 data, ctl, cnt = 100;
7693         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7694         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7695         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7696         u32 sb_bit =  1 << (idu_sb_id%32);
7697         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7698         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7699
7700         /* Not supported in BC mode */
7701         if (CHIP_INT_MODE_IS_BC(bp))
7702                 return;
7703
7704         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7705                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7706                 IGU_REGULAR_CLEANUP_SET                         |
7707                 IGU_REGULAR_BCLEANUP;
7708
7709         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7710               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7711               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7712
7713         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7714                          data, igu_addr_data);
7715         REG_WR(bp, igu_addr_data, data);
7716         mmiowb();
7717         barrier();
7718         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7719                           ctl, igu_addr_ctl);
7720         REG_WR(bp, igu_addr_ctl, ctl);
7721         mmiowb();
7722         barrier();
7723
7724         /* wait for clean up to finish */
7725         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7726                 msleep(20);
7727
7728         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7729                 DP(NETIF_MSG_HW,
7730                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7731                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7732         }
7733 }
7734
7735 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7736 {
7737         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7738 }
7739
7740 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7741 {
7742         u32 i, base = FUNC_ILT_BASE(func);
7743         for (i = base; i < base + ILT_PER_FUNC; i++)
7744                 bnx2x_ilt_wr(bp, i, 0);
7745 }
7746
7747 static void bnx2x_init_searcher(struct bnx2x *bp)
7748 {
7749         int port = BP_PORT(bp);
7750         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7751         /* T1 hash bits value determines the T1 number of entries */
7752         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7753 }
7754
7755 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7756 {
7757         int rc;
7758         struct bnx2x_func_state_params func_params = {NULL};
7759         struct bnx2x_func_switch_update_params *switch_update_params =
7760                 &func_params.params.switch_update;
7761
7762         /* Prepare parameters for function state transitions */
7763         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7764         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7765
7766         func_params.f_obj = &bp->func_obj;
7767         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7768
7769         /* Function parameters */
7770         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7771                   &switch_update_params->changes);
7772         if (suspend)
7773                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7774                           &switch_update_params->changes);
7775
7776         rc = bnx2x_func_state_change(bp, &func_params);
7777
7778         return rc;
7779 }
7780
7781 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7782 {
7783         int rc, i, port = BP_PORT(bp);
7784         int vlan_en = 0, mac_en[NUM_MACS];
7785
7786         /* Close input from network */
7787         if (bp->mf_mode == SINGLE_FUNCTION) {
7788                 bnx2x_set_rx_filter(&bp->link_params, 0);
7789         } else {
7790                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7791                                    NIG_REG_LLH0_FUNC_EN);
7792                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7793                           NIG_REG_LLH0_FUNC_EN, 0);
7794                 for (i = 0; i < NUM_MACS; i++) {
7795                         mac_en[i] = REG_RD(bp, port ?
7796                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7797                                               4 * i) :
7798                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7799                                               4 * i));
7800                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7801                                               4 * i) :
7802                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7803                 }
7804         }
7805
7806         /* Close BMC to host */
7807         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7808                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7809
7810         /* Suspend Tx switching to the PF. Completion of this ramrod
7811          * further guarantees that all the packets of that PF / child
7812          * VFs in BRB were processed by the Parser, so it is safe to
7813          * change the NIC_MODE register.
7814          */
7815         rc = bnx2x_func_switch_update(bp, 1);
7816         if (rc) {
7817                 BNX2X_ERR("Can't suspend tx-switching!\n");
7818                 return rc;
7819         }
7820
7821         /* Change NIC_MODE register */
7822         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7823
7824         /* Open input from network */
7825         if (bp->mf_mode == SINGLE_FUNCTION) {
7826                 bnx2x_set_rx_filter(&bp->link_params, 1);
7827         } else {
7828                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7829                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7830                 for (i = 0; i < NUM_MACS; i++) {
7831                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7832                                               4 * i) :
7833                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7834                                   mac_en[i]);
7835                 }
7836         }
7837
7838         /* Enable BMC to host */
7839         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7840                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7841
7842         /* Resume Tx switching to the PF */
7843         rc = bnx2x_func_switch_update(bp, 0);
7844         if (rc) {
7845                 BNX2X_ERR("Can't resume tx-switching!\n");
7846                 return rc;
7847         }
7848
7849         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7850         return 0;
7851 }
7852
7853 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7854 {
7855         int rc;
7856
7857         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7858
7859         if (CONFIGURE_NIC_MODE(bp)) {
7860                 /* Configure searcher as part of function hw init */
7861                 bnx2x_init_searcher(bp);
7862
7863                 /* Reset NIC mode */
7864                 rc = bnx2x_reset_nic_mode(bp);
7865                 if (rc)
7866                         BNX2X_ERR("Can't change NIC mode!\n");
7867                 return rc;
7868         }
7869
7870         return 0;
7871 }
7872
7873 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7874  * and boot began, or when kdump kernel was loaded. Either case would invalidate
7875  * the addresses of the transaction, resulting in was-error bit set in the pci
7876  * causing all hw-to-host pcie transactions to timeout. If this happened we want
7877  * to clear the interrupt which detected this from the pglueb and the was done
7878  * bit
7879  */
7880 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7881 {
7882         if (!CHIP_IS_E1x(bp))
7883                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7884                        1 << BP_ABS_FUNC(bp));
7885 }
7886
7887 static int bnx2x_init_hw_func(struct bnx2x *bp)
7888 {
7889         int port = BP_PORT(bp);
7890         int func = BP_FUNC(bp);
7891         int init_phase = PHASE_PF0 + func;
7892         struct bnx2x_ilt *ilt = BP_ILT(bp);
7893         u16 cdu_ilt_start;
7894         u32 addr, val;
7895         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7896         int i, main_mem_width, rc;
7897
7898         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7899
7900         /* FLR cleanup - hmmm */
7901         if (!CHIP_IS_E1x(bp)) {
7902                 rc = bnx2x_pf_flr_clnup(bp);
7903                 if (rc) {
7904                         bnx2x_fw_dump(bp);
7905                         return rc;
7906                 }
7907         }
7908
7909         /* set MSI reconfigure capability */
7910         if (bp->common.int_block == INT_BLOCK_HC) {
7911                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7912                 val = REG_RD(bp, addr);
7913                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7914                 REG_WR(bp, addr, val);
7915         }
7916
7917         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7918         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7919
7920         ilt = BP_ILT(bp);
7921         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7922
7923         if (IS_SRIOV(bp))
7924                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7925         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7926
7927         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7928          * those of the VFs, so start line should be reset
7929          */
7930         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7931         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7932                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7933                 ilt->lines[cdu_ilt_start + i].page_mapping =
7934                         bp->context[i].cxt_mapping;
7935                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7936         }
7937
7938         bnx2x_ilt_init_op(bp, INITOP_SET);
7939
7940         if (!CONFIGURE_NIC_MODE(bp)) {
7941                 bnx2x_init_searcher(bp);
7942                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7943                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7944         } else {
7945                 /* Set NIC mode */
7946                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7947                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7948         }
7949
7950         if (!CHIP_IS_E1x(bp)) {
7951                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7952
7953                 /* Turn on a single ISR mode in IGU if driver is going to use
7954                  * INT#x or MSI
7955                  */
7956                 if (!(bp->flags & USING_MSIX_FLAG))
7957                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7958                 /*
7959                  * Timers workaround bug: function init part.
7960                  * Need to wait 20msec after initializing ILT,
7961                  * needed to make sure there are no requests in
7962                  * one of the PXP internal queues with "old" ILT addresses
7963                  */
7964                 msleep(20);
7965                 /*
7966                  * Master enable - Due to WB DMAE writes performed before this
7967                  * register is re-initialized as part of the regular function
7968                  * init
7969                  */
7970                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7971                 /* Enable the function in IGU */
7972                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7973         }
7974
7975         bp->dmae_ready = 1;
7976
7977         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7978
7979         bnx2x_clean_pglue_errors(bp);
7980
7981         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7982         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7983         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7984         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7985         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7986         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7987         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7988         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7989         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7990         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7991         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7992         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7993         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7994
7995         if (!CHIP_IS_E1x(bp))
7996                 REG_WR(bp, QM_REG_PF_EN, 1);
7997
7998         if (!CHIP_IS_E1x(bp)) {
7999                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8000                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8001                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8002                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8003         }
8004         bnx2x_init_block(bp, BLOCK_QM, init_phase);
8005
8006         bnx2x_init_block(bp, BLOCK_TM, init_phase);
8007         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8008         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8009
8010         bnx2x_iov_init_dq(bp);
8011
8012         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8013         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8014         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8015         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8016         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8017         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8018         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8019         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8020         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8021         if (!CHIP_IS_E1x(bp))
8022                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8023
8024         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8025
8026         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8027
8028         if (!CHIP_IS_E1x(bp))
8029                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8030
8031         if (IS_MF(bp)) {
8032                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8033                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8034                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8035                                bp->mf_ov);
8036                 }
8037         }
8038
8039         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8040
8041         /* HC init per function */
8042         if (bp->common.int_block == INT_BLOCK_HC) {
8043                 if (CHIP_IS_E1H(bp)) {
8044                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8045
8046                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8047                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8048                 }
8049                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8050
8051         } else {
8052                 int num_segs, sb_idx, prod_offset;
8053
8054                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8055
8056                 if (!CHIP_IS_E1x(bp)) {
8057                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8058                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8059                 }
8060
8061                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8062
8063                 if (!CHIP_IS_E1x(bp)) {
8064                         int dsb_idx = 0;
8065                         /**
8066                          * Producer memory:
8067                          * E2 mode: address 0-135 match to the mapping memory;
8068                          * 136 - PF0 default prod; 137 - PF1 default prod;
8069                          * 138 - PF2 default prod; 139 - PF3 default prod;
8070                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8071                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8072                          * 144-147 reserved.
8073                          *
8074                          * E1.5 mode - In backward compatible mode;
8075                          * for non default SB; each even line in the memory
8076                          * holds the U producer and each odd line hold
8077                          * the C producer. The first 128 producers are for
8078                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8079                          * producers are for the DSB for each PF.
8080                          * Each PF has five segments: (the order inside each
8081                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8082                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8083                          * 144-147 attn prods;
8084                          */
8085                         /* non-default-status-blocks */
8086                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8087                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8088                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8089                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8090                                         num_segs;
8091
8092                                 for (i = 0; i < num_segs; i++) {
8093                                         addr = IGU_REG_PROD_CONS_MEMORY +
8094                                                         (prod_offset + i) * 4;
8095                                         REG_WR(bp, addr, 0);
8096                                 }
8097                                 /* send consumer update with value 0 */
8098                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8099                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8100                                 bnx2x_igu_clear_sb(bp,
8101                                                    bp->igu_base_sb + sb_idx);
8102                         }
8103
8104                         /* default-status-blocks */
8105                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8106                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8107
8108                         if (CHIP_MODE_IS_4_PORT(bp))
8109                                 dsb_idx = BP_FUNC(bp);
8110                         else
8111                                 dsb_idx = BP_VN(bp);
8112
8113                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8114                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8115                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8116
8117                         /*
8118                          * igu prods come in chunks of E1HVN_MAX (4) -
8119                          * does not matters what is the current chip mode
8120                          */
8121                         for (i = 0; i < (num_segs * E1HVN_MAX);
8122                              i += E1HVN_MAX) {
8123                                 addr = IGU_REG_PROD_CONS_MEMORY +
8124                                                         (prod_offset + i)*4;
8125                                 REG_WR(bp, addr, 0);
8126                         }
8127                         /* send consumer update with 0 */
8128                         if (CHIP_INT_MODE_IS_BC(bp)) {
8129                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8130                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8131                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8132                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8133                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8134                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8135                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8136                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8137                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8138                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8139                         } else {
8140                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8141                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8142                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8143                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8144                         }
8145                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8146
8147                         /* !!! These should become driver const once
8148                            rf-tool supports split-68 const */
8149                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8150                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8151                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8152                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8153                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8154                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8155                 }
8156         }
8157
8158         /* Reset PCIE errors for debug */
8159         REG_WR(bp, 0x2114, 0xffffffff);
8160         REG_WR(bp, 0x2120, 0xffffffff);
8161
8162         if (CHIP_IS_E1x(bp)) {
8163                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8164                 main_mem_base = HC_REG_MAIN_MEMORY +
8165                                 BP_PORT(bp) * (main_mem_size * 4);
8166                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8167                 main_mem_width = 8;
8168
8169                 val = REG_RD(bp, main_mem_prty_clr);
8170                 if (val)
8171                         DP(NETIF_MSG_HW,
8172                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8173                            val);
8174
8175                 /* Clear "false" parity errors in MSI-X table */
8176                 for (i = main_mem_base;
8177                      i < main_mem_base + main_mem_size * 4;
8178                      i += main_mem_width) {
8179                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8180                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8181                                          i, main_mem_width / 4);
8182                 }
8183                 /* Clear HC parity attention */
8184                 REG_RD(bp, main_mem_prty_clr);
8185         }
8186
8187 #ifdef BNX2X_STOP_ON_ERROR
8188         /* Enable STORMs SP logging */
8189         REG_WR8(bp, BAR_USTRORM_INTMEM +
8190                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8191         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8192                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8193         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8194                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8195         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8196                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8197 #endif
8198
8199         bnx2x_phy_probe(&bp->link_params);
8200
8201         return 0;
8202 }
8203
8204 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8205 {
8206         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8207
8208         if (!CHIP_IS_E1x(bp))
8209                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8210                                sizeof(struct host_hc_status_block_e2));
8211         else
8212                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8213                                sizeof(struct host_hc_status_block_e1x));
8214
8215         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8216 }
8217
8218 void bnx2x_free_mem(struct bnx2x *bp)
8219 {
8220         int i;
8221
8222         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8223                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8224
8225         if (IS_VF(bp))
8226                 return;
8227
8228         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8229                        sizeof(struct host_sp_status_block));
8230
8231         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8232                        sizeof(struct bnx2x_slowpath));
8233
8234         for (i = 0; i < L2_ILT_LINES(bp); i++)
8235                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8236                                bp->context[i].size);
8237         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8238
8239         BNX2X_FREE(bp->ilt->lines);
8240
8241         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8242
8243         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8244                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8245
8246         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8247
8248         bnx2x_iov_free_mem(bp);
8249 }
8250
8251 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8252 {
8253         if (!CHIP_IS_E1x(bp)) {
8254                 /* size = the status block + ramrod buffers */
8255                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8256                                                     sizeof(struct host_hc_status_block_e2));
8257                 if (!bp->cnic_sb.e2_sb)
8258                         goto alloc_mem_err;
8259         } else {
8260                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8261                                                      sizeof(struct host_hc_status_block_e1x));
8262                 if (!bp->cnic_sb.e1x_sb)
8263                         goto alloc_mem_err;
8264         }
8265
8266         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8267                 /* allocate searcher T2 table, as it wasn't allocated before */
8268                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8269                 if (!bp->t2)
8270                         goto alloc_mem_err;
8271         }
8272
8273         /* write address to which L5 should insert its values */
8274         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8275                 &bp->slowpath->drv_info_to_mcp;
8276
8277         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8278                 goto alloc_mem_err;
8279
8280         return 0;
8281
8282 alloc_mem_err:
8283         bnx2x_free_mem_cnic(bp);
8284         BNX2X_ERR("Can't allocate memory\n");
8285         return -ENOMEM;
8286 }
8287
8288 int bnx2x_alloc_mem(struct bnx2x *bp)
8289 {
8290         int i, allocated, context_size;
8291
8292         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8293                 /* allocate searcher T2 table */
8294                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8295                 if (!bp->t2)
8296                         goto alloc_mem_err;
8297         }
8298
8299         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8300                                              sizeof(struct host_sp_status_block));
8301         if (!bp->def_status_blk)
8302                 goto alloc_mem_err;
8303
8304         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8305                                        sizeof(struct bnx2x_slowpath));
8306         if (!bp->slowpath)
8307                 goto alloc_mem_err;
8308
8309         /* Allocate memory for CDU context:
8310          * This memory is allocated separately and not in the generic ILT
8311          * functions because CDU differs in few aspects:
8312          * 1. There are multiple entities allocating memory for context -
8313          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8314          * its own ILT lines.
8315          * 2. Since CDU page-size is not a single 4KB page (which is the case
8316          * for the other ILT clients), to be efficient we want to support
8317          * allocation of sub-page-size in the last entry.
8318          * 3. Context pointers are used by the driver to pass to FW / update
8319          * the context (for the other ILT clients the pointers are used just to
8320          * free the memory during unload).
8321          */
8322         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8323
8324         for (i = 0, allocated = 0; allocated < context_size; i++) {
8325                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8326                                           (context_size - allocated));
8327                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8328                                                       bp->context[i].size);
8329                 if (!bp->context[i].vcxt)
8330                         goto alloc_mem_err;
8331                 allocated += bp->context[i].size;
8332         }
8333         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8334                                  GFP_KERNEL);
8335         if (!bp->ilt->lines)
8336                 goto alloc_mem_err;
8337
8338         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8339                 goto alloc_mem_err;
8340
8341         if (bnx2x_iov_alloc_mem(bp))
8342                 goto alloc_mem_err;
8343
8344         /* Slow path ring */
8345         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8346         if (!bp->spq)
8347                 goto alloc_mem_err;
8348
8349         /* EQ */
8350         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8351                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8352         if (!bp->eq_ring)
8353                 goto alloc_mem_err;
8354
8355         return 0;
8356
8357 alloc_mem_err:
8358         bnx2x_free_mem(bp);
8359         BNX2X_ERR("Can't allocate memory\n");
8360         return -ENOMEM;
8361 }
8362
8363 /*
8364  * Init service functions
8365  */
8366
8367 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8368                       struct bnx2x_vlan_mac_obj *obj, bool set,
8369                       int mac_type, unsigned long *ramrod_flags)
8370 {
8371         int rc;
8372         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8373
8374         memset(&ramrod_param, 0, sizeof(ramrod_param));
8375
8376         /* Fill general parameters */
8377         ramrod_param.vlan_mac_obj = obj;
8378         ramrod_param.ramrod_flags = *ramrod_flags;
8379
8380         /* Fill a user request section if needed */
8381         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8382                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8383
8384                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8385
8386                 /* Set the command: ADD or DEL */
8387                 if (set)
8388                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8389                 else
8390                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8391         }
8392
8393         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8394
8395         if (rc == -EEXIST) {
8396                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8397                 /* do not treat adding same MAC as error */
8398                 rc = 0;
8399         } else if (rc < 0)
8400                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8401
8402         return rc;
8403 }
8404
8405 int bnx2x_del_all_macs(struct bnx2x *bp,
8406                        struct bnx2x_vlan_mac_obj *mac_obj,
8407                        int mac_type, bool wait_for_comp)
8408 {
8409         int rc;
8410         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8411
8412         /* Wait for completion of requested */
8413         if (wait_for_comp)
8414                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8415
8416         /* Set the mac type of addresses we want to clear */
8417         __set_bit(mac_type, &vlan_mac_flags);
8418
8419         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8420         if (rc < 0)
8421                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8422
8423         return rc;
8424 }
8425
8426 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8427 {
8428         if (IS_PF(bp)) {
8429                 unsigned long ramrod_flags = 0;
8430
8431                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8432                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8433                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8434                                          &bp->sp_objs->mac_obj, set,
8435                                          BNX2X_ETH_MAC, &ramrod_flags);
8436         } else { /* vf */
8437                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8438                                              bp->fp->index, true);
8439         }
8440 }
8441
8442 int bnx2x_setup_leading(struct bnx2x *bp)
8443 {
8444         if (IS_PF(bp))
8445                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8446         else /* VF */
8447                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8448 }
8449
8450 /**
8451  * bnx2x_set_int_mode - configure interrupt mode
8452  *
8453  * @bp:         driver handle
8454  *
8455  * In case of MSI-X it will also try to enable MSI-X.
8456  */
8457 int bnx2x_set_int_mode(struct bnx2x *bp)
8458 {
8459         int rc = 0;
8460
8461         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8462                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8463                 return -EINVAL;
8464         }
8465
8466         switch (int_mode) {
8467         case BNX2X_INT_MODE_MSIX:
8468                 /* attempt to enable msix */
8469                 rc = bnx2x_enable_msix(bp);
8470
8471                 /* msix attained */
8472                 if (!rc)
8473                         return 0;
8474
8475                 /* vfs use only msix */
8476                 if (rc && IS_VF(bp))
8477                         return rc;
8478
8479                 /* failed to enable multiple MSI-X */
8480                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8481                                bp->num_queues,
8482                                1 + bp->num_cnic_queues);
8483
8484                 /* falling through... */
8485         case BNX2X_INT_MODE_MSI:
8486                 bnx2x_enable_msi(bp);
8487
8488                 /* falling through... */
8489         case BNX2X_INT_MODE_INTX:
8490                 bp->num_ethernet_queues = 1;
8491                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8492                 BNX2X_DEV_INFO("set number of queues to 1\n");
8493                 break;
8494         default:
8495                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8496                 return -EINVAL;
8497         }
8498         return 0;
8499 }
8500
8501 /* must be called prior to any HW initializations */
8502 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8503 {
8504         if (IS_SRIOV(bp))
8505                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8506         return L2_ILT_LINES(bp);
8507 }
8508
8509 void bnx2x_ilt_set_info(struct bnx2x *bp)
8510 {
8511         struct ilt_client_info *ilt_client;
8512         struct bnx2x_ilt *ilt = BP_ILT(bp);
8513         u16 line = 0;
8514
8515         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8516         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8517
8518         /* CDU */
8519         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8520         ilt_client->client_num = ILT_CLIENT_CDU;
8521         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8522         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8523         ilt_client->start = line;
8524         line += bnx2x_cid_ilt_lines(bp);
8525
8526         if (CNIC_SUPPORT(bp))
8527                 line += CNIC_ILT_LINES;
8528         ilt_client->end = line - 1;
8529
8530         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8531            ilt_client->start,
8532            ilt_client->end,
8533            ilt_client->page_size,
8534            ilt_client->flags,
8535            ilog2(ilt_client->page_size >> 12));
8536
8537         /* QM */
8538         if (QM_INIT(bp->qm_cid_count)) {
8539                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8540                 ilt_client->client_num = ILT_CLIENT_QM;
8541                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8542                 ilt_client->flags = 0;
8543                 ilt_client->start = line;
8544
8545                 /* 4 bytes for each cid */
8546                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8547                                                          QM_ILT_PAGE_SZ);
8548
8549                 ilt_client->end = line - 1;
8550
8551                 DP(NETIF_MSG_IFUP,
8552                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8553                    ilt_client->start,
8554                    ilt_client->end,
8555                    ilt_client->page_size,
8556                    ilt_client->flags,
8557                    ilog2(ilt_client->page_size >> 12));
8558         }
8559
8560         if (CNIC_SUPPORT(bp)) {
8561                 /* SRC */
8562                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8563                 ilt_client->client_num = ILT_CLIENT_SRC;
8564                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8565                 ilt_client->flags = 0;
8566                 ilt_client->start = line;
8567                 line += SRC_ILT_LINES;
8568                 ilt_client->end = line - 1;
8569
8570                 DP(NETIF_MSG_IFUP,
8571                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8572                    ilt_client->start,
8573                    ilt_client->end,
8574                    ilt_client->page_size,
8575                    ilt_client->flags,
8576                    ilog2(ilt_client->page_size >> 12));
8577
8578                 /* TM */
8579                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8580                 ilt_client->client_num = ILT_CLIENT_TM;
8581                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8582                 ilt_client->flags = 0;
8583                 ilt_client->start = line;
8584                 line += TM_ILT_LINES;
8585                 ilt_client->end = line - 1;
8586
8587                 DP(NETIF_MSG_IFUP,
8588                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8589                    ilt_client->start,
8590                    ilt_client->end,
8591                    ilt_client->page_size,
8592                    ilt_client->flags,
8593                    ilog2(ilt_client->page_size >> 12));
8594         }
8595
8596         BUG_ON(line > ILT_MAX_LINES);
8597 }
8598
8599 /**
8600  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8601  *
8602  * @bp:                 driver handle
8603  * @fp:                 pointer to fastpath
8604  * @init_params:        pointer to parameters structure
8605  *
8606  * parameters configured:
8607  *      - HC configuration
8608  *      - Queue's CDU context
8609  */
8610 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8611         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8612 {
8613         u8 cos;
8614         int cxt_index, cxt_offset;
8615
8616         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8617         if (!IS_FCOE_FP(fp)) {
8618                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8619                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8620
8621                 /* If HC is supported, enable host coalescing in the transition
8622                  * to INIT state.
8623                  */
8624                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8625                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8626
8627                 /* HC rate */
8628                 init_params->rx.hc_rate = bp->rx_ticks ?
8629                         (1000000 / bp->rx_ticks) : 0;
8630                 init_params->tx.hc_rate = bp->tx_ticks ?
8631                         (1000000 / bp->tx_ticks) : 0;
8632
8633                 /* FW SB ID */
8634                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8635                         fp->fw_sb_id;
8636
8637                 /*
8638                  * CQ index among the SB indices: FCoE clients uses the default
8639                  * SB, therefore it's different.
8640                  */
8641                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8642                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8643         }
8644
8645         /* set maximum number of COSs supported by this queue */
8646         init_params->max_cos = fp->max_cos;
8647
8648         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8649             fp->index, init_params->max_cos);
8650
8651         /* set the context pointers queue object */
8652         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8653                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8654                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8655                                 ILT_PAGE_CIDS);
8656                 init_params->cxts[cos] =
8657                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8658         }
8659 }
8660
8661 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8662                         struct bnx2x_queue_state_params *q_params,
8663                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8664                         int tx_index, bool leading)
8665 {
8666         memset(tx_only_params, 0, sizeof(*tx_only_params));
8667
8668         /* Set the command */
8669         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8670
8671         /* Set tx-only QUEUE flags: don't zero statistics */
8672         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8673
8674         /* choose the index of the cid to send the slow path on */
8675         tx_only_params->cid_index = tx_index;
8676
8677         /* Set general TX_ONLY_SETUP parameters */
8678         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8679
8680         /* Set Tx TX_ONLY_SETUP parameters */
8681         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8682
8683         DP(NETIF_MSG_IFUP,
8684            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8685            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8686            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8687            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8688
8689         /* send the ramrod */
8690         return bnx2x_queue_state_change(bp, q_params);
8691 }
8692
8693 /**
8694  * bnx2x_setup_queue - setup queue
8695  *
8696  * @bp:         driver handle
8697  * @fp:         pointer to fastpath
8698  * @leading:    is leading
8699  *
8700  * This function performs 2 steps in a Queue state machine
8701  *      actually: 1) RESET->INIT 2) INIT->SETUP
8702  */
8703
8704 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8705                        bool leading)
8706 {
8707         struct bnx2x_queue_state_params q_params = {NULL};
8708         struct bnx2x_queue_setup_params *setup_params =
8709                                                 &q_params.params.setup;
8710         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8711                                                 &q_params.params.tx_only;
8712         int rc;
8713         u8 tx_index;
8714
8715         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8716
8717         /* reset IGU state skip FCoE L2 queue */
8718         if (!IS_FCOE_FP(fp))
8719                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8720                              IGU_INT_ENABLE, 0);
8721
8722         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8723         /* We want to wait for completion in this context */
8724         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8725
8726         /* Prepare the INIT parameters */
8727         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8728
8729         /* Set the command */
8730         q_params.cmd = BNX2X_Q_CMD_INIT;
8731
8732         /* Change the state to INIT */
8733         rc = bnx2x_queue_state_change(bp, &q_params);
8734         if (rc) {
8735                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8736                 return rc;
8737         }
8738
8739         DP(NETIF_MSG_IFUP, "init complete\n");
8740
8741         /* Now move the Queue to the SETUP state... */
8742         memset(setup_params, 0, sizeof(*setup_params));
8743
8744         /* Set QUEUE flags */
8745         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8746
8747         /* Set general SETUP parameters */
8748         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8749                                 FIRST_TX_COS_INDEX);
8750
8751         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8752                             &setup_params->rxq_params);
8753
8754         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8755                            FIRST_TX_COS_INDEX);
8756
8757         /* Set the command */
8758         q_params.cmd = BNX2X_Q_CMD_SETUP;
8759
8760         if (IS_FCOE_FP(fp))
8761                 bp->fcoe_init = true;
8762
8763         /* Change the state to SETUP */
8764         rc = bnx2x_queue_state_change(bp, &q_params);
8765         if (rc) {
8766                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8767                 return rc;
8768         }
8769
8770         /* loop through the relevant tx-only indices */
8771         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8772               tx_index < fp->max_cos;
8773               tx_index++) {
8774
8775                 /* prepare and send tx-only ramrod*/
8776                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8777                                           tx_only_params, tx_index, leading);
8778                 if (rc) {
8779                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8780                                   fp->index, tx_index);
8781                         return rc;
8782                 }
8783         }
8784
8785         return rc;
8786 }
8787
8788 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8789 {
8790         struct bnx2x_fastpath *fp = &bp->fp[index];
8791         struct bnx2x_fp_txdata *txdata;
8792         struct bnx2x_queue_state_params q_params = {NULL};
8793         int rc, tx_index;
8794
8795         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8796
8797         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8798         /* We want to wait for completion in this context */
8799         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8800
8801         /* close tx-only connections */
8802         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8803              tx_index < fp->max_cos;
8804              tx_index++){
8805
8806                 /* ascertain this is a normal queue*/
8807                 txdata = fp->txdata_ptr[tx_index];
8808
8809                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8810                                                         txdata->txq_index);
8811
8812                 /* send halt terminate on tx-only connection */
8813                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8814                 memset(&q_params.params.terminate, 0,
8815                        sizeof(q_params.params.terminate));
8816                 q_params.params.terminate.cid_index = tx_index;
8817
8818                 rc = bnx2x_queue_state_change(bp, &q_params);
8819                 if (rc)
8820                         return rc;
8821
8822                 /* send halt terminate on tx-only connection */
8823                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8824                 memset(&q_params.params.cfc_del, 0,
8825                        sizeof(q_params.params.cfc_del));
8826                 q_params.params.cfc_del.cid_index = tx_index;
8827                 rc = bnx2x_queue_state_change(bp, &q_params);
8828                 if (rc)
8829                         return rc;
8830         }
8831         /* Stop the primary connection: */
8832         /* ...halt the connection */
8833         q_params.cmd = BNX2X_Q_CMD_HALT;
8834         rc = bnx2x_queue_state_change(bp, &q_params);
8835         if (rc)
8836                 return rc;
8837
8838         /* ...terminate the connection */
8839         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8840         memset(&q_params.params.terminate, 0,
8841                sizeof(q_params.params.terminate));
8842         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8843         rc = bnx2x_queue_state_change(bp, &q_params);
8844         if (rc)
8845                 return rc;
8846         /* ...delete cfc entry */
8847         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8848         memset(&q_params.params.cfc_del, 0,
8849                sizeof(q_params.params.cfc_del));
8850         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8851         return bnx2x_queue_state_change(bp, &q_params);
8852 }
8853
8854 static void bnx2x_reset_func(struct bnx2x *bp)
8855 {
8856         int port = BP_PORT(bp);
8857         int func = BP_FUNC(bp);
8858         int i;
8859
8860         /* Disable the function in the FW */
8861         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8862         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8863         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8864         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8865
8866         /* FP SBs */
8867         for_each_eth_queue(bp, i) {
8868                 struct bnx2x_fastpath *fp = &bp->fp[i];
8869                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8870                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8871                            SB_DISABLED);
8872         }
8873
8874         if (CNIC_LOADED(bp))
8875                 /* CNIC SB */
8876                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8877                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8878                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8879
8880         /* SP SB */
8881         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8882                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8883                 SB_DISABLED);
8884
8885         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8886                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8887                        0);
8888
8889         /* Configure IGU */
8890         if (bp->common.int_block == INT_BLOCK_HC) {
8891                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8892                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8893         } else {
8894                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8895                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8896         }
8897
8898         if (CNIC_LOADED(bp)) {
8899                 /* Disable Timer scan */
8900                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8901                 /*
8902                  * Wait for at least 10ms and up to 2 second for the timers
8903                  * scan to complete
8904                  */
8905                 for (i = 0; i < 200; i++) {
8906                         usleep_range(10000, 20000);
8907                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8908                                 break;
8909                 }
8910         }
8911         /* Clear ILT */
8912         bnx2x_clear_func_ilt(bp, func);
8913
8914         /* Timers workaround bug for E2: if this is vnic-3,
8915          * we need to set the entire ilt range for this timers.
8916          */
8917         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8918                 struct ilt_client_info ilt_cli;
8919                 /* use dummy TM client */
8920                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8921                 ilt_cli.start = 0;
8922                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8923                 ilt_cli.client_num = ILT_CLIENT_TM;
8924
8925                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8926         }
8927
8928         /* this assumes that reset_port() called before reset_func()*/
8929         if (!CHIP_IS_E1x(bp))
8930                 bnx2x_pf_disable(bp);
8931
8932         bp->dmae_ready = 0;
8933 }
8934
8935 static void bnx2x_reset_port(struct bnx2x *bp)
8936 {
8937         int port = BP_PORT(bp);
8938         u32 val;
8939
8940         /* Reset physical Link */
8941         bnx2x__link_reset(bp);
8942
8943         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8944
8945         /* Do not rcv packets to BRB */
8946         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8947         /* Do not direct rcv packets that are not for MCP to the BRB */
8948         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8949                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8950
8951         /* Configure AEU */
8952         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8953
8954         msleep(100);
8955         /* Check for BRB port occupancy */
8956         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8957         if (val)
8958                 DP(NETIF_MSG_IFDOWN,
8959                    "BRB1 is not empty  %d blocks are occupied\n", val);
8960
8961         /* TODO: Close Doorbell port? */
8962 }
8963
8964 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8965 {
8966         struct bnx2x_func_state_params func_params = {NULL};
8967
8968         /* Prepare parameters for function state transitions */
8969         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8970
8971         func_params.f_obj = &bp->func_obj;
8972         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8973
8974         func_params.params.hw_init.load_phase = load_code;
8975
8976         return bnx2x_func_state_change(bp, &func_params);
8977 }
8978
8979 static int bnx2x_func_stop(struct bnx2x *bp)
8980 {
8981         struct bnx2x_func_state_params func_params = {NULL};
8982         int rc;
8983
8984         /* Prepare parameters for function state transitions */
8985         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8986         func_params.f_obj = &bp->func_obj;
8987         func_params.cmd = BNX2X_F_CMD_STOP;
8988
8989         /*
8990          * Try to stop the function the 'good way'. If fails (in case
8991          * of a parity error during bnx2x_chip_cleanup()) and we are
8992          * not in a debug mode, perform a state transaction in order to
8993          * enable further HW_RESET transaction.
8994          */
8995         rc = bnx2x_func_state_change(bp, &func_params);
8996         if (rc) {
8997 #ifdef BNX2X_STOP_ON_ERROR
8998                 return rc;
8999 #else
9000                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9001                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9002                 return bnx2x_func_state_change(bp, &func_params);
9003 #endif
9004         }
9005
9006         return 0;
9007 }
9008
9009 /**
9010  * bnx2x_send_unload_req - request unload mode from the MCP.
9011  *
9012  * @bp:                 driver handle
9013  * @unload_mode:        requested function's unload mode
9014  *
9015  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9016  */
9017 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9018 {
9019         u32 reset_code = 0;
9020         int port = BP_PORT(bp);
9021
9022         /* Select the UNLOAD request mode */
9023         if (unload_mode == UNLOAD_NORMAL)
9024                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9025
9026         else if (bp->flags & NO_WOL_FLAG)
9027                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9028
9029         else if (bp->wol) {
9030                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9031                 u8 *mac_addr = bp->dev->dev_addr;
9032                 struct pci_dev *pdev = bp->pdev;
9033                 u32 val;
9034                 u16 pmc;
9035
9036                 /* The mac address is written to entries 1-4 to
9037                  * preserve entry 0 which is used by the PMF
9038                  */
9039                 u8 entry = (BP_VN(bp) + 1)*8;
9040
9041                 val = (mac_addr[0] << 8) | mac_addr[1];
9042                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9043
9044                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9045                       (mac_addr[4] << 8) | mac_addr[5];
9046                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9047
9048                 /* Enable the PME and clear the status */
9049                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9050                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9051                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9052
9053                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9054
9055         } else
9056                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9057
9058         /* Send the request to the MCP */
9059         if (!BP_NOMCP(bp))
9060                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9061         else {
9062                 int path = BP_PATH(bp);
9063
9064                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9065                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9066                    bnx2x_load_count[path][2]);
9067                 bnx2x_load_count[path][0]--;
9068                 bnx2x_load_count[path][1 + port]--;
9069                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9070                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9071                    bnx2x_load_count[path][2]);
9072                 if (bnx2x_load_count[path][0] == 0)
9073                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9074                 else if (bnx2x_load_count[path][1 + port] == 0)
9075                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9076                 else
9077                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9078         }
9079
9080         return reset_code;
9081 }
9082
9083 /**
9084  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9085  *
9086  * @bp:         driver handle
9087  * @keep_link:          true iff link should be kept up
9088  */
9089 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9090 {
9091         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9092
9093         /* Report UNLOAD_DONE to MCP */
9094         if (!BP_NOMCP(bp))
9095                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9096 }
9097
9098 static int bnx2x_func_wait_started(struct bnx2x *bp)
9099 {
9100         int tout = 50;
9101         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9102
9103         if (!bp->port.pmf)
9104                 return 0;
9105
9106         /*
9107          * (assumption: No Attention from MCP at this stage)
9108          * PMF probably in the middle of TX disable/enable transaction
9109          * 1. Sync IRS for default SB
9110          * 2. Sync SP queue - this guarantees us that attention handling started
9111          * 3. Wait, that TX disable/enable transaction completes
9112          *
9113          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9114          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9115          * received completion for the transaction the state is TX_STOPPED.
9116          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9117          * transaction.
9118          */
9119
9120         /* make sure default SB ISR is done */
9121         if (msix)
9122                 synchronize_irq(bp->msix_table[0].vector);
9123         else
9124                 synchronize_irq(bp->pdev->irq);
9125
9126         flush_workqueue(bnx2x_wq);
9127         flush_workqueue(bnx2x_iov_wq);
9128
9129         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9130                                 BNX2X_F_STATE_STARTED && tout--)
9131                 msleep(20);
9132
9133         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9134                                                 BNX2X_F_STATE_STARTED) {
9135 #ifdef BNX2X_STOP_ON_ERROR
9136                 BNX2X_ERR("Wrong function state\n");
9137                 return -EBUSY;
9138 #else
9139                 /*
9140                  * Failed to complete the transaction in a "good way"
9141                  * Force both transactions with CLR bit
9142                  */
9143                 struct bnx2x_func_state_params func_params = {NULL};
9144
9145                 DP(NETIF_MSG_IFDOWN,
9146                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9147
9148                 func_params.f_obj = &bp->func_obj;
9149                 __set_bit(RAMROD_DRV_CLR_ONLY,
9150                                         &func_params.ramrod_flags);
9151
9152                 /* STARTED-->TX_ST0PPED */
9153                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9154                 bnx2x_func_state_change(bp, &func_params);
9155
9156                 /* TX_ST0PPED-->STARTED */
9157                 func_params.cmd = BNX2X_F_CMD_TX_START;
9158                 return bnx2x_func_state_change(bp, &func_params);
9159 #endif
9160         }
9161
9162         return 0;
9163 }
9164
9165 static void bnx2x_disable_ptp(struct bnx2x *bp)
9166 {
9167         int port = BP_PORT(bp);
9168
9169         /* Disable sending PTP packets to host */
9170         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9171                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9172
9173         /* Reset PTP event detection rules */
9174         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9175                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9176         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9177                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9178         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9179                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9180         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9181                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9182
9183         /* Disable the PTP feature */
9184         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9185                NIG_REG_P0_PTP_EN, 0x0);
9186 }
9187
9188 /* Called during unload, to stop PTP-related stuff */
9189 static void bnx2x_stop_ptp(struct bnx2x *bp)
9190 {
9191         /* Cancel PTP work queue. Should be done after the Tx queues are
9192          * drained to prevent additional scheduling.
9193          */
9194         cancel_work_sync(&bp->ptp_task);
9195
9196         if (bp->ptp_tx_skb) {
9197                 dev_kfree_skb_any(bp->ptp_tx_skb);
9198                 bp->ptp_tx_skb = NULL;
9199         }
9200
9201         /* Disable PTP in HW */
9202         bnx2x_disable_ptp(bp);
9203
9204         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9205 }
9206
9207 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9208 {
9209         int port = BP_PORT(bp);
9210         int i, rc = 0;
9211         u8 cos;
9212         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9213         u32 reset_code;
9214
9215         /* Wait until tx fastpath tasks complete */
9216         for_each_tx_queue(bp, i) {
9217                 struct bnx2x_fastpath *fp = &bp->fp[i];
9218
9219                 for_each_cos_in_tx_queue(fp, cos)
9220                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9221 #ifdef BNX2X_STOP_ON_ERROR
9222                 if (rc)
9223                         return;
9224 #endif
9225         }
9226
9227         /* Give HW time to discard old tx messages */
9228         usleep_range(1000, 2000);
9229
9230         /* Clean all ETH MACs */
9231         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9232                                 false);
9233         if (rc < 0)
9234                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9235
9236         /* Clean up UC list  */
9237         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9238                                 true);
9239         if (rc < 0)
9240                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9241                           rc);
9242
9243         /* Disable LLH */
9244         if (!CHIP_IS_E1(bp))
9245                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9246
9247         /* Set "drop all" (stop Rx).
9248          * We need to take a netif_addr_lock() here in order to prevent
9249          * a race between the completion code and this code.
9250          */
9251         netif_addr_lock_bh(bp->dev);
9252         /* Schedule the rx_mode command */
9253         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9254                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9255         else
9256                 bnx2x_set_storm_rx_mode(bp);
9257
9258         /* Cleanup multicast configuration */
9259         rparam.mcast_obj = &bp->mcast_obj;
9260         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9261         if (rc < 0)
9262                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9263
9264         netif_addr_unlock_bh(bp->dev);
9265
9266         bnx2x_iov_chip_cleanup(bp);
9267
9268         /*
9269          * Send the UNLOAD_REQUEST to the MCP. This will return if
9270          * this function should perform FUNC, PORT or COMMON HW
9271          * reset.
9272          */
9273         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9274
9275         /*
9276          * (assumption: No Attention from MCP at this stage)
9277          * PMF probably in the middle of TX disable/enable transaction
9278          */
9279         rc = bnx2x_func_wait_started(bp);
9280         if (rc) {
9281                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9282 #ifdef BNX2X_STOP_ON_ERROR
9283                 return;
9284 #endif
9285         }
9286
9287         /* Close multi and leading connections
9288          * Completions for ramrods are collected in a synchronous way
9289          */
9290         for_each_eth_queue(bp, i)
9291                 if (bnx2x_stop_queue(bp, i))
9292 #ifdef BNX2X_STOP_ON_ERROR
9293                         return;
9294 #else
9295                         goto unload_error;
9296 #endif
9297
9298         if (CNIC_LOADED(bp)) {
9299                 for_each_cnic_queue(bp, i)
9300                         if (bnx2x_stop_queue(bp, i))
9301 #ifdef BNX2X_STOP_ON_ERROR
9302                                 return;
9303 #else
9304                                 goto unload_error;
9305 #endif
9306         }
9307
9308         /* If SP settings didn't get completed so far - something
9309          * very wrong has happen.
9310          */
9311         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9312                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9313
9314 #ifndef BNX2X_STOP_ON_ERROR
9315 unload_error:
9316 #endif
9317         rc = bnx2x_func_stop(bp);
9318         if (rc) {
9319                 BNX2X_ERR("Function stop failed!\n");
9320 #ifdef BNX2X_STOP_ON_ERROR
9321                 return;
9322 #endif
9323         }
9324
9325         /* stop_ptp should be after the Tx queues are drained to prevent
9326          * scheduling to the cancelled PTP work queue. It should also be after
9327          * function stop ramrod is sent, since as part of this ramrod FW access
9328          * PTP registers.
9329          */
9330         bnx2x_stop_ptp(bp);
9331
9332         /* Disable HW interrupts, NAPI */
9333         bnx2x_netif_stop(bp, 1);
9334         /* Delete all NAPI objects */
9335         bnx2x_del_all_napi(bp);
9336         if (CNIC_LOADED(bp))
9337                 bnx2x_del_all_napi_cnic(bp);
9338
9339         /* Release IRQs */
9340         bnx2x_free_irq(bp);
9341
9342         /* Reset the chip */
9343         rc = bnx2x_reset_hw(bp, reset_code);
9344         if (rc)
9345                 BNX2X_ERR("HW_RESET failed\n");
9346
9347         /* Report UNLOAD_DONE to MCP */
9348         bnx2x_send_unload_done(bp, keep_link);
9349 }
9350
9351 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9352 {
9353         u32 val;
9354
9355         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9356
9357         if (CHIP_IS_E1(bp)) {
9358                 int port = BP_PORT(bp);
9359                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9360                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9361
9362                 val = REG_RD(bp, addr);
9363                 val &= ~(0x300);
9364                 REG_WR(bp, addr, val);
9365         } else {
9366                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9367                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9368                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9369                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9370         }
9371 }
9372
9373 /* Close gates #2, #3 and #4: */
9374 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9375 {
9376         u32 val;
9377
9378         /* Gates #2 and #4a are closed/opened for "not E1" only */
9379         if (!CHIP_IS_E1(bp)) {
9380                 /* #4 */
9381                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9382                 /* #2 */
9383                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9384         }
9385
9386         /* #3 */
9387         if (CHIP_IS_E1x(bp)) {
9388                 /* Prevent interrupts from HC on both ports */
9389                 val = REG_RD(bp, HC_REG_CONFIG_1);
9390                 REG_WR(bp, HC_REG_CONFIG_1,
9391                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9392                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9393
9394                 val = REG_RD(bp, HC_REG_CONFIG_0);
9395                 REG_WR(bp, HC_REG_CONFIG_0,
9396                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9397                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9398         } else {
9399                 /* Prevent incoming interrupts in IGU */
9400                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9401
9402                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9403                        (!close) ?
9404                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9405                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9406         }
9407
9408         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9409                 close ? "closing" : "opening");
9410         mmiowb();
9411 }
9412
9413 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9414
9415 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9416 {
9417         /* Do some magic... */
9418         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9419         *magic_val = val & SHARED_MF_CLP_MAGIC;
9420         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9421 }
9422
9423 /**
9424  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9425  *
9426  * @bp:         driver handle
9427  * @magic_val:  old value of the `magic' bit.
9428  */
9429 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9430 {
9431         /* Restore the `magic' bit value... */
9432         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9433         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9434                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9435 }
9436
9437 /**
9438  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9439  *
9440  * @bp:         driver handle
9441  * @magic_val:  old value of 'magic' bit.
9442  *
9443  * Takes care of CLP configurations.
9444  */
9445 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9446 {
9447         u32 shmem;
9448         u32 validity_offset;
9449
9450         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9451
9452         /* Set `magic' bit in order to save MF config */
9453         if (!CHIP_IS_E1(bp))
9454                 bnx2x_clp_reset_prep(bp, magic_val);
9455
9456         /* Get shmem offset */
9457         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9458         validity_offset =
9459                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9460
9461         /* Clear validity map flags */
9462         if (shmem > 0)
9463                 REG_WR(bp, shmem + validity_offset, 0);
9464 }
9465
9466 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9467 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9468
9469 /**
9470  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9471  *
9472  * @bp: driver handle
9473  */
9474 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9475 {
9476         /* special handling for emulation and FPGA,
9477            wait 10 times longer */
9478         if (CHIP_REV_IS_SLOW(bp))
9479                 msleep(MCP_ONE_TIMEOUT*10);
9480         else
9481                 msleep(MCP_ONE_TIMEOUT);
9482 }
9483
9484 /*
9485  * initializes bp->common.shmem_base and waits for validity signature to appear
9486  */
9487 static int bnx2x_init_shmem(struct bnx2x *bp)
9488 {
9489         int cnt = 0;
9490         u32 val = 0;
9491
9492         do {
9493                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9494                 if (bp->common.shmem_base) {
9495                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9496                         if (val & SHR_MEM_VALIDITY_MB)
9497                                 return 0;
9498                 }
9499
9500                 bnx2x_mcp_wait_one(bp);
9501
9502         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9503
9504         BNX2X_ERR("BAD MCP validity signature\n");
9505
9506         return -ENODEV;
9507 }
9508
9509 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9510 {
9511         int rc = bnx2x_init_shmem(bp);
9512
9513         /* Restore the `magic' bit value */
9514         if (!CHIP_IS_E1(bp))
9515                 bnx2x_clp_reset_done(bp, magic_val);
9516
9517         return rc;
9518 }
9519
9520 static void bnx2x_pxp_prep(struct bnx2x *bp)
9521 {
9522         if (!CHIP_IS_E1(bp)) {
9523                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9524                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9525                 mmiowb();
9526         }
9527 }
9528
9529 /*
9530  * Reset the whole chip except for:
9531  *      - PCIE core
9532  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9533  *              one reset bit)
9534  *      - IGU
9535  *      - MISC (including AEU)
9536  *      - GRC
9537  *      - RBCN, RBCP
9538  */
9539 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9540 {
9541         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9542         u32 global_bits2, stay_reset2;
9543
9544         /*
9545          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9546          * (per chip) blocks.
9547          */
9548         global_bits2 =
9549                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9550                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9551
9552         /* Don't reset the following blocks.
9553          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9554          *            reset, as in 4 port device they might still be owned
9555          *            by the MCP (there is only one leader per path).
9556          */
9557         not_reset_mask1 =
9558                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9559                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9560                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9561
9562         not_reset_mask2 =
9563                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9564                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9565                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9566                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9567                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9568                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9569                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9570                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9571                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9572                 MISC_REGISTERS_RESET_REG_2_PGLC |
9573                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9574                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9575                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9576                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9577                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9578                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9579
9580         /*
9581          * Keep the following blocks in reset:
9582          *  - all xxMACs are handled by the bnx2x_link code.
9583          */
9584         stay_reset2 =
9585                 MISC_REGISTERS_RESET_REG_2_XMAC |
9586                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9587
9588         /* Full reset masks according to the chip */
9589         reset_mask1 = 0xffffffff;
9590
9591         if (CHIP_IS_E1(bp))
9592                 reset_mask2 = 0xffff;
9593         else if (CHIP_IS_E1H(bp))
9594                 reset_mask2 = 0x1ffff;
9595         else if (CHIP_IS_E2(bp))
9596                 reset_mask2 = 0xfffff;
9597         else /* CHIP_IS_E3 */
9598                 reset_mask2 = 0x3ffffff;
9599
9600         /* Don't reset global blocks unless we need to */
9601         if (!global)
9602                 reset_mask2 &= ~global_bits2;
9603
9604         /*
9605          * In case of attention in the QM, we need to reset PXP
9606          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9607          * because otherwise QM reset would release 'close the gates' shortly
9608          * before resetting the PXP, then the PSWRQ would send a write
9609          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9610          * read the payload data from PSWWR, but PSWWR would not
9611          * respond. The write queue in PGLUE would stuck, dmae commands
9612          * would not return. Therefore it's important to reset the second
9613          * reset register (containing the
9614          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9615          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9616          * bit).
9617          */
9618         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9619                reset_mask2 & (~not_reset_mask2));
9620
9621         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9622                reset_mask1 & (~not_reset_mask1));
9623
9624         barrier();
9625         mmiowb();
9626
9627         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9628                reset_mask2 & (~stay_reset2));
9629
9630         barrier();
9631         mmiowb();
9632
9633         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9634         mmiowb();
9635 }
9636
9637 /**
9638  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9639  * It should get cleared in no more than 1s.
9640  *
9641  * @bp: driver handle
9642  *
9643  * It should get cleared in no more than 1s. Returns 0 if
9644  * pending writes bit gets cleared.
9645  */
9646 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9647 {
9648         u32 cnt = 1000;
9649         u32 pend_bits = 0;
9650
9651         do {
9652                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9653
9654                 if (pend_bits == 0)
9655                         break;
9656
9657                 usleep_range(1000, 2000);
9658         } while (cnt-- > 0);
9659
9660         if (cnt <= 0) {
9661                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9662                           pend_bits);
9663                 return -EBUSY;
9664         }
9665
9666         return 0;
9667 }
9668
9669 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9670 {
9671         int cnt = 1000;
9672         u32 val = 0;
9673         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9674         u32 tags_63_32 = 0;
9675
9676         /* Empty the Tetris buffer, wait for 1s */
9677         do {
9678                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9679                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9680                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9681                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9682                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9683                 if (CHIP_IS_E3(bp))
9684                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9685
9686                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9687                     ((port_is_idle_0 & 0x1) == 0x1) &&
9688                     ((port_is_idle_1 & 0x1) == 0x1) &&
9689                     (pgl_exp_rom2 == 0xffffffff) &&
9690                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9691                         break;
9692                 usleep_range(1000, 2000);
9693         } while (cnt-- > 0);
9694
9695         if (cnt <= 0) {
9696                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9697                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9698                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9699                           pgl_exp_rom2);
9700                 return -EAGAIN;
9701         }
9702
9703         barrier();
9704
9705         /* Close gates #2, #3 and #4 */
9706         bnx2x_set_234_gates(bp, true);
9707
9708         /* Poll for IGU VQs for 57712 and newer chips */
9709         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9710                 return -EAGAIN;
9711
9712         /* TBD: Indicate that "process kill" is in progress to MCP */
9713
9714         /* Clear "unprepared" bit */
9715         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9716         barrier();
9717
9718         /* Make sure all is written to the chip before the reset */
9719         mmiowb();
9720
9721         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9722          * PSWHST, GRC and PSWRD Tetris buffer.
9723          */
9724         usleep_range(1000, 2000);
9725
9726         /* Prepare to chip reset: */
9727         /* MCP */
9728         if (global)
9729                 bnx2x_reset_mcp_prep(bp, &val);
9730
9731         /* PXP */
9732         bnx2x_pxp_prep(bp);
9733         barrier();
9734
9735         /* reset the chip */
9736         bnx2x_process_kill_chip_reset(bp, global);
9737         barrier();
9738
9739         /* clear errors in PGB */
9740         if (!CHIP_IS_E1x(bp))
9741                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9742
9743         /* Recover after reset: */
9744         /* MCP */
9745         if (global && bnx2x_reset_mcp_comp(bp, val))
9746                 return -EAGAIN;
9747
9748         /* TBD: Add resetting the NO_MCP mode DB here */
9749
9750         /* Open the gates #2, #3 and #4 */
9751         bnx2x_set_234_gates(bp, false);
9752
9753         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9754          * reset state, re-enable attentions. */
9755
9756         return 0;
9757 }
9758
9759 static int bnx2x_leader_reset(struct bnx2x *bp)
9760 {
9761         int rc = 0;
9762         bool global = bnx2x_reset_is_global(bp);
9763         u32 load_code;
9764
9765         /* if not going to reset MCP - load "fake" driver to reset HW while
9766          * driver is owner of the HW
9767          */
9768         if (!global && !BP_NOMCP(bp)) {
9769                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9770                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9771                 if (!load_code) {
9772                         BNX2X_ERR("MCP response failure, aborting\n");
9773                         rc = -EAGAIN;
9774                         goto exit_leader_reset;
9775                 }
9776                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9777                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9778                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9779                         rc = -EAGAIN;
9780                         goto exit_leader_reset2;
9781                 }
9782                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9783                 if (!load_code) {
9784                         BNX2X_ERR("MCP response failure, aborting\n");
9785                         rc = -EAGAIN;
9786                         goto exit_leader_reset2;
9787                 }
9788         }
9789
9790         /* Try to recover after the failure */
9791         if (bnx2x_process_kill(bp, global)) {
9792                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9793                           BP_PATH(bp));
9794                 rc = -EAGAIN;
9795                 goto exit_leader_reset2;
9796         }
9797
9798         /*
9799          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9800          * state.
9801          */
9802         bnx2x_set_reset_done(bp);
9803         if (global)
9804                 bnx2x_clear_reset_global(bp);
9805
9806 exit_leader_reset2:
9807         /* unload "fake driver" if it was loaded */
9808         if (!global && !BP_NOMCP(bp)) {
9809                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9810                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9811         }
9812 exit_leader_reset:
9813         bp->is_leader = 0;
9814         bnx2x_release_leader_lock(bp);
9815         smp_mb();
9816         return rc;
9817 }
9818
9819 static void bnx2x_recovery_failed(struct bnx2x *bp)
9820 {
9821         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9822
9823         /* Disconnect this device */
9824         netif_device_detach(bp->dev);
9825
9826         /*
9827          * Block ifup for all function on this engine until "process kill"
9828          * or power cycle.
9829          */
9830         bnx2x_set_reset_in_progress(bp);
9831
9832         /* Shut down the power */
9833         bnx2x_set_power_state(bp, PCI_D3hot);
9834
9835         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9836
9837         smp_mb();
9838 }
9839
9840 /*
9841  * Assumption: runs under rtnl lock. This together with the fact
9842  * that it's called only from bnx2x_sp_rtnl() ensure that it
9843  * will never be called when netif_running(bp->dev) is false.
9844  */
9845 static void bnx2x_parity_recover(struct bnx2x *bp)
9846 {
9847         bool global = false;
9848         u32 error_recovered, error_unrecovered;
9849         bool is_parity;
9850
9851         DP(NETIF_MSG_HW, "Handling parity\n");
9852         while (1) {
9853                 switch (bp->recovery_state) {
9854                 case BNX2X_RECOVERY_INIT:
9855                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9856                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9857                         WARN_ON(!is_parity);
9858
9859                         /* Try to get a LEADER_LOCK HW lock */
9860                         if (bnx2x_trylock_leader_lock(bp)) {
9861                                 bnx2x_set_reset_in_progress(bp);
9862                                 /*
9863                                  * Check if there is a global attention and if
9864                                  * there was a global attention, set the global
9865                                  * reset bit.
9866                                  */
9867
9868                                 if (global)
9869                                         bnx2x_set_reset_global(bp);
9870
9871                                 bp->is_leader = 1;
9872                         }
9873
9874                         /* Stop the driver */
9875                         /* If interface has been removed - break */
9876                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9877                                 return;
9878
9879                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9880
9881                         /* Ensure "is_leader", MCP command sequence and
9882                          * "recovery_state" update values are seen on other
9883                          * CPUs.
9884                          */
9885                         smp_mb();
9886                         break;
9887
9888                 case BNX2X_RECOVERY_WAIT:
9889                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9890                         if (bp->is_leader) {
9891                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9892                                 bool other_load_status =
9893                                         bnx2x_get_load_status(bp, other_engine);
9894                                 bool load_status =
9895                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9896                                 global = bnx2x_reset_is_global(bp);
9897
9898                                 /*
9899                                  * In case of a parity in a global block, let
9900                                  * the first leader that performs a
9901                                  * leader_reset() reset the global blocks in
9902                                  * order to clear global attentions. Otherwise
9903                                  * the gates will remain closed for that
9904                                  * engine.
9905                                  */
9906                                 if (load_status ||
9907                                     (global && other_load_status)) {
9908                                         /* Wait until all other functions get
9909                                          * down.
9910                                          */
9911                                         schedule_delayed_work(&bp->sp_rtnl_task,
9912                                                                 HZ/10);
9913                                         return;
9914                                 } else {
9915                                         /* If all other functions got down -
9916                                          * try to bring the chip back to
9917                                          * normal. In any case it's an exit
9918                                          * point for a leader.
9919                                          */
9920                                         if (bnx2x_leader_reset(bp)) {
9921                                                 bnx2x_recovery_failed(bp);
9922                                                 return;
9923                                         }
9924
9925                                         /* If we are here, means that the
9926                                          * leader has succeeded and doesn't
9927                                          * want to be a leader any more. Try
9928                                          * to continue as a none-leader.
9929                                          */
9930                                         break;
9931                                 }
9932                         } else { /* non-leader */
9933                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9934                                         /* Try to get a LEADER_LOCK HW lock as
9935                                          * long as a former leader may have
9936                                          * been unloaded by the user or
9937                                          * released a leadership by another
9938                                          * reason.
9939                                          */
9940                                         if (bnx2x_trylock_leader_lock(bp)) {
9941                                                 /* I'm a leader now! Restart a
9942                                                  * switch case.
9943                                                  */
9944                                                 bp->is_leader = 1;
9945                                                 break;
9946                                         }
9947
9948                                         schedule_delayed_work(&bp->sp_rtnl_task,
9949                                                                 HZ/10);
9950                                         return;
9951
9952                                 } else {
9953                                         /*
9954                                          * If there was a global attention, wait
9955                                          * for it to be cleared.
9956                                          */
9957                                         if (bnx2x_reset_is_global(bp)) {
9958                                                 schedule_delayed_work(
9959                                                         &bp->sp_rtnl_task,
9960                                                         HZ/10);
9961                                                 return;
9962                                         }
9963
9964                                         error_recovered =
9965                                           bp->eth_stats.recoverable_error;
9966                                         error_unrecovered =
9967                                           bp->eth_stats.unrecoverable_error;
9968                                         bp->recovery_state =
9969                                                 BNX2X_RECOVERY_NIC_LOADING;
9970                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9971                                                 error_unrecovered++;
9972                                                 netdev_err(bp->dev,
9973                                                            "Recovery failed. Power cycle needed\n");
9974                                                 /* Disconnect this device */
9975                                                 netif_device_detach(bp->dev);
9976                                                 /* Shut down the power */
9977                                                 bnx2x_set_power_state(
9978                                                         bp, PCI_D3hot);
9979                                                 smp_mb();
9980                                         } else {
9981                                                 bp->recovery_state =
9982                                                         BNX2X_RECOVERY_DONE;
9983                                                 error_recovered++;
9984                                                 smp_mb();
9985                                         }
9986                                         bp->eth_stats.recoverable_error =
9987                                                 error_recovered;
9988                                         bp->eth_stats.unrecoverable_error =
9989                                                 error_unrecovered;
9990
9991                                         return;
9992                                 }
9993                         }
9994                 default:
9995                         return;
9996                 }
9997         }
9998 }
9999
10000 static int bnx2x_close(struct net_device *dev);
10001
10002 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10003  * scheduled on a general queue in order to prevent a dead lock.
10004  */
10005 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10006 {
10007         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10008
10009         rtnl_lock();
10010
10011         if (!netif_running(bp->dev)) {
10012                 rtnl_unlock();
10013                 return;
10014         }
10015
10016         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10017 #ifdef BNX2X_STOP_ON_ERROR
10018                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10019                           "you will need to reboot when done\n");
10020                 goto sp_rtnl_not_reset;
10021 #endif
10022                 /*
10023                  * Clear all pending SP commands as we are going to reset the
10024                  * function anyway.
10025                  */
10026                 bp->sp_rtnl_state = 0;
10027                 smp_mb();
10028
10029                 bnx2x_parity_recover(bp);
10030
10031                 rtnl_unlock();
10032                 return;
10033         }
10034
10035         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10036 #ifdef BNX2X_STOP_ON_ERROR
10037                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10038                           "you will need to reboot when done\n");
10039                 goto sp_rtnl_not_reset;
10040 #endif
10041
10042                 /*
10043                  * Clear all pending SP commands as we are going to reset the
10044                  * function anyway.
10045                  */
10046                 bp->sp_rtnl_state = 0;
10047                 smp_mb();
10048
10049                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10050                 bnx2x_nic_load(bp, LOAD_NORMAL);
10051
10052                 rtnl_unlock();
10053                 return;
10054         }
10055 #ifdef BNX2X_STOP_ON_ERROR
10056 sp_rtnl_not_reset:
10057 #endif
10058         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10059                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10060         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10061                 bnx2x_after_function_update(bp);
10062         /*
10063          * in case of fan failure we need to reset id if the "stop on error"
10064          * debug flag is set, since we trying to prevent permanent overheating
10065          * damage
10066          */
10067         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10068                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10069                 netif_device_detach(bp->dev);
10070                 bnx2x_close(bp->dev);
10071                 rtnl_unlock();
10072                 return;
10073         }
10074
10075         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10076                 DP(BNX2X_MSG_SP,
10077                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10078                 bnx2x_vfpf_set_mcast(bp->dev);
10079         }
10080         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10081                                &bp->sp_rtnl_state)){
10082                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10083                         bnx2x_tx_disable(bp);
10084                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10085                 }
10086         }
10087
10088         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10089                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10090                 bnx2x_set_rx_mode_inner(bp);
10091         }
10092
10093         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10094                                &bp->sp_rtnl_state))
10095                 bnx2x_pf_set_vfs_vlan(bp);
10096
10097         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10098                 bnx2x_dcbx_stop_hw_tx(bp);
10099                 bnx2x_dcbx_resume_hw_tx(bp);
10100         }
10101
10102         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10103                                &bp->sp_rtnl_state))
10104                 bnx2x_update_mng_version(bp);
10105
10106         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10107          * can be called from other contexts as well)
10108          */
10109         rtnl_unlock();
10110
10111         /* enable SR-IOV if applicable */
10112         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10113                                                &bp->sp_rtnl_state)) {
10114                 bnx2x_disable_sriov(bp);
10115                 bnx2x_enable_sriov(bp);
10116         }
10117 }
10118
10119 static void bnx2x_period_task(struct work_struct *work)
10120 {
10121         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10122
10123         if (!netif_running(bp->dev))
10124                 goto period_task_exit;
10125
10126         if (CHIP_REV_IS_SLOW(bp)) {
10127                 BNX2X_ERR("period task called on emulation, ignoring\n");
10128                 goto period_task_exit;
10129         }
10130
10131         bnx2x_acquire_phy_lock(bp);
10132         /*
10133          * The barrier is needed to ensure the ordering between the writing to
10134          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10135          * the reading here.
10136          */
10137         smp_mb();
10138         if (bp->port.pmf) {
10139                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10140
10141                 /* Re-queue task in 1 sec */
10142                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10143         }
10144
10145         bnx2x_release_phy_lock(bp);
10146 period_task_exit:
10147         return;
10148 }
10149
10150 /*
10151  * Init service functions
10152  */
10153
10154 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10155 {
10156         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10157         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10158         return base + (BP_ABS_FUNC(bp)) * stride;
10159 }
10160
10161 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10162                                          u8 port, u32 reset_reg,
10163                                          struct bnx2x_mac_vals *vals)
10164 {
10165         u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10166         u32 base_addr;
10167
10168         if (!(mask & reset_reg))
10169                 return false;
10170
10171         BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10172         base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10173         vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10174         vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10175         REG_WR(bp, vals->umac_addr[port], 0);
10176
10177         return true;
10178 }
10179
10180 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10181                                         struct bnx2x_mac_vals *vals)
10182 {
10183         u32 val, base_addr, offset, mask, reset_reg;
10184         bool mac_stopped = false;
10185         u8 port = BP_PORT(bp);
10186
10187         /* reset addresses as they also mark which values were changed */
10188         memset(vals, 0, sizeof(*vals));
10189
10190         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10191
10192         if (!CHIP_IS_E3(bp)) {
10193                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10194                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10195                 if ((mask & reset_reg) && val) {
10196                         u32 wb_data[2];
10197                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10198                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10199                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10200                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10201                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10202
10203                         /*
10204                          * use rd/wr since we cannot use dmae. This is safe
10205                          * since MCP won't access the bus due to the request
10206                          * to unload, and no function on the path can be
10207                          * loaded at this time.
10208                          */
10209                         wb_data[0] = REG_RD(bp, base_addr + offset);
10210                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10211                         vals->bmac_addr = base_addr + offset;
10212                         vals->bmac_val[0] = wb_data[0];
10213                         vals->bmac_val[1] = wb_data[1];
10214                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10215                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10216                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10217                 }
10218                 BNX2X_DEV_INFO("Disable emac Rx\n");
10219                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10220                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10221                 REG_WR(bp, vals->emac_addr, 0);
10222                 mac_stopped = true;
10223         } else {
10224                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10225                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10226                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10227                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10228                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10229                                val & ~(1 << 1));
10230                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10231                                val | (1 << 1));
10232                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10233                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10234                         REG_WR(bp, vals->xmac_addr, 0);
10235                         mac_stopped = true;
10236                 }
10237
10238                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10239                                                             reset_reg, vals);
10240                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10241                                                             reset_reg, vals);
10242         }
10243
10244         if (mac_stopped)
10245                 msleep(20);
10246 }
10247
10248 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10249 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10250                                         0x1848 + ((f) << 4))
10251 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10252 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10253 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10254
10255 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10256 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10257 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10258
10259 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10260 {
10261         /* UNDI marks its presence in DORQ -
10262          * it initializes CID offset for normal bell to 0x7
10263          */
10264         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10265             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10266                 return false;
10267
10268         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10269                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10270                 return true;
10271         }
10272
10273         return false;
10274 }
10275
10276 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10277 {
10278         u16 rcq, bd;
10279         u32 addr, tmp_reg;
10280
10281         if (BP_FUNC(bp) < 2)
10282                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10283         else
10284                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10285
10286         tmp_reg = REG_RD(bp, addr);
10287         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10288         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10289
10290         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10291         REG_WR(bp, addr, tmp_reg);
10292
10293         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10294                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10295 }
10296
10297 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10298 {
10299         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10300                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10301         if (!rc) {
10302                 BNX2X_ERR("MCP response failure, aborting\n");
10303                 return -EBUSY;
10304         }
10305
10306         return 0;
10307 }
10308
10309 static struct bnx2x_prev_path_list *
10310                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10311 {
10312         struct bnx2x_prev_path_list *tmp_list;
10313
10314         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10315                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10316                     bp->pdev->bus->number == tmp_list->bus &&
10317                     BP_PATH(bp) == tmp_list->path)
10318                         return tmp_list;
10319
10320         return NULL;
10321 }
10322
10323 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10324 {
10325         struct bnx2x_prev_path_list *tmp_list;
10326         int rc;
10327
10328         rc = down_interruptible(&bnx2x_prev_sem);
10329         if (rc) {
10330                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10331                 return rc;
10332         }
10333
10334         tmp_list = bnx2x_prev_path_get_entry(bp);
10335         if (tmp_list) {
10336                 tmp_list->aer = 1;
10337                 rc = 0;
10338         } else {
10339                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10340                           BP_PATH(bp));
10341         }
10342
10343         up(&bnx2x_prev_sem);
10344
10345         return rc;
10346 }
10347
10348 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10349 {
10350         struct bnx2x_prev_path_list *tmp_list;
10351         bool rc = false;
10352
10353         if (down_trylock(&bnx2x_prev_sem))
10354                 return false;
10355
10356         tmp_list = bnx2x_prev_path_get_entry(bp);
10357         if (tmp_list) {
10358                 if (tmp_list->aer) {
10359                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10360                            BP_PATH(bp));
10361                 } else {
10362                         rc = true;
10363                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10364                                        BP_PATH(bp));
10365                 }
10366         }
10367
10368         up(&bnx2x_prev_sem);
10369
10370         return rc;
10371 }
10372
10373 bool bnx2x_port_after_undi(struct bnx2x *bp)
10374 {
10375         struct bnx2x_prev_path_list *entry;
10376         bool val;
10377
10378         down(&bnx2x_prev_sem);
10379
10380         entry = bnx2x_prev_path_get_entry(bp);
10381         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10382
10383         up(&bnx2x_prev_sem);
10384
10385         return val;
10386 }
10387
10388 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10389 {
10390         struct bnx2x_prev_path_list *tmp_list;
10391         int rc;
10392
10393         rc = down_interruptible(&bnx2x_prev_sem);
10394         if (rc) {
10395                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10396                 return rc;
10397         }
10398
10399         /* Check whether the entry for this path already exists */
10400         tmp_list = bnx2x_prev_path_get_entry(bp);
10401         if (tmp_list) {
10402                 if (!tmp_list->aer) {
10403                         BNX2X_ERR("Re-Marking the path.\n");
10404                 } else {
10405                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10406                            BP_PATH(bp));
10407                         tmp_list->aer = 0;
10408                 }
10409                 up(&bnx2x_prev_sem);
10410                 return 0;
10411         }
10412         up(&bnx2x_prev_sem);
10413
10414         /* Create an entry for this path and add it */
10415         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10416         if (!tmp_list) {
10417                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10418                 return -ENOMEM;
10419         }
10420
10421         tmp_list->bus = bp->pdev->bus->number;
10422         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10423         tmp_list->path = BP_PATH(bp);
10424         tmp_list->aer = 0;
10425         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10426
10427         rc = down_interruptible(&bnx2x_prev_sem);
10428         if (rc) {
10429                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10430                 kfree(tmp_list);
10431         } else {
10432                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10433                    BP_PATH(bp));
10434                 list_add(&tmp_list->list, &bnx2x_prev_list);
10435                 up(&bnx2x_prev_sem);
10436         }
10437
10438         return rc;
10439 }
10440
10441 static int bnx2x_do_flr(struct bnx2x *bp)
10442 {
10443         struct pci_dev *dev = bp->pdev;
10444
10445         if (CHIP_IS_E1x(bp)) {
10446                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10447                 return -EINVAL;
10448         }
10449
10450         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10451         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10452                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10453                           bp->common.bc_ver);
10454                 return -EINVAL;
10455         }
10456
10457         if (!pci_wait_for_pending_transaction(dev))
10458                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10459
10460         BNX2X_DEV_INFO("Initiating FLR\n");
10461         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10462
10463         return 0;
10464 }
10465
10466 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10467 {
10468         int rc;
10469
10470         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10471
10472         /* Test if previous unload process was already finished for this path */
10473         if (bnx2x_prev_is_path_marked(bp))
10474                 return bnx2x_prev_mcp_done(bp);
10475
10476         BNX2X_DEV_INFO("Path is unmarked\n");
10477
10478         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10479         if (bnx2x_prev_is_after_undi(bp))
10480                 goto out;
10481
10482         /* If function has FLR capabilities, and existing FW version matches
10483          * the one required, then FLR will be sufficient to clean any residue
10484          * left by previous driver
10485          */
10486         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10487
10488         if (!rc) {
10489                 /* fw version is good */
10490                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10491                 rc = bnx2x_do_flr(bp);
10492         }
10493
10494         if (!rc) {
10495                 /* FLR was performed */
10496                 BNX2X_DEV_INFO("FLR successful\n");
10497                 return 0;
10498         }
10499
10500         BNX2X_DEV_INFO("Could not FLR\n");
10501
10502 out:
10503         /* Close the MCP request, return failure*/
10504         rc = bnx2x_prev_mcp_done(bp);
10505         if (!rc)
10506                 rc = BNX2X_PREV_WAIT_NEEDED;
10507
10508         return rc;
10509 }
10510
10511 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10512 {
10513         u32 reset_reg, tmp_reg = 0, rc;
10514         bool prev_undi = false;
10515         struct bnx2x_mac_vals mac_vals;
10516
10517         /* It is possible a previous function received 'common' answer,
10518          * but hasn't loaded yet, therefore creating a scenario of
10519          * multiple functions receiving 'common' on the same path.
10520          */
10521         BNX2X_DEV_INFO("Common unload Flow\n");
10522
10523         memset(&mac_vals, 0, sizeof(mac_vals));
10524
10525         if (bnx2x_prev_is_path_marked(bp))
10526                 return bnx2x_prev_mcp_done(bp);
10527
10528         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10529
10530         /* Reset should be performed after BRB is emptied */
10531         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10532                 u32 timer_count = 1000;
10533
10534                 /* Close the MAC Rx to prevent BRB from filling up */
10535                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10536
10537                 /* close LLH filters for both ports towards the BRB */
10538                 bnx2x_set_rx_filter(&bp->link_params, 0);
10539                 bp->link_params.port ^= 1;
10540                 bnx2x_set_rx_filter(&bp->link_params, 0);
10541                 bp->link_params.port ^= 1;
10542
10543                 /* Check if the UNDI driver was previously loaded */
10544                 if (bnx2x_prev_is_after_undi(bp)) {
10545                         prev_undi = true;
10546                         /* clear the UNDI indication */
10547                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10548                         /* clear possible idle check errors */
10549                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10550                 }
10551                 if (!CHIP_IS_E1x(bp))
10552                         /* block FW from writing to host */
10553                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10554
10555                 /* wait until BRB is empty */
10556                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10557                 while (timer_count) {
10558                         u32 prev_brb = tmp_reg;
10559
10560                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10561                         if (!tmp_reg)
10562                                 break;
10563
10564                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10565
10566                         /* reset timer as long as BRB actually gets emptied */
10567                         if (prev_brb > tmp_reg)
10568                                 timer_count = 1000;
10569                         else
10570                                 timer_count--;
10571
10572                         /* If UNDI resides in memory, manually increment it */
10573                         if (prev_undi)
10574                                 bnx2x_prev_unload_undi_inc(bp, 1);
10575
10576                         udelay(10);
10577                 }
10578
10579                 if (!timer_count)
10580                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10581         }
10582
10583         /* No packets are in the pipeline, path is ready for reset */
10584         bnx2x_reset_common(bp);
10585
10586         if (mac_vals.xmac_addr)
10587                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10588         if (mac_vals.umac_addr[0])
10589                 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10590         if (mac_vals.umac_addr[1])
10591                 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10592         if (mac_vals.emac_addr)
10593                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10594         if (mac_vals.bmac_addr) {
10595                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10596                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10597         }
10598
10599         rc = bnx2x_prev_mark_path(bp, prev_undi);
10600         if (rc) {
10601                 bnx2x_prev_mcp_done(bp);
10602                 return rc;
10603         }
10604
10605         return bnx2x_prev_mcp_done(bp);
10606 }
10607
10608 static int bnx2x_prev_unload(struct bnx2x *bp)
10609 {
10610         int time_counter = 10;
10611         u32 rc, fw, hw_lock_reg, hw_lock_val;
10612         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10613
10614         /* clear hw from errors which may have resulted from an interrupted
10615          * dmae transaction.
10616          */
10617         bnx2x_clean_pglue_errors(bp);
10618
10619         /* Release previously held locks */
10620         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10621                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10622                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10623
10624         hw_lock_val = REG_RD(bp, hw_lock_reg);
10625         if (hw_lock_val) {
10626                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10627                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10628                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10629                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10630                 }
10631
10632                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10633                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10634         } else
10635                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10636
10637         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10638                 BNX2X_DEV_INFO("Release previously held alr\n");
10639                 bnx2x_release_alr(bp);
10640         }
10641
10642         do {
10643                 int aer = 0;
10644                 /* Lock MCP using an unload request */
10645                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10646                 if (!fw) {
10647                         BNX2X_ERR("MCP response failure, aborting\n");
10648                         rc = -EBUSY;
10649                         break;
10650                 }
10651
10652                 rc = down_interruptible(&bnx2x_prev_sem);
10653                 if (rc) {
10654                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10655                                   rc);
10656                 } else {
10657                         /* If Path is marked by EEH, ignore unload status */
10658                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10659                                  bnx2x_prev_path_get_entry(bp)->aer);
10660                         up(&bnx2x_prev_sem);
10661                 }
10662
10663                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10664                         rc = bnx2x_prev_unload_common(bp);
10665                         break;
10666                 }
10667
10668                 /* non-common reply from MCP might require looping */
10669                 rc = bnx2x_prev_unload_uncommon(bp);
10670                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10671                         break;
10672
10673                 msleep(20);
10674         } while (--time_counter);
10675
10676         if (!time_counter || rc) {
10677                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10678                 rc = -EPROBE_DEFER;
10679         }
10680
10681         /* Mark function if its port was used to boot from SAN */
10682         if (bnx2x_port_after_undi(bp))
10683                 bp->link_params.feature_config_flags |=
10684                         FEATURE_CONFIG_BOOT_FROM_SAN;
10685
10686         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10687
10688         return rc;
10689 }
10690
10691 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10692 {
10693         u32 val, val2, val3, val4, id, boot_mode;
10694         u16 pmc;
10695
10696         /* Get the chip revision id and number. */
10697         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10698         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10699         id = ((val & 0xffff) << 16);
10700         val = REG_RD(bp, MISC_REG_CHIP_REV);
10701         id |= ((val & 0xf) << 12);
10702
10703         /* Metal is read from PCI regs, but we can't access >=0x400 from
10704          * the configuration space (so we need to reg_rd)
10705          */
10706         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10707         id |= (((val >> 24) & 0xf) << 4);
10708         val = REG_RD(bp, MISC_REG_BOND_ID);
10709         id |= (val & 0xf);
10710         bp->common.chip_id = id;
10711
10712         /* force 57811 according to MISC register */
10713         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10714                 if (CHIP_IS_57810(bp))
10715                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10716                                 (bp->common.chip_id & 0x0000FFFF);
10717                 else if (CHIP_IS_57810_MF(bp))
10718                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10719                                 (bp->common.chip_id & 0x0000FFFF);
10720                 bp->common.chip_id |= 0x1;
10721         }
10722
10723         /* Set doorbell size */
10724         bp->db_size = (1 << BNX2X_DB_SHIFT);
10725
10726         if (!CHIP_IS_E1x(bp)) {
10727                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10728                 if ((val & 1) == 0)
10729                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10730                 else
10731                         val = (val >> 1) & 1;
10732                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10733                                                        "2_PORT_MODE");
10734                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10735                                                  CHIP_2_PORT_MODE;
10736
10737                 if (CHIP_MODE_IS_4_PORT(bp))
10738                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10739                 else
10740                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10741         } else {
10742                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10743                 bp->pfid = bp->pf_num;                  /* 0..7 */
10744         }
10745
10746         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10747
10748         bp->link_params.chip_id = bp->common.chip_id;
10749         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10750
10751         val = (REG_RD(bp, 0x2874) & 0x55);
10752         if ((bp->common.chip_id & 0x1) ||
10753             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10754                 bp->flags |= ONE_PORT_FLAG;
10755                 BNX2X_DEV_INFO("single port device\n");
10756         }
10757
10758         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10759         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10760                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10761         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10762                        bp->common.flash_size, bp->common.flash_size);
10763
10764         bnx2x_init_shmem(bp);
10765
10766         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10767                                         MISC_REG_GENERIC_CR_1 :
10768                                         MISC_REG_GENERIC_CR_0));
10769
10770         bp->link_params.shmem_base = bp->common.shmem_base;
10771         bp->link_params.shmem2_base = bp->common.shmem2_base;
10772         if (SHMEM2_RD(bp, size) >
10773             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10774                 bp->link_params.lfa_base =
10775                 REG_RD(bp, bp->common.shmem2_base +
10776                        (u32)offsetof(struct shmem2_region,
10777                                      lfa_host_addr[BP_PORT(bp)]));
10778         else
10779                 bp->link_params.lfa_base = 0;
10780         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10781                        bp->common.shmem_base, bp->common.shmem2_base);
10782
10783         if (!bp->common.shmem_base) {
10784                 BNX2X_DEV_INFO("MCP not active\n");
10785                 bp->flags |= NO_MCP_FLAG;
10786                 return;
10787         }
10788
10789         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10790         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10791
10792         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10793                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10794                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10795
10796         bp->link_params.feature_config_flags = 0;
10797         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10798         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10799                 bp->link_params.feature_config_flags |=
10800                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10801         else
10802                 bp->link_params.feature_config_flags &=
10803                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10804
10805         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10806         bp->common.bc_ver = val;
10807         BNX2X_DEV_INFO("bc_ver %X\n", val);
10808         if (val < BNX2X_BC_VER) {
10809                 /* for now only warn
10810                  * later we might need to enforce this */
10811                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10812                           BNX2X_BC_VER, val);
10813         }
10814         bp->link_params.feature_config_flags |=
10815                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10816                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10817
10818         bp->link_params.feature_config_flags |=
10819                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10820                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10821         bp->link_params.feature_config_flags |=
10822                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10823                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10824         bp->link_params.feature_config_flags |=
10825                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10826                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10827
10828         bp->link_params.feature_config_flags |=
10829                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10830                 FEATURE_CONFIG_MT_SUPPORT : 0;
10831
10832         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10833                         BC_SUPPORTS_PFC_STATS : 0;
10834
10835         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10836                         BC_SUPPORTS_FCOE_FEATURES : 0;
10837
10838         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10839                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10840
10841         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10842                         BC_SUPPORTS_RMMOD_CMD : 0;
10843
10844         boot_mode = SHMEM_RD(bp,
10845                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10846                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10847         switch (boot_mode) {
10848         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10849                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10850                 break;
10851         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10852                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10853                 break;
10854         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10855                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10856                 break;
10857         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10858                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10859                 break;
10860         }
10861
10862         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10863         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10864
10865         BNX2X_DEV_INFO("%sWoL capable\n",
10866                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10867
10868         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10869         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10870         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10871         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10872
10873         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10874                  val, val2, val3, val4);
10875 }
10876
10877 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10878 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10879
10880 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10881 {
10882         int pfid = BP_FUNC(bp);
10883         int igu_sb_id;
10884         u32 val;
10885         u8 fid, igu_sb_cnt = 0;
10886
10887         bp->igu_base_sb = 0xff;
10888         if (CHIP_INT_MODE_IS_BC(bp)) {
10889                 int vn = BP_VN(bp);
10890                 igu_sb_cnt = bp->igu_sb_cnt;
10891                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10892                         FP_SB_MAX_E1x;
10893
10894                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10895                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10896
10897                 return 0;
10898         }
10899
10900         /* IGU in normal mode - read CAM */
10901         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10902              igu_sb_id++) {
10903                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10904                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10905                         continue;
10906                 fid = IGU_FID(val);
10907                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10908                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10909                                 continue;
10910                         if (IGU_VEC(val) == 0)
10911                                 /* default status block */
10912                                 bp->igu_dsb_id = igu_sb_id;
10913                         else {
10914                                 if (bp->igu_base_sb == 0xff)
10915                                         bp->igu_base_sb = igu_sb_id;
10916                                 igu_sb_cnt++;
10917                         }
10918                 }
10919         }
10920
10921 #ifdef CONFIG_PCI_MSI
10922         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10923          * optional that number of CAM entries will not be equal to the value
10924          * advertised in PCI.
10925          * Driver should use the minimal value of both as the actual status
10926          * block count
10927          */
10928         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10929 #endif
10930
10931         if (igu_sb_cnt == 0) {
10932                 BNX2X_ERR("CAM configuration error\n");
10933                 return -EINVAL;
10934         }
10935
10936         return 0;
10937 }
10938
10939 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10940 {
10941         int cfg_size = 0, idx, port = BP_PORT(bp);
10942
10943         /* Aggregation of supported attributes of all external phys */
10944         bp->port.supported[0] = 0;
10945         bp->port.supported[1] = 0;
10946         switch (bp->link_params.num_phys) {
10947         case 1:
10948                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10949                 cfg_size = 1;
10950                 break;
10951         case 2:
10952                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10953                 cfg_size = 1;
10954                 break;
10955         case 3:
10956                 if (bp->link_params.multi_phy_config &
10957                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10958                         bp->port.supported[1] =
10959                                 bp->link_params.phy[EXT_PHY1].supported;
10960                         bp->port.supported[0] =
10961                                 bp->link_params.phy[EXT_PHY2].supported;
10962                 } else {
10963                         bp->port.supported[0] =
10964                                 bp->link_params.phy[EXT_PHY1].supported;
10965                         bp->port.supported[1] =
10966                                 bp->link_params.phy[EXT_PHY2].supported;
10967                 }
10968                 cfg_size = 2;
10969                 break;
10970         }
10971
10972         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10973                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10974                            SHMEM_RD(bp,
10975                            dev_info.port_hw_config[port].external_phy_config),
10976                            SHMEM_RD(bp,
10977                            dev_info.port_hw_config[port].external_phy_config2));
10978                         return;
10979         }
10980
10981         if (CHIP_IS_E3(bp))
10982                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10983         else {
10984                 switch (switch_cfg) {
10985                 case SWITCH_CFG_1G:
10986                         bp->port.phy_addr = REG_RD(
10987                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10988                         break;
10989                 case SWITCH_CFG_10G:
10990                         bp->port.phy_addr = REG_RD(
10991                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10992                         break;
10993                 default:
10994                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10995                                   bp->port.link_config[0]);
10996                         return;
10997                 }
10998         }
10999         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11000         /* mask what we support according to speed_cap_mask per configuration */
11001         for (idx = 0; idx < cfg_size; idx++) {
11002                 if (!(bp->link_params.speed_cap_mask[idx] &
11003                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11004                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11005
11006                 if (!(bp->link_params.speed_cap_mask[idx] &
11007                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11008                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11009
11010                 if (!(bp->link_params.speed_cap_mask[idx] &
11011                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11012                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11013
11014                 if (!(bp->link_params.speed_cap_mask[idx] &
11015                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11016                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11017
11018                 if (!(bp->link_params.speed_cap_mask[idx] &
11019                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11020                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11021                                                      SUPPORTED_1000baseT_Full);
11022
11023                 if (!(bp->link_params.speed_cap_mask[idx] &
11024                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11025                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11026
11027                 if (!(bp->link_params.speed_cap_mask[idx] &
11028                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11029                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11030
11031                 if (!(bp->link_params.speed_cap_mask[idx] &
11032                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11033                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11034         }
11035
11036         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11037                        bp->port.supported[1]);
11038 }
11039
11040 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11041 {
11042         u32 link_config, idx, cfg_size = 0;
11043         bp->port.advertising[0] = 0;
11044         bp->port.advertising[1] = 0;
11045         switch (bp->link_params.num_phys) {
11046         case 1:
11047         case 2:
11048                 cfg_size = 1;
11049                 break;
11050         case 3:
11051                 cfg_size = 2;
11052                 break;
11053         }
11054         for (idx = 0; idx < cfg_size; idx++) {
11055                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11056                 link_config = bp->port.link_config[idx];
11057                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11058                 case PORT_FEATURE_LINK_SPEED_AUTO:
11059                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11060                                 bp->link_params.req_line_speed[idx] =
11061                                         SPEED_AUTO_NEG;
11062                                 bp->port.advertising[idx] |=
11063                                         bp->port.supported[idx];
11064                                 if (bp->link_params.phy[EXT_PHY1].type ==
11065                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11066                                         bp->port.advertising[idx] |=
11067                                         (SUPPORTED_100baseT_Half |
11068                                          SUPPORTED_100baseT_Full);
11069                         } else {
11070                                 /* force 10G, no AN */
11071                                 bp->link_params.req_line_speed[idx] =
11072                                         SPEED_10000;
11073                                 bp->port.advertising[idx] |=
11074                                         (ADVERTISED_10000baseT_Full |
11075                                          ADVERTISED_FIBRE);
11076                                 continue;
11077                         }
11078                         break;
11079
11080                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11081                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11082                                 bp->link_params.req_line_speed[idx] =
11083                                         SPEED_10;
11084                                 bp->port.advertising[idx] |=
11085                                         (ADVERTISED_10baseT_Full |
11086                                          ADVERTISED_TP);
11087                         } else {
11088                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11089                                             link_config,
11090                                     bp->link_params.speed_cap_mask[idx]);
11091                                 return;
11092                         }
11093                         break;
11094
11095                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11096                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11097                                 bp->link_params.req_line_speed[idx] =
11098                                         SPEED_10;
11099                                 bp->link_params.req_duplex[idx] =
11100                                         DUPLEX_HALF;
11101                                 bp->port.advertising[idx] |=
11102                                         (ADVERTISED_10baseT_Half |
11103                                          ADVERTISED_TP);
11104                         } else {
11105                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11106                                             link_config,
11107                                           bp->link_params.speed_cap_mask[idx]);
11108                                 return;
11109                         }
11110                         break;
11111
11112                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11113                         if (bp->port.supported[idx] &
11114                             SUPPORTED_100baseT_Full) {
11115                                 bp->link_params.req_line_speed[idx] =
11116                                         SPEED_100;
11117                                 bp->port.advertising[idx] |=
11118                                         (ADVERTISED_100baseT_Full |
11119                                          ADVERTISED_TP);
11120                         } else {
11121                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11122                                             link_config,
11123                                           bp->link_params.speed_cap_mask[idx]);
11124                                 return;
11125                         }
11126                         break;
11127
11128                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11129                         if (bp->port.supported[idx] &
11130                             SUPPORTED_100baseT_Half) {
11131                                 bp->link_params.req_line_speed[idx] =
11132                                                                 SPEED_100;
11133                                 bp->link_params.req_duplex[idx] =
11134                                                                 DUPLEX_HALF;
11135                                 bp->port.advertising[idx] |=
11136                                         (ADVERTISED_100baseT_Half |
11137                                          ADVERTISED_TP);
11138                         } else {
11139                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11140                                     link_config,
11141                                     bp->link_params.speed_cap_mask[idx]);
11142                                 return;
11143                         }
11144                         break;
11145
11146                 case PORT_FEATURE_LINK_SPEED_1G:
11147                         if (bp->port.supported[idx] &
11148                             SUPPORTED_1000baseT_Full) {
11149                                 bp->link_params.req_line_speed[idx] =
11150                                         SPEED_1000;
11151                                 bp->port.advertising[idx] |=
11152                                         (ADVERTISED_1000baseT_Full |
11153                                          ADVERTISED_TP);
11154                         } else if (bp->port.supported[idx] &
11155                                    SUPPORTED_1000baseKX_Full) {
11156                                 bp->link_params.req_line_speed[idx] =
11157                                         SPEED_1000;
11158                                 bp->port.advertising[idx] |=
11159                                         ADVERTISED_1000baseKX_Full;
11160                         } else {
11161                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11162                                     link_config,
11163                                     bp->link_params.speed_cap_mask[idx]);
11164                                 return;
11165                         }
11166                         break;
11167
11168                 case PORT_FEATURE_LINK_SPEED_2_5G:
11169                         if (bp->port.supported[idx] &
11170                             SUPPORTED_2500baseX_Full) {
11171                                 bp->link_params.req_line_speed[idx] =
11172                                         SPEED_2500;
11173                                 bp->port.advertising[idx] |=
11174                                         (ADVERTISED_2500baseX_Full |
11175                                                 ADVERTISED_TP);
11176                         } else {
11177                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11178                                     link_config,
11179                                     bp->link_params.speed_cap_mask[idx]);
11180                                 return;
11181                         }
11182                         break;
11183
11184                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11185                         if (bp->port.supported[idx] &
11186                             SUPPORTED_10000baseT_Full) {
11187                                 bp->link_params.req_line_speed[idx] =
11188                                         SPEED_10000;
11189                                 bp->port.advertising[idx] |=
11190                                         (ADVERTISED_10000baseT_Full |
11191                                                 ADVERTISED_FIBRE);
11192                         } else if (bp->port.supported[idx] &
11193                                    SUPPORTED_10000baseKR_Full) {
11194                                 bp->link_params.req_line_speed[idx] =
11195                                         SPEED_10000;
11196                                 bp->port.advertising[idx] |=
11197                                         (ADVERTISED_10000baseKR_Full |
11198                                                 ADVERTISED_FIBRE);
11199                         } else {
11200                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11201                                     link_config,
11202                                     bp->link_params.speed_cap_mask[idx]);
11203                                 return;
11204                         }
11205                         break;
11206                 case PORT_FEATURE_LINK_SPEED_20G:
11207                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11208
11209                         break;
11210                 default:
11211                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11212                                   link_config);
11213                                 bp->link_params.req_line_speed[idx] =
11214                                                         SPEED_AUTO_NEG;
11215                                 bp->port.advertising[idx] =
11216                                                 bp->port.supported[idx];
11217                         break;
11218                 }
11219
11220                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11221                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11222                 if (bp->link_params.req_flow_ctrl[idx] ==
11223                     BNX2X_FLOW_CTRL_AUTO) {
11224                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11225                                 bp->link_params.req_flow_ctrl[idx] =
11226                                                         BNX2X_FLOW_CTRL_NONE;
11227                         else
11228                                 bnx2x_set_requested_fc(bp);
11229                 }
11230
11231                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11232                                bp->link_params.req_line_speed[idx],
11233                                bp->link_params.req_duplex[idx],
11234                                bp->link_params.req_flow_ctrl[idx],
11235                                bp->port.advertising[idx]);
11236         }
11237 }
11238
11239 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11240 {
11241         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11242         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11243         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11244         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11245 }
11246
11247 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11248 {
11249         int port = BP_PORT(bp);
11250         u32 config;
11251         u32 ext_phy_type, ext_phy_config, eee_mode;
11252
11253         bp->link_params.bp = bp;
11254         bp->link_params.port = port;
11255
11256         bp->link_params.lane_config =
11257                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11258
11259         bp->link_params.speed_cap_mask[0] =
11260                 SHMEM_RD(bp,
11261                          dev_info.port_hw_config[port].speed_capability_mask) &
11262                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11263         bp->link_params.speed_cap_mask[1] =
11264                 SHMEM_RD(bp,
11265                          dev_info.port_hw_config[port].speed_capability_mask2) &
11266                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11267         bp->port.link_config[0] =
11268                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11269
11270         bp->port.link_config[1] =
11271                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11272
11273         bp->link_params.multi_phy_config =
11274                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11275         /* If the device is capable of WoL, set the default state according
11276          * to the HW
11277          */
11278         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11279         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11280                    (config & PORT_FEATURE_WOL_ENABLED));
11281
11282         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11283             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11284                 bp->flags |= NO_ISCSI_FLAG;
11285         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11286             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11287                 bp->flags |= NO_FCOE_FLAG;
11288
11289         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11290                        bp->link_params.lane_config,
11291                        bp->link_params.speed_cap_mask[0],
11292                        bp->port.link_config[0]);
11293
11294         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11295                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11296         bnx2x_phy_probe(&bp->link_params);
11297         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11298
11299         bnx2x_link_settings_requested(bp);
11300
11301         /*
11302          * If connected directly, work with the internal PHY, otherwise, work
11303          * with the external PHY
11304          */
11305         ext_phy_config =
11306                 SHMEM_RD(bp,
11307                          dev_info.port_hw_config[port].external_phy_config);
11308         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11309         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11310                 bp->mdio.prtad = bp->port.phy_addr;
11311
11312         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11313                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11314                 bp->mdio.prtad =
11315                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11316
11317         /* Configure link feature according to nvram value */
11318         eee_mode = (((SHMEM_RD(bp, dev_info.
11319                       port_feature_config[port].eee_power_mode)) &
11320                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11321                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11322         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11323                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11324                                            EEE_MODE_ENABLE_LPI |
11325                                            EEE_MODE_OUTPUT_TIME;
11326         } else {
11327                 bp->link_params.eee_mode = 0;
11328         }
11329 }
11330
11331 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11332 {
11333         u32 no_flags = NO_ISCSI_FLAG;
11334         int port = BP_PORT(bp);
11335         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11336                                 drv_lic_key[port].max_iscsi_conn);
11337
11338         if (!CNIC_SUPPORT(bp)) {
11339                 bp->flags |= no_flags;
11340                 return;
11341         }
11342
11343         /* Get the number of maximum allowed iSCSI connections */
11344         bp->cnic_eth_dev.max_iscsi_conn =
11345                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11346                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11347
11348         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11349                        bp->cnic_eth_dev.max_iscsi_conn);
11350
11351         /*
11352          * If maximum allowed number of connections is zero -
11353          * disable the feature.
11354          */
11355         if (!bp->cnic_eth_dev.max_iscsi_conn)
11356                 bp->flags |= no_flags;
11357 }
11358
11359 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11360 {
11361         /* Port info */
11362         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11363                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11364         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11365                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11366
11367         /* Node info */
11368         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11369                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11370         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11371                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11372 }
11373
11374 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11375 {
11376         u8 count = 0;
11377
11378         if (IS_MF(bp)) {
11379                 u8 fid;
11380
11381                 /* iterate over absolute function ids for this path: */
11382                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11383                         if (IS_MF_SD(bp)) {
11384                                 u32 cfg = MF_CFG_RD(bp,
11385                                                     func_mf_config[fid].config);
11386
11387                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11388                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11389                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11390                                         count++;
11391                         } else {
11392                                 u32 cfg = MF_CFG_RD(bp,
11393                                                     func_ext_config[fid].
11394                                                                       func_cfg);
11395
11396                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11397                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11398                                         count++;
11399                         }
11400                 }
11401         } else { /* SF */
11402                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11403
11404                 for (port = 0; port < port_cnt; port++) {
11405                         u32 lic = SHMEM_RD(bp,
11406                                            drv_lic_key[port].max_fcoe_conn) ^
11407                                   FW_ENCODE_32BIT_PATTERN;
11408                         if (lic)
11409                                 count++;
11410                 }
11411         }
11412
11413         return count;
11414 }
11415
11416 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11417 {
11418         int port = BP_PORT(bp);
11419         int func = BP_ABS_FUNC(bp);
11420         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11421                                 drv_lic_key[port].max_fcoe_conn);
11422         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11423
11424         if (!CNIC_SUPPORT(bp)) {
11425                 bp->flags |= NO_FCOE_FLAG;
11426                 return;
11427         }
11428
11429         /* Get the number of maximum allowed FCoE connections */
11430         bp->cnic_eth_dev.max_fcoe_conn =
11431                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11432                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11433
11434         /* Calculate the number of maximum allowed FCoE tasks */
11435         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11436
11437         /* check if FCoE resources must be shared between different functions */
11438         if (num_fcoe_func)
11439                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11440
11441         /* Read the WWN: */
11442         if (!IS_MF(bp)) {
11443                 /* Port info */
11444                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11445                         SHMEM_RD(bp,
11446                                  dev_info.port_hw_config[port].
11447                                  fcoe_wwn_port_name_upper);
11448                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11449                         SHMEM_RD(bp,
11450                                  dev_info.port_hw_config[port].
11451                                  fcoe_wwn_port_name_lower);
11452
11453                 /* Node info */
11454                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11455                         SHMEM_RD(bp,
11456                                  dev_info.port_hw_config[port].
11457                                  fcoe_wwn_node_name_upper);
11458                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11459                         SHMEM_RD(bp,
11460                                  dev_info.port_hw_config[port].
11461                                  fcoe_wwn_node_name_lower);
11462         } else if (!IS_MF_SD(bp)) {
11463                 /* Read the WWN info only if the FCoE feature is enabled for
11464                  * this function.
11465                  */
11466                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11467                         bnx2x_get_ext_wwn_info(bp, func);
11468         } else {
11469                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11470                         bnx2x_get_ext_wwn_info(bp, func);
11471         }
11472
11473         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11474
11475         /*
11476          * If maximum allowed number of connections is zero -
11477          * disable the feature.
11478          */
11479         if (!bp->cnic_eth_dev.max_fcoe_conn)
11480                 bp->flags |= NO_FCOE_FLAG;
11481 }
11482
11483 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11484 {
11485         /*
11486          * iSCSI may be dynamically disabled but reading
11487          * info here we will decrease memory usage by driver
11488          * if the feature is disabled for good
11489          */
11490         bnx2x_get_iscsi_info(bp);
11491         bnx2x_get_fcoe_info(bp);
11492 }
11493
11494 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11495 {
11496         u32 val, val2;
11497         int func = BP_ABS_FUNC(bp);
11498         int port = BP_PORT(bp);
11499         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11500         u8 *fip_mac = bp->fip_mac;
11501
11502         if (IS_MF(bp)) {
11503                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11504                  * FCoE MAC then the appropriate feature should be disabled.
11505                  * In non SD mode features configuration comes from struct
11506                  * func_ext_config.
11507                  */
11508                 if (!IS_MF_SD(bp)) {
11509                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11510                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11511                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11512                                                  iscsi_mac_addr_upper);
11513                                 val = MF_CFG_RD(bp, func_ext_config[func].
11514                                                 iscsi_mac_addr_lower);
11515                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11516                                 BNX2X_DEV_INFO
11517                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11518                         } else {
11519                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11520                         }
11521
11522                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11523                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11524                                                  fcoe_mac_addr_upper);
11525                                 val = MF_CFG_RD(bp, func_ext_config[func].
11526                                                 fcoe_mac_addr_lower);
11527                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11528                                 BNX2X_DEV_INFO
11529                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11530                         } else {
11531                                 bp->flags |= NO_FCOE_FLAG;
11532                         }
11533
11534                         bp->mf_ext_config = cfg;
11535
11536                 } else { /* SD MODE */
11537                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11538                                 /* use primary mac as iscsi mac */
11539                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11540
11541                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11542                                 BNX2X_DEV_INFO
11543                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11544                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11545                                 /* use primary mac as fip mac */
11546                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11547                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11548                                 BNX2X_DEV_INFO
11549                                         ("Read FIP MAC: %pM\n", fip_mac);
11550                         }
11551                 }
11552
11553                 /* If this is a storage-only interface, use SAN mac as
11554                  * primary MAC. Notice that for SD this is already the case,
11555                  * as the SAN mac was copied from the primary MAC.
11556                  */
11557                 if (IS_MF_FCOE_AFEX(bp))
11558                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11559         } else {
11560                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11561                                 iscsi_mac_upper);
11562                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11563                                iscsi_mac_lower);
11564                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11565
11566                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11567                                 fcoe_fip_mac_upper);
11568                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11569                                fcoe_fip_mac_lower);
11570                 bnx2x_set_mac_buf(fip_mac, val, val2);
11571         }
11572
11573         /* Disable iSCSI OOO if MAC configuration is invalid. */
11574         if (!is_valid_ether_addr(iscsi_mac)) {
11575                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11576                 eth_zero_addr(iscsi_mac);
11577         }
11578
11579         /* Disable FCoE if MAC configuration is invalid. */
11580         if (!is_valid_ether_addr(fip_mac)) {
11581                 bp->flags |= NO_FCOE_FLAG;
11582                 eth_zero_addr(bp->fip_mac);
11583         }
11584 }
11585
11586 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11587 {
11588         u32 val, val2;
11589         int func = BP_ABS_FUNC(bp);
11590         int port = BP_PORT(bp);
11591
11592         /* Zero primary MAC configuration */
11593         eth_zero_addr(bp->dev->dev_addr);
11594
11595         if (BP_NOMCP(bp)) {
11596                 BNX2X_ERROR("warning: random MAC workaround active\n");
11597                 eth_hw_addr_random(bp->dev);
11598         } else if (IS_MF(bp)) {
11599                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11600                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11601                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11602                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11603                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11604
11605                 if (CNIC_SUPPORT(bp))
11606                         bnx2x_get_cnic_mac_hwinfo(bp);
11607         } else {
11608                 /* in SF read MACs from port configuration */
11609                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11610                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11611                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11612
11613                 if (CNIC_SUPPORT(bp))
11614                         bnx2x_get_cnic_mac_hwinfo(bp);
11615         }
11616
11617         if (!BP_NOMCP(bp)) {
11618                 /* Read physical port identifier from shmem */
11619                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11620                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11621                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11622                 bp->flags |= HAS_PHYS_PORT_ID;
11623         }
11624
11625         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11626
11627         if (!is_valid_ether_addr(bp->dev->dev_addr))
11628                 dev_err(&bp->pdev->dev,
11629                         "bad Ethernet MAC address configuration: %pM\n"
11630                         "change it manually before bringing up the appropriate network interface\n",
11631                         bp->dev->dev_addr);
11632 }
11633
11634 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11635 {
11636         int tmp;
11637         u32 cfg;
11638
11639         if (IS_VF(bp))
11640                 return false;
11641
11642         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11643                 /* Take function: tmp = func */
11644                 tmp = BP_ABS_FUNC(bp);
11645                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11646                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11647         } else {
11648                 /* Take port: tmp = port */
11649                 tmp = BP_PORT(bp);
11650                 cfg = SHMEM_RD(bp,
11651                                dev_info.port_hw_config[tmp].generic_features);
11652                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11653         }
11654         return cfg;
11655 }
11656
11657 static void validate_set_si_mode(struct bnx2x *bp)
11658 {
11659         u8 func = BP_ABS_FUNC(bp);
11660         u32 val;
11661
11662         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11663
11664         /* check for legal mac (upper bytes) */
11665         if (val != 0xffff) {
11666                 bp->mf_mode = MULTI_FUNCTION_SI;
11667                 bp->mf_config[BP_VN(bp)] =
11668                         MF_CFG_RD(bp, func_mf_config[func].config);
11669         } else
11670                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11671 }
11672
11673 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11674 {
11675         int /*abs*/func = BP_ABS_FUNC(bp);
11676         int vn;
11677         u32 val = 0, val2 = 0;
11678         int rc = 0;
11679
11680         /* Validate that chip access is feasible */
11681         if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11682                 dev_err(&bp->pdev->dev,
11683                         "Chip read returns all Fs. Preventing probe from continuing\n");
11684                 return -EINVAL;
11685         }
11686
11687         bnx2x_get_common_hwinfo(bp);
11688
11689         /*
11690          * initialize IGU parameters
11691          */
11692         if (CHIP_IS_E1x(bp)) {
11693                 bp->common.int_block = INT_BLOCK_HC;
11694
11695                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11696                 bp->igu_base_sb = 0;
11697         } else {
11698                 bp->common.int_block = INT_BLOCK_IGU;
11699
11700                 /* do not allow device reset during IGU info processing */
11701                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11702
11703                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11704
11705                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11706                         int tout = 5000;
11707
11708                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11709
11710                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11711                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11712                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11713
11714                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11715                                 tout--;
11716                                 usleep_range(1000, 2000);
11717                         }
11718
11719                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11720                                 dev_err(&bp->pdev->dev,
11721                                         "FORCING Normal Mode failed!!!\n");
11722                                 bnx2x_release_hw_lock(bp,
11723                                                       HW_LOCK_RESOURCE_RESET);
11724                                 return -EPERM;
11725                         }
11726                 }
11727
11728                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11729                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11730                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11731                 } else
11732                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11733
11734                 rc = bnx2x_get_igu_cam_info(bp);
11735                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11736                 if (rc)
11737                         return rc;
11738         }
11739
11740         /*
11741          * set base FW non-default (fast path) status block id, this value is
11742          * used to initialize the fw_sb_id saved on the fp/queue structure to
11743          * determine the id used by the FW.
11744          */
11745         if (CHIP_IS_E1x(bp))
11746                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11747         else /*
11748               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11749               * the same queue are indicated on the same IGU SB). So we prefer
11750               * FW and IGU SBs to be the same value.
11751               */
11752                 bp->base_fw_ndsb = bp->igu_base_sb;
11753
11754         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11755                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11756                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11757
11758         /*
11759          * Initialize MF configuration
11760          */
11761
11762         bp->mf_ov = 0;
11763         bp->mf_mode = 0;
11764         bp->mf_sub_mode = 0;
11765         vn = BP_VN(bp);
11766
11767         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11768                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11769                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11770                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11771
11772                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11773                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11774                 else
11775                         bp->common.mf_cfg_base = bp->common.shmem_base +
11776                                 offsetof(struct shmem_region, func_mb) +
11777                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11778                 /*
11779                  * get mf configuration:
11780                  * 1. Existence of MF configuration
11781                  * 2. MAC address must be legal (check only upper bytes)
11782                  *    for  Switch-Independent mode;
11783                  *    OVLAN must be legal for Switch-Dependent mode
11784                  * 3. SF_MODE configures specific MF mode
11785                  */
11786                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11787                         /* get mf configuration */
11788                         val = SHMEM_RD(bp,
11789                                        dev_info.shared_feature_config.config);
11790                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11791
11792                         switch (val) {
11793                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11794                                 validate_set_si_mode(bp);
11795                                 break;
11796                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11797                                 if ((!CHIP_IS_E1x(bp)) &&
11798                                     (MF_CFG_RD(bp, func_mf_config[func].
11799                                                mac_upper) != 0xffff) &&
11800                                     (SHMEM2_HAS(bp,
11801                                                 afex_driver_support))) {
11802                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11803                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11804                                                 func_mf_config[func].config);
11805                                 } else {
11806                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11807                                 }
11808                                 break;
11809                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11810                                 /* get OV configuration */
11811                                 val = MF_CFG_RD(bp,
11812                                         func_mf_config[FUNC_0].e1hov_tag);
11813                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11814
11815                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11816                                         bp->mf_mode = MULTI_FUNCTION_SD;
11817                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11818                                                 func_mf_config[func].config);
11819                                 } else
11820                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11821                                 break;
11822                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
11823                                 bp->mf_mode = MULTI_FUNCTION_SD;
11824                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
11825                                 bp->mf_config[vn] =
11826                                         MF_CFG_RD(bp,
11827                                                   func_mf_config[func].config);
11828                                 break;
11829                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11830                                 bp->mf_config[vn] = 0;
11831                                 break;
11832                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
11833                                 val2 = SHMEM_RD(bp,
11834                                         dev_info.shared_hw_config.config_3);
11835                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
11836                                 switch (val2) {
11837                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
11838                                         validate_set_si_mode(bp);
11839                                         bp->mf_sub_mode =
11840                                                         SUB_MF_MODE_NPAR1_DOT_5;
11841                                         break;
11842                                 default:
11843                                         /* Unknown configuration */
11844                                         bp->mf_config[vn] = 0;
11845                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
11846                                                        val);
11847                                 }
11848                                 break;
11849                         default:
11850                                 /* Unknown configuration: reset mf_config */
11851                                 bp->mf_config[vn] = 0;
11852                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11853                         }
11854                 }
11855
11856                 BNX2X_DEV_INFO("%s function mode\n",
11857                                IS_MF(bp) ? "multi" : "single");
11858
11859                 switch (bp->mf_mode) {
11860                 case MULTI_FUNCTION_SD:
11861                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11862                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11863                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11864                                 bp->mf_ov = val;
11865                                 bp->path_has_ovlan = true;
11866
11867                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11868                                                func, bp->mf_ov, bp->mf_ov);
11869                         } else if (bp->mf_sub_mode == SUB_MF_MODE_UFP) {
11870                                 dev_err(&bp->pdev->dev,
11871                                         "Unexpected - no valid MF OV for func %d in UFP mode\n",
11872                                         func);
11873                                 bp->path_has_ovlan = true;
11874                         } else {
11875                                 dev_err(&bp->pdev->dev,
11876                                         "No valid MF OV for func %d, aborting\n",
11877                                         func);
11878                                 return -EPERM;
11879                         }
11880                         break;
11881                 case MULTI_FUNCTION_AFEX:
11882                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11883                         break;
11884                 case MULTI_FUNCTION_SI:
11885                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11886                                        func);
11887                         break;
11888                 default:
11889                         if (vn) {
11890                                 dev_err(&bp->pdev->dev,
11891                                         "VN %d is in a single function mode, aborting\n",
11892                                         vn);
11893                                 return -EPERM;
11894                         }
11895                         break;
11896                 }
11897
11898                 /* check if other port on the path needs ovlan:
11899                  * Since MF configuration is shared between ports
11900                  * Possible mixed modes are only
11901                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11902                  */
11903                 if (CHIP_MODE_IS_4_PORT(bp) &&
11904                     !bp->path_has_ovlan &&
11905                     !IS_MF(bp) &&
11906                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11907                         u8 other_port = !BP_PORT(bp);
11908                         u8 other_func = BP_PATH(bp) + 2*other_port;
11909                         val = MF_CFG_RD(bp,
11910                                         func_mf_config[other_func].e1hov_tag);
11911                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11912                                 bp->path_has_ovlan = true;
11913                 }
11914         }
11915
11916         /* adjust igu_sb_cnt to MF for E1H */
11917         if (CHIP_IS_E1H(bp) && IS_MF(bp))
11918                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11919
11920         /* port info */
11921         bnx2x_get_port_hwinfo(bp);
11922
11923         /* Get MAC addresses */
11924         bnx2x_get_mac_hwinfo(bp);
11925
11926         bnx2x_get_cnic_info(bp);
11927
11928         return rc;
11929 }
11930
11931 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11932 {
11933         int cnt, i, block_end, rodi;
11934         char vpd_start[BNX2X_VPD_LEN+1];
11935         char str_id_reg[VENDOR_ID_LEN+1];
11936         char str_id_cap[VENDOR_ID_LEN+1];
11937         char *vpd_data;
11938         char *vpd_extended_data = NULL;
11939         u8 len;
11940
11941         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11942         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11943
11944         if (cnt < BNX2X_VPD_LEN)
11945                 goto out_not_found;
11946
11947         /* VPD RO tag should be first tag after identifier string, hence
11948          * we should be able to find it in first BNX2X_VPD_LEN chars
11949          */
11950         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11951                              PCI_VPD_LRDT_RO_DATA);
11952         if (i < 0)
11953                 goto out_not_found;
11954
11955         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11956                     pci_vpd_lrdt_size(&vpd_start[i]);
11957
11958         i += PCI_VPD_LRDT_TAG_SIZE;
11959
11960         if (block_end > BNX2X_VPD_LEN) {
11961                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11962                 if (vpd_extended_data  == NULL)
11963                         goto out_not_found;
11964
11965                 /* read rest of vpd image into vpd_extended_data */
11966                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11967                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11968                                    block_end - BNX2X_VPD_LEN,
11969                                    vpd_extended_data + BNX2X_VPD_LEN);
11970                 if (cnt < (block_end - BNX2X_VPD_LEN))
11971                         goto out_not_found;
11972                 vpd_data = vpd_extended_data;
11973         } else
11974                 vpd_data = vpd_start;
11975
11976         /* now vpd_data holds full vpd content in both cases */
11977
11978         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11979                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11980         if (rodi < 0)
11981                 goto out_not_found;
11982
11983         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11984
11985         if (len != VENDOR_ID_LEN)
11986                 goto out_not_found;
11987
11988         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11989
11990         /* vendor specific info */
11991         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11992         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11993         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11994             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11995
11996                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11997                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11998                 if (rodi >= 0) {
11999                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12000
12001                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12002
12003                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12004                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12005                                 bp->fw_ver[len] = ' ';
12006                         }
12007                 }
12008                 kfree(vpd_extended_data);
12009                 return;
12010         }
12011 out_not_found:
12012         kfree(vpd_extended_data);
12013         return;
12014 }
12015
12016 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12017 {
12018         u32 flags = 0;
12019
12020         if (CHIP_REV_IS_FPGA(bp))
12021                 SET_FLAGS(flags, MODE_FPGA);
12022         else if (CHIP_REV_IS_EMUL(bp))
12023                 SET_FLAGS(flags, MODE_EMUL);
12024         else
12025                 SET_FLAGS(flags, MODE_ASIC);
12026
12027         if (CHIP_MODE_IS_4_PORT(bp))
12028                 SET_FLAGS(flags, MODE_PORT4);
12029         else
12030                 SET_FLAGS(flags, MODE_PORT2);
12031
12032         if (CHIP_IS_E2(bp))
12033                 SET_FLAGS(flags, MODE_E2);
12034         else if (CHIP_IS_E3(bp)) {
12035                 SET_FLAGS(flags, MODE_E3);
12036                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12037                         SET_FLAGS(flags, MODE_E3_A0);
12038                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12039                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12040         }
12041
12042         if (IS_MF(bp)) {
12043                 SET_FLAGS(flags, MODE_MF);
12044                 switch (bp->mf_mode) {
12045                 case MULTI_FUNCTION_SD:
12046                         SET_FLAGS(flags, MODE_MF_SD);
12047                         break;
12048                 case MULTI_FUNCTION_SI:
12049                         SET_FLAGS(flags, MODE_MF_SI);
12050                         break;
12051                 case MULTI_FUNCTION_AFEX:
12052                         SET_FLAGS(flags, MODE_MF_AFEX);
12053                         break;
12054                 }
12055         } else
12056                 SET_FLAGS(flags, MODE_SF);
12057
12058 #if defined(__LITTLE_ENDIAN)
12059         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12060 #else /*(__BIG_ENDIAN)*/
12061         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12062 #endif
12063         INIT_MODE_FLAGS(bp) = flags;
12064 }
12065
12066 static int bnx2x_init_bp(struct bnx2x *bp)
12067 {
12068         int func;
12069         int rc;
12070
12071         mutex_init(&bp->port.phy_mutex);
12072         mutex_init(&bp->fw_mb_mutex);
12073         mutex_init(&bp->drv_info_mutex);
12074         sema_init(&bp->stats_lock, 1);
12075         bp->drv_info_mng_owner = false;
12076
12077         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12078         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12079         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12080         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12081         if (IS_PF(bp)) {
12082                 rc = bnx2x_get_hwinfo(bp);
12083                 if (rc)
12084                         return rc;
12085         } else {
12086                 eth_zero_addr(bp->dev->dev_addr);
12087         }
12088
12089         bnx2x_set_modes_bitmap(bp);
12090
12091         rc = bnx2x_alloc_mem_bp(bp);
12092         if (rc)
12093                 return rc;
12094
12095         bnx2x_read_fwinfo(bp);
12096
12097         func = BP_FUNC(bp);
12098
12099         /* need to reset chip if undi was active */
12100         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12101                 /* init fw_seq */
12102                 bp->fw_seq =
12103                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12104                                                         DRV_MSG_SEQ_NUMBER_MASK;
12105                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12106
12107                 rc = bnx2x_prev_unload(bp);
12108                 if (rc) {
12109                         bnx2x_free_mem_bp(bp);
12110                         return rc;
12111                 }
12112         }
12113
12114         if (CHIP_REV_IS_FPGA(bp))
12115                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12116
12117         if (BP_NOMCP(bp) && (func == 0))
12118                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12119
12120         bp->disable_tpa = disable_tpa;
12121         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12122         /* Reduce memory usage in kdump environment by disabling TPA */
12123         bp->disable_tpa |= is_kdump_kernel();
12124
12125         /* Set TPA flags */
12126         if (bp->disable_tpa) {
12127                 bp->dev->hw_features &= ~NETIF_F_LRO;
12128                 bp->dev->features &= ~NETIF_F_LRO;
12129         }
12130
12131         if (CHIP_IS_E1(bp))
12132                 bp->dropless_fc = 0;
12133         else
12134                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12135
12136         bp->mrrs = mrrs;
12137
12138         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12139         if (IS_VF(bp))
12140                 bp->rx_ring_size = MAX_RX_AVAIL;
12141
12142         /* make sure that the numbers are in the right granularity */
12143         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12144         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12145
12146         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12147
12148         init_timer(&bp->timer);
12149         bp->timer.expires = jiffies + bp->current_interval;
12150         bp->timer.data = (unsigned long) bp;
12151         bp->timer.function = bnx2x_timer;
12152
12153         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12154             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12155             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12156             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12157                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12158                 bnx2x_dcbx_init_params(bp);
12159         } else {
12160                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12161         }
12162
12163         if (CHIP_IS_E1x(bp))
12164                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12165         else
12166                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12167
12168         /* multiple tx priority */
12169         if (IS_VF(bp))
12170                 bp->max_cos = 1;
12171         else if (CHIP_IS_E1x(bp))
12172                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12173         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12174                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12175         else if (CHIP_IS_E3B0(bp))
12176                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12177         else
12178                 BNX2X_ERR("unknown chip %x revision %x\n",
12179                           CHIP_NUM(bp), CHIP_REV(bp));
12180         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12181
12182         /* We need at least one default status block for slow-path events,
12183          * second status block for the L2 queue, and a third status block for
12184          * CNIC if supported.
12185          */
12186         if (IS_VF(bp))
12187                 bp->min_msix_vec_cnt = 1;
12188         else if (CNIC_SUPPORT(bp))
12189                 bp->min_msix_vec_cnt = 3;
12190         else /* PF w/o cnic */
12191                 bp->min_msix_vec_cnt = 2;
12192         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12193
12194         bp->dump_preset_idx = 1;
12195
12196         if (CHIP_IS_E3B0(bp))
12197                 bp->flags |= PTP_SUPPORTED;
12198
12199         return rc;
12200 }
12201
12202 /****************************************************************************
12203 * General service functions
12204 ****************************************************************************/
12205
12206 /*
12207  * net_device service functions
12208  */
12209
12210 /* called with rtnl_lock */
12211 static int bnx2x_open(struct net_device *dev)
12212 {
12213         struct bnx2x *bp = netdev_priv(dev);
12214         int rc;
12215
12216         bp->stats_init = true;
12217
12218         netif_carrier_off(dev);
12219
12220         bnx2x_set_power_state(bp, PCI_D0);
12221
12222         /* If parity had happen during the unload, then attentions
12223          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12224          * want the first function loaded on the current engine to
12225          * complete the recovery.
12226          * Parity recovery is only relevant for PF driver.
12227          */
12228         if (IS_PF(bp)) {
12229                 int other_engine = BP_PATH(bp) ? 0 : 1;
12230                 bool other_load_status, load_status;
12231                 bool global = false;
12232
12233                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12234                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12235                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12236                     bnx2x_chk_parity_attn(bp, &global, true)) {
12237                         do {
12238                                 /* If there are attentions and they are in a
12239                                  * global blocks, set the GLOBAL_RESET bit
12240                                  * regardless whether it will be this function
12241                                  * that will complete the recovery or not.
12242                                  */
12243                                 if (global)
12244                                         bnx2x_set_reset_global(bp);
12245
12246                                 /* Only the first function on the current
12247                                  * engine should try to recover in open. In case
12248                                  * of attentions in global blocks only the first
12249                                  * in the chip should try to recover.
12250                                  */
12251                                 if ((!load_status &&
12252                                      (!global || !other_load_status)) &&
12253                                       bnx2x_trylock_leader_lock(bp) &&
12254                                       !bnx2x_leader_reset(bp)) {
12255                                         netdev_info(bp->dev,
12256                                                     "Recovered in open\n");
12257                                         break;
12258                                 }
12259
12260                                 /* recovery has failed... */
12261                                 bnx2x_set_power_state(bp, PCI_D3hot);
12262                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12263
12264                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12265                                           "If you still see this message after a few retries then power cycle is required.\n");
12266
12267                                 return -EAGAIN;
12268                         } while (0);
12269                 }
12270         }
12271
12272         bp->recovery_state = BNX2X_RECOVERY_DONE;
12273         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12274         if (rc)
12275                 return rc;
12276         return 0;
12277 }
12278
12279 /* called with rtnl_lock */
12280 static int bnx2x_close(struct net_device *dev)
12281 {
12282         struct bnx2x *bp = netdev_priv(dev);
12283
12284         /* Unload the driver, release IRQs */
12285         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12286
12287         return 0;
12288 }
12289
12290 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12291                                       struct bnx2x_mcast_ramrod_params *p)
12292 {
12293         int mc_count = netdev_mc_count(bp->dev);
12294         struct bnx2x_mcast_list_elem *mc_mac =
12295                 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12296         struct netdev_hw_addr *ha;
12297
12298         if (!mc_mac)
12299                 return -ENOMEM;
12300
12301         INIT_LIST_HEAD(&p->mcast_list);
12302
12303         netdev_for_each_mc_addr(ha, bp->dev) {
12304                 mc_mac->mac = bnx2x_mc_addr(ha);
12305                 list_add_tail(&mc_mac->link, &p->mcast_list);
12306                 mc_mac++;
12307         }
12308
12309         p->mcast_list_len = mc_count;
12310
12311         return 0;
12312 }
12313
12314 static void bnx2x_free_mcast_macs_list(
12315         struct bnx2x_mcast_ramrod_params *p)
12316 {
12317         struct bnx2x_mcast_list_elem *mc_mac =
12318                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12319                                  link);
12320
12321         WARN_ON(!mc_mac);
12322         kfree(mc_mac);
12323 }
12324
12325 /**
12326  * bnx2x_set_uc_list - configure a new unicast MACs list.
12327  *
12328  * @bp: driver handle
12329  *
12330  * We will use zero (0) as a MAC type for these MACs.
12331  */
12332 static int bnx2x_set_uc_list(struct bnx2x *bp)
12333 {
12334         int rc;
12335         struct net_device *dev = bp->dev;
12336         struct netdev_hw_addr *ha;
12337         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12338         unsigned long ramrod_flags = 0;
12339
12340         /* First schedule a cleanup up of old configuration */
12341         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12342         if (rc < 0) {
12343                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12344                 return rc;
12345         }
12346
12347         netdev_for_each_uc_addr(ha, dev) {
12348                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12349                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12350                 if (rc == -EEXIST) {
12351                         DP(BNX2X_MSG_SP,
12352                            "Failed to schedule ADD operations: %d\n", rc);
12353                         /* do not treat adding same MAC as error */
12354                         rc = 0;
12355
12356                 } else if (rc < 0) {
12357
12358                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12359                                   rc);
12360                         return rc;
12361                 }
12362         }
12363
12364         /* Execute the pending commands */
12365         __set_bit(RAMROD_CONT, &ramrod_flags);
12366         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12367                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12368 }
12369
12370 static int bnx2x_set_mc_list(struct bnx2x *bp)
12371 {
12372         struct net_device *dev = bp->dev;
12373         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12374         int rc = 0;
12375
12376         rparam.mcast_obj = &bp->mcast_obj;
12377
12378         /* first, clear all configured multicast MACs */
12379         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12380         if (rc < 0) {
12381                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12382                 return rc;
12383         }
12384
12385         /* then, configure a new MACs list */
12386         if (netdev_mc_count(dev)) {
12387                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12388                 if (rc) {
12389                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12390                                   rc);
12391                         return rc;
12392                 }
12393
12394                 /* Now add the new MACs */
12395                 rc = bnx2x_config_mcast(bp, &rparam,
12396                                         BNX2X_MCAST_CMD_ADD);
12397                 if (rc < 0)
12398                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12399                                   rc);
12400
12401                 bnx2x_free_mcast_macs_list(&rparam);
12402         }
12403
12404         return rc;
12405 }
12406
12407 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12408 static void bnx2x_set_rx_mode(struct net_device *dev)
12409 {
12410         struct bnx2x *bp = netdev_priv(dev);
12411
12412         if (bp->state != BNX2X_STATE_OPEN) {
12413                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12414                 return;
12415         } else {
12416                 /* Schedule an SP task to handle rest of change */
12417                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12418                                        NETIF_MSG_IFUP);
12419         }
12420 }
12421
12422 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12423 {
12424         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12425
12426         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12427
12428         netif_addr_lock_bh(bp->dev);
12429
12430         if (bp->dev->flags & IFF_PROMISC) {
12431                 rx_mode = BNX2X_RX_MODE_PROMISC;
12432         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12433                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12434                     CHIP_IS_E1(bp))) {
12435                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12436         } else {
12437                 if (IS_PF(bp)) {
12438                         /* some multicasts */
12439                         if (bnx2x_set_mc_list(bp) < 0)
12440                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12441
12442                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12443                         netif_addr_unlock_bh(bp->dev);
12444                         if (bnx2x_set_uc_list(bp) < 0)
12445                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12446                         netif_addr_lock_bh(bp->dev);
12447                 } else {
12448                         /* configuring mcast to a vf involves sleeping (when we
12449                          * wait for the pf's response).
12450                          */
12451                         bnx2x_schedule_sp_rtnl(bp,
12452                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12453                 }
12454         }
12455
12456         bp->rx_mode = rx_mode;
12457         /* handle ISCSI SD mode */
12458         if (IS_MF_ISCSI_ONLY(bp))
12459                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12460
12461         /* Schedule the rx_mode command */
12462         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12463                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12464                 netif_addr_unlock_bh(bp->dev);
12465                 return;
12466         }
12467
12468         if (IS_PF(bp)) {
12469                 bnx2x_set_storm_rx_mode(bp);
12470                 netif_addr_unlock_bh(bp->dev);
12471         } else {
12472                 /* VF will need to request the PF to make this change, and so
12473                  * the VF needs to release the bottom-half lock prior to the
12474                  * request (as it will likely require sleep on the VF side)
12475                  */
12476                 netif_addr_unlock_bh(bp->dev);
12477                 bnx2x_vfpf_storm_rx_mode(bp);
12478         }
12479 }
12480
12481 /* called with rtnl_lock */
12482 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12483                            int devad, u16 addr)
12484 {
12485         struct bnx2x *bp = netdev_priv(netdev);
12486         u16 value;
12487         int rc;
12488
12489         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12490            prtad, devad, addr);
12491
12492         /* The HW expects different devad if CL22 is used */
12493         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12494
12495         bnx2x_acquire_phy_lock(bp);
12496         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12497         bnx2x_release_phy_lock(bp);
12498         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12499
12500         if (!rc)
12501                 rc = value;
12502         return rc;
12503 }
12504
12505 /* called with rtnl_lock */
12506 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12507                             u16 addr, u16 value)
12508 {
12509         struct bnx2x *bp = netdev_priv(netdev);
12510         int rc;
12511
12512         DP(NETIF_MSG_LINK,
12513            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12514            prtad, devad, addr, value);
12515
12516         /* The HW expects different devad if CL22 is used */
12517         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12518
12519         bnx2x_acquire_phy_lock(bp);
12520         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12521         bnx2x_release_phy_lock(bp);
12522         return rc;
12523 }
12524
12525 /* called with rtnl_lock */
12526 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12527 {
12528         struct bnx2x *bp = netdev_priv(dev);
12529         struct mii_ioctl_data *mdio = if_mii(ifr);
12530
12531         if (!netif_running(dev))
12532                 return -EAGAIN;
12533
12534         switch (cmd) {
12535         case SIOCSHWTSTAMP:
12536                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12537         default:
12538                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12539                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12540                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12541         }
12542 }
12543
12544 #ifdef CONFIG_NET_POLL_CONTROLLER
12545 static void poll_bnx2x(struct net_device *dev)
12546 {
12547         struct bnx2x *bp = netdev_priv(dev);
12548         int i;
12549
12550         for_each_eth_queue(bp, i) {
12551                 struct bnx2x_fastpath *fp = &bp->fp[i];
12552                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12553         }
12554 }
12555 #endif
12556
12557 static int bnx2x_validate_addr(struct net_device *dev)
12558 {
12559         struct bnx2x *bp = netdev_priv(dev);
12560
12561         /* query the bulletin board for mac address configured by the PF */
12562         if (IS_VF(bp))
12563                 bnx2x_sample_bulletin(bp);
12564
12565         if (!is_valid_ether_addr(dev->dev_addr)) {
12566                 BNX2X_ERR("Non-valid Ethernet address\n");
12567                 return -EADDRNOTAVAIL;
12568         }
12569         return 0;
12570 }
12571
12572 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12573                                   struct netdev_phys_item_id *ppid)
12574 {
12575         struct bnx2x *bp = netdev_priv(netdev);
12576
12577         if (!(bp->flags & HAS_PHYS_PORT_ID))
12578                 return -EOPNOTSUPP;
12579
12580         ppid->id_len = sizeof(bp->phys_port_id);
12581         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12582
12583         return 0;
12584 }
12585
12586 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12587                                               struct net_device *dev,
12588                                               netdev_features_t features)
12589 {
12590         features = vlan_features_check(skb, features);
12591         return vxlan_features_check(skb, features);
12592 }
12593
12594 static const struct net_device_ops bnx2x_netdev_ops = {
12595         .ndo_open               = bnx2x_open,
12596         .ndo_stop               = bnx2x_close,
12597         .ndo_start_xmit         = bnx2x_start_xmit,
12598         .ndo_select_queue       = bnx2x_select_queue,
12599         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12600         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12601         .ndo_validate_addr      = bnx2x_validate_addr,
12602         .ndo_do_ioctl           = bnx2x_ioctl,
12603         .ndo_change_mtu         = bnx2x_change_mtu,
12604         .ndo_fix_features       = bnx2x_fix_features,
12605         .ndo_set_features       = bnx2x_set_features,
12606         .ndo_tx_timeout         = bnx2x_tx_timeout,
12607 #ifdef CONFIG_NET_POLL_CONTROLLER
12608         .ndo_poll_controller    = poll_bnx2x,
12609 #endif
12610         .ndo_setup_tc           = bnx2x_setup_tc,
12611 #ifdef CONFIG_BNX2X_SRIOV
12612         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12613         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12614         .ndo_get_vf_config      = bnx2x_get_vf_config,
12615 #endif
12616 #ifdef NETDEV_FCOE_WWNN
12617         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12618 #endif
12619
12620 #ifdef CONFIG_NET_RX_BUSY_POLL
12621         .ndo_busy_poll          = bnx2x_low_latency_recv,
12622 #endif
12623         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
12624         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
12625         .ndo_features_check     = bnx2x_features_check,
12626 };
12627
12628 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12629 {
12630         struct device *dev = &bp->pdev->dev;
12631
12632         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12633             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12634                 dev_err(dev, "System does not support DMA, aborting\n");
12635                 return -EIO;
12636         }
12637
12638         return 0;
12639 }
12640
12641 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12642 {
12643         if (bp->flags & AER_ENABLED) {
12644                 pci_disable_pcie_error_reporting(bp->pdev);
12645                 bp->flags &= ~AER_ENABLED;
12646         }
12647 }
12648
12649 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12650                           struct net_device *dev, unsigned long board_type)
12651 {
12652         int rc;
12653         u32 pci_cfg_dword;
12654         bool chip_is_e1x = (board_type == BCM57710 ||
12655                             board_type == BCM57711 ||
12656                             board_type == BCM57711E);
12657
12658         SET_NETDEV_DEV(dev, &pdev->dev);
12659
12660         bp->dev = dev;
12661         bp->pdev = pdev;
12662
12663         rc = pci_enable_device(pdev);
12664         if (rc) {
12665                 dev_err(&bp->pdev->dev,
12666                         "Cannot enable PCI device, aborting\n");
12667                 goto err_out;
12668         }
12669
12670         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12671                 dev_err(&bp->pdev->dev,
12672                         "Cannot find PCI device base address, aborting\n");
12673                 rc = -ENODEV;
12674                 goto err_out_disable;
12675         }
12676
12677         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12678                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12679                 rc = -ENODEV;
12680                 goto err_out_disable;
12681         }
12682
12683         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12684         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12685             PCICFG_REVESION_ID_ERROR_VAL) {
12686                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12687                 rc = -ENODEV;
12688                 goto err_out_disable;
12689         }
12690
12691         if (atomic_read(&pdev->enable_cnt) == 1) {
12692                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12693                 if (rc) {
12694                         dev_err(&bp->pdev->dev,
12695                                 "Cannot obtain PCI resources, aborting\n");
12696                         goto err_out_disable;
12697                 }
12698
12699                 pci_set_master(pdev);
12700                 pci_save_state(pdev);
12701         }
12702
12703         if (IS_PF(bp)) {
12704                 if (!pdev->pm_cap) {
12705                         dev_err(&bp->pdev->dev,
12706                                 "Cannot find power management capability, aborting\n");
12707                         rc = -EIO;
12708                         goto err_out_release;
12709                 }
12710         }
12711
12712         if (!pci_is_pcie(pdev)) {
12713                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12714                 rc = -EIO;
12715                 goto err_out_release;
12716         }
12717
12718         rc = bnx2x_set_coherency_mask(bp);
12719         if (rc)
12720                 goto err_out_release;
12721
12722         dev->mem_start = pci_resource_start(pdev, 0);
12723         dev->base_addr = dev->mem_start;
12724         dev->mem_end = pci_resource_end(pdev, 0);
12725
12726         dev->irq = pdev->irq;
12727
12728         bp->regview = pci_ioremap_bar(pdev, 0);
12729         if (!bp->regview) {
12730                 dev_err(&bp->pdev->dev,
12731                         "Cannot map register space, aborting\n");
12732                 rc = -ENOMEM;
12733                 goto err_out_release;
12734         }
12735
12736         /* In E1/E1H use pci device function given by kernel.
12737          * In E2/E3 read physical function from ME register since these chips
12738          * support Physical Device Assignment where kernel BDF maybe arbitrary
12739          * (depending on hypervisor).
12740          */
12741         if (chip_is_e1x) {
12742                 bp->pf_num = PCI_FUNC(pdev->devfn);
12743         } else {
12744                 /* chip is E2/3*/
12745                 pci_read_config_dword(bp->pdev,
12746                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12747                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12748                                   ME_REG_ABS_PF_NUM_SHIFT);
12749         }
12750         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12751
12752         /* clean indirect addresses */
12753         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12754                                PCICFG_VENDOR_ID_OFFSET);
12755
12756         /* Set PCIe reset type to fundamental for EEH recovery */
12757         pdev->needs_freset = 1;
12758
12759         /* AER (Advanced Error reporting) configuration */
12760         rc = pci_enable_pcie_error_reporting(pdev);
12761         if (!rc)
12762                 bp->flags |= AER_ENABLED;
12763         else
12764                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12765
12766         /*
12767          * Clean the following indirect addresses for all functions since it
12768          * is not used by the driver.
12769          */
12770         if (IS_PF(bp)) {
12771                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12772                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12773                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12774                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12775
12776                 if (chip_is_e1x) {
12777                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12778                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12779                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12780                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12781                 }
12782
12783                 /* Enable internal target-read (in case we are probed after PF
12784                  * FLR). Must be done prior to any BAR read access. Only for
12785                  * 57712 and up
12786                  */
12787                 if (!chip_is_e1x)
12788                         REG_WR(bp,
12789                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12790         }
12791
12792         dev->watchdog_timeo = TX_TIMEOUT;
12793
12794         dev->netdev_ops = &bnx2x_netdev_ops;
12795         bnx2x_set_ethtool_ops(bp, dev);
12796
12797         dev->priv_flags |= IFF_UNICAST_FLT;
12798
12799         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12800                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12801                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12802                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12803         if (!chip_is_e1x) {
12804                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12805                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12806                 dev->hw_enc_features =
12807                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12808                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12809                         NETIF_F_GSO_IPIP |
12810                         NETIF_F_GSO_SIT |
12811                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12812         }
12813
12814         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12815                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12816
12817         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12818         dev->features |= NETIF_F_HIGHDMA;
12819
12820         /* Add Loopback capability to the device */
12821         dev->hw_features |= NETIF_F_LOOPBACK;
12822
12823 #ifdef BCM_DCBNL
12824         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12825 #endif
12826
12827         /* get_port_hwinfo() will set prtad and mmds properly */
12828         bp->mdio.prtad = MDIO_PRTAD_NONE;
12829         bp->mdio.mmds = 0;
12830         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12831         bp->mdio.dev = dev;
12832         bp->mdio.mdio_read = bnx2x_mdio_read;
12833         bp->mdio.mdio_write = bnx2x_mdio_write;
12834
12835         return 0;
12836
12837 err_out_release:
12838         if (atomic_read(&pdev->enable_cnt) == 1)
12839                 pci_release_regions(pdev);
12840
12841 err_out_disable:
12842         pci_disable_device(pdev);
12843
12844 err_out:
12845         return rc;
12846 }
12847
12848 static int bnx2x_check_firmware(struct bnx2x *bp)
12849 {
12850         const struct firmware *firmware = bp->firmware;
12851         struct bnx2x_fw_file_hdr *fw_hdr;
12852         struct bnx2x_fw_file_section *sections;
12853         u32 offset, len, num_ops;
12854         __be16 *ops_offsets;
12855         int i;
12856         const u8 *fw_ver;
12857
12858         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12859                 BNX2X_ERR("Wrong FW size\n");
12860                 return -EINVAL;
12861         }
12862
12863         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12864         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12865
12866         /* Make sure none of the offsets and sizes make us read beyond
12867          * the end of the firmware data */
12868         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12869                 offset = be32_to_cpu(sections[i].offset);
12870                 len = be32_to_cpu(sections[i].len);
12871                 if (offset + len > firmware->size) {
12872                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12873                         return -EINVAL;
12874                 }
12875         }
12876
12877         /* Likewise for the init_ops offsets */
12878         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12879         ops_offsets = (__force __be16 *)(firmware->data + offset);
12880         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12881
12882         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12883                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12884                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12885                         return -EINVAL;
12886                 }
12887         }
12888
12889         /* Check FW version */
12890         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12891         fw_ver = firmware->data + offset;
12892         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12893             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12894             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12895             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12896                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12897                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12898                        BCM_5710_FW_MAJOR_VERSION,
12899                        BCM_5710_FW_MINOR_VERSION,
12900                        BCM_5710_FW_REVISION_VERSION,
12901                        BCM_5710_FW_ENGINEERING_VERSION);
12902                 return -EINVAL;
12903         }
12904
12905         return 0;
12906 }
12907
12908 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12909 {
12910         const __be32 *source = (const __be32 *)_source;
12911         u32 *target = (u32 *)_target;
12912         u32 i;
12913
12914         for (i = 0; i < n/4; i++)
12915                 target[i] = be32_to_cpu(source[i]);
12916 }
12917
12918 /*
12919    Ops array is stored in the following format:
12920    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12921  */
12922 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12923 {
12924         const __be32 *source = (const __be32 *)_source;
12925         struct raw_op *target = (struct raw_op *)_target;
12926         u32 i, j, tmp;
12927
12928         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12929                 tmp = be32_to_cpu(source[j]);
12930                 target[i].op = (tmp >> 24) & 0xff;
12931                 target[i].offset = tmp & 0xffffff;
12932                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12933         }
12934 }
12935
12936 /* IRO array is stored in the following format:
12937  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12938  */
12939 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12940 {
12941         const __be32 *source = (const __be32 *)_source;
12942         struct iro *target = (struct iro *)_target;
12943         u32 i, j, tmp;
12944
12945         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12946                 target[i].base = be32_to_cpu(source[j]);
12947                 j++;
12948                 tmp = be32_to_cpu(source[j]);
12949                 target[i].m1 = (tmp >> 16) & 0xffff;
12950                 target[i].m2 = tmp & 0xffff;
12951                 j++;
12952                 tmp = be32_to_cpu(source[j]);
12953                 target[i].m3 = (tmp >> 16) & 0xffff;
12954                 target[i].size = tmp & 0xffff;
12955                 j++;
12956         }
12957 }
12958
12959 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12960 {
12961         const __be16 *source = (const __be16 *)_source;
12962         u16 *target = (u16 *)_target;
12963         u32 i;
12964
12965         for (i = 0; i < n/2; i++)
12966                 target[i] = be16_to_cpu(source[i]);
12967 }
12968
12969 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12970 do {                                                                    \
12971         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12972         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12973         if (!bp->arr)                                                   \
12974                 goto lbl;                                               \
12975         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12976              (u8 *)bp->arr, len);                                       \
12977 } while (0)
12978
12979 static int bnx2x_init_firmware(struct bnx2x *bp)
12980 {
12981         const char *fw_file_name;
12982         struct bnx2x_fw_file_hdr *fw_hdr;
12983         int rc;
12984
12985         if (bp->firmware)
12986                 return 0;
12987
12988         if (CHIP_IS_E1(bp))
12989                 fw_file_name = FW_FILE_NAME_E1;
12990         else if (CHIP_IS_E1H(bp))
12991                 fw_file_name = FW_FILE_NAME_E1H;
12992         else if (!CHIP_IS_E1x(bp))
12993                 fw_file_name = FW_FILE_NAME_E2;
12994         else {
12995                 BNX2X_ERR("Unsupported chip revision\n");
12996                 return -EINVAL;
12997         }
12998         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12999
13000         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13001         if (rc) {
13002                 BNX2X_ERR("Can't load firmware file %s\n",
13003                           fw_file_name);
13004                 goto request_firmware_exit;
13005         }
13006
13007         rc = bnx2x_check_firmware(bp);
13008         if (rc) {
13009                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13010                 goto request_firmware_exit;
13011         }
13012
13013         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13014
13015         /* Initialize the pointers to the init arrays */
13016         /* Blob */
13017         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13018
13019         /* Opcodes */
13020         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13021
13022         /* Offsets */
13023         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13024                             be16_to_cpu_n);
13025
13026         /* STORMs firmware */
13027         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13028                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13029         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
13030                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13031         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13032                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13033         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
13034                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
13035         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13036                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13037         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
13038                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13039         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13040                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13041         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
13042                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13043         /* IRO */
13044         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13045
13046         return 0;
13047
13048 iro_alloc_err:
13049         kfree(bp->init_ops_offsets);
13050 init_offsets_alloc_err:
13051         kfree(bp->init_ops);
13052 init_ops_alloc_err:
13053         kfree(bp->init_data);
13054 request_firmware_exit:
13055         release_firmware(bp->firmware);
13056         bp->firmware = NULL;
13057
13058         return rc;
13059 }
13060
13061 static void bnx2x_release_firmware(struct bnx2x *bp)
13062 {
13063         kfree(bp->init_ops_offsets);
13064         kfree(bp->init_ops);
13065         kfree(bp->init_data);
13066         release_firmware(bp->firmware);
13067         bp->firmware = NULL;
13068 }
13069
13070 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13071         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13072         .init_hw_cmn      = bnx2x_init_hw_common,
13073         .init_hw_port     = bnx2x_init_hw_port,
13074         .init_hw_func     = bnx2x_init_hw_func,
13075
13076         .reset_hw_cmn     = bnx2x_reset_common,
13077         .reset_hw_port    = bnx2x_reset_port,
13078         .reset_hw_func    = bnx2x_reset_func,
13079
13080         .gunzip_init      = bnx2x_gunzip_init,
13081         .gunzip_end       = bnx2x_gunzip_end,
13082
13083         .init_fw          = bnx2x_init_firmware,
13084         .release_fw       = bnx2x_release_firmware,
13085 };
13086
13087 void bnx2x__init_func_obj(struct bnx2x *bp)
13088 {
13089         /* Prepare DMAE related driver resources */
13090         bnx2x_setup_dmae(bp);
13091
13092         bnx2x_init_func_obj(bp, &bp->func_obj,
13093                             bnx2x_sp(bp, func_rdata),
13094                             bnx2x_sp_mapping(bp, func_rdata),
13095                             bnx2x_sp(bp, func_afex_rdata),
13096                             bnx2x_sp_mapping(bp, func_afex_rdata),
13097                             &bnx2x_func_sp_drv);
13098 }
13099
13100 /* must be called after sriov-enable */
13101 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13102 {
13103         int cid_count = BNX2X_L2_MAX_CID(bp);
13104
13105         if (IS_SRIOV(bp))
13106                 cid_count += BNX2X_VF_CIDS;
13107
13108         if (CNIC_SUPPORT(bp))
13109                 cid_count += CNIC_CID_MAX;
13110
13111         return roundup(cid_count, QM_CID_ROUND);
13112 }
13113
13114 /**
13115  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13116  *
13117  * @dev:        pci device
13118  *
13119  */
13120 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13121 {
13122         int index;
13123         u16 control = 0;
13124
13125         /*
13126          * If MSI-X is not supported - return number of SBs needed to support
13127          * one fast path queue: one FP queue + SB for CNIC
13128          */
13129         if (!pdev->msix_cap) {
13130                 dev_info(&pdev->dev, "no msix capability found\n");
13131                 return 1 + cnic_cnt;
13132         }
13133         dev_info(&pdev->dev, "msix capability found\n");
13134
13135         /*
13136          * The value in the PCI configuration space is the index of the last
13137          * entry, namely one less than the actual size of the table, which is
13138          * exactly what we want to return from this function: number of all SBs
13139          * without the default SB.
13140          * For VFs there is no default SB, then we return (index+1).
13141          */
13142         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13143
13144         index = control & PCI_MSIX_FLAGS_QSIZE;
13145
13146         return index;
13147 }
13148
13149 static int set_max_cos_est(int chip_id)
13150 {
13151         switch (chip_id) {
13152         case BCM57710:
13153         case BCM57711:
13154         case BCM57711E:
13155                 return BNX2X_MULTI_TX_COS_E1X;
13156         case BCM57712:
13157         case BCM57712_MF:
13158                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13159         case BCM57800:
13160         case BCM57800_MF:
13161         case BCM57810:
13162         case BCM57810_MF:
13163         case BCM57840_4_10:
13164         case BCM57840_2_20:
13165         case BCM57840_O:
13166         case BCM57840_MFO:
13167         case BCM57840_MF:
13168         case BCM57811:
13169         case BCM57811_MF:
13170                 return BNX2X_MULTI_TX_COS_E3B0;
13171         case BCM57712_VF:
13172         case BCM57800_VF:
13173         case BCM57810_VF:
13174         case BCM57840_VF:
13175         case BCM57811_VF:
13176                 return 1;
13177         default:
13178                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13179                 return -ENODEV;
13180         }
13181 }
13182
13183 static int set_is_vf(int chip_id)
13184 {
13185         switch (chip_id) {
13186         case BCM57712_VF:
13187         case BCM57800_VF:
13188         case BCM57810_VF:
13189         case BCM57840_VF:
13190         case BCM57811_VF:
13191                 return true;
13192         default:
13193                 return false;
13194         }
13195 }
13196
13197 /* nig_tsgen registers relative address */
13198 #define tsgen_ctrl 0x0
13199 #define tsgen_freecount 0x10
13200 #define tsgen_synctime_t0 0x20
13201 #define tsgen_offset_t0 0x28
13202 #define tsgen_drift_t0 0x30
13203 #define tsgen_synctime_t1 0x58
13204 #define tsgen_offset_t1 0x60
13205 #define tsgen_drift_t1 0x68
13206
13207 /* FW workaround for setting drift */
13208 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13209                                           int best_val, int best_period)
13210 {
13211         struct bnx2x_func_state_params func_params = {NULL};
13212         struct bnx2x_func_set_timesync_params *set_timesync_params =
13213                 &func_params.params.set_timesync;
13214
13215         /* Prepare parameters for function state transitions */
13216         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13217         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13218
13219         func_params.f_obj = &bp->func_obj;
13220         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13221
13222         /* Function parameters */
13223         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13224         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13225         set_timesync_params->add_sub_drift_adjust_value =
13226                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13227         set_timesync_params->drift_adjust_value = best_val;
13228         set_timesync_params->drift_adjust_period = best_period;
13229
13230         return bnx2x_func_state_change(bp, &func_params);
13231 }
13232
13233 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13234 {
13235         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13236         int rc;
13237         int drift_dir = 1;
13238         int val, period, period1, period2, dif, dif1, dif2;
13239         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13240
13241         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13242
13243         if (!netif_running(bp->dev)) {
13244                 DP(BNX2X_MSG_PTP,
13245                    "PTP adjfreq called while the interface is down\n");
13246                 return -EFAULT;
13247         }
13248
13249         if (ppb < 0) {
13250                 ppb = -ppb;
13251                 drift_dir = 0;
13252         }
13253
13254         if (ppb == 0) {
13255                 best_val = 1;
13256                 best_period = 0x1FFFFFF;
13257         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13258                 best_val = 31;
13259                 best_period = 1;
13260         } else {
13261                 /* Changed not to allow val = 8, 16, 24 as these values
13262                  * are not supported in workaround.
13263                  */
13264                 for (val = 0; val <= 31; val++) {
13265                         if ((val & 0x7) == 0)
13266                                 continue;
13267                         period1 = val * 1000000 / ppb;
13268                         period2 = period1 + 1;
13269                         if (period1 != 0)
13270                                 dif1 = ppb - (val * 1000000 / period1);
13271                         else
13272                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13273                         if (dif1 < 0)
13274                                 dif1 = -dif1;
13275                         dif2 = ppb - (val * 1000000 / period2);
13276                         if (dif2 < 0)
13277                                 dif2 = -dif2;
13278                         dif = (dif1 < dif2) ? dif1 : dif2;
13279                         period = (dif1 < dif2) ? period1 : period2;
13280                         if (dif < best_dif) {
13281                                 best_dif = dif;
13282                                 best_val = val;
13283                                 best_period = period;
13284                         }
13285                 }
13286         }
13287
13288         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13289                                             best_period);
13290         if (rc) {
13291                 BNX2X_ERR("Failed to set drift\n");
13292                 return -EFAULT;
13293         }
13294
13295         DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13296            best_period);
13297
13298         return 0;
13299 }
13300
13301 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13302 {
13303         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13304
13305         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13306
13307         timecounter_adjtime(&bp->timecounter, delta);
13308
13309         return 0;
13310 }
13311
13312 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13313 {
13314         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13315         u64 ns;
13316
13317         ns = timecounter_read(&bp->timecounter);
13318
13319         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13320
13321         *ts = ns_to_timespec64(ns);
13322
13323         return 0;
13324 }
13325
13326 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13327                              const struct timespec64 *ts)
13328 {
13329         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13330         u64 ns;
13331
13332         ns = timespec64_to_ns(ts);
13333
13334         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13335
13336         /* Re-init the timecounter */
13337         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13338
13339         return 0;
13340 }
13341
13342 /* Enable (or disable) ancillary features of the phc subsystem */
13343 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13344                             struct ptp_clock_request *rq, int on)
13345 {
13346         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13347
13348         BNX2X_ERR("PHC ancillary features are not supported\n");
13349         return -ENOTSUPP;
13350 }
13351
13352 static void bnx2x_register_phc(struct bnx2x *bp)
13353 {
13354         /* Fill the ptp_clock_info struct and register PTP clock*/
13355         bp->ptp_clock_info.owner = THIS_MODULE;
13356         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13357         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13358         bp->ptp_clock_info.n_alarm = 0;
13359         bp->ptp_clock_info.n_ext_ts = 0;
13360         bp->ptp_clock_info.n_per_out = 0;
13361         bp->ptp_clock_info.pps = 0;
13362         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13363         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13364         bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13365         bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13366         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13367
13368         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13369         if (IS_ERR(bp->ptp_clock)) {
13370                 bp->ptp_clock = NULL;
13371                 BNX2X_ERR("PTP clock registeration failed\n");
13372         }
13373 }
13374
13375 static int bnx2x_init_one(struct pci_dev *pdev,
13376                                     const struct pci_device_id *ent)
13377 {
13378         struct net_device *dev = NULL;
13379         struct bnx2x *bp;
13380         enum pcie_link_width pcie_width;
13381         enum pci_bus_speed pcie_speed;
13382         int rc, max_non_def_sbs;
13383         int rx_count, tx_count, rss_count, doorbell_size;
13384         int max_cos_est;
13385         bool is_vf;
13386         int cnic_cnt;
13387
13388         /* Management FW 'remembers' living interfaces. Allow it some time
13389          * to forget previously living interfaces, allowing a proper re-load.
13390          */
13391         if (is_kdump_kernel()) {
13392                 ktime_t now = ktime_get_boottime();
13393                 ktime_t fw_ready_time = ktime_set(5, 0);
13394
13395                 if (ktime_before(now, fw_ready_time))
13396                         msleep(ktime_ms_delta(fw_ready_time, now));
13397         }
13398
13399         /* An estimated maximum supported CoS number according to the chip
13400          * version.
13401          * We will try to roughly estimate the maximum number of CoSes this chip
13402          * may support in order to minimize the memory allocated for Tx
13403          * netdev_queue's. This number will be accurately calculated during the
13404          * initialization of bp->max_cos based on the chip versions AND chip
13405          * revision in the bnx2x_init_bp().
13406          */
13407         max_cos_est = set_max_cos_est(ent->driver_data);
13408         if (max_cos_est < 0)
13409                 return max_cos_est;
13410         is_vf = set_is_vf(ent->driver_data);
13411         cnic_cnt = is_vf ? 0 : 1;
13412
13413         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13414
13415         /* add another SB for VF as it has no default SB */
13416         max_non_def_sbs += is_vf ? 1 : 0;
13417
13418         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13419         rss_count = max_non_def_sbs - cnic_cnt;
13420
13421         if (rss_count < 1)
13422                 return -EINVAL;
13423
13424         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13425         rx_count = rss_count + cnic_cnt;
13426
13427         /* Maximum number of netdev Tx queues:
13428          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13429          */
13430         tx_count = rss_count * max_cos_est + cnic_cnt;
13431
13432         /* dev zeroed in init_etherdev */
13433         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13434         if (!dev)
13435                 return -ENOMEM;
13436
13437         bp = netdev_priv(dev);
13438
13439         bp->flags = 0;
13440         if (is_vf)
13441                 bp->flags |= IS_VF_FLAG;
13442
13443         bp->igu_sb_cnt = max_non_def_sbs;
13444         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13445         bp->msg_enable = debug;
13446         bp->cnic_support = cnic_cnt;
13447         bp->cnic_probe = bnx2x_cnic_probe;
13448
13449         pci_set_drvdata(pdev, dev);
13450
13451         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13452         if (rc < 0) {
13453                 free_netdev(dev);
13454                 return rc;
13455         }
13456
13457         BNX2X_DEV_INFO("This is a %s function\n",
13458                        IS_PF(bp) ? "physical" : "virtual");
13459         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13460         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13461         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13462                        tx_count, rx_count);
13463
13464         rc = bnx2x_init_bp(bp);
13465         if (rc)
13466                 goto init_one_exit;
13467
13468         /* Map doorbells here as we need the real value of bp->max_cos which
13469          * is initialized in bnx2x_init_bp() to determine the number of
13470          * l2 connections.
13471          */
13472         if (IS_VF(bp)) {
13473                 bp->doorbells = bnx2x_vf_doorbells(bp);
13474                 rc = bnx2x_vf_pci_alloc(bp);
13475                 if (rc)
13476                         goto init_one_exit;
13477         } else {
13478                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13479                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13480                         dev_err(&bp->pdev->dev,
13481                                 "Cannot map doorbells, bar size too small, aborting\n");
13482                         rc = -ENOMEM;
13483                         goto init_one_exit;
13484                 }
13485                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13486                                                 doorbell_size);
13487         }
13488         if (!bp->doorbells) {
13489                 dev_err(&bp->pdev->dev,
13490                         "Cannot map doorbell space, aborting\n");
13491                 rc = -ENOMEM;
13492                 goto init_one_exit;
13493         }
13494
13495         if (IS_VF(bp)) {
13496                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13497                 if (rc)
13498                         goto init_one_exit;
13499         }
13500
13501         /* Enable SRIOV if capability found in configuration space */
13502         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13503         if (rc)
13504                 goto init_one_exit;
13505
13506         /* calc qm_cid_count */
13507         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13508         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13509
13510         /* disable FCOE L2 queue for E1x*/
13511         if (CHIP_IS_E1x(bp))
13512                 bp->flags |= NO_FCOE_FLAG;
13513
13514         /* Set bp->num_queues for MSI-X mode*/
13515         bnx2x_set_num_queues(bp);
13516
13517         /* Configure interrupt mode: try to enable MSI-X/MSI if
13518          * needed.
13519          */
13520         rc = bnx2x_set_int_mode(bp);
13521         if (rc) {
13522                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13523                 goto init_one_exit;
13524         }
13525         BNX2X_DEV_INFO("set interrupts successfully\n");
13526
13527         /* register the net device */
13528         rc = register_netdev(dev);
13529         if (rc) {
13530                 dev_err(&pdev->dev, "Cannot register net device\n");
13531                 goto init_one_exit;
13532         }
13533         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13534
13535         if (!NO_FCOE(bp)) {
13536                 /* Add storage MAC address */
13537                 rtnl_lock();
13538                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13539                 rtnl_unlock();
13540         }
13541         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13542             pcie_speed == PCI_SPEED_UNKNOWN ||
13543             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13544                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13545         else
13546                 BNX2X_DEV_INFO(
13547                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13548                        board_info[ent->driver_data].name,
13549                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13550                        pcie_width,
13551                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13552                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13553                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13554                        "Unknown",
13555                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13556
13557         bnx2x_register_phc(bp);
13558
13559         return 0;
13560
13561 init_one_exit:
13562         bnx2x_disable_pcie_error_reporting(bp);
13563
13564         if (bp->regview)
13565                 iounmap(bp->regview);
13566
13567         if (IS_PF(bp) && bp->doorbells)
13568                 iounmap(bp->doorbells);
13569
13570         free_netdev(dev);
13571
13572         if (atomic_read(&pdev->enable_cnt) == 1)
13573                 pci_release_regions(pdev);
13574
13575         pci_disable_device(pdev);
13576
13577         return rc;
13578 }
13579
13580 static void __bnx2x_remove(struct pci_dev *pdev,
13581                            struct net_device *dev,
13582                            struct bnx2x *bp,
13583                            bool remove_netdev)
13584 {
13585         if (bp->ptp_clock) {
13586                 ptp_clock_unregister(bp->ptp_clock);
13587                 bp->ptp_clock = NULL;
13588         }
13589
13590         /* Delete storage MAC address */
13591         if (!NO_FCOE(bp)) {
13592                 rtnl_lock();
13593                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13594                 rtnl_unlock();
13595         }
13596
13597 #ifdef BCM_DCBNL
13598         /* Delete app tlvs from dcbnl */
13599         bnx2x_dcbnl_update_applist(bp, true);
13600 #endif
13601
13602         if (IS_PF(bp) &&
13603             !BP_NOMCP(bp) &&
13604             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13605                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13606
13607         /* Close the interface - either directly or implicitly */
13608         if (remove_netdev) {
13609                 unregister_netdev(dev);
13610         } else {
13611                 rtnl_lock();
13612                 dev_close(dev);
13613                 rtnl_unlock();
13614         }
13615
13616         bnx2x_iov_remove_one(bp);
13617
13618         /* Power on: we can't let PCI layer write to us while we are in D3 */
13619         if (IS_PF(bp)) {
13620                 bnx2x_set_power_state(bp, PCI_D0);
13621
13622                 /* Set endianity registers to reset values in case next driver
13623                  * boots in different endianty environment.
13624                  */
13625                 bnx2x_reset_endianity(bp);
13626         }
13627
13628         /* Disable MSI/MSI-X */
13629         bnx2x_disable_msi(bp);
13630
13631         /* Power off */
13632         if (IS_PF(bp))
13633                 bnx2x_set_power_state(bp, PCI_D3hot);
13634
13635         /* Make sure RESET task is not scheduled before continuing */
13636         cancel_delayed_work_sync(&bp->sp_rtnl_task);
13637
13638         /* send message via vfpf channel to release the resources of this vf */
13639         if (IS_VF(bp))
13640                 bnx2x_vfpf_release(bp);
13641
13642         /* Assumes no further PCIe PM changes will occur */
13643         if (system_state == SYSTEM_POWER_OFF) {
13644                 pci_wake_from_d3(pdev, bp->wol);
13645                 pci_set_power_state(pdev, PCI_D3hot);
13646         }
13647
13648         bnx2x_disable_pcie_error_reporting(bp);
13649         if (remove_netdev) {
13650                 if (bp->regview)
13651                         iounmap(bp->regview);
13652
13653                 /* For vfs, doorbells are part of the regview and were unmapped
13654                  * along with it. FW is only loaded by PF.
13655                  */
13656                 if (IS_PF(bp)) {
13657                         if (bp->doorbells)
13658                                 iounmap(bp->doorbells);
13659
13660                         bnx2x_release_firmware(bp);
13661                 } else {
13662                         bnx2x_vf_pci_dealloc(bp);
13663                 }
13664                 bnx2x_free_mem_bp(bp);
13665
13666                 free_netdev(dev);
13667
13668                 if (atomic_read(&pdev->enable_cnt) == 1)
13669                         pci_release_regions(pdev);
13670
13671                 pci_disable_device(pdev);
13672         }
13673 }
13674
13675 static void bnx2x_remove_one(struct pci_dev *pdev)
13676 {
13677         struct net_device *dev = pci_get_drvdata(pdev);
13678         struct bnx2x *bp;
13679
13680         if (!dev) {
13681                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13682                 return;
13683         }
13684         bp = netdev_priv(dev);
13685
13686         __bnx2x_remove(pdev, dev, bp, true);
13687 }
13688
13689 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13690 {
13691         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13692
13693         bp->rx_mode = BNX2X_RX_MODE_NONE;
13694
13695         if (CNIC_LOADED(bp))
13696                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13697
13698         /* Stop Tx */
13699         bnx2x_tx_disable(bp);
13700         /* Delete all NAPI objects */
13701         bnx2x_del_all_napi(bp);
13702         if (CNIC_LOADED(bp))
13703                 bnx2x_del_all_napi_cnic(bp);
13704         netdev_reset_tc(bp->dev);
13705
13706         del_timer_sync(&bp->timer);
13707         cancel_delayed_work_sync(&bp->sp_task);
13708         cancel_delayed_work_sync(&bp->period_task);
13709
13710         if (!down_timeout(&bp->stats_lock, HZ / 10)) {
13711                 bp->stats_state = STATS_STATE_DISABLED;
13712                 up(&bp->stats_lock);
13713         }
13714
13715         bnx2x_save_statistics(bp);
13716
13717         netif_carrier_off(bp->dev);
13718
13719         return 0;
13720 }
13721
13722 /**
13723  * bnx2x_io_error_detected - called when PCI error is detected
13724  * @pdev: Pointer to PCI device
13725  * @state: The current pci connection state
13726  *
13727  * This function is called after a PCI bus error affecting
13728  * this device has been detected.
13729  */
13730 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13731                                                 pci_channel_state_t state)
13732 {
13733         struct net_device *dev = pci_get_drvdata(pdev);
13734         struct bnx2x *bp = netdev_priv(dev);
13735
13736         rtnl_lock();
13737
13738         BNX2X_ERR("IO error detected\n");
13739
13740         netif_device_detach(dev);
13741
13742         if (state == pci_channel_io_perm_failure) {
13743                 rtnl_unlock();
13744                 return PCI_ERS_RESULT_DISCONNECT;
13745         }
13746
13747         if (netif_running(dev))
13748                 bnx2x_eeh_nic_unload(bp);
13749
13750         bnx2x_prev_path_mark_eeh(bp);
13751
13752         pci_disable_device(pdev);
13753
13754         rtnl_unlock();
13755
13756         /* Request a slot reset */
13757         return PCI_ERS_RESULT_NEED_RESET;
13758 }
13759
13760 /**
13761  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13762  * @pdev: Pointer to PCI device
13763  *
13764  * Restart the card from scratch, as if from a cold-boot.
13765  */
13766 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13767 {
13768         struct net_device *dev = pci_get_drvdata(pdev);
13769         struct bnx2x *bp = netdev_priv(dev);
13770         int i;
13771
13772         rtnl_lock();
13773         BNX2X_ERR("IO slot reset initializing...\n");
13774         if (pci_enable_device(pdev)) {
13775                 dev_err(&pdev->dev,
13776                         "Cannot re-enable PCI device after reset\n");
13777                 rtnl_unlock();
13778                 return PCI_ERS_RESULT_DISCONNECT;
13779         }
13780
13781         pci_set_master(pdev);
13782         pci_restore_state(pdev);
13783         pci_save_state(pdev);
13784
13785         if (netif_running(dev))
13786                 bnx2x_set_power_state(bp, PCI_D0);
13787
13788         if (netif_running(dev)) {
13789                 BNX2X_ERR("IO slot reset --> driver unload\n");
13790
13791                 /* MCP should have been reset; Need to wait for validity */
13792                 bnx2x_init_shmem(bp);
13793
13794                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13795                         u32 v;
13796
13797                         v = SHMEM2_RD(bp,
13798                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13799                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13800                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13801                 }
13802                 bnx2x_drain_tx_queues(bp);
13803                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13804                 bnx2x_netif_stop(bp, 1);
13805                 bnx2x_free_irq(bp);
13806
13807                 /* Report UNLOAD_DONE to MCP */
13808                 bnx2x_send_unload_done(bp, true);
13809
13810                 bp->sp_state = 0;
13811                 bp->port.pmf = 0;
13812
13813                 bnx2x_prev_unload(bp);
13814
13815                 /* We should have reseted the engine, so It's fair to
13816                  * assume the FW will no longer write to the bnx2x driver.
13817                  */
13818                 bnx2x_squeeze_objects(bp);
13819                 bnx2x_free_skbs(bp);
13820                 for_each_rx_queue(bp, i)
13821                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13822                 bnx2x_free_fp_mem(bp);
13823                 bnx2x_free_mem(bp);
13824
13825                 bp->state = BNX2X_STATE_CLOSED;
13826         }
13827
13828         rtnl_unlock();
13829
13830         /* If AER, perform cleanup of the PCIe registers */
13831         if (bp->flags & AER_ENABLED) {
13832                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13833                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13834                 else
13835                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13836         }
13837
13838         return PCI_ERS_RESULT_RECOVERED;
13839 }
13840
13841 /**
13842  * bnx2x_io_resume - called when traffic can start flowing again
13843  * @pdev: Pointer to PCI device
13844  *
13845  * This callback is called when the error recovery driver tells us that
13846  * its OK to resume normal operation.
13847  */
13848 static void bnx2x_io_resume(struct pci_dev *pdev)
13849 {
13850         struct net_device *dev = pci_get_drvdata(pdev);
13851         struct bnx2x *bp = netdev_priv(dev);
13852
13853         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13854                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13855                 return;
13856         }
13857
13858         rtnl_lock();
13859
13860         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13861                                                         DRV_MSG_SEQ_NUMBER_MASK;
13862
13863         if (netif_running(dev))
13864                 bnx2x_nic_load(bp, LOAD_NORMAL);
13865
13866         netif_device_attach(dev);
13867
13868         rtnl_unlock();
13869 }
13870
13871 static const struct pci_error_handlers bnx2x_err_handler = {
13872         .error_detected = bnx2x_io_error_detected,
13873         .slot_reset     = bnx2x_io_slot_reset,
13874         .resume         = bnx2x_io_resume,
13875 };
13876
13877 static void bnx2x_shutdown(struct pci_dev *pdev)
13878 {
13879         struct net_device *dev = pci_get_drvdata(pdev);
13880         struct bnx2x *bp;
13881
13882         if (!dev)
13883                 return;
13884
13885         bp = netdev_priv(dev);
13886         if (!bp)
13887                 return;
13888
13889         rtnl_lock();
13890         netif_device_detach(dev);
13891         rtnl_unlock();
13892
13893         /* Don't remove the netdevice, as there are scenarios which will cause
13894          * the kernel to hang, e.g., when trying to remove bnx2i while the
13895          * rootfs is mounted from SAN.
13896          */
13897         __bnx2x_remove(pdev, dev, bp, false);
13898 }
13899
13900 static struct pci_driver bnx2x_pci_driver = {
13901         .name        = DRV_MODULE_NAME,
13902         .id_table    = bnx2x_pci_tbl,
13903         .probe       = bnx2x_init_one,
13904         .remove      = bnx2x_remove_one,
13905         .suspend     = bnx2x_suspend,
13906         .resume      = bnx2x_resume,
13907         .err_handler = &bnx2x_err_handler,
13908 #ifdef CONFIG_BNX2X_SRIOV
13909         .sriov_configure = bnx2x_sriov_configure,
13910 #endif
13911         .shutdown    = bnx2x_shutdown,
13912 };
13913
13914 static int __init bnx2x_init(void)
13915 {
13916         int ret;
13917
13918         pr_info("%s", version);
13919
13920         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13921         if (bnx2x_wq == NULL) {
13922                 pr_err("Cannot create workqueue\n");
13923                 return -ENOMEM;
13924         }
13925         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13926         if (!bnx2x_iov_wq) {
13927                 pr_err("Cannot create iov workqueue\n");
13928                 destroy_workqueue(bnx2x_wq);
13929                 return -ENOMEM;
13930         }
13931
13932         ret = pci_register_driver(&bnx2x_pci_driver);
13933         if (ret) {
13934                 pr_err("Cannot register driver\n");
13935                 destroy_workqueue(bnx2x_wq);
13936                 destroy_workqueue(bnx2x_iov_wq);
13937         }
13938         return ret;
13939 }
13940
13941 static void __exit bnx2x_cleanup(void)
13942 {
13943         struct list_head *pos, *q;
13944
13945         pci_unregister_driver(&bnx2x_pci_driver);
13946
13947         destroy_workqueue(bnx2x_wq);
13948         destroy_workqueue(bnx2x_iov_wq);
13949
13950         /* Free globally allocated resources */
13951         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13952                 struct bnx2x_prev_path_list *tmp =
13953                         list_entry(pos, struct bnx2x_prev_path_list, list);
13954                 list_del(pos);
13955                 kfree(tmp);
13956         }
13957 }
13958
13959 void bnx2x_notify_link_changed(struct bnx2x *bp)
13960 {
13961         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13962 }
13963
13964 module_init(bnx2x_init);
13965 module_exit(bnx2x_cleanup);
13966
13967 /**
13968  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13969  *
13970  * @bp:         driver handle
13971  * @set:        set or clear the CAM entry
13972  *
13973  * This function will wait until the ramrod completion returns.
13974  * Return 0 if success, -ENODEV if ramrod doesn't return.
13975  */
13976 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13977 {
13978         unsigned long ramrod_flags = 0;
13979
13980         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13981         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13982                                  &bp->iscsi_l2_mac_obj, true,
13983                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13984 }
13985
13986 /* count denotes the number of new completions we have seen */
13987 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13988 {
13989         struct eth_spe *spe;
13990         int cxt_index, cxt_offset;
13991
13992 #ifdef BNX2X_STOP_ON_ERROR
13993         if (unlikely(bp->panic))
13994                 return;
13995 #endif
13996
13997         spin_lock_bh(&bp->spq_lock);
13998         BUG_ON(bp->cnic_spq_pending < count);
13999         bp->cnic_spq_pending -= count;
14000
14001         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14002                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14003                                 & SPE_HDR_CONN_TYPE) >>
14004                                 SPE_HDR_CONN_TYPE_SHIFT;
14005                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14006                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14007
14008                 /* Set validation for iSCSI L2 client before sending SETUP
14009                  *  ramrod
14010                  */
14011                 if (type == ETH_CONNECTION_TYPE) {
14012                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14013                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14014                                         ILT_PAGE_CIDS;
14015                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14016                                         (cxt_index * ILT_PAGE_CIDS);
14017                                 bnx2x_set_ctx_validation(bp,
14018                                         &bp->context[cxt_index].
14019                                                          vcxt[cxt_offset].eth,
14020                                         BNX2X_ISCSI_ETH_CID(bp));
14021                         }
14022                 }
14023
14024                 /*
14025                  * There may be not more than 8 L2, not more than 8 L5 SPEs
14026                  * and in the air. We also check that number of outstanding
14027                  * COMMON ramrods is not more than the EQ and SPQ can
14028                  * accommodate.
14029                  */
14030                 if (type == ETH_CONNECTION_TYPE) {
14031                         if (!atomic_read(&bp->cq_spq_left))
14032                                 break;
14033                         else
14034                                 atomic_dec(&bp->cq_spq_left);
14035                 } else if (type == NONE_CONNECTION_TYPE) {
14036                         if (!atomic_read(&bp->eq_spq_left))
14037                                 break;
14038                         else
14039                                 atomic_dec(&bp->eq_spq_left);
14040                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14041                            (type == FCOE_CONNECTION_TYPE)) {
14042                         if (bp->cnic_spq_pending >=
14043                             bp->cnic_eth_dev.max_kwqe_pending)
14044                                 break;
14045                         else
14046                                 bp->cnic_spq_pending++;
14047                 } else {
14048                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14049                         bnx2x_panic();
14050                         break;
14051                 }
14052
14053                 spe = bnx2x_sp_get_next(bp);
14054                 *spe = *bp->cnic_kwq_cons;
14055
14056                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14057                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14058
14059                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14060                         bp->cnic_kwq_cons = bp->cnic_kwq;
14061                 else
14062                         bp->cnic_kwq_cons++;
14063         }
14064         bnx2x_sp_prod_update(bp);
14065         spin_unlock_bh(&bp->spq_lock);
14066 }
14067
14068 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14069                                struct kwqe_16 *kwqes[], u32 count)
14070 {
14071         struct bnx2x *bp = netdev_priv(dev);
14072         int i;
14073
14074 #ifdef BNX2X_STOP_ON_ERROR
14075         if (unlikely(bp->panic)) {
14076                 BNX2X_ERR("Can't post to SP queue while panic\n");
14077                 return -EIO;
14078         }
14079 #endif
14080
14081         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14082             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14083                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14084                 return -EAGAIN;
14085         }
14086
14087         spin_lock_bh(&bp->spq_lock);
14088
14089         for (i = 0; i < count; i++) {
14090                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14091
14092                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14093                         break;
14094
14095                 *bp->cnic_kwq_prod = *spe;
14096
14097                 bp->cnic_kwq_pending++;
14098
14099                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14100                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14101                    spe->data.update_data_addr.hi,
14102                    spe->data.update_data_addr.lo,
14103                    bp->cnic_kwq_pending);
14104
14105                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14106                         bp->cnic_kwq_prod = bp->cnic_kwq;
14107                 else
14108                         bp->cnic_kwq_prod++;
14109         }
14110
14111         spin_unlock_bh(&bp->spq_lock);
14112
14113         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14114                 bnx2x_cnic_sp_post(bp, 0);
14115
14116         return i;
14117 }
14118
14119 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14120 {
14121         struct cnic_ops *c_ops;
14122         int rc = 0;
14123
14124         mutex_lock(&bp->cnic_mutex);
14125         c_ops = rcu_dereference_protected(bp->cnic_ops,
14126                                           lockdep_is_held(&bp->cnic_mutex));
14127         if (c_ops)
14128                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14129         mutex_unlock(&bp->cnic_mutex);
14130
14131         return rc;
14132 }
14133
14134 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14135 {
14136         struct cnic_ops *c_ops;
14137         int rc = 0;
14138
14139         rcu_read_lock();
14140         c_ops = rcu_dereference(bp->cnic_ops);
14141         if (c_ops)
14142                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14143         rcu_read_unlock();
14144
14145         return rc;
14146 }
14147
14148 /*
14149  * for commands that have no data
14150  */
14151 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14152 {
14153         struct cnic_ctl_info ctl = {0};
14154
14155         ctl.cmd = cmd;
14156
14157         return bnx2x_cnic_ctl_send(bp, &ctl);
14158 }
14159
14160 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14161 {
14162         struct cnic_ctl_info ctl = {0};
14163
14164         /* first we tell CNIC and only then we count this as a completion */
14165         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14166         ctl.data.comp.cid = cid;
14167         ctl.data.comp.error = err;
14168
14169         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14170         bnx2x_cnic_sp_post(bp, 0);
14171 }
14172
14173 /* Called with netif_addr_lock_bh() taken.
14174  * Sets an rx_mode config for an iSCSI ETH client.
14175  * Doesn't block.
14176  * Completion should be checked outside.
14177  */
14178 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14179 {
14180         unsigned long accept_flags = 0, ramrod_flags = 0;
14181         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14182         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14183
14184         if (start) {
14185                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14186                  * because it's the only way for UIO Queue to accept
14187                  * multicasts (in non-promiscuous mode only one Queue per
14188                  * function will receive multicast packets (leading in our
14189                  * case).
14190                  */
14191                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14192                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14193                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14194                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14195
14196                 /* Clear STOP_PENDING bit if START is requested */
14197                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14198
14199                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14200         } else
14201                 /* Clear START_PENDING bit if STOP is requested */
14202                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14203
14204         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14205                 set_bit(sched_state, &bp->sp_state);
14206         else {
14207                 __set_bit(RAMROD_RX, &ramrod_flags);
14208                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14209                                     ramrod_flags);
14210         }
14211 }
14212
14213 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14214 {
14215         struct bnx2x *bp = netdev_priv(dev);
14216         int rc = 0;
14217
14218         switch (ctl->cmd) {
14219         case DRV_CTL_CTXTBL_WR_CMD: {
14220                 u32 index = ctl->data.io.offset;
14221                 dma_addr_t addr = ctl->data.io.dma_addr;
14222
14223                 bnx2x_ilt_wr(bp, index, addr);
14224                 break;
14225         }
14226
14227         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14228                 int count = ctl->data.credit.credit_count;
14229
14230                 bnx2x_cnic_sp_post(bp, count);
14231                 break;
14232         }
14233
14234         /* rtnl_lock is held.  */
14235         case DRV_CTL_START_L2_CMD: {
14236                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14237                 unsigned long sp_bits = 0;
14238
14239                 /* Configure the iSCSI classification object */
14240                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14241                                    cp->iscsi_l2_client_id,
14242                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14243                                    bnx2x_sp(bp, mac_rdata),
14244                                    bnx2x_sp_mapping(bp, mac_rdata),
14245                                    BNX2X_FILTER_MAC_PENDING,
14246                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14247                                    &bp->macs_pool);
14248
14249                 /* Set iSCSI MAC address */
14250                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14251                 if (rc)
14252                         break;
14253
14254                 mmiowb();
14255                 barrier();
14256
14257                 /* Start accepting on iSCSI L2 ring */
14258
14259                 netif_addr_lock_bh(dev);
14260                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14261                 netif_addr_unlock_bh(dev);
14262
14263                 /* bits to wait on */
14264                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14265                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14266
14267                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14268                         BNX2X_ERR("rx_mode completion timed out!\n");
14269
14270                 break;
14271         }
14272
14273         /* rtnl_lock is held.  */
14274         case DRV_CTL_STOP_L2_CMD: {
14275                 unsigned long sp_bits = 0;
14276
14277                 /* Stop accepting on iSCSI L2 ring */
14278                 netif_addr_lock_bh(dev);
14279                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14280                 netif_addr_unlock_bh(dev);
14281
14282                 /* bits to wait on */
14283                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14284                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14285
14286                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14287                         BNX2X_ERR("rx_mode completion timed out!\n");
14288
14289                 mmiowb();
14290                 barrier();
14291
14292                 /* Unset iSCSI L2 MAC */
14293                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14294                                         BNX2X_ISCSI_ETH_MAC, true);
14295                 break;
14296         }
14297         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14298                 int count = ctl->data.credit.credit_count;
14299
14300                 smp_mb__before_atomic();
14301                 atomic_add(count, &bp->cq_spq_left);
14302                 smp_mb__after_atomic();
14303                 break;
14304         }
14305         case DRV_CTL_ULP_REGISTER_CMD: {
14306                 int ulp_type = ctl->data.register_data.ulp_type;
14307
14308                 if (CHIP_IS_E3(bp)) {
14309                         int idx = BP_FW_MB_IDX(bp);
14310                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14311                         int path = BP_PATH(bp);
14312                         int port = BP_PORT(bp);
14313                         int i;
14314                         u32 scratch_offset;
14315                         u32 *host_addr;
14316
14317                         /* first write capability to shmem2 */
14318                         if (ulp_type == CNIC_ULP_ISCSI)
14319                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14320                         else if (ulp_type == CNIC_ULP_FCOE)
14321                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14322                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14323
14324                         if ((ulp_type != CNIC_ULP_FCOE) ||
14325                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14326                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14327                                 break;
14328
14329                         /* if reached here - should write fcoe capabilities */
14330                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14331                         if (!scratch_offset)
14332                                 break;
14333                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14334                                                    fcoe_features[path][port]);
14335                         host_addr = (u32 *) &(ctl->data.register_data.
14336                                               fcoe_features);
14337                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14338                              i += 4)
14339                                 REG_WR(bp, scratch_offset + i,
14340                                        *(host_addr + i/4));
14341                 }
14342                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14343                 break;
14344         }
14345
14346         case DRV_CTL_ULP_UNREGISTER_CMD: {
14347                 int ulp_type = ctl->data.ulp_type;
14348
14349                 if (CHIP_IS_E3(bp)) {
14350                         int idx = BP_FW_MB_IDX(bp);
14351                         u32 cap;
14352
14353                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14354                         if (ulp_type == CNIC_ULP_ISCSI)
14355                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14356                         else if (ulp_type == CNIC_ULP_FCOE)
14357                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14358                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14359                 }
14360                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14361                 break;
14362         }
14363
14364         default:
14365                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14366                 rc = -EINVAL;
14367         }
14368
14369         return rc;
14370 }
14371
14372 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14373 {
14374         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14375
14376         if (bp->flags & USING_MSIX_FLAG) {
14377                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14378                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14379                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14380         } else {
14381                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14382                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14383         }
14384         if (!CHIP_IS_E1x(bp))
14385                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14386         else
14387                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14388
14389         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14390         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14391         cp->irq_arr[1].status_blk = bp->def_status_blk;
14392         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14393         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14394
14395         cp->num_irq = 2;
14396 }
14397
14398 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14399 {
14400         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14401
14402         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14403                              bnx2x_cid_ilt_lines(bp);
14404         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14405         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14406         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14407
14408         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14409            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14410            cp->iscsi_l2_cid);
14411
14412         if (NO_ISCSI_OOO(bp))
14413                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14414 }
14415
14416 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14417                                void *data)
14418 {
14419         struct bnx2x *bp = netdev_priv(dev);
14420         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14421         int rc;
14422
14423         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14424
14425         if (ops == NULL) {
14426                 BNX2X_ERR("NULL ops received\n");
14427                 return -EINVAL;
14428         }
14429
14430         if (!CNIC_SUPPORT(bp)) {
14431                 BNX2X_ERR("Can't register CNIC when not supported\n");
14432                 return -EOPNOTSUPP;
14433         }
14434
14435         if (!CNIC_LOADED(bp)) {
14436                 rc = bnx2x_load_cnic(bp);
14437                 if (rc) {
14438                         BNX2X_ERR("CNIC-related load failed\n");
14439                         return rc;
14440                 }
14441         }
14442
14443         bp->cnic_enabled = true;
14444
14445         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14446         if (!bp->cnic_kwq)
14447                 return -ENOMEM;
14448
14449         bp->cnic_kwq_cons = bp->cnic_kwq;
14450         bp->cnic_kwq_prod = bp->cnic_kwq;
14451         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14452
14453         bp->cnic_spq_pending = 0;
14454         bp->cnic_kwq_pending = 0;
14455
14456         bp->cnic_data = data;
14457
14458         cp->num_irq = 0;
14459         cp->drv_state |= CNIC_DRV_STATE_REGD;
14460         cp->iro_arr = bp->iro_arr;
14461
14462         bnx2x_setup_cnic_irq_info(bp);
14463
14464         rcu_assign_pointer(bp->cnic_ops, ops);
14465
14466         /* Schedule driver to read CNIC driver versions */
14467         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14468
14469         return 0;
14470 }
14471
14472 static int bnx2x_unregister_cnic(struct net_device *dev)
14473 {
14474         struct bnx2x *bp = netdev_priv(dev);
14475         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14476
14477         mutex_lock(&bp->cnic_mutex);
14478         cp->drv_state = 0;
14479         RCU_INIT_POINTER(bp->cnic_ops, NULL);
14480         mutex_unlock(&bp->cnic_mutex);
14481         synchronize_rcu();
14482         bp->cnic_enabled = false;
14483         kfree(bp->cnic_kwq);
14484         bp->cnic_kwq = NULL;
14485
14486         return 0;
14487 }
14488
14489 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14490 {
14491         struct bnx2x *bp = netdev_priv(dev);
14492         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14493
14494         /* If both iSCSI and FCoE are disabled - return NULL in
14495          * order to indicate CNIC that it should not try to work
14496          * with this device.
14497          */
14498         if (NO_ISCSI(bp) && NO_FCOE(bp))
14499                 return NULL;
14500
14501         cp->drv_owner = THIS_MODULE;
14502         cp->chip_id = CHIP_ID(bp);
14503         cp->pdev = bp->pdev;
14504         cp->io_base = bp->regview;
14505         cp->io_base2 = bp->doorbells;
14506         cp->max_kwqe_pending = 8;
14507         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14508         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14509                              bnx2x_cid_ilt_lines(bp);
14510         cp->ctx_tbl_len = CNIC_ILT_LINES;
14511         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14512         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14513         cp->drv_ctl = bnx2x_drv_ctl;
14514         cp->drv_register_cnic = bnx2x_register_cnic;
14515         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14516         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14517         cp->iscsi_l2_client_id =
14518                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14519         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14520
14521         if (NO_ISCSI_OOO(bp))
14522                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14523
14524         if (NO_ISCSI(bp))
14525                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14526
14527         if (NO_FCOE(bp))
14528                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14529
14530         BNX2X_DEV_INFO(
14531                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14532            cp->ctx_blk_size,
14533            cp->ctx_tbl_offset,
14534            cp->ctx_tbl_len,
14535            cp->starting_cid);
14536         return cp;
14537 }
14538
14539 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14540 {
14541         struct bnx2x *bp = fp->bp;
14542         u32 offset = BAR_USTRORM_INTMEM;
14543
14544         if (IS_VF(bp))
14545                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14546         else if (!CHIP_IS_E1x(bp))
14547                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14548         else
14549                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14550
14551         return offset;
14552 }
14553
14554 /* called only on E1H or E2.
14555  * When pretending to be PF, the pretend value is the function number 0...7
14556  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14557  * combination
14558  */
14559 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14560 {
14561         u32 pretend_reg;
14562
14563         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14564                 return -1;
14565
14566         /* get my own pretend register */
14567         pretend_reg = bnx2x_get_pretend_reg(bp);
14568         REG_WR(bp, pretend_reg, pretend_func_val);
14569         REG_RD(bp, pretend_reg);
14570         return 0;
14571 }
14572
14573 static void bnx2x_ptp_task(struct work_struct *work)
14574 {
14575         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14576         int port = BP_PORT(bp);
14577         u32 val_seq;
14578         u64 timestamp, ns;
14579         struct skb_shared_hwtstamps shhwtstamps;
14580
14581         /* Read Tx timestamp registers */
14582         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14583                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14584         if (val_seq & 0x10000) {
14585                 /* There is a valid timestamp value */
14586                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14587                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14588                 timestamp <<= 32;
14589                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14590                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14591                 /* Reset timestamp register to allow new timestamp */
14592                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14593                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14594                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14595
14596                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14597                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14598                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14599                 dev_kfree_skb_any(bp->ptp_tx_skb);
14600                 bp->ptp_tx_skb = NULL;
14601
14602                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14603                    timestamp, ns);
14604         } else {
14605                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14606                 /* Reschedule to keep checking for a valid timestamp value */
14607                 schedule_work(&bp->ptp_task);
14608         }
14609 }
14610
14611 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14612 {
14613         int port = BP_PORT(bp);
14614         u64 timestamp, ns;
14615
14616         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14617                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14618         timestamp <<= 32;
14619         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14620                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14621
14622         /* Reset timestamp register to allow new timestamp */
14623         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14624                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14625
14626         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14627
14628         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14629
14630         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14631            timestamp, ns);
14632 }
14633
14634 /* Read the PHC */
14635 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14636 {
14637         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14638         int port = BP_PORT(bp);
14639         u32 wb_data[2];
14640         u64 phc_cycles;
14641
14642         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14643                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14644         phc_cycles = wb_data[1];
14645         phc_cycles = (phc_cycles << 32) + wb_data[0];
14646
14647         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14648
14649         return phc_cycles;
14650 }
14651
14652 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14653 {
14654         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14655         bp->cyclecounter.read = bnx2x_cyclecounter_read;
14656         bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
14657         bp->cyclecounter.shift = 1;
14658         bp->cyclecounter.mult = 1;
14659 }
14660
14661 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14662 {
14663         struct bnx2x_func_state_params func_params = {NULL};
14664         struct bnx2x_func_set_timesync_params *set_timesync_params =
14665                 &func_params.params.set_timesync;
14666
14667         /* Prepare parameters for function state transitions */
14668         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14669         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14670
14671         func_params.f_obj = &bp->func_obj;
14672         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14673
14674         /* Function parameters */
14675         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14676         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14677
14678         return bnx2x_func_state_change(bp, &func_params);
14679 }
14680
14681 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14682 {
14683         struct bnx2x_queue_state_params q_params;
14684         int rc, i;
14685
14686         /* send queue update ramrod to enable PTP packets */
14687         memset(&q_params, 0, sizeof(q_params));
14688         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14689         q_params.cmd = BNX2X_Q_CMD_UPDATE;
14690         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14691                   &q_params.params.update.update_flags);
14692         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14693                   &q_params.params.update.update_flags);
14694
14695         /* send the ramrod on all the queues of the PF */
14696         for_each_eth_queue(bp, i) {
14697                 struct bnx2x_fastpath *fp = &bp->fp[i];
14698
14699                 /* Set the appropriate Queue object */
14700                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14701
14702                 /* Update the Queue state */
14703                 rc = bnx2x_queue_state_change(bp, &q_params);
14704                 if (rc) {
14705                         BNX2X_ERR("Failed to enable PTP packets\n");
14706                         return rc;
14707                 }
14708         }
14709
14710         return 0;
14711 }
14712
14713 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14714 {
14715         int port = BP_PORT(bp);
14716         int rc;
14717
14718         if (!bp->hwtstamp_ioctl_called)
14719                 return 0;
14720
14721         switch (bp->tx_type) {
14722         case HWTSTAMP_TX_ON:
14723                 bp->flags |= TX_TIMESTAMPING_EN;
14724                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14725                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14726                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14727                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14728                 break;
14729         case HWTSTAMP_TX_ONESTEP_SYNC:
14730                 BNX2X_ERR("One-step timestamping is not supported\n");
14731                 return -ERANGE;
14732         }
14733
14734         switch (bp->rx_filter) {
14735         case HWTSTAMP_FILTER_NONE:
14736                 break;
14737         case HWTSTAMP_FILTER_ALL:
14738         case HWTSTAMP_FILTER_SOME:
14739                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14740                 break;
14741         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14742         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14743         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14744                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14745                 /* Initialize PTP detection for UDP/IPv4 events */
14746                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14747                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14748                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14749                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14750                 break;
14751         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14752         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14753         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14754                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14755                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14756                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14757                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14758                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14759                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14760                 break;
14761         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14762         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14763         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14764                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14765                 /* Initialize PTP detection L2 events */
14766                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14767                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14768                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14769                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14770
14771                 break;
14772         case HWTSTAMP_FILTER_PTP_V2_EVENT:
14773         case HWTSTAMP_FILTER_PTP_V2_SYNC:
14774         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14775                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14776                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14777                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14778                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14779                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14780                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14781                 break;
14782         }
14783
14784         /* Indicate to FW that this PF expects recorded PTP packets */
14785         rc = bnx2x_enable_ptp_packets(bp);
14786         if (rc)
14787                 return rc;
14788
14789         /* Enable sending PTP packets to host */
14790         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14791                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14792
14793         return 0;
14794 }
14795
14796 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14797 {
14798         struct hwtstamp_config config;
14799         int rc;
14800
14801         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14802
14803         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14804                 return -EFAULT;
14805
14806         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14807            config.tx_type, config.rx_filter);
14808
14809         if (config.flags) {
14810                 BNX2X_ERR("config.flags is reserved for future use\n");
14811                 return -EINVAL;
14812         }
14813
14814         bp->hwtstamp_ioctl_called = 1;
14815         bp->tx_type = config.tx_type;
14816         bp->rx_filter = config.rx_filter;
14817
14818         rc = bnx2x_configure_ptp_filters(bp);
14819         if (rc)
14820                 return rc;
14821
14822         config.rx_filter = bp->rx_filter;
14823
14824         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14825                 -EFAULT : 0;
14826 }
14827
14828 /* Configures HW for PTP */
14829 static int bnx2x_configure_ptp(struct bnx2x *bp)
14830 {
14831         int rc, port = BP_PORT(bp);
14832         u32 wb_data[2];
14833
14834         /* Reset PTP event detection rules - will be configured in the IOCTL */
14835         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14836                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14837         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14838                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14839         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14840                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14841         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14842                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14843
14844         /* Disable PTP packets to host - will be configured in the IOCTL*/
14845         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14846                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14847
14848         /* Enable the PTP feature */
14849         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14850                NIG_REG_P0_PTP_EN, 0x3F);
14851
14852         /* Enable the free-running counter */
14853         wb_data[0] = 0;
14854         wb_data[1] = 0;
14855         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14856
14857         /* Reset drift register (offset register is not reset) */
14858         rc = bnx2x_send_reset_timesync_ramrod(bp);
14859         if (rc) {
14860                 BNX2X_ERR("Failed to reset PHC drift register\n");
14861                 return -EFAULT;
14862         }
14863
14864         /* Reset possibly old timestamps */
14865         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14866                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14867         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14868                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14869
14870         return 0;
14871 }
14872
14873 /* Called during load, to initialize PTP-related stuff */
14874 void bnx2x_init_ptp(struct bnx2x *bp)
14875 {
14876         int rc;
14877
14878         /* Configure PTP in HW */
14879         rc = bnx2x_configure_ptp(bp);
14880         if (rc) {
14881                 BNX2X_ERR("Stopping PTP initialization\n");
14882                 return;
14883         }
14884
14885         /* Init work queue for Tx timestamping */
14886         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14887
14888         /* Init cyclecounter and timecounter. This is done only in the first
14889          * load. If done in every load, PTP application will fail when doing
14890          * unload / load (e.g. MTU change) while it is running.
14891          */
14892         if (!bp->timecounter_init_done) {
14893                 bnx2x_init_cyclecounter(bp);
14894                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14895                                  ktime_to_ns(ktime_get_real()));
14896                 bp->timecounter_init_done = 1;
14897         }
14898
14899         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14900 }