drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2012 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/bitops.h>
  36 #include <linux/irq.h>
  37 #include <linux/delay.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/time.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/mii.h>
  42 #include <linux/if_vlan.h>
  43 #include <net/ip.h>
  44 #include <net/ipv6.h>
  45 #include <net/tcp.h>
  46 #include <net/checksum.h>
  47 #include <net/ip6_checksum.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/crc32.h>
  50 #include <linux/crc32c.h>
  51 #include <linux/prefetch.h>
  52 #include <linux/zlib.h>
  53 #include <linux/io.h>
  54 #include <linux/semaphore.h>
  55 #include <linux/stringify.h>
  56 #include <linux/vmalloc.h>
  57
  58 #include "bnx2x.h"
  59 #include "bnx2x_init.h"
  60 #include "bnx2x_init_ops.h"
  61 #include "bnx2x_cmn.h"
  62 #include "bnx2x_vfpf.h"
  63 #include "bnx2x_dcb.h"
  64 #include "bnx2x_sp.h"
  65
  66 #include <linux/firmware.h>
  67 #include "bnx2x_fw_file_hdr.h"
  68 /* FW files */
  69 #define FW_FILE_VERSION                                 \
  70         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  71         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  73         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  74 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  75 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  77
  78 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
  79
  80 /* Time in jiffies before concluding the transmitter is hung */
  81 #define TX_TIMEOUT              (5*HZ)
  82
  83 static char version[] =
  84         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  85         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  86
  87 MODULE_AUTHOR("Eliezer Tamir");
  88 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  89                    "BCM57710/57711/57711E/"
  90                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  91                    "57840/57840_MF Driver");
  92 MODULE_LICENSE("GPL");
  93 MODULE_VERSION(DRV_MODULE_VERSION);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  96 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  97
  98
  99 int num_queues;
 100 module_param(num_queues, int, 0);
 101 MODULE_PARM_DESC(num_queues,
 102                  " Set number of queues (default is as a number of CPUs)");
 103
 104 static int disable_tpa;
 105 module_param(disable_tpa, int, 0);
 106 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 107
 108 #define INT_MODE_INTx                   1
 109 #define INT_MODE_MSI                    2
 110 int int_mode;
 111 module_param(int_mode, int, 0);
 112 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 113                                 "(1 INT#x; 2 MSI)");
 114
 115 static int dropless_fc;
 116 module_param(dropless_fc, int, 0);
 117 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 118
 119 static int mrrs = -1;
 120 module_param(mrrs, int, 0);
 121 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 122
 123 static int debug;
 124 module_param(debug, int, 0);
 125 MODULE_PARM_DESC(debug, " Default debug msglevel");
 126
 127
 128
 129 struct workqueue_struct *bnx2x_wq;
 130
 131 struct bnx2x_mac_vals {
 132         u32 xmac_addr;
 133         u32 xmac_val;
 134         u32 emac_addr;
 135         u32 emac_val;
 136         u32 umac_addr;
 137         u32 umac_val;
 138         u32 bmac_addr;
 139         u32 bmac_val[2];
 140 };
 141
 142 enum bnx2x_board_type {
 143         BCM57710 = 0,
 144         BCM57711,
 145         BCM57711E,
 146         BCM57712,
 147         BCM57712_MF,
 148         BCM57712_VF,
 149         BCM57800,
 150         BCM57800_MF,
 151         BCM57800_VF,
 152         BCM57810,
 153         BCM57810_MF,
 154         BCM57810_VF,
 155         BCM57840_4_10,
 156         BCM57840_2_20,
 157         BCM57840_MF,
 158         BCM57840_VF,
 159         BCM57811,
 160         BCM57811_MF,
 161         BCM57840_O,
 162         BCM57840_MFO,
 163         BCM57811_VF
 164 };
 165
 166 /* indexed by board_type, above */
 167 static struct {
 168         char *name;
 169 } board_info[] = {
 170         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 171         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 172         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 173         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 174         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 175         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 176         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 177         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 178         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 179         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 180         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 181         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 182         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 183         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 184         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 185         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 186         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 187         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 188         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 189         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 190         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 191 };
 192
 193 #ifndef PCI_DEVICE_ID_NX2_57710
 194 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 195 #endif
 196 #ifndef PCI_DEVICE_ID_NX2_57711
 197 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 198 #endif
 199 #ifndef PCI_DEVICE_ID_NX2_57711E
 200 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 201 #endif
 202 #ifndef PCI_DEVICE_ID_NX2_57712
 203 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 204 #endif
 205 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 206 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 207 #endif
 208 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 209 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 210 #endif
 211 #ifndef PCI_DEVICE_ID_NX2_57800
 212 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 213 #endif
 214 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 215 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 216 #endif
 217 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 218 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 219 #endif
 220 #ifndef PCI_DEVICE_ID_NX2_57810
 221 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 222 #endif
 223 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 224 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 225 #endif
 226 #ifndef PCI_DEVICE_ID_NX2_57840_O
 227 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 228 #endif
 229 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 230 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 231 #endif
 232 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 233 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 234 #endif
 235 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 236 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 237 #endif
 238 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 239 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 240 #endif
 241 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 242 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 243 #endif
 244 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 245 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 246 #endif
 247 #ifndef PCI_DEVICE_ID_NX2_57811
 248 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 249 #endif
 250 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 251 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 252 #endif
 253 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 254 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 255 #endif
 256
 257 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 275         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 276         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 277         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 278         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 279         { 0 }
 280 };
 281
 282 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 283
 284 /* Global resources for unloading a previously loaded device */
 285 #define BNX2X_PREV_WAIT_NEEDED 1
 286 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 287 static LIST_HEAD(bnx2x_prev_list);
 288 /****************************************************************************
 289 * General service functions
 290 ****************************************************************************/
 291
 292 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 293                                        u32 addr, dma_addr_t mapping)
 294 {
 295         REG_WR(bp,  addr, U64_LO(mapping));
 296         REG_WR(bp,  addr + 4, U64_HI(mapping));
 297 }
 298
 299 static void storm_memset_spq_addr(struct bnx2x *bp,
 300                                   dma_addr_t mapping, u16 abs_fid)
 301 {
 302         u32 addr = XSEM_REG_FAST_MEMORY +
 303                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 304
 305         __storm_memset_dma_mapping(bp, addr, mapping);
 306 }
 307
 308 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 309                                   u16 pf_id)
 310 {
 311         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 312                 pf_id);
 313         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 314                 pf_id);
 315         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 316                 pf_id);
 317         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 318                 pf_id);
 319 }
 320
 321 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 322                                  u8 enable)
 323 {
 324         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 325                 enable);
 326         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 327                 enable);
 328         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 329                 enable);
 330         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 331                 enable);
 332 }
 333
 334 static void storm_memset_eq_data(struct bnx2x *bp,
 335                                  struct event_ring_data *eq_data,
 336                                 u16 pfid)
 337 {
 338         size_t size = sizeof(struct event_ring_data);
 339
 340         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 341
 342         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 343 }
 344
 345 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 346                                  u16 pfid)
 347 {
 348         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 349         REG_WR16(bp, addr, eq_prod);
 350 }
 351
 352 /* used only at init
 353  * locking is done by mcp
 354  */
 355 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 356 {
 357         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 358         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 359         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 360                                PCICFG_VENDOR_ID_OFFSET);
 361 }
 362
 363 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 364 {
 365         u32 val;
 366
 367         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 368         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 369         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 370                                PCICFG_VENDOR_ID_OFFSET);
 371
 372         return val;
 373 }
 374
 375 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 376 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 377 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 378 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 379 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 380
 381 void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl)
 382 {
 383         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 384
 385         switch (dmae->opcode & DMAE_COMMAND_DST) {
 386         case DMAE_CMD_DST_PCI:
 387                 if (src_type == DMAE_CMD_SRC_PCI)
 388                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 389                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 390                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 391                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 392                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 393                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 394                            dmae->comp_val);
 395                 else
 396                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 397                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 398                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 399                            dmae->opcode, dmae->src_addr_lo >> 2,
 400                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 401                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 402                            dmae->comp_val);
 403                 break;
 404         case DMAE_CMD_DST_GRC:
 405                 if (src_type == DMAE_CMD_SRC_PCI)
 406                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 407                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 408                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 409                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 410                            dmae->len, dmae->dst_addr_lo >> 2,
 411                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 412                            dmae->comp_val);
 413                 else
 414                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 415                            "src [%08x], len [%d*4], dst [%08x]\n"
 416                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 417                            dmae->opcode, dmae->src_addr_lo >> 2,
 418                            dmae->len, dmae->dst_addr_lo >> 2,
 419                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 420                            dmae->comp_val);
 421                 break;
 422         default:
 423                 if (src_type == DMAE_CMD_SRC_PCI)
 424                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 425                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 426                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 427                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 428                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 429                            dmae->comp_val);
 430                 else
 431                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 432                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 433                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 434                            dmae->opcode, dmae->src_addr_lo >> 2,
 435                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 436                            dmae->comp_val);
 437                 break;
 438         }
 439 }
 440
 441 /* copy command into DMAE command memory and set DMAE command go */
 442 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 443 {
 444         u32 cmd_offset;
 445         int i;
 446
 447         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 448         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 449                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 450         }
 451         REG_WR(bp, dmae_reg_go_c[idx], 1);
 452 }
 453
 454 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 455 {
 456         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 457                            DMAE_CMD_C_ENABLE);
 458 }
 459
 460 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 461 {
 462         return opcode & ~DMAE_CMD_SRC_RESET;
 463 }
 464
 465 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 466                              bool with_comp, u8 comp_type)
 467 {
 468         u32 opcode = 0;
 469
 470         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 471                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 472
 473         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 474
 475         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 476         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 477                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 478         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 479
 480 #ifdef __BIG_ENDIAN
 481         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 482 #else
 483         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 484 #endif
 485         if (with_comp)
 486                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 487         return opcode;
 488 }
 489
 490 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 491                                       struct dmae_command *dmae,
 492                                       u8 src_type, u8 dst_type)
 493 {
 494         memset(dmae, 0, sizeof(struct dmae_command));
 495
 496         /* set the opcode */
 497         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 498                                          true, DMAE_COMP_PCI);
 499
 500         /* fill in the completion parameters */
 501         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 502         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 503         dmae->comp_val = DMAE_COMP_VAL;
 504 }
 505
 506 /* issue a dmae command over the init-channel and wait for completion */
 507 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
 508 {
 509         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
 510         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 511         int rc = 0;
 512
 513         /*
 514          * Lock the dmae channel. Disable BHs to prevent a dead-lock
 515          * as long as this code is called both from syscall context and
 516          * from ndo_set_rx_mode() flow that may be called from BH.
 517          */
 518         spin_lock_bh(&bp->dmae_lock);
 519
 520         /* reset completion */
 521         *wb_comp = 0;
 522
 523         /* post the command on the channel used for initializations */
 524         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 525
 526         /* wait for completion */
 527         udelay(5);
 528         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 529
 530                 if (!cnt ||
 531                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 532                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 533                         BNX2X_ERR("DMAE timeout!\n");
 534                         rc = DMAE_TIMEOUT;
 535                         goto unlock;
 536                 }
 537                 cnt--;
 538                 udelay(50);
 539         }
 540         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 541                 BNX2X_ERR("DMAE PCI error!\n");
 542                 rc = DMAE_PCI_ERROR;
 543         }
 544
 545 unlock:
 546         spin_unlock_bh(&bp->dmae_lock);
 547         return rc;
 548 }
 549
 550 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 551                       u32 len32)
 552 {
 553         struct dmae_command dmae;
 554
 555         if (!bp->dmae_ready) {
 556                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 557
 558                 if (CHIP_IS_E1(bp))
 559                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 560                 else
 561                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 562                 return;
 563         }
 564
 565         /* set opcode and fixed command fields */
 566         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 567
 568         /* fill in addresses and len */
 569         dmae.src_addr_lo = U64_LO(dma_addr);
 570         dmae.src_addr_hi = U64_HI(dma_addr);
 571         dmae.dst_addr_lo = dst_addr >> 2;
 572         dmae.dst_addr_hi = 0;
 573         dmae.len = len32;
 574
 575         /* issue the command and wait for completion */
 576         bnx2x_issue_dmae_with_comp(bp, &dmae);
 577 }
 578
 579 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 580 {
 581         struct dmae_command dmae;
 582
 583         if (!bp->dmae_ready) {
 584                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 585                 int i;
 586
 587                 if (CHIP_IS_E1(bp))
 588                         for (i = 0; i < len32; i++)
 589                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 590                 else
 591                         for (i = 0; i < len32; i++)
 592                                 data[i] = REG_RD(bp, src_addr + i*4);
 593
 594                 return;
 595         }
 596
 597         /* set opcode and fixed command fields */
 598         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 599
 600         /* fill in addresses and len */
 601         dmae.src_addr_lo = src_addr >> 2;
 602         dmae.src_addr_hi = 0;
 603         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 604         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 605         dmae.len = len32;
 606
 607         /* issue the command and wait for completion */
 608         bnx2x_issue_dmae_with_comp(bp, &dmae);
 609 }
 610
 611 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 612                                       u32 addr, u32 len)
 613 {
 614         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 615         int offset = 0;
 616
 617         while (len > dmae_wr_max) {
 618                 bnx2x_write_dmae(bp, phys_addr + offset,
 619                                  addr + offset, dmae_wr_max);
 620                 offset += dmae_wr_max * 4;
 621                 len -= dmae_wr_max;
 622         }
 623
 624         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 625 }
 626
 627 static int bnx2x_mc_assert(struct bnx2x *bp)
 628 {
 629         char last_idx;
 630         int i, rc = 0;
 631         u32 row0, row1, row2, row3;
 632
 633         /* XSTORM */
 634         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 635                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 636         if (last_idx)
 637                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 638
 639         /* print the asserts */
 640         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 641
 642                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 643                               XSTORM_ASSERT_LIST_OFFSET(i));
 644                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 645                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 646                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 647                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 648                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 649                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 650
 651                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 652                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 653                                   i, row3, row2, row1, row0);
 654                         rc++;
 655                 } else {
 656                         break;
 657                 }
 658         }
 659
 660         /* TSTORM */
 661         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 662                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 663         if (last_idx)
 664                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 665
 666         /* print the asserts */
 667         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 668
 669                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 670                               TSTORM_ASSERT_LIST_OFFSET(i));
 671                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 672                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 673                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 674                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 675                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 676                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 677
 678                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 679                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 680                                   i, row3, row2, row1, row0);
 681                         rc++;
 682                 } else {
 683                         break;
 684                 }
 685         }
 686
 687         /* CSTORM */
 688         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 689                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 690         if (last_idx)
 691                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 692
 693         /* print the asserts */
 694         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 695
 696                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 697                               CSTORM_ASSERT_LIST_OFFSET(i));
 698                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 699                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 700                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 701                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 702                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 703                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 704
 705                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 706                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 707                                   i, row3, row2, row1, row0);
 708                         rc++;
 709                 } else {
 710                         break;
 711                 }
 712         }
 713
 714         /* USTORM */
 715         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 716                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 717         if (last_idx)
 718                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 719
 720         /* print the asserts */
 721         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 722
 723                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 724                               USTORM_ASSERT_LIST_OFFSET(i));
 725                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 726                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 727                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 728                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 729                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 730                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 731
 732                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 733                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 734                                   i, row3, row2, row1, row0);
 735                         rc++;
 736                 } else {
 737                         break;
 738                 }
 739         }
 740
 741         return rc;
 742 }
 743
 744 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 745 {
 746         u32 addr, val;
 747         u32 mark, offset;
 748         __be32 data[9];
 749         int word;
 750         u32 trace_shmem_base;
 751         if (BP_NOMCP(bp)) {
 752                 BNX2X_ERR("NO MCP - can not dump\n");
 753                 return;
 754         }
 755         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 756                 (bp->common.bc_ver & 0xff0000) >> 16,
 757                 (bp->common.bc_ver & 0xff00) >> 8,
 758                 (bp->common.bc_ver & 0xff));
 759
 760         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 761         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 762                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 763
 764         if (BP_PATH(bp) == 0)
 765                 trace_shmem_base = bp->common.shmem_base;
 766         else
 767                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 768         addr = trace_shmem_base - 0x800;
 769
 770         /* validate TRCB signature */
 771         mark = REG_RD(bp, addr);
 772         if (mark != MFW_TRACE_SIGNATURE) {
 773                 BNX2X_ERR("Trace buffer signature is missing.");
 774                 return ;
 775         }
 776
 777         /* read cyclic buffer pointer */
 778         addr += 4;
 779         mark = REG_RD(bp, addr);
 780         mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
 781                         + ((mark + 0x3) & ~0x3) - 0x08000000;
 782         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 783
 784         printk("%s", lvl);
 785         for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
 786                 for (word = 0; word < 8; word++)
 787                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 788                 data[8] = 0x0;
 789                 pr_cont("%s", (char *)data);
 790         }
 791         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 792                 for (word = 0; word < 8; word++)
 793                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 794                 data[8] = 0x0;
 795                 pr_cont("%s", (char *)data);
 796         }
 797         printk("%s" "end of fw dump\n", lvl);
 798 }
 799
 800 static void bnx2x_fw_dump(struct bnx2x *bp)
 801 {
 802         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 803 }
 804
 805 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 806 {
 807         int port = BP_PORT(bp);
 808         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 809         u32 val = REG_RD(bp, addr);
 810
 811         /* in E1 we must use only PCI configuration space to disable
 812          * MSI/MSIX capablility
 813          * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 814          */
 815         if (CHIP_IS_E1(bp)) {
 816                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 817                  * Use mask register to prevent from HC sending interrupts
 818                  * after we exit the function
 819                  */
 820                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 821
 822                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 823                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 824                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 825         } else
 826                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 827                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 828                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 829                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 830
 831         DP(NETIF_MSG_IFDOWN,
 832            "write %x to HC %d (addr 0x%x)\n",
 833            val, port, addr);
 834
 835         /* flush all outstanding writes */
 836         mmiowb();
 837
 838         REG_WR(bp, addr, val);
 839         if (REG_RD(bp, addr) != val)
 840                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
 841 }
 842
 843 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 844 {
 845         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 846
 847         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 848                  IGU_PF_CONF_INT_LINE_EN |
 849                  IGU_PF_CONF_ATTN_BIT_EN);
 850
 851         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 852
 853         /* flush all outstanding writes */
 854         mmiowb();
 855
 856         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 857         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 858                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
 859 }
 860
 861 static void bnx2x_int_disable(struct bnx2x *bp)
 862 {
 863         if (bp->common.int_block == INT_BLOCK_HC)
 864                 bnx2x_hc_int_disable(bp);
 865         else
 866                 bnx2x_igu_int_disable(bp);
 867 }
 868
 869 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 870 {
 871         int i;
 872         u16 j;
 873         struct hc_sp_status_block_data sp_sb_data;
 874         int func = BP_FUNC(bp);
 875 #ifdef BNX2X_STOP_ON_ERROR
 876         u16 start = 0, end = 0;
 877         u8 cos;
 878 #endif
 879         if (disable_int)
 880                 bnx2x_int_disable(bp);
 881
 882         bp->stats_state = STATS_STATE_DISABLED;
 883         bp->eth_stats.unrecoverable_error++;
 884         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 885
 886         BNX2X_ERR("begin crash dump -----------------\n");
 887
 888         /* Indices */
 889         /* Common */
 890         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 891                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 892                   bp->spq_prod_idx, bp->stats_counter);
 893         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 894                   bp->def_status_blk->atten_status_block.attn_bits,
 895                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 896                   bp->def_status_blk->atten_status_block.status_block_id,
 897                   bp->def_status_blk->atten_status_block.attn_bits_index);
 898         BNX2X_ERR("     def (");
 899         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 900                 pr_cont("0x%x%s",
 901                         bp->def_status_blk->sp_sb.index_values[i],
 902                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 903
 904         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 905                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 906                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 907                         i*sizeof(u32));
 908
 909         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 910                sp_sb_data.igu_sb_id,
 911                sp_sb_data.igu_seg_id,
 912                sp_sb_data.p_func.pf_id,
 913                sp_sb_data.p_func.vnic_id,
 914                sp_sb_data.p_func.vf_id,
 915                sp_sb_data.p_func.vf_valid,
 916                sp_sb_data.state);
 917
 918
 919         for_each_eth_queue(bp, i) {
 920                 struct bnx2x_fastpath *fp = &bp->fp[i];
 921                 int loop;
 922                 struct hc_status_block_data_e2 sb_data_e2;
 923                 struct hc_status_block_data_e1x sb_data_e1x;
 924                 struct hc_status_block_sm  *hc_sm_p =
 925                         CHIP_IS_E1x(bp) ?
 926                         sb_data_e1x.common.state_machine :
 927                         sb_data_e2.common.state_machine;
 928                 struct hc_index_data *hc_index_p =
 929                         CHIP_IS_E1x(bp) ?
 930                         sb_data_e1x.index_data :
 931                         sb_data_e2.index_data;
 932                 u8 data_size, cos;
 933                 u32 *sb_data_p;
 934                 struct bnx2x_fp_txdata txdata;
 935
 936                 /* Rx */
 937                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 938                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 939                           fp->rx_comp_prod,
 940                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 941                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 942                           fp->rx_sge_prod, fp->last_max_sge,
 943                           le16_to_cpu(fp->fp_hc_idx));
 944
 945                 /* Tx */
 946                 for_each_cos_in_tx_queue(fp, cos)
 947                 {
 948                         txdata = *fp->txdata_ptr[cos];
 949                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 950                                   i, txdata.tx_pkt_prod,
 951                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 952                                   txdata.tx_bd_cons,
 953                                   le16_to_cpu(*txdata.tx_cons_sb));
 954                 }
 955
 956                 loop = CHIP_IS_E1x(bp) ?
 957                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 958
 959                 /* host sb data */
 960
 961                 if (IS_FCOE_FP(fp))
 962                         continue;
 963
 964                 BNX2X_ERR("     run indexes (");
 965                 for (j = 0; j < HC_SB_MAX_SM; j++)
 966                         pr_cont("0x%x%s",
 967                                fp->sb_running_index[j],
 968                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
 969
 970                 BNX2X_ERR("     indexes (");
 971                 for (j = 0; j < loop; j++)
 972                         pr_cont("0x%x%s",
 973                                fp->sb_index_values[j],
 974                                (j == loop - 1) ? ")" : " ");
 975                 /* fw sb data */
 976                 data_size = CHIP_IS_E1x(bp) ?
 977                         sizeof(struct hc_status_block_data_e1x) :
 978                         sizeof(struct hc_status_block_data_e2);
 979                 data_size /= sizeof(u32);
 980                 sb_data_p = CHIP_IS_E1x(bp) ?
 981                         (u32 *)&sb_data_e1x :
 982                         (u32 *)&sb_data_e2;
 983                 /* copy sb data in here */
 984                 for (j = 0; j < data_size; j++)
 985                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 986                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
 987                                 j * sizeof(u32));
 988
 989                 if (!CHIP_IS_E1x(bp)) {
 990                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
 991                                 sb_data_e2.common.p_func.pf_id,
 992                                 sb_data_e2.common.p_func.vf_id,
 993                                 sb_data_e2.common.p_func.vf_valid,
 994                                 sb_data_e2.common.p_func.vnic_id,
 995                                 sb_data_e2.common.same_igu_sb_1b,
 996                                 sb_data_e2.common.state);
 997                 } else {
 998                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
 999                                 sb_data_e1x.common.p_func.pf_id,
1000                                 sb_data_e1x.common.p_func.vf_id,
1001                                 sb_data_e1x.common.p_func.vf_valid,
1002                                 sb_data_e1x.common.p_func.vnic_id,
1003                                 sb_data_e1x.common.same_igu_sb_1b,
1004                                 sb_data_e1x.common.state);
1005                 }
1006
1007                 /* SB_SMs data */
1008                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1009                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1010                                 j, hc_sm_p[j].__flags,
1011                                 hc_sm_p[j].igu_sb_id,
1012                                 hc_sm_p[j].igu_seg_id,
1013                                 hc_sm_p[j].time_to_expire,
1014                                 hc_sm_p[j].timer_value);
1015                 }
1016
1017                 /* Indecies data */
1018                 for (j = 0; j < loop; j++) {
1019                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1020                                hc_index_p[j].flags,
1021                                hc_index_p[j].timeout);
1022                 }
1023         }
1024
1025 #ifdef BNX2X_STOP_ON_ERROR
1026         /* Rings */
1027         /* Rx */
1028         for_each_valid_rx_queue(bp, i) {
1029                 struct bnx2x_fastpath *fp = &bp->fp[i];
1030
1031                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1032                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1033                 for (j = start; j != end; j = RX_BD(j + 1)) {
1034                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1035                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1036
1037                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1038                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1039                 }
1040
1041                 start = RX_SGE(fp->rx_sge_prod);
1042                 end = RX_SGE(fp->last_max_sge);
1043                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1044                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1045                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1046
1047                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1048                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1049                 }
1050
1051                 start = RCQ_BD(fp->rx_comp_cons - 10);
1052                 end = RCQ_BD(fp->rx_comp_cons + 503);
1053                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1054                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1055
1056                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1057                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1058                 }
1059         }
1060
1061         /* Tx */
1062         for_each_valid_tx_queue(bp, i) {
1063                 struct bnx2x_fastpath *fp = &bp->fp[i];
1064                 for_each_cos_in_tx_queue(fp, cos) {
1065                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1066
1067                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1068                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1069                         for (j = start; j != end; j = TX_BD(j + 1)) {
1070                                 struct sw_tx_bd *sw_bd =
1071                                         &txdata->tx_buf_ring[j];
1072
1073                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1074                                           i, cos, j, sw_bd->skb,
1075                                           sw_bd->first_bd);
1076                         }
1077
1078                         start = TX_BD(txdata->tx_bd_cons - 10);
1079                         end = TX_BD(txdata->tx_bd_cons + 254);
1080                         for (j = start; j != end; j = TX_BD(j + 1)) {
1081                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1082
1083                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1084                                           i, cos, j, tx_bd[0], tx_bd[1],
1085                                           tx_bd[2], tx_bd[3]);
1086                         }
1087                 }
1088         }
1089 #endif
1090         bnx2x_fw_dump(bp);
1091         bnx2x_mc_assert(bp);
1092         BNX2X_ERR("end crash dump -----------------\n");
1093 }
1094
1095 /*
1096  * FLR Support for E2
1097  *
1098  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1099  * initialization.
1100  */
1101 #define FLR_WAIT_USEC           10000   /* 10 miliseconds */
1102 #define FLR_WAIT_INTERVAL       50      /* usec */
1103 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1104
1105 struct pbf_pN_buf_regs {
1106         int pN;
1107         u32 init_crd;
1108         u32 crd;
1109         u32 crd_freed;
1110 };
1111
1112 struct pbf_pN_cmd_regs {
1113         int pN;
1114         u32 lines_occup;
1115         u32 lines_freed;
1116 };
1117
1118 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1119                                      struct pbf_pN_buf_regs *regs,
1120                                      u32 poll_count)
1121 {
1122         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1123         u32 cur_cnt = poll_count;
1124
1125         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1126         crd = crd_start = REG_RD(bp, regs->crd);
1127         init_crd = REG_RD(bp, regs->init_crd);
1128
1129         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1130         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1131         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1132
1133         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1134                (init_crd - crd_start))) {
1135                 if (cur_cnt--) {
1136                         udelay(FLR_WAIT_INTERVAL);
1137                         crd = REG_RD(bp, regs->crd);
1138                         crd_freed = REG_RD(bp, regs->crd_freed);
1139                 } else {
1140                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1141                            regs->pN);
1142                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1143                            regs->pN, crd);
1144                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1145                            regs->pN, crd_freed);
1146                         break;
1147                 }
1148         }
1149         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1150            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1151 }
1152
1153 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1154                                      struct pbf_pN_cmd_regs *regs,
1155                                      u32 poll_count)
1156 {
1157         u32 occup, to_free, freed, freed_start;
1158         u32 cur_cnt = poll_count;
1159
1160         occup = to_free = REG_RD(bp, regs->lines_occup);
1161         freed = freed_start = REG_RD(bp, regs->lines_freed);
1162
1163         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1164         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1165
1166         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1167                 if (cur_cnt--) {
1168                         udelay(FLR_WAIT_INTERVAL);
1169                         occup = REG_RD(bp, regs->lines_occup);
1170                         freed = REG_RD(bp, regs->lines_freed);
1171                 } else {
1172                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1173                            regs->pN);
1174                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1175                            regs->pN, occup);
1176                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1177                            regs->pN, freed);
1178                         break;
1179                 }
1180         }
1181         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1182            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1183 }
1184
1185 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1186                                     u32 expected, u32 poll_count)
1187 {
1188         u32 cur_cnt = poll_count;
1189         u32 val;
1190
1191         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1192                 udelay(FLR_WAIT_INTERVAL);
1193
1194         return val;
1195 }
1196
1197 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1198                                     char *msg, u32 poll_cnt)
1199 {
1200         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1201         if (val != 0) {
1202                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1203                 return 1;
1204         }
1205         return 0;
1206 }
1207
1208 /* Common routines with VF FLR cleanup */
1209 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1210 {
1211         /* adjust polling timeout */
1212         if (CHIP_REV_IS_EMUL(bp))
1213                 return FLR_POLL_CNT * 2000;
1214
1215         if (CHIP_REV_IS_FPGA(bp))
1216                 return FLR_POLL_CNT * 120;
1217
1218         return FLR_POLL_CNT;
1219 }
1220
1221 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1222 {
1223         struct pbf_pN_cmd_regs cmd_regs[] = {
1224                 {0, (CHIP_IS_E3B0(bp)) ?
1225                         PBF_REG_TQ_OCCUPANCY_Q0 :
1226                         PBF_REG_P0_TQ_OCCUPANCY,
1227                     (CHIP_IS_E3B0(bp)) ?
1228                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1229                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1230                 {1, (CHIP_IS_E3B0(bp)) ?
1231                         PBF_REG_TQ_OCCUPANCY_Q1 :
1232                         PBF_REG_P1_TQ_OCCUPANCY,
1233                     (CHIP_IS_E3B0(bp)) ?
1234                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1235                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1236                 {4, (CHIP_IS_E3B0(bp)) ?
1237                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1238                         PBF_REG_P4_TQ_OCCUPANCY,
1239                     (CHIP_IS_E3B0(bp)) ?
1240                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1241                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1242         };
1243
1244         struct pbf_pN_buf_regs buf_regs[] = {
1245                 {0, (CHIP_IS_E3B0(bp)) ?
1246                         PBF_REG_INIT_CRD_Q0 :
1247                         PBF_REG_P0_INIT_CRD ,
1248                     (CHIP_IS_E3B0(bp)) ?
1249                         PBF_REG_CREDIT_Q0 :
1250                         PBF_REG_P0_CREDIT,
1251                     (CHIP_IS_E3B0(bp)) ?
1252                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1253                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1254                 {1, (CHIP_IS_E3B0(bp)) ?
1255                         PBF_REG_INIT_CRD_Q1 :
1256                         PBF_REG_P1_INIT_CRD,
1257                     (CHIP_IS_E3B0(bp)) ?
1258                         PBF_REG_CREDIT_Q1 :
1259                         PBF_REG_P1_CREDIT,
1260                     (CHIP_IS_E3B0(bp)) ?
1261                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1262                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1263                 {4, (CHIP_IS_E3B0(bp)) ?
1264                         PBF_REG_INIT_CRD_LB_Q :
1265                         PBF_REG_P4_INIT_CRD,
1266                     (CHIP_IS_E3B0(bp)) ?
1267                         PBF_REG_CREDIT_LB_Q :
1268                         PBF_REG_P4_CREDIT,
1269                     (CHIP_IS_E3B0(bp)) ?
1270                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1271                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1272         };
1273
1274         int i;
1275
1276         /* Verify the command queues are flushed P0, P1, P4 */
1277         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1278                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1279
1280
1281         /* Verify the transmission buffers are flushed P0, P1, P4 */
1282         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1283                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1284 }
1285
1286 #define OP_GEN_PARAM(param) \
1287         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1288
1289 #define OP_GEN_TYPE(type) \
1290         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1291
1292 #define OP_GEN_AGG_VECT(index) \
1293         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1294
1295
1296 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1297 {
1298         struct sdm_op_gen op_gen = {0};
1299
1300         u32 comp_addr = BAR_CSTRORM_INTMEM +
1301                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1302         int ret = 0;
1303
1304         if (REG_RD(bp, comp_addr)) {
1305                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1306                 return 1;
1307         }
1308
1309         op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1310         op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1311         op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1312         op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1313
1314         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1315         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1316
1317         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1318                 BNX2X_ERR("FW final cleanup did not succeed\n");
1319                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1320                    (REG_RD(bp, comp_addr)));
1321                 bnx2x_panic();
1322                 return 1;
1323         }
1324         /* Zero completion for nxt FLR */
1325         REG_WR(bp, comp_addr, 0);
1326
1327         return ret;
1328 }
1329
1330 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1331 {
1332         u16 status;
1333
1334         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1335         return status & PCI_EXP_DEVSTA_TRPND;
1336 }
1337
1338 /* PF FLR specific routines
1339 */
1340 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1341 {
1342
1343         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1344         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1345                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1346                         "CFC PF usage counter timed out",
1347                         poll_cnt))
1348                 return 1;
1349
1350
1351         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1352         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1353                         DORQ_REG_PF_USAGE_CNT,
1354                         "DQ PF usage counter timed out",
1355                         poll_cnt))
1356                 return 1;
1357
1358         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1359         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1360                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1361                         "QM PF usage counter timed out",
1362                         poll_cnt))
1363                 return 1;
1364
1365         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1366         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1367                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1368                         "Timers VNIC usage counter timed out",
1369                         poll_cnt))
1370                 return 1;
1371         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1372                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1373                         "Timers NUM_SCANS usage counter timed out",
1374                         poll_cnt))
1375                 return 1;
1376
1377         /* Wait DMAE PF usage counter to zero */
1378         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1379                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1380                         "DMAE dommand register timed out",
1381                         poll_cnt))
1382                 return 1;
1383
1384         return 0;
1385 }
1386
1387 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1388 {
1389         u32 val;
1390
1391         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1392         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1393
1394         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1395         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1396
1397         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1398         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1399
1400         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1401         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1402
1403         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1404         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1405
1406         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1407         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1408
1409         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1410         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1411
1412         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1413         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1414            val);
1415 }
1416
1417 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1418 {
1419         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1420
1421         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1422
1423         /* Re-enable PF target read access */
1424         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1425
1426         /* Poll HW usage counters */
1427         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1428         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1429                 return -EBUSY;
1430
1431         /* Zero the igu 'trailing edge' and 'leading edge' */
1432
1433         /* Send the FW cleanup command */
1434         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1435                 return -EBUSY;
1436
1437         /* ATC cleanup */
1438
1439         /* Verify TX hw is flushed */
1440         bnx2x_tx_hw_flushed(bp, poll_cnt);
1441
1442         /* Wait 100ms (not adjusted according to platform) */
1443         msleep(100);
1444
1445         /* Verify no pending pci transactions */
1446         if (bnx2x_is_pcie_pending(bp->pdev))
1447                 BNX2X_ERR("PCIE Transactions still pending\n");
1448
1449         /* Debug */
1450         bnx2x_hw_enable_status(bp);
1451
1452         /*
1453          * Master enable - Due to WB DMAE writes performed before this
1454          * register is re-initialized as part of the regular function init
1455          */
1456         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1457
1458         return 0;
1459 }
1460
1461 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1462 {
1463         int port = BP_PORT(bp);
1464         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1465         u32 val = REG_RD(bp, addr);
1466         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1467         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1468         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1469
1470         if (msix) {
1471                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1472                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1473                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1474                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1475                 if (single_msix)
1476                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1477         } else if (msi) {
1478                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1479                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1480                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1481                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1482         } else {
1483                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1484                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1485                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1486                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1487
1488                 if (!CHIP_IS_E1(bp)) {
1489                         DP(NETIF_MSG_IFUP,
1490                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1491
1492                         REG_WR(bp, addr, val);
1493
1494                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1495                 }
1496         }
1497
1498         if (CHIP_IS_E1(bp))
1499                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1500
1501         DP(NETIF_MSG_IFUP,
1502            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1503            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1504
1505         REG_WR(bp, addr, val);
1506         /*
1507          * Ensure that HC_CONFIG is written before leading/trailing edge config
1508          */
1509         mmiowb();
1510         barrier();
1511
1512         if (!CHIP_IS_E1(bp)) {
1513                 /* init leading/trailing edge */
1514                 if (IS_MF(bp)) {
1515                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1516                         if (bp->port.pmf)
1517                                 /* enable nig and gpio3 attention */
1518                                 val |= 0x1100;
1519                 } else
1520                         val = 0xffff;
1521
1522                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1523                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1524         }
1525
1526         /* Make sure that interrupts are indeed enabled from here on */
1527         mmiowb();
1528 }
1529
1530 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1531 {
1532         u32 val;
1533         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1534         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1535         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1536
1537         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1538
1539         if (msix) {
1540                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1541                          IGU_PF_CONF_SINGLE_ISR_EN);
1542                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1543                         IGU_PF_CONF_ATTN_BIT_EN);
1544
1545                 if (single_msix)
1546                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1547         } else if (msi) {
1548                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1549                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1550                         IGU_PF_CONF_ATTN_BIT_EN |
1551                         IGU_PF_CONF_SINGLE_ISR_EN);
1552         } else {
1553                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1554                 val |= (IGU_PF_CONF_INT_LINE_EN |
1555                         IGU_PF_CONF_ATTN_BIT_EN |
1556                         IGU_PF_CONF_SINGLE_ISR_EN);
1557         }
1558
1559         /* Clean previous status - need to configure igu prior to ack*/
1560         if ((!msix) || single_msix) {
1561                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1562                 bnx2x_ack_int(bp);
1563         }
1564
1565         val |= IGU_PF_CONF_FUNC_EN;
1566
1567         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1568            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1569
1570         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1571
1572         if (val & IGU_PF_CONF_INT_LINE_EN)
1573                 pci_intx(bp->pdev, true);
1574
1575         barrier();
1576
1577         /* init leading/trailing edge */
1578         if (IS_MF(bp)) {
1579                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1580                 if (bp->port.pmf)
1581                         /* enable nig and gpio3 attention */
1582                         val |= 0x1100;
1583         } else
1584                 val = 0xffff;
1585
1586         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1587         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1588
1589         /* Make sure that interrupts are indeed enabled from here on */
1590         mmiowb();
1591 }
1592
1593 void bnx2x_int_enable(struct bnx2x *bp)
1594 {
1595         if (bp->common.int_block == INT_BLOCK_HC)
1596                 bnx2x_hc_int_enable(bp);
1597         else
1598                 bnx2x_igu_int_enable(bp);
1599 }
1600
1601 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1602 {
1603         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1604         int i, offset;
1605
1606         if (disable_hw)
1607                 /* prevent the HW from sending interrupts */
1608                 bnx2x_int_disable(bp);
1609
1610         /* make sure all ISRs are done */
1611         if (msix) {
1612                 synchronize_irq(bp->msix_table[0].vector);
1613                 offset = 1;
1614                 if (CNIC_SUPPORT(bp))
1615                         offset++;
1616                 for_each_eth_queue(bp, i)
1617                         synchronize_irq(bp->msix_table[offset++].vector);
1618         } else
1619                 synchronize_irq(bp->pdev->irq);
1620
1621         /* make sure sp_task is not running */
1622         cancel_delayed_work(&bp->sp_task);
1623         cancel_delayed_work(&bp->period_task);
1624         flush_workqueue(bnx2x_wq);
1625 }
1626
1627 /* fast path */
1628
1629 /*
1630  * General service functions
1631  */
1632
1633 /* Return true if succeeded to acquire the lock */
1634 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1635 {
1636         u32 lock_status;
1637         u32 resource_bit = (1 << resource);
1638         int func = BP_FUNC(bp);
1639         u32 hw_lock_control_reg;
1640
1641         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1642            "Trying to take a lock on resource %d\n", resource);
1643
1644         /* Validating that the resource is within range */
1645         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1646                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1647                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1648                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1649                 return false;
1650         }
1651
1652         if (func <= 5)
1653                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1654         else
1655                 hw_lock_control_reg =
1656                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1657
1658         /* Try to acquire the lock */
1659         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1660         lock_status = REG_RD(bp, hw_lock_control_reg);
1661         if (lock_status & resource_bit)
1662                 return true;
1663
1664         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1665            "Failed to get a lock on resource %d\n", resource);
1666         return false;
1667 }
1668
1669 /**
1670  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1671  *
1672  * @bp: driver handle
1673  *
1674  * Returns the recovery leader resource id according to the engine this function
1675  * belongs to. Currently only only 2 engines is supported.
1676  */
1677 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1678 {
1679         if (BP_PATH(bp))
1680                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1681         else
1682                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1683 }
1684
1685 /**
1686  * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1687  *
1688  * @bp: driver handle
1689  *
1690  * Tries to aquire a leader lock for current engine.
1691  */
1692 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1693 {
1694         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1695 }
1696
1697 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1698
1699 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1700 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1701 {
1702         /* Set the interrupt occurred bit for the sp-task to recognize it
1703          * must ack the interrupt and transition according to the IGU
1704          * state machine.
1705          */
1706         atomic_set(&bp->interrupt_occurred, 1);
1707
1708         /* The sp_task must execute only after this bit
1709          * is set, otherwise we will get out of sync and miss all
1710          * further interrupts. Hence, the barrier.
1711          */
1712         smp_wmb();
1713
1714         /* schedule sp_task to workqueue */
1715         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1716 }
1717
1718 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1719 {
1720         struct bnx2x *bp = fp->bp;
1721         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1722         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1723         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1724         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1725
1726         DP(BNX2X_MSG_SP,
1727            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1728            fp->index, cid, command, bp->state,
1729            rr_cqe->ramrod_cqe.ramrod_type);
1730
1731         /* If cid is within VF range, replace the slowpath object with the
1732          * one corresponding to this VF
1733          */
1734         if (cid >= BNX2X_FIRST_VF_CID  &&
1735             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1736                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1737
1738         switch (command) {
1739         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1740                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1741                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1742                 break;
1743
1744         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1745                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1746                 drv_cmd = BNX2X_Q_CMD_SETUP;
1747                 break;
1748
1749         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1750                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1751                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1752                 break;
1753
1754         case (RAMROD_CMD_ID_ETH_HALT):
1755                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1756                 drv_cmd = BNX2X_Q_CMD_HALT;
1757                 break;
1758
1759         case (RAMROD_CMD_ID_ETH_TERMINATE):
1760                 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1761                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1762                 break;
1763
1764         case (RAMROD_CMD_ID_ETH_EMPTY):
1765                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1766                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1767                 break;
1768
1769         default:
1770                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1771                           command, fp->index);
1772                 return;
1773         }
1774
1775         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1776             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1777                 /* q_obj->complete_cmd() failure means that this was
1778                  * an unexpected completion.
1779                  *
1780                  * In this case we don't want to increase the bp->spq_left
1781                  * because apparently we haven't sent this command the first
1782                  * place.
1783                  */
1784 #ifdef BNX2X_STOP_ON_ERROR
1785                 bnx2x_panic();
1786 #else
1787                 return;
1788 #endif
1789         /* SRIOV: reschedule any 'in_progress' operations */
1790         bnx2x_iov_sp_event(bp, cid, true);
1791
1792         smp_mb__before_atomic_inc();
1793         atomic_inc(&bp->cq_spq_left);
1794         /* push the change in bp->spq_left and towards the memory */
1795         smp_mb__after_atomic_inc();
1796
1797         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1798
1799         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1800             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1801                 /* if Q update ramrod is completed for last Q in AFEX vif set
1802                  * flow, then ACK MCP at the end
1803                  *
1804                  * mark pending ACK to MCP bit.
1805                  * prevent case that both bits are cleared.
1806                  * At the end of load/unload driver checks that
1807                  * sp_state is cleaerd, and this order prevents
1808                  * races
1809                  */
1810                 smp_mb__before_clear_bit();
1811                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1812                 wmb();
1813                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1814                 smp_mb__after_clear_bit();
1815
1816                 /* schedule the sp task as mcp ack is required */
1817                 bnx2x_schedule_sp_task(bp);
1818         }
1819
1820         return;
1821 }
1822
1823 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1824 {
1825         struct bnx2x *bp = netdev_priv(dev_instance);
1826         u16 status = bnx2x_ack_int(bp);
1827         u16 mask;
1828         int i;
1829         u8 cos;
1830
1831         /* Return here if interrupt is shared and it's not for us */
1832         if (unlikely(status == 0)) {
1833                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1834                 return IRQ_NONE;
1835         }
1836         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1837
1838 #ifdef BNX2X_STOP_ON_ERROR
1839         if (unlikely(bp->panic))
1840                 return IRQ_HANDLED;
1841 #endif
1842
1843         for_each_eth_queue(bp, i) {
1844                 struct bnx2x_fastpath *fp = &bp->fp[i];
1845
1846                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1847                 if (status & mask) {
1848                         /* Handle Rx or Tx according to SB id */
1849                         prefetch(fp->rx_cons_sb);
1850                         for_each_cos_in_tx_queue(fp, cos)
1851                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1852                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1853                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1854                         status &= ~mask;
1855                 }
1856         }
1857
1858         if (CNIC_SUPPORT(bp)) {
1859                 mask = 0x2;
1860                 if (status & (mask | 0x1)) {
1861                         struct cnic_ops *c_ops = NULL;
1862
1863                         if (likely(bp->state == BNX2X_STATE_OPEN)) {
1864                                 rcu_read_lock();
1865                                 c_ops = rcu_dereference(bp->cnic_ops);
1866                                 if (c_ops)
1867                                         c_ops->cnic_handler(bp->cnic_data,
1868                                                             NULL);
1869                                 rcu_read_unlock();
1870                         }
1871
1872                         status &= ~mask;
1873                 }
1874         }
1875
1876         if (unlikely(status & 0x1)) {
1877
1878                 /* schedule sp task to perform default status block work, ack
1879                  * attentions and enable interrupts.
1880                  */
1881                 bnx2x_schedule_sp_task(bp);
1882
1883                 status &= ~0x1;
1884                 if (!status)
1885                         return IRQ_HANDLED;
1886         }
1887
1888         if (unlikely(status))
1889                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1890                    status);
1891
1892         return IRQ_HANDLED;
1893 }
1894
1895 /* Link */
1896
1897 /*
1898  * General service functions
1899  */
1900
1901 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1902 {
1903         u32 lock_status;
1904         u32 resource_bit = (1 << resource);
1905         int func = BP_FUNC(bp);
1906         u32 hw_lock_control_reg;
1907         int cnt;
1908
1909         /* Validating that the resource is within range */
1910         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1911                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1912                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1913                 return -EINVAL;
1914         }
1915
1916         if (func <= 5) {
1917                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1918         } else {
1919                 hw_lock_control_reg =
1920                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1921         }
1922
1923         /* Validating that the resource is not already taken */
1924         lock_status = REG_RD(bp, hw_lock_control_reg);
1925         if (lock_status & resource_bit) {
1926                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1927                    lock_status, resource_bit);
1928                 return -EEXIST;
1929         }
1930
1931         /* Try for 5 second every 5ms */
1932         for (cnt = 0; cnt < 1000; cnt++) {
1933                 /* Try to acquire the lock */
1934                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1935                 lock_status = REG_RD(bp, hw_lock_control_reg);
1936                 if (lock_status & resource_bit)
1937                         return 0;
1938
1939                 msleep(5);
1940         }
1941         BNX2X_ERR("Timeout\n");
1942         return -EAGAIN;
1943 }
1944
1945 int bnx2x_release_leader_lock(struct bnx2x *bp)
1946 {
1947         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1948 }
1949
1950 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1951 {
1952         u32 lock_status;
1953         u32 resource_bit = (1 << resource);
1954         int func = BP_FUNC(bp);
1955         u32 hw_lock_control_reg;
1956
1957         /* Validating that the resource is within range */
1958         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1959                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1960                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1961                 return -EINVAL;
1962         }
1963
1964         if (func <= 5) {
1965                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1966         } else {
1967                 hw_lock_control_reg =
1968                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1969         }
1970
1971         /* Validating that the resource is currently taken */
1972         lock_status = REG_RD(bp, hw_lock_control_reg);
1973         if (!(lock_status & resource_bit)) {
1974                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1975                    lock_status, resource_bit);
1976                 return -EFAULT;
1977         }
1978
1979         REG_WR(bp, hw_lock_control_reg, resource_bit);
1980         return 0;
1981 }
1982
1983
1984 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1985 {
1986         /* The GPIO should be swapped if swap register is set and active */
1987         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1988                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1989         int gpio_shift = gpio_num +
1990                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1991         u32 gpio_mask = (1 << gpio_shift);
1992         u32 gpio_reg;
1993         int value;
1994
1995         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1996                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1997                 return -EINVAL;
1998         }
1999
2000         /* read GPIO value */
2001         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2002
2003         /* get the requested pin value */
2004         if ((gpio_reg & gpio_mask) == gpio_mask)
2005                 value = 1;
2006         else
2007                 value = 0;
2008
2009         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
2010
2011         return value;
2012 }
2013
2014 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2015 {
2016         /* The GPIO should be swapped if swap register is set and active */
2017         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2018                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2019         int gpio_shift = gpio_num +
2020                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2021         u32 gpio_mask = (1 << gpio_shift);
2022         u32 gpio_reg;
2023
2024         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2025                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2026                 return -EINVAL;
2027         }
2028
2029         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2030         /* read GPIO and mask except the float bits */
2031         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2032
2033         switch (mode) {
2034         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2035                 DP(NETIF_MSG_LINK,
2036                    "Set GPIO %d (shift %d) -> output low\n",
2037                    gpio_num, gpio_shift);
2038                 /* clear FLOAT and set CLR */
2039                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2040                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2041                 break;
2042
2043         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2044                 DP(NETIF_MSG_LINK,
2045                    "Set GPIO %d (shift %d) -> output high\n",
2046                    gpio_num, gpio_shift);
2047                 /* clear FLOAT and set SET */
2048                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2049                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2050                 break;
2051
2052         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2053                 DP(NETIF_MSG_LINK,
2054                    "Set GPIO %d (shift %d) -> input\n",
2055                    gpio_num, gpio_shift);
2056                 /* set FLOAT */
2057                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2058                 break;
2059
2060         default:
2061                 break;
2062         }
2063
2064         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2065         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2066
2067         return 0;
2068 }
2069
2070 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2071 {
2072         u32 gpio_reg = 0;
2073         int rc = 0;
2074
2075         /* Any port swapping should be handled by caller. */
2076
2077         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2078         /* read GPIO and mask except the float bits */
2079         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2080         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2081         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2082         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2083
2084         switch (mode) {
2085         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2086                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2087                 /* set CLR */
2088                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2089                 break;
2090
2091         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2092                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2093                 /* set SET */
2094                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2095                 break;
2096
2097         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2098                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2099                 /* set FLOAT */
2100                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2101                 break;
2102
2103         default:
2104                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2105                 rc = -EINVAL;
2106                 break;
2107         }
2108
2109         if (rc == 0)
2110                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2111
2112         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2113
2114         return rc;
2115 }
2116
2117 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2118 {
2119         /* The GPIO should be swapped if swap register is set and active */
2120         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2121                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2122         int gpio_shift = gpio_num +
2123                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2124         u32 gpio_mask = (1 << gpio_shift);
2125         u32 gpio_reg;
2126
2127         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2128                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2129                 return -EINVAL;
2130         }
2131
2132         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2133         /* read GPIO int */
2134         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2135
2136         switch (mode) {
2137         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2138                 DP(NETIF_MSG_LINK,
2139                    "Clear GPIO INT %d (shift %d) -> output low\n",
2140                    gpio_num, gpio_shift);
2141                 /* clear SET and set CLR */
2142                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2143                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2144                 break;
2145
2146         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2147                 DP(NETIF_MSG_LINK,
2148                    "Set GPIO INT %d (shift %d) -> output high\n",
2149                    gpio_num, gpio_shift);
2150                 /* clear CLR and set SET */
2151                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2152                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2153                 break;
2154
2155         default:
2156                 break;
2157         }
2158
2159         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2160         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2161
2162         return 0;
2163 }
2164
2165 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2166 {
2167         u32 spio_reg;
2168
2169         /* Only 2 SPIOs are configurable */
2170         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2171                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2172                 return -EINVAL;
2173         }
2174
2175         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2176         /* read SPIO and mask except the float bits */
2177         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2178
2179         switch (mode) {
2180         case MISC_SPIO_OUTPUT_LOW:
2181                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2182                 /* clear FLOAT and set CLR */
2183                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2184                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2185                 break;
2186
2187         case MISC_SPIO_OUTPUT_HIGH:
2188                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2189                 /* clear FLOAT and set SET */
2190                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2191                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2192                 break;
2193
2194         case MISC_SPIO_INPUT_HI_Z:
2195                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2196                 /* set FLOAT */
2197                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2198                 break;
2199
2200         default:
2201                 break;
2202         }
2203
2204         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2205         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2206
2207         return 0;
2208 }
2209
2210 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2211 {
2212         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2213         switch (bp->link_vars.ieee_fc &
2214                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2215         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2216                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2217                                                    ADVERTISED_Pause);
2218                 break;
2219
2220         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2221                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2222                                                   ADVERTISED_Pause);
2223                 break;
2224
2225         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2226                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2227                 break;
2228
2229         default:
2230                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2231                                                    ADVERTISED_Pause);
2232                 break;
2233         }
2234 }
2235
2236 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2237 {
2238         /* Initialize link parameters structure variables
2239          * It is recommended to turn off RX FC for jumbo frames
2240          *  for better performance
2241          */
2242         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2243                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2244         else
2245                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2246 }
2247
2248 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2249 {
2250         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2251         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2252
2253         if (!BP_NOMCP(bp)) {
2254                 bnx2x_set_requested_fc(bp);
2255                 bnx2x_acquire_phy_lock(bp);
2256
2257                 if (load_mode == LOAD_DIAG) {
2258                         struct link_params *lp = &bp->link_params;
2259                         lp->loopback_mode = LOOPBACK_XGXS;
2260                         /* do PHY loopback at 10G speed, if possible */
2261                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2262                                 if (lp->speed_cap_mask[cfx_idx] &
2263                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2264                                         lp->req_line_speed[cfx_idx] =
2265                                         SPEED_10000;
2266                                 else
2267                                         lp->req_line_speed[cfx_idx] =
2268                                         SPEED_1000;
2269                         }
2270                 }
2271
2272                 if (load_mode == LOAD_LOOPBACK_EXT) {
2273                         struct link_params *lp = &bp->link_params;
2274                         lp->loopback_mode = LOOPBACK_EXT;
2275                 }
2276
2277                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2278
2279                 bnx2x_release_phy_lock(bp);
2280
2281                 bnx2x_calc_fc_adv(bp);
2282
2283                 if (bp->link_vars.link_up) {
2284                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2285                         bnx2x_link_report(bp);
2286                 }
2287                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2288                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2289                 return rc;
2290         }
2291         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2292         return -EINVAL;
2293 }
2294
2295 void bnx2x_link_set(struct bnx2x *bp)
2296 {
2297         if (!BP_NOMCP(bp)) {
2298                 bnx2x_acquire_phy_lock(bp);
2299                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2300                 bnx2x_release_phy_lock(bp);
2301
2302                 bnx2x_calc_fc_adv(bp);
2303         } else
2304                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2305 }
2306
2307 static void bnx2x__link_reset(struct bnx2x *bp)
2308 {
2309         if (!BP_NOMCP(bp)) {
2310                 bnx2x_acquire_phy_lock(bp);
2311                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2312                 bnx2x_release_phy_lock(bp);
2313         } else
2314                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2315 }
2316
2317 void bnx2x_force_link_reset(struct bnx2x *bp)
2318 {
2319         bnx2x_acquire_phy_lock(bp);
2320         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2321         bnx2x_release_phy_lock(bp);
2322 }
2323
2324 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2325 {
2326         u8 rc = 0;
2327
2328         if (!BP_NOMCP(bp)) {
2329                 bnx2x_acquire_phy_lock(bp);
2330                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2331                                      is_serdes);
2332                 bnx2x_release_phy_lock(bp);
2333         } else
2334                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2335
2336         return rc;
2337 }
2338
2339
2340 /* Calculates the sum of vn_min_rates.
2341    It's needed for further normalizing of the min_rates.
2342    Returns:
2343      sum of vn_min_rates.
2344        or
2345      0 - if all the min_rates are 0.
2346      In the later case fainess algorithm should be deactivated.
2347      If not all min_rates are zero then those that are zeroes will be set to 1.
2348  */
2349 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2350                                       struct cmng_init_input *input)
2351 {
2352         int all_zero = 1;
2353         int vn;
2354
2355         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2356                 u32 vn_cfg = bp->mf_config[vn];
2357                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2358                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2359
2360                 /* Skip hidden vns */
2361                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2362                         vn_min_rate = 0;
2363                 /* If min rate is zero - set it to 1 */
2364                 else if (!vn_min_rate)
2365                         vn_min_rate = DEF_MIN_RATE;
2366                 else
2367                         all_zero = 0;
2368
2369                 input->vnic_min_rate[vn] = vn_min_rate;
2370         }
2371
2372         /* if ETS or all min rates are zeros - disable fairness */
2373         if (BNX2X_IS_ETS_ENABLED(bp)) {
2374                 input->flags.cmng_enables &=
2375                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2376                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2377         } else if (all_zero) {
2378                 input->flags.cmng_enables &=
2379                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2380                 DP(NETIF_MSG_IFUP,
2381                    "All MIN values are zeroes fairness will be disabled\n");
2382         } else
2383                 input->flags.cmng_enables |=
2384                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2385 }
2386
2387 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2388                                     struct cmng_init_input *input)
2389 {
2390         u16 vn_max_rate;
2391         u32 vn_cfg = bp->mf_config[vn];
2392
2393         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2394                 vn_max_rate = 0;
2395         else {
2396                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2397
2398                 if (IS_MF_SI(bp)) {
2399                         /* maxCfg in percents of linkspeed */
2400                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2401                 } else /* SD modes */
2402                         /* maxCfg is absolute in 100Mb units */
2403                         vn_max_rate = maxCfg * 100;
2404         }
2405
2406         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2407
2408         input->vnic_max_rate[vn] = vn_max_rate;
2409 }
2410
2411
2412 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2413 {
2414         if (CHIP_REV_IS_SLOW(bp))
2415                 return CMNG_FNS_NONE;
2416         if (IS_MF(bp))
2417                 return CMNG_FNS_MINMAX;
2418
2419         return CMNG_FNS_NONE;
2420 }
2421
2422 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2423 {
2424         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2425
2426         if (BP_NOMCP(bp))
2427                 return; /* what should be the default bvalue in this case */
2428
2429         /* For 2 port configuration the absolute function number formula
2430          * is:
2431          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2432          *
2433          *      and there are 4 functions per port
2434          *
2435          * For 4 port configuration it is
2436          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2437          *
2438          *      and there are 2 functions per port
2439          */
2440         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2441                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2442
2443                 if (func >= E1H_FUNC_MAX)
2444                         break;
2445
2446                 bp->mf_config[vn] =
2447                         MF_CFG_RD(bp, func_mf_config[func].config);
2448         }
2449         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2450                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2451                 bp->flags |= MF_FUNC_DIS;
2452         } else {
2453                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2454                 bp->flags &= ~MF_FUNC_DIS;
2455         }
2456 }
2457
2458 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2459 {
2460         struct cmng_init_input input;
2461         memset(&input, 0, sizeof(struct cmng_init_input));
2462
2463         input.port_rate = bp->link_vars.line_speed;
2464
2465         if (cmng_type == CMNG_FNS_MINMAX) {
2466                 int vn;
2467
2468                 /* read mf conf from shmem */
2469                 if (read_cfg)
2470                         bnx2x_read_mf_cfg(bp);
2471
2472                 /* vn_weight_sum and enable fairness if not 0 */
2473                 bnx2x_calc_vn_min(bp, &input);
2474
2475                 /* calculate and set min-max rate for each vn */
2476                 if (bp->port.pmf)
2477                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2478                                 bnx2x_calc_vn_max(bp, vn, &input);
2479
2480                 /* always enable rate shaping and fairness */
2481                 input.flags.cmng_enables |=
2482                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2483
2484                 bnx2x_init_cmng(&input, &bp->cmng);
2485                 return;
2486         }
2487
2488         /* rate shaping and fairness are disabled */
2489         DP(NETIF_MSG_IFUP,
2490            "rate shaping and fairness are disabled\n");
2491 }
2492
2493 static void storm_memset_cmng(struct bnx2x *bp,
2494                               struct cmng_init *cmng,
2495                               u8 port)
2496 {
2497         int vn;
2498         size_t size = sizeof(struct cmng_struct_per_port);
2499
2500         u32 addr = BAR_XSTRORM_INTMEM +
2501                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2502
2503         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2504
2505         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2506                 int func = func_by_vn(bp, vn);
2507
2508                 addr = BAR_XSTRORM_INTMEM +
2509                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2510                 size = sizeof(struct rate_shaping_vars_per_vn);
2511                 __storm_memset_struct(bp, addr, size,
2512                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2513
2514                 addr = BAR_XSTRORM_INTMEM +
2515                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2516                 size = sizeof(struct fairness_vars_per_vn);
2517                 __storm_memset_struct(bp, addr, size,
2518                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2519         }
2520 }
2521
2522 /* This function is called upon link interrupt */
2523 static void bnx2x_link_attn(struct bnx2x *bp)
2524 {
2525         /* Make sure that we are synced with the current statistics */
2526         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2527
2528         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2529
2530         if (bp->link_vars.link_up) {
2531
2532                 /* dropless flow control */
2533                 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2534                         int port = BP_PORT(bp);
2535                         u32 pause_enabled = 0;
2536
2537                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2538                                 pause_enabled = 1;
2539
2540                         REG_WR(bp, BAR_USTRORM_INTMEM +
2541                                USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2542                                pause_enabled);
2543                 }
2544
2545                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2546                         struct host_port_stats *pstats;
2547
2548                         pstats = bnx2x_sp(bp, port_stats);
2549                         /* reset old mac stats */
2550                         memset(&(pstats->mac_stx[0]), 0,
2551                                sizeof(struct mac_stx));
2552                 }
2553                 if (bp->state == BNX2X_STATE_OPEN)
2554                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2555         }
2556
2557         if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2558                 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2559
2560                 if (cmng_fns != CMNG_FNS_NONE) {
2561                         bnx2x_cmng_fns_init(bp, false, cmng_fns);
2562                         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2563                 } else
2564                         /* rate shaping and fairness are disabled */
2565                         DP(NETIF_MSG_IFUP,
2566                            "single function mode without fairness\n");
2567         }
2568
2569         __bnx2x_link_report(bp);
2570
2571         if (IS_MF(bp))
2572                 bnx2x_link_sync_notify(bp);
2573 }
2574
2575 void bnx2x__link_status_update(struct bnx2x *bp)
2576 {
2577         if (bp->state != BNX2X_STATE_OPEN)
2578                 return;
2579
2580         /* read updated dcb configuration */
2581         if (IS_PF(bp)) {
2582                 bnx2x_dcbx_pmf_update(bp);
2583                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2584                 if (bp->link_vars.link_up)
2585                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2586                 else
2587                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2588                         /* indicate link status */
2589                 bnx2x_link_report(bp);
2590
2591         } else { /* VF */
2592                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2593                                           SUPPORTED_10baseT_Full |
2594                                           SUPPORTED_100baseT_Half |
2595                                           SUPPORTED_100baseT_Full |
2596                                           SUPPORTED_1000baseT_Full |
2597                                           SUPPORTED_2500baseX_Full |
2598                                           SUPPORTED_10000baseT_Full |
2599                                           SUPPORTED_TP |
2600                                           SUPPORTED_FIBRE |
2601                                           SUPPORTED_Autoneg |
2602                                           SUPPORTED_Pause |
2603                                           SUPPORTED_Asym_Pause);
2604                 bp->port.advertising[0] = bp->port.supported[0];
2605
2606                 bp->link_params.bp = bp;
2607                 bp->link_params.port = BP_PORT(bp);
2608                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2609                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2610                 bp->link_params.req_line_speed[0] = SPEED_10000;
2611                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2612                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2613                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2614                 bp->link_vars.line_speed = SPEED_10000;
2615                 bp->link_vars.link_status =
2616                         (LINK_STATUS_LINK_UP |
2617                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2618                 bp->link_vars.link_up = 1;
2619                 bp->link_vars.duplex = DUPLEX_FULL;
2620                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2621                 __bnx2x_link_report(bp);
2622                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2623         }
2624 }
2625
2626 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2627                                   u16 vlan_val, u8 allowed_prio)
2628 {
2629         struct bnx2x_func_state_params func_params = {0};
2630         struct bnx2x_func_afex_update_params *f_update_params =
2631                 &func_params.params.afex_update;
2632
2633         func_params.f_obj = &bp->func_obj;
2634         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2635
2636         /* no need to wait for RAMROD completion, so don't
2637          * set RAMROD_COMP_WAIT flag
2638          */
2639
2640         f_update_params->vif_id = vifid;
2641         f_update_params->afex_default_vlan = vlan_val;
2642         f_update_params->allowed_priorities = allowed_prio;
2643
2644         /* if ramrod can not be sent, response to MCP immediately */
2645         if (bnx2x_func_state_change(bp, &func_params) < 0)
2646                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2647
2648         return 0;
2649 }
2650
2651 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2652                                           u16 vif_index, u8 func_bit_map)
2653 {
2654         struct bnx2x_func_state_params func_params = {0};
2655         struct bnx2x_func_afex_viflists_params *update_params =
2656                 &func_params.params.afex_viflists;
2657         int rc;
2658         u32 drv_msg_code;
2659
2660         /* validate only LIST_SET and LIST_GET are received from switch */
2661         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2662                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2663                           cmd_type);
2664
2665         func_params.f_obj = &bp->func_obj;
2666         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2667
2668         /* set parameters according to cmd_type */
2669         update_params->afex_vif_list_command = cmd_type;
2670         update_params->vif_list_index = cpu_to_le16(vif_index);
2671         update_params->func_bit_map =
2672                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2673         update_params->func_to_clear = 0;
2674         drv_msg_code =
2675                 (cmd_type == VIF_LIST_RULE_GET) ?
2676                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2677                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2678
2679         /* if ramrod can not be sent, respond to MCP immediately for
2680          * SET and GET requests (other are not triggered from MCP)
2681          */
2682         rc = bnx2x_func_state_change(bp, &func_params);
2683         if (rc < 0)
2684                 bnx2x_fw_command(bp, drv_msg_code, 0);
2685
2686         return 0;
2687 }
2688
2689 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2690 {
2691         struct afex_stats afex_stats;
2692         u32 func = BP_ABS_FUNC(bp);
2693         u32 mf_config;
2694         u16 vlan_val;
2695         u32 vlan_prio;
2696         u16 vif_id;
2697         u8 allowed_prio;
2698         u8 vlan_mode;
2699         u32 addr_to_write, vifid, addrs, stats_type, i;
2700
2701         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2702                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2703                 DP(BNX2X_MSG_MCP,
2704                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2705                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2706         }
2707
2708         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2709                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2710                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2711                 DP(BNX2X_MSG_MCP,
2712                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2713                    vifid, addrs);
2714                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2715                                                addrs);
2716         }
2717
2718         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2719                 addr_to_write = SHMEM2_RD(bp,
2720                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2721                 stats_type = SHMEM2_RD(bp,
2722                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2723
2724                 DP(BNX2X_MSG_MCP,
2725                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2726                    addr_to_write);
2727
2728                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2729
2730                 /* write response to scratchpad, for MCP */
2731                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2732                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2733                                *(((u32 *)(&afex_stats))+i));
2734
2735                 /* send ack message to MCP */
2736                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2737         }
2738
2739         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2740                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2741                 bp->mf_config[BP_VN(bp)] = mf_config;
2742                 DP(BNX2X_MSG_MCP,
2743                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2744                    mf_config);
2745
2746                 /* if VIF_SET is "enabled" */
2747                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2748                         /* set rate limit directly to internal RAM */
2749                         struct cmng_init_input cmng_input;
2750                         struct rate_shaping_vars_per_vn m_rs_vn;
2751                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2752                         u32 addr = BAR_XSTRORM_INTMEM +
2753                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2754
2755                         bp->mf_config[BP_VN(bp)] = mf_config;
2756
2757                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2758                         m_rs_vn.vn_counter.rate =
2759                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2760                         m_rs_vn.vn_counter.quota =
2761                                 (m_rs_vn.vn_counter.rate *
2762                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2763
2764                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2765
2766                         /* read relevant values from mf_cfg struct in shmem */
2767                         vif_id =
2768                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2769                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2770                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2771                         vlan_val =
2772                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2773                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2774                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2775                         vlan_prio = (mf_config &
2776                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2777                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2778                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2779                         vlan_mode =
2780                                 (MF_CFG_RD(bp,
2781                                            func_mf_config[func].afex_config) &
2782                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2783                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2784                         allowed_prio =
2785                                 (MF_CFG_RD(bp,
2786                                            func_mf_config[func].afex_config) &
2787                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2788                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2789
2790                         /* send ramrod to FW, return in case of failure */
2791                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2792                                                    allowed_prio))
2793                                 return;
2794
2795                         bp->afex_def_vlan_tag = vlan_val;
2796                         bp->afex_vlan_mode = vlan_mode;
2797                 } else {
2798                         /* notify link down because BP->flags is disabled */
2799                         bnx2x_link_report(bp);
2800
2801                         /* send INVALID VIF ramrod to FW */
2802                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2803
2804                         /* Reset the default afex VLAN */
2805                         bp->afex_def_vlan_tag = -1;
2806                 }
2807         }
2808 }
2809
2810 static void bnx2x_pmf_update(struct bnx2x *bp)
2811 {
2812         int port = BP_PORT(bp);
2813         u32 val;
2814
2815         bp->port.pmf = 1;
2816         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2817
2818         /*
2819          * We need the mb() to ensure the ordering between the writing to
2820          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2821          */
2822         smp_mb();
2823
2824         /* queue a periodic task */
2825         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2826
2827         bnx2x_dcbx_pmf_update(bp);
2828
2829         /* enable nig attention */
2830         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2831         if (bp->common.int_block == INT_BLOCK_HC) {
2832                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2833                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2834         } else if (!CHIP_IS_E1x(bp)) {
2835                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2836                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2837         }
2838
2839         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2840 }
2841
2842 /* end of Link */
2843
2844 /* slow path */
2845
2846 /*
2847  * General service functions
2848  */
2849
2850 /* send the MCP a request, block until there is a reply */
2851 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2852 {
2853         int mb_idx = BP_FW_MB_IDX(bp);
2854         u32 seq;
2855         u32 rc = 0;
2856         u32 cnt = 1;
2857         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2858
2859         mutex_lock(&bp->fw_mb_mutex);
2860         seq = ++bp->fw_seq;
2861         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2862         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2863
2864         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2865                         (command | seq), param);
2866
2867         do {
2868                 /* let the FW do it's magic ... */
2869                 msleep(delay);
2870
2871                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2872
2873                 /* Give the FW up to 5 second (500*10ms) */
2874         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2875
2876         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2877            cnt*delay, rc, seq);
2878
2879         /* is this a reply to our command? */
2880         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2881                 rc &= FW_MSG_CODE_MASK;
2882         else {
2883                 /* FW BUG! */
2884                 BNX2X_ERR("FW failed to respond!\n");
2885                 bnx2x_fw_dump(bp);
2886                 rc = 0;
2887         }
2888         mutex_unlock(&bp->fw_mb_mutex);
2889
2890         return rc;
2891 }
2892
2893
2894 static void storm_memset_func_cfg(struct bnx2x *bp,
2895                                  struct tstorm_eth_function_common_config *tcfg,
2896                                  u16 abs_fid)
2897 {
2898         size_t size = sizeof(struct tstorm_eth_function_common_config);
2899
2900         u32 addr = BAR_TSTRORM_INTMEM +
2901                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2902
2903         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2904 }
2905
2906 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2907 {
2908         if (CHIP_IS_E1x(bp)) {
2909                 struct tstorm_eth_function_common_config tcfg = {0};
2910
2911                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2912         }
2913
2914         /* Enable the function in the FW */
2915         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2916         storm_memset_func_en(bp, p->func_id, 1);
2917
2918         /* spq */
2919         if (p->func_flgs & FUNC_FLG_SPQ) {
2920                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2921                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2922                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2923         }
2924 }
2925
2926 /**
2927  * bnx2x_get_tx_only_flags - Return common flags
2928  *
2929  * @bp          device handle
2930  * @fp          queue handle
2931  * @zero_stats  TRUE if statistics zeroing is needed
2932  *
2933  * Return the flags that are common for the Tx-only and not normal connections.
2934  */
2935 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2936                                             struct bnx2x_fastpath *fp,
2937                                             bool zero_stats)
2938 {
2939         unsigned long flags = 0;
2940
2941         /* PF driver will always initialize the Queue to an ACTIVE state */
2942         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2943
2944         /* tx only connections collect statistics (on the same index as the
2945          *  parent connection). The statistics are zeroed when the parent
2946          *  connection is initialized.
2947          */
2948
2949         __set_bit(BNX2X_Q_FLG_STATS, &flags);
2950         if (zero_stats)
2951                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2952
2953
2954 #ifdef BNX2X_STOP_ON_ERROR
2955         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
2956 #endif
2957
2958         return flags;
2959 }
2960
2961 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2962                                        struct bnx2x_fastpath *fp,
2963                                        bool leading)
2964 {
2965         unsigned long flags = 0;
2966
2967         /* calculate other queue flags */
2968         if (IS_MF_SD(bp))
2969                 __set_bit(BNX2X_Q_FLG_OV, &flags);
2970
2971         if (IS_FCOE_FP(fp)) {
2972                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2973                 /* For FCoE - force usage of default priority (for afex) */
2974                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2975         }
2976
2977         if (!fp->disable_tpa) {
2978                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2979                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2980                 if (fp->mode == TPA_MODE_GRO)
2981                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2982         }
2983
2984         if (leading) {
2985                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2986                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2987         }
2988
2989         /* Always set HW VLAN stripping */
2990         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2991
2992         /* configure silent vlan removal */
2993         if (IS_MF_AFEX(bp))
2994                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2995
2996
2997         return flags | bnx2x_get_common_flags(bp, fp, true);
2998 }
2999
3000 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3001         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3002         u8 cos)
3003 {
3004         gen_init->stat_id = bnx2x_stats_id(fp);
3005         gen_init->spcl_id = fp->cl_id;
3006
3007         /* Always use mini-jumbo MTU for FCoE L2 ring */
3008         if (IS_FCOE_FP(fp))
3009                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3010         else
3011                 gen_init->mtu = bp->dev->mtu;
3012
3013         gen_init->cos = cos;
3014 }
3015
3016 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3017         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3018         struct bnx2x_rxq_setup_params *rxq_init)
3019 {
3020         u8 max_sge = 0;
3021         u16 sge_sz = 0;
3022         u16 tpa_agg_size = 0;
3023
3024         if (!fp->disable_tpa) {
3025                 pause->sge_th_lo = SGE_TH_LO(bp);
3026                 pause->sge_th_hi = SGE_TH_HI(bp);
3027
3028                 /* validate SGE ring has enough to cross high threshold */
3029                 WARN_ON(bp->dropless_fc &&
3030                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3031                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3032
3033                 tpa_agg_size = min_t(u32,
3034                         (min_t(u32, 8, MAX_SKB_FRAGS) *
3035                         SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
3036                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3037                         SGE_PAGE_SHIFT;
3038                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3039                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3040                 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
3041                                     0xffff);
3042         }
3043
3044         /* pause - not for e1 */
3045         if (!CHIP_IS_E1(bp)) {
3046                 pause->bd_th_lo = BD_TH_LO(bp);
3047                 pause->bd_th_hi = BD_TH_HI(bp);
3048
3049                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3050                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3051                 /*
3052                  * validate that rings have enough entries to cross
3053                  * high thresholds
3054                  */
3055                 WARN_ON(bp->dropless_fc &&
3056                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3057                                 bp->rx_ring_size);
3058                 WARN_ON(bp->dropless_fc &&
3059                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3060                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3061
3062                 pause->pri_map = 1;
3063         }
3064
3065         /* rxq setup */
3066         rxq_init->dscr_map = fp->rx_desc_mapping;
3067         rxq_init->sge_map = fp->rx_sge_mapping;
3068         rxq_init->rcq_map = fp->rx_comp_mapping;
3069         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3070
3071         /* This should be a maximum number of data bytes that may be
3072          * placed on the BD (not including paddings).
3073          */
3074         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3075                 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3076
3077         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3078         rxq_init->tpa_agg_sz = tpa_agg_size;
3079         rxq_init->sge_buf_sz = sge_sz;
3080         rxq_init->max_sges_pkt = max_sge;
3081         rxq_init->rss_engine_id = BP_FUNC(bp);
3082         rxq_init->mcast_engine_id = BP_FUNC(bp);
3083
3084         /* Maximum number or simultaneous TPA aggregation for this Queue.
3085          *
3086          * For PF Clients it should be the maximum avaliable number.
3087          * VF driver(s) may want to define it to a smaller value.
3088          */
3089         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3090
3091         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3092         rxq_init->fw_sb_id = fp->fw_sb_id;
3093
3094         if (IS_FCOE_FP(fp))
3095                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3096         else
3097                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3098         /* configure silent vlan removal
3099          * if multi function mode is afex, then mask default vlan
3100          */
3101         if (IS_MF_AFEX(bp)) {
3102                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3103                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3104         }
3105 }
3106
3107 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3108         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3109         u8 cos)
3110 {
3111         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3112         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3113         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3114         txq_init->fw_sb_id = fp->fw_sb_id;
3115
3116         /*
3117          * set the tss leading client id for TX classfication ==
3118          * leading RSS client id
3119          */
3120         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3121
3122         if (IS_FCOE_FP(fp)) {
3123                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3124                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3125         }
3126 }
3127
3128 static void bnx2x_pf_init(struct bnx2x *bp)
3129 {
3130         struct bnx2x_func_init_params func_init = {0};
3131         struct event_ring_data eq_data = { {0} };
3132         u16 flags;
3133
3134         if (!CHIP_IS_E1x(bp)) {
3135                 /* reset IGU PF statistics: MSIX + ATTN */
3136                 /* PF */
3137                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3138                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3139                            (CHIP_MODE_IS_4_PORT(bp) ?
3140                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3141                 /* ATTN */
3142                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3143                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3144                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3145                            (CHIP_MODE_IS_4_PORT(bp) ?
3146                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3147         }
3148
3149         /* function setup flags */
3150         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3151
3152         /* This flag is relevant for E1x only.
3153          * E2 doesn't have a TPA configuration in a function level.
3154          */
3155         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3156
3157         func_init.func_flgs = flags;
3158         func_init.pf_id = BP_FUNC(bp);
3159         func_init.func_id = BP_FUNC(bp);
3160         func_init.spq_map = bp->spq_mapping;
3161         func_init.spq_prod = bp->spq_prod_idx;
3162
3163         bnx2x_func_init(bp, &func_init);
3164
3165         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3166
3167         /*
3168          * Congestion management values depend on the link rate
3169          * There is no active link so initial link rate is set to 10 Gbps.
3170          * When the link comes up The congestion management values are
3171          * re-calculated according to the actual link rate.
3172          */
3173         bp->link_vars.line_speed = SPEED_10000;
3174         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3175
3176         /* Only the PMF sets the HW */
3177         if (bp->port.pmf)
3178                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3179
3180         /* init Event Queue */
3181         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3182         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3183         eq_data.producer = bp->eq_prod;
3184         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3185         eq_data.sb_id = DEF_SB_ID;
3186         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3187 }
3188
3189
3190 static void bnx2x_e1h_disable(struct bnx2x *bp)
3191 {
3192         int port = BP_PORT(bp);
3193
3194         bnx2x_tx_disable(bp);
3195
3196         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3197 }
3198
3199 static void bnx2x_e1h_enable(struct bnx2x *bp)
3200 {
3201         int port = BP_PORT(bp);
3202
3203         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3204
3205         /* Tx queue should be only reenabled */
3206         netif_tx_wake_all_queues(bp->dev);
3207
3208         /*
3209          * Should not call netif_carrier_on since it will be called if the link
3210          * is up when checking for link state
3211          */
3212 }
3213
3214 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3215
3216 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3217 {
3218         struct eth_stats_info *ether_stat =
3219                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3220
3221         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3222                 ETH_STAT_INFO_VERSION_LEN);
3223
3224         bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3225                                         DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3226                                         ether_stat->mac_local);
3227
3228         ether_stat->mtu_size = bp->dev->mtu;
3229
3230         if (bp->dev->features & NETIF_F_RXCSUM)
3231                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3232         if (bp->dev->features & NETIF_F_TSO)
3233                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3234         ether_stat->feature_flags |= bp->common.boot_mode;
3235
3236         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3237
3238         ether_stat->txq_size = bp->tx_ring_size;
3239         ether_stat->rxq_size = bp->rx_ring_size;
3240 }
3241
3242 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3243 {
3244         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3245         struct fcoe_stats_info *fcoe_stat =
3246                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3247
3248         if (!CNIC_LOADED(bp))
3249                 return;
3250
3251         memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3252                bp->fip_mac, ETH_ALEN);
3253
3254         fcoe_stat->qos_priority =
3255                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3256
3257         /* insert FCoE stats from ramrod response */
3258         if (!NO_FCOE(bp)) {
3259                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3260                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3261                         tstorm_queue_statistics;
3262
3263                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3264                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3265                         xstorm_queue_statistics;
3266
3267                 struct fcoe_statistics_params *fw_fcoe_stat =
3268                         &bp->fw_stats_data->fcoe;
3269
3270                 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3271                        fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3272
3273                 ADD_64(fcoe_stat->rx_bytes_hi,
3274                        fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3275                        fcoe_stat->rx_bytes_lo,
3276                        fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3277
3278                 ADD_64(fcoe_stat->rx_bytes_hi,
3279                        fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3280                        fcoe_stat->rx_bytes_lo,
3281                        fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3282
3283                 ADD_64(fcoe_stat->rx_bytes_hi,
3284                        fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3285                        fcoe_stat->rx_bytes_lo,
3286                        fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3287
3288                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3289                        fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3290
3291                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3292                        fcoe_q_tstorm_stats->rcv_ucast_pkts);
3293
3294                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3295                        fcoe_q_tstorm_stats->rcv_bcast_pkts);
3296
3297                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3298                        fcoe_q_tstorm_stats->rcv_mcast_pkts);
3299
3300                 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3301                        fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3302
3303                 ADD_64(fcoe_stat->tx_bytes_hi,
3304                        fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3305                        fcoe_stat->tx_bytes_lo,
3306                        fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3307
3308                 ADD_64(fcoe_stat->tx_bytes_hi,
3309                        fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3310                        fcoe_stat->tx_bytes_lo,
3311                        fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3312
3313                 ADD_64(fcoe_stat->tx_bytes_hi,
3314                        fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3315                        fcoe_stat->tx_bytes_lo,
3316                        fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3317
3318                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3319                        fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3320
3321                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3322                        fcoe_q_xstorm_stats->ucast_pkts_sent);
3323
3324                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3325                        fcoe_q_xstorm_stats->bcast_pkts_sent);
3326
3327                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3328                        fcoe_q_xstorm_stats->mcast_pkts_sent);
3329         }
3330
3331         /* ask L5 driver to add data to the struct */
3332         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3333 }
3334
3335 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3336 {
3337         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3338         struct iscsi_stats_info *iscsi_stat =
3339                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3340
3341         if (!CNIC_LOADED(bp))
3342                 return;
3343
3344         memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3345                bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3346
3347         iscsi_stat->qos_priority =
3348                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3349
3350         /* ask L5 driver to add data to the struct */
3351         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3352 }
3353
3354 /* called due to MCP event (on pmf):
3355  *      reread new bandwidth configuration
3356  *      configure FW
3357  *      notify others function about the change
3358  */
3359 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3360 {
3361         if (bp->link_vars.link_up) {
3362                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3363                 bnx2x_link_sync_notify(bp);
3364         }
3365         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3366 }
3367
3368 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3369 {
3370         bnx2x_config_mf_bw(bp);
3371         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3372 }
3373
3374 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3375 {
3376         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3377         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3378 }
3379
3380 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3381 {
3382         enum drv_info_opcode op_code;
3383         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3384
3385         /* if drv_info version supported by MFW doesn't match - send NACK */
3386         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3387                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3388                 return;
3389         }
3390
3391         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3392                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3393
3394         memset(&bp->slowpath->drv_info_to_mcp, 0,
3395                sizeof(union drv_info_to_mcp));
3396
3397         switch (op_code) {
3398         case ETH_STATS_OPCODE:
3399                 bnx2x_drv_info_ether_stat(bp);
3400                 break;
3401         case FCOE_STATS_OPCODE:
3402                 bnx2x_drv_info_fcoe_stat(bp);
3403                 break;
3404         case ISCSI_STATS_OPCODE:
3405                 bnx2x_drv_info_iscsi_stat(bp);
3406                 break;
3407         default:
3408                 /* if op code isn't supported - send NACK */
3409                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3410                 return;
3411         }
3412
3413         /* if we got drv_info attn from MFW then these fields are defined in
3414          * shmem2 for sure
3415          */
3416         SHMEM2_WR(bp, drv_info_host_addr_lo,
3417                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3418         SHMEM2_WR(bp, drv_info_host_addr_hi,
3419                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3420
3421         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3422 }
3423
3424 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3425 {
3426         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3427
3428         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3429
3430                 /*
3431                  * This is the only place besides the function initialization
3432                  * where the bp->flags can change so it is done without any
3433                  * locks
3434                  */
3435                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3436                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3437                         bp->flags |= MF_FUNC_DIS;
3438
3439                         bnx2x_e1h_disable(bp);
3440                 } else {
3441                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3442                         bp->flags &= ~MF_FUNC_DIS;
3443
3444                         bnx2x_e1h_enable(bp);
3445                 }
3446                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3447         }
3448         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3449                 bnx2x_config_mf_bw(bp);
3450                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3451         }
3452
3453         /* Report results to MCP */
3454         if (dcc_event)
3455                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3456         else
3457                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3458 }
3459
3460 /* must be called under the spq lock */
3461 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3462 {
3463         struct eth_spe *next_spe = bp->spq_prod_bd;
3464
3465         if (bp->spq_prod_bd == bp->spq_last_bd) {
3466                 bp->spq_prod_bd = bp->spq;
3467                 bp->spq_prod_idx = 0;
3468                 DP(BNX2X_MSG_SP, "end of spq\n");
3469         } else {
3470                 bp->spq_prod_bd++;
3471                 bp->spq_prod_idx++;
3472         }
3473         return next_spe;
3474 }
3475
3476 /* must be called under the spq lock */
3477 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3478 {
3479         int func = BP_FUNC(bp);
3480
3481         /*
3482          * Make sure that BD data is updated before writing the producer:
3483          * BD data is written to the memory, the producer is read from the
3484          * memory, thus we need a full memory barrier to ensure the ordering.
3485          */
3486         mb();
3487
3488         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3489                  bp->spq_prod_idx);
3490         mmiowb();
3491 }
3492
3493 /**
3494  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3495  *
3496  * @cmd:        command to check
3497  * @cmd_type:   command type
3498  */
3499 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3500 {
3501         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3502             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3503             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3504             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3505             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3506             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3507             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3508                 return true;
3509         else
3510                 return false;
3511
3512 }
3513
3514
3515 /**
3516  * bnx2x_sp_post - place a single command on an SP ring
3517  *
3518  * @bp:         driver handle
3519  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3520  * @cid:        SW CID the command is related to
3521  * @data_hi:    command private data address (high 32 bits)
3522  * @data_lo:    command private data address (low 32 bits)
3523  * @cmd_type:   command type (e.g. NONE, ETH)
3524  *
3525  * SP data is handled as if it's always an address pair, thus data fields are
3526  * not swapped to little endian in upper functions. Instead this function swaps
3527  * data as if it's two u32 fields.
3528  */
3529 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3530                   u32 data_hi, u32 data_lo, int cmd_type)
3531 {
3532         struct eth_spe *spe;
3533         u16 type;
3534         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3535
3536 #ifdef BNX2X_STOP_ON_ERROR
3537         if (unlikely(bp->panic)) {
3538                 BNX2X_ERR("Can't post SP when there is panic\n");
3539                 return -EIO;
3540         }
3541 #endif
3542
3543         spin_lock_bh(&bp->spq_lock);
3544
3545         if (common) {
3546                 if (!atomic_read(&bp->eq_spq_left)) {
3547                         BNX2X_ERR("BUG! EQ ring full!\n");
3548                         spin_unlock_bh(&bp->spq_lock);
3549                         bnx2x_panic();
3550                         return -EBUSY;
3551                 }
3552         } else if (!atomic_read(&bp->cq_spq_left)) {
3553                         BNX2X_ERR("BUG! SPQ ring full!\n");
3554                         spin_unlock_bh(&bp->spq_lock);
3555                         bnx2x_panic();
3556                         return -EBUSY;
3557         }
3558
3559         spe = bnx2x_sp_get_next(bp);
3560
3561         /* CID needs port number to be encoded int it */
3562         spe->hdr.conn_and_cmd_data =
3563                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3564                                     HW_CID(bp, cid));
3565
3566         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3567
3568         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3569                  SPE_HDR_FUNCTION_ID);
3570
3571         spe->hdr.type = cpu_to_le16(type);
3572
3573         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3574         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3575
3576         /*
3577          * It's ok if the actual decrement is issued towards the memory
3578          * somewhere between the spin_lock and spin_unlock. Thus no
3579          * more explict memory barrier is needed.
3580          */
3581         if (common)
3582                 atomic_dec(&bp->eq_spq_left);
3583         else
3584                 atomic_dec(&bp->cq_spq_left);
3585
3586
3587         DP(BNX2X_MSG_SP,
3588            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3589            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3590            (u32)(U64_LO(bp->spq_mapping) +
3591            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3592            HW_CID(bp, cid), data_hi, data_lo, type,
3593            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3594
3595         bnx2x_sp_prod_update(bp);
3596         spin_unlock_bh(&bp->spq_lock);
3597         return 0;
3598 }
3599
3600 /* acquire split MCP access lock register */
3601 static int bnx2x_acquire_alr(struct bnx2x *bp)
3602 {
3603         u32 j, val;
3604         int rc = 0;
3605
3606         might_sleep();
3607         for (j = 0; j < 1000; j++) {
3608                 val = (1UL << 31);
3609                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3610                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3611                 if (val & (1L << 31))
3612                         break;
3613
3614                 msleep(5);
3615         }
3616         if (!(val & (1L << 31))) {
3617                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3618                 rc = -EBUSY;
3619         }
3620
3621         return rc;
3622 }
3623
3624 /* release split MCP access lock register */
3625 static void bnx2x_release_alr(struct bnx2x *bp)
3626 {
3627         REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3628 }
3629
3630 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3631 #define BNX2X_DEF_SB_IDX        0x0002
3632
3633 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3634 {
3635         struct host_sp_status_block *def_sb = bp->def_status_blk;
3636         u16 rc = 0;
3637
3638         barrier(); /* status block is written to by the chip */
3639         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3640                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3641                 rc |= BNX2X_DEF_SB_ATT_IDX;
3642         }
3643
3644         if (bp->def_idx != def_sb->sp_sb.running_index) {
3645                 bp->def_idx = def_sb->sp_sb.running_index;
3646                 rc |= BNX2X_DEF_SB_IDX;
3647         }
3648
3649         /* Do not reorder: indecies reading should complete before handling */
3650         barrier();
3651         return rc;
3652 }
3653
3654 /*
3655  * slow path service functions
3656  */
3657
3658 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3659 {
3660         int port = BP_PORT(bp);
3661         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3662                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3663         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3664                                        NIG_REG_MASK_INTERRUPT_PORT0;
3665         u32 aeu_mask;
3666         u32 nig_mask = 0;
3667         u32 reg_addr;
3668
3669         if (bp->attn_state & asserted)
3670                 BNX2X_ERR("IGU ERROR\n");
3671
3672         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3673         aeu_mask = REG_RD(bp, aeu_addr);
3674
3675         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3676            aeu_mask, asserted);
3677         aeu_mask &= ~(asserted & 0x3ff);
3678         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3679
3680         REG_WR(bp, aeu_addr, aeu_mask);
3681         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3682
3683         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3684         bp->attn_state |= asserted;
3685         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3686
3687         if (asserted & ATTN_HARD_WIRED_MASK) {
3688                 if (asserted & ATTN_NIG_FOR_FUNC) {
3689
3690                         bnx2x_acquire_phy_lock(bp);
3691
3692                         /* save nig interrupt mask */
3693                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3694
3695                         /* If nig_mask is not set, no need to call the update
3696                          * function.
3697                          */
3698                         if (nig_mask) {
3699                                 REG_WR(bp, nig_int_mask_addr, 0);
3700
3701                                 bnx2x_link_attn(bp);
3702                         }
3703
3704                         /* handle unicore attn? */
3705                 }
3706                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3707                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3708
3709                 if (asserted & GPIO_2_FUNC)
3710                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3711
3712                 if (asserted & GPIO_3_FUNC)
3713                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3714
3715                 if (asserted & GPIO_4_FUNC)
3716                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3717
3718                 if (port == 0) {
3719                         if (asserted & ATTN_GENERAL_ATTN_1) {
3720                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3721                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3722                         }
3723                         if (asserted & ATTN_GENERAL_ATTN_2) {
3724                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3725                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3726                         }
3727                         if (asserted & ATTN_GENERAL_ATTN_3) {
3728                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3729                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3730                         }
3731                 } else {
3732                         if (asserted & ATTN_GENERAL_ATTN_4) {
3733                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3734                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3735                         }
3736                         if (asserted & ATTN_GENERAL_ATTN_5) {
3737                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3738                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3739                         }
3740                         if (asserted & ATTN_GENERAL_ATTN_6) {
3741                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3742                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3743                         }
3744                 }
3745
3746         } /* if hardwired */
3747
3748         if (bp->common.int_block == INT_BLOCK_HC)
3749                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3750                             COMMAND_REG_ATTN_BITS_SET);
3751         else
3752                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3753
3754         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3755            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3756         REG_WR(bp, reg_addr, asserted);
3757
3758         /* now set back the mask */
3759         if (asserted & ATTN_NIG_FOR_FUNC) {
3760                 /* Verify that IGU ack through BAR was written before restoring
3761                  * NIG mask. This loop should exit after 2-3 iterations max.
3762                  */
3763                 if (bp->common.int_block != INT_BLOCK_HC) {
3764                         u32 cnt = 0, igu_acked;
3765                         do {
3766                                 igu_acked = REG_RD(bp,
3767                                                    IGU_REG_ATTENTION_ACK_BITS);
3768                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3769                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3770                         if (!igu_acked)
3771                                 DP(NETIF_MSG_HW,
3772                                    "Failed to verify IGU ack on time\n");
3773                         barrier();
3774                 }
3775                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3776                 bnx2x_release_phy_lock(bp);
3777         }
3778 }
3779
3780 static void bnx2x_fan_failure(struct bnx2x *bp)
3781 {
3782         int port = BP_PORT(bp);
3783         u32 ext_phy_config;
3784         /* mark the failure */
3785         ext_phy_config =
3786                 SHMEM_RD(bp,
3787                          dev_info.port_hw_config[port].external_phy_config);
3788
3789         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3790         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3791         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3792                  ext_phy_config);
3793
3794         /* log the failure */
3795         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3796                             "Please contact OEM Support for assistance\n");
3797
3798         /*
3799          * Scheudle device reset (unload)
3800          * This is due to some boards consuming sufficient power when driver is
3801          * up to overheat if fan fails.
3802          */
3803         smp_mb__before_clear_bit();
3804         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3805         smp_mb__after_clear_bit();
3806         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3807
3808 }
3809
3810 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3811 {
3812         int port = BP_PORT(bp);
3813         int reg_offset;
3814         u32 val;
3815
3816         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3817                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3818
3819         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3820
3821                 val = REG_RD(bp, reg_offset);
3822                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3823                 REG_WR(bp, reg_offset, val);
3824
3825                 BNX2X_ERR("SPIO5 hw attention\n");
3826
3827                 /* Fan failure attention */
3828                 bnx2x_hw_reset_phy(&bp->link_params);
3829                 bnx2x_fan_failure(bp);
3830         }
3831
3832         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3833                 bnx2x_acquire_phy_lock(bp);
3834                 bnx2x_handle_module_detect_int(&bp->link_params);
3835                 bnx2x_release_phy_lock(bp);
3836         }
3837
3838         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3839
3840                 val = REG_RD(bp, reg_offset);
3841                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3842                 REG_WR(bp, reg_offset, val);
3843
3844                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3845                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3846                 bnx2x_panic();
3847         }
3848 }
3849
3850 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3851 {
3852         u32 val;
3853
3854         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3855
3856                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3857                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3858                 /* DORQ discard attention */
3859                 if (val & 0x2)
3860                         BNX2X_ERR("FATAL error from DORQ\n");
3861         }
3862
3863         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3864
3865                 int port = BP_PORT(bp);
3866                 int reg_offset;
3867
3868                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3869                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3870
3871                 val = REG_RD(bp, reg_offset);
3872                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3873                 REG_WR(bp, reg_offset, val);
3874
3875                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3876                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3877                 bnx2x_panic();
3878         }
3879 }
3880
3881 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3882 {
3883         u32 val;
3884
3885         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3886
3887                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3888                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3889                 /* CFC error attention */
3890                 if (val & 0x2)
3891                         BNX2X_ERR("FATAL error from CFC\n");
3892         }
3893
3894         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3895                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3896                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3897                 /* RQ_USDMDP_FIFO_OVERFLOW */
3898                 if (val & 0x18000)
3899                         BNX2X_ERR("FATAL error from PXP\n");
3900
3901                 if (!CHIP_IS_E1x(bp)) {
3902                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3903                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3904                 }
3905         }
3906
3907         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3908
3909                 int port = BP_PORT(bp);
3910                 int reg_offset;
3911
3912                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3913                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3914
3915                 val = REG_RD(bp, reg_offset);
3916                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3917                 REG_WR(bp, reg_offset, val);
3918
3919                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3920                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3921                 bnx2x_panic();
3922         }
3923 }
3924
3925 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3926 {
3927         u32 val;
3928
3929         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3930
3931                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3932                         int func = BP_FUNC(bp);
3933
3934                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3935                         bnx2x_read_mf_cfg(bp);
3936                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3937                                         func_mf_config[BP_ABS_FUNC(bp)].config);
3938                         val = SHMEM_RD(bp,
3939                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
3940                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3941                                 bnx2x_dcc_event(bp,
3942                                             (val & DRV_STATUS_DCC_EVENT_MASK));
3943
3944                         if (val & DRV_STATUS_SET_MF_BW)
3945                                 bnx2x_set_mf_bw(bp);
3946
3947                         if (val & DRV_STATUS_DRV_INFO_REQ)
3948                                 bnx2x_handle_drv_info_req(bp);
3949
3950                         if (val & DRV_STATUS_VF_DISABLED)
3951                                 bnx2x_vf_handle_flr_event(bp);
3952
3953                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3954                                 bnx2x_pmf_update(bp);
3955
3956                         if (bp->port.pmf &&
3957                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3958                                 bp->dcbx_enabled > 0)
3959                                 /* start dcbx state machine */
3960                                 bnx2x_dcbx_set_params(bp,
3961                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
3962                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
3963                                 bnx2x_handle_afex_cmd(bp,
3964                                         val & DRV_STATUS_AFEX_EVENT_MASK);
3965                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3966                                 bnx2x_handle_eee_event(bp);
3967                         if (bp->link_vars.periodic_flags &
3968                             PERIODIC_FLAGS_LINK_EVENT) {
3969                                 /*  sync with link */
3970                                 bnx2x_acquire_phy_lock(bp);
3971                                 bp->link_vars.periodic_flags &=
3972                                         ~PERIODIC_FLAGS_LINK_EVENT;
3973                                 bnx2x_release_phy_lock(bp);
3974                                 if (IS_MF(bp))
3975                                         bnx2x_link_sync_notify(bp);
3976                                 bnx2x_link_report(bp);
3977                         }
3978                         /* Always call it here: bnx2x_link_report() will
3979                          * prevent the link indication duplication.
3980                          */
3981                         bnx2x__link_status_update(bp);
3982                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3983
3984                         BNX2X_ERR("MC assert!\n");
3985                         bnx2x_mc_assert(bp);
3986                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3987                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3988                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3989                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3990                         bnx2x_panic();
3991
3992                 } else if (attn & BNX2X_MCP_ASSERT) {
3993
3994                         BNX2X_ERR("MCP assert!\n");
3995                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3996                         bnx2x_fw_dump(bp);
3997
3998                 } else
3999                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4000         }
4001
4002         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4003                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4004                 if (attn & BNX2X_GRC_TIMEOUT) {
4005                         val = CHIP_IS_E1(bp) ? 0 :
4006                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4007                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4008                 }
4009                 if (attn & BNX2X_GRC_RSV) {
4010                         val = CHIP_IS_E1(bp) ? 0 :
4011                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4012                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4013                 }
4014                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4015         }
4016 }
4017
4018 /*
4019  * Bits map:
4020  * 0-7   - Engine0 load counter.
4021  * 8-15  - Engine1 load counter.
4022  * 16    - Engine0 RESET_IN_PROGRESS bit.
4023  * 17    - Engine1 RESET_IN_PROGRESS bit.
4024  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4025  *         on the engine
4026  * 19    - Engine1 ONE_IS_LOADED.
4027  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4028  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4029  *         just the one belonging to its engine).
4030  *
4031  */
4032 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4033
4034 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4035 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4036 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4037 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4038 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4039 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4040 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4041
4042 /*
4043  * Set the GLOBAL_RESET bit.
4044  *
4045  * Should be run under rtnl lock
4046  */
4047 void bnx2x_set_reset_global(struct bnx2x *bp)
4048 {
4049         u32 val;
4050         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4051         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4052         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4053         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4054 }
4055
4056 /*
4057  * Clear the GLOBAL_RESET bit.
4058  *
4059  * Should be run under rtnl lock
4060  */
4061 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4062 {
4063         u32 val;
4064         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4065         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4066         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4067         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4068 }
4069
4070 /*
4071  * Checks the GLOBAL_RESET bit.
4072  *
4073  * should be run under rtnl lock
4074  */
4075 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4076 {
4077         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4078
4079         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4080         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4081 }
4082
4083 /*
4084  * Clear RESET_IN_PROGRESS bit for the current engine.
4085  *
4086  * Should be run under rtnl lock
4087  */
4088 static void bnx2x_set_reset_done(struct bnx2x *bp)
4089 {
4090         u32 val;
4091         u32 bit = BP_PATH(bp) ?
4092                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4093         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4094         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4095
4096         /* Clear the bit */
4097         val &= ~bit;
4098         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4099
4100         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4101 }
4102
4103 /*
4104  * Set RESET_IN_PROGRESS for the current engine.
4105  *
4106  * should be run under rtnl lock
4107  */
4108 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4109 {
4110         u32 val;
4111         u32 bit = BP_PATH(bp) ?
4112                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4113         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4114         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4115
4116         /* Set the bit */
4117         val |= bit;
4118         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4119         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4120 }
4121
4122 /*
4123  * Checks the RESET_IN_PROGRESS bit for the given engine.
4124  * should be run under rtnl lock
4125  */
4126 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4127 {
4128         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4129         u32 bit = engine ?
4130                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4131
4132         /* return false if bit is set */
4133         return (val & bit) ? false : true;
4134 }
4135
4136 /*
4137  * set pf load for the current pf.
4138  *
4139  * should be run under rtnl lock
4140  */
4141 void bnx2x_set_pf_load(struct bnx2x *bp)
4142 {
4143         u32 val1, val;
4144         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4145                              BNX2X_PATH0_LOAD_CNT_MASK;
4146         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4147                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4148
4149         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4150         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4151
4152         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4153
4154         /* get the current counter value */
4155         val1 = (val & mask) >> shift;
4156
4157         /* set bit of that PF */
4158         val1 |= (1 << bp->pf_num);
4159
4160         /* clear the old value */
4161         val &= ~mask;
4162
4163         /* set the new one */
4164         val |= ((val1 << shift) & mask);
4165
4166         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4167         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4168 }
4169
4170 /**
4171  * bnx2x_clear_pf_load - clear pf load mark
4172  *
4173  * @bp:         driver handle
4174  *
4175  * Should be run under rtnl lock.
4176  * Decrements the load counter for the current engine. Returns
4177  * whether other functions are still loaded
4178  */
4179 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4180 {
4181         u32 val1, val;
4182         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4183                              BNX2X_PATH0_LOAD_CNT_MASK;
4184         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4185                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4186
4187         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4188         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4189         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4190
4191         /* get the current counter value */
4192         val1 = (val & mask) >> shift;
4193
4194         /* clear bit of that PF */
4195         val1 &= ~(1 << bp->pf_num);
4196
4197         /* clear the old value */
4198         val &= ~mask;
4199
4200         /* set the new one */
4201         val |= ((val1 << shift) & mask);
4202
4203         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4204         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4205         return val1 != 0;
4206 }
4207
4208 /*
4209  * Read the load status for the current engine.
4210  *
4211  * should be run under rtnl lock
4212  */
4213 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4214 {
4215         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4216                              BNX2X_PATH0_LOAD_CNT_MASK);
4217         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4218                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4219         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4220
4221         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4222
4223         val = (val & mask) >> shift;
4224
4225         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4226            engine, val);
4227
4228         return val != 0;
4229 }
4230
4231 static void _print_next_block(int idx, const char *blk)
4232 {
4233         pr_cont("%s%s", idx ? ", " : "", blk);
4234 }
4235
4236 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4237                                            bool print)
4238 {
4239         int i = 0;
4240         u32 cur_bit = 0;
4241         for (i = 0; sig; i++) {
4242                 cur_bit = ((u32)0x1 << i);
4243                 if (sig & cur_bit) {
4244                         switch (cur_bit) {
4245                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4246                                 if (print)
4247                                         _print_next_block(par_num++, "BRB");
4248                                 break;
4249                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4250                                 if (print)
4251                                         _print_next_block(par_num++, "PARSER");
4252                                 break;
4253                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4254                                 if (print)
4255                                         _print_next_block(par_num++, "TSDM");
4256                                 break;
4257                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4258                                 if (print)
4259                                         _print_next_block(par_num++,
4260                                                           "SEARCHER");
4261                                 break;
4262                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4263                                 if (print)
4264                                         _print_next_block(par_num++, "TCM");
4265                                 break;
4266                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4267                                 if (print)
4268                                         _print_next_block(par_num++, "TSEMI");
4269                                 break;
4270                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4271                                 if (print)
4272                                         _print_next_block(par_num++, "XPB");
4273                                 break;
4274                         }
4275
4276                         /* Clear the bit */
4277                         sig &= ~cur_bit;
4278                 }
4279         }
4280
4281         return par_num;
4282 }
4283
4284 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4285                                            bool *global, bool print)
4286 {
4287         int i = 0;
4288         u32 cur_bit = 0;
4289         for (i = 0; sig; i++) {
4290                 cur_bit = ((u32)0x1 << i);
4291                 if (sig & cur_bit) {
4292                         switch (cur_bit) {
4293                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4294                                 if (print)
4295                                         _print_next_block(par_num++, "PBF");
4296                                 break;
4297                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4298                                 if (print)
4299                                         _print_next_block(par_num++, "QM");
4300                                 break;
4301                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4302                                 if (print)
4303                                         _print_next_block(par_num++, "TM");
4304                                 break;
4305                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4306                                 if (print)
4307                                         _print_next_block(par_num++, "XSDM");
4308                                 break;
4309                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4310                                 if (print)
4311                                         _print_next_block(par_num++, "XCM");
4312                                 break;
4313                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4314                                 if (print)
4315                                         _print_next_block(par_num++, "XSEMI");
4316                                 break;
4317                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4318                                 if (print)
4319                                         _print_next_block(par_num++,
4320                                                           "DOORBELLQ");
4321                                 break;
4322                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4323                                 if (print)
4324                                         _print_next_block(par_num++, "NIG");
4325                                 break;
4326                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4327                                 if (print)
4328                                         _print_next_block(par_num++,
4329                                                           "VAUX PCI CORE");
4330                                 *global = true;
4331                                 break;
4332                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4333                                 if (print)
4334                                         _print_next_block(par_num++, "DEBUG");
4335                                 break;
4336                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4337                                 if (print)
4338                                         _print_next_block(par_num++, "USDM");
4339                                 break;
4340                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4341                                 if (print)
4342                                         _print_next_block(par_num++, "UCM");
4343                                 break;
4344                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4345                                 if (print)
4346                                         _print_next_block(par_num++, "USEMI");
4347                                 break;
4348                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4349                                 if (print)
4350                                         _print_next_block(par_num++, "UPB");
4351                                 break;
4352                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4353                                 if (print)
4354                                         _print_next_block(par_num++, "CSDM");
4355                                 break;
4356                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4357                                 if (print)
4358                                         _print_next_block(par_num++, "CCM");
4359                                 break;
4360                         }
4361
4362                         /* Clear the bit */
4363                         sig &= ~cur_bit;
4364                 }
4365         }
4366
4367         return par_num;
4368 }
4369
4370 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4371                                            bool print)
4372 {
4373         int i = 0;
4374         u32 cur_bit = 0;
4375         for (i = 0; sig; i++) {
4376                 cur_bit = ((u32)0x1 << i);
4377                 if (sig & cur_bit) {
4378                         switch (cur_bit) {
4379                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4380                                 if (print)
4381                                         _print_next_block(par_num++, "CSEMI");
4382                                 break;
4383                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4384                                 if (print)
4385                                         _print_next_block(par_num++, "PXP");
4386                                 break;
4387                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4388                                 if (print)
4389                                         _print_next_block(par_num++,
4390                                         "PXPPCICLOCKCLIENT");
4391                                 break;
4392                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4393                                 if (print)
4394                                         _print_next_block(par_num++, "CFC");
4395                                 break;
4396                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4397                                 if (print)
4398                                         _print_next_block(par_num++, "CDU");
4399                                 break;
4400                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4401                                 if (print)
4402                                         _print_next_block(par_num++, "DMAE");
4403                                 break;
4404                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4405                                 if (print)
4406                                         _print_next_block(par_num++, "IGU");
4407                                 break;
4408                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4409                                 if (print)
4410                                         _print_next_block(par_num++, "MISC");
4411                                 break;
4412                         }
4413
4414                         /* Clear the bit */
4415                         sig &= ~cur_bit;
4416                 }
4417         }
4418
4419         return par_num;
4420 }
4421
4422 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4423                                            bool *global, bool print)
4424 {
4425         int i = 0;
4426         u32 cur_bit = 0;
4427         for (i = 0; sig; i++) {
4428                 cur_bit = ((u32)0x1 << i);
4429                 if (sig & cur_bit) {
4430                         switch (cur_bit) {
4431                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4432                                 if (print)
4433                                         _print_next_block(par_num++, "MCP ROM");
4434                                 *global = true;
4435                                 break;
4436                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4437                                 if (print)
4438                                         _print_next_block(par_num++,
4439                                                           "MCP UMP RX");
4440                                 *global = true;
4441                                 break;
4442                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4443                                 if (print)
4444                                         _print_next_block(par_num++,
4445                                                           "MCP UMP TX");
4446                                 *global = true;
4447                                 break;
4448                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4449                                 if (print)
4450                                         _print_next_block(par_num++,
4451                                                           "MCP SCPAD");
4452                                 *global = true;
4453                                 break;
4454                         }
4455
4456                         /* Clear the bit */
4457                         sig &= ~cur_bit;
4458                 }
4459         }
4460
4461         return par_num;
4462 }
4463
4464 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4465                                            bool print)
4466 {
4467         int i = 0;
4468         u32 cur_bit = 0;
4469         for (i = 0; sig; i++) {
4470                 cur_bit = ((u32)0x1 << i);
4471                 if (sig & cur_bit) {
4472                         switch (cur_bit) {
4473                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4474                                 if (print)
4475                                         _print_next_block(par_num++, "PGLUE_B");
4476                                 break;
4477                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4478                                 if (print)
4479                                         _print_next_block(par_num++, "ATC");
4480                                 break;
4481                         }
4482
4483                         /* Clear the bit */
4484                         sig &= ~cur_bit;
4485                 }
4486         }
4487
4488         return par_num;
4489 }
4490
4491 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4492                               u32 *sig)
4493 {
4494         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4495             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4496             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4497             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4498             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4499                 int par_num = 0;
4500                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4501                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4502                           sig[0] & HW_PRTY_ASSERT_SET_0,
4503                           sig[1] & HW_PRTY_ASSERT_SET_1,
4504                           sig[2] & HW_PRTY_ASSERT_SET_2,
4505                           sig[3] & HW_PRTY_ASSERT_SET_3,
4506                           sig[4] & HW_PRTY_ASSERT_SET_4);
4507                 if (print)
4508                         netdev_err(bp->dev,
4509                                    "Parity errors detected in blocks: ");
4510                 par_num = bnx2x_check_blocks_with_parity0(
4511                         sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4512                 par_num = bnx2x_check_blocks_with_parity1(
4513                         sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4514                 par_num = bnx2x_check_blocks_with_parity2(
4515                         sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4516                 par_num = bnx2x_check_blocks_with_parity3(
4517                         sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4518                 par_num = bnx2x_check_blocks_with_parity4(
4519                         sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4520
4521                 if (print)
4522                         pr_cont("\n");
4523
4524                 return true;
4525         } else
4526                 return false;
4527 }
4528
4529 /**
4530  * bnx2x_chk_parity_attn - checks for parity attentions.
4531  *
4532  * @bp:         driver handle
4533  * @global:     true if there was a global attention
4534  * @print:      show parity attention in syslog
4535  */
4536 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4537 {
4538         struct attn_route attn = { {0} };
4539         int port = BP_PORT(bp);
4540
4541         attn.sig[0] = REG_RD(bp,
4542                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4543                              port*4);
4544         attn.sig[1] = REG_RD(bp,
4545                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4546                              port*4);
4547         attn.sig[2] = REG_RD(bp,
4548                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4549                              port*4);
4550         attn.sig[3] = REG_RD(bp,
4551                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4552                              port*4);
4553
4554         if (!CHIP_IS_E1x(bp))
4555                 attn.sig[4] = REG_RD(bp,
4556                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4557                                      port*4);
4558
4559         return bnx2x_parity_attn(bp, global, print, attn.sig);
4560 }
4561
4562
4563 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4564 {
4565         u32 val;
4566         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4567
4568                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4569                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4570                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4571                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4572                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4573                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4574                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4575                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4576                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4577                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4578                 if (val &
4579                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4580                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4581                 if (val &
4582                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4583                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4584                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4585                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4586                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4587                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4588                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4589                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4590         }
4591         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4592                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4593                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4594                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4595                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4596                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4597                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4598                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4599                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4600                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4601                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4602                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4603                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4604                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4605                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4606         }
4607
4608         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4609                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4610                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4611                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4612                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4613         }
4614
4615 }
4616
4617 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4618 {
4619         struct attn_route attn, *group_mask;
4620         int port = BP_PORT(bp);
4621         int index;
4622         u32 reg_addr;
4623         u32 val;
4624         u32 aeu_mask;
4625         bool global = false;
4626
4627         /* need to take HW lock because MCP or other port might also
4628            try to handle this event */
4629         bnx2x_acquire_alr(bp);
4630
4631         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4632 #ifndef BNX2X_STOP_ON_ERROR
4633                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4634                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4635                 /* Disable HW interrupts */
4636                 bnx2x_int_disable(bp);
4637                 /* In case of parity errors don't handle attentions so that
4638                  * other function would "see" parity errors.
4639                  */
4640 #else
4641                 bnx2x_panic();
4642 #endif
4643                 bnx2x_release_alr(bp);
4644                 return;
4645         }
4646
4647         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4648         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4649         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4650         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4651         if (!CHIP_IS_E1x(bp))
4652                 attn.sig[4] =
4653                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4654         else
4655                 attn.sig[4] = 0;
4656
4657         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4658            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4659
4660         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4661                 if (deasserted & (1 << index)) {
4662                         group_mask = &bp->attn_group[index];
4663
4664                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4665                            index,
4666                            group_mask->sig[0], group_mask->sig[1],
4667                            group_mask->sig[2], group_mask->sig[3],
4668                            group_mask->sig[4]);
4669
4670                         bnx2x_attn_int_deasserted4(bp,
4671                                         attn.sig[4] & group_mask->sig[4]);
4672                         bnx2x_attn_int_deasserted3(bp,
4673                                         attn.sig[3] & group_mask->sig[3]);
4674                         bnx2x_attn_int_deasserted1(bp,
4675                                         attn.sig[1] & group_mask->sig[1]);
4676                         bnx2x_attn_int_deasserted2(bp,
4677                                         attn.sig[2] & group_mask->sig[2]);
4678                         bnx2x_attn_int_deasserted0(bp,
4679                                         attn.sig[0] & group_mask->sig[0]);
4680                 }
4681         }
4682
4683         bnx2x_release_alr(bp);
4684
4685         if (bp->common.int_block == INT_BLOCK_HC)
4686                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4687                             COMMAND_REG_ATTN_BITS_CLR);
4688         else
4689                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4690
4691         val = ~deasserted;
4692         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4693            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4694         REG_WR(bp, reg_addr, val);
4695
4696         if (~bp->attn_state & deasserted)
4697                 BNX2X_ERR("IGU ERROR\n");
4698
4699         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4700                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4701
4702         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4703         aeu_mask = REG_RD(bp, reg_addr);
4704
4705         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4706            aeu_mask, deasserted);
4707         aeu_mask |= (deasserted & 0x3ff);
4708         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4709
4710         REG_WR(bp, reg_addr, aeu_mask);
4711         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4712
4713         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4714         bp->attn_state &= ~deasserted;
4715         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4716 }
4717
4718 static void bnx2x_attn_int(struct bnx2x *bp)
4719 {
4720         /* read local copy of bits */
4721         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4722                                                                 attn_bits);
4723         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4724                                                                 attn_bits_ack);
4725         u32 attn_state = bp->attn_state;
4726
4727         /* look for changed bits */
4728         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4729         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4730
4731         DP(NETIF_MSG_HW,
4732            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4733            attn_bits, attn_ack, asserted, deasserted);
4734
4735         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4736                 BNX2X_ERR("BAD attention state\n");
4737
4738         /* handle bits that were raised */
4739         if (asserted)
4740                 bnx2x_attn_int_asserted(bp, asserted);
4741
4742         if (deasserted)
4743                 bnx2x_attn_int_deasserted(bp, deasserted);
4744 }
4745
4746 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4747                       u16 index, u8 op, u8 update)
4748 {
4749         u32 igu_addr = bp->igu_base_addr;
4750         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4751         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4752                              igu_addr);
4753 }
4754
4755 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4756 {
4757         /* No memory barriers */
4758         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4759         mmiowb(); /* keep prod updates ordered */
4760 }
4761
4762 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4763                                       union event_ring_elem *elem)
4764 {
4765         u8 err = elem->message.error;
4766
4767         if (!bp->cnic_eth_dev.starting_cid  ||
4768             (cid < bp->cnic_eth_dev.starting_cid &&
4769             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4770                 return 1;
4771
4772         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4773
4774         if (unlikely(err)) {
4775
4776                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4777                           cid);
4778                 bnx2x_panic_dump(bp, false);
4779         }
4780         bnx2x_cnic_cfc_comp(bp, cid, err);
4781         return 0;
4782 }
4783
4784 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4785 {
4786         struct bnx2x_mcast_ramrod_params rparam;
4787         int rc;
4788
4789         memset(&rparam, 0, sizeof(rparam));
4790
4791         rparam.mcast_obj = &bp->mcast_obj;
4792
4793         netif_addr_lock_bh(bp->dev);
4794
4795         /* Clear pending state for the last command */
4796         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4797
4798         /* If there are pending mcast commands - send them */
4799         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4800                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4801                 if (rc < 0)
4802                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4803                                   rc);
4804         }
4805
4806         netif_addr_unlock_bh(bp->dev);
4807 }
4808
4809 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4810                                             union event_ring_elem *elem)
4811 {
4812         unsigned long ramrod_flags = 0;
4813         int rc = 0;
4814         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4815         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4816
4817         /* Always push next commands out, don't wait here */
4818         __set_bit(RAMROD_CONT, &ramrod_flags);
4819
4820         switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4821         case BNX2X_FILTER_MAC_PENDING:
4822                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4823                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4824                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4825                 else
4826                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4827
4828                 break;
4829         case BNX2X_FILTER_MCAST_PENDING:
4830                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4831                 /* This is only relevant for 57710 where multicast MACs are
4832                  * configured as unicast MACs using the same ramrod.
4833                  */
4834                 bnx2x_handle_mcast_eqe(bp);
4835                 return;
4836         default:
4837                 BNX2X_ERR("Unsupported classification command: %d\n",
4838                           elem->message.data.eth_event.echo);
4839                 return;
4840         }
4841
4842         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4843
4844         if (rc < 0)
4845                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4846         else if (rc > 0)
4847                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4848
4849 }
4850
4851 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4852
4853 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4854 {
4855         netif_addr_lock_bh(bp->dev);
4856
4857         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4858
4859         /* Send rx_mode command again if was requested */
4860         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4861                 bnx2x_set_storm_rx_mode(bp);
4862         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4863                                     &bp->sp_state))
4864                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4865         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4866                                     &bp->sp_state))
4867                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4868
4869         netif_addr_unlock_bh(bp->dev);
4870 }
4871
4872 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4873                                               union event_ring_elem *elem)
4874 {
4875         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4876                 DP(BNX2X_MSG_SP,
4877                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4878                    elem->message.data.vif_list_event.func_bit_map);
4879                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4880                         elem->message.data.vif_list_event.func_bit_map);
4881         } else if (elem->message.data.vif_list_event.echo ==
4882                    VIF_LIST_RULE_SET) {
4883                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4884                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4885         }
4886 }
4887
4888 /* called with rtnl_lock */
4889 static void bnx2x_after_function_update(struct bnx2x *bp)
4890 {
4891         int q, rc;
4892         struct bnx2x_fastpath *fp;
4893         struct bnx2x_queue_state_params queue_params = {NULL};
4894         struct bnx2x_queue_update_params *q_update_params =
4895                 &queue_params.params.update;
4896
4897         /* Send Q update command with afex vlan removal values  for all Qs */
4898         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4899
4900         /* set silent vlan removal values according to vlan mode */
4901         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4902                   &q_update_params->update_flags);
4903         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4904                   &q_update_params->update_flags);
4905         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4906
4907         /* in access mode mark mask and value are 0 to strip all vlans */
4908         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4909                 q_update_params->silent_removal_value = 0;
4910                 q_update_params->silent_removal_mask = 0;
4911         } else {
4912                 q_update_params->silent_removal_value =
4913                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4914                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4915         }
4916
4917         for_each_eth_queue(bp, q) {
4918                 /* Set the appropriate Queue object */
4919                 fp = &bp->fp[q];
4920                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4921
4922                 /* send the ramrod */
4923                 rc = bnx2x_queue_state_change(bp, &queue_params);
4924                 if (rc < 0)
4925                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4926                                   q);
4927         }
4928
4929         if (!NO_FCOE(bp)) {
4930                 fp = &bp->fp[FCOE_IDX(bp)];
4931                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4932
4933                 /* clear pending completion bit */
4934                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4935
4936                 /* mark latest Q bit */
4937                 smp_mb__before_clear_bit();
4938                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4939                 smp_mb__after_clear_bit();
4940
4941                 /* send Q update ramrod for FCoE Q */
4942                 rc = bnx2x_queue_state_change(bp, &queue_params);
4943                 if (rc < 0)
4944                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4945                                   q);
4946         } else {
4947                 /* If no FCoE ring - ACK MCP now */
4948                 bnx2x_link_report(bp);
4949                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4950         }
4951 }
4952
4953 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4954         struct bnx2x *bp, u32 cid)
4955 {
4956         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4957
4958         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
4959                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4960         else
4961                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4962 }
4963
4964 static void bnx2x_eq_int(struct bnx2x *bp)
4965 {
4966         u16 hw_cons, sw_cons, sw_prod;
4967         union event_ring_elem *elem;
4968         u8 echo;
4969         u32 cid;
4970         u8 opcode;
4971         int rc, spqe_cnt = 0;
4972         struct bnx2x_queue_sp_obj *q_obj;
4973         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4974         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4975
4976         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4977
4978         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4979          * when we get the the next-page we nned to adjust so the loop
4980          * condition below will be met. The next element is the size of a
4981          * regular element and hence incrementing by 1
4982          */
4983         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4984                 hw_cons++;
4985
4986         /* This function may never run in parallel with itself for a
4987          * specific bp, thus there is no need in "paired" read memory
4988          * barrier here.
4989          */
4990         sw_cons = bp->eq_cons;
4991         sw_prod = bp->eq_prod;
4992
4993         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
4994                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4995
4996         for (; sw_cons != hw_cons;
4997               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4998
4999
5000                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5001
5002                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5003                 if (!rc) {
5004                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5005                            rc);
5006                         goto next_spqe;
5007                 }
5008                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
5009                 opcode = elem->message.opcode;
5010
5011
5012                 /* handle eq element */
5013                 switch (opcode) {
5014                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5015                         DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5016                         bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5017                         continue;
5018
5019                 case EVENT_RING_OPCODE_STAT_QUERY:
5020                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5021                            "got statistics comp event %d\n",
5022                            bp->stats_comp++);
5023                         /* nothing to do with stats comp */
5024                         goto next_spqe;
5025
5026                 case EVENT_RING_OPCODE_CFC_DEL:
5027                         /* handle according to cid range */
5028                         /*
5029                          * we may want to verify here that the bp state is
5030                          * HALTING
5031                          */
5032                         DP(BNX2X_MSG_SP,
5033                            "got delete ramrod for MULTI[%d]\n", cid);
5034
5035                         if (CNIC_LOADED(bp) &&
5036                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5037                                 goto next_spqe;
5038
5039                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5040
5041                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5042                                 break;
5043
5044
5045
5046                         goto next_spqe;
5047
5048                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5049                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5050                         if (f_obj->complete_cmd(bp, f_obj,
5051                                                 BNX2X_F_CMD_TX_STOP))
5052                                 break;
5053                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5054                         goto next_spqe;
5055
5056                 case EVENT_RING_OPCODE_START_TRAFFIC:
5057                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5058                         if (f_obj->complete_cmd(bp, f_obj,
5059                                                 BNX2X_F_CMD_TX_START))
5060                                 break;
5061                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5062                         goto next_spqe;
5063
5064                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5065                         echo = elem->message.data.function_update_event.echo;
5066                         if (echo == SWITCH_UPDATE) {
5067                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5068                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5069                                 if (f_obj->complete_cmd(
5070                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5071                                         break;
5072
5073                         } else {
5074                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5075                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5076                                 f_obj->complete_cmd(bp, f_obj,
5077                                                     BNX2X_F_CMD_AFEX_UPDATE);
5078
5079                                 /* We will perform the Queues update from
5080                                  * sp_rtnl task as all Queue SP operations
5081                                  * should run under rtnl_lock.
5082                                  */
5083                                 smp_mb__before_clear_bit();
5084                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5085                                         &bp->sp_rtnl_state);
5086                                 smp_mb__after_clear_bit();
5087
5088                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5089                         }
5090
5091                         goto next_spqe;
5092
5093                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5094                         f_obj->complete_cmd(bp, f_obj,
5095                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5096                         bnx2x_after_afex_vif_lists(bp, elem);
5097                         goto next_spqe;
5098                 case EVENT_RING_OPCODE_FUNCTION_START:
5099                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5100                            "got FUNC_START ramrod\n");
5101                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5102                                 break;
5103
5104                         goto next_spqe;
5105
5106                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5107                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5108                            "got FUNC_STOP ramrod\n");
5109                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5110                                 break;
5111
5112                         goto next_spqe;
5113                 }
5114
5115                 switch (opcode | bp->state) {
5116                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5117                       BNX2X_STATE_OPEN):
5118                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5119                       BNX2X_STATE_OPENING_WAIT4_PORT):
5120                         cid = elem->message.data.eth_event.echo &
5121                                 BNX2X_SWCID_MASK;
5122                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5123                            cid);
5124                         rss_raw->clear_pending(rss_raw);
5125                         break;
5126
5127                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5128                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5129                 case (EVENT_RING_OPCODE_SET_MAC |
5130                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5131                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5132                       BNX2X_STATE_OPEN):
5133                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5134                       BNX2X_STATE_DIAG):
5135                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5136                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5137                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5138                         bnx2x_handle_classification_eqe(bp, elem);
5139                         break;
5140
5141                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5142                       BNX2X_STATE_OPEN):
5143                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5144                       BNX2X_STATE_DIAG):
5145                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5146                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5147                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5148                         bnx2x_handle_mcast_eqe(bp);
5149                         break;
5150
5151                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5152                       BNX2X_STATE_OPEN):
5153                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5154                       BNX2X_STATE_DIAG):
5155                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5156                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5157                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5158                         bnx2x_handle_rx_mode_eqe(bp);
5159                         break;
5160                 default:
5161                         /* unknown event log error and continue */
5162                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5163                                   elem->message.opcode, bp->state);
5164                 }
5165 next_spqe:
5166                 spqe_cnt++;
5167         } /* for */
5168
5169         smp_mb__before_atomic_inc();
5170         atomic_add(spqe_cnt, &bp->eq_spq_left);
5171
5172         bp->eq_cons = sw_cons;
5173         bp->eq_prod = sw_prod;
5174         /* Make sure that above mem writes were issued towards the memory */
5175         smp_wmb();
5176
5177         /* update producer */
5178         bnx2x_update_eq_prod(bp, bp->eq_prod);
5179 }
5180
5181 static void bnx2x_sp_task(struct work_struct *work)
5182 {
5183         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5184
5185         DP(BNX2X_MSG_SP, "sp task invoked\n");
5186
5187         /* make sure the atomic interupt_occurred has been written */
5188         smp_rmb();
5189         if (atomic_read(&bp->interrupt_occurred)) {
5190
5191                 /* what work needs to be performed? */
5192                 u16 status = bnx2x_update_dsb_idx(bp);
5193
5194                 DP(BNX2X_MSG_SP, "status %x\n", status);
5195                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5196                 atomic_set(&bp->interrupt_occurred, 0);
5197
5198                 /* HW attentions */
5199                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5200                         bnx2x_attn_int(bp);
5201                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5202                 }
5203
5204                 /* SP events: STAT_QUERY and others */
5205                 if (status & BNX2X_DEF_SB_IDX) {
5206                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5207
5208                 if (FCOE_INIT(bp) &&
5209                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5210                                 /* Prevent local bottom-halves from running as
5211                                  * we are going to change the local NAPI list.
5212                                  */
5213                                 local_bh_disable();
5214                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5215                                 local_bh_enable();
5216                         }
5217
5218                         /* Handle EQ completions */
5219                         bnx2x_eq_int(bp);
5220                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5221                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5222
5223                         status &= ~BNX2X_DEF_SB_IDX;
5224                 }
5225
5226                 /* if status is non zero then perhaps something went wrong */
5227                 if (unlikely(status))
5228                         DP(BNX2X_MSG_SP,
5229                            "got an unknown interrupt! (status 0x%x)\n", status);
5230
5231                 /* ack status block only if something was actually handled */
5232                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5233                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5234
5235         }
5236
5237         /* must be called after the EQ processing (since eq leads to sriov
5238          * ramrod completion flows).
5239          * This flow may have been scheduled by the arrival of a ramrod
5240          * completion, or by the sriov code rescheduling itself.
5241          */
5242         bnx2x_iov_sp_task(bp);
5243
5244         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5245         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5246                                &bp->sp_state)) {
5247                 bnx2x_link_report(bp);
5248                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5249         }
5250 }
5251
5252 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5253 {
5254         struct net_device *dev = dev_instance;
5255         struct bnx2x *bp = netdev_priv(dev);
5256
5257         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5258                      IGU_INT_DISABLE, 0);
5259
5260 #ifdef BNX2X_STOP_ON_ERROR
5261         if (unlikely(bp->panic))
5262                 return IRQ_HANDLED;
5263 #endif
5264
5265         if (CNIC_LOADED(bp)) {
5266                 struct cnic_ops *c_ops;
5267
5268                 rcu_read_lock();
5269                 c_ops = rcu_dereference(bp->cnic_ops);
5270                 if (c_ops)
5271                         c_ops->cnic_handler(bp->cnic_data, NULL);
5272                 rcu_read_unlock();
5273         }
5274
5275         /* schedule sp task to perform default status block work, ack
5276          * attentions and enable interrupts.
5277          */
5278         bnx2x_schedule_sp_task(bp);
5279
5280         return IRQ_HANDLED;
5281 }
5282
5283 /* end of slow path */
5284
5285
5286 void bnx2x_drv_pulse(struct bnx2x *bp)
5287 {
5288         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5289                  bp->fw_drv_pulse_wr_seq);
5290 }
5291
5292 static void bnx2x_timer(unsigned long data)
5293 {
5294         struct bnx2x *bp = (struct bnx2x *) data;
5295
5296         if (!netif_running(bp->dev))
5297                 return;
5298
5299         if (IS_PF(bp) &&
5300             !BP_NOMCP(bp)) {
5301                 int mb_idx = BP_FW_MB_IDX(bp);
5302                 u32 drv_pulse;
5303                 u32 mcp_pulse;
5304
5305                 ++bp->fw_drv_pulse_wr_seq;
5306                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5307                 /* TBD - add SYSTEM_TIME */
5308                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5309                 bnx2x_drv_pulse(bp);
5310
5311                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5312                              MCP_PULSE_SEQ_MASK);
5313                 /* The delta between driver pulse and mcp response
5314                  * should be 1 (before mcp response) or 0 (after mcp response)
5315                  */
5316                 if ((drv_pulse != mcp_pulse) &&
5317                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5318                         /* someone lost a heartbeat... */
5319                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5320                                   drv_pulse, mcp_pulse);
5321                 }
5322         }
5323
5324         if (bp->state == BNX2X_STATE_OPEN)
5325                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5326
5327         /* sample pf vf bulletin board for new posts from pf */
5328         if (IS_VF(bp))
5329                 bnx2x_sample_bulletin(bp);
5330
5331         mod_timer(&bp->timer, jiffies + bp->current_interval);
5332 }
5333
5334 /* end of Statistics */
5335
5336 /* nic init */
5337
5338 /*
5339  * nic init service functions
5340  */
5341
5342 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5343 {
5344         u32 i;
5345         if (!(len%4) && !(addr%4))
5346                 for (i = 0; i < len; i += 4)
5347                         REG_WR(bp, addr + i, fill);
5348         else
5349                 for (i = 0; i < len; i++)
5350                         REG_WR8(bp, addr + i, fill);
5351
5352 }
5353
5354 /* helper: writes FP SP data to FW - data_size in dwords */
5355 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5356                                 int fw_sb_id,
5357                                 u32 *sb_data_p,
5358                                 u32 data_size)
5359 {
5360         int index;
5361         for (index = 0; index < data_size; index++)
5362                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5363                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5364                         sizeof(u32)*index,
5365                         *(sb_data_p + index));
5366 }
5367
5368 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5369 {
5370         u32 *sb_data_p;
5371         u32 data_size = 0;
5372         struct hc_status_block_data_e2 sb_data_e2;
5373         struct hc_status_block_data_e1x sb_data_e1x;
5374
5375         /* disable the function first */
5376         if (!CHIP_IS_E1x(bp)) {
5377                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5378                 sb_data_e2.common.state = SB_DISABLED;
5379                 sb_data_e2.common.p_func.vf_valid = false;
5380                 sb_data_p = (u32 *)&sb_data_e2;
5381                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5382         } else {
5383                 memset(&sb_data_e1x, 0,
5384                        sizeof(struct hc_status_block_data_e1x));
5385                 sb_data_e1x.common.state = SB_DISABLED;
5386                 sb_data_e1x.common.p_func.vf_valid = false;
5387                 sb_data_p = (u32 *)&sb_data_e1x;
5388                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5389         }
5390         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5391
5392         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5393                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5394                         CSTORM_STATUS_BLOCK_SIZE);
5395         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5396                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5397                         CSTORM_SYNC_BLOCK_SIZE);
5398 }
5399
5400 /* helper:  writes SP SB data to FW */
5401 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5402                 struct hc_sp_status_block_data *sp_sb_data)
5403 {
5404         int func = BP_FUNC(bp);
5405         int i;
5406         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5407                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5408                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5409                         i*sizeof(u32),
5410                         *((u32 *)sp_sb_data + i));
5411 }
5412
5413 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5414 {
5415         int func = BP_FUNC(bp);
5416         struct hc_sp_status_block_data sp_sb_data;
5417         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5418
5419         sp_sb_data.state = SB_DISABLED;
5420         sp_sb_data.p_func.vf_valid = false;
5421
5422         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5423
5424         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5425                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5426                         CSTORM_SP_STATUS_BLOCK_SIZE);
5427         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5428                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5429                         CSTORM_SP_SYNC_BLOCK_SIZE);
5430
5431 }
5432
5433
5434 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5435                                            int igu_sb_id, int igu_seg_id)
5436 {
5437         hc_sm->igu_sb_id = igu_sb_id;
5438         hc_sm->igu_seg_id = igu_seg_id;
5439         hc_sm->timer_value = 0xFF;
5440         hc_sm->time_to_expire = 0xFFFFFFFF;
5441 }
5442
5443
5444 /* allocates state machine ids. */
5445 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5446 {
5447         /* zero out state machine indices */
5448         /* rx indices */
5449         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5450
5451         /* tx indices */
5452         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5453         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5454         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5455         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5456
5457         /* map indices */
5458         /* rx indices */
5459         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5460                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5461
5462         /* tx indices */
5463         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5464                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5465         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5466                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5467         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5468                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5469         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5470                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5471 }
5472
5473 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5474                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5475 {
5476         int igu_seg_id;
5477
5478         struct hc_status_block_data_e2 sb_data_e2;
5479         struct hc_status_block_data_e1x sb_data_e1x;
5480         struct hc_status_block_sm  *hc_sm_p;
5481         int data_size;
5482         u32 *sb_data_p;
5483
5484         if (CHIP_INT_MODE_IS_BC(bp))
5485                 igu_seg_id = HC_SEG_ACCESS_NORM;
5486         else
5487                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5488
5489         bnx2x_zero_fp_sb(bp, fw_sb_id);
5490
5491         if (!CHIP_IS_E1x(bp)) {
5492                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5493                 sb_data_e2.common.state = SB_ENABLED;
5494                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5495                 sb_data_e2.common.p_func.vf_id = vfid;
5496                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5497                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5498                 sb_data_e2.common.same_igu_sb_1b = true;
5499                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5500                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5501                 hc_sm_p = sb_data_e2.common.state_machine;
5502                 sb_data_p = (u32 *)&sb_data_e2;
5503                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5504                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5505         } else {
5506                 memset(&sb_data_e1x, 0,
5507                        sizeof(struct hc_status_block_data_e1x));
5508                 sb_data_e1x.common.state = SB_ENABLED;
5509                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5510                 sb_data_e1x.common.p_func.vf_id = 0xff;
5511                 sb_data_e1x.common.p_func.vf_valid = false;
5512                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5513                 sb_data_e1x.common.same_igu_sb_1b = true;
5514                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5515                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5516                 hc_sm_p = sb_data_e1x.common.state_machine;
5517                 sb_data_p = (u32 *)&sb_data_e1x;
5518                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5519                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5520         }
5521
5522         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5523                                        igu_sb_id, igu_seg_id);
5524         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5525                                        igu_sb_id, igu_seg_id);
5526
5527         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5528
5529         /* write indecies to HW */
5530         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5531 }
5532
5533 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5534                                      u16 tx_usec, u16 rx_usec)
5535 {
5536         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5537                                     false, rx_usec);
5538         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5539                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5540                                        tx_usec);
5541         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5542                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5543                                        tx_usec);
5544         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5545                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5546                                        tx_usec);
5547 }
5548
5549 static void bnx2x_init_def_sb(struct bnx2x *bp)
5550 {
5551         struct host_sp_status_block *def_sb = bp->def_status_blk;
5552         dma_addr_t mapping = bp->def_status_blk_mapping;
5553         int igu_sp_sb_index;
5554         int igu_seg_id;
5555         int port = BP_PORT(bp);
5556         int func = BP_FUNC(bp);
5557         int reg_offset, reg_offset_en5;
5558         u64 section;
5559         int index;
5560         struct hc_sp_status_block_data sp_sb_data;
5561         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5562
5563         if (CHIP_INT_MODE_IS_BC(bp)) {
5564                 igu_sp_sb_index = DEF_SB_IGU_ID;
5565                 igu_seg_id = HC_SEG_ACCESS_DEF;
5566         } else {
5567                 igu_sp_sb_index = bp->igu_dsb_id;
5568                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5569         }
5570
5571         /* ATTN */
5572         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5573                                             atten_status_block);
5574         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5575
5576         bp->attn_state = 0;
5577
5578         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5579                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5580         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5581                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5582         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5583                 int sindex;
5584                 /* take care of sig[0]..sig[4] */
5585                 for (sindex = 0; sindex < 4; sindex++)
5586                         bp->attn_group[index].sig[sindex] =
5587                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5588
5589                 if (!CHIP_IS_E1x(bp))
5590                         /*
5591                          * enable5 is separate from the rest of the registers,
5592                          * and therefore the address skip is 4
5593                          * and not 16 between the different groups
5594                          */
5595                         bp->attn_group[index].sig[4] = REG_RD(bp,
5596                                         reg_offset_en5 + 0x4*index);
5597                 else
5598                         bp->attn_group[index].sig[4] = 0;
5599         }
5600
5601         if (bp->common.int_block == INT_BLOCK_HC) {
5602                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5603                                      HC_REG_ATTN_MSG0_ADDR_L);
5604
5605                 REG_WR(bp, reg_offset, U64_LO(section));
5606                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5607         } else if (!CHIP_IS_E1x(bp)) {
5608                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5609                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5610         }
5611
5612         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5613                                             sp_sb);
5614
5615         bnx2x_zero_sp_sb(bp);
5616
5617         sp_sb_data.state                = SB_ENABLED;
5618         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5619         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5620         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5621         sp_sb_data.igu_seg_id           = igu_seg_id;
5622         sp_sb_data.p_func.pf_id         = func;
5623         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5624         sp_sb_data.p_func.vf_id         = 0xff;
5625
5626         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5627
5628         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5629 }
5630
5631 void bnx2x_update_coalesce(struct bnx2x *bp)
5632 {
5633         int i;
5634
5635         for_each_eth_queue(bp, i)
5636                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5637                                          bp->tx_ticks, bp->rx_ticks);
5638 }
5639
5640 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5641 {
5642         spin_lock_init(&bp->spq_lock);
5643         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5644
5645         bp->spq_prod_idx = 0;
5646         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5647         bp->spq_prod_bd = bp->spq;
5648         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5649 }
5650
5651 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5652 {
5653         int i;
5654         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5655                 union event_ring_elem *elem =
5656                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5657
5658                 elem->next_page.addr.hi =
5659                         cpu_to_le32(U64_HI(bp->eq_mapping +
5660                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5661                 elem->next_page.addr.lo =
5662                         cpu_to_le32(U64_LO(bp->eq_mapping +
5663                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5664         }
5665         bp->eq_cons = 0;
5666         bp->eq_prod = NUM_EQ_DESC;
5667         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5668         /* we want a warning message before it gets rought... */
5669         atomic_set(&bp->eq_spq_left,
5670                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5671 }
5672
5673
5674 /* called with netif_addr_lock_bh() */
5675 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5676                          unsigned long rx_mode_flags,
5677                          unsigned long rx_accept_flags,
5678                          unsigned long tx_accept_flags,
5679                          unsigned long ramrod_flags)
5680 {
5681         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5682         int rc;
5683
5684         memset(&ramrod_param, 0, sizeof(ramrod_param));
5685
5686         /* Prepare ramrod parameters */
5687         ramrod_param.cid = 0;
5688         ramrod_param.cl_id = cl_id;
5689         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5690         ramrod_param.func_id = BP_FUNC(bp);
5691
5692         ramrod_param.pstate = &bp->sp_state;
5693         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5694
5695         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5696         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5697
5698         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5699
5700         ramrod_param.ramrod_flags = ramrod_flags;
5701         ramrod_param.rx_mode_flags = rx_mode_flags;
5702
5703         ramrod_param.rx_accept_flags = rx_accept_flags;
5704         ramrod_param.tx_accept_flags = tx_accept_flags;
5705
5706         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5707         if (rc < 0) {
5708                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5709                 return;
5710         }
5711 }
5712
5713 /* called with netif_addr_lock_bh() */
5714 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5715 {
5716         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5717         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5718
5719         if (!NO_FCOE(bp))
5720
5721                 /* Configure rx_mode of FCoE Queue */
5722                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5723
5724         switch (bp->rx_mode) {
5725         case BNX2X_RX_MODE_NONE:
5726                 /*
5727                  * 'drop all' supersedes any accept flags that may have been
5728                  * passed to the function.
5729                  */
5730                 break;
5731         case BNX2X_RX_MODE_NORMAL:
5732                 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5733                 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5734                 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5735
5736                 /* internal switching mode */
5737                 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5738                 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5739                 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5740
5741                 break;
5742         case BNX2X_RX_MODE_ALLMULTI:
5743                 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5744                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5745                 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5746
5747                 /* internal switching mode */
5748                 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5749                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5750                 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5751
5752                 break;
5753         case BNX2X_RX_MODE_PROMISC:
5754                 /* According to deffinition of SI mode, iface in promisc mode
5755                  * should receive matched and unmatched (in resolution of port)
5756                  * unicast packets.
5757                  */
5758                 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5759                 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5760                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5761                 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5762
5763                 /* internal switching mode */
5764                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5765                 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5766
5767                 if (IS_MF_SI(bp))
5768                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5769                 else
5770                         __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5771
5772                 break;
5773         default:
5774                 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5775                 return;
5776         }
5777
5778         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5779                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5780                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5781         }
5782
5783         __set_bit(RAMROD_RX, &ramrod_flags);
5784         __set_bit(RAMROD_TX, &ramrod_flags);
5785
5786         bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5787                             tx_accept_flags, ramrod_flags);
5788 }
5789
5790 static void bnx2x_init_internal_common(struct bnx2x *bp)
5791 {
5792         int i;
5793
5794         if (IS_MF_SI(bp))
5795                 /*
5796                  * In switch independent mode, the TSTORM needs to accept
5797                  * packets that failed classification, since approximate match
5798                  * mac addresses aren't written to NIG LLH
5799                  */
5800                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5801                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5802         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5803                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5804                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5805
5806         /* Zero this manually as its initialization is
5807            currently missing in the initTool */
5808         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5809                 REG_WR(bp, BAR_USTRORM_INTMEM +
5810                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
5811         if (!CHIP_IS_E1x(bp)) {
5812                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5813                         CHIP_INT_MODE_IS_BC(bp) ?
5814                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5815         }
5816 }
5817
5818 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5819 {
5820         switch (load_code) {
5821         case FW_MSG_CODE_DRV_LOAD_COMMON:
5822         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5823                 bnx2x_init_internal_common(bp);
5824                 /* no break */
5825
5826         case FW_MSG_CODE_DRV_LOAD_PORT:
5827                 /* nothing to do */
5828                 /* no break */
5829
5830         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5831                 /* internal memory per function is
5832                    initialized inside bnx2x_pf_init */
5833                 break;
5834
5835         default:
5836                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5837                 break;
5838         }
5839 }
5840
5841 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5842 {
5843         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5844 }
5845
5846 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5847 {
5848         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5849 }
5850
5851 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5852 {
5853         if (CHIP_IS_E1x(fp->bp))
5854                 return BP_L_ID(fp->bp) + fp->index;
5855         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
5856                 return bnx2x_fp_igu_sb_id(fp);
5857 }
5858
5859 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5860 {
5861         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5862         u8 cos;
5863         unsigned long q_type = 0;
5864         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5865         fp->rx_queue = fp_idx;
5866         fp->cid = fp_idx;
5867         fp->cl_id = bnx2x_fp_cl_id(fp);
5868         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5869         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5870         /* qZone id equals to FW (per path) client id */
5871         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
5872
5873         /* init shortcut */
5874         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5875
5876         /* Setup SB indicies */
5877         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5878
5879         /* Configure Queue State object */
5880         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5881         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5882
5883         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5884
5885         /* init tx data */
5886         for_each_cos_in_tx_queue(fp, cos) {
5887                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5888                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5889                                   FP_COS_TO_TXQ(fp, cos, bp),
5890                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
5891                 cids[cos] = fp->txdata_ptr[cos]->cid;
5892         }
5893
5894         /* nothing more for vf to do here */
5895         if (IS_VF(bp))
5896                 return;
5897
5898         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5899                       fp->fw_sb_id, fp->igu_sb_id);
5900         bnx2x_update_fpsb_idx(fp);
5901         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5902                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5903                              bnx2x_sp_mapping(bp, q_rdata), q_type);
5904
5905         /**
5906          * Configure classification DBs: Always enable Tx switching
5907          */
5908         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5909
5910         DP(NETIF_MSG_IFUP,
5911            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
5912            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5913            fp->igu_sb_id);
5914 }
5915
5916 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5917 {
5918         int i;
5919
5920         for (i = 1; i <= NUM_TX_RINGS; i++) {
5921                 struct eth_tx_next_bd *tx_next_bd =
5922                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5923
5924                 tx_next_bd->addr_hi =
5925                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5926                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5927                 tx_next_bd->addr_lo =
5928                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5929                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5930         }
5931
5932         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5933         txdata->tx_db.data.zero_fill1 = 0;
5934         txdata->tx_db.data.prod = 0;
5935
5936         txdata->tx_pkt_prod = 0;
5937         txdata->tx_pkt_cons = 0;
5938         txdata->tx_bd_prod = 0;
5939         txdata->tx_bd_cons = 0;
5940         txdata->tx_pkt = 0;
5941 }
5942
5943 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5944 {
5945         int i;
5946
5947         for_each_tx_queue_cnic(bp, i)
5948                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
5949 }
5950 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5951 {
5952         int i;
5953         u8 cos;
5954
5955         for_each_eth_queue(bp, i)
5956                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5957                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5958 }
5959
5960 void bnx2x_nic_init_cnic(struct bnx2x *bp)
5961 {
5962         if (!NO_FCOE(bp))
5963                 bnx2x_init_fcoe_fp(bp);
5964
5965         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5966                       BNX2X_VF_ID_INVALID, false,
5967                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5968
5969         /* ensure status block indices were read */
5970         rmb();
5971         bnx2x_init_rx_rings_cnic(bp);
5972         bnx2x_init_tx_rings_cnic(bp);
5973
5974         /* flush all */
5975         mb();
5976         mmiowb();
5977 }
5978
5979 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5980 {
5981         int i;
5982
5983         for_each_eth_queue(bp, i)
5984                 bnx2x_init_eth_fp(bp, i);
5985
5986         /* ensure status block indices were read */
5987         rmb();
5988         bnx2x_init_rx_rings(bp);
5989         bnx2x_init_tx_rings(bp);
5990
5991         if (IS_VF(bp))
5992                 return;
5993
5994         /* Initialize MOD_ABS interrupts */
5995         bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5996                                bp->common.shmem_base, bp->common.shmem2_base,
5997                                BP_PORT(bp));
5998
5999         bnx2x_init_def_sb(bp);
6000         bnx2x_update_dsb_idx(bp);
6001         bnx2x_init_sp_ring(bp);
6002         bnx2x_init_eq_ring(bp);
6003         bnx2x_init_internal(bp, load_code);
6004         bnx2x_pf_init(bp);
6005         bnx2x_stats_init(bp);
6006
6007         /* flush all before enabling interrupts */
6008         mb();
6009         mmiowb();
6010
6011         bnx2x_int_enable(bp);
6012
6013         /* Check for SPIO5 */
6014         bnx2x_attn_int_deasserted0(bp,
6015                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6016                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6017 }
6018
6019 /* end of nic init */
6020
6021 /*
6022  * gzip service functions
6023  */
6024
6025 static int bnx2x_gunzip_init(struct bnx2x *bp)
6026 {
6027         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6028                                             &bp->gunzip_mapping, GFP_KERNEL);
6029         if (bp->gunzip_buf  == NULL)
6030                 goto gunzip_nomem1;
6031
6032         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6033         if (bp->strm  == NULL)
6034                 goto gunzip_nomem2;
6035
6036         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6037         if (bp->strm->workspace == NULL)
6038                 goto gunzip_nomem3;
6039
6040         return 0;
6041
6042 gunzip_nomem3:
6043         kfree(bp->strm);
6044         bp->strm = NULL;
6045
6046 gunzip_nomem2:
6047         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6048                           bp->gunzip_mapping);
6049         bp->gunzip_buf = NULL;
6050
6051 gunzip_nomem1:
6052         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6053         return -ENOMEM;
6054 }
6055
6056 static void bnx2x_gunzip_end(struct bnx2x *bp)
6057 {
6058         if (bp->strm) {
6059                 vfree(bp->strm->workspace);
6060                 kfree(bp->strm);
6061                 bp->strm = NULL;
6062         }
6063
6064         if (bp->gunzip_buf) {
6065                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6066                                   bp->gunzip_mapping);
6067                 bp->gunzip_buf = NULL;
6068         }
6069 }
6070
6071 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6072 {
6073         int n, rc;
6074
6075         /* check gzip header */
6076         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6077                 BNX2X_ERR("Bad gzip header\n");
6078                 return -EINVAL;
6079         }
6080
6081         n = 10;
6082
6083 #define FNAME                           0x8
6084
6085         if (zbuf[3] & FNAME)
6086                 while ((zbuf[n++] != 0) && (n < len));
6087
6088         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6089         bp->strm->avail_in = len - n;
6090         bp->strm->next_out = bp->gunzip_buf;
6091         bp->strm->avail_out = FW_BUF_SIZE;
6092
6093         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6094         if (rc != Z_OK)
6095                 return rc;
6096
6097         rc = zlib_inflate(bp->strm, Z_FINISH);
6098         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6099                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6100                            bp->strm->msg);
6101
6102         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6103         if (bp->gunzip_outlen & 0x3)
6104                 netdev_err(bp->dev,
6105                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6106                                 bp->gunzip_outlen);
6107         bp->gunzip_outlen >>= 2;
6108
6109         zlib_inflateEnd(bp->strm);
6110
6111         if (rc == Z_STREAM_END)
6112                 return 0;
6113
6114         return rc;
6115 }
6116
6117 /* nic load/unload */
6118
6119 /*
6120  * General service functions
6121  */
6122
6123 /* send a NIG loopback debug packet */
6124 static void bnx2x_lb_pckt(struct bnx2x *bp)
6125 {
6126         u32 wb_write[3];
6127
6128         /* Ethernet source and destination addresses */
6129         wb_write[0] = 0x55555555;
6130         wb_write[1] = 0x55555555;
6131         wb_write[2] = 0x20;             /* SOP */
6132         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6133
6134         /* NON-IP protocol */
6135         wb_write[0] = 0x09000000;
6136         wb_write[1] = 0x55555555;
6137         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6138         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6139 }
6140
6141 /* some of the internal memories
6142  * are not directly readable from the driver
6143  * to test them we send debug packets
6144  */
6145 static int bnx2x_int_mem_test(struct bnx2x *bp)
6146 {
6147         int factor;
6148         int count, i;
6149         u32 val = 0;
6150
6151         if (CHIP_REV_IS_FPGA(bp))
6152                 factor = 120;
6153         else if (CHIP_REV_IS_EMUL(bp))
6154                 factor = 200;
6155         else
6156                 factor = 1;
6157
6158         /* Disable inputs of parser neighbor blocks */
6159         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6160         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6161         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6162         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6163
6164         /*  Write 0 to parser credits for CFC search request */
6165         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6166
6167         /* send Ethernet packet */
6168         bnx2x_lb_pckt(bp);
6169
6170         /* TODO do i reset NIG statistic? */
6171         /* Wait until NIG register shows 1 packet of size 0x10 */
6172         count = 1000 * factor;
6173         while (count) {
6174
6175                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6176                 val = *bnx2x_sp(bp, wb_data[0]);
6177                 if (val == 0x10)
6178                         break;
6179
6180                 msleep(10);
6181                 count--;
6182         }
6183         if (val != 0x10) {
6184                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6185                 return -1;
6186         }
6187
6188         /* Wait until PRS register shows 1 packet */
6189         count = 1000 * factor;
6190         while (count) {
6191                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6192                 if (val == 1)
6193                         break;
6194
6195                 msleep(10);
6196                 count--;
6197         }
6198         if (val != 0x1) {
6199                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6200                 return -2;
6201         }
6202
6203         /* Reset and init BRB, PRS */
6204         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6205         msleep(50);
6206         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6207         msleep(50);
6208         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6209         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6210
6211         DP(NETIF_MSG_HW, "part2\n");
6212
6213         /* Disable inputs of parser neighbor blocks */
6214         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6215         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6216         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6217         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6218
6219         /* Write 0 to parser credits for CFC search request */
6220         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6221
6222         /* send 10 Ethernet packets */
6223         for (i = 0; i < 10; i++)
6224                 bnx2x_lb_pckt(bp);
6225
6226         /* Wait until NIG register shows 10 + 1
6227            packets of size 11*0x10 = 0xb0 */
6228         count = 1000 * factor;
6229         while (count) {
6230
6231                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6232                 val = *bnx2x_sp(bp, wb_data[0]);
6233                 if (val == 0xb0)
6234                         break;
6235
6236                 msleep(10);
6237                 count--;
6238         }
6239         if (val != 0xb0) {
6240                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6241                 return -3;
6242         }
6243
6244         /* Wait until PRS register shows 2 packets */
6245         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6246         if (val != 2)
6247                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6248
6249         /* Write 1 to parser credits for CFC search request */
6250         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6251
6252         /* Wait until PRS register shows 3 packets */
6253         msleep(10 * factor);
6254         /* Wait until NIG register shows 1 packet of size 0x10 */
6255         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6256         if (val != 3)
6257                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6258
6259         /* clear NIG EOP FIFO */
6260         for (i = 0; i < 11; i++)
6261                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6262         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6263         if (val != 1) {
6264                 BNX2X_ERR("clear of NIG failed\n");
6265                 return -4;
6266         }
6267
6268         /* Reset and init BRB, PRS, NIG */
6269         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6270         msleep(50);
6271         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6272         msleep(50);
6273         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6274         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6275         if (!CNIC_SUPPORT(bp))
6276                 /* set NIC mode */
6277                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6278
6279         /* Enable inputs of parser neighbor blocks */
6280         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6281         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6282         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6283         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6284
6285         DP(NETIF_MSG_HW, "done\n");
6286
6287         return 0; /* OK */
6288 }
6289
6290 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6291 {
6292         u32 val;
6293
6294         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6295         if (!CHIP_IS_E1x(bp))
6296                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6297         else
6298                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6299         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6300         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6301         /*
6302          * mask read length error interrupts in brb for parser
6303          * (parsing unit and 'checksum and crc' unit)
6304          * these errors are legal (PU reads fixed length and CAC can cause
6305          * read length error on truncated packets)
6306          */
6307         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6308         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6309         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6310         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6311         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6312         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6313 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6314 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6315         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6316         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6317         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6318 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6319 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6320         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6321         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6322         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6323         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6324 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6325 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6326
6327         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6328                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6329                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6330         if (!CHIP_IS_E1x(bp))
6331                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6332                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6333         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6334
6335         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6336         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6337         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6338 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6339
6340         if (!CHIP_IS_E1x(bp))
6341                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6342                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6343
6344         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6345         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6346 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6347         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6348 }
6349
6350 static void bnx2x_reset_common(struct bnx2x *bp)
6351 {
6352         u32 val = 0x1400;
6353
6354         /* reset_common */
6355         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6356                0xd3ffff7f);
6357
6358         if (CHIP_IS_E3(bp)) {
6359                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6360                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6361         }
6362
6363         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6364 }
6365
6366 static void bnx2x_setup_dmae(struct bnx2x *bp)
6367 {
6368         bp->dmae_ready = 0;
6369         spin_lock_init(&bp->dmae_lock);
6370 }
6371
6372 static void bnx2x_init_pxp(struct bnx2x *bp)
6373 {
6374         u16 devctl;
6375         int r_order, w_order;
6376
6377         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6378         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6379         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6380         if (bp->mrrs == -1)
6381                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6382         else {
6383                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6384                 r_order = bp->mrrs;
6385         }
6386
6387         bnx2x_init_pxp_arb(bp, r_order, w_order);
6388 }
6389
6390 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6391 {
6392         int is_required;
6393         u32 val;
6394         int port;
6395
6396         if (BP_NOMCP(bp))
6397                 return;
6398
6399         is_required = 0;
6400         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6401               SHARED_HW_CFG_FAN_FAILURE_MASK;
6402
6403         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6404                 is_required = 1;
6405
6406         /*
6407          * The fan failure mechanism is usually related to the PHY type since
6408          * the power consumption of the board is affected by the PHY. Currently,
6409          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6410          */
6411         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6412                 for (port = PORT_0; port < PORT_MAX; port++) {
6413                         is_required |=
6414                                 bnx2x_fan_failure_det_req(
6415                                         bp,
6416                                         bp->common.shmem_base,
6417                                         bp->common.shmem2_base,
6418                                         port);
6419                 }
6420
6421         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6422
6423         if (is_required == 0)
6424                 return;
6425
6426         /* Fan failure is indicated by SPIO 5 */
6427         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6428
6429         /* set to active low mode */
6430         val = REG_RD(bp, MISC_REG_SPIO_INT);
6431         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6432         REG_WR(bp, MISC_REG_SPIO_INT, val);
6433
6434         /* enable interrupt to signal the IGU */
6435         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6436         val |= MISC_SPIO_SPIO5;
6437         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6438 }
6439
6440 void bnx2x_pf_disable(struct bnx2x *bp)
6441 {
6442         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6443         val &= ~IGU_PF_CONF_FUNC_EN;
6444
6445         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6446         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6447         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6448 }
6449
6450 static void bnx2x__common_init_phy(struct bnx2x *bp)
6451 {
6452         u32 shmem_base[2], shmem2_base[2];
6453         /* Avoid common init in case MFW supports LFA */
6454         if (SHMEM2_RD(bp, size) >
6455             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6456                 return;
6457         shmem_base[0] =  bp->common.shmem_base;
6458         shmem2_base[0] = bp->common.shmem2_base;
6459         if (!CHIP_IS_E1x(bp)) {
6460                 shmem_base[1] =
6461                         SHMEM2_RD(bp, other_shmem_base_addr);
6462                 shmem2_base[1] =
6463                         SHMEM2_RD(bp, other_shmem2_base_addr);
6464         }
6465         bnx2x_acquire_phy_lock(bp);
6466         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6467                               bp->common.chip_id);
6468         bnx2x_release_phy_lock(bp);
6469 }
6470
6471 /**
6472  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6473  *
6474  * @bp:         driver handle
6475  */
6476 static int bnx2x_init_hw_common(struct bnx2x *bp)
6477 {
6478         u32 val;
6479
6480         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6481
6482         /*
6483          * take the UNDI lock to protect undi_unload flow from accessing
6484          * registers while we're resetting the chip
6485          */
6486         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6487
6488         bnx2x_reset_common(bp);
6489         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6490
6491         val = 0xfffc;
6492         if (CHIP_IS_E3(bp)) {
6493                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6494                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6495         }
6496         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6497
6498         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6499
6500         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6501
6502         if (!CHIP_IS_E1x(bp)) {
6503                 u8 abs_func_id;
6504
6505                 /**
6506                  * 4-port mode or 2-port mode we need to turn of master-enable
6507                  * for everyone, after that, turn it back on for self.
6508                  * so, we disregard multi-function or not, and always disable
6509                  * for all functions on the given path, this means 0,2,4,6 for
6510                  * path 0 and 1,3,5,7 for path 1
6511                  */
6512                 for (abs_func_id = BP_PATH(bp);
6513                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6514                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6515                                 REG_WR(bp,
6516                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6517                                     1);
6518                                 continue;
6519                         }
6520
6521                         bnx2x_pretend_func(bp, abs_func_id);
6522                         /* clear pf enable */
6523                         bnx2x_pf_disable(bp);
6524                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6525                 }
6526         }
6527
6528         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6529         if (CHIP_IS_E1(bp)) {
6530                 /* enable HW interrupt from PXP on USDM overflow
6531                    bit 16 on INT_MASK_0 */
6532                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6533         }
6534
6535         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6536         bnx2x_init_pxp(bp);
6537
6538 #ifdef __BIG_ENDIAN
6539         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6540         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6541         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6542         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6543         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6544         /* make sure this value is 0 */
6545         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6546
6547 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6548         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6549         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6550         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6551         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6552 #endif
6553
6554         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6555
6556         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6557                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6558
6559         /* let the HW do it's magic ... */
6560         msleep(100);
6561         /* finish PXP init */
6562         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6563         if (val != 1) {
6564                 BNX2X_ERR("PXP2 CFG failed\n");
6565                 return -EBUSY;
6566         }
6567         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6568         if (val != 1) {
6569                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6570                 return -EBUSY;
6571         }
6572
6573         /* Timers bug workaround E2 only. We need to set the entire ILT to
6574          * have entries with value "0" and valid bit on.
6575          * This needs to be done by the first PF that is loaded in a path
6576          * (i.e. common phase)
6577          */
6578         if (!CHIP_IS_E1x(bp)) {
6579 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6580  * (i.e. vnic3) to start even if it is marked as "scan-off".
6581  * This occurs when a different function (func2,3) is being marked
6582  * as "scan-off". Real-life scenario for example: if a driver is being
6583  * load-unloaded while func6,7 are down. This will cause the timer to access
6584  * the ilt, translate to a logical address and send a request to read/write.
6585  * Since the ilt for the function that is down is not valid, this will cause
6586  * a translation error which is unrecoverable.
6587  * The Workaround is intended to make sure that when this happens nothing fatal
6588  * will occur. The workaround:
6589  *      1.  First PF driver which loads on a path will:
6590  *              a.  After taking the chip out of reset, by using pretend,
6591  *                  it will write "0" to the following registers of
6592  *                  the other vnics.
6593  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6594  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6595  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6596  *                  And for itself it will write '1' to
6597  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6598  *                  dmae-operations (writing to pram for example.)
6599  *                  note: can be done for only function 6,7 but cleaner this
6600  *                        way.
6601  *              b.  Write zero+valid to the entire ILT.
6602  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6603  *                  VNIC3 (of that port). The range allocated will be the
6604  *                  entire ILT. This is needed to prevent  ILT range error.
6605  *      2.  Any PF driver load flow:
6606  *              a.  ILT update with the physical addresses of the allocated
6607  *                  logical pages.
6608  *              b.  Wait 20msec. - note that this timeout is needed to make
6609  *                  sure there are no requests in one of the PXP internal
6610  *                  queues with "old" ILT addresses.
6611  *              c.  PF enable in the PGLC.
6612  *              d.  Clear the was_error of the PF in the PGLC. (could have
6613  *                  occured while driver was down)
6614  *              e.  PF enable in the CFC (WEAK + STRONG)
6615  *              f.  Timers scan enable
6616  *      3.  PF driver unload flow:
6617  *              a.  Clear the Timers scan_en.
6618  *              b.  Polling for scan_on=0 for that PF.
6619  *              c.  Clear the PF enable bit in the PXP.
6620  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6621  *              e.  Write zero+valid to all ILT entries (The valid bit must
6622  *                  stay set)
6623  *              f.  If this is VNIC 3 of a port then also init
6624  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6625  *                  to the last enrty in the ILT.
6626  *
6627  *      Notes:
6628  *      Currently the PF error in the PGLC is non recoverable.
6629  *      In the future the there will be a recovery routine for this error.
6630  *      Currently attention is masked.
6631  *      Having an MCP lock on the load/unload process does not guarantee that
6632  *      there is no Timer disable during Func6/7 enable. This is because the
6633  *      Timers scan is currently being cleared by the MCP on FLR.
6634  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6635  *      there is error before clearing it. But the flow above is simpler and
6636  *      more general.
6637  *      All ILT entries are written by zero+valid and not just PF6/7
6638  *      ILT entries since in the future the ILT entries allocation for
6639  *      PF-s might be dynamic.
6640  */
6641                 struct ilt_client_info ilt_cli;
6642                 struct bnx2x_ilt ilt;
6643                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6644                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6645
6646                 /* initialize dummy TM client */
6647                 ilt_cli.start = 0;
6648                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6649                 ilt_cli.client_num = ILT_CLIENT_TM;
6650
6651                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6652                  * Step 2: set the timers first/last ilt entry to point
6653                  * to the entire range to prevent ILT range error for 3rd/4th
6654                  * vnic (this code assumes existance of the vnic)
6655                  *
6656                  * both steps performed by call to bnx2x_ilt_client_init_op()
6657                  * with dummy TM client
6658                  *
6659                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6660                  * and his brother are split registers
6661                  */
6662                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6663                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6664                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6665
6666                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6667                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6668                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6669         }
6670
6671
6672         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6673         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6674
6675         if (!CHIP_IS_E1x(bp)) {
6676                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6677                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6678                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6679
6680                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6681
6682                 /* let the HW do it's magic ... */
6683                 do {
6684                         msleep(200);
6685                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6686                 } while (factor-- && (val != 1));
6687
6688                 if (val != 1) {
6689                         BNX2X_ERR("ATC_INIT failed\n");
6690                         return -EBUSY;
6691                 }
6692         }
6693
6694         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6695
6696         bnx2x_iov_init_dmae(bp);
6697
6698         /* clean the DMAE memory */
6699         bp->dmae_ready = 1;
6700         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6701
6702         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6703
6704         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6705
6706         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6707
6708         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6709
6710         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6711         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6712         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6713         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6714
6715         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6716
6717
6718         /* QM queues pointers table */
6719         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6720
6721         /* soft reset pulse */
6722         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6723         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6724
6725         if (CNIC_SUPPORT(bp))
6726                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6727
6728         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6729         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6730         if (!CHIP_REV_IS_SLOW(bp))
6731                 /* enable hw interrupt from doorbell Q */
6732                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6733
6734         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6735
6736         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6737         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6738
6739         if (!CHIP_IS_E1(bp))
6740                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6741
6742         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6743                 if (IS_MF_AFEX(bp)) {
6744                         /* configure that VNTag and VLAN headers must be
6745                          * received in afex mode
6746                          */
6747                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6748                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6749                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6750                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6751                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6752                 } else {
6753                         /* Bit-map indicating which L2 hdrs may appear
6754                          * after the basic Ethernet header
6755                          */
6756                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6757                                bp->path_has_ovlan ? 7 : 6);
6758                 }
6759         }
6760
6761         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6762         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6763         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6764         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6765
6766         if (!CHIP_IS_E1x(bp)) {
6767                 /* reset VFC memories */
6768                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6769                            VFC_MEMORIES_RST_REG_CAM_RST |
6770                            VFC_MEMORIES_RST_REG_RAM_RST);
6771                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6772                            VFC_MEMORIES_RST_REG_CAM_RST |
6773                            VFC_MEMORIES_RST_REG_RAM_RST);
6774
6775                 msleep(20);
6776         }
6777
6778         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6779         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6780         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6781         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6782
6783         /* sync semi rtc */
6784         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6785                0x80000000);
6786         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6787                0x80000000);
6788
6789         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6790         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6791         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6792
6793         if (!CHIP_IS_E1x(bp)) {
6794                 if (IS_MF_AFEX(bp)) {
6795                         /* configure that VNTag and VLAN headers must be
6796                          * sent in afex mode
6797                          */
6798                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6799                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6800                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6801                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6802                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6803                 } else {
6804                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6805                                bp->path_has_ovlan ? 7 : 6);
6806                 }
6807         }
6808
6809         REG_WR(bp, SRC_REG_SOFT_RST, 1);
6810
6811         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6812
6813         if (CNIC_SUPPORT(bp)) {
6814                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6815                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6816                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6817                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6818                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6819                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6820                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6821                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6822                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6823                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6824         }
6825         REG_WR(bp, SRC_REG_SOFT_RST, 0);
6826
6827         if (sizeof(union cdu_context) != 1024)
6828                 /* we currently assume that a context is 1024 bytes */
6829                 dev_alert(&bp->pdev->dev,
6830                           "please adjust the size of cdu_context(%ld)\n",
6831                           (long)sizeof(union cdu_context));
6832
6833         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6834         val = (4 << 24) + (0 << 12) + 1024;
6835         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6836
6837         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6838         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6839         /* enable context validation interrupt from CFC */
6840         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6841
6842         /* set the thresholds to prevent CFC/CDU race */
6843         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6844
6845         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6846
6847         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6848                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6849
6850         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6851         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6852
6853         /* Reset PCIE errors for debug */
6854         REG_WR(bp, 0x2814, 0xffffffff);
6855         REG_WR(bp, 0x3820, 0xffffffff);
6856
6857         if (!CHIP_IS_E1x(bp)) {
6858                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6859                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6860                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6861                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6862                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6863                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6864                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6865                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6866                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6867                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6868                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6869         }
6870
6871         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6872         if (!CHIP_IS_E1(bp)) {
6873                 /* in E3 this done in per-port section */
6874                 if (!CHIP_IS_E3(bp))
6875                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6876         }
6877         if (CHIP_IS_E1H(bp))
6878                 /* not applicable for E2 (and above ...) */
6879                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6880
6881         if (CHIP_REV_IS_SLOW(bp))
6882                 msleep(200);
6883
6884         /* finish CFC init */
6885         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6886         if (val != 1) {
6887                 BNX2X_ERR("CFC LL_INIT failed\n");
6888                 return -EBUSY;
6889         }
6890         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6891         if (val != 1) {
6892                 BNX2X_ERR("CFC AC_INIT failed\n");
6893                 return -EBUSY;
6894         }
6895         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6896         if (val != 1) {
6897                 BNX2X_ERR("CFC CAM_INIT failed\n");
6898                 return -EBUSY;
6899         }
6900         REG_WR(bp, CFC_REG_DEBUG0, 0);
6901
6902         if (CHIP_IS_E1(bp)) {
6903                 /* read NIG statistic
6904                    to see if this is our first up since powerup */
6905                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6906                 val = *bnx2x_sp(bp, wb_data[0]);
6907
6908                 /* do internal memory self test */
6909                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6910                         BNX2X_ERR("internal mem self test failed\n");
6911                         return -EBUSY;
6912                 }
6913         }
6914
6915         bnx2x_setup_fan_failure_detection(bp);
6916
6917         /* clear PXP2 attentions */
6918         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6919
6920         bnx2x_enable_blocks_attention(bp);
6921         bnx2x_enable_blocks_parity(bp);
6922
6923         if (!BP_NOMCP(bp)) {
6924                 if (CHIP_IS_E1x(bp))
6925                         bnx2x__common_init_phy(bp);
6926         } else
6927                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6928
6929         return 0;
6930 }
6931
6932 /**
6933  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6934  *
6935  * @bp:         driver handle
6936  */
6937 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6938 {
6939         int rc = bnx2x_init_hw_common(bp);
6940
6941         if (rc)
6942                 return rc;
6943
6944         /* In E2 2-PORT mode, same ext phy is used for the two paths */
6945         if (!BP_NOMCP(bp))
6946                 bnx2x__common_init_phy(bp);
6947
6948         return 0;
6949 }
6950
6951 static int bnx2x_init_hw_port(struct bnx2x *bp)
6952 {
6953         int port = BP_PORT(bp);
6954         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6955         u32 low, high;
6956         u32 val;
6957
6958
6959         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
6960
6961         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6962
6963         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6964         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6965         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6966
6967         /* Timers bug workaround: disables the pf_master bit in pglue at
6968          * common phase, we need to enable it here before any dmae access are
6969          * attempted. Therefore we manually added the enable-master to the
6970          * port phase (it also happens in the function phase)
6971          */
6972         if (!CHIP_IS_E1x(bp))
6973                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6974
6975         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6976         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6977         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6978         bnx2x_init_block(bp, BLOCK_QM, init_phase);
6979
6980         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6981         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6982         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6983         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6984
6985         /* QM cid (connection) count */
6986         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6987
6988         if (CNIC_SUPPORT(bp)) {
6989                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6990                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6991                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6992         }
6993
6994         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6995
6996         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6997
6998         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6999
7000                 if (IS_MF(bp))
7001                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7002                 else if (bp->dev->mtu > 4096) {
7003                         if (bp->flags & ONE_PORT_FLAG)
7004                                 low = 160;
7005                         else {
7006                                 val = bp->dev->mtu;
7007                                 /* (24*1024 + val*4)/256 */
7008                                 low = 96 + (val/64) +
7009                                                 ((val % 64) ? 1 : 0);
7010                         }
7011                 } else
7012                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7013                 high = low + 56;        /* 14*1024/256 */
7014                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7015                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7016         }
7017
7018         if (CHIP_MODE_IS_4_PORT(bp))
7019                 REG_WR(bp, (BP_PORT(bp) ?
7020                             BRB1_REG_MAC_GUARANTIED_1 :
7021                             BRB1_REG_MAC_GUARANTIED_0), 40);
7022
7023
7024         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7025         if (CHIP_IS_E3B0(bp)) {
7026                 if (IS_MF_AFEX(bp)) {
7027                         /* configure headers for AFEX mode */
7028                         REG_WR(bp, BP_PORT(bp) ?
7029                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7030                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7031                         REG_WR(bp, BP_PORT(bp) ?
7032                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7033                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7034                         REG_WR(bp, BP_PORT(bp) ?
7035                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7036                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7037                 } else {
7038                         /* Ovlan exists only if we are in multi-function +
7039                          * switch-dependent mode, in switch-independent there
7040                          * is no ovlan headers
7041                          */
7042                         REG_WR(bp, BP_PORT(bp) ?
7043                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7044                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7045                                (bp->path_has_ovlan ? 7 : 6));
7046                 }
7047         }
7048
7049         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7050         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7051         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7052         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7053
7054         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7055         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7056         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7057         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7058
7059         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7060         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7061
7062         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7063
7064         if (CHIP_IS_E1x(bp)) {
7065                 /* configure PBF to work without PAUSE mtu 9000 */
7066                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7067
7068                 /* update threshold */
7069                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7070                 /* update init credit */
7071                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7072
7073                 /* probe changes */
7074                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7075                 udelay(50);
7076                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7077         }
7078
7079         if (CNIC_SUPPORT(bp))
7080                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7081
7082         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7083         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7084
7085         if (CHIP_IS_E1(bp)) {
7086                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7087                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7088         }
7089         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7090
7091         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7092
7093         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7094         /* init aeu_mask_attn_func_0/1:
7095          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
7096          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
7097          *             bits 4-7 are used for "per vn group attention" */
7098         val = IS_MF(bp) ? 0xF7 : 0x7;
7099         /* Enable DCBX attention for all but E1 */
7100         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7101         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7102
7103         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7104
7105         if (!CHIP_IS_E1x(bp)) {
7106                 /* Bit-map indicating which L2 hdrs may appear after the
7107                  * basic Ethernet header
7108                  */
7109                 if (IS_MF_AFEX(bp))
7110                         REG_WR(bp, BP_PORT(bp) ?
7111                                NIG_REG_P1_HDRS_AFTER_BASIC :
7112                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7113                 else
7114                         REG_WR(bp, BP_PORT(bp) ?
7115                                NIG_REG_P1_HDRS_AFTER_BASIC :
7116                                NIG_REG_P0_HDRS_AFTER_BASIC,
7117                                IS_MF_SD(bp) ? 7 : 6);
7118
7119                 if (CHIP_IS_E3(bp))
7120                         REG_WR(bp, BP_PORT(bp) ?
7121                                    NIG_REG_LLH1_MF_MODE :
7122                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7123         }
7124         if (!CHIP_IS_E3(bp))
7125                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7126
7127         if (!CHIP_IS_E1(bp)) {
7128                 /* 0x2 disable mf_ov, 0x1 enable */
7129                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7130                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7131
7132                 if (!CHIP_IS_E1x(bp)) {
7133                         val = 0;
7134                         switch (bp->mf_mode) {
7135                         case MULTI_FUNCTION_SD:
7136                                 val = 1;
7137                                 break;
7138                         case MULTI_FUNCTION_SI:
7139                         case MULTI_FUNCTION_AFEX:
7140                                 val = 2;
7141                                 break;
7142                         }
7143
7144                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7145                                                   NIG_REG_LLH0_CLS_TYPE), val);
7146                 }
7147                 {
7148                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7149                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7150                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7151                 }
7152         }
7153
7154
7155         /* If SPIO5 is set to generate interrupts, enable it for this port */
7156         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7157         if (val & MISC_SPIO_SPIO5) {
7158                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7159                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7160                 val = REG_RD(bp, reg_addr);
7161                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7162                 REG_WR(bp, reg_addr, val);
7163         }
7164
7165         return 0;
7166 }
7167
7168 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7169 {
7170         int reg;
7171         u32 wb_write[2];
7172
7173         if (CHIP_IS_E1(bp))
7174                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7175         else
7176                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7177
7178         wb_write[0] = ONCHIP_ADDR1(addr);
7179         wb_write[1] = ONCHIP_ADDR2(addr);
7180         REG_WR_DMAE(bp, reg, wb_write, 2);
7181 }
7182
7183 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7184 {
7185         u32 data, ctl, cnt = 100;
7186         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7187         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7188         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7189         u32 sb_bit =  1 << (idu_sb_id%32);
7190         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7191         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7192
7193         /* Not supported in BC mode */
7194         if (CHIP_INT_MODE_IS_BC(bp))
7195                 return;
7196
7197         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7198                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7199                 IGU_REGULAR_CLEANUP_SET                         |
7200                 IGU_REGULAR_BCLEANUP;
7201
7202         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7203               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7204               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7205
7206         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7207                          data, igu_addr_data);
7208         REG_WR(bp, igu_addr_data, data);
7209         mmiowb();
7210         barrier();
7211         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7212                           ctl, igu_addr_ctl);
7213         REG_WR(bp, igu_addr_ctl, ctl);
7214         mmiowb();
7215         barrier();
7216
7217         /* wait for clean up to finish */
7218         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7219                 msleep(20);
7220
7221
7222         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7223                 DP(NETIF_MSG_HW,
7224                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7225                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7226         }
7227 }
7228
7229 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7230 {
7231         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7232 }
7233
7234 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7235 {
7236         u32 i, base = FUNC_ILT_BASE(func);
7237         for (i = base; i < base + ILT_PER_FUNC; i++)
7238                 bnx2x_ilt_wr(bp, i, 0);
7239 }
7240
7241
7242 static void bnx2x_init_searcher(struct bnx2x *bp)
7243 {
7244         int port = BP_PORT(bp);
7245         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7246         /* T1 hash bits value determines the T1 number of entries */
7247         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7248 }
7249
7250 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7251 {
7252         int rc;
7253         struct bnx2x_func_state_params func_params = {NULL};
7254         struct bnx2x_func_switch_update_params *switch_update_params =
7255                 &func_params.params.switch_update;
7256
7257         /* Prepare parameters for function state transitions */
7258         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7259         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7260
7261         func_params.f_obj = &bp->func_obj;
7262         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7263
7264         /* Function parameters */
7265         switch_update_params->suspend = suspend;
7266
7267         rc = bnx2x_func_state_change(bp, &func_params);
7268
7269         return rc;
7270 }
7271
7272 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7273 {
7274         int rc, i, port = BP_PORT(bp);
7275         int vlan_en = 0, mac_en[NUM_MACS];
7276
7277
7278         /* Close input from network */
7279         if (bp->mf_mode == SINGLE_FUNCTION) {
7280                 bnx2x_set_rx_filter(&bp->link_params, 0);
7281         } else {
7282                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7283                                    NIG_REG_LLH0_FUNC_EN);
7284                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7285                           NIG_REG_LLH0_FUNC_EN, 0);
7286                 for (i = 0; i < NUM_MACS; i++) {
7287                         mac_en[i] = REG_RD(bp, port ?
7288                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7289                                               4 * i) :
7290                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7291                                               4 * i));
7292                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7293                                               4 * i) :
7294                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7295                 }
7296         }
7297
7298         /* Close BMC to host */
7299         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7300                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7301
7302         /* Suspend Tx switching to the PF. Completion of this ramrod
7303          * further guarantees that all the packets of that PF / child
7304          * VFs in BRB were processed by the Parser, so it is safe to
7305          * change the NIC_MODE register.
7306          */
7307         rc = bnx2x_func_switch_update(bp, 1);
7308         if (rc) {
7309                 BNX2X_ERR("Can't suspend tx-switching!\n");
7310                 return rc;
7311         }
7312
7313         /* Change NIC_MODE register */
7314         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7315
7316         /* Open input from network */
7317         if (bp->mf_mode == SINGLE_FUNCTION) {
7318                 bnx2x_set_rx_filter(&bp->link_params, 1);
7319         } else {
7320                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7321                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7322                 for (i = 0; i < NUM_MACS; i++) {
7323                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7324                                               4 * i) :
7325                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7326                                   mac_en[i]);
7327                 }
7328         }
7329
7330         /* Enable BMC to host */
7331         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7332                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7333
7334         /* Resume Tx switching to the PF */
7335         rc = bnx2x_func_switch_update(bp, 0);
7336         if (rc) {
7337                 BNX2X_ERR("Can't resume tx-switching!\n");
7338                 return rc;
7339         }
7340
7341         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7342         return 0;
7343 }
7344
7345 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7346 {
7347         int rc;
7348
7349         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7350
7351         if (CONFIGURE_NIC_MODE(bp)) {
7352                 /* Configrue searcher as part of function hw init */
7353                 bnx2x_init_searcher(bp);
7354
7355                 /* Reset NIC mode */
7356                 rc = bnx2x_reset_nic_mode(bp);
7357                 if (rc)
7358                         BNX2X_ERR("Can't change NIC mode!\n");
7359                 return rc;
7360         }
7361
7362         return 0;
7363 }
7364
7365 static int bnx2x_init_hw_func(struct bnx2x *bp)
7366 {
7367         int port = BP_PORT(bp);
7368         int func = BP_FUNC(bp);
7369         int init_phase = PHASE_PF0 + func;
7370         struct bnx2x_ilt *ilt = BP_ILT(bp);
7371         u16 cdu_ilt_start;
7372         u32 addr, val;
7373         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7374         int i, main_mem_width, rc;
7375
7376         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7377
7378         /* FLR cleanup - hmmm */
7379         if (!CHIP_IS_E1x(bp)) {
7380                 rc = bnx2x_pf_flr_clnup(bp);
7381                 if (rc)
7382                         return rc;
7383         }
7384
7385         /* set MSI reconfigure capability */
7386         if (bp->common.int_block == INT_BLOCK_HC) {
7387                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7388                 val = REG_RD(bp, addr);
7389                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7390                 REG_WR(bp, addr, val);
7391         }
7392
7393         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7394         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7395
7396         ilt = BP_ILT(bp);
7397         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7398
7399         if (IS_SRIOV(bp))
7400                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7401         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7402
7403         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7404          * those of the VFs, so start line should be reset
7405          */
7406         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7407         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7408                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7409                 ilt->lines[cdu_ilt_start + i].page_mapping =
7410                         bp->context[i].cxt_mapping;
7411                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7412         }
7413
7414         bnx2x_ilt_init_op(bp, INITOP_SET);
7415
7416         if (!CONFIGURE_NIC_MODE(bp)) {
7417                 bnx2x_init_searcher(bp);
7418                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7419                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7420         } else {
7421                 /* Set NIC mode */
7422                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7423                 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
7424
7425         }
7426
7427         if (!CHIP_IS_E1x(bp)) {
7428                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7429
7430                 /* Turn on a single ISR mode in IGU if driver is going to use
7431                  * INT#x or MSI
7432                  */
7433                 if (!(bp->flags & USING_MSIX_FLAG))
7434                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7435                 /*
7436                  * Timers workaround bug: function init part.
7437                  * Need to wait 20msec after initializing ILT,
7438                  * needed to make sure there are no requests in
7439                  * one of the PXP internal queues with "old" ILT addresses
7440                  */
7441                 msleep(20);
7442                 /*
7443                  * Master enable - Due to WB DMAE writes performed before this
7444                  * register is re-initialized as part of the regular function
7445                  * init
7446                  */
7447                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7448                 /* Enable the function in IGU */
7449                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7450         }
7451
7452         bp->dmae_ready = 1;
7453
7454         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7455
7456         if (!CHIP_IS_E1x(bp))
7457                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7458
7459         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7460         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7461         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7462         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7463         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7464         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7465         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7466         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7467         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7468         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7469         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7470         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7471         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7472
7473         if (!CHIP_IS_E1x(bp))
7474                 REG_WR(bp, QM_REG_PF_EN, 1);
7475
7476         if (!CHIP_IS_E1x(bp)) {
7477                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7478                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7479                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7480                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7481         }
7482         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7483
7484         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7485         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7486
7487         bnx2x_iov_init_dq(bp);
7488
7489         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7490         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7491         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7492         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7493         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7494         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7495         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7496         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7497         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7498         if (!CHIP_IS_E1x(bp))
7499                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7500
7501         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7502
7503         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7504
7505         if (!CHIP_IS_E1x(bp))
7506                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7507
7508         if (IS_MF(bp)) {
7509                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7510                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7511         }
7512
7513         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7514
7515         /* HC init per function */
7516         if (bp->common.int_block == INT_BLOCK_HC) {
7517                 if (CHIP_IS_E1H(bp)) {
7518                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7519
7520                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7521                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7522                 }
7523                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7524
7525         } else {
7526                 int num_segs, sb_idx, prod_offset;
7527
7528                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7529
7530                 if (!CHIP_IS_E1x(bp)) {
7531                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7532                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7533                 }
7534
7535                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7536
7537                 if (!CHIP_IS_E1x(bp)) {
7538                         int dsb_idx = 0;
7539                         /**
7540                          * Producer memory:
7541                          * E2 mode: address 0-135 match to the mapping memory;
7542                          * 136 - PF0 default prod; 137 - PF1 default prod;
7543                          * 138 - PF2 default prod; 139 - PF3 default prod;
7544                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7545                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7546                          * 144-147 reserved.
7547                          *
7548                          * E1.5 mode - In backward compatible mode;
7549                          * for non default SB; each even line in the memory
7550                          * holds the U producer and each odd line hold
7551                          * the C producer. The first 128 producers are for
7552                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7553                          * producers are for the DSB for each PF.
7554                          * Each PF has five segments: (the order inside each
7555                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7556                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7557                          * 144-147 attn prods;
7558                          */
7559                         /* non-default-status-blocks */
7560                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7561                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7562                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7563                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7564                                         num_segs;
7565
7566                                 for (i = 0; i < num_segs; i++) {
7567                                         addr = IGU_REG_PROD_CONS_MEMORY +
7568                                                         (prod_offset + i) * 4;
7569                                         REG_WR(bp, addr, 0);
7570                                 }
7571                                 /* send consumer update with value 0 */
7572                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7573                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7574                                 bnx2x_igu_clear_sb(bp,
7575                                                    bp->igu_base_sb + sb_idx);
7576                         }
7577
7578                         /* default-status-blocks */
7579                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7580                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7581
7582                         if (CHIP_MODE_IS_4_PORT(bp))
7583                                 dsb_idx = BP_FUNC(bp);
7584                         else
7585                                 dsb_idx = BP_VN(bp);
7586
7587                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7588                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7589                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7590
7591                         /*
7592                          * igu prods come in chunks of E1HVN_MAX (4) -
7593                          * does not matters what is the current chip mode
7594                          */
7595                         for (i = 0; i < (num_segs * E1HVN_MAX);
7596                              i += E1HVN_MAX) {
7597                                 addr = IGU_REG_PROD_CONS_MEMORY +
7598                                                         (prod_offset + i)*4;
7599                                 REG_WR(bp, addr, 0);
7600                         }
7601                         /* send consumer update with 0 */
7602                         if (CHIP_INT_MODE_IS_BC(bp)) {
7603                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7604                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7605                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7606                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7607                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7608                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7609                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7610                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7611                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7612                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7613                         } else {
7614                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7615                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7616                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7617                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7618                         }
7619                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7620
7621                         /* !!! these should become driver const once
7622                            rf-tool supports split-68 const */
7623                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7624                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7625                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7626                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7627                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7628                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7629                 }
7630         }
7631
7632         /* Reset PCIE errors for debug */
7633         REG_WR(bp, 0x2114, 0xffffffff);
7634         REG_WR(bp, 0x2120, 0xffffffff);
7635
7636         if (CHIP_IS_E1x(bp)) {
7637                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7638                 main_mem_base = HC_REG_MAIN_MEMORY +
7639                                 BP_PORT(bp) * (main_mem_size * 4);
7640                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7641                 main_mem_width = 8;
7642
7643                 val = REG_RD(bp, main_mem_prty_clr);
7644                 if (val)
7645                         DP(NETIF_MSG_HW,
7646                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7647                            val);
7648
7649                 /* Clear "false" parity errors in MSI-X table */
7650                 for (i = main_mem_base;
7651                      i < main_mem_base + main_mem_size * 4;
7652                      i += main_mem_width) {
7653                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7654                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7655                                          i, main_mem_width / 4);
7656                 }
7657                 /* Clear HC parity attention */
7658                 REG_RD(bp, main_mem_prty_clr);
7659         }
7660
7661 #ifdef BNX2X_STOP_ON_ERROR
7662         /* Enable STORMs SP logging */
7663         REG_WR8(bp, BAR_USTRORM_INTMEM +
7664                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7665         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7666                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7667         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7668                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7669         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7670                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7671 #endif
7672
7673         bnx2x_phy_probe(&bp->link_params);
7674
7675         return 0;
7676 }
7677
7678
7679 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7680 {
7681         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7682
7683         if (!CHIP_IS_E1x(bp))
7684                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7685                                sizeof(struct host_hc_status_block_e2));
7686         else
7687                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7688                                sizeof(struct host_hc_status_block_e1x));
7689
7690         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7691 }
7692
7693 void bnx2x_free_mem(struct bnx2x *bp)
7694 {
7695         int i;
7696
7697         /* fastpath */
7698         bnx2x_free_fp_mem(bp);
7699         /* end of fastpath */
7700
7701         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7702                        sizeof(struct host_sp_status_block));
7703
7704         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7705                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7706
7707         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7708                        sizeof(struct bnx2x_slowpath));
7709
7710         for (i = 0; i < L2_ILT_LINES(bp); i++)
7711                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7712                                bp->context[i].size);
7713         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7714
7715         BNX2X_FREE(bp->ilt->lines);
7716
7717         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7718
7719         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7720                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7721 }
7722
7723
7724 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7725 {
7726         if (!CHIP_IS_E1x(bp))
7727                 /* size = the status block + ramrod buffers */
7728                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7729                                 sizeof(struct host_hc_status_block_e2));
7730         else
7731                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7732                                 &bp->cnic_sb_mapping,
7733                                 sizeof(struct
7734                                        host_hc_status_block_e1x));
7735
7736         if (CONFIGURE_NIC_MODE(bp))
7737                 /* allocate searcher T2 table, as it wan't allocated before */
7738                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7739
7740         /* write address to which L5 should insert its values */
7741         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7742                 &bp->slowpath->drv_info_to_mcp;
7743
7744         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7745                 goto alloc_mem_err;
7746
7747         return 0;
7748
7749 alloc_mem_err:
7750         bnx2x_free_mem_cnic(bp);
7751         BNX2X_ERR("Can't allocate memory\n");
7752         return -ENOMEM;
7753 }
7754
7755 int bnx2x_alloc_mem(struct bnx2x *bp)
7756 {
7757         int i, allocated, context_size;
7758
7759         if (!CONFIGURE_NIC_MODE(bp))
7760                 /* allocate searcher T2 table */
7761                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7762
7763         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7764                         sizeof(struct host_sp_status_block));
7765
7766         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7767                         sizeof(struct bnx2x_slowpath));
7768
7769         /* Allocate memory for CDU context:
7770          * This memory is allocated separately and not in the generic ILT
7771          * functions because CDU differs in few aspects:
7772          * 1. There are multiple entities allocating memory for context -
7773          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7774          * its own ILT lines.
7775          * 2. Since CDU page-size is not a single 4KB page (which is the case
7776          * for the other ILT clients), to be efficient we want to support
7777          * allocation of sub-page-size in the last entry.
7778          * 3. Context pointers are used by the driver to pass to FW / update
7779          * the context (for the other ILT clients the pointers are used just to
7780          * free the memory during unload).
7781          */
7782         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7783
7784         for (i = 0, allocated = 0; allocated < context_size; i++) {
7785                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7786                                           (context_size - allocated));
7787                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7788                                 &bp->context[i].cxt_mapping,
7789                                 bp->context[i].size);
7790                 allocated += bp->context[i].size;
7791         }
7792         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7793
7794         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7795                 goto alloc_mem_err;
7796
7797         if (bnx2x_iov_alloc_mem(bp))
7798                 goto alloc_mem_err;
7799
7800         /* Slow path ring */
7801         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7802
7803         /* EQ */
7804         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7805                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
7806
7807         return 0;
7808
7809 alloc_mem_err:
7810         bnx2x_free_mem(bp);
7811         BNX2X_ERR("Can't allocate memory\n");
7812         return -ENOMEM;
7813 }
7814
7815 /*
7816  * Init service functions
7817  */
7818
7819 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7820                       struct bnx2x_vlan_mac_obj *obj, bool set,
7821                       int mac_type, unsigned long *ramrod_flags)
7822 {
7823         int rc;
7824         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7825
7826         memset(&ramrod_param, 0, sizeof(ramrod_param));
7827
7828         /* Fill general parameters */
7829         ramrod_param.vlan_mac_obj = obj;
7830         ramrod_param.ramrod_flags = *ramrod_flags;
7831
7832         /* Fill a user request section if needed */
7833         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7834                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7835
7836                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7837
7838                 /* Set the command: ADD or DEL */
7839                 if (set)
7840                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7841                 else
7842                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7843         }
7844
7845         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7846
7847         if (rc == -EEXIST) {
7848                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7849                 /* do not treat adding same MAC as error */
7850                 rc = 0;
7851         } else if (rc < 0)
7852                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7853
7854         return rc;
7855 }
7856
7857 int bnx2x_del_all_macs(struct bnx2x *bp,
7858                        struct bnx2x_vlan_mac_obj *mac_obj,
7859                        int mac_type, bool wait_for_comp)
7860 {
7861         int rc;
7862         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7863
7864         /* Wait for completion of requested */
7865         if (wait_for_comp)
7866                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7867
7868         /* Set the mac type of addresses we want to clear */
7869         __set_bit(mac_type, &vlan_mac_flags);
7870
7871         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7872         if (rc < 0)
7873                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7874
7875         return rc;
7876 }
7877
7878 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7879 {
7880         unsigned long ramrod_flags = 0;
7881
7882         if (is_zero_ether_addr(bp->dev->dev_addr) &&
7883             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7884                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7885                    "Ignoring Zero MAC for STORAGE SD mode\n");
7886                 return 0;
7887         }
7888
7889         DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7890
7891         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7892         /* Eth MAC is set on RSS leading client (fp[0]) */
7893         return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7894                                  set, BNX2X_ETH_MAC, &ramrod_flags);
7895 }
7896
7897 int bnx2x_setup_leading(struct bnx2x *bp)
7898 {
7899         return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7900 }
7901
7902 /**
7903  * bnx2x_set_int_mode - configure interrupt mode
7904  *
7905  * @bp:         driver handle
7906  *
7907  * In case of MSI-X it will also try to enable MSI-X.
7908  */
7909 int bnx2x_set_int_mode(struct bnx2x *bp)
7910 {
7911         int rc = 0;
7912
7913         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
7914                 return -EINVAL;
7915
7916         switch (int_mode) {
7917         case BNX2X_INT_MODE_MSIX:
7918                 /* attempt to enable msix */
7919                 rc = bnx2x_enable_msix(bp);
7920
7921                 /* msix attained */
7922                 if (!rc)
7923                         return 0;
7924
7925                 /* vfs use only msix */
7926                 if (rc && IS_VF(bp))
7927                         return rc;
7928
7929                 /* failed to enable multiple MSI-X */
7930                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7931                                bp->num_queues,
7932                                1 + bp->num_cnic_queues);
7933
7934                 /* falling through... */
7935         case BNX2X_INT_MODE_MSI:
7936                 bnx2x_enable_msi(bp);
7937
7938                 /* falling through... */
7939         case BNX2X_INT_MODE_INTX:
7940                 bp->num_ethernet_queues = 1;
7941                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
7942                 BNX2X_DEV_INFO("set number of queues to 1\n");
7943                 break;
7944         default:
7945                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7946                 return -EINVAL;
7947         }
7948         return 0;
7949 }
7950
7951 /* must be called prior to any HW initializations */
7952 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7953 {
7954         if (IS_SRIOV(bp))
7955                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
7956         return L2_ILT_LINES(bp);
7957 }
7958
7959 void bnx2x_ilt_set_info(struct bnx2x *bp)
7960 {
7961         struct ilt_client_info *ilt_client;
7962         struct bnx2x_ilt *ilt = BP_ILT(bp);
7963         u16 line = 0;
7964
7965         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7966         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7967
7968         /* CDU */
7969         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7970         ilt_client->client_num = ILT_CLIENT_CDU;
7971         ilt_client->page_size = CDU_ILT_PAGE_SZ;
7972         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7973         ilt_client->start = line;
7974         line += bnx2x_cid_ilt_lines(bp);
7975
7976         if (CNIC_SUPPORT(bp))
7977                 line += CNIC_ILT_LINES;
7978         ilt_client->end = line - 1;
7979
7980         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7981            ilt_client->start,
7982            ilt_client->end,
7983            ilt_client->page_size,
7984            ilt_client->flags,
7985            ilog2(ilt_client->page_size >> 12));
7986
7987         /* QM */
7988         if (QM_INIT(bp->qm_cid_count)) {
7989                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7990                 ilt_client->client_num = ILT_CLIENT_QM;
7991                 ilt_client->page_size = QM_ILT_PAGE_SZ;
7992                 ilt_client->flags = 0;
7993                 ilt_client->start = line;
7994
7995                 /* 4 bytes for each cid */
7996                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7997                                                          QM_ILT_PAGE_SZ);
7998
7999                 ilt_client->end = line - 1;
8000
8001                 DP(NETIF_MSG_IFUP,
8002                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8003                    ilt_client->start,
8004                    ilt_client->end,
8005                    ilt_client->page_size,
8006                    ilt_client->flags,
8007                    ilog2(ilt_client->page_size >> 12));
8008
8009         }
8010
8011         if (CNIC_SUPPORT(bp)) {
8012                 /* SRC */
8013                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8014                 ilt_client->client_num = ILT_CLIENT_SRC;
8015                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8016                 ilt_client->flags = 0;
8017                 ilt_client->start = line;
8018                 line += SRC_ILT_LINES;
8019                 ilt_client->end = line - 1;
8020
8021                 DP(NETIF_MSG_IFUP,
8022                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8023                    ilt_client->start,
8024                    ilt_client->end,
8025                    ilt_client->page_size,
8026                    ilt_client->flags,
8027                    ilog2(ilt_client->page_size >> 12));
8028
8029                 /* TM */
8030                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8031                 ilt_client->client_num = ILT_CLIENT_TM;
8032                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8033                 ilt_client->flags = 0;
8034                 ilt_client->start = line;
8035                 line += TM_ILT_LINES;
8036                 ilt_client->end = line - 1;
8037
8038                 DP(NETIF_MSG_IFUP,
8039                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8040                    ilt_client->start,
8041                    ilt_client->end,
8042                    ilt_client->page_size,
8043                    ilt_client->flags,
8044                    ilog2(ilt_client->page_size >> 12));
8045         }
8046
8047         BUG_ON(line > ILT_MAX_LINES);
8048 }
8049
8050 /**
8051  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8052  *
8053  * @bp:                 driver handle
8054  * @fp:                 pointer to fastpath
8055  * @init_params:        pointer to parameters structure
8056  *
8057  * parameters configured:
8058  *      - HC configuration
8059  *      - Queue's CDU context
8060  */
8061 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8062         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8063 {
8064
8065         u8 cos;
8066         int cxt_index, cxt_offset;
8067
8068         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8069         if (!IS_FCOE_FP(fp)) {
8070                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8071                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8072
8073                 /* If HC is supporterd, enable host coalescing in the transition
8074                  * to INIT state.
8075                  */
8076                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8077                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8078
8079                 /* HC rate */
8080                 init_params->rx.hc_rate = bp->rx_ticks ?
8081                         (1000000 / bp->rx_ticks) : 0;
8082                 init_params->tx.hc_rate = bp->tx_ticks ?
8083                         (1000000 / bp->tx_ticks) : 0;
8084
8085                 /* FW SB ID */
8086                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8087                         fp->fw_sb_id;
8088
8089                 /*
8090                  * CQ index among the SB indices: FCoE clients uses the default
8091                  * SB, therefore it's different.
8092                  */
8093                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8094                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8095         }
8096
8097         /* set maximum number of COSs supported by this queue */
8098         init_params->max_cos = fp->max_cos;
8099
8100         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8101             fp->index, init_params->max_cos);
8102
8103         /* set the context pointers queue object */
8104         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8105                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8106                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8107                                 ILT_PAGE_CIDS);
8108                 init_params->cxts[cos] =
8109                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8110         }
8111 }
8112
8113 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8114                         struct bnx2x_queue_state_params *q_params,
8115                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8116                         int tx_index, bool leading)
8117 {
8118         memset(tx_only_params, 0, sizeof(*tx_only_params));
8119
8120         /* Set the command */
8121         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8122
8123         /* Set tx-only QUEUE flags: don't zero statistics */
8124         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8125
8126         /* choose the index of the cid to send the slow path on */
8127         tx_only_params->cid_index = tx_index;
8128
8129         /* Set general TX_ONLY_SETUP parameters */
8130         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8131
8132         /* Set Tx TX_ONLY_SETUP parameters */
8133         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8134
8135         DP(NETIF_MSG_IFUP,
8136            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8137            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8138            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8139            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8140
8141         /* send the ramrod */
8142         return bnx2x_queue_state_change(bp, q_params);
8143 }
8144
8145
8146 /**
8147  * bnx2x_setup_queue - setup queue
8148  *
8149  * @bp:         driver handle
8150  * @fp:         pointer to fastpath
8151  * @leading:    is leading
8152  *
8153  * This function performs 2 steps in a Queue state machine
8154  *      actually: 1) RESET->INIT 2) INIT->SETUP
8155  */
8156
8157 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8158                        bool leading)
8159 {
8160         struct bnx2x_queue_state_params q_params = {NULL};
8161         struct bnx2x_queue_setup_params *setup_params =
8162                                                 &q_params.params.setup;
8163         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8164                                                 &q_params.params.tx_only;
8165         int rc;
8166         u8 tx_index;
8167
8168         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8169
8170         /* reset IGU state skip FCoE L2 queue */
8171         if (!IS_FCOE_FP(fp))
8172                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8173                              IGU_INT_ENABLE, 0);
8174
8175         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8176         /* We want to wait for completion in this context */
8177         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8178
8179         /* Prepare the INIT parameters */
8180         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8181
8182         /* Set the command */
8183         q_params.cmd = BNX2X_Q_CMD_INIT;
8184
8185         /* Change the state to INIT */
8186         rc = bnx2x_queue_state_change(bp, &q_params);
8187         if (rc) {
8188                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8189                 return rc;
8190         }
8191
8192         DP(NETIF_MSG_IFUP, "init complete\n");
8193
8194
8195         /* Now move the Queue to the SETUP state... */
8196         memset(setup_params, 0, sizeof(*setup_params));
8197
8198         /* Set QUEUE flags */
8199         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8200
8201         /* Set general SETUP parameters */
8202         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8203                                 FIRST_TX_COS_INDEX);
8204
8205         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8206                             &setup_params->rxq_params);
8207
8208         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8209                            FIRST_TX_COS_INDEX);
8210
8211         /* Set the command */
8212         q_params.cmd = BNX2X_Q_CMD_SETUP;
8213
8214         if (IS_FCOE_FP(fp))
8215                 bp->fcoe_init = true;
8216
8217         /* Change the state to SETUP */
8218         rc = bnx2x_queue_state_change(bp, &q_params);
8219         if (rc) {
8220                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8221                 return rc;
8222         }
8223
8224         /* loop through the relevant tx-only indices */
8225         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8226               tx_index < fp->max_cos;
8227               tx_index++) {
8228
8229                 /* prepare and send tx-only ramrod*/
8230                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8231                                           tx_only_params, tx_index, leading);
8232                 if (rc) {
8233                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8234                                   fp->index, tx_index);
8235                         return rc;
8236                 }
8237         }
8238
8239         return rc;
8240 }
8241
8242 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8243 {
8244         struct bnx2x_fastpath *fp = &bp->fp[index];
8245         struct bnx2x_fp_txdata *txdata;
8246         struct bnx2x_queue_state_params q_params = {NULL};
8247         int rc, tx_index;
8248
8249         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8250
8251         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8252         /* We want to wait for completion in this context */
8253         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8254
8255
8256         /* close tx-only connections */
8257         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8258              tx_index < fp->max_cos;
8259              tx_index++){
8260
8261                 /* ascertain this is a normal queue*/
8262                 txdata = fp->txdata_ptr[tx_index];
8263
8264                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8265                                                         txdata->txq_index);
8266
8267                 /* send halt terminate on tx-only connection */
8268                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8269                 memset(&q_params.params.terminate, 0,
8270                        sizeof(q_params.params.terminate));
8271                 q_params.params.terminate.cid_index = tx_index;
8272
8273                 rc = bnx2x_queue_state_change(bp, &q_params);
8274                 if (rc)
8275                         return rc;
8276
8277                 /* send halt terminate on tx-only connection */
8278                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8279                 memset(&q_params.params.cfc_del, 0,
8280                        sizeof(q_params.params.cfc_del));
8281                 q_params.params.cfc_del.cid_index = tx_index;
8282                 rc = bnx2x_queue_state_change(bp, &q_params);
8283                 if (rc)
8284                         return rc;
8285         }
8286         /* Stop the primary connection: */
8287         /* ...halt the connection */
8288         q_params.cmd = BNX2X_Q_CMD_HALT;
8289         rc = bnx2x_queue_state_change(bp, &q_params);
8290         if (rc)
8291                 return rc;
8292
8293         /* ...terminate the connection */
8294         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8295         memset(&q_params.params.terminate, 0,
8296                sizeof(q_params.params.terminate));
8297         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8298         rc = bnx2x_queue_state_change(bp, &q_params);
8299         if (rc)
8300                 return rc;
8301         /* ...delete cfc entry */
8302         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8303         memset(&q_params.params.cfc_del, 0,
8304                sizeof(q_params.params.cfc_del));
8305         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8306         return bnx2x_queue_state_change(bp, &q_params);
8307 }
8308
8309
8310 static void bnx2x_reset_func(struct bnx2x *bp)
8311 {
8312         int port = BP_PORT(bp);
8313         int func = BP_FUNC(bp);
8314         int i;
8315
8316         /* Disable the function in the FW */
8317         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8318         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8319         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8320         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8321
8322         /* FP SBs */
8323         for_each_eth_queue(bp, i) {
8324                 struct bnx2x_fastpath *fp = &bp->fp[i];
8325                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8326                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8327                            SB_DISABLED);
8328         }
8329
8330         if (CNIC_LOADED(bp))
8331                 /* CNIC SB */
8332                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8333                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8334                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8335
8336         /* SP SB */
8337         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8338                    CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8339                    SB_DISABLED);
8340
8341         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8342                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8343                        0);
8344
8345         /* Configure IGU */
8346         if (bp->common.int_block == INT_BLOCK_HC) {
8347                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8348                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8349         } else {
8350                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8351                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8352         }
8353
8354         if (CNIC_LOADED(bp)) {
8355                 /* Disable Timer scan */
8356                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8357                 /*
8358                  * Wait for at least 10ms and up to 2 second for the timers
8359                  * scan to complete
8360                  */
8361                 for (i = 0; i < 200; i++) {
8362                         msleep(10);
8363                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8364                                 break;
8365                 }
8366         }
8367         /* Clear ILT */
8368         bnx2x_clear_func_ilt(bp, func);
8369
8370         /* Timers workaround bug for E2: if this is vnic-3,
8371          * we need to set the entire ilt range for this timers.
8372          */
8373         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8374                 struct ilt_client_info ilt_cli;
8375                 /* use dummy TM client */
8376                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8377                 ilt_cli.start = 0;
8378                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8379                 ilt_cli.client_num = ILT_CLIENT_TM;
8380
8381                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8382         }
8383
8384         /* this assumes that reset_port() called before reset_func()*/
8385         if (!CHIP_IS_E1x(bp))
8386                 bnx2x_pf_disable(bp);
8387
8388         bp->dmae_ready = 0;
8389 }
8390
8391 static void bnx2x_reset_port(struct bnx2x *bp)
8392 {
8393         int port = BP_PORT(bp);
8394         u32 val;
8395
8396         /* Reset physical Link */
8397         bnx2x__link_reset(bp);
8398
8399         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8400
8401         /* Do not rcv packets to BRB */
8402         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8403         /* Do not direct rcv packets that are not for MCP to the BRB */
8404         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8405                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8406
8407         /* Configure AEU */
8408         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8409
8410         msleep(100);
8411         /* Check for BRB port occupancy */
8412         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8413         if (val)
8414                 DP(NETIF_MSG_IFDOWN,
8415                    "BRB1 is not empty  %d blocks are occupied\n", val);
8416
8417         /* TODO: Close Doorbell port? */
8418 }
8419
8420 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8421 {
8422         struct bnx2x_func_state_params func_params = {NULL};
8423
8424         /* Prepare parameters for function state transitions */
8425         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8426
8427         func_params.f_obj = &bp->func_obj;
8428         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8429
8430         func_params.params.hw_init.load_phase = load_code;
8431
8432         return bnx2x_func_state_change(bp, &func_params);
8433 }
8434
8435 static int bnx2x_func_stop(struct bnx2x *bp)
8436 {
8437         struct bnx2x_func_state_params func_params = {NULL};
8438         int rc;
8439
8440         /* Prepare parameters for function state transitions */
8441         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8442         func_params.f_obj = &bp->func_obj;
8443         func_params.cmd = BNX2X_F_CMD_STOP;
8444
8445         /*
8446          * Try to stop the function the 'good way'. If fails (in case
8447          * of a parity error during bnx2x_chip_cleanup()) and we are
8448          * not in a debug mode, perform a state transaction in order to
8449          * enable further HW_RESET transaction.
8450          */
8451         rc = bnx2x_func_state_change(bp, &func_params);
8452         if (rc) {
8453 #ifdef BNX2X_STOP_ON_ERROR
8454                 return rc;
8455 #else
8456                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8457                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8458                 return bnx2x_func_state_change(bp, &func_params);
8459 #endif
8460         }
8461
8462         return 0;
8463 }
8464
8465 /**
8466  * bnx2x_send_unload_req - request unload mode from the MCP.
8467  *
8468  * @bp:                 driver handle
8469  * @unload_mode:        requested function's unload mode
8470  *
8471  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8472  */
8473 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8474 {
8475         u32 reset_code = 0;
8476         int port = BP_PORT(bp);
8477
8478         /* Select the UNLOAD request mode */
8479         if (unload_mode == UNLOAD_NORMAL)
8480                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8481
8482         else if (bp->flags & NO_WOL_FLAG)
8483                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8484
8485         else if (bp->wol) {
8486                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8487                 u8 *mac_addr = bp->dev->dev_addr;
8488                 u32 val;
8489                 u16 pmc;
8490
8491                 /* The mac address is written to entries 1-4 to
8492                  * preserve entry 0 which is used by the PMF
8493                  */
8494                 u8 entry = (BP_VN(bp) + 1)*8;
8495
8496                 val = (mac_addr[0] << 8) | mac_addr[1];
8497                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8498
8499                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8500                       (mac_addr[4] << 8) | mac_addr[5];
8501                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8502
8503                 /* Enable the PME and clear the status */
8504                 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8505                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8506                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8507
8508                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8509
8510         } else
8511                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8512
8513         /* Send the request to the MCP */
8514         if (!BP_NOMCP(bp))
8515                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8516         else {
8517                 int path = BP_PATH(bp);
8518
8519                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8520                    path, load_count[path][0], load_count[path][1],
8521                    load_count[path][2]);
8522                 load_count[path][0]--;
8523                 load_count[path][1 + port]--;
8524                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8525                    path, load_count[path][0], load_count[path][1],
8526                    load_count[path][2]);
8527                 if (load_count[path][0] == 0)
8528                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8529                 else if (load_count[path][1 + port] == 0)
8530                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8531                 else
8532                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8533         }
8534
8535         return reset_code;
8536 }
8537
8538 /**
8539  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8540  *
8541  * @bp:         driver handle
8542  * @keep_link:          true iff link should be kept up
8543  */
8544 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8545 {
8546         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8547
8548         /* Report UNLOAD_DONE to MCP */
8549         if (!BP_NOMCP(bp))
8550                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8551 }
8552
8553 static int bnx2x_func_wait_started(struct bnx2x *bp)
8554 {
8555         int tout = 50;
8556         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8557
8558         if (!bp->port.pmf)
8559                 return 0;
8560
8561         /*
8562          * (assumption: No Attention from MCP at this stage)
8563          * PMF probably in the middle of TXdisable/enable transaction
8564          * 1. Sync IRS for default SB
8565          * 2. Sync SP queue - this guarantes us that attention handling started
8566          * 3. Wait, that TXdisable/enable transaction completes
8567          *
8568          * 1+2 guranty that if DCBx attention was scheduled it already changed
8569          * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8570          * received complettion for the transaction the state is TX_STOPPED.
8571          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8572          * transaction.
8573          */
8574
8575         /* make sure default SB ISR is done */
8576         if (msix)
8577                 synchronize_irq(bp->msix_table[0].vector);
8578         else
8579                 synchronize_irq(bp->pdev->irq);
8580
8581         flush_workqueue(bnx2x_wq);
8582
8583         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8584                                 BNX2X_F_STATE_STARTED && tout--)
8585                 msleep(20);
8586
8587         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8588                                                 BNX2X_F_STATE_STARTED) {
8589 #ifdef BNX2X_STOP_ON_ERROR
8590                 BNX2X_ERR("Wrong function state\n");
8591                 return -EBUSY;
8592 #else
8593                 /*
8594                  * Failed to complete the transaction in a "good way"
8595                  * Force both transactions with CLR bit
8596                  */
8597                 struct bnx2x_func_state_params func_params = {NULL};
8598
8599                 DP(NETIF_MSG_IFDOWN,
8600                    "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8601
8602                 func_params.f_obj = &bp->func_obj;
8603                 __set_bit(RAMROD_DRV_CLR_ONLY,
8604                                         &func_params.ramrod_flags);
8605
8606                 /* STARTED-->TX_ST0PPED */
8607                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8608                 bnx2x_func_state_change(bp, &func_params);
8609
8610                 /* TX_ST0PPED-->STARTED */
8611                 func_params.cmd = BNX2X_F_CMD_TX_START;
8612                 return bnx2x_func_state_change(bp, &func_params);
8613 #endif
8614         }
8615
8616         return 0;
8617 }
8618
8619 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8620 {
8621         int port = BP_PORT(bp);
8622         int i, rc = 0;
8623         u8 cos;
8624         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8625         u32 reset_code;
8626
8627         /* Wait until tx fastpath tasks complete */
8628         for_each_tx_queue(bp, i) {
8629                 struct bnx2x_fastpath *fp = &bp->fp[i];
8630
8631                 for_each_cos_in_tx_queue(fp, cos)
8632                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8633 #ifdef BNX2X_STOP_ON_ERROR
8634                 if (rc)
8635                         return;
8636 #endif
8637         }
8638
8639         /* Give HW time to discard old tx messages */
8640         usleep_range(1000, 1000);
8641
8642         /* Clean all ETH MACs */
8643         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8644                                 false);
8645         if (rc < 0)
8646                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8647
8648         /* Clean up UC list  */
8649         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8650                                 true);
8651         if (rc < 0)
8652                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8653                           rc);
8654
8655         /* Disable LLH */
8656         if (!CHIP_IS_E1(bp))
8657                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8658
8659         /* Set "drop all" (stop Rx).
8660          * We need to take a netif_addr_lock() here in order to prevent
8661          * a race between the completion code and this code.
8662          */
8663         netif_addr_lock_bh(bp->dev);
8664         /* Schedule the rx_mode command */
8665         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8666                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8667         else
8668                 bnx2x_set_storm_rx_mode(bp);
8669
8670         /* Cleanup multicast configuration */
8671         rparam.mcast_obj = &bp->mcast_obj;
8672         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8673         if (rc < 0)
8674                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8675
8676         netif_addr_unlock_bh(bp->dev);
8677
8678         bnx2x_iov_chip_cleanup(bp);
8679
8680
8681         /*
8682          * Send the UNLOAD_REQUEST to the MCP. This will return if
8683          * this function should perform FUNC, PORT or COMMON HW
8684          * reset.
8685          */
8686         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8687
8688         /*
8689          * (assumption: No Attention from MCP at this stage)
8690          * PMF probably in the middle of TXdisable/enable transaction
8691          */
8692         rc = bnx2x_func_wait_started(bp);
8693         if (rc) {
8694                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8695 #ifdef BNX2X_STOP_ON_ERROR
8696                 return;
8697 #endif
8698         }
8699
8700         /* Close multi and leading connections
8701          * Completions for ramrods are collected in a synchronous way
8702          */
8703         for_each_eth_queue(bp, i)
8704                 if (bnx2x_stop_queue(bp, i))
8705 #ifdef BNX2X_STOP_ON_ERROR
8706                         return;
8707 #else
8708                         goto unload_error;
8709 #endif
8710
8711         if (CNIC_LOADED(bp)) {
8712                 for_each_cnic_queue(bp, i)
8713                         if (bnx2x_stop_queue(bp, i))
8714 #ifdef BNX2X_STOP_ON_ERROR
8715                                 return;
8716 #else
8717                                 goto unload_error;
8718 #endif
8719         }
8720
8721         /* If SP settings didn't get completed so far - something
8722          * very wrong has happen.
8723          */
8724         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8725                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8726
8727 #ifndef BNX2X_STOP_ON_ERROR
8728 unload_error:
8729 #endif
8730         rc = bnx2x_func_stop(bp);
8731         if (rc) {
8732                 BNX2X_ERR("Function stop failed!\n");
8733 #ifdef BNX2X_STOP_ON_ERROR
8734                 return;
8735 #endif
8736         }
8737
8738         /* Disable HW interrupts, NAPI */
8739         bnx2x_netif_stop(bp, 1);
8740         /* Delete all NAPI objects */
8741         bnx2x_del_all_napi(bp);
8742         if (CNIC_LOADED(bp))
8743                 bnx2x_del_all_napi_cnic(bp);
8744
8745         /* Release IRQs */
8746         bnx2x_free_irq(bp);
8747
8748         /* Reset the chip */
8749         rc = bnx2x_reset_hw(bp, reset_code);
8750         if (rc)
8751                 BNX2X_ERR("HW_RESET failed\n");
8752
8753
8754         /* Report UNLOAD_DONE to MCP */
8755         bnx2x_send_unload_done(bp, keep_link);
8756 }
8757
8758 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8759 {
8760         u32 val;
8761
8762         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8763
8764         if (CHIP_IS_E1(bp)) {
8765                 int port = BP_PORT(bp);
8766                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8767                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8768
8769                 val = REG_RD(bp, addr);
8770                 val &= ~(0x300);
8771                 REG_WR(bp, addr, val);
8772         } else {
8773                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8774                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8775                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8776                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8777         }
8778 }
8779
8780 /* Close gates #2, #3 and #4: */
8781 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8782 {
8783         u32 val;
8784
8785         /* Gates #2 and #4a are closed/opened for "not E1" only */
8786         if (!CHIP_IS_E1(bp)) {
8787                 /* #4 */
8788                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8789                 /* #2 */
8790                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8791         }
8792
8793         /* #3 */
8794         if (CHIP_IS_E1x(bp)) {
8795                 /* Prevent interrupts from HC on both ports */
8796                 val = REG_RD(bp, HC_REG_CONFIG_1);
8797                 REG_WR(bp, HC_REG_CONFIG_1,
8798                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8799                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8800
8801                 val = REG_RD(bp, HC_REG_CONFIG_0);
8802                 REG_WR(bp, HC_REG_CONFIG_0,
8803                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8804                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8805         } else {
8806                 /* Prevent incomming interrupts in IGU */
8807                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8808
8809                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8810                        (!close) ?
8811                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8812                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8813         }
8814
8815         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8816                 close ? "closing" : "opening");
8817         mmiowb();
8818 }
8819
8820 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
8821
8822 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8823 {
8824         /* Do some magic... */
8825         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8826         *magic_val = val & SHARED_MF_CLP_MAGIC;
8827         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8828 }
8829
8830 /**
8831  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8832  *
8833  * @bp:         driver handle
8834  * @magic_val:  old value of the `magic' bit.
8835  */
8836 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8837 {
8838         /* Restore the `magic' bit value... */
8839         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8840         MF_CFG_WR(bp, shared_mf_config.clp_mb,
8841                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8842 }
8843
8844 /**
8845  * bnx2x_reset_mcp_prep - prepare for MCP reset.
8846  *
8847  * @bp:         driver handle
8848  * @magic_val:  old value of 'magic' bit.
8849  *
8850  * Takes care of CLP configurations.
8851  */
8852 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8853 {
8854         u32 shmem;
8855         u32 validity_offset;
8856
8857         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8858
8859         /* Set `magic' bit in order to save MF config */
8860         if (!CHIP_IS_E1(bp))
8861                 bnx2x_clp_reset_prep(bp, magic_val);
8862
8863         /* Get shmem offset */
8864         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8865         validity_offset =
8866                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
8867
8868         /* Clear validity map flags */
8869         if (shmem > 0)
8870                 REG_WR(bp, shmem + validity_offset, 0);
8871 }
8872
8873 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
8874 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
8875
8876 /**
8877  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8878  *
8879  * @bp: driver handle
8880  */
8881 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8882 {
8883         /* special handling for emulation and FPGA,
8884            wait 10 times longer */
8885         if (CHIP_REV_IS_SLOW(bp))
8886                 msleep(MCP_ONE_TIMEOUT*10);
8887         else
8888                 msleep(MCP_ONE_TIMEOUT);
8889 }
8890
8891 /*
8892  * initializes bp->common.shmem_base and waits for validity signature to appear
8893  */
8894 static int bnx2x_init_shmem(struct bnx2x *bp)
8895 {
8896         int cnt = 0;
8897         u32 val = 0;
8898
8899         do {
8900                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8901                 if (bp->common.shmem_base) {
8902                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8903                         if (val & SHR_MEM_VALIDITY_MB)
8904                                 return 0;
8905                 }
8906
8907                 bnx2x_mcp_wait_one(bp);
8908
8909         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8910
8911         BNX2X_ERR("BAD MCP validity signature\n");
8912
8913         return -ENODEV;
8914 }
8915
8916 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8917 {
8918         int rc = bnx2x_init_shmem(bp);
8919
8920         /* Restore the `magic' bit value */
8921         if (!CHIP_IS_E1(bp))
8922                 bnx2x_clp_reset_done(bp, magic_val);
8923
8924         return rc;
8925 }
8926
8927 static void bnx2x_pxp_prep(struct bnx2x *bp)
8928 {
8929         if (!CHIP_IS_E1(bp)) {
8930                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8931                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8932                 mmiowb();
8933         }
8934 }
8935
8936 /*
8937  * Reset the whole chip except for:
8938  *      - PCIE core
8939  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8940  *              one reset bit)
8941  *      - IGU
8942  *      - MISC (including AEU)
8943  *      - GRC
8944  *      - RBCN, RBCP
8945  */
8946 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8947 {
8948         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8949         u32 global_bits2, stay_reset2;
8950
8951         /*
8952          * Bits that have to be set in reset_mask2 if we want to reset 'global'
8953          * (per chip) blocks.
8954          */
8955         global_bits2 =
8956                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8957                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8958
8959         /* Don't reset the following blocks.
8960          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
8961          *            reset, as in 4 port device they might still be owned
8962          *            by the MCP (there is only one leader per path).
8963          */
8964         not_reset_mask1 =
8965                 MISC_REGISTERS_RESET_REG_1_RST_HC |
8966                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8967                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8968
8969         not_reset_mask2 =
8970                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8971                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8972                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8973                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8974                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8975                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
8976                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8977                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8978                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8979                 MISC_REGISTERS_RESET_REG_2_PGLC |
8980                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8981                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8982                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8983                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8984                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8985                 MISC_REGISTERS_RESET_REG_2_UMAC1;
8986
8987         /*
8988          * Keep the following blocks in reset:
8989          *  - all xxMACs are handled by the bnx2x_link code.
8990          */
8991         stay_reset2 =
8992                 MISC_REGISTERS_RESET_REG_2_XMAC |
8993                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8994
8995         /* Full reset masks according to the chip */
8996         reset_mask1 = 0xffffffff;
8997
8998         if (CHIP_IS_E1(bp))
8999                 reset_mask2 = 0xffff;
9000         else if (CHIP_IS_E1H(bp))
9001                 reset_mask2 = 0x1ffff;
9002         else if (CHIP_IS_E2(bp))
9003                 reset_mask2 = 0xfffff;
9004         else /* CHIP_IS_E3 */
9005                 reset_mask2 = 0x3ffffff;
9006
9007         /* Don't reset global blocks unless we need to */
9008         if (!global)
9009                 reset_mask2 &= ~global_bits2;
9010
9011         /*
9012          * In case of attention in the QM, we need to reset PXP
9013          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9014          * because otherwise QM reset would release 'close the gates' shortly
9015          * before resetting the PXP, then the PSWRQ would send a write
9016          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9017          * read the payload data from PSWWR, but PSWWR would not
9018          * respond. The write queue in PGLUE would stuck, dmae commands
9019          * would not return. Therefore it's important to reset the second
9020          * reset register (containing the
9021          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9022          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9023          * bit).
9024          */
9025         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9026                reset_mask2 & (~not_reset_mask2));
9027
9028         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9029                reset_mask1 & (~not_reset_mask1));
9030
9031         barrier();
9032         mmiowb();
9033
9034         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9035                reset_mask2 & (~stay_reset2));
9036
9037         barrier();
9038         mmiowb();
9039
9040         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9041         mmiowb();
9042 }
9043
9044 /**
9045  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9046  * It should get cleared in no more than 1s.
9047  *
9048  * @bp: driver handle
9049  *
9050  * It should get cleared in no more than 1s. Returns 0 if
9051  * pending writes bit gets cleared.
9052  */
9053 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9054 {
9055         u32 cnt = 1000;
9056         u32 pend_bits = 0;
9057
9058         do {
9059                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9060
9061                 if (pend_bits == 0)
9062                         break;
9063
9064                 usleep_range(1000, 1000);
9065         } while (cnt-- > 0);
9066
9067         if (cnt <= 0) {
9068                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9069                           pend_bits);
9070                 return -EBUSY;
9071         }
9072
9073         return 0;
9074 }
9075
9076 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9077 {
9078         int cnt = 1000;
9079         u32 val = 0;
9080         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9081                 u32 tags_63_32 = 0;
9082
9083
9084         /* Empty the Tetris buffer, wait for 1s */
9085         do {
9086                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9087                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9088                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9089                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9090                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9091                 if (CHIP_IS_E3(bp))
9092                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9093
9094                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9095                     ((port_is_idle_0 & 0x1) == 0x1) &&
9096                     ((port_is_idle_1 & 0x1) == 0x1) &&
9097                     (pgl_exp_rom2 == 0xffffffff) &&
9098                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9099                         break;
9100                 usleep_range(1000, 1000);
9101         } while (cnt-- > 0);
9102
9103         if (cnt <= 0) {
9104                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9105                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9106                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9107                           pgl_exp_rom2);
9108                 return -EAGAIN;
9109         }
9110
9111         barrier();
9112
9113         /* Close gates #2, #3 and #4 */
9114         bnx2x_set_234_gates(bp, true);
9115
9116         /* Poll for IGU VQs for 57712 and newer chips */
9117         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9118                 return -EAGAIN;
9119
9120
9121         /* TBD: Indicate that "process kill" is in progress to MCP */
9122
9123         /* Clear "unprepared" bit */
9124         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9125         barrier();
9126
9127         /* Make sure all is written to the chip before the reset */
9128         mmiowb();
9129
9130         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9131          * PSWHST, GRC and PSWRD Tetris buffer.
9132          */
9133         usleep_range(1000, 1000);
9134
9135         /* Prepare to chip reset: */
9136         /* MCP */
9137         if (global)
9138                 bnx2x_reset_mcp_prep(bp, &val);
9139
9140         /* PXP */
9141         bnx2x_pxp_prep(bp);
9142         barrier();
9143
9144         /* reset the chip */
9145         bnx2x_process_kill_chip_reset(bp, global);
9146         barrier();
9147
9148         /* Recover after reset: */
9149         /* MCP */
9150         if (global && bnx2x_reset_mcp_comp(bp, val))
9151                 return -EAGAIN;
9152
9153         /* TBD: Add resetting the NO_MCP mode DB here */
9154
9155         /* Open the gates #2, #3 and #4 */
9156         bnx2x_set_234_gates(bp, false);
9157
9158         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9159          * reset state, re-enable attentions. */
9160
9161         return 0;
9162 }
9163
9164 static int bnx2x_leader_reset(struct bnx2x *bp)
9165 {
9166         int rc = 0;
9167         bool global = bnx2x_reset_is_global(bp);
9168         u32 load_code;
9169
9170         /* if not going to reset MCP - load "fake" driver to reset HW while
9171          * driver is owner of the HW
9172          */
9173         if (!global && !BP_NOMCP(bp)) {
9174                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9175                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9176                 if (!load_code) {
9177                         BNX2X_ERR("MCP response failure, aborting\n");
9178                         rc = -EAGAIN;
9179                         goto exit_leader_reset;
9180                 }
9181                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9182                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9183                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9184                         rc = -EAGAIN;
9185                         goto exit_leader_reset2;
9186                 }
9187                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9188                 if (!load_code) {
9189                         BNX2X_ERR("MCP response failure, aborting\n");
9190                         rc = -EAGAIN;
9191                         goto exit_leader_reset2;
9192                 }
9193         }
9194
9195         /* Try to recover after the failure */
9196         if (bnx2x_process_kill(bp, global)) {
9197                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9198                           BP_PATH(bp));
9199                 rc = -EAGAIN;
9200                 goto exit_leader_reset2;
9201         }
9202
9203         /*
9204          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9205          * state.
9206          */
9207         bnx2x_set_reset_done(bp);
9208         if (global)
9209                 bnx2x_clear_reset_global(bp);
9210
9211 exit_leader_reset2:
9212         /* unload "fake driver" if it was loaded */
9213         if (!global && !BP_NOMCP(bp)) {
9214                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9215                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9216         }
9217 exit_leader_reset:
9218         bp->is_leader = 0;
9219         bnx2x_release_leader_lock(bp);
9220         smp_mb();
9221         return rc;
9222 }
9223
9224 static void bnx2x_recovery_failed(struct bnx2x *bp)
9225 {
9226         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9227
9228         /* Disconnect this device */
9229         netif_device_detach(bp->dev);
9230
9231         /*
9232          * Block ifup for all function on this engine until "process kill"
9233          * or power cycle.
9234          */
9235         bnx2x_set_reset_in_progress(bp);
9236
9237         /* Shut down the power */
9238         bnx2x_set_power_state(bp, PCI_D3hot);
9239
9240         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9241
9242         smp_mb();
9243 }
9244
9245 /*
9246  * Assumption: runs under rtnl lock. This together with the fact
9247  * that it's called only from bnx2x_sp_rtnl() ensure that it
9248  * will never be called when netif_running(bp->dev) is false.
9249  */
9250 static void bnx2x_parity_recover(struct bnx2x *bp)
9251 {
9252         bool global = false;
9253         u32 error_recovered, error_unrecovered;
9254         bool is_parity;
9255
9256         DP(NETIF_MSG_HW, "Handling parity\n");
9257         while (1) {
9258                 switch (bp->recovery_state) {
9259                 case BNX2X_RECOVERY_INIT:
9260                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9261                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9262                         WARN_ON(!is_parity);
9263
9264                         /* Try to get a LEADER_LOCK HW lock */
9265                         if (bnx2x_trylock_leader_lock(bp)) {
9266                                 bnx2x_set_reset_in_progress(bp);
9267                                 /*
9268                                  * Check if there is a global attention and if
9269                                  * there was a global attention, set the global
9270                                  * reset bit.
9271                                  */
9272
9273                                 if (global)
9274                                         bnx2x_set_reset_global(bp);
9275
9276                                 bp->is_leader = 1;
9277                         }
9278
9279                         /* Stop the driver */
9280                         /* If interface has been removed - break */
9281                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9282                                 return;
9283
9284                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9285
9286                         /* Ensure "is_leader", MCP command sequence and
9287                          * "recovery_state" update values are seen on other
9288                          * CPUs.
9289                          */
9290                         smp_mb();
9291                         break;
9292
9293                 case BNX2X_RECOVERY_WAIT:
9294                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9295                         if (bp->is_leader) {
9296                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9297                                 bool other_load_status =
9298                                         bnx2x_get_load_status(bp, other_engine);
9299                                 bool load_status =
9300                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9301                                 global = bnx2x_reset_is_global(bp);
9302
9303                                 /*
9304                                  * In case of a parity in a global block, let
9305                                  * the first leader that performs a
9306                                  * leader_reset() reset the global blocks in
9307                                  * order to clear global attentions. Otherwise
9308                                  * the the gates will remain closed for that
9309                                  * engine.
9310                                  */
9311                                 if (load_status ||
9312                                     (global && other_load_status)) {
9313                                         /* Wait until all other functions get
9314                                          * down.
9315                                          */
9316                                         schedule_delayed_work(&bp->sp_rtnl_task,
9317                                                                 HZ/10);
9318                                         return;
9319                                 } else {
9320                                         /* If all other functions got down -
9321                                          * try to bring the chip back to
9322                                          * normal. In any case it's an exit
9323                                          * point for a leader.
9324                                          */
9325                                         if (bnx2x_leader_reset(bp)) {
9326                                                 bnx2x_recovery_failed(bp);
9327                                                 return;
9328                                         }
9329
9330                                         /* If we are here, means that the
9331                                          * leader has succeeded and doesn't
9332                                          * want to be a leader any more. Try
9333                                          * to continue as a none-leader.
9334                                          */
9335                                         break;
9336                                 }
9337                         } else { /* non-leader */
9338                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9339                                         /* Try to get a LEADER_LOCK HW lock as
9340                                          * long as a former leader may have
9341                                          * been unloaded by the user or
9342                                          * released a leadership by another
9343                                          * reason.
9344                                          */
9345                                         if (bnx2x_trylock_leader_lock(bp)) {
9346                                                 /* I'm a leader now! Restart a
9347                                                  * switch case.
9348                                                  */
9349                                                 bp->is_leader = 1;
9350                                                 break;
9351                                         }
9352
9353                                         schedule_delayed_work(&bp->sp_rtnl_task,
9354                                                                 HZ/10);
9355                                         return;
9356
9357                                 } else {
9358                                         /*
9359                                          * If there was a global attention, wait
9360                                          * for it to be cleared.
9361                                          */
9362                                         if (bnx2x_reset_is_global(bp)) {
9363                                                 schedule_delayed_work(
9364                                                         &bp->sp_rtnl_task,
9365                                                         HZ/10);
9366                                                 return;
9367                                         }
9368
9369                                         error_recovered =
9370                                           bp->eth_stats.recoverable_error;
9371                                         error_unrecovered =
9372                                           bp->eth_stats.unrecoverable_error;
9373                                         bp->recovery_state =
9374                                                 BNX2X_RECOVERY_NIC_LOADING;
9375                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9376                                                 error_unrecovered++;
9377                                                 netdev_err(bp->dev,
9378                                                            "Recovery failed. Power cycle needed\n");
9379                                                 /* Disconnect this device */
9380                                                 netif_device_detach(bp->dev);
9381                                                 /* Shut down the power */
9382                                                 bnx2x_set_power_state(
9383                                                         bp, PCI_D3hot);
9384                                                 smp_mb();
9385                                         } else {
9386                                                 bp->recovery_state =
9387                                                         BNX2X_RECOVERY_DONE;
9388                                                 error_recovered++;
9389                                                 smp_mb();
9390                                         }
9391                                         bp->eth_stats.recoverable_error =
9392                                                 error_recovered;
9393                                         bp->eth_stats.unrecoverable_error =
9394                                                 error_unrecovered;
9395
9396                                         return;
9397                                 }
9398                         }
9399                 default:
9400                         return;
9401                 }
9402         }
9403 }
9404
9405 static int bnx2x_close(struct net_device *dev);
9406
9407 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9408  * scheduled on a general queue in order to prevent a dead lock.
9409  */
9410 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9411 {
9412         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9413
9414         rtnl_lock();
9415
9416         if (!netif_running(bp->dev)) {
9417                 rtnl_unlock();
9418                 return;
9419         }
9420
9421         /* if stop on error is defined no recovery flows should be executed */
9422 #ifdef BNX2X_STOP_ON_ERROR
9423         BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9424                   "you will need to reboot when done\n");
9425         goto sp_rtnl_not_reset;
9426 #endif
9427
9428         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9429                 /*
9430                  * Clear all pending SP commands as we are going to reset the
9431                  * function anyway.
9432                  */
9433                 bp->sp_rtnl_state = 0;
9434                 smp_mb();
9435
9436                 bnx2x_parity_recover(bp);
9437
9438                 rtnl_unlock();
9439                 return;
9440         }
9441
9442         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9443                 /*
9444                  * Clear all pending SP commands as we are going to reset the
9445                  * function anyway.
9446                  */
9447                 bp->sp_rtnl_state = 0;
9448                 smp_mb();
9449
9450                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9451                 bnx2x_nic_load(bp, LOAD_NORMAL);
9452
9453                 rtnl_unlock();
9454                 return;
9455         }
9456 #ifdef BNX2X_STOP_ON_ERROR
9457 sp_rtnl_not_reset:
9458 #endif
9459         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9460                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9461         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9462                 bnx2x_after_function_update(bp);
9463         /*
9464          * in case of fan failure we need to reset id if the "stop on error"
9465          * debug flag is set, since we trying to prevent permanent overheating
9466          * damage
9467          */
9468         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9469                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9470                 netif_device_detach(bp->dev);
9471                 bnx2x_close(bp->dev);
9472                 rtnl_unlock();
9473                 return;
9474         }
9475
9476         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9477                 DP(BNX2X_MSG_SP,
9478                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9479                 bnx2x_vfpf_set_mcast(bp->dev);
9480         }
9481
9482         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9483                                &bp->sp_rtnl_state)) {
9484                 DP(BNX2X_MSG_SP,
9485                    "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9486                 bnx2x_vfpf_storm_rx_mode(bp);
9487         }
9488
9489         /* work which needs rtnl lock not-taken (as it takes the lock itself and
9490          * can be called from other contexts as well)
9491          */
9492         rtnl_unlock();
9493
9494         /* enable SR-IOV if applicable */
9495         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9496                                                &bp->sp_rtnl_state))
9497                 bnx2x_enable_sriov(bp);
9498 }
9499
9500 static void bnx2x_period_task(struct work_struct *work)
9501 {
9502         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9503
9504         if (!netif_running(bp->dev))
9505                 goto period_task_exit;
9506
9507         if (CHIP_REV_IS_SLOW(bp)) {
9508                 BNX2X_ERR("period task called on emulation, ignoring\n");
9509                 goto period_task_exit;
9510         }
9511
9512         bnx2x_acquire_phy_lock(bp);
9513         /*
9514          * The barrier is needed to ensure the ordering between the writing to
9515          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9516          * the reading here.
9517          */
9518         smp_mb();
9519         if (bp->port.pmf) {
9520                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9521
9522                 /* Re-queue task in 1 sec */
9523                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9524         }
9525
9526         bnx2x_release_phy_lock(bp);
9527 period_task_exit:
9528         return;
9529 }
9530
9531 /*
9532  * Init service functions
9533  */
9534
9535 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9536 {
9537         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9538         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9539         return base + (BP_ABS_FUNC(bp)) * stride;
9540 }
9541
9542 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9543 {
9544         u32 reg = bnx2x_get_pretend_reg(bp);
9545
9546         /* Flush all outstanding writes */
9547         mmiowb();
9548
9549         /* Pretend to be function 0 */
9550         REG_WR(bp, reg, 0);
9551         REG_RD(bp, reg);        /* Flush the GRC transaction (in the chip) */
9552
9553         /* From now we are in the "like-E1" mode */
9554         bnx2x_int_disable(bp);
9555
9556         /* Flush all outstanding writes */
9557         mmiowb();
9558
9559         /* Restore the original function */
9560         REG_WR(bp, reg, BP_ABS_FUNC(bp));
9561         REG_RD(bp, reg);
9562 }
9563
9564 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9565 {
9566         if (CHIP_IS_E1(bp))
9567                 bnx2x_int_disable(bp);
9568         else
9569                 bnx2x_undi_int_disable_e1h(bp);
9570 }
9571
9572 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9573                                         struct bnx2x_mac_vals *vals)
9574 {
9575         u32 val, base_addr, offset, mask, reset_reg;
9576         bool mac_stopped = false;
9577         u8 port = BP_PORT(bp);
9578
9579         /* reset addresses as they also mark which values were changed */
9580         vals->bmac_addr = 0;
9581         vals->umac_addr = 0;
9582         vals->xmac_addr = 0;
9583         vals->emac_addr = 0;
9584
9585         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9586
9587         if (!CHIP_IS_E3(bp)) {
9588                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9589                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9590                 if ((mask & reset_reg) && val) {
9591                         u32 wb_data[2];
9592                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9593                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9594                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9595                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9596                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9597
9598                         /*
9599                          * use rd/wr since we cannot use dmae. This is safe
9600                          * since MCP won't access the bus due to the request
9601                          * to unload, and no function on the path can be
9602                          * loaded at this time.
9603                          */
9604                         wb_data[0] = REG_RD(bp, base_addr + offset);
9605                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9606                         vals->bmac_addr = base_addr + offset;
9607                         vals->bmac_val[0] = wb_data[0];
9608                         vals->bmac_val[1] = wb_data[1];
9609                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9610                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
9611                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9612
9613                 }
9614                 BNX2X_DEV_INFO("Disable emac Rx\n");
9615                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9616                 vals->emac_val = REG_RD(bp, vals->emac_addr);
9617                 REG_WR(bp, vals->emac_addr, 0);
9618                 mac_stopped = true;
9619         } else {
9620                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9621                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9622                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9623                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9624                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9625                                val & ~(1 << 1));
9626                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9627                                val | (1 << 1));
9628                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9629                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9630                         REG_WR(bp, vals->xmac_addr, 0);
9631                         mac_stopped = true;
9632                 }
9633                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9634                 if (mask & reset_reg) {
9635                         BNX2X_DEV_INFO("Disable umac Rx\n");
9636                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9637                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9638                         vals->umac_val = REG_RD(bp, vals->umac_addr);
9639                         REG_WR(bp, vals->umac_addr, 0);
9640                         mac_stopped = true;
9641                 }
9642         }
9643
9644         if (mac_stopped)
9645                 msleep(20);
9646
9647 }
9648
9649 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9650 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9651 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9652 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9653
9654 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9655 {
9656         u16 rcq, bd;
9657         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9658
9659         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9660         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9661
9662         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9663         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9664
9665         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9666                        port, bd, rcq);
9667 }
9668
9669 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9670 {
9671         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9672                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9673         if (!rc) {
9674                 BNX2X_ERR("MCP response failure, aborting\n");
9675                 return -EBUSY;
9676         }
9677
9678         return 0;
9679 }
9680
9681 static struct bnx2x_prev_path_list *
9682                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9683 {
9684         struct bnx2x_prev_path_list *tmp_list;
9685
9686         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9687                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9688                     bp->pdev->bus->number == tmp_list->bus &&
9689                     BP_PATH(bp) == tmp_list->path)
9690                         return tmp_list;
9691
9692         return NULL;
9693 }
9694
9695 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9696 {
9697         struct bnx2x_prev_path_list *tmp_list;
9698         int rc = false;
9699
9700         if (down_trylock(&bnx2x_prev_sem))
9701                 return false;
9702
9703         list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9704                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9705                     bp->pdev->bus->number == tmp_list->bus &&
9706                     BP_PATH(bp) == tmp_list->path) {
9707                         rc = true;
9708                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9709                                        BP_PATH(bp));
9710                         break;
9711                 }
9712         }
9713
9714         up(&bnx2x_prev_sem);
9715
9716         return rc;
9717 }
9718
9719 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9720 {
9721         struct bnx2x_prev_path_list *tmp_list;
9722         int rc;
9723
9724         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9725         if (!tmp_list) {
9726                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9727                 return -ENOMEM;
9728         }
9729
9730         tmp_list->bus = bp->pdev->bus->number;
9731         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9732         tmp_list->path = BP_PATH(bp);
9733         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9734
9735         rc = down_interruptible(&bnx2x_prev_sem);
9736         if (rc) {
9737                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9738                 kfree(tmp_list);
9739         } else {
9740                 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9741                                 BP_PATH(bp));
9742                 list_add(&tmp_list->list, &bnx2x_prev_list);
9743                 up(&bnx2x_prev_sem);
9744         }
9745
9746         return rc;
9747 }
9748
9749 static int bnx2x_do_flr(struct bnx2x *bp)
9750 {
9751         int i;
9752         u16 status;
9753         struct pci_dev *dev = bp->pdev;
9754
9755
9756         if (CHIP_IS_E1x(bp)) {
9757                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9758                 return -EINVAL;
9759         }
9760
9761         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9762         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9763                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9764                           bp->common.bc_ver);
9765                 return -EINVAL;
9766         }
9767
9768         /* Wait for Transaction Pending bit clean */
9769         for (i = 0; i < 4; i++) {
9770                 if (i)
9771                         msleep((1 << (i - 1)) * 100);
9772
9773                 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9774                 if (!(status & PCI_EXP_DEVSTA_TRPND))
9775                         goto clear;
9776         }
9777
9778         dev_err(&dev->dev,
9779                 "transaction is not cleared; proceeding with reset anyway\n");
9780
9781 clear:
9782
9783         BNX2X_DEV_INFO("Initiating FLR\n");
9784         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9785
9786         return 0;
9787 }
9788
9789 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9790 {
9791         int rc;
9792
9793         BNX2X_DEV_INFO("Uncommon unload Flow\n");
9794
9795         /* Test if previous unload process was already finished for this path */
9796         if (bnx2x_prev_is_path_marked(bp))
9797                 return bnx2x_prev_mcp_done(bp);
9798
9799         /* If function has FLR capabilities, and existing FW version matches
9800          * the one required, then FLR will be sufficient to clean any residue
9801          * left by previous driver
9802          */
9803         rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9804
9805         if (!rc) {
9806                 /* fw version is good */
9807                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9808                 rc = bnx2x_do_flr(bp);
9809         }
9810
9811         if (!rc) {
9812                 /* FLR was performed */
9813                 BNX2X_DEV_INFO("FLR successful\n");
9814                 return 0;
9815         }
9816
9817         BNX2X_DEV_INFO("Could not FLR\n");
9818
9819         /* Close the MCP request, return failure*/
9820         rc = bnx2x_prev_mcp_done(bp);
9821         if (!rc)
9822                 rc = BNX2X_PREV_WAIT_NEEDED;
9823
9824         return rc;
9825 }
9826
9827 static int bnx2x_prev_unload_common(struct bnx2x *bp)
9828 {
9829         u32 reset_reg, tmp_reg = 0, rc;
9830         bool prev_undi = false;
9831         struct bnx2x_mac_vals mac_vals;
9832
9833         /* It is possible a previous function received 'common' answer,
9834          * but hasn't loaded yet, therefore creating a scenario of
9835          * multiple functions receiving 'common' on the same path.
9836          */
9837         BNX2X_DEV_INFO("Common unload Flow\n");
9838
9839         memset(&mac_vals, 0, sizeof(mac_vals));
9840
9841         if (bnx2x_prev_is_path_marked(bp))
9842                 return bnx2x_prev_mcp_done(bp);
9843
9844         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9845
9846         /* Reset should be performed after BRB is emptied */
9847         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9848                 u32 timer_count = 1000;
9849
9850                 /* Close the MAC Rx to prevent BRB from filling up */
9851                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
9852
9853                 /* close LLH filters towards the BRB */
9854                 bnx2x_set_rx_filter(&bp->link_params, 0);
9855
9856                 /* Check if the UNDI driver was previously loaded
9857                  * UNDI driver initializes CID offset for normal bell to 0x7
9858                  */
9859                 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9860                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9861                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9862                         if (tmp_reg == 0x7) {
9863                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
9864                                 prev_undi = true;
9865                                 /* clear the UNDI indication */
9866                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9867                                 /* clear possible idle check errors */
9868                                 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
9869                         }
9870                 }
9871                 /* wait until BRB is empty */
9872                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9873                 while (timer_count) {
9874                         u32 prev_brb = tmp_reg;
9875
9876                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9877                         if (!tmp_reg)
9878                                 break;
9879
9880                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9881
9882                         /* reset timer as long as BRB actually gets emptied */
9883                         if (prev_brb > tmp_reg)
9884                                 timer_count = 1000;
9885                         else
9886                                 timer_count--;
9887
9888                         /* If UNDI resides in memory, manually increment it */
9889                         if (prev_undi)
9890                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9891
9892                         udelay(10);
9893                 }
9894
9895                 if (!timer_count)
9896                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9897
9898         }
9899
9900         /* No packets are in the pipeline, path is ready for reset */
9901         bnx2x_reset_common(bp);
9902
9903         if (mac_vals.xmac_addr)
9904                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
9905         if (mac_vals.umac_addr)
9906                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
9907         if (mac_vals.emac_addr)
9908                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
9909         if (mac_vals.bmac_addr) {
9910                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9911                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9912         }
9913
9914         rc = bnx2x_prev_mark_path(bp, prev_undi);
9915         if (rc) {
9916                 bnx2x_prev_mcp_done(bp);
9917                 return rc;
9918         }
9919
9920         return bnx2x_prev_mcp_done(bp);
9921 }
9922
9923 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9924  * and boot began, or when kdump kernel was loaded. Either case would invalidate
9925  * the addresses of the transaction, resulting in was-error bit set in the pci
9926  * causing all hw-to-host pcie transactions to timeout. If this happened we want
9927  * to clear the interrupt which detected this from the pglueb and the was done
9928  * bit
9929  */
9930 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9931 {
9932         if (!CHIP_IS_E1x(bp)) {
9933                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9934                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9935                         BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9936                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9937                                1 << BP_FUNC(bp));
9938                 }
9939         }
9940 }
9941
9942 static int bnx2x_prev_unload(struct bnx2x *bp)
9943 {
9944         int time_counter = 10;
9945         u32 rc, fw, hw_lock_reg, hw_lock_val;
9946         struct bnx2x_prev_path_list *prev_list;
9947         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9948
9949         /* clear hw from errors which may have resulted from an interrupted
9950          * dmae transaction.
9951          */
9952         bnx2x_prev_interrupted_dmae(bp);
9953
9954         /* Release previously held locks */
9955         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9956                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9957                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9958
9959         hw_lock_val = (REG_RD(bp, hw_lock_reg));
9960         if (hw_lock_val) {
9961                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9962                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9963                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9964                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9965                 }
9966
9967                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9968                 REG_WR(bp, hw_lock_reg, 0xffffffff);
9969         } else
9970                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9971
9972         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9973                 BNX2X_DEV_INFO("Release previously held alr\n");
9974                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9975         }
9976
9977
9978         do {
9979                 /* Lock MCP using an unload request */
9980                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9981                 if (!fw) {
9982                         BNX2X_ERR("MCP response failure, aborting\n");
9983                         rc = -EBUSY;
9984                         break;
9985                 }
9986
9987                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9988                         rc = bnx2x_prev_unload_common(bp);
9989                         break;
9990                 }
9991
9992                 /* non-common reply from MCP night require looping */
9993                 rc = bnx2x_prev_unload_uncommon(bp);
9994                 if (rc != BNX2X_PREV_WAIT_NEEDED)
9995                         break;
9996
9997                 msleep(20);
9998         } while (--time_counter);
9999
10000         if (!time_counter || rc) {
10001                 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10002                 rc = -EBUSY;
10003         }
10004
10005         /* Mark function if its port was used to boot from SAN */
10006         prev_list = bnx2x_prev_path_get_entry(bp);
10007         if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
10008                 bp->link_params.feature_config_flags |=
10009                         FEATURE_CONFIG_BOOT_FROM_SAN;
10010
10011         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10012
10013         return rc;
10014 }
10015
10016 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10017 {
10018         u32 val, val2, val3, val4, id, boot_mode;
10019         u16 pmc;
10020
10021         /* Get the chip revision id and number. */
10022         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10023         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10024         id = ((val & 0xffff) << 16);
10025         val = REG_RD(bp, MISC_REG_CHIP_REV);
10026         id |= ((val & 0xf) << 12);
10027         val = REG_RD(bp, MISC_REG_CHIP_METAL);
10028         id |= ((val & 0xff) << 4);
10029         val = REG_RD(bp, MISC_REG_BOND_ID);
10030         id |= (val & 0xf);
10031         bp->common.chip_id = id;
10032
10033         /* force 57811 according to MISC register */
10034         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10035                 if (CHIP_IS_57810(bp))
10036                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10037                                 (bp->common.chip_id & 0x0000FFFF);
10038                 else if (CHIP_IS_57810_MF(bp))
10039                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10040                                 (bp->common.chip_id & 0x0000FFFF);
10041                 bp->common.chip_id |= 0x1;
10042         }
10043
10044         /* Set doorbell size */
10045         bp->db_size = (1 << BNX2X_DB_SHIFT);
10046
10047         if (!CHIP_IS_E1x(bp)) {
10048                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10049                 if ((val & 1) == 0)
10050                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10051                 else
10052                         val = (val >> 1) & 1;
10053                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10054                                                        "2_PORT_MODE");
10055                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10056                                                  CHIP_2_PORT_MODE;
10057
10058                 if (CHIP_MODE_IS_4_PORT(bp))
10059                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10060                 else
10061                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10062         } else {
10063                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10064                 bp->pfid = bp->pf_num;                  /* 0..7 */
10065         }
10066
10067         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10068
10069         bp->link_params.chip_id = bp->common.chip_id;
10070         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10071
10072         val = (REG_RD(bp, 0x2874) & 0x55);
10073         if ((bp->common.chip_id & 0x1) ||
10074             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10075                 bp->flags |= ONE_PORT_FLAG;
10076                 BNX2X_DEV_INFO("single port device\n");
10077         }
10078
10079         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10080         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10081                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10082         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10083                        bp->common.flash_size, bp->common.flash_size);
10084
10085         bnx2x_init_shmem(bp);
10086
10087
10088
10089         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10090                                         MISC_REG_GENERIC_CR_1 :
10091                                         MISC_REG_GENERIC_CR_0));
10092
10093         bp->link_params.shmem_base = bp->common.shmem_base;
10094         bp->link_params.shmem2_base = bp->common.shmem2_base;
10095         if (SHMEM2_RD(bp, size) >
10096             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10097                 bp->link_params.lfa_base =
10098                 REG_RD(bp, bp->common.shmem2_base +
10099                        (u32)offsetof(struct shmem2_region,
10100                                      lfa_host_addr[BP_PORT(bp)]));
10101         else
10102                 bp->link_params.lfa_base = 0;
10103         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10104                        bp->common.shmem_base, bp->common.shmem2_base);
10105
10106         if (!bp->common.shmem_base) {
10107                 BNX2X_DEV_INFO("MCP not active\n");
10108                 bp->flags |= NO_MCP_FLAG;
10109                 return;
10110         }
10111
10112         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10113         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10114
10115         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10116                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10117                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10118
10119         bp->link_params.feature_config_flags = 0;
10120         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10121         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10122                 bp->link_params.feature_config_flags |=
10123                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10124         else
10125                 bp->link_params.feature_config_flags &=
10126                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10127
10128         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10129         bp->common.bc_ver = val;
10130         BNX2X_DEV_INFO("bc_ver %X\n", val);
10131         if (val < BNX2X_BC_VER) {
10132                 /* for now only warn
10133                  * later we might need to enforce this */
10134                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10135                           BNX2X_BC_VER, val);
10136         }
10137         bp->link_params.feature_config_flags |=
10138                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10139                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10140
10141         bp->link_params.feature_config_flags |=
10142                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10143                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10144         bp->link_params.feature_config_flags |=
10145                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10146                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10147         bp->link_params.feature_config_flags |=
10148                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10149                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10150
10151         bp->link_params.feature_config_flags |=
10152                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10153                 FEATURE_CONFIG_MT_SUPPORT : 0;
10154
10155         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10156                         BC_SUPPORTS_PFC_STATS : 0;
10157
10158         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10159                         BC_SUPPORTS_FCOE_FEATURES : 0;
10160
10161         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10162                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10163         boot_mode = SHMEM_RD(bp,
10164                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10165                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10166         switch (boot_mode) {
10167         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10168                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10169                 break;
10170         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10171                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10172                 break;
10173         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10174                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10175                 break;
10176         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10177                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10178                 break;
10179         }
10180
10181         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10182         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10183
10184         BNX2X_DEV_INFO("%sWoL capable\n",
10185                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10186
10187         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10188         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10189         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10190         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10191
10192         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10193                  val, val2, val3, val4);
10194 }
10195
10196 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10197 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10198
10199 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10200 {
10201         int pfid = BP_FUNC(bp);
10202         int igu_sb_id;
10203         u32 val;
10204         u8 fid, igu_sb_cnt = 0;
10205
10206         bp->igu_base_sb = 0xff;
10207         if (CHIP_INT_MODE_IS_BC(bp)) {
10208                 int vn = BP_VN(bp);
10209                 igu_sb_cnt = bp->igu_sb_cnt;
10210                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10211                         FP_SB_MAX_E1x;
10212
10213                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10214                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10215
10216                 return 0;
10217         }
10218
10219         /* IGU in normal mode - read CAM */
10220         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10221              igu_sb_id++) {
10222                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10223                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10224                         continue;
10225                 fid = IGU_FID(val);
10226                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10227                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10228                                 continue;
10229                         if (IGU_VEC(val) == 0)
10230                                 /* default status block */
10231                                 bp->igu_dsb_id = igu_sb_id;
10232                         else {
10233                                 if (bp->igu_base_sb == 0xff)
10234                                         bp->igu_base_sb = igu_sb_id;
10235                                 igu_sb_cnt++;
10236                         }
10237                 }
10238         }
10239
10240 #ifdef CONFIG_PCI_MSI
10241         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10242          * optional that number of CAM entries will not be equal to the value
10243          * advertised in PCI.
10244          * Driver should use the minimal value of both as the actual status
10245          * block count
10246          */
10247         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10248 #endif
10249
10250         if (igu_sb_cnt == 0) {
10251                 BNX2X_ERR("CAM configuration error\n");
10252                 return -EINVAL;
10253         }
10254
10255         return 0;
10256 }
10257
10258 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10259 {
10260         int cfg_size = 0, idx, port = BP_PORT(bp);
10261
10262         /* Aggregation of supported attributes of all external phys */
10263         bp->port.supported[0] = 0;
10264         bp->port.supported[1] = 0;
10265         switch (bp->link_params.num_phys) {
10266         case 1:
10267                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10268                 cfg_size = 1;
10269                 break;
10270         case 2:
10271                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10272                 cfg_size = 1;
10273                 break;
10274         case 3:
10275                 if (bp->link_params.multi_phy_config &
10276                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10277                         bp->port.supported[1] =
10278                                 bp->link_params.phy[EXT_PHY1].supported;
10279                         bp->port.supported[0] =
10280                                 bp->link_params.phy[EXT_PHY2].supported;
10281                 } else {
10282                         bp->port.supported[0] =
10283                                 bp->link_params.phy[EXT_PHY1].supported;
10284                         bp->port.supported[1] =
10285                                 bp->link_params.phy[EXT_PHY2].supported;
10286                 }
10287                 cfg_size = 2;
10288                 break;
10289         }
10290
10291         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10292                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10293                            SHMEM_RD(bp,
10294                            dev_info.port_hw_config[port].external_phy_config),
10295                            SHMEM_RD(bp,
10296                            dev_info.port_hw_config[port].external_phy_config2));
10297                         return;
10298         }
10299
10300         if (CHIP_IS_E3(bp))
10301                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10302         else {
10303                 switch (switch_cfg) {
10304                 case SWITCH_CFG_1G:
10305                         bp->port.phy_addr = REG_RD(
10306                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10307                         break;
10308                 case SWITCH_CFG_10G:
10309                         bp->port.phy_addr = REG_RD(
10310                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10311                         break;
10312                 default:
10313                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10314                                   bp->port.link_config[0]);
10315                         return;
10316                 }
10317         }
10318         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10319         /* mask what we support according to speed_cap_mask per configuration */
10320         for (idx = 0; idx < cfg_size; idx++) {
10321                 if (!(bp->link_params.speed_cap_mask[idx] &
10322                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10323                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10324
10325                 if (!(bp->link_params.speed_cap_mask[idx] &
10326                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10327                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10328
10329                 if (!(bp->link_params.speed_cap_mask[idx] &
10330                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10331                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10332
10333                 if (!(bp->link_params.speed_cap_mask[idx] &
10334                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10335                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10336
10337                 if (!(bp->link_params.speed_cap_mask[idx] &
10338                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10339                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10340                                                      SUPPORTED_1000baseT_Full);
10341
10342                 if (!(bp->link_params.speed_cap_mask[idx] &
10343                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10344                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10345
10346                 if (!(bp->link_params.speed_cap_mask[idx] &
10347                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10348                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10349
10350         }
10351
10352         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10353                        bp->port.supported[1]);
10354 }
10355
10356 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10357 {
10358         u32 link_config, idx, cfg_size = 0;
10359         bp->port.advertising[0] = 0;
10360         bp->port.advertising[1] = 0;
10361         switch (bp->link_params.num_phys) {
10362         case 1:
10363         case 2:
10364                 cfg_size = 1;
10365                 break;
10366         case 3:
10367                 cfg_size = 2;
10368                 break;
10369         }
10370         for (idx = 0; idx < cfg_size; idx++) {
10371                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10372                 link_config = bp->port.link_config[idx];
10373                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10374                 case PORT_FEATURE_LINK_SPEED_AUTO:
10375                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10376                                 bp->link_params.req_line_speed[idx] =
10377                                         SPEED_AUTO_NEG;
10378                                 bp->port.advertising[idx] |=
10379                                         bp->port.supported[idx];
10380                                 if (bp->link_params.phy[EXT_PHY1].type ==
10381                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10382                                         bp->port.advertising[idx] |=
10383                                         (SUPPORTED_100baseT_Half |
10384                                          SUPPORTED_100baseT_Full);
10385                         } else {
10386                                 /* force 10G, no AN */
10387                                 bp->link_params.req_line_speed[idx] =
10388                                         SPEED_10000;
10389                                 bp->port.advertising[idx] |=
10390                                         (ADVERTISED_10000baseT_Full |
10391                                          ADVERTISED_FIBRE);
10392                                 continue;
10393                         }
10394                         break;
10395
10396                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10397                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10398                                 bp->link_params.req_line_speed[idx] =
10399                                         SPEED_10;
10400                                 bp->port.advertising[idx] |=
10401                                         (ADVERTISED_10baseT_Full |
10402                                          ADVERTISED_TP);
10403                         } else {
10404                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10405                                             link_config,
10406                                     bp->link_params.speed_cap_mask[idx]);
10407                                 return;
10408                         }
10409                         break;
10410
10411                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10412                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10413                                 bp->link_params.req_line_speed[idx] =
10414                                         SPEED_10;
10415                                 bp->link_params.req_duplex[idx] =
10416                                         DUPLEX_HALF;
10417                                 bp->port.advertising[idx] |=
10418                                         (ADVERTISED_10baseT_Half |
10419                                          ADVERTISED_TP);
10420                         } else {
10421                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10422                                             link_config,
10423                                           bp->link_params.speed_cap_mask[idx]);
10424                                 return;
10425                         }
10426                         break;
10427
10428                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10429                         if (bp->port.supported[idx] &
10430                             SUPPORTED_100baseT_Full) {
10431                                 bp->link_params.req_line_speed[idx] =
10432                                         SPEED_100;
10433                                 bp->port.advertising[idx] |=
10434                                         (ADVERTISED_100baseT_Full |
10435                                          ADVERTISED_TP);
10436                         } else {
10437                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10438                                             link_config,
10439                                           bp->link_params.speed_cap_mask[idx]);
10440                                 return;
10441                         }
10442                         break;
10443
10444                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10445                         if (bp->port.supported[idx] &
10446                             SUPPORTED_100baseT_Half) {
10447                                 bp->link_params.req_line_speed[idx] =
10448                                                                 SPEED_100;
10449                                 bp->link_params.req_duplex[idx] =
10450                                                                 DUPLEX_HALF;
10451                                 bp->port.advertising[idx] |=
10452                                         (ADVERTISED_100baseT_Half |
10453                                          ADVERTISED_TP);
10454                         } else {
10455                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10456                                     link_config,
10457                                     bp->link_params.speed_cap_mask[idx]);
10458                                 return;
10459                         }
10460                         break;
10461
10462                 case PORT_FEATURE_LINK_SPEED_1G:
10463                         if (bp->port.supported[idx] &
10464                             SUPPORTED_1000baseT_Full) {
10465                                 bp->link_params.req_line_speed[idx] =
10466                                         SPEED_1000;
10467                                 bp->port.advertising[idx] |=
10468                                         (ADVERTISED_1000baseT_Full |
10469                                          ADVERTISED_TP);
10470                         } else {
10471                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10472                                     link_config,
10473                                     bp->link_params.speed_cap_mask[idx]);
10474                                 return;
10475                         }
10476                         break;
10477
10478                 case PORT_FEATURE_LINK_SPEED_2_5G:
10479                         if (bp->port.supported[idx] &
10480                             SUPPORTED_2500baseX_Full) {
10481                                 bp->link_params.req_line_speed[idx] =
10482                                         SPEED_2500;
10483                                 bp->port.advertising[idx] |=
10484                                         (ADVERTISED_2500baseX_Full |
10485                                                 ADVERTISED_TP);
10486                         } else {
10487                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10488                                     link_config,
10489                                     bp->link_params.speed_cap_mask[idx]);
10490                                 return;
10491                         }
10492                         break;
10493
10494                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10495                         if (bp->port.supported[idx] &
10496                             SUPPORTED_10000baseT_Full) {
10497                                 bp->link_params.req_line_speed[idx] =
10498                                         SPEED_10000;
10499                                 bp->port.advertising[idx] |=
10500                                         (ADVERTISED_10000baseT_Full |
10501                                                 ADVERTISED_FIBRE);
10502                         } else {
10503                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10504                                     link_config,
10505                                     bp->link_params.speed_cap_mask[idx]);
10506                                 return;
10507                         }
10508                         break;
10509                 case PORT_FEATURE_LINK_SPEED_20G:
10510                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10511
10512                         break;
10513                 default:
10514                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10515                                   link_config);
10516                                 bp->link_params.req_line_speed[idx] =
10517                                                         SPEED_AUTO_NEG;
10518                                 bp->port.advertising[idx] =
10519                                                 bp->port.supported[idx];
10520                         break;
10521                 }
10522
10523                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10524                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10525                 if (bp->link_params.req_flow_ctrl[idx] ==
10526                     BNX2X_FLOW_CTRL_AUTO) {
10527                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10528                                 bp->link_params.req_flow_ctrl[idx] =
10529                                                         BNX2X_FLOW_CTRL_NONE;
10530                         else
10531                                 bnx2x_set_requested_fc(bp);
10532                 }
10533
10534                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10535                                bp->link_params.req_line_speed[idx],
10536                                bp->link_params.req_duplex[idx],
10537                                bp->link_params.req_flow_ctrl[idx],
10538                                bp->port.advertising[idx]);
10539         }
10540 }
10541
10542 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10543 {
10544         mac_hi = cpu_to_be16(mac_hi);
10545         mac_lo = cpu_to_be32(mac_lo);
10546         memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10547         memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10548 }
10549
10550 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10551 {
10552         int port = BP_PORT(bp);
10553         u32 config;
10554         u32 ext_phy_type, ext_phy_config, eee_mode;
10555
10556         bp->link_params.bp = bp;
10557         bp->link_params.port = port;
10558
10559         bp->link_params.lane_config =
10560                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10561
10562         bp->link_params.speed_cap_mask[0] =
10563                 SHMEM_RD(bp,
10564                          dev_info.port_hw_config[port].speed_capability_mask);
10565         bp->link_params.speed_cap_mask[1] =
10566                 SHMEM_RD(bp,
10567                          dev_info.port_hw_config[port].speed_capability_mask2);
10568         bp->port.link_config[0] =
10569                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10570
10571         bp->port.link_config[1] =
10572                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10573
10574         bp->link_params.multi_phy_config =
10575                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10576         /* If the device is capable of WoL, set the default state according
10577          * to the HW
10578          */
10579         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10580         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10581                    (config & PORT_FEATURE_WOL_ENABLED));
10582
10583         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10584             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10585                 bp->flags |= NO_ISCSI_FLAG;
10586         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10587             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10588                 bp->flags |= NO_FCOE_FLAG;
10589
10590         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10591                        bp->link_params.lane_config,
10592                        bp->link_params.speed_cap_mask[0],
10593                        bp->port.link_config[0]);
10594
10595         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10596                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10597         bnx2x_phy_probe(&bp->link_params);
10598         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10599
10600         bnx2x_link_settings_requested(bp);
10601
10602         /*
10603          * If connected directly, work with the internal PHY, otherwise, work
10604          * with the external PHY
10605          */
10606         ext_phy_config =
10607                 SHMEM_RD(bp,
10608                          dev_info.port_hw_config[port].external_phy_config);
10609         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10610         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10611                 bp->mdio.prtad = bp->port.phy_addr;
10612
10613         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10614                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10615                 bp->mdio.prtad =
10616                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10617
10618         /* Configure link feature according to nvram value */
10619         eee_mode = (((SHMEM_RD(bp, dev_info.
10620                       port_feature_config[port].eee_power_mode)) &
10621                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10622                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10623         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10624                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10625                                            EEE_MODE_ENABLE_LPI |
10626                                            EEE_MODE_OUTPUT_TIME;
10627         } else {
10628                 bp->link_params.eee_mode = 0;
10629         }
10630 }
10631
10632 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10633 {
10634         u32 no_flags = NO_ISCSI_FLAG;
10635         int port = BP_PORT(bp);
10636         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10637                                 drv_lic_key[port].max_iscsi_conn);
10638
10639         if (!CNIC_SUPPORT(bp)) {
10640                 bp->flags |= no_flags;
10641                 return;
10642         }
10643
10644         /* Get the number of maximum allowed iSCSI connections */
10645         bp->cnic_eth_dev.max_iscsi_conn =
10646                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10647                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10648
10649         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10650                        bp->cnic_eth_dev.max_iscsi_conn);
10651
10652         /*
10653          * If maximum allowed number of connections is zero -
10654          * disable the feature.
10655          */
10656         if (!bp->cnic_eth_dev.max_iscsi_conn)
10657                 bp->flags |= no_flags;
10658
10659 }
10660
10661 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10662 {
10663         /* Port info */
10664         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10665                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10666         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10667                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10668
10669         /* Node info */
10670         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10671                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10672         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10673                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10674 }
10675 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10676 {
10677         int port = BP_PORT(bp);
10678         int func = BP_ABS_FUNC(bp);
10679         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10680                                 drv_lic_key[port].max_fcoe_conn);
10681
10682         if (!CNIC_SUPPORT(bp)) {
10683                 bp->flags |= NO_FCOE_FLAG;
10684                 return;
10685         }
10686
10687         /* Get the number of maximum allowed FCoE connections */
10688         bp->cnic_eth_dev.max_fcoe_conn =
10689                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10690                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10691
10692         /* Read the WWN: */
10693         if (!IS_MF(bp)) {
10694                 /* Port info */
10695                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10696                         SHMEM_RD(bp,
10697                                 dev_info.port_hw_config[port].
10698                                  fcoe_wwn_port_name_upper);
10699                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10700                         SHMEM_RD(bp,
10701                                 dev_info.port_hw_config[port].
10702                                  fcoe_wwn_port_name_lower);
10703
10704                 /* Node info */
10705                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10706                         SHMEM_RD(bp,
10707                                 dev_info.port_hw_config[port].
10708                                  fcoe_wwn_node_name_upper);
10709                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10710                         SHMEM_RD(bp,
10711                                 dev_info.port_hw_config[port].
10712                                  fcoe_wwn_node_name_lower);
10713         } else if (!IS_MF_SD(bp)) {
10714                 /*
10715                  * Read the WWN info only if the FCoE feature is enabled for
10716                  * this function.
10717                  */
10718                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10719                         bnx2x_get_ext_wwn_info(bp, func);
10720
10721         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10722                 bnx2x_get_ext_wwn_info(bp, func);
10723         }
10724
10725         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10726
10727         /*
10728          * If maximum allowed number of connections is zero -
10729          * disable the feature.
10730          */
10731         if (!bp->cnic_eth_dev.max_fcoe_conn)
10732                 bp->flags |= NO_FCOE_FLAG;
10733 }
10734
10735 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10736 {
10737         /*
10738          * iSCSI may be dynamically disabled but reading
10739          * info here we will decrease memory usage by driver
10740          * if the feature is disabled for good
10741          */
10742         bnx2x_get_iscsi_info(bp);
10743         bnx2x_get_fcoe_info(bp);
10744 }
10745
10746 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10747 {
10748         u32 val, val2;
10749         int func = BP_ABS_FUNC(bp);
10750         int port = BP_PORT(bp);
10751         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10752         u8 *fip_mac = bp->fip_mac;
10753
10754         if (IS_MF(bp)) {
10755                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10756                  * FCoE MAC then the appropriate feature should be disabled.
10757                  * In non SD mode features configuration comes from struct
10758                  * func_ext_config.
10759                  */
10760                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
10761                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10762                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10763                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10764                                                  iscsi_mac_addr_upper);
10765                                 val = MF_CFG_RD(bp, func_ext_config[func].
10766                                                 iscsi_mac_addr_lower);
10767                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10768                                 BNX2X_DEV_INFO
10769                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10770                         } else {
10771                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10772                         }
10773
10774                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10775                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10776                                                  fcoe_mac_addr_upper);
10777                                 val = MF_CFG_RD(bp, func_ext_config[func].
10778                                                 fcoe_mac_addr_lower);
10779                                 bnx2x_set_mac_buf(fip_mac, val, val2);
10780                                 BNX2X_DEV_INFO
10781                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
10782                         } else {
10783                                 bp->flags |= NO_FCOE_FLAG;
10784                         }
10785
10786                         bp->mf_ext_config = cfg;
10787
10788                 } else { /* SD MODE */
10789                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10790                                 /* use primary mac as iscsi mac */
10791                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10792
10793                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10794                                 BNX2X_DEV_INFO
10795                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10796                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10797                                 /* use primary mac as fip mac */
10798                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10799                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
10800                                 BNX2X_DEV_INFO
10801                                         ("Read FIP MAC: %pM\n", fip_mac);
10802                         }
10803                 }
10804
10805                 if (IS_MF_STORAGE_SD(bp))
10806                         /* Zero primary MAC configuration */
10807                         memset(bp->dev->dev_addr, 0, ETH_ALEN);
10808
10809                 if (IS_MF_FCOE_AFEX(bp) || IS_MF_FCOE_SD(bp))
10810                         /* use FIP MAC as primary MAC */
10811                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10812
10813         } else {
10814                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10815                                 iscsi_mac_upper);
10816                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10817                                iscsi_mac_lower);
10818                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10819
10820                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10821                                 fcoe_fip_mac_upper);
10822                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10823                                fcoe_fip_mac_lower);
10824                 bnx2x_set_mac_buf(fip_mac, val, val2);
10825         }
10826
10827         /* Disable iSCSI OOO if MAC configuration is invalid. */
10828         if (!is_valid_ether_addr(iscsi_mac)) {
10829                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10830                 memset(iscsi_mac, 0, ETH_ALEN);
10831         }
10832
10833         /* Disable FCoE if MAC configuration is invalid. */
10834         if (!is_valid_ether_addr(fip_mac)) {
10835                 bp->flags |= NO_FCOE_FLAG;
10836                 memset(bp->fip_mac, 0, ETH_ALEN);
10837         }
10838 }
10839
10840 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10841 {
10842         u32 val, val2;
10843         int func = BP_ABS_FUNC(bp);
10844         int port = BP_PORT(bp);
10845
10846         /* Zero primary MAC configuration */
10847         memset(bp->dev->dev_addr, 0, ETH_ALEN);
10848
10849         if (BP_NOMCP(bp)) {
10850                 BNX2X_ERROR("warning: random MAC workaround active\n");
10851                 eth_hw_addr_random(bp->dev);
10852         } else if (IS_MF(bp)) {
10853                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10854                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10855                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10856                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10857                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10858
10859                 if (CNIC_SUPPORT(bp))
10860                         bnx2x_get_cnic_mac_hwinfo(bp);
10861         } else {
10862                 /* in SF read MACs from port configuration */
10863                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10864                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10865                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10866
10867                 if (CNIC_SUPPORT(bp))
10868                         bnx2x_get_cnic_mac_hwinfo(bp);
10869         }
10870
10871         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10872
10873         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10874                 dev_err(&bp->pdev->dev,
10875                         "bad Ethernet MAC address configuration: %pM\n"
10876                         "change it manually before bringing up the appropriate network interface\n",
10877                         bp->dev->dev_addr);
10878 }
10879
10880 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
10881 {
10882         int tmp;
10883         u32 cfg;
10884
10885         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10886                 /* Take function: tmp = func */
10887                 tmp = BP_ABS_FUNC(bp);
10888                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10889                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10890         } else {
10891                 /* Take port: tmp = port */
10892                 tmp = BP_PORT(bp);
10893                 cfg = SHMEM_RD(bp,
10894                                dev_info.port_hw_config[tmp].generic_features);
10895                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10896         }
10897         return cfg;
10898 }
10899
10900 static int bnx2x_get_hwinfo(struct bnx2x *bp)
10901 {
10902         int /*abs*/func = BP_ABS_FUNC(bp);
10903         int vn;
10904         u32 val = 0;
10905         int rc = 0;
10906
10907         bnx2x_get_common_hwinfo(bp);
10908
10909         /*
10910          * initialize IGU parameters
10911          */
10912         if (CHIP_IS_E1x(bp)) {
10913                 bp->common.int_block = INT_BLOCK_HC;
10914
10915                 bp->igu_dsb_id = DEF_SB_IGU_ID;
10916                 bp->igu_base_sb = 0;
10917         } else {
10918                 bp->common.int_block = INT_BLOCK_IGU;
10919
10920                 /* do not allow device reset during IGU info preocessing */
10921                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10922
10923                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10924
10925                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10926                         int tout = 5000;
10927
10928                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
10929
10930                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10931                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10932                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10933
10934                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10935                                 tout--;
10936                                 usleep_range(1000, 1000);
10937                         }
10938
10939                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10940                                 dev_err(&bp->pdev->dev,
10941                                         "FORCING Normal Mode failed!!!\n");
10942                                 bnx2x_release_hw_lock(bp,
10943                                                       HW_LOCK_RESOURCE_RESET);
10944                                 return -EPERM;
10945                         }
10946                 }
10947
10948                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10949                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10950                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10951                 } else
10952                         BNX2X_DEV_INFO("IGU Normal Mode\n");
10953
10954                 rc = bnx2x_get_igu_cam_info(bp);
10955                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10956                 if (rc)
10957                         return rc;
10958         }
10959
10960         /*
10961          * set base FW non-default (fast path) status block id, this value is
10962          * used to initialize the fw_sb_id saved on the fp/queue structure to
10963          * determine the id used by the FW.
10964          */
10965         if (CHIP_IS_E1x(bp))
10966                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10967         else /*
10968               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10969               * the same queue are indicated on the same IGU SB). So we prefer
10970               * FW and IGU SBs to be the same value.
10971               */
10972                 bp->base_fw_ndsb = bp->igu_base_sb;
10973
10974         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
10975                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10976                        bp->igu_sb_cnt, bp->base_fw_ndsb);
10977
10978         /*
10979          * Initialize MF configuration
10980          */
10981
10982         bp->mf_ov = 0;
10983         bp->mf_mode = 0;
10984         vn = BP_VN(bp);
10985
10986         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10987                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10988                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
10989                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10990
10991                 if (SHMEM2_HAS(bp, mf_cfg_addr))
10992                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10993                 else
10994                         bp->common.mf_cfg_base = bp->common.shmem_base +
10995                                 offsetof(struct shmem_region, func_mb) +
10996                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
10997                 /*
10998                  * get mf configuration:
10999                  * 1. existence of MF configuration
11000                  * 2. MAC address must be legal (check only upper bytes)
11001                  *    for  Switch-Independent mode;
11002                  *    OVLAN must be legal for Switch-Dependent mode
11003                  * 3. SF_MODE configures specific MF mode
11004                  */
11005                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11006                         /* get mf configuration */
11007                         val = SHMEM_RD(bp,
11008                                        dev_info.shared_feature_config.config);
11009                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11010
11011                         switch (val) {
11012                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11013                                 val = MF_CFG_RD(bp, func_mf_config[func].
11014                                                 mac_upper);
11015                                 /* check for legal mac (upper bytes)*/
11016                                 if (val != 0xffff) {
11017                                         bp->mf_mode = MULTI_FUNCTION_SI;
11018                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11019                                                    func_mf_config[func].config);
11020                                 } else
11021                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11022                                 break;
11023                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11024                                 if ((!CHIP_IS_E1x(bp)) &&
11025                                     (MF_CFG_RD(bp, func_mf_config[func].
11026                                                mac_upper) != 0xffff) &&
11027                                     (SHMEM2_HAS(bp,
11028                                                 afex_driver_support))) {
11029                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11030                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11031                                                 func_mf_config[func].config);
11032                                 } else {
11033                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11034                                 }
11035                                 break;
11036                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11037                                 /* get OV configuration */
11038                                 val = MF_CFG_RD(bp,
11039                                         func_mf_config[FUNC_0].e1hov_tag);
11040                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11041
11042                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11043                                         bp->mf_mode = MULTI_FUNCTION_SD;
11044                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11045                                                 func_mf_config[func].config);
11046                                 } else
11047                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11048                                 break;
11049                         default:
11050                                 /* Unknown configuration: reset mf_config */
11051                                 bp->mf_config[vn] = 0;
11052                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11053                         }
11054                 }
11055
11056                 BNX2X_DEV_INFO("%s function mode\n",
11057                                IS_MF(bp) ? "multi" : "single");
11058
11059                 switch (bp->mf_mode) {
11060                 case MULTI_FUNCTION_SD:
11061                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11062                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11063                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11064                                 bp->mf_ov = val;
11065                                 bp->path_has_ovlan = true;
11066
11067                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11068                                                func, bp->mf_ov, bp->mf_ov);
11069                         } else {
11070                                 dev_err(&bp->pdev->dev,
11071                                         "No valid MF OV for func %d, aborting\n",
11072                                         func);
11073                                 return -EPERM;
11074                         }
11075                         break;
11076                 case MULTI_FUNCTION_AFEX:
11077                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11078                         break;
11079                 case MULTI_FUNCTION_SI:
11080                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11081                                        func);
11082                         break;
11083                 default:
11084                         if (vn) {
11085                                 dev_err(&bp->pdev->dev,
11086                                         "VN %d is in a single function mode, aborting\n",
11087                                         vn);
11088                                 return -EPERM;
11089                         }
11090                         break;
11091                 }
11092
11093                 /* check if other port on the path needs ovlan:
11094                  * Since MF configuration is shared between ports
11095                  * Possible mixed modes are only
11096                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11097                  */
11098                 if (CHIP_MODE_IS_4_PORT(bp) &&
11099                     !bp->path_has_ovlan &&
11100                     !IS_MF(bp) &&
11101                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11102                         u8 other_port = !BP_PORT(bp);
11103                         u8 other_func = BP_PATH(bp) + 2*other_port;
11104                         val = MF_CFG_RD(bp,
11105                                         func_mf_config[other_func].e1hov_tag);
11106                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11107                                 bp->path_has_ovlan = true;
11108                 }
11109         }
11110
11111         /* adjust igu_sb_cnt to MF for E1x */
11112         if (CHIP_IS_E1x(bp) && IS_MF(bp))
11113                 bp->igu_sb_cnt /= E1HVN_MAX;
11114
11115         /* port info */
11116         bnx2x_get_port_hwinfo(bp);
11117
11118         /* Get MAC addresses */
11119         bnx2x_get_mac_hwinfo(bp);
11120
11121         bnx2x_get_cnic_info(bp);
11122
11123         return rc;
11124 }
11125
11126 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11127 {
11128         int cnt, i, block_end, rodi;
11129         char vpd_start[BNX2X_VPD_LEN+1];
11130         char str_id_reg[VENDOR_ID_LEN+1];
11131         char str_id_cap[VENDOR_ID_LEN+1];
11132         char *vpd_data;
11133         char *vpd_extended_data = NULL;
11134         u8 len;
11135
11136         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11137         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11138
11139         if (cnt < BNX2X_VPD_LEN)
11140                 goto out_not_found;
11141
11142         /* VPD RO tag should be first tag after identifier string, hence
11143          * we should be able to find it in first BNX2X_VPD_LEN chars
11144          */
11145         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11146                              PCI_VPD_LRDT_RO_DATA);
11147         if (i < 0)
11148                 goto out_not_found;
11149
11150         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11151                     pci_vpd_lrdt_size(&vpd_start[i]);
11152
11153         i += PCI_VPD_LRDT_TAG_SIZE;
11154
11155         if (block_end > BNX2X_VPD_LEN) {
11156                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11157                 if (vpd_extended_data  == NULL)
11158                         goto out_not_found;
11159
11160                 /* read rest of vpd image into vpd_extended_data */
11161                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11162                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11163                                    block_end - BNX2X_VPD_LEN,
11164                                    vpd_extended_data + BNX2X_VPD_LEN);
11165                 if (cnt < (block_end - BNX2X_VPD_LEN))
11166                         goto out_not_found;
11167                 vpd_data = vpd_extended_data;
11168         } else
11169                 vpd_data = vpd_start;
11170
11171         /* now vpd_data holds full vpd content in both cases */
11172
11173         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11174                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11175         if (rodi < 0)
11176                 goto out_not_found;
11177
11178         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11179
11180         if (len != VENDOR_ID_LEN)
11181                 goto out_not_found;
11182
11183         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11184
11185         /* vendor specific info */
11186         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11187         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11188         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11189             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11190
11191                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11192                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11193                 if (rodi >= 0) {
11194                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11195
11196                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11197
11198                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11199                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11200                                 bp->fw_ver[len] = ' ';
11201                         }
11202                 }
11203                 kfree(vpd_extended_data);
11204                 return;
11205         }
11206 out_not_found:
11207         kfree(vpd_extended_data);
11208         return;
11209 }
11210
11211 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11212 {
11213         u32 flags = 0;
11214
11215         if (CHIP_REV_IS_FPGA(bp))
11216                 SET_FLAGS(flags, MODE_FPGA);
11217         else if (CHIP_REV_IS_EMUL(bp))
11218                 SET_FLAGS(flags, MODE_EMUL);
11219         else
11220                 SET_FLAGS(flags, MODE_ASIC);
11221
11222         if (CHIP_MODE_IS_4_PORT(bp))
11223                 SET_FLAGS(flags, MODE_PORT4);
11224         else
11225                 SET_FLAGS(flags, MODE_PORT2);
11226
11227         if (CHIP_IS_E2(bp))
11228                 SET_FLAGS(flags, MODE_E2);
11229         else if (CHIP_IS_E3(bp)) {
11230                 SET_FLAGS(flags, MODE_E3);
11231                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11232                         SET_FLAGS(flags, MODE_E3_A0);
11233                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11234                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11235         }
11236
11237         if (IS_MF(bp)) {
11238                 SET_FLAGS(flags, MODE_MF);
11239                 switch (bp->mf_mode) {
11240                 case MULTI_FUNCTION_SD:
11241                         SET_FLAGS(flags, MODE_MF_SD);
11242                         break;
11243                 case MULTI_FUNCTION_SI:
11244                         SET_FLAGS(flags, MODE_MF_SI);
11245                         break;
11246                 case MULTI_FUNCTION_AFEX:
11247                         SET_FLAGS(flags, MODE_MF_AFEX);
11248                         break;
11249                 }
11250         } else
11251                 SET_FLAGS(flags, MODE_SF);
11252
11253 #if defined(__LITTLE_ENDIAN)
11254         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11255 #else /*(__BIG_ENDIAN)*/
11256         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11257 #endif
11258         INIT_MODE_FLAGS(bp) = flags;
11259 }
11260
11261 static int bnx2x_init_bp(struct bnx2x *bp)
11262 {
11263         int func;
11264         int rc;
11265
11266         mutex_init(&bp->port.phy_mutex);
11267         mutex_init(&bp->fw_mb_mutex);
11268         spin_lock_init(&bp->stats_lock);
11269
11270
11271         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11272         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11273         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11274         if (IS_PF(bp)) {
11275                 rc = bnx2x_get_hwinfo(bp);
11276                 if (rc)
11277                         return rc;
11278         } else {
11279                 random_ether_addr(bp->dev->dev_addr);
11280         }
11281
11282         bnx2x_set_modes_bitmap(bp);
11283
11284         rc = bnx2x_alloc_mem_bp(bp);
11285         if (rc)
11286                 return rc;
11287
11288         bnx2x_read_fwinfo(bp);
11289
11290         func = BP_FUNC(bp);
11291
11292         /* need to reset chip if undi was active */
11293         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11294                 /* init fw_seq */
11295                 bp->fw_seq =
11296                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11297                                                         DRV_MSG_SEQ_NUMBER_MASK;
11298                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11299
11300                 bnx2x_prev_unload(bp);
11301         }
11302
11303
11304         if (CHIP_REV_IS_FPGA(bp))
11305                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11306
11307         if (BP_NOMCP(bp) && (func == 0))
11308                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11309
11310         bp->disable_tpa = disable_tpa;
11311         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11312
11313         /* Set TPA flags */
11314         if (bp->disable_tpa) {
11315                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11316                 bp->dev->features &= ~NETIF_F_LRO;
11317         } else {
11318                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11319                 bp->dev->features |= NETIF_F_LRO;
11320         }
11321
11322         if (CHIP_IS_E1(bp))
11323                 bp->dropless_fc = 0;
11324         else
11325                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11326
11327         bp->mrrs = mrrs;
11328
11329         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11330         if (IS_VF(bp))
11331                 bp->rx_ring_size = MAX_RX_AVAIL;
11332
11333         /* make sure that the numbers are in the right granularity */
11334         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11335         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11336
11337         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11338
11339         init_timer(&bp->timer);
11340         bp->timer.expires = jiffies + bp->current_interval;
11341         bp->timer.data = (unsigned long) bp;
11342         bp->timer.function = bnx2x_timer;
11343
11344         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11345             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11346             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11347             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11348                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11349                 bnx2x_dcbx_init_params(bp);
11350         } else {
11351                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11352         }
11353
11354         if (CHIP_IS_E1x(bp))
11355                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11356         else
11357                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11358
11359         /* multiple tx priority */
11360         if (IS_VF(bp))
11361                 bp->max_cos = 1;
11362         else if (CHIP_IS_E1x(bp))
11363                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11364         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11365                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11366         else if (CHIP_IS_E3B0(bp))
11367                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11368         else
11369                 BNX2X_ERR("unknown chip %x revision %x\n",
11370                           CHIP_NUM(bp), CHIP_REV(bp));
11371         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11372
11373         /* We need at least one default status block for slow-path events,
11374          * second status block for the L2 queue, and a third status block for
11375          * CNIC if supproted.
11376          */
11377         if (CNIC_SUPPORT(bp))
11378                 bp->min_msix_vec_cnt = 3;
11379         else
11380                 bp->min_msix_vec_cnt = 2;
11381         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11382
11383         return rc;
11384 }
11385
11386
11387 /****************************************************************************
11388 * General service functions
11389 ****************************************************************************/
11390
11391 /*
11392  * net_device service functions
11393  */
11394
11395 static int bnx2x_open_epilog(struct bnx2x *bp)
11396 {
11397         /* Enable sriov via delayed work. This must be done via delayed work
11398          * because it causes the probe of the vf devices to be run, which invoke
11399          * register_netdevice which must have rtnl lock taken. As we are holding
11400          * the lock right now, that could only work if the probe would not take
11401          * the lock. However, as the probe of the vf may be called from other
11402          * contexts as well (such as passthrough to vm failes) it can't assume
11403          * the lock is being held for it. Using delayed work here allows the
11404          * probe code to simply take the lock (i.e. wait for it to be released
11405          * if it is being held).
11406          */
11407         smp_mb__before_clear_bit();
11408         set_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, &bp->sp_rtnl_state);
11409         smp_mb__after_clear_bit();
11410         schedule_delayed_work(&bp->sp_rtnl_task, 0);
11411
11412         return 0;
11413 }
11414
11415 /* called with rtnl_lock */
11416 static int bnx2x_open(struct net_device *dev)
11417 {
11418         struct bnx2x *bp = netdev_priv(dev);
11419         bool global = false;
11420         int other_engine = BP_PATH(bp) ? 0 : 1;
11421         bool other_load_status, load_status;
11422         int rc;
11423
11424         bp->stats_init = true;
11425
11426         netif_carrier_off(dev);
11427
11428         bnx2x_set_power_state(bp, PCI_D0);
11429
11430         /* If parity had happen during the unload, then attentions
11431          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11432          * want the first function loaded on the current engine to
11433          * complete the recovery.
11434          * Parity recovery is only relevant for PF driver.
11435          */
11436         if (IS_PF(bp)) {
11437                 other_load_status = bnx2x_get_load_status(bp, other_engine);
11438                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11439                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11440                     bnx2x_chk_parity_attn(bp, &global, true)) {
11441                         do {
11442                                 /* If there are attentions and they are in a
11443                                  * global blocks, set the GLOBAL_RESET bit
11444                                  * regardless whether it will be this function
11445                                  * that will complete the recovery or not.
11446                                  */
11447                                 if (global)
11448                                         bnx2x_set_reset_global(bp);
11449
11450                                 /* Only the first function on the current
11451                                  * engine should try to recover in open. In case
11452                                  * of attentions in global blocks only the first
11453                                  * in the chip should try to recover.
11454                                  */
11455                                 if ((!load_status &&
11456                                      (!global || !other_load_status)) &&
11457                                       bnx2x_trylock_leader_lock(bp) &&
11458                                       !bnx2x_leader_reset(bp)) {
11459                                         netdev_info(bp->dev,
11460                                                     "Recovered in open\n");
11461                                         break;
11462                                 }
11463
11464                                 /* recovery has failed... */
11465                                 bnx2x_set_power_state(bp, PCI_D3hot);
11466                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11467
11468                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11469                                           "If you still see this message after a few retries then power cycle is required.\n");
11470
11471                                 return -EAGAIN;
11472                         } while (0);
11473                 }
11474         }
11475
11476         bp->recovery_state = BNX2X_RECOVERY_DONE;
11477         rc = bnx2x_nic_load(bp, LOAD_OPEN);
11478         if (rc)
11479                 return rc;
11480         return bnx2x_open_epilog(bp);
11481 }
11482
11483 /* called with rtnl_lock */
11484 static int bnx2x_close(struct net_device *dev)
11485 {
11486         struct bnx2x *bp = netdev_priv(dev);
11487
11488         /* Unload the driver, release IRQs */
11489         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11490
11491         /* Power off */
11492         bnx2x_set_power_state(bp, PCI_D3hot);
11493
11494         return 0;
11495 }
11496
11497 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11498                                       struct bnx2x_mcast_ramrod_params *p)
11499 {
11500         int mc_count = netdev_mc_count(bp->dev);
11501         struct bnx2x_mcast_list_elem *mc_mac =
11502                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11503         struct netdev_hw_addr *ha;
11504
11505         if (!mc_mac)
11506                 return -ENOMEM;
11507
11508         INIT_LIST_HEAD(&p->mcast_list);
11509
11510         netdev_for_each_mc_addr(ha, bp->dev) {
11511                 mc_mac->mac = bnx2x_mc_addr(ha);
11512                 list_add_tail(&mc_mac->link, &p->mcast_list);
11513                 mc_mac++;
11514         }
11515
11516         p->mcast_list_len = mc_count;
11517
11518         return 0;
11519 }
11520
11521 static void bnx2x_free_mcast_macs_list(
11522         struct bnx2x_mcast_ramrod_params *p)
11523 {
11524         struct bnx2x_mcast_list_elem *mc_mac =
11525                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11526                                  link);
11527
11528         WARN_ON(!mc_mac);
11529         kfree(mc_mac);
11530 }
11531
11532 /**
11533  * bnx2x_set_uc_list - configure a new unicast MACs list.
11534  *
11535  * @bp: driver handle
11536  *
11537  * We will use zero (0) as a MAC type for these MACs.
11538  */
11539 static int bnx2x_set_uc_list(struct bnx2x *bp)
11540 {
11541         int rc;
11542         struct net_device *dev = bp->dev;
11543         struct netdev_hw_addr *ha;
11544         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11545         unsigned long ramrod_flags = 0;
11546
11547         /* First schedule a cleanup up of old configuration */
11548         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11549         if (rc < 0) {
11550                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11551                 return rc;
11552         }
11553
11554         netdev_for_each_uc_addr(ha, dev) {
11555                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11556                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11557                 if (rc == -EEXIST) {
11558                         DP(BNX2X_MSG_SP,
11559                            "Failed to schedule ADD operations: %d\n", rc);
11560                         /* do not treat adding same MAC as error */
11561                         rc = 0;
11562
11563                 } else if (rc < 0) {
11564
11565                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11566                                   rc);
11567                         return rc;
11568                 }
11569         }
11570
11571         /* Execute the pending commands */
11572         __set_bit(RAMROD_CONT, &ramrod_flags);
11573         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11574                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11575 }
11576
11577 static int bnx2x_set_mc_list(struct bnx2x *bp)
11578 {
11579         struct net_device *dev = bp->dev;
11580         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11581         int rc = 0;
11582
11583         rparam.mcast_obj = &bp->mcast_obj;
11584
11585         /* first, clear all configured multicast MACs */
11586         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11587         if (rc < 0) {
11588                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11589                 return rc;
11590         }
11591
11592         /* then, configure a new MACs list */
11593         if (netdev_mc_count(dev)) {
11594                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11595                 if (rc) {
11596                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11597                                   rc);
11598                         return rc;
11599                 }
11600
11601                 /* Now add the new MACs */
11602                 rc = bnx2x_config_mcast(bp, &rparam,
11603                                         BNX2X_MCAST_CMD_ADD);
11604                 if (rc < 0)
11605                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11606                                   rc);
11607
11608                 bnx2x_free_mcast_macs_list(&rparam);
11609         }
11610
11611         return rc;
11612 }
11613
11614
11615 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11616 void bnx2x_set_rx_mode(struct net_device *dev)
11617 {
11618         struct bnx2x *bp = netdev_priv(dev);
11619         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11620
11621         if (bp->state != BNX2X_STATE_OPEN) {
11622                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11623                 return;
11624         }
11625
11626         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11627
11628         if (dev->flags & IFF_PROMISC)
11629                 rx_mode = BNX2X_RX_MODE_PROMISC;
11630         else if ((dev->flags & IFF_ALLMULTI) ||
11631                  ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11632                   CHIP_IS_E1(bp)))
11633                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11634         else {
11635                 if (IS_PF(bp)) {
11636                         /* some multicasts */
11637                         if (bnx2x_set_mc_list(bp) < 0)
11638                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11639
11640                         if (bnx2x_set_uc_list(bp) < 0)
11641                                 rx_mode = BNX2X_RX_MODE_PROMISC;
11642                 } else {
11643                         /* configuring mcast to a vf involves sleeping (when we
11644                          * wait for the pf's response). Since this function is
11645                          * called from non sleepable context we must schedule
11646                          * a work item for this purpose
11647                          */
11648                         smp_mb__before_clear_bit();
11649                         set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11650                                 &bp->sp_rtnl_state);
11651                         smp_mb__after_clear_bit();
11652                         schedule_delayed_work(&bp->sp_rtnl_task, 0);
11653                 }
11654         }
11655
11656         bp->rx_mode = rx_mode;
11657         /* handle ISCSI SD mode */
11658         if (IS_MF_ISCSI_SD(bp))
11659                 bp->rx_mode = BNX2X_RX_MODE_NONE;
11660
11661         /* Schedule the rx_mode command */
11662         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11663                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11664                 return;
11665         }
11666
11667         if (IS_PF(bp)) {
11668                 bnx2x_set_storm_rx_mode(bp);
11669         } else {
11670                 /* configuring rx mode to storms in a vf involves sleeping (when
11671                  * we wait for the pf's response). Since this function is
11672                  * called from non sleepable context we must schedule
11673                  * a work item for this purpose
11674                  */
11675                 smp_mb__before_clear_bit();
11676                 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11677                         &bp->sp_rtnl_state);
11678                 smp_mb__after_clear_bit();
11679                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11680         }
11681 }
11682
11683 /* called with rtnl_lock */
11684 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11685                            int devad, u16 addr)
11686 {
11687         struct bnx2x *bp = netdev_priv(netdev);
11688         u16 value;
11689         int rc;
11690
11691         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11692            prtad, devad, addr);
11693
11694         /* The HW expects different devad if CL22 is used */
11695         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11696
11697         bnx2x_acquire_phy_lock(bp);
11698         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11699         bnx2x_release_phy_lock(bp);
11700         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11701
11702         if (!rc)
11703                 rc = value;
11704         return rc;
11705 }
11706
11707 /* called with rtnl_lock */
11708 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11709                             u16 addr, u16 value)
11710 {
11711         struct bnx2x *bp = netdev_priv(netdev);
11712         int rc;
11713
11714         DP(NETIF_MSG_LINK,
11715            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11716            prtad, devad, addr, value);
11717
11718         /* The HW expects different devad if CL22 is used */
11719         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11720
11721         bnx2x_acquire_phy_lock(bp);
11722         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11723         bnx2x_release_phy_lock(bp);
11724         return rc;
11725 }
11726
11727 /* called with rtnl_lock */
11728 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11729 {
11730         struct bnx2x *bp = netdev_priv(dev);
11731         struct mii_ioctl_data *mdio = if_mii(ifr);
11732
11733         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11734            mdio->phy_id, mdio->reg_num, mdio->val_in);
11735
11736         if (!netif_running(dev))
11737                 return -EAGAIN;
11738
11739         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11740 }
11741
11742 #ifdef CONFIG_NET_POLL_CONTROLLER
11743 static void poll_bnx2x(struct net_device *dev)
11744 {
11745         struct bnx2x *bp = netdev_priv(dev);
11746         int i;
11747
11748         for_each_eth_queue(bp, i) {
11749                 struct bnx2x_fastpath *fp = &bp->fp[i];
11750                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11751         }
11752 }
11753 #endif
11754
11755 static int bnx2x_validate_addr(struct net_device *dev)
11756 {
11757         struct bnx2x *bp = netdev_priv(dev);
11758
11759         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11760                 BNX2X_ERR("Non-valid Ethernet address\n");
11761                 return -EADDRNOTAVAIL;
11762         }
11763         return 0;
11764 }
11765
11766 static const struct net_device_ops bnx2x_netdev_ops = {
11767         .ndo_open               = bnx2x_open,
11768         .ndo_stop               = bnx2x_close,
11769         .ndo_start_xmit         = bnx2x_start_xmit,
11770         .ndo_select_queue       = bnx2x_select_queue,
11771         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
11772         .ndo_set_mac_address    = bnx2x_change_mac_addr,
11773         .ndo_validate_addr      = bnx2x_validate_addr,
11774         .ndo_do_ioctl           = bnx2x_ioctl,
11775         .ndo_change_mtu         = bnx2x_change_mtu,
11776         .ndo_fix_features       = bnx2x_fix_features,
11777         .ndo_set_features       = bnx2x_set_features,
11778         .ndo_tx_timeout         = bnx2x_tx_timeout,
11779 #ifdef CONFIG_NET_POLL_CONTROLLER
11780         .ndo_poll_controller    = poll_bnx2x,
11781 #endif
11782         .ndo_setup_tc           = bnx2x_setup_tc,
11783 #ifdef CONFIG_BNX2X_SRIOV
11784         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
11785 #endif
11786 #ifdef NETDEV_FCOE_WWNN
11787         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
11788 #endif
11789 };
11790
11791 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11792 {
11793         struct device *dev = &bp->pdev->dev;
11794
11795         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11796                 bp->flags |= USING_DAC_FLAG;
11797                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11798                         dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11799                         return -EIO;
11800                 }
11801         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11802                 dev_err(dev, "System does not support DMA, aborting\n");
11803                 return -EIO;
11804         }
11805
11806         return 0;
11807 }
11808
11809 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
11810                           struct net_device *dev, unsigned long board_type)
11811 {
11812         int rc;
11813         u32 pci_cfg_dword;
11814         bool chip_is_e1x = (board_type == BCM57710 ||
11815                             board_type == BCM57711 ||
11816                             board_type == BCM57711E);
11817
11818         SET_NETDEV_DEV(dev, &pdev->dev);
11819
11820         bp->dev = dev;
11821         bp->pdev = pdev;
11822
11823         rc = pci_enable_device(pdev);
11824         if (rc) {
11825                 dev_err(&bp->pdev->dev,
11826                         "Cannot enable PCI device, aborting\n");
11827                 goto err_out;
11828         }
11829
11830         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11831                 dev_err(&bp->pdev->dev,
11832                         "Cannot find PCI device base address, aborting\n");
11833                 rc = -ENODEV;
11834                 goto err_out_disable;
11835         }
11836
11837         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11838                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
11839                 rc = -ENODEV;
11840                 goto err_out_disable;
11841         }
11842
11843         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11844         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11845             PCICFG_REVESION_ID_ERROR_VAL) {
11846                 pr_err("PCI device error, probably due to fan failure, aborting\n");
11847                 rc = -ENODEV;
11848                 goto err_out_disable;
11849         }
11850
11851         if (atomic_read(&pdev->enable_cnt) == 1) {
11852                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11853                 if (rc) {
11854                         dev_err(&bp->pdev->dev,
11855                                 "Cannot obtain PCI resources, aborting\n");
11856                         goto err_out_disable;
11857                 }
11858
11859                 pci_set_master(pdev);
11860                 pci_save_state(pdev);
11861         }
11862
11863         if (IS_PF(bp)) {
11864                 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11865                 if (bp->pm_cap == 0) {
11866                         dev_err(&bp->pdev->dev,
11867                                 "Cannot find power management capability, aborting\n");
11868                         rc = -EIO;
11869                         goto err_out_release;
11870                 }
11871         }
11872
11873         if (!pci_is_pcie(pdev)) {
11874                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11875                 rc = -EIO;
11876                 goto err_out_release;
11877         }
11878
11879         rc = bnx2x_set_coherency_mask(bp);
11880         if (rc)
11881                 goto err_out_release;
11882
11883         dev->mem_start = pci_resource_start(pdev, 0);
11884         dev->base_addr = dev->mem_start;
11885         dev->mem_end = pci_resource_end(pdev, 0);
11886
11887         dev->irq = pdev->irq;
11888
11889         bp->regview = pci_ioremap_bar(pdev, 0);
11890         if (!bp->regview) {
11891                 dev_err(&bp->pdev->dev,
11892                         "Cannot map register space, aborting\n");
11893                 rc = -ENOMEM;
11894                 goto err_out_release;
11895         }
11896
11897         /* In E1/E1H use pci device function given by kernel.
11898          * In E2/E3 read physical function from ME register since these chips
11899          * support Physical Device Assignment where kernel BDF maybe arbitrary
11900          * (depending on hypervisor).
11901          */
11902         if (chip_is_e1x)
11903                 bp->pf_num = PCI_FUNC(pdev->devfn);
11904         else {/* chip is E2/3*/
11905                 pci_read_config_dword(bp->pdev,
11906                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
11907                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11908                     ME_REG_ABS_PF_NUM_SHIFT);
11909         }
11910         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11911
11912         bnx2x_set_power_state(bp, PCI_D0);
11913
11914         /* clean indirect addresses */
11915         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11916                                PCICFG_VENDOR_ID_OFFSET);
11917         /*
11918          * Clean the following indirect addresses for all functions since it
11919          * is not used by the driver.
11920          */
11921         if (IS_PF(bp)) {
11922                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11923                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11924                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11925                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11926
11927                 if (chip_is_e1x) {
11928                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11929                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11930                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11931                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11932                 }
11933
11934                 /* Enable internal target-read (in case we are probed after PF
11935                  * FLR). Must be done prior to any BAR read access. Only for
11936                  * 57712 and up
11937                  */
11938                 if (!chip_is_e1x)
11939                         REG_WR(bp,
11940                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11941         }
11942
11943         dev->watchdog_timeo = TX_TIMEOUT;
11944
11945         dev->netdev_ops = &bnx2x_netdev_ops;
11946         bnx2x_set_ethtool_ops(dev);
11947
11948         dev->priv_flags |= IFF_UNICAST_FLT;
11949
11950         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11951                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11952                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11953                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11954
11955         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11956                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11957
11958         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11959         if (bp->flags & USING_DAC_FLAG)
11960                 dev->features |= NETIF_F_HIGHDMA;
11961
11962         /* Add Loopback capability to the device */
11963         dev->hw_features |= NETIF_F_LOOPBACK;
11964
11965 #ifdef BCM_DCBNL
11966         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11967 #endif
11968
11969         /* get_port_hwinfo() will set prtad and mmds properly */
11970         bp->mdio.prtad = MDIO_PRTAD_NONE;
11971         bp->mdio.mmds = 0;
11972         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11973         bp->mdio.dev = dev;
11974         bp->mdio.mdio_read = bnx2x_mdio_read;
11975         bp->mdio.mdio_write = bnx2x_mdio_write;
11976
11977         return 0;
11978
11979 err_out_release:
11980         if (atomic_read(&pdev->enable_cnt) == 1)
11981                 pci_release_regions(pdev);
11982
11983 err_out_disable:
11984         pci_disable_device(pdev);
11985         pci_set_drvdata(pdev, NULL);
11986
11987 err_out:
11988         return rc;
11989 }
11990
11991 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
11992 {
11993         u32 val = 0;
11994
11995         pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
11996         *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11997
11998         /* return value of 1=2.5GHz 2=5GHz */
11999         *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12000 }
12001
12002 static int bnx2x_check_firmware(struct bnx2x *bp)
12003 {
12004         const struct firmware *firmware = bp->firmware;
12005         struct bnx2x_fw_file_hdr *fw_hdr;
12006         struct bnx2x_fw_file_section *sections;
12007         u32 offset, len, num_ops;
12008         u16 *ops_offsets;
12009         int i;
12010         const u8 *fw_ver;
12011
12012         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12013                 BNX2X_ERR("Wrong FW size\n");
12014                 return -EINVAL;
12015         }
12016
12017         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12018         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12019
12020         /* Make sure none of the offsets and sizes make us read beyond
12021          * the end of the firmware data */
12022         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12023                 offset = be32_to_cpu(sections[i].offset);
12024                 len = be32_to_cpu(sections[i].len);
12025                 if (offset + len > firmware->size) {
12026                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12027                         return -EINVAL;
12028                 }
12029         }
12030
12031         /* Likewise for the init_ops offsets */
12032         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12033         ops_offsets = (u16 *)(firmware->data + offset);
12034         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12035
12036         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12037                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12038                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12039                         return -EINVAL;
12040                 }
12041         }
12042
12043         /* Check FW version */
12044         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12045         fw_ver = firmware->data + offset;
12046         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12047             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12048             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12049             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12050                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12051                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12052                        BCM_5710_FW_MAJOR_VERSION,
12053                        BCM_5710_FW_MINOR_VERSION,
12054                        BCM_5710_FW_REVISION_VERSION,
12055                        BCM_5710_FW_ENGINEERING_VERSION);
12056                 return -EINVAL;
12057         }
12058
12059         return 0;
12060 }
12061
12062 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12063 {
12064         const __be32 *source = (const __be32 *)_source;
12065         u32 *target = (u32 *)_target;
12066         u32 i;
12067
12068         for (i = 0; i < n/4; i++)
12069                 target[i] = be32_to_cpu(source[i]);
12070 }
12071
12072 /*
12073    Ops array is stored in the following format:
12074    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12075  */
12076 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12077 {
12078         const __be32 *source = (const __be32 *)_source;
12079         struct raw_op *target = (struct raw_op *)_target;
12080         u32 i, j, tmp;
12081
12082         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12083                 tmp = be32_to_cpu(source[j]);
12084                 target[i].op = (tmp >> 24) & 0xff;
12085                 target[i].offset = tmp & 0xffffff;
12086                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12087         }
12088 }
12089
12090 /* IRO array is stored in the following format:
12091  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12092  */
12093 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12094 {
12095         const __be32 *source = (const __be32 *)_source;
12096         struct iro *target = (struct iro *)_target;
12097         u32 i, j, tmp;
12098
12099         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12100                 target[i].base = be32_to_cpu(source[j]);
12101                 j++;
12102                 tmp = be32_to_cpu(source[j]);
12103                 target[i].m1 = (tmp >> 16) & 0xffff;
12104                 target[i].m2 = tmp & 0xffff;
12105                 j++;
12106                 tmp = be32_to_cpu(source[j]);
12107                 target[i].m3 = (tmp >> 16) & 0xffff;
12108                 target[i].size = tmp & 0xffff;
12109                 j++;
12110         }
12111 }
12112
12113 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12114 {
12115         const __be16 *source = (const __be16 *)_source;
12116         u16 *target = (u16 *)_target;
12117         u32 i;
12118
12119         for (i = 0; i < n/2; i++)
12120                 target[i] = be16_to_cpu(source[i]);
12121 }
12122
12123 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12124 do {                                                                    \
12125         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12126         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12127         if (!bp->arr)                                                   \
12128                 goto lbl;                                               \
12129         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12130              (u8 *)bp->arr, len);                                       \
12131 } while (0)
12132
12133 static int bnx2x_init_firmware(struct bnx2x *bp)
12134 {
12135         const char *fw_file_name;
12136         struct bnx2x_fw_file_hdr *fw_hdr;
12137         int rc;
12138
12139         if (bp->firmware)
12140                 return 0;
12141
12142         if (CHIP_IS_E1(bp))
12143                 fw_file_name = FW_FILE_NAME_E1;
12144         else if (CHIP_IS_E1H(bp))
12145                 fw_file_name = FW_FILE_NAME_E1H;
12146         else if (!CHIP_IS_E1x(bp))
12147                 fw_file_name = FW_FILE_NAME_E2;
12148         else {
12149                 BNX2X_ERR("Unsupported chip revision\n");
12150                 return -EINVAL;
12151         }
12152         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12153
12154         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12155         if (rc) {
12156                 BNX2X_ERR("Can't load firmware file %s\n",
12157                           fw_file_name);
12158                 goto request_firmware_exit;
12159         }
12160
12161         rc = bnx2x_check_firmware(bp);
12162         if (rc) {
12163                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12164                 goto request_firmware_exit;
12165         }
12166
12167         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12168
12169         /* Initialize the pointers to the init arrays */
12170         /* Blob */
12171         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12172
12173         /* Opcodes */
12174         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12175
12176         /* Offsets */
12177         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12178                             be16_to_cpu_n);
12179
12180         /* STORMs firmware */
12181         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12182                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12183         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12184                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12185         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12186                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12187         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12188                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12189         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12190                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12191         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12192                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12193         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12194                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12195         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12196                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12197         /* IRO */
12198         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12199
12200         return 0;
12201
12202 iro_alloc_err:
12203         kfree(bp->init_ops_offsets);
12204 init_offsets_alloc_err:
12205         kfree(bp->init_ops);
12206 init_ops_alloc_err:
12207         kfree(bp->init_data);
12208 request_firmware_exit:
12209         release_firmware(bp->firmware);
12210         bp->firmware = NULL;
12211
12212         return rc;
12213 }
12214
12215 static void bnx2x_release_firmware(struct bnx2x *bp)
12216 {
12217         kfree(bp->init_ops_offsets);
12218         kfree(bp->init_ops);
12219         kfree(bp->init_data);
12220         release_firmware(bp->firmware);
12221         bp->firmware = NULL;
12222 }
12223
12224
12225 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12226         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12227         .init_hw_cmn      = bnx2x_init_hw_common,
12228         .init_hw_port     = bnx2x_init_hw_port,
12229         .init_hw_func     = bnx2x_init_hw_func,
12230
12231         .reset_hw_cmn     = bnx2x_reset_common,
12232         .reset_hw_port    = bnx2x_reset_port,
12233         .reset_hw_func    = bnx2x_reset_func,
12234
12235         .gunzip_init      = bnx2x_gunzip_init,
12236         .gunzip_end       = bnx2x_gunzip_end,
12237
12238         .init_fw          = bnx2x_init_firmware,
12239         .release_fw       = bnx2x_release_firmware,
12240 };
12241
12242 void bnx2x__init_func_obj(struct bnx2x *bp)
12243 {
12244         /* Prepare DMAE related driver resources */
12245         bnx2x_setup_dmae(bp);
12246
12247         bnx2x_init_func_obj(bp, &bp->func_obj,
12248                             bnx2x_sp(bp, func_rdata),
12249                             bnx2x_sp_mapping(bp, func_rdata),
12250                             bnx2x_sp(bp, func_afex_rdata),
12251                             bnx2x_sp_mapping(bp, func_afex_rdata),
12252                             &bnx2x_func_sp_drv);
12253 }
12254
12255 /* must be called after sriov-enable */
12256 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12257 {
12258         int cid_count = BNX2X_L2_MAX_CID(bp);
12259
12260         if (IS_SRIOV(bp))
12261                 cid_count += BNX2X_VF_CIDS;
12262
12263         if (CNIC_SUPPORT(bp))
12264                 cid_count += CNIC_CID_MAX;
12265
12266         return roundup(cid_count, QM_CID_ROUND);
12267 }
12268
12269 /**
12270  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12271  *
12272  * @dev:        pci device
12273  *
12274  */
12275 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12276                                      int cnic_cnt, bool is_vf)
12277 {
12278         int pos, index;
12279         u16 control = 0;
12280
12281         pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12282
12283         /*
12284          * If MSI-X is not supported - return number of SBs needed to support
12285          * one fast path queue: one FP queue + SB for CNIC
12286          */
12287         if (!pos) {
12288                 dev_info(&pdev->dev, "no msix capability found\n");
12289                 return 1 + cnic_cnt;
12290         }
12291         dev_info(&pdev->dev, "msix capability found\n");
12292
12293         /*
12294          * The value in the PCI configuration space is the index of the last
12295          * entry, namely one less than the actual size of the table, which is
12296          * exactly what we want to return from this function: number of all SBs
12297          * without the default SB.
12298          * For VFs there is no default SB, then we return (index+1).
12299          */
12300         pci_read_config_word(pdev, pos  + PCI_MSI_FLAGS, &control);
12301
12302         index = control & PCI_MSIX_FLAGS_QSIZE;
12303
12304         return is_vf ? index + 1 : index;
12305 }
12306
12307 static int set_max_cos_est(int chip_id)
12308 {
12309         switch (chip_id) {
12310         case BCM57710:
12311         case BCM57711:
12312         case BCM57711E:
12313                 return BNX2X_MULTI_TX_COS_E1X;
12314         case BCM57712:
12315         case BCM57712_MF:
12316         case BCM57712_VF:
12317                 return BNX2X_MULTI_TX_COS_E2_E3A0;
12318         case BCM57800:
12319         case BCM57800_MF:
12320         case BCM57800_VF:
12321         case BCM57810:
12322         case BCM57810_MF:
12323         case BCM57840_4_10:
12324         case BCM57840_2_20:
12325         case BCM57840_O:
12326         case BCM57840_MFO:
12327         case BCM57810_VF:
12328         case BCM57840_MF:
12329         case BCM57840_VF:
12330         case BCM57811:
12331         case BCM57811_MF:
12332         case BCM57811_VF:
12333                 return BNX2X_MULTI_TX_COS_E3B0;
12334                 return 1;
12335         default:
12336                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12337                 return -ENODEV;
12338         }
12339 }
12340
12341 static int set_is_vf(int chip_id)
12342 {
12343         switch (chip_id) {
12344         case BCM57712_VF:
12345         case BCM57800_VF:
12346         case BCM57810_VF:
12347         case BCM57840_VF:
12348         case BCM57811_VF:
12349                 return true;
12350         default:
12351                 return false;
12352         }
12353 }
12354
12355 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12356
12357 static int bnx2x_init_one(struct pci_dev *pdev,
12358                                     const struct pci_device_id *ent)
12359 {
12360         struct net_device *dev = NULL;
12361         struct bnx2x *bp;
12362         int pcie_width, pcie_speed;
12363         int rc, max_non_def_sbs;
12364         int rx_count, tx_count, rss_count, doorbell_size;
12365         int max_cos_est;
12366         bool is_vf;
12367         int cnic_cnt;
12368
12369         /* An estimated maximum supported CoS number according to the chip
12370          * version.
12371          * We will try to roughly estimate the maximum number of CoSes this chip
12372          * may support in order to minimize the memory allocated for Tx
12373          * netdev_queue's. This number will be accurately calculated during the
12374          * initialization of bp->max_cos based on the chip versions AND chip
12375          * revision in the bnx2x_init_bp().
12376          */
12377         max_cos_est = set_max_cos_est(ent->driver_data);
12378         if (max_cos_est < 0)
12379                 return max_cos_est;
12380         is_vf = set_is_vf(ent->driver_data);
12381         cnic_cnt = is_vf ? 0 : 1;
12382
12383         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12384
12385         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12386         rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12387
12388         if (rss_count < 1)
12389                 return -EINVAL;
12390
12391         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12392         rx_count = rss_count + cnic_cnt;
12393
12394         /* Maximum number of netdev Tx queues:
12395          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12396          */
12397         tx_count = rss_count * max_cos_est + cnic_cnt;
12398
12399         /* dev zeroed in init_etherdev */
12400         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12401         if (!dev)
12402                 return -ENOMEM;
12403
12404         bp = netdev_priv(dev);
12405
12406         bp->flags = 0;
12407         if (is_vf)
12408                 bp->flags |= IS_VF_FLAG;
12409
12410         bp->igu_sb_cnt = max_non_def_sbs;
12411         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12412         bp->msg_enable = debug;
12413         bp->cnic_support = cnic_cnt;
12414         bp->cnic_probe = bnx2x_cnic_probe;
12415
12416         pci_set_drvdata(pdev, dev);
12417
12418         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12419         if (rc < 0) {
12420                 free_netdev(dev);
12421                 return rc;
12422         }
12423
12424         BNX2X_DEV_INFO("This is a %s function\n",
12425                        IS_PF(bp) ? "physical" : "virtual");
12426         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12427         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12428         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12429                           tx_count, rx_count);
12430
12431         rc = bnx2x_init_bp(bp);
12432         if (rc)
12433                 goto init_one_exit;
12434
12435         /* Map doorbells here as we need the real value of bp->max_cos which
12436          * is initialized in bnx2x_init_bp() to determine the number of
12437          * l2 connections.
12438          */
12439         if (IS_VF(bp)) {
12440                 bnx2x_vf_map_doorbells(bp);
12441                 rc = bnx2x_vf_pci_alloc(bp);
12442                 if (rc)
12443                         goto init_one_exit;
12444         } else {
12445                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12446                 if (doorbell_size > pci_resource_len(pdev, 2)) {
12447                         dev_err(&bp->pdev->dev,
12448                                 "Cannot map doorbells, bar size too small, aborting\n");
12449                         rc = -ENOMEM;
12450                         goto init_one_exit;
12451                 }
12452                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12453                                                 doorbell_size);
12454         }
12455         if (!bp->doorbells) {
12456                 dev_err(&bp->pdev->dev,
12457                         "Cannot map doorbell space, aborting\n");
12458                 rc = -ENOMEM;
12459                 goto init_one_exit;
12460         }
12461
12462         if (IS_VF(bp)) {
12463                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12464                 if (rc)
12465                         goto init_one_exit;
12466         }
12467
12468         /* Enable SRIOV if capability found in configuration space.
12469          * Once the generic SR-IOV framework makes it in from the
12470          * pci tree this will be revised, to allow dynamic control
12471          * over the number of VFs. Right now, change the num of vfs
12472          * param below to enable SR-IOV.
12473          */
12474         rc = bnx2x_iov_init_one(bp, int_mode, 0/*num vfs*/);
12475         if (rc)
12476                 goto init_one_exit;
12477
12478         /* calc qm_cid_count */
12479         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12480         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12481
12482         /* disable FCOE L2 queue for E1x*/
12483         if (CHIP_IS_E1x(bp))
12484                 bp->flags |= NO_FCOE_FLAG;
12485
12486         /* disable FCOE for 57840 device, until FW supports it */
12487         switch (ent->driver_data) {
12488         case BCM57840_O:
12489         case BCM57840_4_10:
12490         case BCM57840_2_20:
12491         case BCM57840_MFO:
12492         case BCM57840_MF:
12493                 bp->flags |= NO_FCOE_FLAG;
12494         }
12495
12496         /* Set bp->num_queues for MSI-X mode*/
12497         bnx2x_set_num_queues(bp);
12498
12499         /* Configure interrupt mode: try to enable MSI-X/MSI if
12500          * needed.
12501          */
12502         rc = bnx2x_set_int_mode(bp);
12503         if (rc) {
12504                 dev_err(&pdev->dev, "Cannot set interrupts\n");
12505                 goto init_one_exit;
12506         }
12507
12508         /* register the net device */
12509         rc = register_netdev(dev);
12510         if (rc) {
12511                 dev_err(&pdev->dev, "Cannot register net device\n");
12512                 goto init_one_exit;
12513         }
12514         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12515
12516
12517         if (!NO_FCOE(bp)) {
12518                 /* Add storage MAC address */
12519                 rtnl_lock();
12520                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12521                 rtnl_unlock();
12522         }
12523
12524         bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12525         BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12526                        pcie_width, pcie_speed);
12527
12528         BNX2X_DEV_INFO(
12529                 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12530                     board_info[ent->driver_data].name,
12531                     (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12532                     pcie_width,
12533                     ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12534                      (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12535                     "5GHz (Gen2)" : "2.5GHz",
12536                     dev->base_addr, bp->pdev->irq, dev->dev_addr);
12537
12538         return 0;
12539
12540 init_one_exit:
12541         if (bp->regview)
12542                 iounmap(bp->regview);
12543
12544         if (IS_PF(bp) && bp->doorbells)
12545                 iounmap(bp->doorbells);
12546
12547         free_netdev(dev);
12548
12549         if (atomic_read(&pdev->enable_cnt) == 1)
12550                 pci_release_regions(pdev);
12551
12552         pci_disable_device(pdev);
12553         pci_set_drvdata(pdev, NULL);
12554
12555         return rc;
12556 }
12557
12558 static void bnx2x_remove_one(struct pci_dev *pdev)
12559 {
12560         struct net_device *dev = pci_get_drvdata(pdev);
12561         struct bnx2x *bp;
12562
12563         if (!dev) {
12564                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12565                 return;
12566         }
12567         bp = netdev_priv(dev);
12568
12569         /* Delete storage MAC address */
12570         if (!NO_FCOE(bp)) {
12571                 rtnl_lock();
12572                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12573                 rtnl_unlock();
12574         }
12575
12576 #ifdef BCM_DCBNL
12577         /* Delete app tlvs from dcbnl */
12578         bnx2x_dcbnl_update_applist(bp, true);
12579 #endif
12580
12581         unregister_netdev(dev);
12582
12583         /* Power on: we can't let PCI layer write to us while we are in D3 */
12584         if (IS_PF(bp))
12585                 bnx2x_set_power_state(bp, PCI_D0);
12586
12587         /* Disable MSI/MSI-X */
12588         bnx2x_disable_msi(bp);
12589
12590         /* Power off */
12591         if (IS_PF(bp))
12592                 bnx2x_set_power_state(bp, PCI_D3hot);
12593
12594         /* Make sure RESET task is not scheduled before continuing */
12595         cancel_delayed_work_sync(&bp->sp_rtnl_task);
12596
12597         bnx2x_iov_remove_one(bp);
12598
12599         /* send message via vfpf channel to release the resources of this vf */
12600         if (IS_VF(bp))
12601                 bnx2x_vfpf_release(bp);
12602
12603         if (bp->regview)
12604                 iounmap(bp->regview);
12605
12606         /* for vf doorbells are part of the regview and were unmapped along with
12607          * it. FW is only loaded by PF.
12608          */
12609         if (IS_PF(bp)) {
12610                 if (bp->doorbells)
12611                         iounmap(bp->doorbells);
12612
12613                 bnx2x_release_firmware(bp);
12614         }
12615         bnx2x_free_mem_bp(bp);
12616
12617         free_netdev(dev);
12618
12619         if (atomic_read(&pdev->enable_cnt) == 1)
12620                 pci_release_regions(pdev);
12621
12622         pci_disable_device(pdev);
12623         pci_set_drvdata(pdev, NULL);
12624 }
12625
12626 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12627 {
12628         int i;
12629
12630         bp->state = BNX2X_STATE_ERROR;
12631
12632         bp->rx_mode = BNX2X_RX_MODE_NONE;
12633
12634         if (CNIC_LOADED(bp))
12635                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12636
12637         /* Stop Tx */
12638         bnx2x_tx_disable(bp);
12639
12640         bnx2x_netif_stop(bp, 0);
12641         /* Delete all NAPI objects */
12642         bnx2x_del_all_napi(bp);
12643         if (CNIC_LOADED(bp))
12644                 bnx2x_del_all_napi_cnic(bp);
12645
12646         del_timer_sync(&bp->timer);
12647
12648         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12649
12650         /* Release IRQs */
12651         bnx2x_free_irq(bp);
12652
12653         /* Free SKBs, SGEs, TPA pool and driver internals */
12654         bnx2x_free_skbs(bp);
12655
12656         for_each_rx_queue(bp, i)
12657                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12658
12659         bnx2x_free_mem(bp);
12660
12661         bp->state = BNX2X_STATE_CLOSED;
12662
12663         netif_carrier_off(bp->dev);
12664
12665         return 0;
12666 }
12667
12668 static void bnx2x_eeh_recover(struct bnx2x *bp)
12669 {
12670         u32 val;
12671
12672         mutex_init(&bp->port.phy_mutex);
12673
12674
12675         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12676         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12677                 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12678                 BNX2X_ERR("BAD MCP validity signature\n");
12679 }
12680
12681 /**
12682  * bnx2x_io_error_detected - called when PCI error is detected
12683  * @pdev: Pointer to PCI device
12684  * @state: The current pci connection state
12685  *
12686  * This function is called after a PCI bus error affecting
12687  * this device has been detected.
12688  */
12689 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12690                                                 pci_channel_state_t state)
12691 {
12692         struct net_device *dev = pci_get_drvdata(pdev);
12693         struct bnx2x *bp = netdev_priv(dev);
12694
12695         rtnl_lock();
12696
12697         netif_device_detach(dev);
12698
12699         if (state == pci_channel_io_perm_failure) {
12700                 rtnl_unlock();
12701                 return PCI_ERS_RESULT_DISCONNECT;
12702         }
12703
12704         if (netif_running(dev))
12705                 bnx2x_eeh_nic_unload(bp);
12706
12707         pci_disable_device(pdev);
12708
12709         rtnl_unlock();
12710
12711         /* Request a slot reset */
12712         return PCI_ERS_RESULT_NEED_RESET;
12713 }
12714
12715 /**
12716  * bnx2x_io_slot_reset - called after the PCI bus has been reset
12717  * @pdev: Pointer to PCI device
12718  *
12719  * Restart the card from scratch, as if from a cold-boot.
12720  */
12721 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12722 {
12723         struct net_device *dev = pci_get_drvdata(pdev);
12724         struct bnx2x *bp = netdev_priv(dev);
12725
12726         rtnl_lock();
12727
12728         if (pci_enable_device(pdev)) {
12729                 dev_err(&pdev->dev,
12730                         "Cannot re-enable PCI device after reset\n");
12731                 rtnl_unlock();
12732                 return PCI_ERS_RESULT_DISCONNECT;
12733         }
12734
12735         pci_set_master(pdev);
12736         pci_restore_state(pdev);
12737
12738         if (netif_running(dev))
12739                 bnx2x_set_power_state(bp, PCI_D0);
12740
12741         rtnl_unlock();
12742
12743         return PCI_ERS_RESULT_RECOVERED;
12744 }
12745
12746 /**
12747  * bnx2x_io_resume - called when traffic can start flowing again
12748  * @pdev: Pointer to PCI device
12749  *
12750  * This callback is called when the error recovery driver tells us that
12751  * its OK to resume normal operation.
12752  */
12753 static void bnx2x_io_resume(struct pci_dev *pdev)
12754 {
12755         struct net_device *dev = pci_get_drvdata(pdev);
12756         struct bnx2x *bp = netdev_priv(dev);
12757
12758         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12759                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12760                 return;
12761         }
12762
12763         rtnl_lock();
12764
12765         bnx2x_eeh_recover(bp);
12766
12767         if (netif_running(dev))
12768                 bnx2x_nic_load(bp, LOAD_NORMAL);
12769
12770         netif_device_attach(dev);
12771
12772         rtnl_unlock();
12773 }
12774
12775 static const struct pci_error_handlers bnx2x_err_handler = {
12776         .error_detected = bnx2x_io_error_detected,
12777         .slot_reset     = bnx2x_io_slot_reset,
12778         .resume         = bnx2x_io_resume,
12779 };
12780
12781 static struct pci_driver bnx2x_pci_driver = {
12782         .name        = DRV_MODULE_NAME,
12783         .id_table    = bnx2x_pci_tbl,
12784         .probe       = bnx2x_init_one,
12785         .remove      = bnx2x_remove_one,
12786         .suspend     = bnx2x_suspend,
12787         .resume      = bnx2x_resume,
12788         .err_handler = &bnx2x_err_handler,
12789 };
12790
12791 static int __init bnx2x_init(void)
12792 {
12793         int ret;
12794
12795         pr_info("%s", version);
12796
12797         bnx2x_wq = create_singlethread_workqueue("bnx2x");
12798         if (bnx2x_wq == NULL) {
12799                 pr_err("Cannot create workqueue\n");
12800                 return -ENOMEM;
12801         }
12802
12803         ret = pci_register_driver(&bnx2x_pci_driver);
12804         if (ret) {
12805                 pr_err("Cannot register driver\n");
12806                 destroy_workqueue(bnx2x_wq);
12807         }
12808         return ret;
12809 }
12810
12811 static void __exit bnx2x_cleanup(void)
12812 {
12813         struct list_head *pos, *q;
12814         pci_unregister_driver(&bnx2x_pci_driver);
12815
12816         destroy_workqueue(bnx2x_wq);
12817
12818         /* Free globablly allocated resources */
12819         list_for_each_safe(pos, q, &bnx2x_prev_list) {
12820                 struct bnx2x_prev_path_list *tmp =
12821                         list_entry(pos, struct bnx2x_prev_path_list, list);
12822                 list_del(pos);
12823                 kfree(tmp);
12824         }
12825 }
12826
12827 void bnx2x_notify_link_changed(struct bnx2x *bp)
12828 {
12829         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12830 }
12831
12832 module_init(bnx2x_init);
12833 module_exit(bnx2x_cleanup);
12834
12835 /**
12836  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12837  *
12838  * @bp:         driver handle
12839  * @set:        set or clear the CAM entry
12840  *
12841  * This function will wait until the ramdord completion returns.
12842  * Return 0 if success, -ENODEV if ramrod doesn't return.
12843  */
12844 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12845 {
12846         unsigned long ramrod_flags = 0;
12847
12848         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12849         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12850                                  &bp->iscsi_l2_mac_obj, true,
12851                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12852 }
12853
12854 /* count denotes the number of new completions we have seen */
12855 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12856 {
12857         struct eth_spe *spe;
12858         int cxt_index, cxt_offset;
12859
12860 #ifdef BNX2X_STOP_ON_ERROR
12861         if (unlikely(bp->panic))
12862                 return;
12863 #endif
12864
12865         spin_lock_bh(&bp->spq_lock);
12866         BUG_ON(bp->cnic_spq_pending < count);
12867         bp->cnic_spq_pending -= count;
12868
12869
12870         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12871                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12872                                 & SPE_HDR_CONN_TYPE) >>
12873                                 SPE_HDR_CONN_TYPE_SHIFT;
12874                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12875                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12876
12877                 /* Set validation for iSCSI L2 client before sending SETUP
12878                  *  ramrod
12879                  */
12880                 if (type == ETH_CONNECTION_TYPE) {
12881                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12882                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12883                                         ILT_PAGE_CIDS;
12884                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12885                                         (cxt_index * ILT_PAGE_CIDS);
12886                                 bnx2x_set_ctx_validation(bp,
12887                                         &bp->context[cxt_index].
12888                                                          vcxt[cxt_offset].eth,
12889                                         BNX2X_ISCSI_ETH_CID(bp));
12890                         }
12891                 }
12892
12893                 /*
12894                  * There may be not more than 8 L2, not more than 8 L5 SPEs
12895                  * and in the air. We also check that number of outstanding
12896                  * COMMON ramrods is not more than the EQ and SPQ can
12897                  * accommodate.
12898                  */
12899                 if (type == ETH_CONNECTION_TYPE) {
12900                         if (!atomic_read(&bp->cq_spq_left))
12901                                 break;
12902                         else
12903                                 atomic_dec(&bp->cq_spq_left);
12904                 } else if (type == NONE_CONNECTION_TYPE) {
12905                         if (!atomic_read(&bp->eq_spq_left))
12906                                 break;
12907                         else
12908                                 atomic_dec(&bp->eq_spq_left);
12909                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12910                            (type == FCOE_CONNECTION_TYPE)) {
12911                         if (bp->cnic_spq_pending >=
12912                             bp->cnic_eth_dev.max_kwqe_pending)
12913                                 break;
12914                         else
12915                                 bp->cnic_spq_pending++;
12916                 } else {
12917                         BNX2X_ERR("Unknown SPE type: %d\n", type);
12918                         bnx2x_panic();
12919                         break;
12920                 }
12921
12922                 spe = bnx2x_sp_get_next(bp);
12923                 *spe = *bp->cnic_kwq_cons;
12924
12925                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12926                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12927
12928                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12929                         bp->cnic_kwq_cons = bp->cnic_kwq;
12930                 else
12931                         bp->cnic_kwq_cons++;
12932         }
12933         bnx2x_sp_prod_update(bp);
12934         spin_unlock_bh(&bp->spq_lock);
12935 }
12936
12937 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12938                                struct kwqe_16 *kwqes[], u32 count)
12939 {
12940         struct bnx2x *bp = netdev_priv(dev);
12941         int i;
12942
12943 #ifdef BNX2X_STOP_ON_ERROR
12944         if (unlikely(bp->panic)) {
12945                 BNX2X_ERR("Can't post to SP queue while panic\n");
12946                 return -EIO;
12947         }
12948 #endif
12949
12950         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12951             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12952                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12953                 return -EAGAIN;
12954         }
12955
12956         spin_lock_bh(&bp->spq_lock);
12957
12958         for (i = 0; i < count; i++) {
12959                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12960
12961                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12962                         break;
12963
12964                 *bp->cnic_kwq_prod = *spe;
12965
12966                 bp->cnic_kwq_pending++;
12967
12968                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12969                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
12970                    spe->data.update_data_addr.hi,
12971                    spe->data.update_data_addr.lo,
12972                    bp->cnic_kwq_pending);
12973
12974                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12975                         bp->cnic_kwq_prod = bp->cnic_kwq;
12976                 else
12977                         bp->cnic_kwq_prod++;
12978         }
12979
12980         spin_unlock_bh(&bp->spq_lock);
12981
12982         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12983                 bnx2x_cnic_sp_post(bp, 0);
12984
12985         return i;
12986 }
12987
12988 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12989 {
12990         struct cnic_ops *c_ops;
12991         int rc = 0;
12992
12993         mutex_lock(&bp->cnic_mutex);
12994         c_ops = rcu_dereference_protected(bp->cnic_ops,
12995                                           lockdep_is_held(&bp->cnic_mutex));
12996         if (c_ops)
12997                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12998         mutex_unlock(&bp->cnic_mutex);
12999
13000         return rc;
13001 }
13002
13003 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13004 {
13005         struct cnic_ops *c_ops;
13006         int rc = 0;
13007
13008         rcu_read_lock();
13009         c_ops = rcu_dereference(bp->cnic_ops);
13010         if (c_ops)
13011                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13012         rcu_read_unlock();
13013
13014         return rc;
13015 }
13016
13017 /*
13018  * for commands that have no data
13019  */
13020 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13021 {
13022         struct cnic_ctl_info ctl = {0};
13023
13024         ctl.cmd = cmd;
13025
13026         return bnx2x_cnic_ctl_send(bp, &ctl);
13027 }
13028
13029 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13030 {
13031         struct cnic_ctl_info ctl = {0};
13032
13033         /* first we tell CNIC and only then we count this as a completion */
13034         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13035         ctl.data.comp.cid = cid;
13036         ctl.data.comp.error = err;
13037
13038         bnx2x_cnic_ctl_send_bh(bp, &ctl);
13039         bnx2x_cnic_sp_post(bp, 0);
13040 }
13041
13042
13043 /* Called with netif_addr_lock_bh() taken.
13044  * Sets an rx_mode config for an iSCSI ETH client.
13045  * Doesn't block.
13046  * Completion should be checked outside.
13047  */
13048 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13049 {
13050         unsigned long accept_flags = 0, ramrod_flags = 0;
13051         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13052         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13053
13054         if (start) {
13055                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13056                  * because it's the only way for UIO Queue to accept
13057                  * multicasts (in non-promiscuous mode only one Queue per
13058                  * function will receive multicast packets (leading in our
13059                  * case).
13060                  */
13061                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13062                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13063                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13064                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13065
13066                 /* Clear STOP_PENDING bit if START is requested */
13067                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13068
13069                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13070         } else
13071                 /* Clear START_PENDING bit if STOP is requested */
13072                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13073
13074         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13075                 set_bit(sched_state, &bp->sp_state);
13076         else {
13077                 __set_bit(RAMROD_RX, &ramrod_flags);
13078                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13079                                     ramrod_flags);
13080         }
13081 }
13082
13083
13084 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13085 {
13086         struct bnx2x *bp = netdev_priv(dev);
13087         int rc = 0;
13088
13089         switch (ctl->cmd) {
13090         case DRV_CTL_CTXTBL_WR_CMD: {
13091                 u32 index = ctl->data.io.offset;
13092                 dma_addr_t addr = ctl->data.io.dma_addr;
13093
13094                 bnx2x_ilt_wr(bp, index, addr);
13095                 break;
13096         }
13097
13098         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13099                 int count = ctl->data.credit.credit_count;
13100
13101                 bnx2x_cnic_sp_post(bp, count);
13102                 break;
13103         }
13104
13105         /* rtnl_lock is held.  */
13106         case DRV_CTL_START_L2_CMD: {
13107                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13108                 unsigned long sp_bits = 0;
13109
13110                 /* Configure the iSCSI classification object */
13111                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13112                                    cp->iscsi_l2_client_id,
13113                                    cp->iscsi_l2_cid, BP_FUNC(bp),
13114                                    bnx2x_sp(bp, mac_rdata),
13115                                    bnx2x_sp_mapping(bp, mac_rdata),
13116                                    BNX2X_FILTER_MAC_PENDING,
13117                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13118                                    &bp->macs_pool);
13119
13120                 /* Set iSCSI MAC address */
13121                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13122                 if (rc)
13123                         break;
13124
13125                 mmiowb();
13126                 barrier();
13127
13128                 /* Start accepting on iSCSI L2 ring */
13129
13130                 netif_addr_lock_bh(dev);
13131                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13132                 netif_addr_unlock_bh(dev);
13133
13134                 /* bits to wait on */
13135                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13136                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13137
13138                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13139                         BNX2X_ERR("rx_mode completion timed out!\n");
13140
13141                 break;
13142         }
13143
13144         /* rtnl_lock is held.  */
13145         case DRV_CTL_STOP_L2_CMD: {
13146                 unsigned long sp_bits = 0;
13147
13148                 /* Stop accepting on iSCSI L2 ring */
13149                 netif_addr_lock_bh(dev);
13150                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13151                 netif_addr_unlock_bh(dev);
13152
13153                 /* bits to wait on */
13154                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13155                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13156
13157                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13158                         BNX2X_ERR("rx_mode completion timed out!\n");
13159
13160                 mmiowb();
13161                 barrier();
13162
13163                 /* Unset iSCSI L2 MAC */
13164                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13165                                         BNX2X_ISCSI_ETH_MAC, true);
13166                 break;
13167         }
13168         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13169                 int count = ctl->data.credit.credit_count;
13170
13171                 smp_mb__before_atomic_inc();
13172                 atomic_add(count, &bp->cq_spq_left);
13173                 smp_mb__after_atomic_inc();
13174                 break;
13175         }
13176         case DRV_CTL_ULP_REGISTER_CMD: {
13177                 int ulp_type = ctl->data.register_data.ulp_type;
13178
13179                 if (CHIP_IS_E3(bp)) {
13180                         int idx = BP_FW_MB_IDX(bp);
13181                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13182                         int path = BP_PATH(bp);
13183                         int port = BP_PORT(bp);
13184                         int i;
13185                         u32 scratch_offset;
13186                         u32 *host_addr;
13187
13188                         /* first write capability to shmem2 */
13189                         if (ulp_type == CNIC_ULP_ISCSI)
13190                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13191                         else if (ulp_type == CNIC_ULP_FCOE)
13192                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13193                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13194
13195                         if ((ulp_type != CNIC_ULP_FCOE) ||
13196                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13197                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
13198                                 break;
13199
13200                         /* if reached here - should write fcoe capabilities */
13201                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13202                         if (!scratch_offset)
13203                                 break;
13204                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
13205                                                    fcoe_features[path][port]);
13206                         host_addr = (u32 *) &(ctl->data.register_data.
13207                                               fcoe_features);
13208                         for (i = 0; i < sizeof(struct fcoe_capabilities);
13209                              i += 4)
13210                                 REG_WR(bp, scratch_offset + i,
13211                                        *(host_addr + i/4));
13212                 }
13213                 break;
13214         }
13215
13216         case DRV_CTL_ULP_UNREGISTER_CMD: {
13217                 int ulp_type = ctl->data.ulp_type;
13218
13219                 if (CHIP_IS_E3(bp)) {
13220                         int idx = BP_FW_MB_IDX(bp);
13221                         u32 cap;
13222
13223                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13224                         if (ulp_type == CNIC_ULP_ISCSI)
13225                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13226                         else if (ulp_type == CNIC_ULP_FCOE)
13227                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13228                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13229                 }
13230                 break;
13231         }
13232
13233         default:
13234                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13235                 rc = -EINVAL;
13236         }
13237
13238         return rc;
13239 }
13240
13241 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13242 {
13243         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13244
13245         if (bp->flags & USING_MSIX_FLAG) {
13246                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13247                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13248                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13249         } else {
13250                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13251                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13252         }
13253         if (!CHIP_IS_E1x(bp))
13254                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13255         else
13256                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13257
13258         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
13259         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13260         cp->irq_arr[1].status_blk = bp->def_status_blk;
13261         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13262         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13263
13264         cp->num_irq = 2;
13265 }
13266
13267 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13268 {
13269         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13270
13271
13272         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13273                              bnx2x_cid_ilt_lines(bp);
13274         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13275         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13276         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13277
13278         if (NO_ISCSI_OOO(bp))
13279                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13280 }
13281
13282 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13283                                void *data)
13284 {
13285         struct bnx2x *bp = netdev_priv(dev);
13286         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13287         int rc;
13288
13289         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13290
13291         if (ops == NULL) {
13292                 BNX2X_ERR("NULL ops received\n");
13293                 return -EINVAL;
13294         }
13295
13296         if (!CNIC_SUPPORT(bp)) {
13297                 BNX2X_ERR("Can't register CNIC when not supported\n");
13298                 return -EOPNOTSUPP;
13299         }
13300
13301         if (!CNIC_LOADED(bp)) {
13302                 rc = bnx2x_load_cnic(bp);
13303                 if (rc) {
13304                         BNX2X_ERR("CNIC-related load failed\n");
13305                         return rc;
13306                 }
13307
13308         }
13309
13310         bp->cnic_enabled = true;
13311
13312         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13313         if (!bp->cnic_kwq)
13314                 return -ENOMEM;
13315
13316         bp->cnic_kwq_cons = bp->cnic_kwq;
13317         bp->cnic_kwq_prod = bp->cnic_kwq;
13318         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13319
13320         bp->cnic_spq_pending = 0;
13321         bp->cnic_kwq_pending = 0;
13322
13323         bp->cnic_data = data;
13324
13325         cp->num_irq = 0;
13326         cp->drv_state |= CNIC_DRV_STATE_REGD;
13327         cp->iro_arr = bp->iro_arr;
13328
13329         bnx2x_setup_cnic_irq_info(bp);
13330
13331         rcu_assign_pointer(bp->cnic_ops, ops);
13332
13333         return 0;
13334 }
13335
13336 static int bnx2x_unregister_cnic(struct net_device *dev)
13337 {
13338         struct bnx2x *bp = netdev_priv(dev);
13339         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13340
13341         mutex_lock(&bp->cnic_mutex);
13342         cp->drv_state = 0;
13343         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13344         mutex_unlock(&bp->cnic_mutex);
13345         synchronize_rcu();
13346         kfree(bp->cnic_kwq);
13347         bp->cnic_kwq = NULL;
13348
13349         return 0;
13350 }
13351
13352 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13353 {
13354         struct bnx2x *bp = netdev_priv(dev);
13355         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13356
13357         /* If both iSCSI and FCoE are disabled - return NULL in
13358          * order to indicate CNIC that it should not try to work
13359          * with this device.
13360          */
13361         if (NO_ISCSI(bp) && NO_FCOE(bp))
13362                 return NULL;
13363
13364         cp->drv_owner = THIS_MODULE;
13365         cp->chip_id = CHIP_ID(bp);
13366         cp->pdev = bp->pdev;
13367         cp->io_base = bp->regview;
13368         cp->io_base2 = bp->doorbells;
13369         cp->max_kwqe_pending = 8;
13370         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13371         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13372                              bnx2x_cid_ilt_lines(bp);
13373         cp->ctx_tbl_len = CNIC_ILT_LINES;
13374         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13375         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13376         cp->drv_ctl = bnx2x_drv_ctl;
13377         cp->drv_register_cnic = bnx2x_register_cnic;
13378         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13379         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13380         cp->iscsi_l2_client_id =
13381                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13382         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13383
13384         if (NO_ISCSI_OOO(bp))
13385                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13386
13387         if (NO_ISCSI(bp))
13388                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13389
13390         if (NO_FCOE(bp))
13391                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13392
13393         BNX2X_DEV_INFO(
13394                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13395            cp->ctx_blk_size,
13396            cp->ctx_tbl_offset,
13397            cp->ctx_tbl_len,
13398            cp->starting_cid);
13399         return cp;
13400 }
13401
13402 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13403 {
13404         struct bnx2x *bp = fp->bp;
13405         u32 offset = BAR_USTRORM_INTMEM;
13406
13407         if (IS_VF(bp))
13408                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13409         else if (!CHIP_IS_E1x(bp))
13410                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13411         else
13412                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13413
13414         return offset;
13415 }
13416
13417 /* called only on E1H or E2.
13418  * When pretending to be PF, the pretend value is the function number 0...7
13419  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13420  * combination
13421  */
13422 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13423 {
13424         u32 pretend_reg;
13425
13426         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13427                 return -1;
13428
13429         /* get my own pretend register */
13430         pretend_reg = bnx2x_get_pretend_reg(bp);
13431         REG_WR(bp, pretend_reg, pretend_func_val);
13432         REG_RD(bp, pretend_reg);
13433         return 0;
13434 }