drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/aer.h>
  31 #include <linux/init.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/bitops.h>
  37 #include <linux/irq.h>
  38 #include <linux/delay.h>
  39 #include <asm/byteorder.h>
  40 #include <linux/time.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mii.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/crash_dump.h>
  45 #include <net/ip.h>
  46 #include <net/ipv6.h>
  47 #include <net/tcp.h>
  48 #include <net/vxlan.h>
  49 #include <net/checksum.h>
  50 #include <net/ip6_checksum.h>
  51 #include <linux/workqueue.h>
  52 #include <linux/crc32.h>
  53 #include <linux/crc32c.h>
  54 #include <linux/prefetch.h>
  55 #include <linux/zlib.h>
  56 #include <linux/io.h>
  57 #include <linux/semaphore.h>
  58 #include <linux/stringify.h>
  59 #include <linux/vmalloc.h>
  60
  61 #include "bnx2x.h"
  62 #include "bnx2x_init.h"
  63 #include "bnx2x_init_ops.h"
  64 #include "bnx2x_cmn.h"
  65 #include "bnx2x_vfpf.h"
  66 #include "bnx2x_dcb.h"
  67 #include "bnx2x_sp.h"
  68 #include <linux/firmware.h>
  69 #include "bnx2x_fw_file_hdr.h"
  70 /* FW files */
  71 #define FW_FILE_VERSION                                 \
  72         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  73         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  74         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  75         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  76 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  77 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  78 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  79
  80 /* Time in jiffies before concluding the transmitter is hung */
  81 #define TX_TIMEOUT              (5*HZ)
  82
  83 static char version[] =
  84         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  85         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  86
  87 MODULE_AUTHOR("Eliezer Tamir");
  88 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  89                    "BCM57710/57711/57711E/"
  90                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  91                    "57840/57840_MF Driver");
  92 MODULE_LICENSE("GPL");
  93 MODULE_VERSION(DRV_MODULE_VERSION);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  96 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  97
  98 int bnx2x_num_queues;
  99 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
 100 MODULE_PARM_DESC(num_queues,
 101                  " Set number of queues (default is as a number of CPUs)");
 102
 103 static int disable_tpa;
 104 module_param(disable_tpa, int, S_IRUGO);
 105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 106
 107 static int int_mode;
 108 module_param(int_mode, int, S_IRUGO);
 109 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 110                                 "(1 INT#x; 2 MSI)");
 111
 112 static int dropless_fc;
 113 module_param(dropless_fc, int, S_IRUGO);
 114 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 115
 116 static int mrrs = -1;
 117 module_param(mrrs, int, S_IRUGO);
 118 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 119
 120 static int debug;
 121 module_param(debug, int, S_IRUGO);
 122 MODULE_PARM_DESC(debug, " Default debug msglevel");
 123
 124 static struct workqueue_struct *bnx2x_wq;
 125 struct workqueue_struct *bnx2x_iov_wq;
 126
 127 struct bnx2x_mac_vals {
 128         u32 xmac_addr;
 129         u32 xmac_val;
 130         u32 emac_addr;
 131         u32 emac_val;
 132         u32 umac_addr[2];
 133         u32 umac_val[2];
 134         u32 bmac_addr;
 135         u32 bmac_val[2];
 136 };
 137
 138 enum bnx2x_board_type {
 139         BCM57710 = 0,
 140         BCM57711,
 141         BCM57711E,
 142         BCM57712,
 143         BCM57712_MF,
 144         BCM57712_VF,
 145         BCM57800,
 146         BCM57800_MF,
 147         BCM57800_VF,
 148         BCM57810,
 149         BCM57810_MF,
 150         BCM57810_VF,
 151         BCM57840_4_10,
 152         BCM57840_2_20,
 153         BCM57840_MF,
 154         BCM57840_VF,
 155         BCM57811,
 156         BCM57811_MF,
 157         BCM57840_O,
 158         BCM57840_MFO,
 159         BCM57811_VF
 160 };
 161
 162 /* indexed by board_type, above */
 163 static struct {
 164         char *name;
 165 } board_info[] = {
 166         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 167         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 168         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 169         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 170         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 171         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 172         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 173         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 174         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 175         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 176         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 177         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 178         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 179         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 180         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 181         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 182         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 183         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 184         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 185         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 186         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 187 };
 188
 189 #ifndef PCI_DEVICE_ID_NX2_57710
 190 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 191 #endif
 192 #ifndef PCI_DEVICE_ID_NX2_57711
 193 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 194 #endif
 195 #ifndef PCI_DEVICE_ID_NX2_57711E
 196 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 197 #endif
 198 #ifndef PCI_DEVICE_ID_NX2_57712
 199 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 200 #endif
 201 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 202 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 203 #endif
 204 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 205 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 206 #endif
 207 #ifndef PCI_DEVICE_ID_NX2_57800
 208 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 209 #endif
 210 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 211 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 212 #endif
 213 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 214 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 215 #endif
 216 #ifndef PCI_DEVICE_ID_NX2_57810
 217 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 218 #endif
 219 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 220 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 221 #endif
 222 #ifndef PCI_DEVICE_ID_NX2_57840_O
 223 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 224 #endif
 225 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 226 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 227 #endif
 228 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 229 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 230 #endif
 231 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 232 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 233 #endif
 234 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 235 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 236 #endif
 237 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 238 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 239 #endif
 240 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 241 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 242 #endif
 243 #ifndef PCI_DEVICE_ID_NX2_57811
 244 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 245 #endif
 246 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 247 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 248 #endif
 249 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 250 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 251 #endif
 252
 253 static const struct pci_device_id bnx2x_pci_tbl[] = {
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 275         { 0 }
 276 };
 277
 278 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 279
 280 /* Global resources for unloading a previously loaded device */
 281 #define BNX2X_PREV_WAIT_NEEDED 1
 282 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 283 static LIST_HEAD(bnx2x_prev_list);
 284
 285 /* Forward declaration */
 286 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 287 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 288 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 289
 290 /****************************************************************************
 291 * General service functions
 292 ****************************************************************************/
 293
 294 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 295
 296 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 297                                        u32 addr, dma_addr_t mapping)
 298 {
 299         REG_WR(bp,  addr, U64_LO(mapping));
 300         REG_WR(bp,  addr + 4, U64_HI(mapping));
 301 }
 302
 303 static void storm_memset_spq_addr(struct bnx2x *bp,
 304                                   dma_addr_t mapping, u16 abs_fid)
 305 {
 306         u32 addr = XSEM_REG_FAST_MEMORY +
 307                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 308
 309         __storm_memset_dma_mapping(bp, addr, mapping);
 310 }
 311
 312 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 313                                   u16 pf_id)
 314 {
 315         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 316                 pf_id);
 317         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 318                 pf_id);
 319         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 320                 pf_id);
 321         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 322                 pf_id);
 323 }
 324
 325 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 326                                  u8 enable)
 327 {
 328         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 329                 enable);
 330         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 331                 enable);
 332         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 333                 enable);
 334         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 335                 enable);
 336 }
 337
 338 static void storm_memset_eq_data(struct bnx2x *bp,
 339                                  struct event_ring_data *eq_data,
 340                                 u16 pfid)
 341 {
 342         size_t size = sizeof(struct event_ring_data);
 343
 344         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 345
 346         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 347 }
 348
 349 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 350                                  u16 pfid)
 351 {
 352         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 353         REG_WR16(bp, addr, eq_prod);
 354 }
 355
 356 /* used only at init
 357  * locking is done by mcp
 358  */
 359 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 360 {
 361         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 362         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 363         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 364                                PCICFG_VENDOR_ID_OFFSET);
 365 }
 366
 367 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 368 {
 369         u32 val;
 370
 371         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 372         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 373         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 374                                PCICFG_VENDOR_ID_OFFSET);
 375
 376         return val;
 377 }
 378
 379 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 380 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 381 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 382 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 383 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 384
 385 static void bnx2x_dp_dmae(struct bnx2x *bp,
 386                           struct dmae_command *dmae, int msglvl)
 387 {
 388         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 389         int i;
 390
 391         switch (dmae->opcode & DMAE_COMMAND_DST) {
 392         case DMAE_CMD_DST_PCI:
 393                 if (src_type == DMAE_CMD_SRC_PCI)
 394                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 395                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 396                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 397                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 398                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 399                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 400                            dmae->comp_val);
 401                 else
 402                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 403                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 404                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 405                            dmae->opcode, dmae->src_addr_lo >> 2,
 406                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 407                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 408                            dmae->comp_val);
 409                 break;
 410         case DMAE_CMD_DST_GRC:
 411                 if (src_type == DMAE_CMD_SRC_PCI)
 412                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 413                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 414                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 415                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 416                            dmae->len, dmae->dst_addr_lo >> 2,
 417                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 418                            dmae->comp_val);
 419                 else
 420                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 421                            "src [%08x], len [%d*4], dst [%08x]\n"
 422                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 423                            dmae->opcode, dmae->src_addr_lo >> 2,
 424                            dmae->len, dmae->dst_addr_lo >> 2,
 425                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 426                            dmae->comp_val);
 427                 break;
 428         default:
 429                 if (src_type == DMAE_CMD_SRC_PCI)
 430                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 431                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 432                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 433                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 434                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 435                            dmae->comp_val);
 436                 else
 437                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 438                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 439                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 440                            dmae->opcode, dmae->src_addr_lo >> 2,
 441                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 442                            dmae->comp_val);
 443                 break;
 444         }
 445
 446         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 447                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 448                    i, *(((u32 *)dmae) + i));
 449 }
 450
 451 /* copy command into DMAE command memory and set DMAE command go */
 452 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 453 {
 454         u32 cmd_offset;
 455         int i;
 456
 457         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 458         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 459                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 460         }
 461         REG_WR(bp, dmae_reg_go_c[idx], 1);
 462 }
 463
 464 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 465 {
 466         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 467                            DMAE_CMD_C_ENABLE);
 468 }
 469
 470 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 471 {
 472         return opcode & ~DMAE_CMD_SRC_RESET;
 473 }
 474
 475 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 476                              bool with_comp, u8 comp_type)
 477 {
 478         u32 opcode = 0;
 479
 480         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 481                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 482
 483         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 484
 485         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 486         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 487                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 488         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 489
 490 #ifdef __BIG_ENDIAN
 491         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 492 #else
 493         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 494 #endif
 495         if (with_comp)
 496                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 497         return opcode;
 498 }
 499
 500 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 501                                       struct dmae_command *dmae,
 502                                       u8 src_type, u8 dst_type)
 503 {
 504         memset(dmae, 0, sizeof(struct dmae_command));
 505
 506         /* set the opcode */
 507         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 508                                          true, DMAE_COMP_PCI);
 509
 510         /* fill in the completion parameters */
 511         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 512         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 513         dmae->comp_val = DMAE_COMP_VAL;
 514 }
 515
 516 /* issue a dmae command over the init-channel and wait for completion */
 517 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 518                                u32 *comp)
 519 {
 520         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 521         int rc = 0;
 522
 523         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 524
 525         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 526          * as long as this code is called both from syscall context and
 527          * from ndo_set_rx_mode() flow that may be called from BH.
 528          */
 529
 530         spin_lock_bh(&bp->dmae_lock);
 531
 532         /* reset completion */
 533         *comp = 0;
 534
 535         /* post the command on the channel used for initializations */
 536         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 537
 538         /* wait for completion */
 539         udelay(5);
 540         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 541
 542                 if (!cnt ||
 543                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 544                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 545                         BNX2X_ERR("DMAE timeout!\n");
 546                         rc = DMAE_TIMEOUT;
 547                         goto unlock;
 548                 }
 549                 cnt--;
 550                 udelay(50);
 551         }
 552         if (*comp & DMAE_PCI_ERR_FLAG) {
 553                 BNX2X_ERR("DMAE PCI error!\n");
 554                 rc = DMAE_PCI_ERROR;
 555         }
 556
 557 unlock:
 558
 559         spin_unlock_bh(&bp->dmae_lock);
 560
 561         return rc;
 562 }
 563
 564 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 565                       u32 len32)
 566 {
 567         int rc;
 568         struct dmae_command dmae;
 569
 570         if (!bp->dmae_ready) {
 571                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 572
 573                 if (CHIP_IS_E1(bp))
 574                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 575                 else
 576                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 577                 return;
 578         }
 579
 580         /* set opcode and fixed command fields */
 581         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 582
 583         /* fill in addresses and len */
 584         dmae.src_addr_lo = U64_LO(dma_addr);
 585         dmae.src_addr_hi = U64_HI(dma_addr);
 586         dmae.dst_addr_lo = dst_addr >> 2;
 587         dmae.dst_addr_hi = 0;
 588         dmae.len = len32;
 589
 590         /* issue the command and wait for completion */
 591         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 592         if (rc) {
 593                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 594 #ifdef BNX2X_STOP_ON_ERROR
 595                 bnx2x_panic();
 596 #endif
 597         }
 598 }
 599
 600 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 601 {
 602         int rc;
 603         struct dmae_command dmae;
 604
 605         if (!bp->dmae_ready) {
 606                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 607                 int i;
 608
 609                 if (CHIP_IS_E1(bp))
 610                         for (i = 0; i < len32; i++)
 611                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 612                 else
 613                         for (i = 0; i < len32; i++)
 614                                 data[i] = REG_RD(bp, src_addr + i*4);
 615
 616                 return;
 617         }
 618
 619         /* set opcode and fixed command fields */
 620         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 621
 622         /* fill in addresses and len */
 623         dmae.src_addr_lo = src_addr >> 2;
 624         dmae.src_addr_hi = 0;
 625         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 626         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 627         dmae.len = len32;
 628
 629         /* issue the command and wait for completion */
 630         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 631         if (rc) {
 632                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 633 #ifdef BNX2X_STOP_ON_ERROR
 634                 bnx2x_panic();
 635 #endif
 636         }
 637 }
 638
 639 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 640                                       u32 addr, u32 len)
 641 {
 642         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 643         int offset = 0;
 644
 645         while (len > dmae_wr_max) {
 646                 bnx2x_write_dmae(bp, phys_addr + offset,
 647                                  addr + offset, dmae_wr_max);
 648                 offset += dmae_wr_max * 4;
 649                 len -= dmae_wr_max;
 650         }
 651
 652         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 653 }
 654
 655 enum storms {
 656            XSTORM,
 657            TSTORM,
 658            CSTORM,
 659            USTORM,
 660            MAX_STORMS
 661 };
 662
 663 #define STORMS_NUM 4
 664 #define REGS_IN_ENTRY 4
 665
 666 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 667                                               enum storms storm,
 668                                               int entry)
 669 {
 670         switch (storm) {
 671         case XSTORM:
 672                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 673         case TSTORM:
 674                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 675         case CSTORM:
 676                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 677         case USTORM:
 678                 return USTORM_ASSERT_LIST_OFFSET(entry);
 679         case MAX_STORMS:
 680         default:
 681                 BNX2X_ERR("unknown storm\n");
 682         }
 683         return -EINVAL;
 684 }
 685
 686 static int bnx2x_mc_assert(struct bnx2x *bp)
 687 {
 688         char last_idx;
 689         int i, j, rc = 0;
 690         enum storms storm;
 691         u32 regs[REGS_IN_ENTRY];
 692         u32 bar_storm_intmem[STORMS_NUM] = {
 693                 BAR_XSTRORM_INTMEM,
 694                 BAR_TSTRORM_INTMEM,
 695                 BAR_CSTRORM_INTMEM,
 696                 BAR_USTRORM_INTMEM
 697         };
 698         u32 storm_assert_list_index[STORMS_NUM] = {
 699                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 700                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 701                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 702                 USTORM_ASSERT_LIST_INDEX_OFFSET
 703         };
 704         char *storms_string[STORMS_NUM] = {
 705                 "XSTORM",
 706                 "TSTORM",
 707                 "CSTORM",
 708                 "USTORM"
 709         };
 710
 711         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 712                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 713                                    storm_assert_list_index[storm]);
 714                 if (last_idx)
 715                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 716                                   storms_string[storm], last_idx);
 717
 718                 /* print the asserts */
 719                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 720                         /* read a single assert entry */
 721                         for (j = 0; j < REGS_IN_ENTRY; j++)
 722                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 723                                           bnx2x_get_assert_list_entry(bp,
 724                                                                       storm,
 725                                                                       i) +
 726                                           sizeof(u32) * j);
 727
 728                         /* log entry if it contains a valid assert */
 729                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 730                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 731                                           storms_string[storm], i, regs[3],
 732                                           regs[2], regs[1], regs[0]);
 733                                 rc++;
 734                         } else {
 735                                 break;
 736                         }
 737                 }
 738         }
 739
 740         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
 741                   CHIP_IS_E1(bp) ? "everest1" :
 742                   CHIP_IS_E1H(bp) ? "everest1h" :
 743                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
 744                   BCM_5710_FW_MAJOR_VERSION,
 745                   BCM_5710_FW_MINOR_VERSION,
 746                   BCM_5710_FW_REVISION_VERSION);
 747
 748         return rc;
 749 }
 750
 751 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 752 #define SCRATCH_BUFFER_SIZE(bp) \
 753         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 754
 755 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 756 {
 757         u32 addr, val;
 758         u32 mark, offset;
 759         __be32 data[9];
 760         int word;
 761         u32 trace_shmem_base;
 762         if (BP_NOMCP(bp)) {
 763                 BNX2X_ERR("NO MCP - can not dump\n");
 764                 return;
 765         }
 766         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 767                 (bp->common.bc_ver & 0xff0000) >> 16,
 768                 (bp->common.bc_ver & 0xff00) >> 8,
 769                 (bp->common.bc_ver & 0xff));
 770
 771         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 772         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 773                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 774
 775         if (BP_PATH(bp) == 0)
 776                 trace_shmem_base = bp->common.shmem_base;
 777         else
 778                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 779
 780         /* sanity */
 781         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 782             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 783                                 SCRATCH_BUFFER_SIZE(bp)) {
 784                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 785                           trace_shmem_base);
 786                 return;
 787         }
 788
 789         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 790
 791         /* validate TRCB signature */
 792         mark = REG_RD(bp, addr);
 793         if (mark != MFW_TRACE_SIGNATURE) {
 794                 BNX2X_ERR("Trace buffer signature is missing.");
 795                 return ;
 796         }
 797
 798         /* read cyclic buffer pointer */
 799         addr += 4;
 800         mark = REG_RD(bp, addr);
 801         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 802         if (mark >= trace_shmem_base || mark < addr + 4) {
 803                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 804                 return;
 805         }
 806         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 807
 808         printk("%s", lvl);
 809
 810         /* dump buffer after the mark */
 811         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 812                 for (word = 0; word < 8; word++)
 813                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 814                 data[8] = 0x0;
 815                 pr_cont("%s", (char *)data);
 816         }
 817
 818         /* dump buffer before the mark */
 819         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 820                 for (word = 0; word < 8; word++)
 821                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 822                 data[8] = 0x0;
 823                 pr_cont("%s", (char *)data);
 824         }
 825         printk("%s" "end of fw dump\n", lvl);
 826 }
 827
 828 static void bnx2x_fw_dump(struct bnx2x *bp)
 829 {
 830         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 831 }
 832
 833 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 834 {
 835         int port = BP_PORT(bp);
 836         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 837         u32 val = REG_RD(bp, addr);
 838
 839         /* in E1 we must use only PCI configuration space to disable
 840          * MSI/MSIX capability
 841          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 842          */
 843         if (CHIP_IS_E1(bp)) {
 844                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 845                  * Use mask register to prevent from HC sending interrupts
 846                  * after we exit the function
 847                  */
 848                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 849
 850                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 851                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 852                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 853         } else
 854                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 855                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 856                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 857                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 858
 859         DP(NETIF_MSG_IFDOWN,
 860            "write %x to HC %d (addr 0x%x)\n",
 861            val, port, addr);
 862
 863         /* flush all outstanding writes */
 864         mmiowb();
 865
 866         REG_WR(bp, addr, val);
 867         if (REG_RD(bp, addr) != val)
 868                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 869 }
 870
 871 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 872 {
 873         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 874
 875         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 876                  IGU_PF_CONF_INT_LINE_EN |
 877                  IGU_PF_CONF_ATTN_BIT_EN);
 878
 879         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 880
 881         /* flush all outstanding writes */
 882         mmiowb();
 883
 884         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 885         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 886                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 887 }
 888
 889 static void bnx2x_int_disable(struct bnx2x *bp)
 890 {
 891         if (bp->common.int_block == INT_BLOCK_HC)
 892                 bnx2x_hc_int_disable(bp);
 893         else
 894                 bnx2x_igu_int_disable(bp);
 895 }
 896
 897 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 898 {
 899         int i;
 900         u16 j;
 901         struct hc_sp_status_block_data sp_sb_data;
 902         int func = BP_FUNC(bp);
 903 #ifdef BNX2X_STOP_ON_ERROR
 904         u16 start = 0, end = 0;
 905         u8 cos;
 906 #endif
 907         if (IS_PF(bp) && disable_int)
 908                 bnx2x_int_disable(bp);
 909
 910         bp->stats_state = STATS_STATE_DISABLED;
 911         bp->eth_stats.unrecoverable_error++;
 912         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 913
 914         BNX2X_ERR("begin crash dump -----------------\n");
 915
 916         /* Indices */
 917         /* Common */
 918         if (IS_PF(bp)) {
 919                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 920                 int data_size, cstorm_offset;
 921
 922                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 923                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 924                           bp->spq_prod_idx, bp->stats_counter);
 925                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 926                           def_sb->atten_status_block.attn_bits,
 927                           def_sb->atten_status_block.attn_bits_ack,
 928                           def_sb->atten_status_block.status_block_id,
 929                           def_sb->atten_status_block.attn_bits_index);
 930                 BNX2X_ERR("     def (");
 931                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 932                         pr_cont("0x%x%s",
 933                                 def_sb->sp_sb.index_values[i],
 934                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 935
 936                 data_size = sizeof(struct hc_sp_status_block_data) /
 937                             sizeof(u32);
 938                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 939                 for (i = 0; i < data_size; i++)
 940                         *((u32 *)&sp_sb_data + i) =
 941                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 942                                            i * sizeof(u32));
 943
 944                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 945                         sp_sb_data.igu_sb_id,
 946                         sp_sb_data.igu_seg_id,
 947                         sp_sb_data.p_func.pf_id,
 948                         sp_sb_data.p_func.vnic_id,
 949                         sp_sb_data.p_func.vf_id,
 950                         sp_sb_data.p_func.vf_valid,
 951                         sp_sb_data.state);
 952         }
 953
 954         for_each_eth_queue(bp, i) {
 955                 struct bnx2x_fastpath *fp = &bp->fp[i];
 956                 int loop;
 957                 struct hc_status_block_data_e2 sb_data_e2;
 958                 struct hc_status_block_data_e1x sb_data_e1x;
 959                 struct hc_status_block_sm  *hc_sm_p =
 960                         CHIP_IS_E1x(bp) ?
 961                         sb_data_e1x.common.state_machine :
 962                         sb_data_e2.common.state_machine;
 963                 struct hc_index_data *hc_index_p =
 964                         CHIP_IS_E1x(bp) ?
 965                         sb_data_e1x.index_data :
 966                         sb_data_e2.index_data;
 967                 u8 data_size, cos;
 968                 u32 *sb_data_p;
 969                 struct bnx2x_fp_txdata txdata;
 970
 971                 if (!bp->fp)
 972                         break;
 973
 974                 if (!fp->rx_cons_sb)
 975                         continue;
 976
 977                 /* Rx */
 978                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 979                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 980                           fp->rx_comp_prod,
 981                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 982                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 983                           fp->rx_sge_prod, fp->last_max_sge,
 984                           le16_to_cpu(fp->fp_hc_idx));
 985
 986                 /* Tx */
 987                 for_each_cos_in_tx_queue(fp, cos)
 988                 {
 989                         if (!fp->txdata_ptr[cos])
 990                                 break;
 991
 992                         txdata = *fp->txdata_ptr[cos];
 993
 994                         if (!txdata.tx_cons_sb)
 995                                 continue;
 996
 997                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 998                                   i, txdata.tx_pkt_prod,
 999                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1000                                   txdata.tx_bd_cons,
1001                                   le16_to_cpu(*txdata.tx_cons_sb));
1002                 }
1003
1004                 loop = CHIP_IS_E1x(bp) ?
1005                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1006
1007                 /* host sb data */
1008
1009                 if (IS_FCOE_FP(fp))
1010                         continue;
1011
1012                 BNX2X_ERR("     run indexes (");
1013                 for (j = 0; j < HC_SB_MAX_SM; j++)
1014                         pr_cont("0x%x%s",
1015                                fp->sb_running_index[j],
1016                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1017
1018                 BNX2X_ERR("     indexes (");
1019                 for (j = 0; j < loop; j++)
1020                         pr_cont("0x%x%s",
1021                                fp->sb_index_values[j],
1022                                (j == loop - 1) ? ")" : " ");
1023
1024                 /* VF cannot access FW refelection for status block */
1025                 if (IS_VF(bp))
1026                         continue;
1027
1028                 /* fw sb data */
1029                 data_size = CHIP_IS_E1x(bp) ?
1030                         sizeof(struct hc_status_block_data_e1x) :
1031                         sizeof(struct hc_status_block_data_e2);
1032                 data_size /= sizeof(u32);
1033                 sb_data_p = CHIP_IS_E1x(bp) ?
1034                         (u32 *)&sb_data_e1x :
1035                         (u32 *)&sb_data_e2;
1036                 /* copy sb data in here */
1037                 for (j = 0; j < data_size; j++)
1038                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1039                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1040                                 j * sizeof(u32));
1041
1042                 if (!CHIP_IS_E1x(bp)) {
1043                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1044                                 sb_data_e2.common.p_func.pf_id,
1045                                 sb_data_e2.common.p_func.vf_id,
1046                                 sb_data_e2.common.p_func.vf_valid,
1047                                 sb_data_e2.common.p_func.vnic_id,
1048                                 sb_data_e2.common.same_igu_sb_1b,
1049                                 sb_data_e2.common.state);
1050                 } else {
1051                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1052                                 sb_data_e1x.common.p_func.pf_id,
1053                                 sb_data_e1x.common.p_func.vf_id,
1054                                 sb_data_e1x.common.p_func.vf_valid,
1055                                 sb_data_e1x.common.p_func.vnic_id,
1056                                 sb_data_e1x.common.same_igu_sb_1b,
1057                                 sb_data_e1x.common.state);
1058                 }
1059
1060                 /* SB_SMs data */
1061                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1062                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1063                                 j, hc_sm_p[j].__flags,
1064                                 hc_sm_p[j].igu_sb_id,
1065                                 hc_sm_p[j].igu_seg_id,
1066                                 hc_sm_p[j].time_to_expire,
1067                                 hc_sm_p[j].timer_value);
1068                 }
1069
1070                 /* Indices data */
1071                 for (j = 0; j < loop; j++) {
1072                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1073                                hc_index_p[j].flags,
1074                                hc_index_p[j].timeout);
1075                 }
1076         }
1077
1078 #ifdef BNX2X_STOP_ON_ERROR
1079         if (IS_PF(bp)) {
1080                 /* event queue */
1081                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1082                 for (i = 0; i < NUM_EQ_DESC; i++) {
1083                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1084
1085                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1086                                   i, bp->eq_ring[i].message.opcode,
1087                                   bp->eq_ring[i].message.error);
1088                         BNX2X_ERR("data: %x %x %x\n",
1089                                   data[0], data[1], data[2]);
1090                 }
1091         }
1092
1093         /* Rings */
1094         /* Rx */
1095         for_each_valid_rx_queue(bp, i) {
1096                 struct bnx2x_fastpath *fp = &bp->fp[i];
1097
1098                 if (!bp->fp)
1099                         break;
1100
1101                 if (!fp->rx_cons_sb)
1102                         continue;
1103
1104                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1105                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1106                 for (j = start; j != end; j = RX_BD(j + 1)) {
1107                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1108                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1109
1110                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1111                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1112                 }
1113
1114                 start = RX_SGE(fp->rx_sge_prod);
1115                 end = RX_SGE(fp->last_max_sge);
1116                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1117                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1118                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1119
1120                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1121                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1122                 }
1123
1124                 start = RCQ_BD(fp->rx_comp_cons - 10);
1125                 end = RCQ_BD(fp->rx_comp_cons + 503);
1126                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1127                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1128
1129                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1130                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1131                 }
1132         }
1133
1134         /* Tx */
1135         for_each_valid_tx_queue(bp, i) {
1136                 struct bnx2x_fastpath *fp = &bp->fp[i];
1137
1138                 if (!bp->fp)
1139                         break;
1140
1141                 for_each_cos_in_tx_queue(fp, cos) {
1142                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1143
1144                         if (!fp->txdata_ptr[cos])
1145                                 break;
1146
1147                         if (!txdata->tx_cons_sb)
1148                                 continue;
1149
1150                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1151                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1152                         for (j = start; j != end; j = TX_BD(j + 1)) {
1153                                 struct sw_tx_bd *sw_bd =
1154                                         &txdata->tx_buf_ring[j];
1155
1156                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1157                                           i, cos, j, sw_bd->skb,
1158                                           sw_bd->first_bd);
1159                         }
1160
1161                         start = TX_BD(txdata->tx_bd_cons - 10);
1162                         end = TX_BD(txdata->tx_bd_cons + 254);
1163                         for (j = start; j != end; j = TX_BD(j + 1)) {
1164                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1165
1166                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1167                                           i, cos, j, tx_bd[0], tx_bd[1],
1168                                           tx_bd[2], tx_bd[3]);
1169                         }
1170                 }
1171         }
1172 #endif
1173         if (IS_PF(bp)) {
1174                 bnx2x_fw_dump(bp);
1175                 bnx2x_mc_assert(bp);
1176         }
1177         BNX2X_ERR("end crash dump -----------------\n");
1178 }
1179
1180 /*
1181  * FLR Support for E2
1182  *
1183  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1184  * initialization.
1185  */
1186 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1187 #define FLR_WAIT_INTERVAL       50      /* usec */
1188 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1189
1190 struct pbf_pN_buf_regs {
1191         int pN;
1192         u32 init_crd;
1193         u32 crd;
1194         u32 crd_freed;
1195 };
1196
1197 struct pbf_pN_cmd_regs {
1198         int pN;
1199         u32 lines_occup;
1200         u32 lines_freed;
1201 };
1202
1203 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1204                                      struct pbf_pN_buf_regs *regs,
1205                                      u32 poll_count)
1206 {
1207         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1208         u32 cur_cnt = poll_count;
1209
1210         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1211         crd = crd_start = REG_RD(bp, regs->crd);
1212         init_crd = REG_RD(bp, regs->init_crd);
1213
1214         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1215         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1216         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1217
1218         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1219                (init_crd - crd_start))) {
1220                 if (cur_cnt--) {
1221                         udelay(FLR_WAIT_INTERVAL);
1222                         crd = REG_RD(bp, regs->crd);
1223                         crd_freed = REG_RD(bp, regs->crd_freed);
1224                 } else {
1225                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1226                            regs->pN);
1227                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1228                            regs->pN, crd);
1229                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1230                            regs->pN, crd_freed);
1231                         break;
1232                 }
1233         }
1234         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1235            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1236 }
1237
1238 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1239                                      struct pbf_pN_cmd_regs *regs,
1240                                      u32 poll_count)
1241 {
1242         u32 occup, to_free, freed, freed_start;
1243         u32 cur_cnt = poll_count;
1244
1245         occup = to_free = REG_RD(bp, regs->lines_occup);
1246         freed = freed_start = REG_RD(bp, regs->lines_freed);
1247
1248         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1249         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1250
1251         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1252                 if (cur_cnt--) {
1253                         udelay(FLR_WAIT_INTERVAL);
1254                         occup = REG_RD(bp, regs->lines_occup);
1255                         freed = REG_RD(bp, regs->lines_freed);
1256                 } else {
1257                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1258                            regs->pN);
1259                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1260                            regs->pN, occup);
1261                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1262                            regs->pN, freed);
1263                         break;
1264                 }
1265         }
1266         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1267            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1268 }
1269
1270 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1271                                     u32 expected, u32 poll_count)
1272 {
1273         u32 cur_cnt = poll_count;
1274         u32 val;
1275
1276         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1277                 udelay(FLR_WAIT_INTERVAL);
1278
1279         return val;
1280 }
1281
1282 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1283                                     char *msg, u32 poll_cnt)
1284 {
1285         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1286         if (val != 0) {
1287                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1288                 return 1;
1289         }
1290         return 0;
1291 }
1292
1293 /* Common routines with VF FLR cleanup */
1294 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1295 {
1296         /* adjust polling timeout */
1297         if (CHIP_REV_IS_EMUL(bp))
1298                 return FLR_POLL_CNT * 2000;
1299
1300         if (CHIP_REV_IS_FPGA(bp))
1301                 return FLR_POLL_CNT * 120;
1302
1303         return FLR_POLL_CNT;
1304 }
1305
1306 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1307 {
1308         struct pbf_pN_cmd_regs cmd_regs[] = {
1309                 {0, (CHIP_IS_E3B0(bp)) ?
1310                         PBF_REG_TQ_OCCUPANCY_Q0 :
1311                         PBF_REG_P0_TQ_OCCUPANCY,
1312                     (CHIP_IS_E3B0(bp)) ?
1313                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1314                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1315                 {1, (CHIP_IS_E3B0(bp)) ?
1316                         PBF_REG_TQ_OCCUPANCY_Q1 :
1317                         PBF_REG_P1_TQ_OCCUPANCY,
1318                     (CHIP_IS_E3B0(bp)) ?
1319                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1320                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1321                 {4, (CHIP_IS_E3B0(bp)) ?
1322                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1323                         PBF_REG_P4_TQ_OCCUPANCY,
1324                     (CHIP_IS_E3B0(bp)) ?
1325                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1326                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1327         };
1328
1329         struct pbf_pN_buf_regs buf_regs[] = {
1330                 {0, (CHIP_IS_E3B0(bp)) ?
1331                         PBF_REG_INIT_CRD_Q0 :
1332                         PBF_REG_P0_INIT_CRD ,
1333                     (CHIP_IS_E3B0(bp)) ?
1334                         PBF_REG_CREDIT_Q0 :
1335                         PBF_REG_P0_CREDIT,
1336                     (CHIP_IS_E3B0(bp)) ?
1337                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1338                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1339                 {1, (CHIP_IS_E3B0(bp)) ?
1340                         PBF_REG_INIT_CRD_Q1 :
1341                         PBF_REG_P1_INIT_CRD,
1342                     (CHIP_IS_E3B0(bp)) ?
1343                         PBF_REG_CREDIT_Q1 :
1344                         PBF_REG_P1_CREDIT,
1345                     (CHIP_IS_E3B0(bp)) ?
1346                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1347                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1348                 {4, (CHIP_IS_E3B0(bp)) ?
1349                         PBF_REG_INIT_CRD_LB_Q :
1350                         PBF_REG_P4_INIT_CRD,
1351                     (CHIP_IS_E3B0(bp)) ?
1352                         PBF_REG_CREDIT_LB_Q :
1353                         PBF_REG_P4_CREDIT,
1354                     (CHIP_IS_E3B0(bp)) ?
1355                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1356                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1357         };
1358
1359         int i;
1360
1361         /* Verify the command queues are flushed P0, P1, P4 */
1362         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1363                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1364
1365         /* Verify the transmission buffers are flushed P0, P1, P4 */
1366         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1367                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1368 }
1369
1370 #define OP_GEN_PARAM(param) \
1371         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1372
1373 #define OP_GEN_TYPE(type) \
1374         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1375
1376 #define OP_GEN_AGG_VECT(index) \
1377         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1378
1379 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1380 {
1381         u32 op_gen_command = 0;
1382         u32 comp_addr = BAR_CSTRORM_INTMEM +
1383                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1384         int ret = 0;
1385
1386         if (REG_RD(bp, comp_addr)) {
1387                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1388                 return 1;
1389         }
1390
1391         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1392         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1393         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1394         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1395
1396         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1397         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1398
1399         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1400                 BNX2X_ERR("FW final cleanup did not succeed\n");
1401                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1402                    (REG_RD(bp, comp_addr)));
1403                 bnx2x_panic();
1404                 return 1;
1405         }
1406         /* Zero completion for next FLR */
1407         REG_WR(bp, comp_addr, 0);
1408
1409         return ret;
1410 }
1411
1412 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1413 {
1414         u16 status;
1415
1416         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1417         return status & PCI_EXP_DEVSTA_TRPND;
1418 }
1419
1420 /* PF FLR specific routines
1421 */
1422 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1423 {
1424         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1425         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1426                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1427                         "CFC PF usage counter timed out",
1428                         poll_cnt))
1429                 return 1;
1430
1431         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1432         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1433                         DORQ_REG_PF_USAGE_CNT,
1434                         "DQ PF usage counter timed out",
1435                         poll_cnt))
1436                 return 1;
1437
1438         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1439         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1440                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1441                         "QM PF usage counter timed out",
1442                         poll_cnt))
1443                 return 1;
1444
1445         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1446         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1447                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1448                         "Timers VNIC usage counter timed out",
1449                         poll_cnt))
1450                 return 1;
1451         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1452                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1453                         "Timers NUM_SCANS usage counter timed out",
1454                         poll_cnt))
1455                 return 1;
1456
1457         /* Wait DMAE PF usage counter to zero */
1458         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1459                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1460                         "DMAE command register timed out",
1461                         poll_cnt))
1462                 return 1;
1463
1464         return 0;
1465 }
1466
1467 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1468 {
1469         u32 val;
1470
1471         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1472         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1473
1474         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1475         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1476
1477         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1478         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1479
1480         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1481         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1482
1483         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1484         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1485
1486         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1487         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1488
1489         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1490         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1491
1492         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1493         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1494            val);
1495 }
1496
1497 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1498 {
1499         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1500
1501         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1502
1503         /* Re-enable PF target read access */
1504         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1505
1506         /* Poll HW usage counters */
1507         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1508         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1509                 return -EBUSY;
1510
1511         /* Zero the igu 'trailing edge' and 'leading edge' */
1512
1513         /* Send the FW cleanup command */
1514         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1515                 return -EBUSY;
1516
1517         /* ATC cleanup */
1518
1519         /* Verify TX hw is flushed */
1520         bnx2x_tx_hw_flushed(bp, poll_cnt);
1521
1522         /* Wait 100ms (not adjusted according to platform) */
1523         msleep(100);
1524
1525         /* Verify no pending pci transactions */
1526         if (bnx2x_is_pcie_pending(bp->pdev))
1527                 BNX2X_ERR("PCIE Transactions still pending\n");
1528
1529         /* Debug */
1530         bnx2x_hw_enable_status(bp);
1531
1532         /*
1533          * Master enable - Due to WB DMAE writes performed before this
1534          * register is re-initialized as part of the regular function init
1535          */
1536         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1537
1538         return 0;
1539 }
1540
1541 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1542 {
1543         int port = BP_PORT(bp);
1544         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1545         u32 val = REG_RD(bp, addr);
1546         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1547         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1548         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1549
1550         if (msix) {
1551                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1552                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1553                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1554                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1555                 if (single_msix)
1556                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1557         } else if (msi) {
1558                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1559                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1560                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1561                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1562         } else {
1563                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1564                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1565                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1566                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1567
1568                 if (!CHIP_IS_E1(bp)) {
1569                         DP(NETIF_MSG_IFUP,
1570                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1571
1572                         REG_WR(bp, addr, val);
1573
1574                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1575                 }
1576         }
1577
1578         if (CHIP_IS_E1(bp))
1579                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1580
1581         DP(NETIF_MSG_IFUP,
1582            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1583            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1584
1585         REG_WR(bp, addr, val);
1586         /*
1587          * Ensure that HC_CONFIG is written before leading/trailing edge config
1588          */
1589         mmiowb();
1590         barrier();
1591
1592         if (!CHIP_IS_E1(bp)) {
1593                 /* init leading/trailing edge */
1594                 if (IS_MF(bp)) {
1595                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1596                         if (bp->port.pmf)
1597                                 /* enable nig and gpio3 attention */
1598                                 val |= 0x1100;
1599                 } else
1600                         val = 0xffff;
1601
1602                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1603                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1604         }
1605
1606         /* Make sure that interrupts are indeed enabled from here on */
1607         mmiowb();
1608 }
1609
1610 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1611 {
1612         u32 val;
1613         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1614         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1615         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1616
1617         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1618
1619         if (msix) {
1620                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1621                          IGU_PF_CONF_SINGLE_ISR_EN);
1622                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1623                         IGU_PF_CONF_ATTN_BIT_EN);
1624
1625                 if (single_msix)
1626                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1627         } else if (msi) {
1628                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1629                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1630                         IGU_PF_CONF_ATTN_BIT_EN |
1631                         IGU_PF_CONF_SINGLE_ISR_EN);
1632         } else {
1633                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1634                 val |= (IGU_PF_CONF_INT_LINE_EN |
1635                         IGU_PF_CONF_ATTN_BIT_EN |
1636                         IGU_PF_CONF_SINGLE_ISR_EN);
1637         }
1638
1639         /* Clean previous status - need to configure igu prior to ack*/
1640         if ((!msix) || single_msix) {
1641                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1642                 bnx2x_ack_int(bp);
1643         }
1644
1645         val |= IGU_PF_CONF_FUNC_EN;
1646
1647         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1648            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1649
1650         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1651
1652         if (val & IGU_PF_CONF_INT_LINE_EN)
1653                 pci_intx(bp->pdev, true);
1654
1655         barrier();
1656
1657         /* init leading/trailing edge */
1658         if (IS_MF(bp)) {
1659                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1660                 if (bp->port.pmf)
1661                         /* enable nig and gpio3 attention */
1662                         val |= 0x1100;
1663         } else
1664                 val = 0xffff;
1665
1666         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1667         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1668
1669         /* Make sure that interrupts are indeed enabled from here on */
1670         mmiowb();
1671 }
1672
1673 void bnx2x_int_enable(struct bnx2x *bp)
1674 {
1675         if (bp->common.int_block == INT_BLOCK_HC)
1676                 bnx2x_hc_int_enable(bp);
1677         else
1678                 bnx2x_igu_int_enable(bp);
1679 }
1680
1681 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1682 {
1683         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1684         int i, offset;
1685
1686         if (disable_hw)
1687                 /* prevent the HW from sending interrupts */
1688                 bnx2x_int_disable(bp);
1689
1690         /* make sure all ISRs are done */
1691         if (msix) {
1692                 synchronize_irq(bp->msix_table[0].vector);
1693                 offset = 1;
1694                 if (CNIC_SUPPORT(bp))
1695                         offset++;
1696                 for_each_eth_queue(bp, i)
1697                         synchronize_irq(bp->msix_table[offset++].vector);
1698         } else
1699                 synchronize_irq(bp->pdev->irq);
1700
1701         /* make sure sp_task is not running */
1702         cancel_delayed_work(&bp->sp_task);
1703         cancel_delayed_work(&bp->period_task);
1704         flush_workqueue(bnx2x_wq);
1705 }
1706
1707 /* fast path */
1708
1709 /*
1710  * General service functions
1711  */
1712
1713 /* Return true if succeeded to acquire the lock */
1714 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1715 {
1716         u32 lock_status;
1717         u32 resource_bit = (1 << resource);
1718         int func = BP_FUNC(bp);
1719         u32 hw_lock_control_reg;
1720
1721         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1722            "Trying to take a lock on resource %d\n", resource);
1723
1724         /* Validating that the resource is within range */
1725         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1726                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1727                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1728                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1729                 return false;
1730         }
1731
1732         if (func <= 5)
1733                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1734         else
1735                 hw_lock_control_reg =
1736                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1737
1738         /* Try to acquire the lock */
1739         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1740         lock_status = REG_RD(bp, hw_lock_control_reg);
1741         if (lock_status & resource_bit)
1742                 return true;
1743
1744         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1745            "Failed to get a lock on resource %d\n", resource);
1746         return false;
1747 }
1748
1749 /**
1750  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1751  *
1752  * @bp: driver handle
1753  *
1754  * Returns the recovery leader resource id according to the engine this function
1755  * belongs to. Currently only only 2 engines is supported.
1756  */
1757 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1758 {
1759         if (BP_PATH(bp))
1760                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1761         else
1762                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1763 }
1764
1765 /**
1766  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1767  *
1768  * @bp: driver handle
1769  *
1770  * Tries to acquire a leader lock for current engine.
1771  */
1772 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1773 {
1774         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1775 }
1776
1777 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1778
1779 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1780 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1781 {
1782         /* Set the interrupt occurred bit for the sp-task to recognize it
1783          * must ack the interrupt and transition according to the IGU
1784          * state machine.
1785          */
1786         atomic_set(&bp->interrupt_occurred, 1);
1787
1788         /* The sp_task must execute only after this bit
1789          * is set, otherwise we will get out of sync and miss all
1790          * further interrupts. Hence, the barrier.
1791          */
1792         smp_wmb();
1793
1794         /* schedule sp_task to workqueue */
1795         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1796 }
1797
1798 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1799 {
1800         struct bnx2x *bp = fp->bp;
1801         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1802         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1803         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1804         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1805
1806         DP(BNX2X_MSG_SP,
1807            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1808            fp->index, cid, command, bp->state,
1809            rr_cqe->ramrod_cqe.ramrod_type);
1810
1811         /* If cid is within VF range, replace the slowpath object with the
1812          * one corresponding to this VF
1813          */
1814         if (cid >= BNX2X_FIRST_VF_CID  &&
1815             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1816                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1817
1818         switch (command) {
1819         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1820                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1821                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1822                 break;
1823
1824         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1825                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1826                 drv_cmd = BNX2X_Q_CMD_SETUP;
1827                 break;
1828
1829         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1830                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1831                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1832                 break;
1833
1834         case (RAMROD_CMD_ID_ETH_HALT):
1835                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1836                 drv_cmd = BNX2X_Q_CMD_HALT;
1837                 break;
1838
1839         case (RAMROD_CMD_ID_ETH_TERMINATE):
1840                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1841                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1842                 break;
1843
1844         case (RAMROD_CMD_ID_ETH_EMPTY):
1845                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1846                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1847                 break;
1848
1849         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1850                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1851                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1852                 break;
1853
1854         default:
1855                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1856                           command, fp->index);
1857                 return;
1858         }
1859
1860         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1861             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1862                 /* q_obj->complete_cmd() failure means that this was
1863                  * an unexpected completion.
1864                  *
1865                  * In this case we don't want to increase the bp->spq_left
1866                  * because apparently we haven't sent this command the first
1867                  * place.
1868                  */
1869 #ifdef BNX2X_STOP_ON_ERROR
1870                 bnx2x_panic();
1871 #else
1872                 return;
1873 #endif
1874
1875         smp_mb__before_atomic();
1876         atomic_inc(&bp->cq_spq_left);
1877         /* push the change in bp->spq_left and towards the memory */
1878         smp_mb__after_atomic();
1879
1880         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1881
1882         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1883             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1884                 /* if Q update ramrod is completed for last Q in AFEX vif set
1885                  * flow, then ACK MCP at the end
1886                  *
1887                  * mark pending ACK to MCP bit.
1888                  * prevent case that both bits are cleared.
1889                  * At the end of load/unload driver checks that
1890                  * sp_state is cleared, and this order prevents
1891                  * races
1892                  */
1893                 smp_mb__before_atomic();
1894                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1895                 wmb();
1896                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1897                 smp_mb__after_atomic();
1898
1899                 /* schedule the sp task as mcp ack is required */
1900                 bnx2x_schedule_sp_task(bp);
1901         }
1902
1903         return;
1904 }
1905
1906 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1907 {
1908         struct bnx2x *bp = netdev_priv(dev_instance);
1909         u16 status = bnx2x_ack_int(bp);
1910         u16 mask;
1911         int i;
1912         u8 cos;
1913
1914         /* Return here if interrupt is shared and it's not for us */
1915         if (unlikely(status == 0)) {
1916                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1917                 return IRQ_NONE;
1918         }
1919         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1920
1921 #ifdef BNX2X_STOP_ON_ERROR
1922         if (unlikely(bp->panic))
1923                 return IRQ_HANDLED;
1924 #endif
1925
1926         for_each_eth_queue(bp, i) {
1927                 struct bnx2x_fastpath *fp = &bp->fp[i];
1928
1929                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1930                 if (status & mask) {
1931                         /* Handle Rx or Tx according to SB id */
1932                         for_each_cos_in_tx_queue(fp, cos)
1933                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1934                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1935                         napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1936                         status &= ~mask;
1937                 }
1938         }
1939
1940         if (CNIC_SUPPORT(bp)) {
1941                 mask = 0x2;
1942                 if (status & (mask | 0x1)) {
1943                         struct cnic_ops *c_ops = NULL;
1944
1945                         rcu_read_lock();
1946                         c_ops = rcu_dereference(bp->cnic_ops);
1947                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1948                                       CNIC_DRV_STATE_HANDLES_IRQ))
1949                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1950                         rcu_read_unlock();
1951
1952                         status &= ~mask;
1953                 }
1954         }
1955
1956         if (unlikely(status & 0x1)) {
1957
1958                 /* schedule sp task to perform default status block work, ack
1959                  * attentions and enable interrupts.
1960                  */
1961                 bnx2x_schedule_sp_task(bp);
1962
1963                 status &= ~0x1;
1964                 if (!status)
1965                         return IRQ_HANDLED;
1966         }
1967
1968         if (unlikely(status))
1969                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1970                    status);
1971
1972         return IRQ_HANDLED;
1973 }
1974
1975 /* Link */
1976
1977 /*
1978  * General service functions
1979  */
1980
1981 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1982 {
1983         u32 lock_status;
1984         u32 resource_bit = (1 << resource);
1985         int func = BP_FUNC(bp);
1986         u32 hw_lock_control_reg;
1987         int cnt;
1988
1989         /* Validating that the resource is within range */
1990         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1991                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1992                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1993                 return -EINVAL;
1994         }
1995
1996         if (func <= 5) {
1997                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1998         } else {
1999                 hw_lock_control_reg =
2000                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2001         }
2002
2003         /* Validating that the resource is not already taken */
2004         lock_status = REG_RD(bp, hw_lock_control_reg);
2005         if (lock_status & resource_bit) {
2006                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2007                    lock_status, resource_bit);
2008                 return -EEXIST;
2009         }
2010
2011         /* Try for 5 second every 5ms */
2012         for (cnt = 0; cnt < 1000; cnt++) {
2013                 /* Try to acquire the lock */
2014                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2015                 lock_status = REG_RD(bp, hw_lock_control_reg);
2016                 if (lock_status & resource_bit)
2017                         return 0;
2018
2019                 usleep_range(5000, 10000);
2020         }
2021         BNX2X_ERR("Timeout\n");
2022         return -EAGAIN;
2023 }
2024
2025 int bnx2x_release_leader_lock(struct bnx2x *bp)
2026 {
2027         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2028 }
2029
2030 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2031 {
2032         u32 lock_status;
2033         u32 resource_bit = (1 << resource);
2034         int func = BP_FUNC(bp);
2035         u32 hw_lock_control_reg;
2036
2037         /* Validating that the resource is within range */
2038         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2039                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2040                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2041                 return -EINVAL;
2042         }
2043
2044         if (func <= 5) {
2045                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2046         } else {
2047                 hw_lock_control_reg =
2048                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2049         }
2050
2051         /* Validating that the resource is currently taken */
2052         lock_status = REG_RD(bp, hw_lock_control_reg);
2053         if (!(lock_status & resource_bit)) {
2054                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2055                           lock_status, resource_bit);
2056                 return -EFAULT;
2057         }
2058
2059         REG_WR(bp, hw_lock_control_reg, resource_bit);
2060         return 0;
2061 }
2062
2063 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2064 {
2065         /* The GPIO should be swapped if swap register is set and active */
2066         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2067                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2068         int gpio_shift = gpio_num +
2069                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2070         u32 gpio_mask = (1 << gpio_shift);
2071         u32 gpio_reg;
2072         int value;
2073
2074         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2075                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2076                 return -EINVAL;
2077         }
2078
2079         /* read GPIO value */
2080         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2081
2082         /* get the requested pin value */
2083         if ((gpio_reg & gpio_mask) == gpio_mask)
2084                 value = 1;
2085         else
2086                 value = 0;
2087
2088         return value;
2089 }
2090
2091 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2092 {
2093         /* The GPIO should be swapped if swap register is set and active */
2094         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2095                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2096         int gpio_shift = gpio_num +
2097                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2098         u32 gpio_mask = (1 << gpio_shift);
2099         u32 gpio_reg;
2100
2101         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2102                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2103                 return -EINVAL;
2104         }
2105
2106         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2107         /* read GPIO and mask except the float bits */
2108         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2109
2110         switch (mode) {
2111         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2112                 DP(NETIF_MSG_LINK,
2113                    "Set GPIO %d (shift %d) -> output low\n",
2114                    gpio_num, gpio_shift);
2115                 /* clear FLOAT and set CLR */
2116                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2117                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2118                 break;
2119
2120         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2121                 DP(NETIF_MSG_LINK,
2122                    "Set GPIO %d (shift %d) -> output high\n",
2123                    gpio_num, gpio_shift);
2124                 /* clear FLOAT and set SET */
2125                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2126                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2127                 break;
2128
2129         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2130                 DP(NETIF_MSG_LINK,
2131                    "Set GPIO %d (shift %d) -> input\n",
2132                    gpio_num, gpio_shift);
2133                 /* set FLOAT */
2134                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2135                 break;
2136
2137         default:
2138                 break;
2139         }
2140
2141         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2142         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2143
2144         return 0;
2145 }
2146
2147 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2148 {
2149         u32 gpio_reg = 0;
2150         int rc = 0;
2151
2152         /* Any port swapping should be handled by caller. */
2153
2154         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2155         /* read GPIO and mask except the float bits */
2156         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2157         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2158         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2159         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2160
2161         switch (mode) {
2162         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2163                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2164                 /* set CLR */
2165                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2166                 break;
2167
2168         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2169                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2170                 /* set SET */
2171                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2172                 break;
2173
2174         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2175                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2176                 /* set FLOAT */
2177                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2178                 break;
2179
2180         default:
2181                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2182                 rc = -EINVAL;
2183                 break;
2184         }
2185
2186         if (rc == 0)
2187                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2188
2189         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2190
2191         return rc;
2192 }
2193
2194 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2195 {
2196         /* The GPIO should be swapped if swap register is set and active */
2197         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2198                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2199         int gpio_shift = gpio_num +
2200                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2201         u32 gpio_mask = (1 << gpio_shift);
2202         u32 gpio_reg;
2203
2204         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2205                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2206                 return -EINVAL;
2207         }
2208
2209         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2210         /* read GPIO int */
2211         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2212
2213         switch (mode) {
2214         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2215                 DP(NETIF_MSG_LINK,
2216                    "Clear GPIO INT %d (shift %d) -> output low\n",
2217                    gpio_num, gpio_shift);
2218                 /* clear SET and set CLR */
2219                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2220                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2221                 break;
2222
2223         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2224                 DP(NETIF_MSG_LINK,
2225                    "Set GPIO INT %d (shift %d) -> output high\n",
2226                    gpio_num, gpio_shift);
2227                 /* clear CLR and set SET */
2228                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2229                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2230                 break;
2231
2232         default:
2233                 break;
2234         }
2235
2236         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2237         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2238
2239         return 0;
2240 }
2241
2242 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2243 {
2244         u32 spio_reg;
2245
2246         /* Only 2 SPIOs are configurable */
2247         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2248                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2249                 return -EINVAL;
2250         }
2251
2252         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2253         /* read SPIO and mask except the float bits */
2254         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2255
2256         switch (mode) {
2257         case MISC_SPIO_OUTPUT_LOW:
2258                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2259                 /* clear FLOAT and set CLR */
2260                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2261                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2262                 break;
2263
2264         case MISC_SPIO_OUTPUT_HIGH:
2265                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2266                 /* clear FLOAT and set SET */
2267                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2268                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2269                 break;
2270
2271         case MISC_SPIO_INPUT_HI_Z:
2272                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2273                 /* set FLOAT */
2274                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2275                 break;
2276
2277         default:
2278                 break;
2279         }
2280
2281         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2282         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2283
2284         return 0;
2285 }
2286
2287 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2288 {
2289         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2290
2291         bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2292                                            ADVERTISED_Pause);
2293         switch (bp->link_vars.ieee_fc &
2294                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2295         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2296                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2297                                                   ADVERTISED_Pause);
2298                 break;
2299
2300         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2301                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2302                 break;
2303
2304         default:
2305                 break;
2306         }
2307 }
2308
2309 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2310 {
2311         /* Initialize link parameters structure variables
2312          * It is recommended to turn off RX FC for jumbo frames
2313          *  for better performance
2314          */
2315         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2316                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2317         else
2318                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2319 }
2320
2321 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2322 {
2323         u32 pause_enabled = 0;
2324
2325         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2326                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2327                         pause_enabled = 1;
2328
2329                 REG_WR(bp, BAR_USTRORM_INTMEM +
2330                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2331                        pause_enabled);
2332         }
2333
2334         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2335            pause_enabled ? "enabled" : "disabled");
2336 }
2337
2338 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2339 {
2340         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2341         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2342
2343         if (!BP_NOMCP(bp)) {
2344                 bnx2x_set_requested_fc(bp);
2345                 bnx2x_acquire_phy_lock(bp);
2346
2347                 if (load_mode == LOAD_DIAG) {
2348                         struct link_params *lp = &bp->link_params;
2349                         lp->loopback_mode = LOOPBACK_XGXS;
2350                         /* Prefer doing PHY loopback at highest speed */
2351                         if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2352                                 if (lp->speed_cap_mask[cfx_idx] &
2353                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2354                                         lp->req_line_speed[cfx_idx] =
2355                                         SPEED_20000;
2356                                 else if (lp->speed_cap_mask[cfx_idx] &
2357                                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2358                                                 lp->req_line_speed[cfx_idx] =
2359                                                 SPEED_10000;
2360                                 else
2361                                         lp->req_line_speed[cfx_idx] =
2362                                         SPEED_1000;
2363                         }
2364                 }
2365
2366                 if (load_mode == LOAD_LOOPBACK_EXT) {
2367                         struct link_params *lp = &bp->link_params;
2368                         lp->loopback_mode = LOOPBACK_EXT;
2369                 }
2370
2371                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2372
2373                 bnx2x_release_phy_lock(bp);
2374
2375                 bnx2x_init_dropless_fc(bp);
2376
2377                 bnx2x_calc_fc_adv(bp);
2378
2379                 if (bp->link_vars.link_up) {
2380                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2381                         bnx2x_link_report(bp);
2382                 }
2383                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2384                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2385                 return rc;
2386         }
2387         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2388         return -EINVAL;
2389 }
2390
2391 void bnx2x_link_set(struct bnx2x *bp)
2392 {
2393         if (!BP_NOMCP(bp)) {
2394                 bnx2x_acquire_phy_lock(bp);
2395                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2396                 bnx2x_release_phy_lock(bp);
2397
2398                 bnx2x_init_dropless_fc(bp);
2399
2400                 bnx2x_calc_fc_adv(bp);
2401         } else
2402                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2403 }
2404
2405 static void bnx2x__link_reset(struct bnx2x *bp)
2406 {
2407         if (!BP_NOMCP(bp)) {
2408                 bnx2x_acquire_phy_lock(bp);
2409                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2410                 bnx2x_release_phy_lock(bp);
2411         } else
2412                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2413 }
2414
2415 void bnx2x_force_link_reset(struct bnx2x *bp)
2416 {
2417         bnx2x_acquire_phy_lock(bp);
2418         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2419         bnx2x_release_phy_lock(bp);
2420 }
2421
2422 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2423 {
2424         u8 rc = 0;
2425
2426         if (!BP_NOMCP(bp)) {
2427                 bnx2x_acquire_phy_lock(bp);
2428                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2429                                      is_serdes);
2430                 bnx2x_release_phy_lock(bp);
2431         } else
2432                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2433
2434         return rc;
2435 }
2436
2437 /* Calculates the sum of vn_min_rates.
2438    It's needed for further normalizing of the min_rates.
2439    Returns:
2440      sum of vn_min_rates.
2441        or
2442      0 - if all the min_rates are 0.
2443      In the later case fairness algorithm should be deactivated.
2444      If not all min_rates are zero then those that are zeroes will be set to 1.
2445  */
2446 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2447                                       struct cmng_init_input *input)
2448 {
2449         int all_zero = 1;
2450         int vn;
2451
2452         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2453                 u32 vn_cfg = bp->mf_config[vn];
2454                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2455                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2456
2457                 /* Skip hidden vns */
2458                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2459                         vn_min_rate = 0;
2460                 /* If min rate is zero - set it to 1 */
2461                 else if (!vn_min_rate)
2462                         vn_min_rate = DEF_MIN_RATE;
2463                 else
2464                         all_zero = 0;
2465
2466                 input->vnic_min_rate[vn] = vn_min_rate;
2467         }
2468
2469         /* if ETS or all min rates are zeros - disable fairness */
2470         if (BNX2X_IS_ETS_ENABLED(bp)) {
2471                 input->flags.cmng_enables &=
2472                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2473                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2474         } else if (all_zero) {
2475                 input->flags.cmng_enables &=
2476                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2477                 DP(NETIF_MSG_IFUP,
2478                    "All MIN values are zeroes fairness will be disabled\n");
2479         } else
2480                 input->flags.cmng_enables |=
2481                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2482 }
2483
2484 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2485                                     struct cmng_init_input *input)
2486 {
2487         u16 vn_max_rate;
2488         u32 vn_cfg = bp->mf_config[vn];
2489
2490         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2491                 vn_max_rate = 0;
2492         else {
2493                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2494
2495                 if (IS_MF_SI(bp)) {
2496                         /* maxCfg in percents of linkspeed */
2497                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2498                 } else /* SD modes */
2499                         /* maxCfg is absolute in 100Mb units */
2500                         vn_max_rate = maxCfg * 100;
2501         }
2502
2503         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2504
2505         input->vnic_max_rate[vn] = vn_max_rate;
2506 }
2507
2508 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2509 {
2510         if (CHIP_REV_IS_SLOW(bp))
2511                 return CMNG_FNS_NONE;
2512         if (IS_MF(bp))
2513                 return CMNG_FNS_MINMAX;
2514
2515         return CMNG_FNS_NONE;
2516 }
2517
2518 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2519 {
2520         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2521
2522         if (BP_NOMCP(bp))
2523                 return; /* what should be the default value in this case */
2524
2525         /* For 2 port configuration the absolute function number formula
2526          * is:
2527          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2528          *
2529          *      and there are 4 functions per port
2530          *
2531          * For 4 port configuration it is
2532          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2533          *
2534          *      and there are 2 functions per port
2535          */
2536         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2537                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2538
2539                 if (func >= E1H_FUNC_MAX)
2540                         break;
2541
2542                 bp->mf_config[vn] =
2543                         MF_CFG_RD(bp, func_mf_config[func].config);
2544         }
2545         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2546                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2547                 bp->flags |= MF_FUNC_DIS;
2548         } else {
2549                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2550                 bp->flags &= ~MF_FUNC_DIS;
2551         }
2552 }
2553
2554 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2555 {
2556         struct cmng_init_input input;
2557         memset(&input, 0, sizeof(struct cmng_init_input));
2558
2559         input.port_rate = bp->link_vars.line_speed;
2560
2561         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2562                 int vn;
2563
2564                 /* read mf conf from shmem */
2565                 if (read_cfg)
2566                         bnx2x_read_mf_cfg(bp);
2567
2568                 /* vn_weight_sum and enable fairness if not 0 */
2569                 bnx2x_calc_vn_min(bp, &input);
2570
2571                 /* calculate and set min-max rate for each vn */
2572                 if (bp->port.pmf)
2573                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2574                                 bnx2x_calc_vn_max(bp, vn, &input);
2575
2576                 /* always enable rate shaping and fairness */
2577                 input.flags.cmng_enables |=
2578                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2579
2580                 bnx2x_init_cmng(&input, &bp->cmng);
2581                 return;
2582         }
2583
2584         /* rate shaping and fairness are disabled */
2585         DP(NETIF_MSG_IFUP,
2586            "rate shaping and fairness are disabled\n");
2587 }
2588
2589 static void storm_memset_cmng(struct bnx2x *bp,
2590                               struct cmng_init *cmng,
2591                               u8 port)
2592 {
2593         int vn;
2594         size_t size = sizeof(struct cmng_struct_per_port);
2595
2596         u32 addr = BAR_XSTRORM_INTMEM +
2597                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2598
2599         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2600
2601         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2602                 int func = func_by_vn(bp, vn);
2603
2604                 addr = BAR_XSTRORM_INTMEM +
2605                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2606                 size = sizeof(struct rate_shaping_vars_per_vn);
2607                 __storm_memset_struct(bp, addr, size,
2608                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2609
2610                 addr = BAR_XSTRORM_INTMEM +
2611                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2612                 size = sizeof(struct fairness_vars_per_vn);
2613                 __storm_memset_struct(bp, addr, size,
2614                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2615         }
2616 }
2617
2618 /* init cmng mode in HW according to local configuration */
2619 void bnx2x_set_local_cmng(struct bnx2x *bp)
2620 {
2621         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2622
2623         if (cmng_fns != CMNG_FNS_NONE) {
2624                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2625                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2626         } else {
2627                 /* rate shaping and fairness are disabled */
2628                 DP(NETIF_MSG_IFUP,
2629                    "single function mode without fairness\n");
2630         }
2631 }
2632
2633 /* This function is called upon link interrupt */
2634 static void bnx2x_link_attn(struct bnx2x *bp)
2635 {
2636         /* Make sure that we are synced with the current statistics */
2637         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2638
2639         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2640
2641         bnx2x_init_dropless_fc(bp);
2642
2643         if (bp->link_vars.link_up) {
2644
2645                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2646                         struct host_port_stats *pstats;
2647
2648                         pstats = bnx2x_sp(bp, port_stats);
2649                         /* reset old mac stats */
2650                         memset(&(pstats->mac_stx[0]), 0,
2651                                sizeof(struct mac_stx));
2652                 }
2653                 if (bp->state == BNX2X_STATE_OPEN)
2654                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2655         }
2656
2657         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2658                 bnx2x_set_local_cmng(bp);
2659
2660         __bnx2x_link_report(bp);
2661
2662         if (IS_MF(bp))
2663                 bnx2x_link_sync_notify(bp);
2664 }
2665
2666 void bnx2x__link_status_update(struct bnx2x *bp)
2667 {
2668         if (bp->state != BNX2X_STATE_OPEN)
2669                 return;
2670
2671         /* read updated dcb configuration */
2672         if (IS_PF(bp)) {
2673                 bnx2x_dcbx_pmf_update(bp);
2674                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2675                 if (bp->link_vars.link_up)
2676                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2677                 else
2678                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2679                         /* indicate link status */
2680                 bnx2x_link_report(bp);
2681
2682         } else { /* VF */
2683                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2684                                           SUPPORTED_10baseT_Full |
2685                                           SUPPORTED_100baseT_Half |
2686                                           SUPPORTED_100baseT_Full |
2687                                           SUPPORTED_1000baseT_Full |
2688                                           SUPPORTED_2500baseX_Full |
2689                                           SUPPORTED_10000baseT_Full |
2690                                           SUPPORTED_TP |
2691                                           SUPPORTED_FIBRE |
2692                                           SUPPORTED_Autoneg |
2693                                           SUPPORTED_Pause |
2694                                           SUPPORTED_Asym_Pause);
2695                 bp->port.advertising[0] = bp->port.supported[0];
2696
2697                 bp->link_params.bp = bp;
2698                 bp->link_params.port = BP_PORT(bp);
2699                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2700                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2701                 bp->link_params.req_line_speed[0] = SPEED_10000;
2702                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2703                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2704                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2705                 bp->link_vars.line_speed = SPEED_10000;
2706                 bp->link_vars.link_status =
2707                         (LINK_STATUS_LINK_UP |
2708                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2709                 bp->link_vars.link_up = 1;
2710                 bp->link_vars.duplex = DUPLEX_FULL;
2711                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2712                 __bnx2x_link_report(bp);
2713
2714                 bnx2x_sample_bulletin(bp);
2715
2716                 /* if bulletin board did not have an update for link status
2717                  * __bnx2x_link_report will report current status
2718                  * but it will NOT duplicate report in case of already reported
2719                  * during sampling bulletin board.
2720                  */
2721                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2722         }
2723 }
2724
2725 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2726                                   u16 vlan_val, u8 allowed_prio)
2727 {
2728         struct bnx2x_func_state_params func_params = {NULL};
2729         struct bnx2x_func_afex_update_params *f_update_params =
2730                 &func_params.params.afex_update;
2731
2732         func_params.f_obj = &bp->func_obj;
2733         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2734
2735         /* no need to wait for RAMROD completion, so don't
2736          * set RAMROD_COMP_WAIT flag
2737          */
2738
2739         f_update_params->vif_id = vifid;
2740         f_update_params->afex_default_vlan = vlan_val;
2741         f_update_params->allowed_priorities = allowed_prio;
2742
2743         /* if ramrod can not be sent, response to MCP immediately */
2744         if (bnx2x_func_state_change(bp, &func_params) < 0)
2745                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2746
2747         return 0;
2748 }
2749
2750 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2751                                           u16 vif_index, u8 func_bit_map)
2752 {
2753         struct bnx2x_func_state_params func_params = {NULL};
2754         struct bnx2x_func_afex_viflists_params *update_params =
2755                 &func_params.params.afex_viflists;
2756         int rc;
2757         u32 drv_msg_code;
2758
2759         /* validate only LIST_SET and LIST_GET are received from switch */
2760         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2761                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2762                           cmd_type);
2763
2764         func_params.f_obj = &bp->func_obj;
2765         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2766
2767         /* set parameters according to cmd_type */
2768         update_params->afex_vif_list_command = cmd_type;
2769         update_params->vif_list_index = vif_index;
2770         update_params->func_bit_map =
2771                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2772         update_params->func_to_clear = 0;
2773         drv_msg_code =
2774                 (cmd_type == VIF_LIST_RULE_GET) ?
2775                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2776                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2777
2778         /* if ramrod can not be sent, respond to MCP immediately for
2779          * SET and GET requests (other are not triggered from MCP)
2780          */
2781         rc = bnx2x_func_state_change(bp, &func_params);
2782         if (rc < 0)
2783                 bnx2x_fw_command(bp, drv_msg_code, 0);
2784
2785         return 0;
2786 }
2787
2788 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2789 {
2790         struct afex_stats afex_stats;
2791         u32 func = BP_ABS_FUNC(bp);
2792         u32 mf_config;
2793         u16 vlan_val;
2794         u32 vlan_prio;
2795         u16 vif_id;
2796         u8 allowed_prio;
2797         u8 vlan_mode;
2798         u32 addr_to_write, vifid, addrs, stats_type, i;
2799
2800         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2801                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2802                 DP(BNX2X_MSG_MCP,
2803                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2804                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2805         }
2806
2807         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2808                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2809                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2810                 DP(BNX2X_MSG_MCP,
2811                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2812                    vifid, addrs);
2813                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2814                                                addrs);
2815         }
2816
2817         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2818                 addr_to_write = SHMEM2_RD(bp,
2819                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2820                 stats_type = SHMEM2_RD(bp,
2821                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2822
2823                 DP(BNX2X_MSG_MCP,
2824                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2825                    addr_to_write);
2826
2827                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2828
2829                 /* write response to scratchpad, for MCP */
2830                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2831                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2832                                *(((u32 *)(&afex_stats))+i));
2833
2834                 /* send ack message to MCP */
2835                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2836         }
2837
2838         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2839                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2840                 bp->mf_config[BP_VN(bp)] = mf_config;
2841                 DP(BNX2X_MSG_MCP,
2842                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2843                    mf_config);
2844
2845                 /* if VIF_SET is "enabled" */
2846                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2847                         /* set rate limit directly to internal RAM */
2848                         struct cmng_init_input cmng_input;
2849                         struct rate_shaping_vars_per_vn m_rs_vn;
2850                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2851                         u32 addr = BAR_XSTRORM_INTMEM +
2852                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2853
2854                         bp->mf_config[BP_VN(bp)] = mf_config;
2855
2856                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2857                         m_rs_vn.vn_counter.rate =
2858                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2859                         m_rs_vn.vn_counter.quota =
2860                                 (m_rs_vn.vn_counter.rate *
2861                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2862
2863                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2864
2865                         /* read relevant values from mf_cfg struct in shmem */
2866                         vif_id =
2867                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2868                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2869                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2870                         vlan_val =
2871                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2872                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2873                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2874                         vlan_prio = (mf_config &
2875                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2876                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2877                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2878                         vlan_mode =
2879                                 (MF_CFG_RD(bp,
2880                                            func_mf_config[func].afex_config) &
2881                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2882                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2883                         allowed_prio =
2884                                 (MF_CFG_RD(bp,
2885                                            func_mf_config[func].afex_config) &
2886                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2887                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2888
2889                         /* send ramrod to FW, return in case of failure */
2890                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2891                                                    allowed_prio))
2892                                 return;
2893
2894                         bp->afex_def_vlan_tag = vlan_val;
2895                         bp->afex_vlan_mode = vlan_mode;
2896                 } else {
2897                         /* notify link down because BP->flags is disabled */
2898                         bnx2x_link_report(bp);
2899
2900                         /* send INVALID VIF ramrod to FW */
2901                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2902
2903                         /* Reset the default afex VLAN */
2904                         bp->afex_def_vlan_tag = -1;
2905                 }
2906         }
2907 }
2908
2909 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2910 {
2911         struct bnx2x_func_switch_update_params *switch_update_params;
2912         struct bnx2x_func_state_params func_params;
2913
2914         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2915         switch_update_params = &func_params.params.switch_update;
2916         func_params.f_obj = &bp->func_obj;
2917         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2918
2919         if (IS_MF_UFP(bp)) {
2920                 int func = BP_ABS_FUNC(bp);
2921                 u32 val;
2922
2923                 /* Re-learn the S-tag from shmem */
2924                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2925                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2926                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2927                         bp->mf_ov = val;
2928                 } else {
2929                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2930                         goto fail;
2931                 }
2932
2933                 /* Configure new S-tag in LLH */
2934                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2935                        bp->mf_ov);
2936
2937                 /* Send Ramrod to update FW of change */
2938                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2939                           &switch_update_params->changes);
2940                 switch_update_params->vlan = bp->mf_ov;
2941
2942                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2943                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2944                                   bp->mf_ov);
2945                         goto fail;
2946                 }
2947
2948                 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov);
2949
2950                 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2951
2952                 return;
2953         }
2954
2955         /* not supported by SW yet */
2956 fail:
2957         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2958 }
2959
2960 static void bnx2x_pmf_update(struct bnx2x *bp)
2961 {
2962         int port = BP_PORT(bp);
2963         u32 val;
2964
2965         bp->port.pmf = 1;
2966         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2967
2968         /*
2969          * We need the mb() to ensure the ordering between the writing to
2970          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2971          */
2972         smp_mb();
2973
2974         /* queue a periodic task */
2975         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2976
2977         bnx2x_dcbx_pmf_update(bp);
2978
2979         /* enable nig attention */
2980         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2981         if (bp->common.int_block == INT_BLOCK_HC) {
2982                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2983                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2984         } else if (!CHIP_IS_E1x(bp)) {
2985                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2986                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2987         }
2988
2989         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2990 }
2991
2992 /* end of Link */
2993
2994 /* slow path */
2995
2996 /*
2997  * General service functions
2998  */
2999
3000 /* send the MCP a request, block until there is a reply */
3001 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3002 {
3003         int mb_idx = BP_FW_MB_IDX(bp);
3004         u32 seq;
3005         u32 rc = 0;
3006         u32 cnt = 1;
3007         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3008
3009         mutex_lock(&bp->fw_mb_mutex);
3010         seq = ++bp->fw_seq;
3011         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3012         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3013
3014         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3015                         (command | seq), param);
3016
3017         do {
3018                 /* let the FW do it's magic ... */
3019                 msleep(delay);
3020
3021                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3022
3023                 /* Give the FW up to 5 second (500*10ms) */
3024         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3025
3026         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3027            cnt*delay, rc, seq);
3028
3029         /* is this a reply to our command? */
3030         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3031                 rc &= FW_MSG_CODE_MASK;
3032         else {
3033                 /* FW BUG! */
3034                 BNX2X_ERR("FW failed to respond!\n");
3035                 bnx2x_fw_dump(bp);
3036                 rc = 0;
3037         }
3038         mutex_unlock(&bp->fw_mb_mutex);
3039
3040         return rc;
3041 }
3042
3043 static void storm_memset_func_cfg(struct bnx2x *bp,
3044                                  struct tstorm_eth_function_common_config *tcfg,
3045                                  u16 abs_fid)
3046 {
3047         size_t size = sizeof(struct tstorm_eth_function_common_config);
3048
3049         u32 addr = BAR_TSTRORM_INTMEM +
3050                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3051
3052         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3053 }
3054
3055 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3056 {
3057         if (CHIP_IS_E1x(bp)) {
3058                 struct tstorm_eth_function_common_config tcfg = {0};
3059
3060                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3061         }
3062
3063         /* Enable the function in the FW */
3064         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3065         storm_memset_func_en(bp, p->func_id, 1);
3066
3067         /* spq */
3068         if (p->func_flgs & FUNC_FLG_SPQ) {
3069                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3070                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3071                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3072         }
3073 }
3074
3075 /**
3076  * bnx2x_get_common_flags - Return common flags
3077  *
3078  * @bp          device handle
3079  * @fp          queue handle
3080  * @zero_stats  TRUE if statistics zeroing is needed
3081  *
3082  * Return the flags that are common for the Tx-only and not normal connections.
3083  */
3084 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3085                                             struct bnx2x_fastpath *fp,
3086                                             bool zero_stats)
3087 {
3088         unsigned long flags = 0;
3089
3090         /* PF driver will always initialize the Queue to an ACTIVE state */
3091         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3092
3093         /* tx only connections collect statistics (on the same index as the
3094          * parent connection). The statistics are zeroed when the parent
3095          * connection is initialized.
3096          */
3097
3098         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3099         if (zero_stats)
3100                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3101
3102         if (bp->flags & TX_SWITCHING)
3103                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3104
3105         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3106         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3107
3108 #ifdef BNX2X_STOP_ON_ERROR
3109         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3110 #endif
3111
3112         return flags;
3113 }
3114
3115 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3116                                        struct bnx2x_fastpath *fp,
3117                                        bool leading)
3118 {
3119         unsigned long flags = 0;
3120
3121         /* calculate other queue flags */
3122         if (IS_MF_SD(bp))
3123                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3124
3125         if (IS_FCOE_FP(fp)) {
3126                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3127                 /* For FCoE - force usage of default priority (for afex) */
3128                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3129         }
3130
3131         if (fp->mode != TPA_MODE_DISABLED) {
3132                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3133                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3134                 if (fp->mode == TPA_MODE_GRO)
3135                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3136         }
3137
3138         if (leading) {
3139                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3140                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3141         }
3142
3143         /* Always set HW VLAN stripping */
3144         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3145
3146         /* configure silent vlan removal */
3147         if (IS_MF_AFEX(bp))
3148                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3149
3150         return flags | bnx2x_get_common_flags(bp, fp, true);
3151 }
3152
3153 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3154         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3155         u8 cos)
3156 {
3157         gen_init->stat_id = bnx2x_stats_id(fp);
3158         gen_init->spcl_id = fp->cl_id;
3159
3160         /* Always use mini-jumbo MTU for FCoE L2 ring */
3161         if (IS_FCOE_FP(fp))
3162                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3163         else
3164                 gen_init->mtu = bp->dev->mtu;
3165
3166         gen_init->cos = cos;
3167
3168         gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3169 }
3170
3171 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3172         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3173         struct bnx2x_rxq_setup_params *rxq_init)
3174 {
3175         u8 max_sge = 0;
3176         u16 sge_sz = 0;
3177         u16 tpa_agg_size = 0;
3178
3179         if (fp->mode != TPA_MODE_DISABLED) {
3180                 pause->sge_th_lo = SGE_TH_LO(bp);
3181                 pause->sge_th_hi = SGE_TH_HI(bp);
3182
3183                 /* validate SGE ring has enough to cross high threshold */
3184                 WARN_ON(bp->dropless_fc &&
3185                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3186                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3187
3188                 tpa_agg_size = TPA_AGG_SIZE;
3189                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3190                         SGE_PAGE_SHIFT;
3191                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3192                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3193                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3194         }
3195
3196         /* pause - not for e1 */
3197         if (!CHIP_IS_E1(bp)) {
3198                 pause->bd_th_lo = BD_TH_LO(bp);
3199                 pause->bd_th_hi = BD_TH_HI(bp);
3200
3201                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3202                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3203                 /*
3204                  * validate that rings have enough entries to cross
3205                  * high thresholds
3206                  */
3207                 WARN_ON(bp->dropless_fc &&
3208                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3209                                 bp->rx_ring_size);
3210                 WARN_ON(bp->dropless_fc &&
3211                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3212                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3213
3214                 pause->pri_map = 1;
3215         }
3216
3217         /* rxq setup */
3218         rxq_init->dscr_map = fp->rx_desc_mapping;
3219         rxq_init->sge_map = fp->rx_sge_mapping;
3220         rxq_init->rcq_map = fp->rx_comp_mapping;
3221         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3222
3223         /* This should be a maximum number of data bytes that may be
3224          * placed on the BD (not including paddings).
3225          */
3226         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3227                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3228
3229         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3230         rxq_init->tpa_agg_sz = tpa_agg_size;
3231         rxq_init->sge_buf_sz = sge_sz;
3232         rxq_init->max_sges_pkt = max_sge;
3233         rxq_init->rss_engine_id = BP_FUNC(bp);
3234         rxq_init->mcast_engine_id = BP_FUNC(bp);
3235
3236         /* Maximum number or simultaneous TPA aggregation for this Queue.
3237          *
3238          * For PF Clients it should be the maximum available number.
3239          * VF driver(s) may want to define it to a smaller value.
3240          */
3241         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3242
3243         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3244         rxq_init->fw_sb_id = fp->fw_sb_id;
3245
3246         if (IS_FCOE_FP(fp))
3247                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3248         else
3249                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3250         /* configure silent vlan removal
3251          * if multi function mode is afex, then mask default vlan
3252          */
3253         if (IS_MF_AFEX(bp)) {
3254                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3255                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3256         }
3257 }
3258
3259 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3260         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3261         u8 cos)
3262 {
3263         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3264         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3265         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3266         txq_init->fw_sb_id = fp->fw_sb_id;
3267
3268         /*
3269          * set the tss leading client id for TX classification ==
3270          * leading RSS client id
3271          */
3272         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3273
3274         if (IS_FCOE_FP(fp)) {
3275                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3276                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3277         }
3278 }
3279
3280 static void bnx2x_pf_init(struct bnx2x *bp)
3281 {
3282         struct bnx2x_func_init_params func_init = {0};
3283         struct event_ring_data eq_data = { {0} };
3284         u16 flags;
3285
3286         if (!CHIP_IS_E1x(bp)) {
3287                 /* reset IGU PF statistics: MSIX + ATTN */
3288                 /* PF */
3289                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3290                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3291                            (CHIP_MODE_IS_4_PORT(bp) ?
3292                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3293                 /* ATTN */
3294                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3295                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3296                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3297                            (CHIP_MODE_IS_4_PORT(bp) ?
3298                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3299         }
3300
3301         /* function setup flags */
3302         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3303
3304         /* This flag is relevant for E1x only.
3305          * E2 doesn't have a TPA configuration in a function level.
3306          */
3307         flags |= (bp->dev->features & NETIF_F_LRO) ? FUNC_FLG_TPA : 0;
3308
3309         func_init.func_flgs = flags;
3310         func_init.pf_id = BP_FUNC(bp);
3311         func_init.func_id = BP_FUNC(bp);
3312         func_init.spq_map = bp->spq_mapping;
3313         func_init.spq_prod = bp->spq_prod_idx;
3314
3315         bnx2x_func_init(bp, &func_init);
3316
3317         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3318
3319         /*
3320          * Congestion management values depend on the link rate
3321          * There is no active link so initial link rate is set to 10 Gbps.
3322          * When the link comes up The congestion management values are
3323          * re-calculated according to the actual link rate.
3324          */
3325         bp->link_vars.line_speed = SPEED_10000;
3326         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3327
3328         /* Only the PMF sets the HW */
3329         if (bp->port.pmf)
3330                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3331
3332         /* init Event Queue - PCI bus guarantees correct endianity*/
3333         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3334         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3335         eq_data.producer = bp->eq_prod;
3336         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3337         eq_data.sb_id = DEF_SB_ID;
3338         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3339 }
3340
3341 static void bnx2x_e1h_disable(struct bnx2x *bp)
3342 {
3343         int port = BP_PORT(bp);
3344
3345         bnx2x_tx_disable(bp);
3346
3347         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3348 }
3349
3350 static void bnx2x_e1h_enable(struct bnx2x *bp)
3351 {
3352         int port = BP_PORT(bp);
3353
3354         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3355                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3356
3357         /* Tx queue should be only re-enabled */
3358         netif_tx_wake_all_queues(bp->dev);
3359
3360         /*
3361          * Should not call netif_carrier_on since it will be called if the link
3362          * is up when checking for link state
3363          */
3364 }
3365
3366 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3367
3368 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3369 {
3370         struct eth_stats_info *ether_stat =
3371                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3372         struct bnx2x_vlan_mac_obj *mac_obj =
3373                 &bp->sp_objs->mac_obj;
3374         int i;
3375
3376         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3377                 ETH_STAT_INFO_VERSION_LEN);
3378
3379         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3380          * mac_local field in ether_stat struct. The base address is offset by 2
3381          * bytes to account for the field being 8 bytes but a mac address is
3382          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3383          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3384          * allocated by the ether_stat struct, so the macs will land in their
3385          * proper positions.
3386          */
3387         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3388                 memset(ether_stat->mac_local + i, 0,
3389                        sizeof(ether_stat->mac_local[0]));
3390         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3391                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3392                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3393                                 ETH_ALEN);
3394         ether_stat->mtu_size = bp->dev->mtu;
3395         if (bp->dev->features & NETIF_F_RXCSUM)
3396                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3397         if (bp->dev->features & NETIF_F_TSO)
3398                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3399         ether_stat->feature_flags |= bp->common.boot_mode;
3400
3401         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3402
3403         ether_stat->txq_size = bp->tx_ring_size;
3404         ether_stat->rxq_size = bp->rx_ring_size;
3405
3406 #ifdef CONFIG_BNX2X_SRIOV
3407         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3408 #endif
3409 }
3410
3411 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3412 {
3413         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3414         struct fcoe_stats_info *fcoe_stat =
3415                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3416
3417         if (!CNIC_LOADED(bp))
3418                 return;
3419
3420         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3421
3422         fcoe_stat->qos_priority =
3423                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3424
3425         /* insert FCoE stats from ramrod response */
3426         if (!NO_FCOE(bp)) {
3427                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3428                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3429                         tstorm_queue_statistics;
3430
3431                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3432                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3433                         xstorm_queue_statistics;
3434
3435                 struct fcoe_statistics_params *fw_fcoe_stat =
3436                         &bp->fw_stats_data->fcoe;
3437
3438                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3439                           fcoe_stat->rx_bytes_lo,
3440                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3441
3442                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3443                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3444                           fcoe_stat->rx_bytes_lo,
3445                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3446
3447                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3448                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3449                           fcoe_stat->rx_bytes_lo,
3450                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3451
3452                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3453                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3454                           fcoe_stat->rx_bytes_lo,
3455                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3456
3457                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458                           fcoe_stat->rx_frames_lo,
3459                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3460
3461                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462                           fcoe_stat->rx_frames_lo,
3463                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3464
3465                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466                           fcoe_stat->rx_frames_lo,
3467                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3468
3469                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3470                           fcoe_stat->rx_frames_lo,
3471                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3472
3473                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3474                           fcoe_stat->tx_bytes_lo,
3475                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3476
3477                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3478                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3479                           fcoe_stat->tx_bytes_lo,
3480                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3481
3482                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3483                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3484                           fcoe_stat->tx_bytes_lo,
3485                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3486
3487                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3488                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3489                           fcoe_stat->tx_bytes_lo,
3490                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3491
3492                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493                           fcoe_stat->tx_frames_lo,
3494                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3495
3496                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497                           fcoe_stat->tx_frames_lo,
3498                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3499
3500                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501                           fcoe_stat->tx_frames_lo,
3502                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3503
3504                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3505                           fcoe_stat->tx_frames_lo,
3506                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3507         }
3508
3509         /* ask L5 driver to add data to the struct */
3510         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3511 }
3512
3513 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3514 {
3515         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3516         struct iscsi_stats_info *iscsi_stat =
3517                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3518
3519         if (!CNIC_LOADED(bp))
3520                 return;
3521
3522         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3523                ETH_ALEN);
3524
3525         iscsi_stat->qos_priority =
3526                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3527
3528         /* ask L5 driver to add data to the struct */
3529         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3530 }
3531
3532 /* called due to MCP event (on pmf):
3533  *      reread new bandwidth configuration
3534  *      configure FW
3535  *      notify others function about the change
3536  */
3537 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3538 {
3539         if (bp->link_vars.link_up) {
3540                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3541                 bnx2x_link_sync_notify(bp);
3542         }
3543         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3544 }
3545
3546 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3547 {
3548         bnx2x_config_mf_bw(bp);
3549         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3550 }
3551
3552 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3553 {
3554         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3555         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3556 }
3557
3558 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3559 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3560
3561 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3562 {
3563         enum drv_info_opcode op_code;
3564         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3565         bool release = false;
3566         int wait;
3567
3568         /* if drv_info version supported by MFW doesn't match - send NACK */
3569         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3570                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3571                 return;
3572         }
3573
3574         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3575                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3576
3577         /* Must prevent other flows from accessing drv_info_to_mcp */
3578         mutex_lock(&bp->drv_info_mutex);
3579
3580         memset(&bp->slowpath->drv_info_to_mcp, 0,
3581                sizeof(union drv_info_to_mcp));
3582
3583         switch (op_code) {
3584         case ETH_STATS_OPCODE:
3585                 bnx2x_drv_info_ether_stat(bp);
3586                 break;
3587         case FCOE_STATS_OPCODE:
3588                 bnx2x_drv_info_fcoe_stat(bp);
3589                 break;
3590         case ISCSI_STATS_OPCODE:
3591                 bnx2x_drv_info_iscsi_stat(bp);
3592                 break;
3593         default:
3594                 /* if op code isn't supported - send NACK */
3595                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3596                 goto out;
3597         }
3598
3599         /* if we got drv_info attn from MFW then these fields are defined in
3600          * shmem2 for sure
3601          */
3602         SHMEM2_WR(bp, drv_info_host_addr_lo,
3603                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3604         SHMEM2_WR(bp, drv_info_host_addr_hi,
3605                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3606
3607         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3608
3609         /* Since possible management wants both this and get_driver_version
3610          * need to wait until management notifies us it finished utilizing
3611          * the buffer.
3612          */
3613         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3614                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3615         } else if (!bp->drv_info_mng_owner) {
3616                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3617
3618                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3619                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3620
3621                         /* Management is done; need to clear indication */
3622                         if (indication & bit) {
3623                                 SHMEM2_WR(bp, mfw_drv_indication,
3624                                           indication & ~bit);
3625                                 release = true;
3626                                 break;
3627                         }
3628
3629                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3630                 }
3631         }
3632         if (!release) {
3633                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3634                 bp->drv_info_mng_owner = true;
3635         }
3636
3637 out:
3638         mutex_unlock(&bp->drv_info_mutex);
3639 }
3640
3641 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3642 {
3643         u8 vals[4];
3644         int i = 0;
3645
3646         if (bnx2x_format) {
3647                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3648                            &vals[0], &vals[1], &vals[2], &vals[3]);
3649                 if (i > 0)
3650                         vals[0] -= '0';
3651         } else {
3652                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3653                            &vals[0], &vals[1], &vals[2], &vals[3]);
3654         }
3655
3656         while (i < 4)
3657                 vals[i++] = 0;
3658
3659         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3660 }
3661
3662 void bnx2x_update_mng_version(struct bnx2x *bp)
3663 {
3664         u32 iscsiver = DRV_VER_NOT_LOADED;
3665         u32 fcoever = DRV_VER_NOT_LOADED;
3666         u32 ethver = DRV_VER_NOT_LOADED;
3667         int idx = BP_FW_MB_IDX(bp);
3668         u8 *version;
3669
3670         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3671                 return;
3672
3673         mutex_lock(&bp->drv_info_mutex);
3674         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3675         if (bp->drv_info_mng_owner)
3676                 goto out;
3677
3678         if (bp->state != BNX2X_STATE_OPEN)
3679                 goto out;
3680
3681         /* Parse ethernet driver version */
3682         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3683         if (!CNIC_LOADED(bp))
3684                 goto out;
3685
3686         /* Try getting storage driver version via cnic */
3687         memset(&bp->slowpath->drv_info_to_mcp, 0,
3688                sizeof(union drv_info_to_mcp));
3689         bnx2x_drv_info_iscsi_stat(bp);
3690         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3691         iscsiver = bnx2x_update_mng_version_utility(version, false);
3692
3693         memset(&bp->slowpath->drv_info_to_mcp, 0,
3694                sizeof(union drv_info_to_mcp));
3695         bnx2x_drv_info_fcoe_stat(bp);
3696         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3697         fcoever = bnx2x_update_mng_version_utility(version, false);
3698
3699 out:
3700         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3701         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3702         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3703
3704         mutex_unlock(&bp->drv_info_mutex);
3705
3706         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3707            ethver, iscsiver, fcoever);
3708 }
3709
3710 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3711 {
3712         u32 cmd_ok, cmd_fail;
3713
3714         /* sanity */
3715         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3716             event & DRV_STATUS_OEM_EVENT_MASK) {
3717                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3718                 return;
3719         }
3720
3721         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3722                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3723                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3724         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3725                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3726                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3727         }
3728
3729         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3730
3731         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3732                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3733                 /* This is the only place besides the function initialization
3734                  * where the bp->flags can change so it is done without any
3735                  * locks
3736                  */
3737                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3738                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3739                         bp->flags |= MF_FUNC_DIS;
3740
3741                         bnx2x_e1h_disable(bp);
3742                 } else {
3743                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3744                         bp->flags &= ~MF_FUNC_DIS;
3745
3746                         bnx2x_e1h_enable(bp);
3747                 }
3748                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3749                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3750         }
3751
3752         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3753                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3754                 bnx2x_config_mf_bw(bp);
3755                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3756                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3757         }
3758
3759         /* Report results to MCP */
3760         if (event)
3761                 bnx2x_fw_command(bp, cmd_fail, 0);
3762         else
3763                 bnx2x_fw_command(bp, cmd_ok, 0);
3764 }
3765
3766 /* must be called under the spq lock */
3767 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3768 {
3769         struct eth_spe *next_spe = bp->spq_prod_bd;
3770
3771         if (bp->spq_prod_bd == bp->spq_last_bd) {
3772                 bp->spq_prod_bd = bp->spq;
3773                 bp->spq_prod_idx = 0;
3774                 DP(BNX2X_MSG_SP, "end of spq\n");
3775         } else {
3776                 bp->spq_prod_bd++;
3777                 bp->spq_prod_idx++;
3778         }
3779         return next_spe;
3780 }
3781
3782 /* must be called under the spq lock */
3783 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3784 {
3785         int func = BP_FUNC(bp);
3786
3787         /*
3788          * Make sure that BD data is updated before writing the producer:
3789          * BD data is written to the memory, the producer is read from the
3790          * memory, thus we need a full memory barrier to ensure the ordering.
3791          */
3792         mb();
3793
3794         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3795                  bp->spq_prod_idx);
3796         mmiowb();
3797 }
3798
3799 /**
3800  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3801  *
3802  * @cmd:        command to check
3803  * @cmd_type:   command type
3804  */
3805 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3806 {
3807         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3808             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3809             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3810             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3811             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3812             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3813             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3814                 return true;
3815         else
3816                 return false;
3817 }
3818
3819 /**
3820  * bnx2x_sp_post - place a single command on an SP ring
3821  *
3822  * @bp:         driver handle
3823  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3824  * @cid:        SW CID the command is related to
3825  * @data_hi:    command private data address (high 32 bits)
3826  * @data_lo:    command private data address (low 32 bits)
3827  * @cmd_type:   command type (e.g. NONE, ETH)
3828  *
3829  * SP data is handled as if it's always an address pair, thus data fields are
3830  * not swapped to little endian in upper functions. Instead this function swaps
3831  * data as if it's two u32 fields.
3832  */
3833 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3834                   u32 data_hi, u32 data_lo, int cmd_type)
3835 {
3836         struct eth_spe *spe;
3837         u16 type;
3838         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3839
3840 #ifdef BNX2X_STOP_ON_ERROR
3841         if (unlikely(bp->panic)) {
3842                 BNX2X_ERR("Can't post SP when there is panic\n");
3843                 return -EIO;
3844         }
3845 #endif
3846
3847         spin_lock_bh(&bp->spq_lock);
3848
3849         if (common) {
3850                 if (!atomic_read(&bp->eq_spq_left)) {
3851                         BNX2X_ERR("BUG! EQ ring full!\n");
3852                         spin_unlock_bh(&bp->spq_lock);
3853                         bnx2x_panic();
3854                         return -EBUSY;
3855                 }
3856         } else if (!atomic_read(&bp->cq_spq_left)) {
3857                         BNX2X_ERR("BUG! SPQ ring full!\n");
3858                         spin_unlock_bh(&bp->spq_lock);
3859                         bnx2x_panic();
3860                         return -EBUSY;
3861         }
3862
3863         spe = bnx2x_sp_get_next(bp);
3864
3865         /* CID needs port number to be encoded int it */
3866         spe->hdr.conn_and_cmd_data =
3867                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3868                                     HW_CID(bp, cid));
3869
3870         /* In some cases, type may already contain the func-id
3871          * mainly in SRIOV related use cases, so we add it here only
3872          * if it's not already set.
3873          */
3874         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3875                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3876                         SPE_HDR_CONN_TYPE;
3877                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3878                          SPE_HDR_FUNCTION_ID);
3879         } else {
3880                 type = cmd_type;
3881         }
3882
3883         spe->hdr.type = cpu_to_le16(type);
3884
3885         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3886         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3887
3888         /*
3889          * It's ok if the actual decrement is issued towards the memory
3890          * somewhere between the spin_lock and spin_unlock. Thus no
3891          * more explicit memory barrier is needed.
3892          */
3893         if (common)
3894                 atomic_dec(&bp->eq_spq_left);
3895         else
3896                 atomic_dec(&bp->cq_spq_left);
3897
3898         DP(BNX2X_MSG_SP,
3899            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3900            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3901            (u32)(U64_LO(bp->spq_mapping) +
3902            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3903            HW_CID(bp, cid), data_hi, data_lo, type,
3904            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3905
3906         bnx2x_sp_prod_update(bp);
3907         spin_unlock_bh(&bp->spq_lock);
3908         return 0;
3909 }
3910
3911 /* acquire split MCP access lock register */
3912 static int bnx2x_acquire_alr(struct bnx2x *bp)
3913 {
3914         u32 j, val;
3915         int rc = 0;
3916
3917         might_sleep();
3918         for (j = 0; j < 1000; j++) {
3919                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3920                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3921                 if (val & MCPR_ACCESS_LOCK_LOCK)
3922                         break;
3923
3924                 usleep_range(5000, 10000);
3925         }
3926         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3927                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3928                 rc = -EBUSY;
3929         }
3930
3931         return rc;
3932 }
3933
3934 /* release split MCP access lock register */
3935 static void bnx2x_release_alr(struct bnx2x *bp)
3936 {
3937         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3938 }
3939
3940 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3941 #define BNX2X_DEF_SB_IDX        0x0002
3942
3943 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3944 {
3945         struct host_sp_status_block *def_sb = bp->def_status_blk;
3946         u16 rc = 0;
3947
3948         barrier(); /* status block is written to by the chip */
3949         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3950                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3951                 rc |= BNX2X_DEF_SB_ATT_IDX;
3952         }
3953
3954         if (bp->def_idx != def_sb->sp_sb.running_index) {
3955                 bp->def_idx = def_sb->sp_sb.running_index;
3956                 rc |= BNX2X_DEF_SB_IDX;
3957         }
3958
3959         /* Do not reorder: indices reading should complete before handling */
3960         barrier();
3961         return rc;
3962 }
3963
3964 /*
3965  * slow path service functions
3966  */
3967
3968 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3969 {
3970         int port = BP_PORT(bp);
3971         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3972                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3973         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3974                                        NIG_REG_MASK_INTERRUPT_PORT0;
3975         u32 aeu_mask;
3976         u32 nig_mask = 0;
3977         u32 reg_addr;
3978
3979         if (bp->attn_state & asserted)
3980                 BNX2X_ERR("IGU ERROR\n");
3981
3982         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3983         aeu_mask = REG_RD(bp, aeu_addr);
3984
3985         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3986            aeu_mask, asserted);
3987         aeu_mask &= ~(asserted & 0x3ff);
3988         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3989
3990         REG_WR(bp, aeu_addr, aeu_mask);
3991         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3992
3993         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3994         bp->attn_state |= asserted;
3995         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3996
3997         if (asserted & ATTN_HARD_WIRED_MASK) {
3998                 if (asserted & ATTN_NIG_FOR_FUNC) {
3999
4000                         bnx2x_acquire_phy_lock(bp);
4001
4002                         /* save nig interrupt mask */
4003                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4004
4005                         /* If nig_mask is not set, no need to call the update
4006                          * function.
4007                          */
4008                         if (nig_mask) {
4009                                 REG_WR(bp, nig_int_mask_addr, 0);
4010
4011                                 bnx2x_link_attn(bp);
4012                         }
4013
4014                         /* handle unicore attn? */
4015                 }
4016                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4017                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4018
4019                 if (asserted & GPIO_2_FUNC)
4020                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4021
4022                 if (asserted & GPIO_3_FUNC)
4023                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4024
4025                 if (asserted & GPIO_4_FUNC)
4026                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4027
4028                 if (port == 0) {
4029                         if (asserted & ATTN_GENERAL_ATTN_1) {
4030                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4031                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4032                         }
4033                         if (asserted & ATTN_GENERAL_ATTN_2) {
4034                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4035                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4036                         }
4037                         if (asserted & ATTN_GENERAL_ATTN_3) {
4038                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4039                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4040                         }
4041                 } else {
4042                         if (asserted & ATTN_GENERAL_ATTN_4) {
4043                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4044                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4045                         }
4046                         if (asserted & ATTN_GENERAL_ATTN_5) {
4047                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4048                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4049                         }
4050                         if (asserted & ATTN_GENERAL_ATTN_6) {
4051                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4052                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4053                         }
4054                 }
4055
4056         } /* if hardwired */
4057
4058         if (bp->common.int_block == INT_BLOCK_HC)
4059                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4060                             COMMAND_REG_ATTN_BITS_SET);
4061         else
4062                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4063
4064         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4065            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4066         REG_WR(bp, reg_addr, asserted);
4067
4068         /* now set back the mask */
4069         if (asserted & ATTN_NIG_FOR_FUNC) {
4070                 /* Verify that IGU ack through BAR was written before restoring
4071                  * NIG mask. This loop should exit after 2-3 iterations max.
4072                  */
4073                 if (bp->common.int_block != INT_BLOCK_HC) {
4074                         u32 cnt = 0, igu_acked;
4075                         do {
4076                                 igu_acked = REG_RD(bp,
4077                                                    IGU_REG_ATTENTION_ACK_BITS);
4078                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4079                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4080                         if (!igu_acked)
4081                                 DP(NETIF_MSG_HW,
4082                                    "Failed to verify IGU ack on time\n");
4083                         barrier();
4084                 }
4085                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4086                 bnx2x_release_phy_lock(bp);
4087         }
4088 }
4089
4090 static void bnx2x_fan_failure(struct bnx2x *bp)
4091 {
4092         int port = BP_PORT(bp);
4093         u32 ext_phy_config;
4094         /* mark the failure */
4095         ext_phy_config =
4096                 SHMEM_RD(bp,
4097                          dev_info.port_hw_config[port].external_phy_config);
4098
4099         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4100         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4101         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4102                  ext_phy_config);
4103
4104         /* log the failure */
4105         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4106                             "Please contact OEM Support for assistance\n");
4107
4108         /* Schedule device reset (unload)
4109          * This is due to some boards consuming sufficient power when driver is
4110          * up to overheat if fan fails.
4111          */
4112         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4113 }
4114
4115 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4116 {
4117         int port = BP_PORT(bp);
4118         int reg_offset;
4119         u32 val;
4120
4121         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4122                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4123
4124         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4125
4126                 val = REG_RD(bp, reg_offset);
4127                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4128                 REG_WR(bp, reg_offset, val);
4129
4130                 BNX2X_ERR("SPIO5 hw attention\n");
4131
4132                 /* Fan failure attention */
4133                 bnx2x_hw_reset_phy(&bp->link_params);
4134                 bnx2x_fan_failure(bp);
4135         }
4136
4137         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4138                 bnx2x_acquire_phy_lock(bp);
4139                 bnx2x_handle_module_detect_int(&bp->link_params);
4140                 bnx2x_release_phy_lock(bp);
4141         }
4142
4143         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4144
4145                 val = REG_RD(bp, reg_offset);
4146                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4147                 REG_WR(bp, reg_offset, val);
4148
4149                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4150                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4151                 bnx2x_panic();
4152         }
4153 }
4154
4155 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4156 {
4157         u32 val;
4158
4159         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4160
4161                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4162                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4163                 /* DORQ discard attention */
4164                 if (val & 0x2)
4165                         BNX2X_ERR("FATAL error from DORQ\n");
4166         }
4167
4168         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4169
4170                 int port = BP_PORT(bp);
4171                 int reg_offset;
4172
4173                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4174                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4175
4176                 val = REG_RD(bp, reg_offset);
4177                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4178                 REG_WR(bp, reg_offset, val);
4179
4180                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4181                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4182                 bnx2x_panic();
4183         }
4184 }
4185
4186 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4187 {
4188         u32 val;
4189
4190         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4191
4192                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4193                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4194                 /* CFC error attention */
4195                 if (val & 0x2)
4196                         BNX2X_ERR("FATAL error from CFC\n");
4197         }
4198
4199         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4200                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4201                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4202                 /* RQ_USDMDP_FIFO_OVERFLOW */
4203                 if (val & 0x18000)
4204                         BNX2X_ERR("FATAL error from PXP\n");
4205
4206                 if (!CHIP_IS_E1x(bp)) {
4207                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4208                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4209                 }
4210         }
4211
4212         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4213
4214                 int port = BP_PORT(bp);
4215                 int reg_offset;
4216
4217                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4218                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4219
4220                 val = REG_RD(bp, reg_offset);
4221                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4222                 REG_WR(bp, reg_offset, val);
4223
4224                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4225                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4226                 bnx2x_panic();
4227         }
4228 }
4229
4230 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4231 {
4232         u32 val;
4233
4234         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4235
4236                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4237                         int func = BP_FUNC(bp);
4238
4239                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4240                         bnx2x_read_mf_cfg(bp);
4241                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4242                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4243                         val = SHMEM_RD(bp,
4244                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4245
4246                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4247                                    DRV_STATUS_OEM_EVENT_MASK))
4248                                 bnx2x_oem_event(bp,
4249                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4250                                                 DRV_STATUS_OEM_EVENT_MASK)));
4251
4252                         if (val & DRV_STATUS_SET_MF_BW)
4253                                 bnx2x_set_mf_bw(bp);
4254
4255                         if (val & DRV_STATUS_DRV_INFO_REQ)
4256                                 bnx2x_handle_drv_info_req(bp);
4257
4258                         if (val & DRV_STATUS_VF_DISABLED)
4259                                 bnx2x_schedule_iov_task(bp,
4260                                                         BNX2X_IOV_HANDLE_FLR);
4261
4262                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4263                                 bnx2x_pmf_update(bp);
4264
4265                         if (bp->port.pmf &&
4266                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4267                                 bp->dcbx_enabled > 0)
4268                                 /* start dcbx state machine */
4269                                 bnx2x_dcbx_set_params(bp,
4270                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4271                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4272                                 bnx2x_handle_afex_cmd(bp,
4273                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4274                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4275                                 bnx2x_handle_eee_event(bp);
4276
4277                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4278                                 bnx2x_handle_update_svid_cmd(bp);
4279
4280                         if (bp->link_vars.periodic_flags &
4281                             PERIODIC_FLAGS_LINK_EVENT) {
4282                                 /*  sync with link */
4283                                 bnx2x_acquire_phy_lock(bp);
4284                                 bp->link_vars.periodic_flags &=
4285                                         ~PERIODIC_FLAGS_LINK_EVENT;
4286                                 bnx2x_release_phy_lock(bp);
4287                                 if (IS_MF(bp))
4288                                         bnx2x_link_sync_notify(bp);
4289                                 bnx2x_link_report(bp);
4290                         }
4291                         /* Always call it here: bnx2x_link_report() will
4292                          * prevent the link indication duplication.
4293                          */
4294                         bnx2x__link_status_update(bp);
4295                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4296
4297                         BNX2X_ERR("MC assert!\n");
4298                         bnx2x_mc_assert(bp);
4299                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4300                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4301                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4302                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4303                         bnx2x_panic();
4304
4305                 } else if (attn & BNX2X_MCP_ASSERT) {
4306
4307                         BNX2X_ERR("MCP assert!\n");
4308                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4309                         bnx2x_fw_dump(bp);
4310
4311                 } else
4312                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4313         }
4314
4315         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4316                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4317                 if (attn & BNX2X_GRC_TIMEOUT) {
4318                         val = CHIP_IS_E1(bp) ? 0 :
4319                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4320                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4321                 }
4322                 if (attn & BNX2X_GRC_RSV) {
4323                         val = CHIP_IS_E1(bp) ? 0 :
4324                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4325                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4326                 }
4327                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4328         }
4329 }
4330
4331 /*
4332  * Bits map:
4333  * 0-7   - Engine0 load counter.
4334  * 8-15  - Engine1 load counter.
4335  * 16    - Engine0 RESET_IN_PROGRESS bit.
4336  * 17    - Engine1 RESET_IN_PROGRESS bit.
4337  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4338  *         on the engine
4339  * 19    - Engine1 ONE_IS_LOADED.
4340  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4341  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4342  *         just the one belonging to its engine).
4343  *
4344  */
4345 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4346
4347 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4348 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4349 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4350 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4351 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4352 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4353 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4354
4355 /*
4356  * Set the GLOBAL_RESET bit.
4357  *
4358  * Should be run under rtnl lock
4359  */
4360 void bnx2x_set_reset_global(struct bnx2x *bp)
4361 {
4362         u32 val;
4363         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4364         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4365         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4366         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4367 }
4368
4369 /*
4370  * Clear the GLOBAL_RESET bit.
4371  *
4372  * Should be run under rtnl lock
4373  */
4374 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4375 {
4376         u32 val;
4377         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4378         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4379         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4380         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4381 }
4382
4383 /*
4384  * Checks the GLOBAL_RESET bit.
4385  *
4386  * should be run under rtnl lock
4387  */
4388 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4389 {
4390         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4391
4392         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4393         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4394 }
4395
4396 /*
4397  * Clear RESET_IN_PROGRESS bit for the current engine.
4398  *
4399  * Should be run under rtnl lock
4400  */
4401 static void bnx2x_set_reset_done(struct bnx2x *bp)
4402 {
4403         u32 val;
4404         u32 bit = BP_PATH(bp) ?
4405                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4406         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4407         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4408
4409         /* Clear the bit */
4410         val &= ~bit;
4411         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4412
4413         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4414 }
4415
4416 /*
4417  * Set RESET_IN_PROGRESS for the current engine.
4418  *
4419  * should be run under rtnl lock
4420  */
4421 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4422 {
4423         u32 val;
4424         u32 bit = BP_PATH(bp) ?
4425                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4426         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4427         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4428
4429         /* Set the bit */
4430         val |= bit;
4431         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4432         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4433 }
4434
4435 /*
4436  * Checks the RESET_IN_PROGRESS bit for the given engine.
4437  * should be run under rtnl lock
4438  */
4439 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4440 {
4441         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4442         u32 bit = engine ?
4443                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4444
4445         /* return false if bit is set */
4446         return (val & bit) ? false : true;
4447 }
4448
4449 /*
4450  * set pf load for the current pf.
4451  *
4452  * should be run under rtnl lock
4453  */
4454 void bnx2x_set_pf_load(struct bnx2x *bp)
4455 {
4456         u32 val1, val;
4457         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4458                              BNX2X_PATH0_LOAD_CNT_MASK;
4459         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4460                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4461
4462         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4463         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4464
4465         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4466
4467         /* get the current counter value */
4468         val1 = (val & mask) >> shift;
4469
4470         /* set bit of that PF */
4471         val1 |= (1 << bp->pf_num);
4472
4473         /* clear the old value */
4474         val &= ~mask;
4475
4476         /* set the new one */
4477         val |= ((val1 << shift) & mask);
4478
4479         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4480         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4481 }
4482
4483 /**
4484  * bnx2x_clear_pf_load - clear pf load mark
4485  *
4486  * @bp:         driver handle
4487  *
4488  * Should be run under rtnl lock.
4489  * Decrements the load counter for the current engine. Returns
4490  * whether other functions are still loaded
4491  */
4492 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4493 {
4494         u32 val1, val;
4495         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4496                              BNX2X_PATH0_LOAD_CNT_MASK;
4497         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4498                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4499
4500         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4501         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4502         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4503
4504         /* get the current counter value */
4505         val1 = (val & mask) >> shift;
4506
4507         /* clear bit of that PF */
4508         val1 &= ~(1 << bp->pf_num);
4509
4510         /* clear the old value */
4511         val &= ~mask;
4512
4513         /* set the new one */
4514         val |= ((val1 << shift) & mask);
4515
4516         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4517         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4518         return val1 != 0;
4519 }
4520
4521 /*
4522  * Read the load status for the current engine.
4523  *
4524  * should be run under rtnl lock
4525  */
4526 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4527 {
4528         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4529                              BNX2X_PATH0_LOAD_CNT_MASK);
4530         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4531                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4532         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4533
4534         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4535
4536         val = (val & mask) >> shift;
4537
4538         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4539            engine, val);
4540
4541         return val != 0;
4542 }
4543
4544 static void _print_parity(struct bnx2x *bp, u32 reg)
4545 {
4546         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4547 }
4548
4549 static void _print_next_block(int idx, const char *blk)
4550 {
4551         pr_cont("%s%s", idx ? ", " : "", blk);
4552 }
4553
4554 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4555                                             int *par_num, bool print)
4556 {
4557         u32 cur_bit;
4558         bool res;
4559         int i;
4560
4561         res = false;
4562
4563         for (i = 0; sig; i++) {
4564                 cur_bit = (0x1UL << i);
4565                 if (sig & cur_bit) {
4566                         res |= true; /* Each bit is real error! */
4567
4568                         if (print) {
4569                                 switch (cur_bit) {
4570                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4571                                         _print_next_block((*par_num)++, "BRB");
4572                                         _print_parity(bp,
4573                                                       BRB1_REG_BRB1_PRTY_STS);
4574                                         break;
4575                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4576                                         _print_next_block((*par_num)++,
4577                                                           "PARSER");
4578                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4579                                         break;
4580                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4581                                         _print_next_block((*par_num)++, "TSDM");
4582                                         _print_parity(bp,
4583                                                       TSDM_REG_TSDM_PRTY_STS);
4584                                         break;
4585                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4586                                         _print_next_block((*par_num)++,
4587                                                           "SEARCHER");
4588                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4589                                         break;
4590                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4591                                         _print_next_block((*par_num)++, "TCM");
4592                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4593                                         break;
4594                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4595                                         _print_next_block((*par_num)++,
4596                                                           "TSEMI");
4597                                         _print_parity(bp,
4598                                                       TSEM_REG_TSEM_PRTY_STS_0);
4599                                         _print_parity(bp,
4600                                                       TSEM_REG_TSEM_PRTY_STS_1);
4601                                         break;
4602                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4603                                         _print_next_block((*par_num)++, "XPB");
4604                                         _print_parity(bp, GRCBASE_XPB +
4605                                                           PB_REG_PB_PRTY_STS);
4606                                         break;
4607                                 }
4608                         }
4609
4610                         /* Clear the bit */
4611                         sig &= ~cur_bit;
4612                 }
4613         }
4614
4615         return res;
4616 }
4617
4618 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4619                                             int *par_num, bool *global,
4620                                             bool print)
4621 {
4622         u32 cur_bit;
4623         bool res;
4624         int i;
4625
4626         res = false;
4627
4628         for (i = 0; sig; i++) {
4629                 cur_bit = (0x1UL << i);
4630                 if (sig & cur_bit) {
4631                         res |= true; /* Each bit is real error! */
4632                         switch (cur_bit) {
4633                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4634                                 if (print) {
4635                                         _print_next_block((*par_num)++, "PBF");
4636                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4637                                 }
4638                                 break;
4639                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4640                                 if (print) {
4641                                         _print_next_block((*par_num)++, "QM");
4642                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4643                                 }
4644                                 break;
4645                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4646                                 if (print) {
4647                                         _print_next_block((*par_num)++, "TM");
4648                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4649                                 }
4650                                 break;
4651                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4652                                 if (print) {
4653                                         _print_next_block((*par_num)++, "XSDM");
4654                                         _print_parity(bp,
4655                                                       XSDM_REG_XSDM_PRTY_STS);
4656                                 }
4657                                 break;
4658                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4659                                 if (print) {
4660                                         _print_next_block((*par_num)++, "XCM");
4661                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4662                                 }
4663                                 break;
4664                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4665                                 if (print) {
4666                                         _print_next_block((*par_num)++,
4667                                                           "XSEMI");
4668                                         _print_parity(bp,
4669                                                       XSEM_REG_XSEM_PRTY_STS_0);
4670                                         _print_parity(bp,
4671                                                       XSEM_REG_XSEM_PRTY_STS_1);
4672                                 }
4673                                 break;
4674                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4675                                 if (print) {
4676                                         _print_next_block((*par_num)++,
4677                                                           "DOORBELLQ");
4678                                         _print_parity(bp,
4679                                                       DORQ_REG_DORQ_PRTY_STS);
4680                                 }
4681                                 break;
4682                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4683                                 if (print) {
4684                                         _print_next_block((*par_num)++, "NIG");
4685                                         if (CHIP_IS_E1x(bp)) {
4686                                                 _print_parity(bp,
4687                                                         NIG_REG_NIG_PRTY_STS);
4688                                         } else {
4689                                                 _print_parity(bp,
4690                                                         NIG_REG_NIG_PRTY_STS_0);
4691                                                 _print_parity(bp,
4692                                                         NIG_REG_NIG_PRTY_STS_1);
4693                                         }
4694                                 }
4695                                 break;
4696                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4697                                 if (print)
4698                                         _print_next_block((*par_num)++,
4699                                                           "VAUX PCI CORE");
4700                                 *global = true;
4701                                 break;
4702                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4703                                 if (print) {
4704                                         _print_next_block((*par_num)++,
4705                                                           "DEBUG");
4706                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4707                                 }
4708                                 break;
4709                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4710                                 if (print) {
4711                                         _print_next_block((*par_num)++, "USDM");
4712                                         _print_parity(bp,
4713                                                       USDM_REG_USDM_PRTY_STS);
4714                                 }
4715                                 break;
4716                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4717                                 if (print) {
4718                                         _print_next_block((*par_num)++, "UCM");
4719                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4720                                 }
4721                                 break;
4722                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4723                                 if (print) {
4724                                         _print_next_block((*par_num)++,
4725                                                           "USEMI");
4726                                         _print_parity(bp,
4727                                                       USEM_REG_USEM_PRTY_STS_0);
4728                                         _print_parity(bp,
4729                                                       USEM_REG_USEM_PRTY_STS_1);
4730                                 }
4731                                 break;
4732                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4733                                 if (print) {
4734                                         _print_next_block((*par_num)++, "UPB");
4735                                         _print_parity(bp, GRCBASE_UPB +
4736                                                           PB_REG_PB_PRTY_STS);
4737                                 }
4738                                 break;
4739                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4740                                 if (print) {
4741                                         _print_next_block((*par_num)++, "CSDM");
4742                                         _print_parity(bp,
4743                                                       CSDM_REG_CSDM_PRTY_STS);
4744                                 }
4745                                 break;
4746                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4747                                 if (print) {
4748                                         _print_next_block((*par_num)++, "CCM");
4749                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4750                                 }
4751                                 break;
4752                         }
4753
4754                         /* Clear the bit */
4755                         sig &= ~cur_bit;
4756                 }
4757         }
4758
4759         return res;
4760 }
4761
4762 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4763                                             int *par_num, bool print)
4764 {
4765         u32 cur_bit;
4766         bool res;
4767         int i;
4768
4769         res = false;
4770
4771         for (i = 0; sig; i++) {
4772                 cur_bit = (0x1UL << i);
4773                 if (sig & cur_bit) {
4774                         res = true; /* Each bit is real error! */
4775                         if (print) {
4776                                 switch (cur_bit) {
4777                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4778                                         _print_next_block((*par_num)++,
4779                                                           "CSEMI");
4780                                         _print_parity(bp,
4781                                                       CSEM_REG_CSEM_PRTY_STS_0);
4782                                         _print_parity(bp,
4783                                                       CSEM_REG_CSEM_PRTY_STS_1);
4784                                         break;
4785                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4786                                         _print_next_block((*par_num)++, "PXP");
4787                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4788                                         _print_parity(bp,
4789                                                       PXP2_REG_PXP2_PRTY_STS_0);
4790                                         _print_parity(bp,
4791                                                       PXP2_REG_PXP2_PRTY_STS_1);
4792                                         break;
4793                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4794                                         _print_next_block((*par_num)++,
4795                                                           "PXPPCICLOCKCLIENT");
4796                                         break;
4797                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4798                                         _print_next_block((*par_num)++, "CFC");
4799                                         _print_parity(bp,
4800                                                       CFC_REG_CFC_PRTY_STS);
4801                                         break;
4802                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4803                                         _print_next_block((*par_num)++, "CDU");
4804                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4805                                         break;
4806                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4807                                         _print_next_block((*par_num)++, "DMAE");
4808                                         _print_parity(bp,
4809                                                       DMAE_REG_DMAE_PRTY_STS);
4810                                         break;
4811                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4812                                         _print_next_block((*par_num)++, "IGU");
4813                                         if (CHIP_IS_E1x(bp))
4814                                                 _print_parity(bp,
4815                                                         HC_REG_HC_PRTY_STS);
4816                                         else
4817                                                 _print_parity(bp,
4818                                                         IGU_REG_IGU_PRTY_STS);
4819                                         break;
4820                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4821                                         _print_next_block((*par_num)++, "MISC");
4822                                         _print_parity(bp,
4823                                                       MISC_REG_MISC_PRTY_STS);
4824                                         break;
4825                                 }
4826                         }
4827
4828                         /* Clear the bit */
4829                         sig &= ~cur_bit;
4830                 }
4831         }
4832
4833         return res;
4834 }
4835
4836 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4837                                             int *par_num, bool *global,
4838                                             bool print)
4839 {
4840         bool res = false;
4841         u32 cur_bit;
4842         int i;
4843
4844         for (i = 0; sig; i++) {
4845                 cur_bit = (0x1UL << i);
4846                 if (sig & cur_bit) {
4847                         switch (cur_bit) {
4848                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4849                                 if (print)
4850                                         _print_next_block((*par_num)++,
4851                                                           "MCP ROM");
4852                                 *global = true;
4853                                 res = true;
4854                                 break;
4855                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4856                                 if (print)
4857                                         _print_next_block((*par_num)++,
4858                                                           "MCP UMP RX");
4859                                 *global = true;
4860                                 res = true;
4861                                 break;
4862                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4863                                 if (print)
4864                                         _print_next_block((*par_num)++,
4865                                                           "MCP UMP TX");
4866                                 *global = true;
4867                                 res = true;
4868                                 break;
4869                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4870                                 (*par_num)++;
4871                                 /* clear latched SCPAD PATIRY from MCP */
4872                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4873                                        1UL << 10);
4874                                 break;
4875                         }
4876
4877                         /* Clear the bit */
4878                         sig &= ~cur_bit;
4879                 }
4880         }
4881
4882         return res;
4883 }
4884
4885 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4886                                             int *par_num, bool print)
4887 {
4888         u32 cur_bit;
4889         bool res;
4890         int i;
4891
4892         res = false;
4893
4894         for (i = 0; sig; i++) {
4895                 cur_bit = (0x1UL << i);
4896                 if (sig & cur_bit) {
4897                         res = true; /* Each bit is real error! */
4898                         if (print) {
4899                                 switch (cur_bit) {
4900                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4901                                         _print_next_block((*par_num)++,
4902                                                           "PGLUE_B");
4903                                         _print_parity(bp,
4904                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4905                                         break;
4906                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4907                                         _print_next_block((*par_num)++, "ATC");
4908                                         _print_parity(bp,
4909                                                       ATC_REG_ATC_PRTY_STS);
4910                                         break;
4911                                 }
4912                         }
4913                         /* Clear the bit */
4914                         sig &= ~cur_bit;
4915                 }
4916         }
4917
4918         return res;
4919 }
4920
4921 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4922                               u32 *sig)
4923 {
4924         bool res = false;
4925
4926         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4927             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4928             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4929             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4930             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4931                 int par_num = 0;
4932
4933                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4934                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4935                           sig[0] & HW_PRTY_ASSERT_SET_0,
4936                           sig[1] & HW_PRTY_ASSERT_SET_1,
4937                           sig[2] & HW_PRTY_ASSERT_SET_2,
4938                           sig[3] & HW_PRTY_ASSERT_SET_3,
4939                           sig[4] & HW_PRTY_ASSERT_SET_4);
4940                 if (print) {
4941                         if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4942                              (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4943                              (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4944                              (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4945                              (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4946                                 netdev_err(bp->dev,
4947                                            "Parity errors detected in blocks: ");
4948                         } else {
4949                                 print = false;
4950                         }
4951                 }
4952                 res |= bnx2x_check_blocks_with_parity0(bp,
4953                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4954                 res |= bnx2x_check_blocks_with_parity1(bp,
4955                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4956                 res |= bnx2x_check_blocks_with_parity2(bp,
4957                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4958                 res |= bnx2x_check_blocks_with_parity3(bp,
4959                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4960                 res |= bnx2x_check_blocks_with_parity4(bp,
4961                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4962
4963                 if (print)
4964                         pr_cont("\n");
4965         }
4966
4967         return res;
4968 }
4969
4970 /**
4971  * bnx2x_chk_parity_attn - checks for parity attentions.
4972  *
4973  * @bp:         driver handle
4974  * @global:     true if there was a global attention
4975  * @print:      show parity attention in syslog
4976  */
4977 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4978 {
4979         struct attn_route attn = { {0} };
4980         int port = BP_PORT(bp);
4981
4982         attn.sig[0] = REG_RD(bp,
4983                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4984                              port*4);
4985         attn.sig[1] = REG_RD(bp,
4986                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4987                              port*4);
4988         attn.sig[2] = REG_RD(bp,
4989                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4990                              port*4);
4991         attn.sig[3] = REG_RD(bp,
4992                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4993                              port*4);
4994         /* Since MCP attentions can't be disabled inside the block, we need to
4995          * read AEU registers to see whether they're currently disabled
4996          */
4997         attn.sig[3] &= ((REG_RD(bp,
4998                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4999                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5000                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5001                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5002
5003         if (!CHIP_IS_E1x(bp))
5004                 attn.sig[4] = REG_RD(bp,
5005                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5006                                      port*4);
5007
5008         return bnx2x_parity_attn(bp, global, print, attn.sig);
5009 }
5010
5011 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5012 {
5013         u32 val;
5014         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5015
5016                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5017                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5018                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5019                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5020                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5021                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5022                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5023                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5024                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5025                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5026                 if (val &
5027                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5028                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5029                 if (val &
5030                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5031                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5032                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5033                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5034                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5035                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5036                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5037                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5038         }
5039         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5040                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5041                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5042                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5043                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5044                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5045                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5046                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5047                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5048                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5049                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5050                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5051                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5052                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5053                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5054         }
5055
5056         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5057                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5058                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5059                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5060                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5061         }
5062 }
5063
5064 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5065 {
5066         struct attn_route attn, *group_mask;
5067         int port = BP_PORT(bp);
5068         int index;
5069         u32 reg_addr;
5070         u32 val;
5071         u32 aeu_mask;
5072         bool global = false;
5073
5074         /* need to take HW lock because MCP or other port might also
5075            try to handle this event */
5076         bnx2x_acquire_alr(bp);
5077
5078         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5079 #ifndef BNX2X_STOP_ON_ERROR
5080                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5081                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5082                 /* Disable HW interrupts */
5083                 bnx2x_int_disable(bp);
5084                 /* In case of parity errors don't handle attentions so that
5085                  * other function would "see" parity errors.
5086                  */
5087 #else
5088                 bnx2x_panic();
5089 #endif
5090                 bnx2x_release_alr(bp);
5091                 return;
5092         }
5093
5094         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5095         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5096         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5097         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5098         if (!CHIP_IS_E1x(bp))
5099                 attn.sig[4] =
5100                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5101         else
5102                 attn.sig[4] = 0;
5103
5104         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5105            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5106
5107         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5108                 if (deasserted & (1 << index)) {
5109                         group_mask = &bp->attn_group[index];
5110
5111                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5112                            index,
5113                            group_mask->sig[0], group_mask->sig[1],
5114                            group_mask->sig[2], group_mask->sig[3],
5115                            group_mask->sig[4]);
5116
5117                         bnx2x_attn_int_deasserted4(bp,
5118                                         attn.sig[4] & group_mask->sig[4]);
5119                         bnx2x_attn_int_deasserted3(bp,
5120                                         attn.sig[3] & group_mask->sig[3]);
5121                         bnx2x_attn_int_deasserted1(bp,
5122                                         attn.sig[1] & group_mask->sig[1]);
5123                         bnx2x_attn_int_deasserted2(bp,
5124                                         attn.sig[2] & group_mask->sig[2]);
5125                         bnx2x_attn_int_deasserted0(bp,
5126                                         attn.sig[0] & group_mask->sig[0]);
5127                 }
5128         }
5129
5130         bnx2x_release_alr(bp);
5131
5132         if (bp->common.int_block == INT_BLOCK_HC)
5133                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5134                             COMMAND_REG_ATTN_BITS_CLR);
5135         else
5136                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5137
5138         val = ~deasserted;
5139         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5140            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5141         REG_WR(bp, reg_addr, val);
5142
5143         if (~bp->attn_state & deasserted)
5144                 BNX2X_ERR("IGU ERROR\n");
5145
5146         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5147                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5148
5149         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5150         aeu_mask = REG_RD(bp, reg_addr);
5151
5152         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5153            aeu_mask, deasserted);
5154         aeu_mask |= (deasserted & 0x3ff);
5155         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5156
5157         REG_WR(bp, reg_addr, aeu_mask);
5158         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5159
5160         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5161         bp->attn_state &= ~deasserted;
5162         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5163 }
5164
5165 static void bnx2x_attn_int(struct bnx2x *bp)
5166 {
5167         /* read local copy of bits */
5168         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5169                                                                 attn_bits);
5170         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5171                                                                 attn_bits_ack);
5172         u32 attn_state = bp->attn_state;
5173
5174         /* look for changed bits */
5175         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5176         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5177
5178         DP(NETIF_MSG_HW,
5179            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5180            attn_bits, attn_ack, asserted, deasserted);
5181
5182         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5183                 BNX2X_ERR("BAD attention state\n");
5184
5185         /* handle bits that were raised */
5186         if (asserted)
5187                 bnx2x_attn_int_asserted(bp, asserted);
5188
5189         if (deasserted)
5190                 bnx2x_attn_int_deasserted(bp, deasserted);
5191 }
5192
5193 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5194                       u16 index, u8 op, u8 update)
5195 {
5196         u32 igu_addr = bp->igu_base_addr;
5197         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5198         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5199                              igu_addr);
5200 }
5201
5202 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5203 {
5204         /* No memory barriers */
5205         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5206         mmiowb(); /* keep prod updates ordered */
5207 }
5208
5209 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5210                                       union event_ring_elem *elem)
5211 {
5212         u8 err = elem->message.error;
5213
5214         if (!bp->cnic_eth_dev.starting_cid  ||
5215             (cid < bp->cnic_eth_dev.starting_cid &&
5216             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5217                 return 1;
5218
5219         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5220
5221         if (unlikely(err)) {
5222
5223                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5224                           cid);
5225                 bnx2x_panic_dump(bp, false);
5226         }
5227         bnx2x_cnic_cfc_comp(bp, cid, err);
5228         return 0;
5229 }
5230
5231 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5232 {
5233         struct bnx2x_mcast_ramrod_params rparam;
5234         int rc;
5235
5236         memset(&rparam, 0, sizeof(rparam));
5237
5238         rparam.mcast_obj = &bp->mcast_obj;
5239
5240         netif_addr_lock_bh(bp->dev);
5241
5242         /* Clear pending state for the last command */
5243         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5244
5245         /* If there are pending mcast commands - send them */
5246         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5247                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5248                 if (rc < 0)
5249                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5250                                   rc);
5251         }
5252
5253         netif_addr_unlock_bh(bp->dev);
5254 }
5255
5256 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5257                                             union event_ring_elem *elem)
5258 {
5259         unsigned long ramrod_flags = 0;
5260         int rc = 0;
5261         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5262         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5263
5264         /* Always push next commands out, don't wait here */
5265         __set_bit(RAMROD_CONT, &ramrod_flags);
5266
5267         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5268                             >> BNX2X_SWCID_SHIFT) {
5269         case BNX2X_FILTER_MAC_PENDING:
5270                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5271                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5272                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5273                 else
5274                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5275
5276                 break;
5277         case BNX2X_FILTER_MCAST_PENDING:
5278                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5279                 /* This is only relevant for 57710 where multicast MACs are
5280                  * configured as unicast MACs using the same ramrod.
5281                  */
5282                 bnx2x_handle_mcast_eqe(bp);
5283                 return;
5284         default:
5285                 BNX2X_ERR("Unsupported classification command: %d\n",
5286                           elem->message.data.eth_event.echo);
5287                 return;
5288         }
5289
5290         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5291
5292         if (rc < 0)
5293                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5294         else if (rc > 0)
5295                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5296 }
5297
5298 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5299
5300 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5301 {
5302         netif_addr_lock_bh(bp->dev);
5303
5304         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5305
5306         /* Send rx_mode command again if was requested */
5307         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5308                 bnx2x_set_storm_rx_mode(bp);
5309         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5310                                     &bp->sp_state))
5311                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5312         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5313                                     &bp->sp_state))
5314                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5315
5316         netif_addr_unlock_bh(bp->dev);
5317 }
5318
5319 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5320                                               union event_ring_elem *elem)
5321 {
5322         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5323                 DP(BNX2X_MSG_SP,
5324                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5325                    elem->message.data.vif_list_event.func_bit_map);
5326                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5327                         elem->message.data.vif_list_event.func_bit_map);
5328         } else if (elem->message.data.vif_list_event.echo ==
5329                    VIF_LIST_RULE_SET) {
5330                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5331                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5332         }
5333 }
5334
5335 /* called with rtnl_lock */
5336 static void bnx2x_after_function_update(struct bnx2x *bp)
5337 {
5338         int q, rc;
5339         struct bnx2x_fastpath *fp;
5340         struct bnx2x_queue_state_params queue_params = {NULL};
5341         struct bnx2x_queue_update_params *q_update_params =
5342                 &queue_params.params.update;
5343
5344         /* Send Q update command with afex vlan removal values for all Qs */
5345         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5346
5347         /* set silent vlan removal values according to vlan mode */
5348         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5349                   &q_update_params->update_flags);
5350         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5351                   &q_update_params->update_flags);
5352         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5353
5354         /* in access mode mark mask and value are 0 to strip all vlans */
5355         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5356                 q_update_params->silent_removal_value = 0;
5357                 q_update_params->silent_removal_mask = 0;
5358         } else {
5359                 q_update_params->silent_removal_value =
5360                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5361                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5362         }
5363
5364         for_each_eth_queue(bp, q) {
5365                 /* Set the appropriate Queue object */
5366                 fp = &bp->fp[q];
5367                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5368
5369                 /* send the ramrod */
5370                 rc = bnx2x_queue_state_change(bp, &queue_params);
5371                 if (rc < 0)
5372                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5373                                   q);
5374         }
5375
5376         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5377                 fp = &bp->fp[FCOE_IDX(bp)];
5378                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5379
5380                 /* clear pending completion bit */
5381                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5382
5383                 /* mark latest Q bit */
5384                 smp_mb__before_atomic();
5385                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5386                 smp_mb__after_atomic();
5387
5388                 /* send Q update ramrod for FCoE Q */
5389                 rc = bnx2x_queue_state_change(bp, &queue_params);
5390                 if (rc < 0)
5391                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5392                                   q);
5393         } else {
5394                 /* If no FCoE ring - ACK MCP now */
5395                 bnx2x_link_report(bp);
5396                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5397         }
5398 }
5399
5400 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5401         struct bnx2x *bp, u32 cid)
5402 {
5403         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5404
5405         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5406                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5407         else
5408                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5409 }
5410
5411 static void bnx2x_eq_int(struct bnx2x *bp)
5412 {
5413         u16 hw_cons, sw_cons, sw_prod;
5414         union event_ring_elem *elem;
5415         u8 echo;
5416         u32 cid;
5417         u8 opcode;
5418         int rc, spqe_cnt = 0;
5419         struct bnx2x_queue_sp_obj *q_obj;
5420         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5421         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5422
5423         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5424
5425         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5426          * when we get the next-page we need to adjust so the loop
5427          * condition below will be met. The next element is the size of a
5428          * regular element and hence incrementing by 1
5429          */
5430         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5431                 hw_cons++;
5432
5433         /* This function may never run in parallel with itself for a
5434          * specific bp, thus there is no need in "paired" read memory
5435          * barrier here.
5436          */
5437         sw_cons = bp->eq_cons;
5438         sw_prod = bp->eq_prod;
5439
5440         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5441                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5442
5443         for (; sw_cons != hw_cons;
5444               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5445
5446                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5447
5448                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5449                 if (!rc) {
5450                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5451                            rc);
5452                         goto next_spqe;
5453                 }
5454
5455                 /* elem CID originates from FW; actually LE */
5456                 cid = SW_CID((__force __le32)
5457                              elem->message.data.cfc_del_event.cid);
5458                 opcode = elem->message.opcode;
5459
5460                 /* handle eq element */
5461                 switch (opcode) {
5462                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5463                         bnx2x_vf_mbx_schedule(bp,
5464                                               &elem->message.data.vf_pf_event);
5465                         continue;
5466
5467                 case EVENT_RING_OPCODE_STAT_QUERY:
5468                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5469                                "got statistics comp event %d\n",
5470                                bp->stats_comp++);
5471                         /* nothing to do with stats comp */
5472                         goto next_spqe;
5473
5474                 case EVENT_RING_OPCODE_CFC_DEL:
5475                         /* handle according to cid range */
5476                         /*
5477                          * we may want to verify here that the bp state is
5478                          * HALTING
5479                          */
5480                         DP(BNX2X_MSG_SP,
5481                            "got delete ramrod for MULTI[%d]\n", cid);
5482
5483                         if (CNIC_LOADED(bp) &&
5484                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5485                                 goto next_spqe;
5486
5487                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5488
5489                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5490                                 break;
5491
5492                         goto next_spqe;
5493
5494                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5495                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5496                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5497                         if (f_obj->complete_cmd(bp, f_obj,
5498                                                 BNX2X_F_CMD_TX_STOP))
5499                                 break;
5500                         goto next_spqe;
5501
5502                 case EVENT_RING_OPCODE_START_TRAFFIC:
5503                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5504                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5505                         if (f_obj->complete_cmd(bp, f_obj,
5506                                                 BNX2X_F_CMD_TX_START))
5507                                 break;
5508                         goto next_spqe;
5509
5510                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5511                         echo = elem->message.data.function_update_event.echo;
5512                         if (echo == SWITCH_UPDATE) {
5513                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5514                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5515                                 if (f_obj->complete_cmd(
5516                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5517                                         break;
5518
5519                         } else {
5520                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5521
5522                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5523                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5524                                 f_obj->complete_cmd(bp, f_obj,
5525                                                     BNX2X_F_CMD_AFEX_UPDATE);
5526
5527                                 /* We will perform the Queues update from
5528                                  * sp_rtnl task as all Queue SP operations
5529                                  * should run under rtnl_lock.
5530                                  */
5531                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5532                         }
5533
5534                         goto next_spqe;
5535
5536                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5537                         f_obj->complete_cmd(bp, f_obj,
5538                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5539                         bnx2x_after_afex_vif_lists(bp, elem);
5540                         goto next_spqe;
5541                 case EVENT_RING_OPCODE_FUNCTION_START:
5542                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5543                            "got FUNC_START ramrod\n");
5544                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5545                                 break;
5546
5547                         goto next_spqe;
5548
5549                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5550                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5551                            "got FUNC_STOP ramrod\n");
5552                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5553                                 break;
5554
5555                         goto next_spqe;
5556
5557                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5558                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5559                            "got set_timesync ramrod completion\n");
5560                         if (f_obj->complete_cmd(bp, f_obj,
5561                                                 BNX2X_F_CMD_SET_TIMESYNC))
5562                                 break;
5563                         goto next_spqe;
5564                 }
5565
5566                 switch (opcode | bp->state) {
5567                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5568                       BNX2X_STATE_OPEN):
5569                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5570                       BNX2X_STATE_OPENING_WAIT4_PORT):
5571                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5572                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5573                         cid = elem->message.data.eth_event.echo &
5574                                 BNX2X_SWCID_MASK;
5575                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5576                            cid);
5577                         rss_raw->clear_pending(rss_raw);
5578                         break;
5579
5580                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5581                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5582                 case (EVENT_RING_OPCODE_SET_MAC |
5583                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5584                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5585                       BNX2X_STATE_OPEN):
5586                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5587                       BNX2X_STATE_DIAG):
5588                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5589                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5590                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5591                         bnx2x_handle_classification_eqe(bp, elem);
5592                         break;
5593
5594                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5595                       BNX2X_STATE_OPEN):
5596                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5597                       BNX2X_STATE_DIAG):
5598                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5599                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5600                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5601                         bnx2x_handle_mcast_eqe(bp);
5602                         break;
5603
5604                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5605                       BNX2X_STATE_OPEN):
5606                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5607                       BNX2X_STATE_DIAG):
5608                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5609                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5610                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5611                         bnx2x_handle_rx_mode_eqe(bp);
5612                         break;
5613                 default:
5614                         /* unknown event log error and continue */
5615                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5616                                   elem->message.opcode, bp->state);
5617                 }
5618 next_spqe:
5619                 spqe_cnt++;
5620         } /* for */
5621
5622         smp_mb__before_atomic();
5623         atomic_add(spqe_cnt, &bp->eq_spq_left);
5624
5625         bp->eq_cons = sw_cons;
5626         bp->eq_prod = sw_prod;
5627         /* Make sure that above mem writes were issued towards the memory */
5628         smp_wmb();
5629
5630         /* update producer */
5631         bnx2x_update_eq_prod(bp, bp->eq_prod);
5632 }
5633
5634 static void bnx2x_sp_task(struct work_struct *work)
5635 {
5636         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5637
5638         DP(BNX2X_MSG_SP, "sp task invoked\n");
5639
5640         /* make sure the atomic interrupt_occurred has been written */
5641         smp_rmb();
5642         if (atomic_read(&bp->interrupt_occurred)) {
5643
5644                 /* what work needs to be performed? */
5645                 u16 status = bnx2x_update_dsb_idx(bp);
5646
5647                 DP(BNX2X_MSG_SP, "status %x\n", status);
5648                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5649                 atomic_set(&bp->interrupt_occurred, 0);
5650
5651                 /* HW attentions */
5652                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5653                         bnx2x_attn_int(bp);
5654                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5655                 }
5656
5657                 /* SP events: STAT_QUERY and others */
5658                 if (status & BNX2X_DEF_SB_IDX) {
5659                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5660
5661                 if (FCOE_INIT(bp) &&
5662                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5663                                 /* Prevent local bottom-halves from running as
5664                                  * we are going to change the local NAPI list.
5665                                  */
5666                                 local_bh_disable();
5667                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5668                                 local_bh_enable();
5669                         }
5670
5671                         /* Handle EQ completions */
5672                         bnx2x_eq_int(bp);
5673                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5674                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5675
5676                         status &= ~BNX2X_DEF_SB_IDX;
5677                 }
5678
5679                 /* if status is non zero then perhaps something went wrong */
5680                 if (unlikely(status))
5681                         DP(BNX2X_MSG_SP,
5682                            "got an unknown interrupt! (status 0x%x)\n", status);
5683
5684                 /* ack status block only if something was actually handled */
5685                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5686                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5687         }
5688
5689         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5690         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5691                                &bp->sp_state)) {
5692                 bnx2x_link_report(bp);
5693                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5694         }
5695 }
5696
5697 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5698 {
5699         struct net_device *dev = dev_instance;
5700         struct bnx2x *bp = netdev_priv(dev);
5701
5702         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5703                      IGU_INT_DISABLE, 0);
5704
5705 #ifdef BNX2X_STOP_ON_ERROR
5706         if (unlikely(bp->panic))
5707                 return IRQ_HANDLED;
5708 #endif
5709
5710         if (CNIC_LOADED(bp)) {
5711                 struct cnic_ops *c_ops;
5712
5713                 rcu_read_lock();
5714                 c_ops = rcu_dereference(bp->cnic_ops);
5715                 if (c_ops)
5716                         c_ops->cnic_handler(bp->cnic_data, NULL);
5717                 rcu_read_unlock();
5718         }
5719
5720         /* schedule sp task to perform default status block work, ack
5721          * attentions and enable interrupts.
5722          */
5723         bnx2x_schedule_sp_task(bp);
5724
5725         return IRQ_HANDLED;
5726 }
5727
5728 /* end of slow path */
5729
5730 void bnx2x_drv_pulse(struct bnx2x *bp)
5731 {
5732         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5733                  bp->fw_drv_pulse_wr_seq);
5734 }
5735
5736 static void bnx2x_timer(unsigned long data)
5737 {
5738         struct bnx2x *bp = (struct bnx2x *) data;
5739
5740         if (!netif_running(bp->dev))
5741                 return;
5742
5743         if (IS_PF(bp) &&
5744             !BP_NOMCP(bp)) {
5745                 int mb_idx = BP_FW_MB_IDX(bp);
5746                 u16 drv_pulse;
5747                 u16 mcp_pulse;
5748
5749                 ++bp->fw_drv_pulse_wr_seq;
5750                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5751                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5752                 bnx2x_drv_pulse(bp);
5753
5754                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5755                              MCP_PULSE_SEQ_MASK);
5756                 /* The delta between driver pulse and mcp response
5757                  * should not get too big. If the MFW is more than 5 pulses
5758                  * behind, we should worry about it enough to generate an error
5759                  * log.
5760                  */
5761                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5762                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5763                                   drv_pulse, mcp_pulse);
5764         }
5765
5766         if (bp->state == BNX2X_STATE_OPEN)
5767                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5768
5769         /* sample pf vf bulletin board for new posts from pf */
5770         if (IS_VF(bp))
5771                 bnx2x_timer_sriov(bp);
5772
5773         mod_timer(&bp->timer, jiffies + bp->current_interval);
5774 }
5775
5776 /* end of Statistics */
5777
5778 /* nic init */
5779
5780 /*
5781  * nic init service functions
5782  */
5783
5784 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5785 {
5786         u32 i;
5787         if (!(len%4) && !(addr%4))
5788                 for (i = 0; i < len; i += 4)
5789                         REG_WR(bp, addr + i, fill);
5790         else
5791                 for (i = 0; i < len; i++)
5792                         REG_WR8(bp, addr + i, fill);
5793 }
5794
5795 /* helper: writes FP SP data to FW - data_size in dwords */
5796 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5797                                 int fw_sb_id,
5798                                 u32 *sb_data_p,
5799                                 u32 data_size)
5800 {
5801         int index;
5802         for (index = 0; index < data_size; index++)
5803                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5804                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5805                         sizeof(u32)*index,
5806                         *(sb_data_p + index));
5807 }
5808
5809 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5810 {
5811         u32 *sb_data_p;
5812         u32 data_size = 0;
5813         struct hc_status_block_data_e2 sb_data_e2;
5814         struct hc_status_block_data_e1x sb_data_e1x;
5815
5816         /* disable the function first */
5817         if (!CHIP_IS_E1x(bp)) {
5818                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5819                 sb_data_e2.common.state = SB_DISABLED;
5820                 sb_data_e2.common.p_func.vf_valid = false;
5821                 sb_data_p = (u32 *)&sb_data_e2;
5822                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5823         } else {
5824                 memset(&sb_data_e1x, 0,
5825                        sizeof(struct hc_status_block_data_e1x));
5826                 sb_data_e1x.common.state = SB_DISABLED;
5827                 sb_data_e1x.common.p_func.vf_valid = false;
5828                 sb_data_p = (u32 *)&sb_data_e1x;
5829                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5830         }
5831         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5832
5833         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5834                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5835                         CSTORM_STATUS_BLOCK_SIZE);
5836         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5837                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5838                         CSTORM_SYNC_BLOCK_SIZE);
5839 }
5840
5841 /* helper:  writes SP SB data to FW */
5842 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5843                 struct hc_sp_status_block_data *sp_sb_data)
5844 {
5845         int func = BP_FUNC(bp);
5846         int i;
5847         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5848                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5849                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5850                         i*sizeof(u32),
5851                         *((u32 *)sp_sb_data + i));
5852 }
5853
5854 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5855 {
5856         int func = BP_FUNC(bp);
5857         struct hc_sp_status_block_data sp_sb_data;
5858         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5859
5860         sp_sb_data.state = SB_DISABLED;
5861         sp_sb_data.p_func.vf_valid = false;
5862
5863         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5864
5865         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5866                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5867                         CSTORM_SP_STATUS_BLOCK_SIZE);
5868         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5869                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5870                         CSTORM_SP_SYNC_BLOCK_SIZE);
5871 }
5872
5873 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5874                                            int igu_sb_id, int igu_seg_id)
5875 {
5876         hc_sm->igu_sb_id = igu_sb_id;
5877         hc_sm->igu_seg_id = igu_seg_id;
5878         hc_sm->timer_value = 0xFF;
5879         hc_sm->time_to_expire = 0xFFFFFFFF;
5880 }
5881
5882 /* allocates state machine ids. */
5883 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5884 {
5885         /* zero out state machine indices */
5886         /* rx indices */
5887         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5888
5889         /* tx indices */
5890         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5891         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5892         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5893         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5894
5895         /* map indices */
5896         /* rx indices */
5897         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5898                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5899
5900         /* tx indices */
5901         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5902                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5903         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5904                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5905         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5906                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5907         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5908                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5909 }
5910
5911 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5912                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5913 {
5914         int igu_seg_id;
5915
5916         struct hc_status_block_data_e2 sb_data_e2;
5917         struct hc_status_block_data_e1x sb_data_e1x;
5918         struct hc_status_block_sm  *hc_sm_p;
5919         int data_size;
5920         u32 *sb_data_p;
5921
5922         if (CHIP_INT_MODE_IS_BC(bp))
5923                 igu_seg_id = HC_SEG_ACCESS_NORM;
5924         else
5925                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5926
5927         bnx2x_zero_fp_sb(bp, fw_sb_id);
5928
5929         if (!CHIP_IS_E1x(bp)) {
5930                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5931                 sb_data_e2.common.state = SB_ENABLED;
5932                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5933                 sb_data_e2.common.p_func.vf_id = vfid;
5934                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5935                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5936                 sb_data_e2.common.same_igu_sb_1b = true;
5937                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5938                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5939                 hc_sm_p = sb_data_e2.common.state_machine;
5940                 sb_data_p = (u32 *)&sb_data_e2;
5941                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5942                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5943         } else {
5944                 memset(&sb_data_e1x, 0,
5945                        sizeof(struct hc_status_block_data_e1x));
5946                 sb_data_e1x.common.state = SB_ENABLED;
5947                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5948                 sb_data_e1x.common.p_func.vf_id = 0xff;
5949                 sb_data_e1x.common.p_func.vf_valid = false;
5950                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5951                 sb_data_e1x.common.same_igu_sb_1b = true;
5952                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5953                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5954                 hc_sm_p = sb_data_e1x.common.state_machine;
5955                 sb_data_p = (u32 *)&sb_data_e1x;
5956                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5957                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5958         }
5959
5960         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5961                                        igu_sb_id, igu_seg_id);
5962         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5963                                        igu_sb_id, igu_seg_id);
5964
5965         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5966
5967         /* write indices to HW - PCI guarantees endianity of regpairs */
5968         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5969 }
5970
5971 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5972                                      u16 tx_usec, u16 rx_usec)
5973 {
5974         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5975                                     false, rx_usec);
5976         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5977                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5978                                        tx_usec);
5979         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5980                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5981                                        tx_usec);
5982         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5983                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5984                                        tx_usec);
5985 }
5986
5987 static void bnx2x_init_def_sb(struct bnx2x *bp)
5988 {
5989         struct host_sp_status_block *def_sb = bp->def_status_blk;
5990         dma_addr_t mapping = bp->def_status_blk_mapping;
5991         int igu_sp_sb_index;
5992         int igu_seg_id;
5993         int port = BP_PORT(bp);
5994         int func = BP_FUNC(bp);
5995         int reg_offset, reg_offset_en5;
5996         u64 section;
5997         int index;
5998         struct hc_sp_status_block_data sp_sb_data;
5999         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6000
6001         if (CHIP_INT_MODE_IS_BC(bp)) {
6002                 igu_sp_sb_index = DEF_SB_IGU_ID;
6003                 igu_seg_id = HC_SEG_ACCESS_DEF;
6004         } else {
6005                 igu_sp_sb_index = bp->igu_dsb_id;
6006                 igu_seg_id = IGU_SEG_ACCESS_DEF;
6007         }
6008
6009         /* ATTN */
6010         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6011                                             atten_status_block);
6012         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6013
6014         bp->attn_state = 0;
6015
6016         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6017                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6018         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6019                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6020         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6021                 int sindex;
6022                 /* take care of sig[0]..sig[4] */
6023                 for (sindex = 0; sindex < 4; sindex++)
6024                         bp->attn_group[index].sig[sindex] =
6025                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6026
6027                 if (!CHIP_IS_E1x(bp))
6028                         /*
6029                          * enable5 is separate from the rest of the registers,
6030                          * and therefore the address skip is 4
6031                          * and not 16 between the different groups
6032                          */
6033                         bp->attn_group[index].sig[4] = REG_RD(bp,
6034                                         reg_offset_en5 + 0x4*index);
6035                 else
6036                         bp->attn_group[index].sig[4] = 0;
6037         }
6038
6039         if (bp->common.int_block == INT_BLOCK_HC) {
6040                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6041                                      HC_REG_ATTN_MSG0_ADDR_L);
6042
6043                 REG_WR(bp, reg_offset, U64_LO(section));
6044                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6045         } else if (!CHIP_IS_E1x(bp)) {
6046                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6047                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6048         }
6049
6050         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6051                                             sp_sb);
6052
6053         bnx2x_zero_sp_sb(bp);
6054
6055         /* PCI guarantees endianity of regpairs */
6056         sp_sb_data.state                = SB_ENABLED;
6057         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6058         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6059         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6060         sp_sb_data.igu_seg_id           = igu_seg_id;
6061         sp_sb_data.p_func.pf_id         = func;
6062         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6063         sp_sb_data.p_func.vf_id         = 0xff;
6064
6065         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6066
6067         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6068 }
6069
6070 void bnx2x_update_coalesce(struct bnx2x *bp)
6071 {
6072         int i;
6073
6074         for_each_eth_queue(bp, i)
6075                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6076                                          bp->tx_ticks, bp->rx_ticks);
6077 }
6078
6079 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6080 {
6081         spin_lock_init(&bp->spq_lock);
6082         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6083
6084         bp->spq_prod_idx = 0;
6085         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6086         bp->spq_prod_bd = bp->spq;
6087         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6088 }
6089
6090 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6091 {
6092         int i;
6093         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6094                 union event_ring_elem *elem =
6095                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6096
6097                 elem->next_page.addr.hi =
6098                         cpu_to_le32(U64_HI(bp->eq_mapping +
6099                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6100                 elem->next_page.addr.lo =
6101                         cpu_to_le32(U64_LO(bp->eq_mapping +
6102                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6103         }
6104         bp->eq_cons = 0;
6105         bp->eq_prod = NUM_EQ_DESC;
6106         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6107         /* we want a warning message before it gets wrought... */
6108         atomic_set(&bp->eq_spq_left,
6109                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6110 }
6111
6112 /* called with netif_addr_lock_bh() */
6113 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6114                                unsigned long rx_mode_flags,
6115                                unsigned long rx_accept_flags,
6116                                unsigned long tx_accept_flags,
6117                                unsigned long ramrod_flags)
6118 {
6119         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6120         int rc;
6121
6122         memset(&ramrod_param, 0, sizeof(ramrod_param));
6123
6124         /* Prepare ramrod parameters */
6125         ramrod_param.cid = 0;
6126         ramrod_param.cl_id = cl_id;
6127         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6128         ramrod_param.func_id = BP_FUNC(bp);
6129
6130         ramrod_param.pstate = &bp->sp_state;
6131         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6132
6133         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6134         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6135
6136         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6137
6138         ramrod_param.ramrod_flags = ramrod_flags;
6139         ramrod_param.rx_mode_flags = rx_mode_flags;
6140
6141         ramrod_param.rx_accept_flags = rx_accept_flags;
6142         ramrod_param.tx_accept_flags = tx_accept_flags;
6143
6144         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6145         if (rc < 0) {
6146                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6147                 return rc;
6148         }
6149
6150         return 0;
6151 }
6152
6153 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6154                                    unsigned long *rx_accept_flags,
6155                                    unsigned long *tx_accept_flags)
6156 {
6157         /* Clear the flags first */
6158         *rx_accept_flags = 0;
6159         *tx_accept_flags = 0;
6160
6161         switch (rx_mode) {
6162         case BNX2X_RX_MODE_NONE:
6163                 /*
6164                  * 'drop all' supersedes any accept flags that may have been
6165                  * passed to the function.
6166                  */
6167                 break;
6168         case BNX2X_RX_MODE_NORMAL:
6169                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6170                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6171                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6172
6173                 /* internal switching mode */
6174                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6175                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6176                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6177
6178                 break;
6179         case BNX2X_RX_MODE_ALLMULTI:
6180                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6181                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6182                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6183
6184                 /* internal switching mode */
6185                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6186                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6187                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6188
6189                 break;
6190         case BNX2X_RX_MODE_PROMISC:
6191                 /* According to definition of SI mode, iface in promisc mode
6192                  * should receive matched and unmatched (in resolution of port)
6193                  * unicast packets.
6194                  */
6195                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6196                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6197                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6198                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6199
6200                 /* internal switching mode */
6201                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6202                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6203
6204                 if (IS_MF_SI(bp))
6205                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6206                 else
6207                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6208
6209                 break;
6210         default:
6211                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6212                 return -EINVAL;
6213         }
6214
6215         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6216         if (rx_mode != BNX2X_RX_MODE_NONE) {
6217                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6218                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6219         }
6220
6221         return 0;
6222 }
6223
6224 /* called with netif_addr_lock_bh() */
6225 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6226 {
6227         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6228         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6229         int rc;
6230
6231         if (!NO_FCOE(bp))
6232                 /* Configure rx_mode of FCoE Queue */
6233                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6234
6235         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6236                                      &tx_accept_flags);
6237         if (rc)
6238                 return rc;
6239
6240         __set_bit(RAMROD_RX, &ramrod_flags);
6241         __set_bit(RAMROD_TX, &ramrod_flags);
6242
6243         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6244                                    rx_accept_flags, tx_accept_flags,
6245                                    ramrod_flags);
6246 }
6247
6248 static void bnx2x_init_internal_common(struct bnx2x *bp)
6249 {
6250         int i;
6251
6252         /* Zero this manually as its initialization is
6253            currently missing in the initTool */
6254         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6255                 REG_WR(bp, BAR_USTRORM_INTMEM +
6256                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6257         if (!CHIP_IS_E1x(bp)) {
6258                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6259                         CHIP_INT_MODE_IS_BC(bp) ?
6260                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6261         }
6262 }
6263
6264 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6265 {
6266         switch (load_code) {
6267         case FW_MSG_CODE_DRV_LOAD_COMMON:
6268         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6269                 bnx2x_init_internal_common(bp);
6270                 /* no break */
6271
6272         case FW_MSG_CODE_DRV_LOAD_PORT:
6273                 /* nothing to do */
6274                 /* no break */
6275
6276         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6277                 /* internal memory per function is
6278                    initialized inside bnx2x_pf_init */
6279                 break;
6280
6281         default:
6282                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6283                 break;
6284         }
6285 }
6286
6287 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6288 {
6289         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6290 }
6291
6292 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6293 {
6294         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6295 }
6296
6297 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6298 {
6299         if (CHIP_IS_E1x(fp->bp))
6300                 return BP_L_ID(fp->bp) + fp->index;
6301         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6302                 return bnx2x_fp_igu_sb_id(fp);
6303 }
6304
6305 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6306 {
6307         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6308         u8 cos;
6309         unsigned long q_type = 0;
6310         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6311         fp->rx_queue = fp_idx;
6312         fp->cid = fp_idx;
6313         fp->cl_id = bnx2x_fp_cl_id(fp);
6314         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6315         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6316         /* qZone id equals to FW (per path) client id */
6317         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6318
6319         /* init shortcut */
6320         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6321
6322         /* Setup SB indices */
6323         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6324
6325         /* Configure Queue State object */
6326         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6327         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6328
6329         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6330
6331         /* init tx data */
6332         for_each_cos_in_tx_queue(fp, cos) {
6333                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6334                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6335                                   FP_COS_TO_TXQ(fp, cos, bp),
6336                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6337                 cids[cos] = fp->txdata_ptr[cos]->cid;
6338         }
6339
6340         /* nothing more for vf to do here */
6341         if (IS_VF(bp))
6342                 return;
6343
6344         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6345                       fp->fw_sb_id, fp->igu_sb_id);
6346         bnx2x_update_fpsb_idx(fp);
6347         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6348                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6349                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6350
6351         /**
6352          * Configure classification DBs: Always enable Tx switching
6353          */
6354         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6355
6356         DP(NETIF_MSG_IFUP,
6357            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6358            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6359            fp->igu_sb_id);
6360 }
6361
6362 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6363 {
6364         int i;
6365
6366         for (i = 1; i <= NUM_TX_RINGS; i++) {
6367                 struct eth_tx_next_bd *tx_next_bd =
6368                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6369
6370                 tx_next_bd->addr_hi =
6371                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6372                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6373                 tx_next_bd->addr_lo =
6374                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6375                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6376         }
6377
6378         *txdata->tx_cons_sb = cpu_to_le16(0);
6379
6380         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6381         txdata->tx_db.data.zero_fill1 = 0;
6382         txdata->tx_db.data.prod = 0;
6383
6384         txdata->tx_pkt_prod = 0;
6385         txdata->tx_pkt_cons = 0;
6386         txdata->tx_bd_prod = 0;
6387         txdata->tx_bd_cons = 0;
6388         txdata->tx_pkt = 0;
6389 }
6390
6391 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6392 {
6393         int i;
6394
6395         for_each_tx_queue_cnic(bp, i)
6396                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6397 }
6398
6399 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6400 {
6401         int i;
6402         u8 cos;
6403
6404         for_each_eth_queue(bp, i)
6405                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6406                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6407 }
6408
6409 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6410 {
6411         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6412         unsigned long q_type = 0;
6413
6414         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6415         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6416                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6417         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6418         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6419         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6420         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6421         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6422                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6423                           fp);
6424
6425         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6426
6427         /* qZone id equals to FW (per path) client id */
6428         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6429         /* init shortcut */
6430         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6431                 bnx2x_rx_ustorm_prods_offset(fp);
6432
6433         /* Configure Queue State object */
6434         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6435         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6436
6437         /* No multi-CoS for FCoE L2 client */
6438         BUG_ON(fp->max_cos != 1);
6439
6440         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6441                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6442                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6443
6444         DP(NETIF_MSG_IFUP,
6445            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6446            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6447            fp->igu_sb_id);
6448 }
6449
6450 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6451 {
6452         if (!NO_FCOE(bp))
6453                 bnx2x_init_fcoe_fp(bp);
6454
6455         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6456                       BNX2X_VF_ID_INVALID, false,
6457                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6458
6459         /* ensure status block indices were read */
6460         rmb();
6461         bnx2x_init_rx_rings_cnic(bp);
6462         bnx2x_init_tx_rings_cnic(bp);
6463
6464         /* flush all */
6465         mb();
6466         mmiowb();
6467 }
6468
6469 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6470 {
6471         int i;
6472
6473         /* Setup NIC internals and enable interrupts */
6474         for_each_eth_queue(bp, i)
6475                 bnx2x_init_eth_fp(bp, i);
6476
6477         /* ensure status block indices were read */
6478         rmb();
6479         bnx2x_init_rx_rings(bp);
6480         bnx2x_init_tx_rings(bp);
6481
6482         if (IS_PF(bp)) {
6483                 /* Initialize MOD_ABS interrupts */
6484                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6485                                        bp->common.shmem_base,
6486                                        bp->common.shmem2_base, BP_PORT(bp));
6487
6488                 /* initialize the default status block and sp ring */
6489                 bnx2x_init_def_sb(bp);
6490                 bnx2x_update_dsb_idx(bp);
6491                 bnx2x_init_sp_ring(bp);
6492         } else {
6493                 bnx2x_memset_stats(bp);
6494         }
6495 }
6496
6497 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6498 {
6499         bnx2x_init_eq_ring(bp);
6500         bnx2x_init_internal(bp, load_code);
6501         bnx2x_pf_init(bp);
6502         bnx2x_stats_init(bp);
6503
6504         /* flush all before enabling interrupts */
6505         mb();
6506         mmiowb();
6507
6508         bnx2x_int_enable(bp);
6509
6510         /* Check for SPIO5 */
6511         bnx2x_attn_int_deasserted0(bp,
6512                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6513                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6514 }
6515
6516 /* gzip service functions */
6517 static int bnx2x_gunzip_init(struct bnx2x *bp)
6518 {
6519         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6520                                             &bp->gunzip_mapping, GFP_KERNEL);
6521         if (bp->gunzip_buf  == NULL)
6522                 goto gunzip_nomem1;
6523
6524         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6525         if (bp->strm  == NULL)
6526                 goto gunzip_nomem2;
6527
6528         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6529         if (bp->strm->workspace == NULL)
6530                 goto gunzip_nomem3;
6531
6532         return 0;
6533
6534 gunzip_nomem3:
6535         kfree(bp->strm);
6536         bp->strm = NULL;
6537
6538 gunzip_nomem2:
6539         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6540                           bp->gunzip_mapping);
6541         bp->gunzip_buf = NULL;
6542
6543 gunzip_nomem1:
6544         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6545         return -ENOMEM;
6546 }
6547
6548 static void bnx2x_gunzip_end(struct bnx2x *bp)
6549 {
6550         if (bp->strm) {
6551                 vfree(bp->strm->workspace);
6552                 kfree(bp->strm);
6553                 bp->strm = NULL;
6554         }
6555
6556         if (bp->gunzip_buf) {
6557                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6558                                   bp->gunzip_mapping);
6559                 bp->gunzip_buf = NULL;
6560         }
6561 }
6562
6563 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6564 {
6565         int n, rc;
6566
6567         /* check gzip header */
6568         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6569                 BNX2X_ERR("Bad gzip header\n");
6570                 return -EINVAL;
6571         }
6572
6573         n = 10;
6574
6575 #define FNAME                           0x8
6576
6577         if (zbuf[3] & FNAME)
6578                 while ((zbuf[n++] != 0) && (n < len));
6579
6580         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6581         bp->strm->avail_in = len - n;
6582         bp->strm->next_out = bp->gunzip_buf;
6583         bp->strm->avail_out = FW_BUF_SIZE;
6584
6585         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6586         if (rc != Z_OK)
6587                 return rc;
6588
6589         rc = zlib_inflate(bp->strm, Z_FINISH);
6590         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6591                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6592                            bp->strm->msg);
6593
6594         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6595         if (bp->gunzip_outlen & 0x3)
6596                 netdev_err(bp->dev,
6597                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6598                                 bp->gunzip_outlen);
6599         bp->gunzip_outlen >>= 2;
6600
6601         zlib_inflateEnd(bp->strm);
6602
6603         if (rc == Z_STREAM_END)
6604                 return 0;
6605
6606         return rc;
6607 }
6608
6609 /* nic load/unload */
6610
6611 /*
6612  * General service functions
6613  */
6614
6615 /* send a NIG loopback debug packet */
6616 static void bnx2x_lb_pckt(struct bnx2x *bp)
6617 {
6618         u32 wb_write[3];
6619
6620         /* Ethernet source and destination addresses */
6621         wb_write[0] = 0x55555555;
6622         wb_write[1] = 0x55555555;
6623         wb_write[2] = 0x20;             /* SOP */
6624         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6625
6626         /* NON-IP protocol */
6627         wb_write[0] = 0x09000000;
6628         wb_write[1] = 0x55555555;
6629         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6630         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6631 }
6632
6633 /* some of the internal memories
6634  * are not directly readable from the driver
6635  * to test them we send debug packets
6636  */
6637 static int bnx2x_int_mem_test(struct bnx2x *bp)
6638 {
6639         int factor;
6640         int count, i;
6641         u32 val = 0;
6642
6643         if (CHIP_REV_IS_FPGA(bp))
6644                 factor = 120;
6645         else if (CHIP_REV_IS_EMUL(bp))
6646                 factor = 200;
6647         else
6648                 factor = 1;
6649
6650         /* Disable inputs of parser neighbor blocks */
6651         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6652         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6653         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6654         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6655
6656         /*  Write 0 to parser credits for CFC search request */
6657         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6658
6659         /* send Ethernet packet */
6660         bnx2x_lb_pckt(bp);
6661
6662         /* TODO do i reset NIG statistic? */
6663         /* Wait until NIG register shows 1 packet of size 0x10 */
6664         count = 1000 * factor;
6665         while (count) {
6666
6667                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6668                 val = *bnx2x_sp(bp, wb_data[0]);
6669                 if (val == 0x10)
6670                         break;
6671
6672                 usleep_range(10000, 20000);
6673                 count--;
6674         }
6675         if (val != 0x10) {
6676                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6677                 return -1;
6678         }
6679
6680         /* Wait until PRS register shows 1 packet */
6681         count = 1000 * factor;
6682         while (count) {
6683                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6684                 if (val == 1)
6685                         break;
6686
6687                 usleep_range(10000, 20000);
6688                 count--;
6689         }
6690         if (val != 0x1) {
6691                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6692                 return -2;
6693         }
6694
6695         /* Reset and init BRB, PRS */
6696         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6697         msleep(50);
6698         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6699         msleep(50);
6700         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6701         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6702
6703         DP(NETIF_MSG_HW, "part2\n");
6704
6705         /* Disable inputs of parser neighbor blocks */
6706         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6707         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6708         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6709         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6710
6711         /* Write 0 to parser credits for CFC search request */
6712         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6713
6714         /* send 10 Ethernet packets */
6715         for (i = 0; i < 10; i++)
6716                 bnx2x_lb_pckt(bp);
6717
6718         /* Wait until NIG register shows 10 + 1
6719            packets of size 11*0x10 = 0xb0 */
6720         count = 1000 * factor;
6721         while (count) {
6722
6723                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6724                 val = *bnx2x_sp(bp, wb_data[0]);
6725                 if (val == 0xb0)
6726                         break;
6727
6728                 usleep_range(10000, 20000);
6729                 count--;
6730         }
6731         if (val != 0xb0) {
6732                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6733                 return -3;
6734         }
6735
6736         /* Wait until PRS register shows 2 packets */
6737         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6738         if (val != 2)
6739                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6740
6741         /* Write 1 to parser credits for CFC search request */
6742         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6743
6744         /* Wait until PRS register shows 3 packets */
6745         msleep(10 * factor);
6746         /* Wait until NIG register shows 1 packet of size 0x10 */
6747         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6748         if (val != 3)
6749                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6750
6751         /* clear NIG EOP FIFO */
6752         for (i = 0; i < 11; i++)
6753                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6754         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6755         if (val != 1) {
6756                 BNX2X_ERR("clear of NIG failed\n");
6757                 return -4;
6758         }
6759
6760         /* Reset and init BRB, PRS, NIG */
6761         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6762         msleep(50);
6763         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6764         msleep(50);
6765         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6766         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6767         if (!CNIC_SUPPORT(bp))
6768                 /* set NIC mode */
6769                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6770
6771         /* Enable inputs of parser neighbor blocks */
6772         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6773         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6774         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6775         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6776
6777         DP(NETIF_MSG_HW, "done\n");
6778
6779         return 0; /* OK */
6780 }
6781
6782 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6783 {
6784         u32 val;
6785
6786         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6787         if (!CHIP_IS_E1x(bp))
6788                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6789         else
6790                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6791         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6792         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6793         /*
6794          * mask read length error interrupts in brb for parser
6795          * (parsing unit and 'checksum and crc' unit)
6796          * these errors are legal (PU reads fixed length and CAC can cause
6797          * read length error on truncated packets)
6798          */
6799         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6800         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6801         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6802         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6803         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6804         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6805 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6806 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6807         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6808         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6809         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6810 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6811 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6812         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6813         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6814         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6815         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6816 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6817 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6818
6819         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6820                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6821                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6822         if (!CHIP_IS_E1x(bp))
6823                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6824                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6825         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6826
6827         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6828         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6829         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6830 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6831
6832         if (!CHIP_IS_E1x(bp))
6833                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6834                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6835
6836         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6837         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6838 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6839         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6840 }
6841
6842 static void bnx2x_reset_common(struct bnx2x *bp)
6843 {
6844         u32 val = 0x1400;
6845
6846         /* reset_common */
6847         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6848                0xd3ffff7f);
6849
6850         if (CHIP_IS_E3(bp)) {
6851                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6852                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6853         }
6854
6855         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6856 }
6857
6858 static void bnx2x_setup_dmae(struct bnx2x *bp)
6859 {
6860         bp->dmae_ready = 0;
6861         spin_lock_init(&bp->dmae_lock);
6862 }
6863
6864 static void bnx2x_init_pxp(struct bnx2x *bp)
6865 {
6866         u16 devctl;
6867         int r_order, w_order;
6868
6869         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6870         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6871         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6872         if (bp->mrrs == -1)
6873                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6874         else {
6875                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6876                 r_order = bp->mrrs;
6877         }
6878
6879         bnx2x_init_pxp_arb(bp, r_order, w_order);
6880 }
6881
6882 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6883 {
6884         int is_required;
6885         u32 val;
6886         int port;
6887
6888         if (BP_NOMCP(bp))
6889                 return;
6890
6891         is_required = 0;
6892         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6893               SHARED_HW_CFG_FAN_FAILURE_MASK;
6894
6895         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6896                 is_required = 1;
6897
6898         /*
6899          * The fan failure mechanism is usually related to the PHY type since
6900          * the power consumption of the board is affected by the PHY. Currently,
6901          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6902          */
6903         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6904                 for (port = PORT_0; port < PORT_MAX; port++) {
6905                         is_required |=
6906                                 bnx2x_fan_failure_det_req(
6907                                         bp,
6908                                         bp->common.shmem_base,
6909                                         bp->common.shmem2_base,
6910                                         port);
6911                 }
6912
6913         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6914
6915         if (is_required == 0)
6916                 return;
6917
6918         /* Fan failure is indicated by SPIO 5 */
6919         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6920
6921         /* set to active low mode */
6922         val = REG_RD(bp, MISC_REG_SPIO_INT);
6923         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6924         REG_WR(bp, MISC_REG_SPIO_INT, val);
6925
6926         /* enable interrupt to signal the IGU */
6927         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6928         val |= MISC_SPIO_SPIO5;
6929         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6930 }
6931
6932 void bnx2x_pf_disable(struct bnx2x *bp)
6933 {
6934         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6935         val &= ~IGU_PF_CONF_FUNC_EN;
6936
6937         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6938         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6939         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6940 }
6941
6942 static void bnx2x__common_init_phy(struct bnx2x *bp)
6943 {
6944         u32 shmem_base[2], shmem2_base[2];
6945         /* Avoid common init in case MFW supports LFA */
6946         if (SHMEM2_RD(bp, size) >
6947             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6948                 return;
6949         shmem_base[0] =  bp->common.shmem_base;
6950         shmem2_base[0] = bp->common.shmem2_base;
6951         if (!CHIP_IS_E1x(bp)) {
6952                 shmem_base[1] =
6953                         SHMEM2_RD(bp, other_shmem_base_addr);
6954                 shmem2_base[1] =
6955                         SHMEM2_RD(bp, other_shmem2_base_addr);
6956         }
6957         bnx2x_acquire_phy_lock(bp);
6958         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6959                               bp->common.chip_id);
6960         bnx2x_release_phy_lock(bp);
6961 }
6962
6963 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6964 {
6965         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6966         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6967         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6968         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6969         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6970
6971         /* make sure this value is 0 */
6972         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6973
6974         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
6975         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
6976         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
6977         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
6978 }
6979
6980 static void bnx2x_set_endianity(struct bnx2x *bp)
6981 {
6982 #ifdef __BIG_ENDIAN
6983         bnx2x_config_endianity(bp, 1);
6984 #else
6985         bnx2x_config_endianity(bp, 0);
6986 #endif
6987 }
6988
6989 static void bnx2x_reset_endianity(struct bnx2x *bp)
6990 {
6991         bnx2x_config_endianity(bp, 0);
6992 }
6993
6994 /**
6995  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6996  *
6997  * @bp:         driver handle
6998  */
6999 static int bnx2x_init_hw_common(struct bnx2x *bp)
7000 {
7001         u32 val;
7002
7003         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
7004
7005         /*
7006          * take the RESET lock to protect undi_unload flow from accessing
7007          * registers while we're resetting the chip
7008          */
7009         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7010
7011         bnx2x_reset_common(bp);
7012         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7013
7014         val = 0xfffc;
7015         if (CHIP_IS_E3(bp)) {
7016                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7017                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7018         }
7019         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7020
7021         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7022
7023         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7024
7025         if (!CHIP_IS_E1x(bp)) {
7026                 u8 abs_func_id;
7027
7028                 /**
7029                  * 4-port mode or 2-port mode we need to turn of master-enable
7030                  * for everyone, after that, turn it back on for self.
7031                  * so, we disregard multi-function or not, and always disable
7032                  * for all functions on the given path, this means 0,2,4,6 for
7033                  * path 0 and 1,3,5,7 for path 1
7034                  */
7035                 for (abs_func_id = BP_PATH(bp);
7036                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7037                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7038                                 REG_WR(bp,
7039                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7040                                     1);
7041                                 continue;
7042                         }
7043
7044                         bnx2x_pretend_func(bp, abs_func_id);
7045                         /* clear pf enable */
7046                         bnx2x_pf_disable(bp);
7047                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7048                 }
7049         }
7050
7051         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7052         if (CHIP_IS_E1(bp)) {
7053                 /* enable HW interrupt from PXP on USDM overflow
7054                    bit 16 on INT_MASK_0 */
7055                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7056         }
7057
7058         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7059         bnx2x_init_pxp(bp);
7060         bnx2x_set_endianity(bp);
7061         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7062
7063         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7064                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7065
7066         /* let the HW do it's magic ... */
7067         msleep(100);
7068         /* finish PXP init */
7069         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7070         if (val != 1) {
7071                 BNX2X_ERR("PXP2 CFG failed\n");
7072                 return -EBUSY;
7073         }
7074         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7075         if (val != 1) {
7076                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7077                 return -EBUSY;
7078         }
7079
7080         /* Timers bug workaround E2 only. We need to set the entire ILT to
7081          * have entries with value "0" and valid bit on.
7082          * This needs to be done by the first PF that is loaded in a path
7083          * (i.e. common phase)
7084          */
7085         if (!CHIP_IS_E1x(bp)) {
7086 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7087  * (i.e. vnic3) to start even if it is marked as "scan-off".
7088  * This occurs when a different function (func2,3) is being marked
7089  * as "scan-off". Real-life scenario for example: if a driver is being
7090  * load-unloaded while func6,7 are down. This will cause the timer to access
7091  * the ilt, translate to a logical address and send a request to read/write.
7092  * Since the ilt for the function that is down is not valid, this will cause
7093  * a translation error which is unrecoverable.
7094  * The Workaround is intended to make sure that when this happens nothing fatal
7095  * will occur. The workaround:
7096  *      1.  First PF driver which loads on a path will:
7097  *              a.  After taking the chip out of reset, by using pretend,
7098  *                  it will write "0" to the following registers of
7099  *                  the other vnics.
7100  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7101  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7102  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7103  *                  And for itself it will write '1' to
7104  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7105  *                  dmae-operations (writing to pram for example.)
7106  *                  note: can be done for only function 6,7 but cleaner this
7107  *                        way.
7108  *              b.  Write zero+valid to the entire ILT.
7109  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7110  *                  VNIC3 (of that port). The range allocated will be the
7111  *                  entire ILT. This is needed to prevent  ILT range error.
7112  *      2.  Any PF driver load flow:
7113  *              a.  ILT update with the physical addresses of the allocated
7114  *                  logical pages.
7115  *              b.  Wait 20msec. - note that this timeout is needed to make
7116  *                  sure there are no requests in one of the PXP internal
7117  *                  queues with "old" ILT addresses.
7118  *              c.  PF enable in the PGLC.
7119  *              d.  Clear the was_error of the PF in the PGLC. (could have
7120  *                  occurred while driver was down)
7121  *              e.  PF enable in the CFC (WEAK + STRONG)
7122  *              f.  Timers scan enable
7123  *      3.  PF driver unload flow:
7124  *              a.  Clear the Timers scan_en.
7125  *              b.  Polling for scan_on=0 for that PF.
7126  *              c.  Clear the PF enable bit in the PXP.
7127  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7128  *              e.  Write zero+valid to all ILT entries (The valid bit must
7129  *                  stay set)
7130  *              f.  If this is VNIC 3 of a port then also init
7131  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7132  *                  to the last entry in the ILT.
7133  *
7134  *      Notes:
7135  *      Currently the PF error in the PGLC is non recoverable.
7136  *      In the future the there will be a recovery routine for this error.
7137  *      Currently attention is masked.
7138  *      Having an MCP lock on the load/unload process does not guarantee that
7139  *      there is no Timer disable during Func6/7 enable. This is because the
7140  *      Timers scan is currently being cleared by the MCP on FLR.
7141  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7142  *      there is error before clearing it. But the flow above is simpler and
7143  *      more general.
7144  *      All ILT entries are written by zero+valid and not just PF6/7
7145  *      ILT entries since in the future the ILT entries allocation for
7146  *      PF-s might be dynamic.
7147  */
7148                 struct ilt_client_info ilt_cli;
7149                 struct bnx2x_ilt ilt;
7150                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7151                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7152
7153                 /* initialize dummy TM client */
7154                 ilt_cli.start = 0;
7155                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7156                 ilt_cli.client_num = ILT_CLIENT_TM;
7157
7158                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7159                  * Step 2: set the timers first/last ilt entry to point
7160                  * to the entire range to prevent ILT range error for 3rd/4th
7161                  * vnic (this code assumes existence of the vnic)
7162                  *
7163                  * both steps performed by call to bnx2x_ilt_client_init_op()
7164                  * with dummy TM client
7165                  *
7166                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7167                  * and his brother are split registers
7168                  */
7169                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7170                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7171                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7172
7173                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7174                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7175                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7176         }
7177
7178         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7179         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7180
7181         if (!CHIP_IS_E1x(bp)) {
7182                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7183                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7184                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7185
7186                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7187
7188                 /* let the HW do it's magic ... */
7189                 do {
7190                         msleep(200);
7191                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7192                 } while (factor-- && (val != 1));
7193
7194                 if (val != 1) {
7195                         BNX2X_ERR("ATC_INIT failed\n");
7196                         return -EBUSY;
7197                 }
7198         }
7199
7200         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7201
7202         bnx2x_iov_init_dmae(bp);
7203
7204         /* clean the DMAE memory */
7205         bp->dmae_ready = 1;
7206         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7207
7208         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7209
7210         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7211
7212         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7213
7214         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7215
7216         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7217         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7218         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7219         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7220
7221         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7222
7223         /* QM queues pointers table */
7224         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7225
7226         /* soft reset pulse */
7227         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7228         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7229
7230         if (CNIC_SUPPORT(bp))
7231                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7232
7233         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7234
7235         if (!CHIP_REV_IS_SLOW(bp))
7236                 /* enable hw interrupt from doorbell Q */
7237                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7238
7239         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7240
7241         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7242         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7243
7244         if (!CHIP_IS_E1(bp))
7245                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7246
7247         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7248                 if (IS_MF_AFEX(bp)) {
7249                         /* configure that VNTag and VLAN headers must be
7250                          * received in afex mode
7251                          */
7252                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7253                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7254                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7255                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7256                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7257                 } else {
7258                         /* Bit-map indicating which L2 hdrs may appear
7259                          * after the basic Ethernet header
7260                          */
7261                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7262                                bp->path_has_ovlan ? 7 : 6);
7263                 }
7264         }
7265
7266         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7267         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7268         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7269         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7270
7271         if (!CHIP_IS_E1x(bp)) {
7272                 /* reset VFC memories */
7273                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7274                            VFC_MEMORIES_RST_REG_CAM_RST |
7275                            VFC_MEMORIES_RST_REG_RAM_RST);
7276                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7277                            VFC_MEMORIES_RST_REG_CAM_RST |
7278                            VFC_MEMORIES_RST_REG_RAM_RST);
7279
7280                 msleep(20);
7281         }
7282
7283         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7284         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7285         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7286         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7287
7288         /* sync semi rtc */
7289         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7290                0x80000000);
7291         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7292                0x80000000);
7293
7294         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7295         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7296         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7297
7298         if (!CHIP_IS_E1x(bp)) {
7299                 if (IS_MF_AFEX(bp)) {
7300                         /* configure that VNTag and VLAN headers must be
7301                          * sent in afex mode
7302                          */
7303                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7304                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7305                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7306                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7307                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7308                 } else {
7309                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7310                                bp->path_has_ovlan ? 7 : 6);
7311                 }
7312         }
7313
7314         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7315
7316         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7317
7318         if (CNIC_SUPPORT(bp)) {
7319                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7320                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7321                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7322                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7323                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7324                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7325                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7326                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7327                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7328                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7329         }
7330         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7331
7332         if (sizeof(union cdu_context) != 1024)
7333                 /* we currently assume that a context is 1024 bytes */
7334                 dev_alert(&bp->pdev->dev,
7335                           "please adjust the size of cdu_context(%ld)\n",
7336                           (long)sizeof(union cdu_context));
7337
7338         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7339         val = (4 << 24) + (0 << 12) + 1024;
7340         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7341
7342         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7343         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7344         /* enable context validation interrupt from CFC */
7345         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7346
7347         /* set the thresholds to prevent CFC/CDU race */
7348         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7349
7350         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7351
7352         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7353                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7354
7355         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7356         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7357
7358         /* Reset PCIE errors for debug */
7359         REG_WR(bp, 0x2814, 0xffffffff);
7360         REG_WR(bp, 0x3820, 0xffffffff);
7361
7362         if (!CHIP_IS_E1x(bp)) {
7363                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7364                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7365                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7366                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7367                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7368                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7369                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7370                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7371                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7372                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7373                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7374         }
7375
7376         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7377         if (!CHIP_IS_E1(bp)) {
7378                 /* in E3 this done in per-port section */
7379                 if (!CHIP_IS_E3(bp))
7380                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7381         }
7382         if (CHIP_IS_E1H(bp))
7383                 /* not applicable for E2 (and above ...) */
7384                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7385
7386         if (CHIP_REV_IS_SLOW(bp))
7387                 msleep(200);
7388
7389         /* finish CFC init */
7390         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7391         if (val != 1) {
7392                 BNX2X_ERR("CFC LL_INIT failed\n");
7393                 return -EBUSY;
7394         }
7395         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7396         if (val != 1) {
7397                 BNX2X_ERR("CFC AC_INIT failed\n");
7398                 return -EBUSY;
7399         }
7400         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7401         if (val != 1) {
7402                 BNX2X_ERR("CFC CAM_INIT failed\n");
7403                 return -EBUSY;
7404         }
7405         REG_WR(bp, CFC_REG_DEBUG0, 0);
7406
7407         if (CHIP_IS_E1(bp)) {
7408                 /* read NIG statistic
7409                    to see if this is our first up since powerup */
7410                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7411                 val = *bnx2x_sp(bp, wb_data[0]);
7412
7413                 /* do internal memory self test */
7414                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7415                         BNX2X_ERR("internal mem self test failed\n");
7416                         return -EBUSY;
7417                 }
7418         }
7419
7420         bnx2x_setup_fan_failure_detection(bp);
7421
7422         /* clear PXP2 attentions */
7423         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7424
7425         bnx2x_enable_blocks_attention(bp);
7426         bnx2x_enable_blocks_parity(bp);
7427
7428         if (!BP_NOMCP(bp)) {
7429                 if (CHIP_IS_E1x(bp))
7430                         bnx2x__common_init_phy(bp);
7431         } else
7432                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7433
7434         return 0;
7435 }
7436
7437 /**
7438  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7439  *
7440  * @bp:         driver handle
7441  */
7442 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7443 {
7444         int rc = bnx2x_init_hw_common(bp);
7445
7446         if (rc)
7447                 return rc;
7448
7449         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7450         if (!BP_NOMCP(bp))
7451                 bnx2x__common_init_phy(bp);
7452
7453         return 0;
7454 }
7455
7456 static int bnx2x_init_hw_port(struct bnx2x *bp)
7457 {
7458         int port = BP_PORT(bp);
7459         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7460         u32 low, high;
7461         u32 val, reg;
7462
7463         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7464
7465         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7466
7467         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7468         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7469         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7470
7471         /* Timers bug workaround: disables the pf_master bit in pglue at
7472          * common phase, we need to enable it here before any dmae access are
7473          * attempted. Therefore we manually added the enable-master to the
7474          * port phase (it also happens in the function phase)
7475          */
7476         if (!CHIP_IS_E1x(bp))
7477                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7478
7479         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7480         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7481         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7482         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7483
7484         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7485         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7486         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7487         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7488
7489         /* QM cid (connection) count */
7490         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7491
7492         if (CNIC_SUPPORT(bp)) {
7493                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7494                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7495                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7496         }
7497
7498         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7499
7500         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7501
7502         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7503
7504                 if (IS_MF(bp))
7505                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7506                 else if (bp->dev->mtu > 4096) {
7507                         if (bp->flags & ONE_PORT_FLAG)
7508                                 low = 160;
7509                         else {
7510                                 val = bp->dev->mtu;
7511                                 /* (24*1024 + val*4)/256 */
7512                                 low = 96 + (val/64) +
7513                                                 ((val % 64) ? 1 : 0);
7514                         }
7515                 } else
7516                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7517                 high = low + 56;        /* 14*1024/256 */
7518                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7519                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7520         }
7521
7522         if (CHIP_MODE_IS_4_PORT(bp))
7523                 REG_WR(bp, (BP_PORT(bp) ?
7524                             BRB1_REG_MAC_GUARANTIED_1 :
7525                             BRB1_REG_MAC_GUARANTIED_0), 40);
7526
7527         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7528         if (CHIP_IS_E3B0(bp)) {
7529                 if (IS_MF_AFEX(bp)) {
7530                         /* configure headers for AFEX mode */
7531                         REG_WR(bp, BP_PORT(bp) ?
7532                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7533                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7534                         REG_WR(bp, BP_PORT(bp) ?
7535                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7536                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7537                         REG_WR(bp, BP_PORT(bp) ?
7538                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7539                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7540                 } else {
7541                         /* Ovlan exists only if we are in multi-function +
7542                          * switch-dependent mode, in switch-independent there
7543                          * is no ovlan headers
7544                          */
7545                         REG_WR(bp, BP_PORT(bp) ?
7546                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7547                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7548                                (bp->path_has_ovlan ? 7 : 6));
7549                 }
7550         }
7551
7552         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7553         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7554         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7555         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7556
7557         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7558         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7559         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7560         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7561
7562         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7563         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7564
7565         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7566
7567         if (CHIP_IS_E1x(bp)) {
7568                 /* configure PBF to work without PAUSE mtu 9000 */
7569                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7570
7571                 /* update threshold */
7572                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7573                 /* update init credit */
7574                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7575
7576                 /* probe changes */
7577                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7578                 udelay(50);
7579                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7580         }
7581
7582         if (CNIC_SUPPORT(bp))
7583                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7584
7585         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7586         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7587
7588         if (CHIP_IS_E1(bp)) {
7589                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7590                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7591         }
7592         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7593
7594         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7595
7596         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7597         /* init aeu_mask_attn_func_0/1:
7598          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7599          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7600          *             bits 4-7 are used for "per vn group attention" */
7601         val = IS_MF(bp) ? 0xF7 : 0x7;
7602         /* Enable DCBX attention for all but E1 */
7603         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7604         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7605
7606         /* SCPAD_PARITY should NOT trigger close the gates */
7607         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7608         REG_WR(bp, reg,
7609                REG_RD(bp, reg) &
7610                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7611
7612         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7613         REG_WR(bp, reg,
7614                REG_RD(bp, reg) &
7615                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7616
7617         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7618
7619         if (!CHIP_IS_E1x(bp)) {
7620                 /* Bit-map indicating which L2 hdrs may appear after the
7621                  * basic Ethernet header
7622                  */
7623                 if (IS_MF_AFEX(bp))
7624                         REG_WR(bp, BP_PORT(bp) ?
7625                                NIG_REG_P1_HDRS_AFTER_BASIC :
7626                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7627                 else
7628                         REG_WR(bp, BP_PORT(bp) ?
7629                                NIG_REG_P1_HDRS_AFTER_BASIC :
7630                                NIG_REG_P0_HDRS_AFTER_BASIC,
7631                                IS_MF_SD(bp) ? 7 : 6);
7632
7633                 if (CHIP_IS_E3(bp))
7634                         REG_WR(bp, BP_PORT(bp) ?
7635                                    NIG_REG_LLH1_MF_MODE :
7636                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7637         }
7638         if (!CHIP_IS_E3(bp))
7639                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7640
7641         if (!CHIP_IS_E1(bp)) {
7642                 /* 0x2 disable mf_ov, 0x1 enable */
7643                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7644                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7645
7646                 if (!CHIP_IS_E1x(bp)) {
7647                         val = 0;
7648                         switch (bp->mf_mode) {
7649                         case MULTI_FUNCTION_SD:
7650                                 val = 1;
7651                                 break;
7652                         case MULTI_FUNCTION_SI:
7653                         case MULTI_FUNCTION_AFEX:
7654                                 val = 2;
7655                                 break;
7656                         }
7657
7658                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7659                                                   NIG_REG_LLH0_CLS_TYPE), val);
7660                 }
7661                 {
7662                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7663                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7664                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7665                 }
7666         }
7667
7668         /* If SPIO5 is set to generate interrupts, enable it for this port */
7669         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7670         if (val & MISC_SPIO_SPIO5) {
7671                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7672                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7673                 val = REG_RD(bp, reg_addr);
7674                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7675                 REG_WR(bp, reg_addr, val);
7676         }
7677
7678         return 0;
7679 }
7680
7681 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7682 {
7683         int reg;
7684         u32 wb_write[2];
7685
7686         if (CHIP_IS_E1(bp))
7687                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7688         else
7689                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7690
7691         wb_write[0] = ONCHIP_ADDR1(addr);
7692         wb_write[1] = ONCHIP_ADDR2(addr);
7693         REG_WR_DMAE(bp, reg, wb_write, 2);
7694 }
7695
7696 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7697 {
7698         u32 data, ctl, cnt = 100;
7699         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7700         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7701         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7702         u32 sb_bit =  1 << (idu_sb_id%32);
7703         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7704         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7705
7706         /* Not supported in BC mode */
7707         if (CHIP_INT_MODE_IS_BC(bp))
7708                 return;
7709
7710         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7711                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7712                 IGU_REGULAR_CLEANUP_SET                         |
7713                 IGU_REGULAR_BCLEANUP;
7714
7715         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7716               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7717               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7718
7719         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7720                          data, igu_addr_data);
7721         REG_WR(bp, igu_addr_data, data);
7722         mmiowb();
7723         barrier();
7724         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7725                           ctl, igu_addr_ctl);
7726         REG_WR(bp, igu_addr_ctl, ctl);
7727         mmiowb();
7728         barrier();
7729
7730         /* wait for clean up to finish */
7731         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7732                 msleep(20);
7733
7734         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7735                 DP(NETIF_MSG_HW,
7736                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7737                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7738         }
7739 }
7740
7741 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7742 {
7743         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7744 }
7745
7746 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7747 {
7748         u32 i, base = FUNC_ILT_BASE(func);
7749         for (i = base; i < base + ILT_PER_FUNC; i++)
7750                 bnx2x_ilt_wr(bp, i, 0);
7751 }
7752
7753 static void bnx2x_init_searcher(struct bnx2x *bp)
7754 {
7755         int port = BP_PORT(bp);
7756         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7757         /* T1 hash bits value determines the T1 number of entries */
7758         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7759 }
7760
7761 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7762 {
7763         int rc;
7764         struct bnx2x_func_state_params func_params = {NULL};
7765         struct bnx2x_func_switch_update_params *switch_update_params =
7766                 &func_params.params.switch_update;
7767
7768         /* Prepare parameters for function state transitions */
7769         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7770         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7771
7772         func_params.f_obj = &bp->func_obj;
7773         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7774
7775         /* Function parameters */
7776         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7777                   &switch_update_params->changes);
7778         if (suspend)
7779                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7780                           &switch_update_params->changes);
7781
7782         rc = bnx2x_func_state_change(bp, &func_params);
7783
7784         return rc;
7785 }
7786
7787 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7788 {
7789         int rc, i, port = BP_PORT(bp);
7790         int vlan_en = 0, mac_en[NUM_MACS];
7791
7792         /* Close input from network */
7793         if (bp->mf_mode == SINGLE_FUNCTION) {
7794                 bnx2x_set_rx_filter(&bp->link_params, 0);
7795         } else {
7796                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7797                                    NIG_REG_LLH0_FUNC_EN);
7798                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7799                           NIG_REG_LLH0_FUNC_EN, 0);
7800                 for (i = 0; i < NUM_MACS; i++) {
7801                         mac_en[i] = REG_RD(bp, port ?
7802                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7803                                               4 * i) :
7804                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7805                                               4 * i));
7806                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7807                                               4 * i) :
7808                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7809                 }
7810         }
7811
7812         /* Close BMC to host */
7813         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7814                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7815
7816         /* Suspend Tx switching to the PF. Completion of this ramrod
7817          * further guarantees that all the packets of that PF / child
7818          * VFs in BRB were processed by the Parser, so it is safe to
7819          * change the NIC_MODE register.
7820          */
7821         rc = bnx2x_func_switch_update(bp, 1);
7822         if (rc) {
7823                 BNX2X_ERR("Can't suspend tx-switching!\n");
7824                 return rc;
7825         }
7826
7827         /* Change NIC_MODE register */
7828         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7829
7830         /* Open input from network */
7831         if (bp->mf_mode == SINGLE_FUNCTION) {
7832                 bnx2x_set_rx_filter(&bp->link_params, 1);
7833         } else {
7834                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7835                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7836                 for (i = 0; i < NUM_MACS; i++) {
7837                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7838                                               4 * i) :
7839                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7840                                   mac_en[i]);
7841                 }
7842         }
7843
7844         /* Enable BMC to host */
7845         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7846                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7847
7848         /* Resume Tx switching to the PF */
7849         rc = bnx2x_func_switch_update(bp, 0);
7850         if (rc) {
7851                 BNX2X_ERR("Can't resume tx-switching!\n");
7852                 return rc;
7853         }
7854
7855         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7856         return 0;
7857 }
7858
7859 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7860 {
7861         int rc;
7862
7863         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7864
7865         if (CONFIGURE_NIC_MODE(bp)) {
7866                 /* Configure searcher as part of function hw init */
7867                 bnx2x_init_searcher(bp);
7868
7869                 /* Reset NIC mode */
7870                 rc = bnx2x_reset_nic_mode(bp);
7871                 if (rc)
7872                         BNX2X_ERR("Can't change NIC mode!\n");
7873                 return rc;
7874         }
7875
7876         return 0;
7877 }
7878
7879 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7880  * and boot began, or when kdump kernel was loaded. Either case would invalidate
7881  * the addresses of the transaction, resulting in was-error bit set in the pci
7882  * causing all hw-to-host pcie transactions to timeout. If this happened we want
7883  * to clear the interrupt which detected this from the pglueb and the was done
7884  * bit
7885  */
7886 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7887 {
7888         if (!CHIP_IS_E1x(bp))
7889                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7890                        1 << BP_ABS_FUNC(bp));
7891 }
7892
7893 static int bnx2x_init_hw_func(struct bnx2x *bp)
7894 {
7895         int port = BP_PORT(bp);
7896         int func = BP_FUNC(bp);
7897         int init_phase = PHASE_PF0 + func;
7898         struct bnx2x_ilt *ilt = BP_ILT(bp);
7899         u16 cdu_ilt_start;
7900         u32 addr, val;
7901         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7902         int i, main_mem_width, rc;
7903
7904         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7905
7906         /* FLR cleanup - hmmm */
7907         if (!CHIP_IS_E1x(bp)) {
7908                 rc = bnx2x_pf_flr_clnup(bp);
7909                 if (rc) {
7910                         bnx2x_fw_dump(bp);
7911                         return rc;
7912                 }
7913         }
7914
7915         /* set MSI reconfigure capability */
7916         if (bp->common.int_block == INT_BLOCK_HC) {
7917                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7918                 val = REG_RD(bp, addr);
7919                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7920                 REG_WR(bp, addr, val);
7921         }
7922
7923         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7924         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7925
7926         ilt = BP_ILT(bp);
7927         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7928
7929         if (IS_SRIOV(bp))
7930                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7931         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7932
7933         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7934          * those of the VFs, so start line should be reset
7935          */
7936         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7937         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7938                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7939                 ilt->lines[cdu_ilt_start + i].page_mapping =
7940                         bp->context[i].cxt_mapping;
7941                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7942         }
7943
7944         bnx2x_ilt_init_op(bp, INITOP_SET);
7945
7946         if (!CONFIGURE_NIC_MODE(bp)) {
7947                 bnx2x_init_searcher(bp);
7948                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7949                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7950         } else {
7951                 /* Set NIC mode */
7952                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7953                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7954         }
7955
7956         if (!CHIP_IS_E1x(bp)) {
7957                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7958
7959                 /* Turn on a single ISR mode in IGU if driver is going to use
7960                  * INT#x or MSI
7961                  */
7962                 if (!(bp->flags & USING_MSIX_FLAG))
7963                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7964                 /*
7965                  * Timers workaround bug: function init part.
7966                  * Need to wait 20msec after initializing ILT,
7967                  * needed to make sure there are no requests in
7968                  * one of the PXP internal queues with "old" ILT addresses
7969                  */
7970                 msleep(20);
7971                 /*
7972                  * Master enable - Due to WB DMAE writes performed before this
7973                  * register is re-initialized as part of the regular function
7974                  * init
7975                  */
7976                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7977                 /* Enable the function in IGU */
7978                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7979         }
7980
7981         bp->dmae_ready = 1;
7982
7983         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7984
7985         bnx2x_clean_pglue_errors(bp);
7986
7987         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7988         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7989         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7990         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7991         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7992         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7993         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7994         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7995         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7996         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7997         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7998         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7999         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8000
8001         if (!CHIP_IS_E1x(bp))
8002                 REG_WR(bp, QM_REG_PF_EN, 1);
8003
8004         if (!CHIP_IS_E1x(bp)) {
8005                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8006                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8007                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8008                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8009         }
8010         bnx2x_init_block(bp, BLOCK_QM, init_phase);
8011
8012         bnx2x_init_block(bp, BLOCK_TM, init_phase);
8013         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8014         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8015
8016         bnx2x_iov_init_dq(bp);
8017
8018         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8019         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8020         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8021         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8022         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8023         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8024         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8025         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8026         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8027         if (!CHIP_IS_E1x(bp))
8028                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8029
8030         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8031
8032         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8033
8034         if (!CHIP_IS_E1x(bp))
8035                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8036
8037         if (IS_MF(bp)) {
8038                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8039                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8040                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8041                                bp->mf_ov);
8042                 }
8043         }
8044
8045         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8046
8047         /* HC init per function */
8048         if (bp->common.int_block == INT_BLOCK_HC) {
8049                 if (CHIP_IS_E1H(bp)) {
8050                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8051
8052                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8053                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8054                 }
8055                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8056
8057         } else {
8058                 int num_segs, sb_idx, prod_offset;
8059
8060                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8061
8062                 if (!CHIP_IS_E1x(bp)) {
8063                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8064                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8065                 }
8066
8067                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8068
8069                 if (!CHIP_IS_E1x(bp)) {
8070                         int dsb_idx = 0;
8071                         /**
8072                          * Producer memory:
8073                          * E2 mode: address 0-135 match to the mapping memory;
8074                          * 136 - PF0 default prod; 137 - PF1 default prod;
8075                          * 138 - PF2 default prod; 139 - PF3 default prod;
8076                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8077                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8078                          * 144-147 reserved.
8079                          *
8080                          * E1.5 mode - In backward compatible mode;
8081                          * for non default SB; each even line in the memory
8082                          * holds the U producer and each odd line hold
8083                          * the C producer. The first 128 producers are for
8084                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8085                          * producers are for the DSB for each PF.
8086                          * Each PF has five segments: (the order inside each
8087                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8088                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8089                          * 144-147 attn prods;
8090                          */
8091                         /* non-default-status-blocks */
8092                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8093                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8094                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8095                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8096                                         num_segs;
8097
8098                                 for (i = 0; i < num_segs; i++) {
8099                                         addr = IGU_REG_PROD_CONS_MEMORY +
8100                                                         (prod_offset + i) * 4;
8101                                         REG_WR(bp, addr, 0);
8102                                 }
8103                                 /* send consumer update with value 0 */
8104                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8105                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8106                                 bnx2x_igu_clear_sb(bp,
8107                                                    bp->igu_base_sb + sb_idx);
8108                         }
8109
8110                         /* default-status-blocks */
8111                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8112                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8113
8114                         if (CHIP_MODE_IS_4_PORT(bp))
8115                                 dsb_idx = BP_FUNC(bp);
8116                         else
8117                                 dsb_idx = BP_VN(bp);
8118
8119                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8120                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8121                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8122
8123                         /*
8124                          * igu prods come in chunks of E1HVN_MAX (4) -
8125                          * does not matters what is the current chip mode
8126                          */
8127                         for (i = 0; i < (num_segs * E1HVN_MAX);
8128                              i += E1HVN_MAX) {
8129                                 addr = IGU_REG_PROD_CONS_MEMORY +
8130                                                         (prod_offset + i)*4;
8131                                 REG_WR(bp, addr, 0);
8132                         }
8133                         /* send consumer update with 0 */
8134                         if (CHIP_INT_MODE_IS_BC(bp)) {
8135                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8136                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8137                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8138                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8139                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8140                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8141                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8142                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8143                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8144                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8145                         } else {
8146                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8147                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8148                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8149                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8150                         }
8151                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8152
8153                         /* !!! These should become driver const once
8154                            rf-tool supports split-68 const */
8155                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8156                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8157                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8158                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8159                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8160                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8161                 }
8162         }
8163
8164         /* Reset PCIE errors for debug */
8165         REG_WR(bp, 0x2114, 0xffffffff);
8166         REG_WR(bp, 0x2120, 0xffffffff);
8167
8168         if (CHIP_IS_E1x(bp)) {
8169                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8170                 main_mem_base = HC_REG_MAIN_MEMORY +
8171                                 BP_PORT(bp) * (main_mem_size * 4);
8172                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8173                 main_mem_width = 8;
8174
8175                 val = REG_RD(bp, main_mem_prty_clr);
8176                 if (val)
8177                         DP(NETIF_MSG_HW,
8178                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8179                            val);
8180
8181                 /* Clear "false" parity errors in MSI-X table */
8182                 for (i = main_mem_base;
8183                      i < main_mem_base + main_mem_size * 4;
8184                      i += main_mem_width) {
8185                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8186                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8187                                          i, main_mem_width / 4);
8188                 }
8189                 /* Clear HC parity attention */
8190                 REG_RD(bp, main_mem_prty_clr);
8191         }
8192
8193 #ifdef BNX2X_STOP_ON_ERROR
8194         /* Enable STORMs SP logging */
8195         REG_WR8(bp, BAR_USTRORM_INTMEM +
8196                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8197         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8198                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8199         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8200                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8201         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8202                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8203 #endif
8204
8205         bnx2x_phy_probe(&bp->link_params);
8206
8207         return 0;
8208 }
8209
8210 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8211 {
8212         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8213
8214         if (!CHIP_IS_E1x(bp))
8215                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8216                                sizeof(struct host_hc_status_block_e2));
8217         else
8218                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8219                                sizeof(struct host_hc_status_block_e1x));
8220
8221         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8222 }
8223
8224 void bnx2x_free_mem(struct bnx2x *bp)
8225 {
8226         int i;
8227
8228         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8229                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8230
8231         if (IS_VF(bp))
8232                 return;
8233
8234         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8235                        sizeof(struct host_sp_status_block));
8236
8237         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8238                        sizeof(struct bnx2x_slowpath));
8239
8240         for (i = 0; i < L2_ILT_LINES(bp); i++)
8241                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8242                                bp->context[i].size);
8243         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8244
8245         BNX2X_FREE(bp->ilt->lines);
8246
8247         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8248
8249         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8250                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8251
8252         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8253
8254         bnx2x_iov_free_mem(bp);
8255 }
8256
8257 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8258 {
8259         if (!CHIP_IS_E1x(bp)) {
8260                 /* size = the status block + ramrod buffers */
8261                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8262                                                     sizeof(struct host_hc_status_block_e2));
8263                 if (!bp->cnic_sb.e2_sb)
8264                         goto alloc_mem_err;
8265         } else {
8266                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8267                                                      sizeof(struct host_hc_status_block_e1x));
8268                 if (!bp->cnic_sb.e1x_sb)
8269                         goto alloc_mem_err;
8270         }
8271
8272         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8273                 /* allocate searcher T2 table, as it wasn't allocated before */
8274                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8275                 if (!bp->t2)
8276                         goto alloc_mem_err;
8277         }
8278
8279         /* write address to which L5 should insert its values */
8280         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8281                 &bp->slowpath->drv_info_to_mcp;
8282
8283         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8284                 goto alloc_mem_err;
8285
8286         return 0;
8287
8288 alloc_mem_err:
8289         bnx2x_free_mem_cnic(bp);
8290         BNX2X_ERR("Can't allocate memory\n");
8291         return -ENOMEM;
8292 }
8293
8294 int bnx2x_alloc_mem(struct bnx2x *bp)
8295 {
8296         int i, allocated, context_size;
8297
8298         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8299                 /* allocate searcher T2 table */
8300                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8301                 if (!bp->t2)
8302                         goto alloc_mem_err;
8303         }
8304
8305         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8306                                              sizeof(struct host_sp_status_block));
8307         if (!bp->def_status_blk)
8308                 goto alloc_mem_err;
8309
8310         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8311                                        sizeof(struct bnx2x_slowpath));
8312         if (!bp->slowpath)
8313                 goto alloc_mem_err;
8314
8315         /* Allocate memory for CDU context:
8316          * This memory is allocated separately and not in the generic ILT
8317          * functions because CDU differs in few aspects:
8318          * 1. There are multiple entities allocating memory for context -
8319          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8320          * its own ILT lines.
8321          * 2. Since CDU page-size is not a single 4KB page (which is the case
8322          * for the other ILT clients), to be efficient we want to support
8323          * allocation of sub-page-size in the last entry.
8324          * 3. Context pointers are used by the driver to pass to FW / update
8325          * the context (for the other ILT clients the pointers are used just to
8326          * free the memory during unload).
8327          */
8328         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8329
8330         for (i = 0, allocated = 0; allocated < context_size; i++) {
8331                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8332                                           (context_size - allocated));
8333                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8334                                                       bp->context[i].size);
8335                 if (!bp->context[i].vcxt)
8336                         goto alloc_mem_err;
8337                 allocated += bp->context[i].size;
8338         }
8339         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8340                                  GFP_KERNEL);
8341         if (!bp->ilt->lines)
8342                 goto alloc_mem_err;
8343
8344         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8345                 goto alloc_mem_err;
8346
8347         if (bnx2x_iov_alloc_mem(bp))
8348                 goto alloc_mem_err;
8349
8350         /* Slow path ring */
8351         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8352         if (!bp->spq)
8353                 goto alloc_mem_err;
8354
8355         /* EQ */
8356         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8357                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8358         if (!bp->eq_ring)
8359                 goto alloc_mem_err;
8360
8361         return 0;
8362
8363 alloc_mem_err:
8364         bnx2x_free_mem(bp);
8365         BNX2X_ERR("Can't allocate memory\n");
8366         return -ENOMEM;
8367 }
8368
8369 /*
8370  * Init service functions
8371  */
8372
8373 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8374                       struct bnx2x_vlan_mac_obj *obj, bool set,
8375                       int mac_type, unsigned long *ramrod_flags)
8376 {
8377         int rc;
8378         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8379
8380         memset(&ramrod_param, 0, sizeof(ramrod_param));
8381
8382         /* Fill general parameters */
8383         ramrod_param.vlan_mac_obj = obj;
8384         ramrod_param.ramrod_flags = *ramrod_flags;
8385
8386         /* Fill a user request section if needed */
8387         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8388                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8389
8390                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8391
8392                 /* Set the command: ADD or DEL */
8393                 if (set)
8394                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8395                 else
8396                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8397         }
8398
8399         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8400
8401         if (rc == -EEXIST) {
8402                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8403                 /* do not treat adding same MAC as error */
8404                 rc = 0;
8405         } else if (rc < 0)
8406                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8407
8408         return rc;
8409 }
8410
8411 int bnx2x_del_all_macs(struct bnx2x *bp,
8412                        struct bnx2x_vlan_mac_obj *mac_obj,
8413                        int mac_type, bool wait_for_comp)
8414 {
8415         int rc;
8416         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8417
8418         /* Wait for completion of requested */
8419         if (wait_for_comp)
8420                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8421
8422         /* Set the mac type of addresses we want to clear */
8423         __set_bit(mac_type, &vlan_mac_flags);
8424
8425         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8426         if (rc < 0)
8427                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8428
8429         return rc;
8430 }
8431
8432 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8433 {
8434         if (IS_PF(bp)) {
8435                 unsigned long ramrod_flags = 0;
8436
8437                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8438                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8439                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8440                                          &bp->sp_objs->mac_obj, set,
8441                                          BNX2X_ETH_MAC, &ramrod_flags);
8442         } else { /* vf */
8443                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8444                                              bp->fp->index, set);
8445         }
8446 }
8447
8448 int bnx2x_setup_leading(struct bnx2x *bp)
8449 {
8450         if (IS_PF(bp))
8451                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8452         else /* VF */
8453                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8454 }
8455
8456 /**
8457  * bnx2x_set_int_mode - configure interrupt mode
8458  *
8459  * @bp:         driver handle
8460  *
8461  * In case of MSI-X it will also try to enable MSI-X.
8462  */
8463 int bnx2x_set_int_mode(struct bnx2x *bp)
8464 {
8465         int rc = 0;
8466
8467         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8468                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8469                 return -EINVAL;
8470         }
8471
8472         switch (int_mode) {
8473         case BNX2X_INT_MODE_MSIX:
8474                 /* attempt to enable msix */
8475                 rc = bnx2x_enable_msix(bp);
8476
8477                 /* msix attained */
8478                 if (!rc)
8479                         return 0;
8480
8481                 /* vfs use only msix */
8482                 if (rc && IS_VF(bp))
8483                         return rc;
8484
8485                 /* failed to enable multiple MSI-X */
8486                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8487                                bp->num_queues,
8488                                1 + bp->num_cnic_queues);
8489
8490                 /* falling through... */
8491         case BNX2X_INT_MODE_MSI:
8492                 bnx2x_enable_msi(bp);
8493
8494                 /* falling through... */
8495         case BNX2X_INT_MODE_INTX:
8496                 bp->num_ethernet_queues = 1;
8497                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8498                 BNX2X_DEV_INFO("set number of queues to 1\n");
8499                 break;
8500         default:
8501                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8502                 return -EINVAL;
8503         }
8504         return 0;
8505 }
8506
8507 /* must be called prior to any HW initializations */
8508 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8509 {
8510         if (IS_SRIOV(bp))
8511                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8512         return L2_ILT_LINES(bp);
8513 }
8514
8515 void bnx2x_ilt_set_info(struct bnx2x *bp)
8516 {
8517         struct ilt_client_info *ilt_client;
8518         struct bnx2x_ilt *ilt = BP_ILT(bp);
8519         u16 line = 0;
8520
8521         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8522         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8523
8524         /* CDU */
8525         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8526         ilt_client->client_num = ILT_CLIENT_CDU;
8527         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8528         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8529         ilt_client->start = line;
8530         line += bnx2x_cid_ilt_lines(bp);
8531
8532         if (CNIC_SUPPORT(bp))
8533                 line += CNIC_ILT_LINES;
8534         ilt_client->end = line - 1;
8535
8536         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8537            ilt_client->start,
8538            ilt_client->end,
8539            ilt_client->page_size,
8540            ilt_client->flags,
8541            ilog2(ilt_client->page_size >> 12));
8542
8543         /* QM */
8544         if (QM_INIT(bp->qm_cid_count)) {
8545                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8546                 ilt_client->client_num = ILT_CLIENT_QM;
8547                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8548                 ilt_client->flags = 0;
8549                 ilt_client->start = line;
8550
8551                 /* 4 bytes for each cid */
8552                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8553                                                          QM_ILT_PAGE_SZ);
8554
8555                 ilt_client->end = line - 1;
8556
8557                 DP(NETIF_MSG_IFUP,
8558                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8559                    ilt_client->start,
8560                    ilt_client->end,
8561                    ilt_client->page_size,
8562                    ilt_client->flags,
8563                    ilog2(ilt_client->page_size >> 12));
8564         }
8565
8566         if (CNIC_SUPPORT(bp)) {
8567                 /* SRC */
8568                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8569                 ilt_client->client_num = ILT_CLIENT_SRC;
8570                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8571                 ilt_client->flags = 0;
8572                 ilt_client->start = line;
8573                 line += SRC_ILT_LINES;
8574                 ilt_client->end = line - 1;
8575
8576                 DP(NETIF_MSG_IFUP,
8577                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8578                    ilt_client->start,
8579                    ilt_client->end,
8580                    ilt_client->page_size,
8581                    ilt_client->flags,
8582                    ilog2(ilt_client->page_size >> 12));
8583
8584                 /* TM */
8585                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8586                 ilt_client->client_num = ILT_CLIENT_TM;
8587                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8588                 ilt_client->flags = 0;
8589                 ilt_client->start = line;
8590                 line += TM_ILT_LINES;
8591                 ilt_client->end = line - 1;
8592
8593                 DP(NETIF_MSG_IFUP,
8594                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8595                    ilt_client->start,
8596                    ilt_client->end,
8597                    ilt_client->page_size,
8598                    ilt_client->flags,
8599                    ilog2(ilt_client->page_size >> 12));
8600         }
8601
8602         BUG_ON(line > ILT_MAX_LINES);
8603 }
8604
8605 /**
8606  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8607  *
8608  * @bp:                 driver handle
8609  * @fp:                 pointer to fastpath
8610  * @init_params:        pointer to parameters structure
8611  *
8612  * parameters configured:
8613  *      - HC configuration
8614  *      - Queue's CDU context
8615  */
8616 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8617         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8618 {
8619         u8 cos;
8620         int cxt_index, cxt_offset;
8621
8622         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8623         if (!IS_FCOE_FP(fp)) {
8624                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8625                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8626
8627                 /* If HC is supported, enable host coalescing in the transition
8628                  * to INIT state.
8629                  */
8630                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8631                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8632
8633                 /* HC rate */
8634                 init_params->rx.hc_rate = bp->rx_ticks ?
8635                         (1000000 / bp->rx_ticks) : 0;
8636                 init_params->tx.hc_rate = bp->tx_ticks ?
8637                         (1000000 / bp->tx_ticks) : 0;
8638
8639                 /* FW SB ID */
8640                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8641                         fp->fw_sb_id;
8642
8643                 /*
8644                  * CQ index among the SB indices: FCoE clients uses the default
8645                  * SB, therefore it's different.
8646                  */
8647                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8648                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8649         }
8650
8651         /* set maximum number of COSs supported by this queue */
8652         init_params->max_cos = fp->max_cos;
8653
8654         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8655             fp->index, init_params->max_cos);
8656
8657         /* set the context pointers queue object */
8658         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8659                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8660                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8661                                 ILT_PAGE_CIDS);
8662                 init_params->cxts[cos] =
8663                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8664         }
8665 }
8666
8667 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8668                         struct bnx2x_queue_state_params *q_params,
8669                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8670                         int tx_index, bool leading)
8671 {
8672         memset(tx_only_params, 0, sizeof(*tx_only_params));
8673
8674         /* Set the command */
8675         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8676
8677         /* Set tx-only QUEUE flags: don't zero statistics */
8678         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8679
8680         /* choose the index of the cid to send the slow path on */
8681         tx_only_params->cid_index = tx_index;
8682
8683         /* Set general TX_ONLY_SETUP parameters */
8684         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8685
8686         /* Set Tx TX_ONLY_SETUP parameters */
8687         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8688
8689         DP(NETIF_MSG_IFUP,
8690            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8691            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8692            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8693            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8694
8695         /* send the ramrod */
8696         return bnx2x_queue_state_change(bp, q_params);
8697 }
8698
8699 /**
8700  * bnx2x_setup_queue - setup queue
8701  *
8702  * @bp:         driver handle
8703  * @fp:         pointer to fastpath
8704  * @leading:    is leading
8705  *
8706  * This function performs 2 steps in a Queue state machine
8707  *      actually: 1) RESET->INIT 2) INIT->SETUP
8708  */
8709
8710 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8711                        bool leading)
8712 {
8713         struct bnx2x_queue_state_params q_params = {NULL};
8714         struct bnx2x_queue_setup_params *setup_params =
8715                                                 &q_params.params.setup;
8716         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8717                                                 &q_params.params.tx_only;
8718         int rc;
8719         u8 tx_index;
8720
8721         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8722
8723         /* reset IGU state skip FCoE L2 queue */
8724         if (!IS_FCOE_FP(fp))
8725                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8726                              IGU_INT_ENABLE, 0);
8727
8728         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8729         /* We want to wait for completion in this context */
8730         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8731
8732         /* Prepare the INIT parameters */
8733         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8734
8735         /* Set the command */
8736         q_params.cmd = BNX2X_Q_CMD_INIT;
8737
8738         /* Change the state to INIT */
8739         rc = bnx2x_queue_state_change(bp, &q_params);
8740         if (rc) {
8741                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8742                 return rc;
8743         }
8744
8745         DP(NETIF_MSG_IFUP, "init complete\n");
8746
8747         /* Now move the Queue to the SETUP state... */
8748         memset(setup_params, 0, sizeof(*setup_params));
8749
8750         /* Set QUEUE flags */
8751         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8752
8753         /* Set general SETUP parameters */
8754         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8755                                 FIRST_TX_COS_INDEX);
8756
8757         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8758                             &setup_params->rxq_params);
8759
8760         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8761                            FIRST_TX_COS_INDEX);
8762
8763         /* Set the command */
8764         q_params.cmd = BNX2X_Q_CMD_SETUP;
8765
8766         if (IS_FCOE_FP(fp))
8767                 bp->fcoe_init = true;
8768
8769         /* Change the state to SETUP */
8770         rc = bnx2x_queue_state_change(bp, &q_params);
8771         if (rc) {
8772                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8773                 return rc;
8774         }
8775
8776         /* loop through the relevant tx-only indices */
8777         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8778               tx_index < fp->max_cos;
8779               tx_index++) {
8780
8781                 /* prepare and send tx-only ramrod*/
8782                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8783                                           tx_only_params, tx_index, leading);
8784                 if (rc) {
8785                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8786                                   fp->index, tx_index);
8787                         return rc;
8788                 }
8789         }
8790
8791         return rc;
8792 }
8793
8794 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8795 {
8796         struct bnx2x_fastpath *fp = &bp->fp[index];
8797         struct bnx2x_fp_txdata *txdata;
8798         struct bnx2x_queue_state_params q_params = {NULL};
8799         int rc, tx_index;
8800
8801         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8802
8803         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8804         /* We want to wait for completion in this context */
8805         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8806
8807         /* close tx-only connections */
8808         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8809              tx_index < fp->max_cos;
8810              tx_index++){
8811
8812                 /* ascertain this is a normal queue*/
8813                 txdata = fp->txdata_ptr[tx_index];
8814
8815                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8816                                                         txdata->txq_index);
8817
8818                 /* send halt terminate on tx-only connection */
8819                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8820                 memset(&q_params.params.terminate, 0,
8821                        sizeof(q_params.params.terminate));
8822                 q_params.params.terminate.cid_index = tx_index;
8823
8824                 rc = bnx2x_queue_state_change(bp, &q_params);
8825                 if (rc)
8826                         return rc;
8827
8828                 /* send halt terminate on tx-only connection */
8829                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8830                 memset(&q_params.params.cfc_del, 0,
8831                        sizeof(q_params.params.cfc_del));
8832                 q_params.params.cfc_del.cid_index = tx_index;
8833                 rc = bnx2x_queue_state_change(bp, &q_params);
8834                 if (rc)
8835                         return rc;
8836         }
8837         /* Stop the primary connection: */
8838         /* ...halt the connection */
8839         q_params.cmd = BNX2X_Q_CMD_HALT;
8840         rc = bnx2x_queue_state_change(bp, &q_params);
8841         if (rc)
8842                 return rc;
8843
8844         /* ...terminate the connection */
8845         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8846         memset(&q_params.params.terminate, 0,
8847                sizeof(q_params.params.terminate));
8848         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8849         rc = bnx2x_queue_state_change(bp, &q_params);
8850         if (rc)
8851                 return rc;
8852         /* ...delete cfc entry */
8853         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8854         memset(&q_params.params.cfc_del, 0,
8855                sizeof(q_params.params.cfc_del));
8856         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8857         return bnx2x_queue_state_change(bp, &q_params);
8858 }
8859
8860 static void bnx2x_reset_func(struct bnx2x *bp)
8861 {
8862         int port = BP_PORT(bp);
8863         int func = BP_FUNC(bp);
8864         int i;
8865
8866         /* Disable the function in the FW */
8867         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8868         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8869         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8870         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8871
8872         /* FP SBs */
8873         for_each_eth_queue(bp, i) {
8874                 struct bnx2x_fastpath *fp = &bp->fp[i];
8875                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8876                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8877                            SB_DISABLED);
8878         }
8879
8880         if (CNIC_LOADED(bp))
8881                 /* CNIC SB */
8882                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8883                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8884                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8885
8886         /* SP SB */
8887         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8888                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8889                 SB_DISABLED);
8890
8891         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8892                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8893                        0);
8894
8895         /* Configure IGU */
8896         if (bp->common.int_block == INT_BLOCK_HC) {
8897                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8898                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8899         } else {
8900                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8901                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8902         }
8903
8904         if (CNIC_LOADED(bp)) {
8905                 /* Disable Timer scan */
8906                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8907                 /*
8908                  * Wait for at least 10ms and up to 2 second for the timers
8909                  * scan to complete
8910                  */
8911                 for (i = 0; i < 200; i++) {
8912                         usleep_range(10000, 20000);
8913                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8914                                 break;
8915                 }
8916         }
8917         /* Clear ILT */
8918         bnx2x_clear_func_ilt(bp, func);
8919
8920         /* Timers workaround bug for E2: if this is vnic-3,
8921          * we need to set the entire ilt range for this timers.
8922          */
8923         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8924                 struct ilt_client_info ilt_cli;
8925                 /* use dummy TM client */
8926                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8927                 ilt_cli.start = 0;
8928                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8929                 ilt_cli.client_num = ILT_CLIENT_TM;
8930
8931                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8932         }
8933
8934         /* this assumes that reset_port() called before reset_func()*/
8935         if (!CHIP_IS_E1x(bp))
8936                 bnx2x_pf_disable(bp);
8937
8938         bp->dmae_ready = 0;
8939 }
8940
8941 static void bnx2x_reset_port(struct bnx2x *bp)
8942 {
8943         int port = BP_PORT(bp);
8944         u32 val;
8945
8946         /* Reset physical Link */
8947         bnx2x__link_reset(bp);
8948
8949         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8950
8951         /* Do not rcv packets to BRB */
8952         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8953         /* Do not direct rcv packets that are not for MCP to the BRB */
8954         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8955                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8956
8957         /* Configure AEU */
8958         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8959
8960         msleep(100);
8961         /* Check for BRB port occupancy */
8962         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8963         if (val)
8964                 DP(NETIF_MSG_IFDOWN,
8965                    "BRB1 is not empty  %d blocks are occupied\n", val);
8966
8967         /* TODO: Close Doorbell port? */
8968 }
8969
8970 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8971 {
8972         struct bnx2x_func_state_params func_params = {NULL};
8973
8974         /* Prepare parameters for function state transitions */
8975         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8976
8977         func_params.f_obj = &bp->func_obj;
8978         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8979
8980         func_params.params.hw_init.load_phase = load_code;
8981
8982         return bnx2x_func_state_change(bp, &func_params);
8983 }
8984
8985 static int bnx2x_func_stop(struct bnx2x *bp)
8986 {
8987         struct bnx2x_func_state_params func_params = {NULL};
8988         int rc;
8989
8990         /* Prepare parameters for function state transitions */
8991         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8992         func_params.f_obj = &bp->func_obj;
8993         func_params.cmd = BNX2X_F_CMD_STOP;
8994
8995         /*
8996          * Try to stop the function the 'good way'. If fails (in case
8997          * of a parity error during bnx2x_chip_cleanup()) and we are
8998          * not in a debug mode, perform a state transaction in order to
8999          * enable further HW_RESET transaction.
9000          */
9001         rc = bnx2x_func_state_change(bp, &func_params);
9002         if (rc) {
9003 #ifdef BNX2X_STOP_ON_ERROR
9004                 return rc;
9005 #else
9006                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9007                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9008                 return bnx2x_func_state_change(bp, &func_params);
9009 #endif
9010         }
9011
9012         return 0;
9013 }
9014
9015 /**
9016  * bnx2x_send_unload_req - request unload mode from the MCP.
9017  *
9018  * @bp:                 driver handle
9019  * @unload_mode:        requested function's unload mode
9020  *
9021  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9022  */
9023 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9024 {
9025         u32 reset_code = 0;
9026         int port = BP_PORT(bp);
9027
9028         /* Select the UNLOAD request mode */
9029         if (unload_mode == UNLOAD_NORMAL)
9030                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9031
9032         else if (bp->flags & NO_WOL_FLAG)
9033                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9034
9035         else if (bp->wol) {
9036                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9037                 u8 *mac_addr = bp->dev->dev_addr;
9038                 struct pci_dev *pdev = bp->pdev;
9039                 u32 val;
9040                 u16 pmc;
9041
9042                 /* The mac address is written to entries 1-4 to
9043                  * preserve entry 0 which is used by the PMF
9044                  */
9045                 u8 entry = (BP_VN(bp) + 1)*8;
9046
9047                 val = (mac_addr[0] << 8) | mac_addr[1];
9048                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9049
9050                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9051                       (mac_addr[4] << 8) | mac_addr[5];
9052                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9053
9054                 /* Enable the PME and clear the status */
9055                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9056                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9057                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9058
9059                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9060
9061         } else
9062                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9063
9064         /* Send the request to the MCP */
9065         if (!BP_NOMCP(bp))
9066                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9067         else {
9068                 int path = BP_PATH(bp);
9069
9070                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9071                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9072                    bnx2x_load_count[path][2]);
9073                 bnx2x_load_count[path][0]--;
9074                 bnx2x_load_count[path][1 + port]--;
9075                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9076                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9077                    bnx2x_load_count[path][2]);
9078                 if (bnx2x_load_count[path][0] == 0)
9079                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9080                 else if (bnx2x_load_count[path][1 + port] == 0)
9081                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9082                 else
9083                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9084         }
9085
9086         return reset_code;
9087 }
9088
9089 /**
9090  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9091  *
9092  * @bp:         driver handle
9093  * @keep_link:          true iff link should be kept up
9094  */
9095 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9096 {
9097         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9098
9099         /* Report UNLOAD_DONE to MCP */
9100         if (!BP_NOMCP(bp))
9101                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9102 }
9103
9104 static int bnx2x_func_wait_started(struct bnx2x *bp)
9105 {
9106         int tout = 50;
9107         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9108
9109         if (!bp->port.pmf)
9110                 return 0;
9111
9112         /*
9113          * (assumption: No Attention from MCP at this stage)
9114          * PMF probably in the middle of TX disable/enable transaction
9115          * 1. Sync IRS for default SB
9116          * 2. Sync SP queue - this guarantees us that attention handling started
9117          * 3. Wait, that TX disable/enable transaction completes
9118          *
9119          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9120          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9121          * received completion for the transaction the state is TX_STOPPED.
9122          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9123          * transaction.
9124          */
9125
9126         /* make sure default SB ISR is done */
9127         if (msix)
9128                 synchronize_irq(bp->msix_table[0].vector);
9129         else
9130                 synchronize_irq(bp->pdev->irq);
9131
9132         flush_workqueue(bnx2x_wq);
9133         flush_workqueue(bnx2x_iov_wq);
9134
9135         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9136                                 BNX2X_F_STATE_STARTED && tout--)
9137                 msleep(20);
9138
9139         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9140                                                 BNX2X_F_STATE_STARTED) {
9141 #ifdef BNX2X_STOP_ON_ERROR
9142                 BNX2X_ERR("Wrong function state\n");
9143                 return -EBUSY;
9144 #else
9145                 /*
9146                  * Failed to complete the transaction in a "good way"
9147                  * Force both transactions with CLR bit
9148                  */
9149                 struct bnx2x_func_state_params func_params = {NULL};
9150
9151                 DP(NETIF_MSG_IFDOWN,
9152                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9153
9154                 func_params.f_obj = &bp->func_obj;
9155                 __set_bit(RAMROD_DRV_CLR_ONLY,
9156                                         &func_params.ramrod_flags);
9157
9158                 /* STARTED-->TX_ST0PPED */
9159                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9160                 bnx2x_func_state_change(bp, &func_params);
9161
9162                 /* TX_ST0PPED-->STARTED */
9163                 func_params.cmd = BNX2X_F_CMD_TX_START;
9164                 return bnx2x_func_state_change(bp, &func_params);
9165 #endif
9166         }
9167
9168         return 0;
9169 }
9170
9171 static void bnx2x_disable_ptp(struct bnx2x *bp)
9172 {
9173         int port = BP_PORT(bp);
9174
9175         /* Disable sending PTP packets to host */
9176         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9177                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9178
9179         /* Reset PTP event detection rules */
9180         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9181                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9182         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9183                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9184         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9185                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9186         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9187                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9188
9189         /* Disable the PTP feature */
9190         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9191                NIG_REG_P0_PTP_EN, 0x0);
9192 }
9193
9194 /* Called during unload, to stop PTP-related stuff */
9195 static void bnx2x_stop_ptp(struct bnx2x *bp)
9196 {
9197         /* Cancel PTP work queue. Should be done after the Tx queues are
9198          * drained to prevent additional scheduling.
9199          */
9200         cancel_work_sync(&bp->ptp_task);
9201
9202         if (bp->ptp_tx_skb) {
9203                 dev_kfree_skb_any(bp->ptp_tx_skb);
9204                 bp->ptp_tx_skb = NULL;
9205         }
9206
9207         /* Disable PTP in HW */
9208         bnx2x_disable_ptp(bp);
9209
9210         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9211 }
9212
9213 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9214 {
9215         int port = BP_PORT(bp);
9216         int i, rc = 0;
9217         u8 cos;
9218         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9219         u32 reset_code;
9220
9221         /* Wait until tx fastpath tasks complete */
9222         for_each_tx_queue(bp, i) {
9223                 struct bnx2x_fastpath *fp = &bp->fp[i];
9224
9225                 for_each_cos_in_tx_queue(fp, cos)
9226                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9227 #ifdef BNX2X_STOP_ON_ERROR
9228                 if (rc)
9229                         return;
9230 #endif
9231         }
9232
9233         /* Give HW time to discard old tx messages */
9234         usleep_range(1000, 2000);
9235
9236         /* Clean all ETH MACs */
9237         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9238                                 false);
9239         if (rc < 0)
9240                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9241
9242         /* Clean up UC list  */
9243         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9244                                 true);
9245         if (rc < 0)
9246                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9247                           rc);
9248
9249         /* Disable LLH */
9250         if (!CHIP_IS_E1(bp))
9251                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9252
9253         /* Set "drop all" (stop Rx).
9254          * We need to take a netif_addr_lock() here in order to prevent
9255          * a race between the completion code and this code.
9256          */
9257         netif_addr_lock_bh(bp->dev);
9258         /* Schedule the rx_mode command */
9259         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9260                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9261         else
9262                 bnx2x_set_storm_rx_mode(bp);
9263
9264         /* Cleanup multicast configuration */
9265         rparam.mcast_obj = &bp->mcast_obj;
9266         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9267         if (rc < 0)
9268                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9269
9270         netif_addr_unlock_bh(bp->dev);
9271
9272         bnx2x_iov_chip_cleanup(bp);
9273
9274         /*
9275          * Send the UNLOAD_REQUEST to the MCP. This will return if
9276          * this function should perform FUNC, PORT or COMMON HW
9277          * reset.
9278          */
9279         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9280
9281         /*
9282          * (assumption: No Attention from MCP at this stage)
9283          * PMF probably in the middle of TX disable/enable transaction
9284          */
9285         rc = bnx2x_func_wait_started(bp);
9286         if (rc) {
9287                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9288 #ifdef BNX2X_STOP_ON_ERROR
9289                 return;
9290 #endif
9291         }
9292
9293         /* Close multi and leading connections
9294          * Completions for ramrods are collected in a synchronous way
9295          */
9296         for_each_eth_queue(bp, i)
9297                 if (bnx2x_stop_queue(bp, i))
9298 #ifdef BNX2X_STOP_ON_ERROR
9299                         return;
9300 #else
9301                         goto unload_error;
9302 #endif
9303
9304         if (CNIC_LOADED(bp)) {
9305                 for_each_cnic_queue(bp, i)
9306                         if (bnx2x_stop_queue(bp, i))
9307 #ifdef BNX2X_STOP_ON_ERROR
9308                                 return;
9309 #else
9310                                 goto unload_error;
9311 #endif
9312         }
9313
9314         /* If SP settings didn't get completed so far - something
9315          * very wrong has happen.
9316          */
9317         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9318                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9319
9320 #ifndef BNX2X_STOP_ON_ERROR
9321 unload_error:
9322 #endif
9323         rc = bnx2x_func_stop(bp);
9324         if (rc) {
9325                 BNX2X_ERR("Function stop failed!\n");
9326 #ifdef BNX2X_STOP_ON_ERROR
9327                 return;
9328 #endif
9329         }
9330
9331         /* stop_ptp should be after the Tx queues are drained to prevent
9332          * scheduling to the cancelled PTP work queue. It should also be after
9333          * function stop ramrod is sent, since as part of this ramrod FW access
9334          * PTP registers.
9335          */
9336         if (bp->flags & PTP_SUPPORTED)
9337                 bnx2x_stop_ptp(bp);
9338
9339         /* Disable HW interrupts, NAPI */
9340         bnx2x_netif_stop(bp, 1);
9341         /* Delete all NAPI objects */
9342         bnx2x_del_all_napi(bp);
9343         if (CNIC_LOADED(bp))
9344                 bnx2x_del_all_napi_cnic(bp);
9345
9346         /* Release IRQs */
9347         bnx2x_free_irq(bp);
9348
9349         /* Reset the chip */
9350         rc = bnx2x_reset_hw(bp, reset_code);
9351         if (rc)
9352                 BNX2X_ERR("HW_RESET failed\n");
9353
9354         /* Report UNLOAD_DONE to MCP */
9355         bnx2x_send_unload_done(bp, keep_link);
9356 }
9357
9358 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9359 {
9360         u32 val;
9361
9362         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9363
9364         if (CHIP_IS_E1(bp)) {
9365                 int port = BP_PORT(bp);
9366                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9367                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9368
9369                 val = REG_RD(bp, addr);
9370                 val &= ~(0x300);
9371                 REG_WR(bp, addr, val);
9372         } else {
9373                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9374                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9375                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9376                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9377         }
9378 }
9379
9380 /* Close gates #2, #3 and #4: */
9381 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9382 {
9383         u32 val;
9384
9385         /* Gates #2 and #4a are closed/opened for "not E1" only */
9386         if (!CHIP_IS_E1(bp)) {
9387                 /* #4 */
9388                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9389                 /* #2 */
9390                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9391         }
9392
9393         /* #3 */
9394         if (CHIP_IS_E1x(bp)) {
9395                 /* Prevent interrupts from HC on both ports */
9396                 val = REG_RD(bp, HC_REG_CONFIG_1);
9397                 REG_WR(bp, HC_REG_CONFIG_1,
9398                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9399                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9400
9401                 val = REG_RD(bp, HC_REG_CONFIG_0);
9402                 REG_WR(bp, HC_REG_CONFIG_0,
9403                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9404                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9405         } else {
9406                 /* Prevent incoming interrupts in IGU */
9407                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9408
9409                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9410                        (!close) ?
9411                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9412                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9413         }
9414
9415         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9416                 close ? "closing" : "opening");
9417         mmiowb();
9418 }
9419
9420 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9421
9422 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9423 {
9424         /* Do some magic... */
9425         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9426         *magic_val = val & SHARED_MF_CLP_MAGIC;
9427         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9428 }
9429
9430 /**
9431  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9432  *
9433  * @bp:         driver handle
9434  * @magic_val:  old value of the `magic' bit.
9435  */
9436 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9437 {
9438         /* Restore the `magic' bit value... */
9439         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9440         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9441                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9442 }
9443
9444 /**
9445  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9446  *
9447  * @bp:         driver handle
9448  * @magic_val:  old value of 'magic' bit.
9449  *
9450  * Takes care of CLP configurations.
9451  */
9452 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9453 {
9454         u32 shmem;
9455         u32 validity_offset;
9456
9457         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9458
9459         /* Set `magic' bit in order to save MF config */
9460         if (!CHIP_IS_E1(bp))
9461                 bnx2x_clp_reset_prep(bp, magic_val);
9462
9463         /* Get shmem offset */
9464         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9465         validity_offset =
9466                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9467
9468         /* Clear validity map flags */
9469         if (shmem > 0)
9470                 REG_WR(bp, shmem + validity_offset, 0);
9471 }
9472
9473 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9474 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9475
9476 /**
9477  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9478  *
9479  * @bp: driver handle
9480  */
9481 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9482 {
9483         /* special handling for emulation and FPGA,
9484            wait 10 times longer */
9485         if (CHIP_REV_IS_SLOW(bp))
9486                 msleep(MCP_ONE_TIMEOUT*10);
9487         else
9488                 msleep(MCP_ONE_TIMEOUT);
9489 }
9490
9491 /*
9492  * initializes bp->common.shmem_base and waits for validity signature to appear
9493  */
9494 static int bnx2x_init_shmem(struct bnx2x *bp)
9495 {
9496         int cnt = 0;
9497         u32 val = 0;
9498
9499         do {
9500                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9501                 if (bp->common.shmem_base) {
9502                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9503                         if (val & SHR_MEM_VALIDITY_MB)
9504                                 return 0;
9505                 }
9506
9507                 bnx2x_mcp_wait_one(bp);
9508
9509         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9510
9511         BNX2X_ERR("BAD MCP validity signature\n");
9512
9513         return -ENODEV;
9514 }
9515
9516 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9517 {
9518         int rc = bnx2x_init_shmem(bp);
9519
9520         /* Restore the `magic' bit value */
9521         if (!CHIP_IS_E1(bp))
9522                 bnx2x_clp_reset_done(bp, magic_val);
9523
9524         return rc;
9525 }
9526
9527 static void bnx2x_pxp_prep(struct bnx2x *bp)
9528 {
9529         if (!CHIP_IS_E1(bp)) {
9530                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9531                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9532                 mmiowb();
9533         }
9534 }
9535
9536 /*
9537  * Reset the whole chip except for:
9538  *      - PCIE core
9539  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9540  *              one reset bit)
9541  *      - IGU
9542  *      - MISC (including AEU)
9543  *      - GRC
9544  *      - RBCN, RBCP
9545  */
9546 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9547 {
9548         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9549         u32 global_bits2, stay_reset2;
9550
9551         /*
9552          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9553          * (per chip) blocks.
9554          */
9555         global_bits2 =
9556                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9557                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9558
9559         /* Don't reset the following blocks.
9560          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9561          *            reset, as in 4 port device they might still be owned
9562          *            by the MCP (there is only one leader per path).
9563          */
9564         not_reset_mask1 =
9565                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9566                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9567                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9568
9569         not_reset_mask2 =
9570                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9571                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9572                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9573                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9574                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9575                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9576                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9577                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9578                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9579                 MISC_REGISTERS_RESET_REG_2_PGLC |
9580                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9581                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9582                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9583                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9584                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9585                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9586
9587         /*
9588          * Keep the following blocks in reset:
9589          *  - all xxMACs are handled by the bnx2x_link code.
9590          */
9591         stay_reset2 =
9592                 MISC_REGISTERS_RESET_REG_2_XMAC |
9593                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9594
9595         /* Full reset masks according to the chip */
9596         reset_mask1 = 0xffffffff;
9597
9598         if (CHIP_IS_E1(bp))
9599                 reset_mask2 = 0xffff;
9600         else if (CHIP_IS_E1H(bp))
9601                 reset_mask2 = 0x1ffff;
9602         else if (CHIP_IS_E2(bp))
9603                 reset_mask2 = 0xfffff;
9604         else /* CHIP_IS_E3 */
9605                 reset_mask2 = 0x3ffffff;
9606
9607         /* Don't reset global blocks unless we need to */
9608         if (!global)
9609                 reset_mask2 &= ~global_bits2;
9610
9611         /*
9612          * In case of attention in the QM, we need to reset PXP
9613          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9614          * because otherwise QM reset would release 'close the gates' shortly
9615          * before resetting the PXP, then the PSWRQ would send a write
9616          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9617          * read the payload data from PSWWR, but PSWWR would not
9618          * respond. The write queue in PGLUE would stuck, dmae commands
9619          * would not return. Therefore it's important to reset the second
9620          * reset register (containing the
9621          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9622          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9623          * bit).
9624          */
9625         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9626                reset_mask2 & (~not_reset_mask2));
9627
9628         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9629                reset_mask1 & (~not_reset_mask1));
9630
9631         barrier();
9632         mmiowb();
9633
9634         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9635                reset_mask2 & (~stay_reset2));
9636
9637         barrier();
9638         mmiowb();
9639
9640         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9641         mmiowb();
9642 }
9643
9644 /**
9645  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9646  * It should get cleared in no more than 1s.
9647  *
9648  * @bp: driver handle
9649  *
9650  * It should get cleared in no more than 1s. Returns 0 if
9651  * pending writes bit gets cleared.
9652  */
9653 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9654 {
9655         u32 cnt = 1000;
9656         u32 pend_bits = 0;
9657
9658         do {
9659                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9660
9661                 if (pend_bits == 0)
9662                         break;
9663
9664                 usleep_range(1000, 2000);
9665         } while (cnt-- > 0);
9666
9667         if (cnt <= 0) {
9668                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9669                           pend_bits);
9670                 return -EBUSY;
9671         }
9672
9673         return 0;
9674 }
9675
9676 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9677 {
9678         int cnt = 1000;
9679         u32 val = 0;
9680         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9681         u32 tags_63_32 = 0;
9682
9683         /* Empty the Tetris buffer, wait for 1s */
9684         do {
9685                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9686                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9687                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9688                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9689                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9690                 if (CHIP_IS_E3(bp))
9691                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9692
9693                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9694                     ((port_is_idle_0 & 0x1) == 0x1) &&
9695                     ((port_is_idle_1 & 0x1) == 0x1) &&
9696                     (pgl_exp_rom2 == 0xffffffff) &&
9697                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9698                         break;
9699                 usleep_range(1000, 2000);
9700         } while (cnt-- > 0);
9701
9702         if (cnt <= 0) {
9703                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9704                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9705                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9706                           pgl_exp_rom2);
9707                 return -EAGAIN;
9708         }
9709
9710         barrier();
9711
9712         /* Close gates #2, #3 and #4 */
9713         bnx2x_set_234_gates(bp, true);
9714
9715         /* Poll for IGU VQs for 57712 and newer chips */
9716         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9717                 return -EAGAIN;
9718
9719         /* TBD: Indicate that "process kill" is in progress to MCP */
9720
9721         /* Clear "unprepared" bit */
9722         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9723         barrier();
9724
9725         /* Make sure all is written to the chip before the reset */
9726         mmiowb();
9727
9728         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9729          * PSWHST, GRC and PSWRD Tetris buffer.
9730          */
9731         usleep_range(1000, 2000);
9732
9733         /* Prepare to chip reset: */
9734         /* MCP */
9735         if (global)
9736                 bnx2x_reset_mcp_prep(bp, &val);
9737
9738         /* PXP */
9739         bnx2x_pxp_prep(bp);
9740         barrier();
9741
9742         /* reset the chip */
9743         bnx2x_process_kill_chip_reset(bp, global);
9744         barrier();
9745
9746         /* clear errors in PGB */
9747         if (!CHIP_IS_E1x(bp))
9748                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9749
9750         /* Recover after reset: */
9751         /* MCP */
9752         if (global && bnx2x_reset_mcp_comp(bp, val))
9753                 return -EAGAIN;
9754
9755         /* TBD: Add resetting the NO_MCP mode DB here */
9756
9757         /* Open the gates #2, #3 and #4 */
9758         bnx2x_set_234_gates(bp, false);
9759
9760         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9761          * reset state, re-enable attentions. */
9762
9763         return 0;
9764 }
9765
9766 static int bnx2x_leader_reset(struct bnx2x *bp)
9767 {
9768         int rc = 0;
9769         bool global = bnx2x_reset_is_global(bp);
9770         u32 load_code;
9771
9772         /* if not going to reset MCP - load "fake" driver to reset HW while
9773          * driver is owner of the HW
9774          */
9775         if (!global && !BP_NOMCP(bp)) {
9776                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9777                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9778                 if (!load_code) {
9779                         BNX2X_ERR("MCP response failure, aborting\n");
9780                         rc = -EAGAIN;
9781                         goto exit_leader_reset;
9782                 }
9783                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9784                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9785                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9786                         rc = -EAGAIN;
9787                         goto exit_leader_reset2;
9788                 }
9789                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9790                 if (!load_code) {
9791                         BNX2X_ERR("MCP response failure, aborting\n");
9792                         rc = -EAGAIN;
9793                         goto exit_leader_reset2;
9794                 }
9795         }
9796
9797         /* Try to recover after the failure */
9798         if (bnx2x_process_kill(bp, global)) {
9799                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9800                           BP_PATH(bp));
9801                 rc = -EAGAIN;
9802                 goto exit_leader_reset2;
9803         }
9804
9805         /*
9806          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9807          * state.
9808          */
9809         bnx2x_set_reset_done(bp);
9810         if (global)
9811                 bnx2x_clear_reset_global(bp);
9812
9813 exit_leader_reset2:
9814         /* unload "fake driver" if it was loaded */
9815         if (!global && !BP_NOMCP(bp)) {
9816                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9817                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9818         }
9819 exit_leader_reset:
9820         bp->is_leader = 0;
9821         bnx2x_release_leader_lock(bp);
9822         smp_mb();
9823         return rc;
9824 }
9825
9826 static void bnx2x_recovery_failed(struct bnx2x *bp)
9827 {
9828         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9829
9830         /* Disconnect this device */
9831         netif_device_detach(bp->dev);
9832
9833         /*
9834          * Block ifup for all function on this engine until "process kill"
9835          * or power cycle.
9836          */
9837         bnx2x_set_reset_in_progress(bp);
9838
9839         /* Shut down the power */
9840         bnx2x_set_power_state(bp, PCI_D3hot);
9841
9842         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9843
9844         smp_mb();
9845 }
9846
9847 /*
9848  * Assumption: runs under rtnl lock. This together with the fact
9849  * that it's called only from bnx2x_sp_rtnl() ensure that it
9850  * will never be called when netif_running(bp->dev) is false.
9851  */
9852 static void bnx2x_parity_recover(struct bnx2x *bp)
9853 {
9854         bool global = false;
9855         u32 error_recovered, error_unrecovered;
9856         bool is_parity;
9857
9858         DP(NETIF_MSG_HW, "Handling parity\n");
9859         while (1) {
9860                 switch (bp->recovery_state) {
9861                 case BNX2X_RECOVERY_INIT:
9862                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9863                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9864                         WARN_ON(!is_parity);
9865
9866                         /* Try to get a LEADER_LOCK HW lock */
9867                         if (bnx2x_trylock_leader_lock(bp)) {
9868                                 bnx2x_set_reset_in_progress(bp);
9869                                 /*
9870                                  * Check if there is a global attention and if
9871                                  * there was a global attention, set the global
9872                                  * reset bit.
9873                                  */
9874
9875                                 if (global)
9876                                         bnx2x_set_reset_global(bp);
9877
9878                                 bp->is_leader = 1;
9879                         }
9880
9881                         /* Stop the driver */
9882                         /* If interface has been removed - break */
9883                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9884                                 return;
9885
9886                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9887
9888                         /* Ensure "is_leader", MCP command sequence and
9889                          * "recovery_state" update values are seen on other
9890                          * CPUs.
9891                          */
9892                         smp_mb();
9893                         break;
9894
9895                 case BNX2X_RECOVERY_WAIT:
9896                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9897                         if (bp->is_leader) {
9898                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9899                                 bool other_load_status =
9900                                         bnx2x_get_load_status(bp, other_engine);
9901                                 bool load_status =
9902                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9903                                 global = bnx2x_reset_is_global(bp);
9904
9905                                 /*
9906                                  * In case of a parity in a global block, let
9907                                  * the first leader that performs a
9908                                  * leader_reset() reset the global blocks in
9909                                  * order to clear global attentions. Otherwise
9910                                  * the gates will remain closed for that
9911                                  * engine.
9912                                  */
9913                                 if (load_status ||
9914                                     (global && other_load_status)) {
9915                                         /* Wait until all other functions get
9916                                          * down.
9917                                          */
9918                                         schedule_delayed_work(&bp->sp_rtnl_task,
9919                                                                 HZ/10);
9920                                         return;
9921                                 } else {
9922                                         /* If all other functions got down -
9923                                          * try to bring the chip back to
9924                                          * normal. In any case it's an exit
9925                                          * point for a leader.
9926                                          */
9927                                         if (bnx2x_leader_reset(bp)) {
9928                                                 bnx2x_recovery_failed(bp);
9929                                                 return;
9930                                         }
9931
9932                                         /* If we are here, means that the
9933                                          * leader has succeeded and doesn't
9934                                          * want to be a leader any more. Try
9935                                          * to continue as a none-leader.
9936                                          */
9937                                         break;
9938                                 }
9939                         } else { /* non-leader */
9940                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9941                                         /* Try to get a LEADER_LOCK HW lock as
9942                                          * long as a former leader may have
9943                                          * been unloaded by the user or
9944                                          * released a leadership by another
9945                                          * reason.
9946                                          */
9947                                         if (bnx2x_trylock_leader_lock(bp)) {
9948                                                 /* I'm a leader now! Restart a
9949                                                  * switch case.
9950                                                  */
9951                                                 bp->is_leader = 1;
9952                                                 break;
9953                                         }
9954
9955                                         schedule_delayed_work(&bp->sp_rtnl_task,
9956                                                                 HZ/10);
9957                                         return;
9958
9959                                 } else {
9960                                         /*
9961                                          * If there was a global attention, wait
9962                                          * for it to be cleared.
9963                                          */
9964                                         if (bnx2x_reset_is_global(bp)) {
9965                                                 schedule_delayed_work(
9966                                                         &bp->sp_rtnl_task,
9967                                                         HZ/10);
9968                                                 return;
9969                                         }
9970
9971                                         error_recovered =
9972                                           bp->eth_stats.recoverable_error;
9973                                         error_unrecovered =
9974                                           bp->eth_stats.unrecoverable_error;
9975                                         bp->recovery_state =
9976                                                 BNX2X_RECOVERY_NIC_LOADING;
9977                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9978                                                 error_unrecovered++;
9979                                                 netdev_err(bp->dev,
9980                                                            "Recovery failed. Power cycle needed\n");
9981                                                 /* Disconnect this device */
9982                                                 netif_device_detach(bp->dev);
9983                                                 /* Shut down the power */
9984                                                 bnx2x_set_power_state(
9985                                                         bp, PCI_D3hot);
9986                                                 smp_mb();
9987                                         } else {
9988                                                 bp->recovery_state =
9989                                                         BNX2X_RECOVERY_DONE;
9990                                                 error_recovered++;
9991                                                 smp_mb();
9992                                         }
9993                                         bp->eth_stats.recoverable_error =
9994                                                 error_recovered;
9995                                         bp->eth_stats.unrecoverable_error =
9996                                                 error_unrecovered;
9997
9998                                         return;
9999                                 }
10000                         }
10001                 default:
10002                         return;
10003                 }
10004         }
10005 }
10006
10007 static int bnx2x_close(struct net_device *dev);
10008
10009 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10010  * scheduled on a general queue in order to prevent a dead lock.
10011  */
10012 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10013 {
10014         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10015
10016         rtnl_lock();
10017
10018         if (!netif_running(bp->dev)) {
10019                 rtnl_unlock();
10020                 return;
10021         }
10022
10023         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10024 #ifdef BNX2X_STOP_ON_ERROR
10025                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10026                           "you will need to reboot when done\n");
10027                 goto sp_rtnl_not_reset;
10028 #endif
10029                 /*
10030                  * Clear all pending SP commands as we are going to reset the
10031                  * function anyway.
10032                  */
10033                 bp->sp_rtnl_state = 0;
10034                 smp_mb();
10035
10036                 bnx2x_parity_recover(bp);
10037
10038                 rtnl_unlock();
10039                 return;
10040         }
10041
10042         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10043 #ifdef BNX2X_STOP_ON_ERROR
10044                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10045                           "you will need to reboot when done\n");
10046                 goto sp_rtnl_not_reset;
10047 #endif
10048
10049                 /*
10050                  * Clear all pending SP commands as we are going to reset the
10051                  * function anyway.
10052                  */
10053                 bp->sp_rtnl_state = 0;
10054                 smp_mb();
10055
10056                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10057                 bnx2x_nic_load(bp, LOAD_NORMAL);
10058
10059                 rtnl_unlock();
10060                 return;
10061         }
10062 #ifdef BNX2X_STOP_ON_ERROR
10063 sp_rtnl_not_reset:
10064 #endif
10065         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10066                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10067         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10068                 bnx2x_after_function_update(bp);
10069         /*
10070          * in case of fan failure we need to reset id if the "stop on error"
10071          * debug flag is set, since we trying to prevent permanent overheating
10072          * damage
10073          */
10074         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10075                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10076                 netif_device_detach(bp->dev);
10077                 bnx2x_close(bp->dev);
10078                 rtnl_unlock();
10079                 return;
10080         }
10081
10082         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10083                 DP(BNX2X_MSG_SP,
10084                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10085                 bnx2x_vfpf_set_mcast(bp->dev);
10086         }
10087         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10088                                &bp->sp_rtnl_state)){
10089                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10090                         bnx2x_tx_disable(bp);
10091                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10092                 }
10093         }
10094
10095         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10096                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10097                 bnx2x_set_rx_mode_inner(bp);
10098         }
10099
10100         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10101                                &bp->sp_rtnl_state))
10102                 bnx2x_pf_set_vfs_vlan(bp);
10103
10104         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10105                 bnx2x_dcbx_stop_hw_tx(bp);
10106                 bnx2x_dcbx_resume_hw_tx(bp);
10107         }
10108
10109         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10110                                &bp->sp_rtnl_state))
10111                 bnx2x_update_mng_version(bp);
10112
10113         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10114          * can be called from other contexts as well)
10115          */
10116         rtnl_unlock();
10117
10118         /* enable SR-IOV if applicable */
10119         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10120                                                &bp->sp_rtnl_state)) {
10121                 bnx2x_disable_sriov(bp);
10122                 bnx2x_enable_sriov(bp);
10123         }
10124 }
10125
10126 static void bnx2x_period_task(struct work_struct *work)
10127 {
10128         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10129
10130         if (!netif_running(bp->dev))
10131                 goto period_task_exit;
10132
10133         if (CHIP_REV_IS_SLOW(bp)) {
10134                 BNX2X_ERR("period task called on emulation, ignoring\n");
10135                 goto period_task_exit;
10136         }
10137
10138         bnx2x_acquire_phy_lock(bp);
10139         /*
10140          * The barrier is needed to ensure the ordering between the writing to
10141          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10142          * the reading here.
10143          */
10144         smp_mb();
10145         if (bp->port.pmf) {
10146                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10147
10148                 /* Re-queue task in 1 sec */
10149                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10150         }
10151
10152         bnx2x_release_phy_lock(bp);
10153 period_task_exit:
10154         return;
10155 }
10156
10157 /*
10158  * Init service functions
10159  */
10160
10161 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10162 {
10163         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10164         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10165         return base + (BP_ABS_FUNC(bp)) * stride;
10166 }
10167
10168 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10169                                          u8 port, u32 reset_reg,
10170                                          struct bnx2x_mac_vals *vals)
10171 {
10172         u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10173         u32 base_addr;
10174
10175         if (!(mask & reset_reg))
10176                 return false;
10177
10178         BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10179         base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10180         vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10181         vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10182         REG_WR(bp, vals->umac_addr[port], 0);
10183
10184         return true;
10185 }
10186
10187 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10188                                         struct bnx2x_mac_vals *vals)
10189 {
10190         u32 val, base_addr, offset, mask, reset_reg;
10191         bool mac_stopped = false;
10192         u8 port = BP_PORT(bp);
10193
10194         /* reset addresses as they also mark which values were changed */
10195         memset(vals, 0, sizeof(*vals));
10196
10197         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10198
10199         if (!CHIP_IS_E3(bp)) {
10200                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10201                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10202                 if ((mask & reset_reg) && val) {
10203                         u32 wb_data[2];
10204                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10205                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10206                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10207                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10208                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10209
10210                         /*
10211                          * use rd/wr since we cannot use dmae. This is safe
10212                          * since MCP won't access the bus due to the request
10213                          * to unload, and no function on the path can be
10214                          * loaded at this time.
10215                          */
10216                         wb_data[0] = REG_RD(bp, base_addr + offset);
10217                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10218                         vals->bmac_addr = base_addr + offset;
10219                         vals->bmac_val[0] = wb_data[0];
10220                         vals->bmac_val[1] = wb_data[1];
10221                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10222                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10223                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10224                 }
10225                 BNX2X_DEV_INFO("Disable emac Rx\n");
10226                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10227                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10228                 REG_WR(bp, vals->emac_addr, 0);
10229                 mac_stopped = true;
10230         } else {
10231                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10232                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10233                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10234                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10235                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10236                                val & ~(1 << 1));
10237                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10238                                val | (1 << 1));
10239                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10240                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10241                         REG_WR(bp, vals->xmac_addr, 0);
10242                         mac_stopped = true;
10243                 }
10244
10245                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10246                                                             reset_reg, vals);
10247                 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10248                                                             reset_reg, vals);
10249         }
10250
10251         if (mac_stopped)
10252                 msleep(20);
10253 }
10254
10255 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10256 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10257                                         0x1848 + ((f) << 4))
10258 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10259 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10260 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10261
10262 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10263 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10264 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10265
10266 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10267 {
10268         /* UNDI marks its presence in DORQ -
10269          * it initializes CID offset for normal bell to 0x7
10270          */
10271         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10272             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10273                 return false;
10274
10275         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10276                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10277                 return true;
10278         }
10279
10280         return false;
10281 }
10282
10283 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10284 {
10285         u16 rcq, bd;
10286         u32 addr, tmp_reg;
10287
10288         if (BP_FUNC(bp) < 2)
10289                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10290         else
10291                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10292
10293         tmp_reg = REG_RD(bp, addr);
10294         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10295         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10296
10297         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10298         REG_WR(bp, addr, tmp_reg);
10299
10300         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10301                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10302 }
10303
10304 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10305 {
10306         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10307                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10308         if (!rc) {
10309                 BNX2X_ERR("MCP response failure, aborting\n");
10310                 return -EBUSY;
10311         }
10312
10313         return 0;
10314 }
10315
10316 static struct bnx2x_prev_path_list *
10317                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10318 {
10319         struct bnx2x_prev_path_list *tmp_list;
10320
10321         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10322                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10323                     bp->pdev->bus->number == tmp_list->bus &&
10324                     BP_PATH(bp) == tmp_list->path)
10325                         return tmp_list;
10326
10327         return NULL;
10328 }
10329
10330 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10331 {
10332         struct bnx2x_prev_path_list *tmp_list;
10333         int rc;
10334
10335         rc = down_interruptible(&bnx2x_prev_sem);
10336         if (rc) {
10337                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10338                 return rc;
10339         }
10340
10341         tmp_list = bnx2x_prev_path_get_entry(bp);
10342         if (tmp_list) {
10343                 tmp_list->aer = 1;
10344                 rc = 0;
10345         } else {
10346                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10347                           BP_PATH(bp));
10348         }
10349
10350         up(&bnx2x_prev_sem);
10351
10352         return rc;
10353 }
10354
10355 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10356 {
10357         struct bnx2x_prev_path_list *tmp_list;
10358         bool rc = false;
10359
10360         if (down_trylock(&bnx2x_prev_sem))
10361                 return false;
10362
10363         tmp_list = bnx2x_prev_path_get_entry(bp);
10364         if (tmp_list) {
10365                 if (tmp_list->aer) {
10366                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10367                            BP_PATH(bp));
10368                 } else {
10369                         rc = true;
10370                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10371                                        BP_PATH(bp));
10372                 }
10373         }
10374
10375         up(&bnx2x_prev_sem);
10376
10377         return rc;
10378 }
10379
10380 bool bnx2x_port_after_undi(struct bnx2x *bp)
10381 {
10382         struct bnx2x_prev_path_list *entry;
10383         bool val;
10384
10385         down(&bnx2x_prev_sem);
10386
10387         entry = bnx2x_prev_path_get_entry(bp);
10388         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10389
10390         up(&bnx2x_prev_sem);
10391
10392         return val;
10393 }
10394
10395 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10396 {
10397         struct bnx2x_prev_path_list *tmp_list;
10398         int rc;
10399
10400         rc = down_interruptible(&bnx2x_prev_sem);
10401         if (rc) {
10402                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10403                 return rc;
10404         }
10405
10406         /* Check whether the entry for this path already exists */
10407         tmp_list = bnx2x_prev_path_get_entry(bp);
10408         if (tmp_list) {
10409                 if (!tmp_list->aer) {
10410                         BNX2X_ERR("Re-Marking the path.\n");
10411                 } else {
10412                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10413                            BP_PATH(bp));
10414                         tmp_list->aer = 0;
10415                 }
10416                 up(&bnx2x_prev_sem);
10417                 return 0;
10418         }
10419         up(&bnx2x_prev_sem);
10420
10421         /* Create an entry for this path and add it */
10422         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10423         if (!tmp_list) {
10424                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10425                 return -ENOMEM;
10426         }
10427
10428         tmp_list->bus = bp->pdev->bus->number;
10429         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10430         tmp_list->path = BP_PATH(bp);
10431         tmp_list->aer = 0;
10432         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10433
10434         rc = down_interruptible(&bnx2x_prev_sem);
10435         if (rc) {
10436                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10437                 kfree(tmp_list);
10438         } else {
10439                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10440                    BP_PATH(bp));
10441                 list_add(&tmp_list->list, &bnx2x_prev_list);
10442                 up(&bnx2x_prev_sem);
10443         }
10444
10445         return rc;
10446 }
10447
10448 static int bnx2x_do_flr(struct bnx2x *bp)
10449 {
10450         struct pci_dev *dev = bp->pdev;
10451
10452         if (CHIP_IS_E1x(bp)) {
10453                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10454                 return -EINVAL;
10455         }
10456
10457         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10458         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10459                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10460                           bp->common.bc_ver);
10461                 return -EINVAL;
10462         }
10463
10464         if (!pci_wait_for_pending_transaction(dev))
10465                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10466
10467         BNX2X_DEV_INFO("Initiating FLR\n");
10468         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10469
10470         return 0;
10471 }
10472
10473 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10474 {
10475         int rc;
10476
10477         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10478
10479         /* Test if previous unload process was already finished for this path */
10480         if (bnx2x_prev_is_path_marked(bp))
10481                 return bnx2x_prev_mcp_done(bp);
10482
10483         BNX2X_DEV_INFO("Path is unmarked\n");
10484
10485         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10486         if (bnx2x_prev_is_after_undi(bp))
10487                 goto out;
10488
10489         /* If function has FLR capabilities, and existing FW version matches
10490          * the one required, then FLR will be sufficient to clean any residue
10491          * left by previous driver
10492          */
10493         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10494
10495         if (!rc) {
10496                 /* fw version is good */
10497                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10498                 rc = bnx2x_do_flr(bp);
10499         }
10500
10501         if (!rc) {
10502                 /* FLR was performed */
10503                 BNX2X_DEV_INFO("FLR successful\n");
10504                 return 0;
10505         }
10506
10507         BNX2X_DEV_INFO("Could not FLR\n");
10508
10509 out:
10510         /* Close the MCP request, return failure*/
10511         rc = bnx2x_prev_mcp_done(bp);
10512         if (!rc)
10513                 rc = BNX2X_PREV_WAIT_NEEDED;
10514
10515         return rc;
10516 }
10517
10518 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10519 {
10520         u32 reset_reg, tmp_reg = 0, rc;
10521         bool prev_undi = false;
10522         struct bnx2x_mac_vals mac_vals;
10523
10524         /* It is possible a previous function received 'common' answer,
10525          * but hasn't loaded yet, therefore creating a scenario of
10526          * multiple functions receiving 'common' on the same path.
10527          */
10528         BNX2X_DEV_INFO("Common unload Flow\n");
10529
10530         memset(&mac_vals, 0, sizeof(mac_vals));
10531
10532         if (bnx2x_prev_is_path_marked(bp))
10533                 return bnx2x_prev_mcp_done(bp);
10534
10535         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10536
10537         /* Reset should be performed after BRB is emptied */
10538         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10539                 u32 timer_count = 1000;
10540
10541                 /* Close the MAC Rx to prevent BRB from filling up */
10542                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10543
10544                 /* close LLH filters for both ports towards the BRB */
10545                 bnx2x_set_rx_filter(&bp->link_params, 0);
10546                 bp->link_params.port ^= 1;
10547                 bnx2x_set_rx_filter(&bp->link_params, 0);
10548                 bp->link_params.port ^= 1;
10549
10550                 /* Check if the UNDI driver was previously loaded */
10551                 if (bnx2x_prev_is_after_undi(bp)) {
10552                         prev_undi = true;
10553                         /* clear the UNDI indication */
10554                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10555                         /* clear possible idle check errors */
10556                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10557                 }
10558                 if (!CHIP_IS_E1x(bp))
10559                         /* block FW from writing to host */
10560                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10561
10562                 /* wait until BRB is empty */
10563                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10564                 while (timer_count) {
10565                         u32 prev_brb = tmp_reg;
10566
10567                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10568                         if (!tmp_reg)
10569                                 break;
10570
10571                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10572
10573                         /* reset timer as long as BRB actually gets emptied */
10574                         if (prev_brb > tmp_reg)
10575                                 timer_count = 1000;
10576                         else
10577                                 timer_count--;
10578
10579                         /* If UNDI resides in memory, manually increment it */
10580                         if (prev_undi)
10581                                 bnx2x_prev_unload_undi_inc(bp, 1);
10582
10583                         udelay(10);
10584                 }
10585
10586                 if (!timer_count)
10587                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10588         }
10589
10590         /* No packets are in the pipeline, path is ready for reset */
10591         bnx2x_reset_common(bp);
10592
10593         if (mac_vals.xmac_addr)
10594                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10595         if (mac_vals.umac_addr[0])
10596                 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10597         if (mac_vals.umac_addr[1])
10598                 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10599         if (mac_vals.emac_addr)
10600                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10601         if (mac_vals.bmac_addr) {
10602                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10603                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10604         }
10605
10606         rc = bnx2x_prev_mark_path(bp, prev_undi);
10607         if (rc) {
10608                 bnx2x_prev_mcp_done(bp);
10609                 return rc;
10610         }
10611
10612         return bnx2x_prev_mcp_done(bp);
10613 }
10614
10615 static int bnx2x_prev_unload(struct bnx2x *bp)
10616 {
10617         int time_counter = 10;
10618         u32 rc, fw, hw_lock_reg, hw_lock_val;
10619         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10620
10621         /* clear hw from errors which may have resulted from an interrupted
10622          * dmae transaction.
10623          */
10624         bnx2x_clean_pglue_errors(bp);
10625
10626         /* Release previously held locks */
10627         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10628                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10629                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10630
10631         hw_lock_val = REG_RD(bp, hw_lock_reg);
10632         if (hw_lock_val) {
10633                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10634                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10635                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10636                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10637                 }
10638
10639                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10640                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10641         } else
10642                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10643
10644         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10645                 BNX2X_DEV_INFO("Release previously held alr\n");
10646                 bnx2x_release_alr(bp);
10647         }
10648
10649         do {
10650                 int aer = 0;
10651                 /* Lock MCP using an unload request */
10652                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10653                 if (!fw) {
10654                         BNX2X_ERR("MCP response failure, aborting\n");
10655                         rc = -EBUSY;
10656                         break;
10657                 }
10658
10659                 rc = down_interruptible(&bnx2x_prev_sem);
10660                 if (rc) {
10661                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10662                                   rc);
10663                 } else {
10664                         /* If Path is marked by EEH, ignore unload status */
10665                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10666                                  bnx2x_prev_path_get_entry(bp)->aer);
10667                         up(&bnx2x_prev_sem);
10668                 }
10669
10670                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10671                         rc = bnx2x_prev_unload_common(bp);
10672                         break;
10673                 }
10674
10675                 /* non-common reply from MCP might require looping */
10676                 rc = bnx2x_prev_unload_uncommon(bp);
10677                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10678                         break;
10679
10680                 msleep(20);
10681         } while (--time_counter);
10682
10683         if (!time_counter || rc) {
10684                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10685                 rc = -EPROBE_DEFER;
10686         }
10687
10688         /* Mark function if its port was used to boot from SAN */
10689         if (bnx2x_port_after_undi(bp))
10690                 bp->link_params.feature_config_flags |=
10691                         FEATURE_CONFIG_BOOT_FROM_SAN;
10692
10693         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10694
10695         return rc;
10696 }
10697
10698 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10699 {
10700         u32 val, val2, val3, val4, id, boot_mode;
10701         u16 pmc;
10702
10703         /* Get the chip revision id and number. */
10704         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10705         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10706         id = ((val & 0xffff) << 16);
10707         val = REG_RD(bp, MISC_REG_CHIP_REV);
10708         id |= ((val & 0xf) << 12);
10709
10710         /* Metal is read from PCI regs, but we can't access >=0x400 from
10711          * the configuration space (so we need to reg_rd)
10712          */
10713         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10714         id |= (((val >> 24) & 0xf) << 4);
10715         val = REG_RD(bp, MISC_REG_BOND_ID);
10716         id |= (val & 0xf);
10717         bp->common.chip_id = id;
10718
10719         /* force 57811 according to MISC register */
10720         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10721                 if (CHIP_IS_57810(bp))
10722                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10723                                 (bp->common.chip_id & 0x0000FFFF);
10724                 else if (CHIP_IS_57810_MF(bp))
10725                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10726                                 (bp->common.chip_id & 0x0000FFFF);
10727                 bp->common.chip_id |= 0x1;
10728         }
10729
10730         /* Set doorbell size */
10731         bp->db_size = (1 << BNX2X_DB_SHIFT);
10732
10733         if (!CHIP_IS_E1x(bp)) {
10734                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10735                 if ((val & 1) == 0)
10736                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10737                 else
10738                         val = (val >> 1) & 1;
10739                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10740                                                        "2_PORT_MODE");
10741                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10742                                                  CHIP_2_PORT_MODE;
10743
10744                 if (CHIP_MODE_IS_4_PORT(bp))
10745                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10746                 else
10747                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10748         } else {
10749                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10750                 bp->pfid = bp->pf_num;                  /* 0..7 */
10751         }
10752
10753         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10754
10755         bp->link_params.chip_id = bp->common.chip_id;
10756         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10757
10758         val = (REG_RD(bp, 0x2874) & 0x55);
10759         if ((bp->common.chip_id & 0x1) ||
10760             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10761                 bp->flags |= ONE_PORT_FLAG;
10762                 BNX2X_DEV_INFO("single port device\n");
10763         }
10764
10765         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10766         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10767                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10768         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10769                        bp->common.flash_size, bp->common.flash_size);
10770
10771         bnx2x_init_shmem(bp);
10772
10773         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10774                                         MISC_REG_GENERIC_CR_1 :
10775                                         MISC_REG_GENERIC_CR_0));
10776
10777         bp->link_params.shmem_base = bp->common.shmem_base;
10778         bp->link_params.shmem2_base = bp->common.shmem2_base;
10779         if (SHMEM2_RD(bp, size) >
10780             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10781                 bp->link_params.lfa_base =
10782                 REG_RD(bp, bp->common.shmem2_base +
10783                        (u32)offsetof(struct shmem2_region,
10784                                      lfa_host_addr[BP_PORT(bp)]));
10785         else
10786                 bp->link_params.lfa_base = 0;
10787         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10788                        bp->common.shmem_base, bp->common.shmem2_base);
10789
10790         if (!bp->common.shmem_base) {
10791                 BNX2X_DEV_INFO("MCP not active\n");
10792                 bp->flags |= NO_MCP_FLAG;
10793                 return;
10794         }
10795
10796         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10797         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10798
10799         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10800                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10801                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10802
10803         bp->link_params.feature_config_flags = 0;
10804         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10805         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10806                 bp->link_params.feature_config_flags |=
10807                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10808         else
10809                 bp->link_params.feature_config_flags &=
10810                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10811
10812         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10813         bp->common.bc_ver = val;
10814         BNX2X_DEV_INFO("bc_ver %X\n", val);
10815         if (val < BNX2X_BC_VER) {
10816                 /* for now only warn
10817                  * later we might need to enforce this */
10818                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10819                           BNX2X_BC_VER, val);
10820         }
10821         bp->link_params.feature_config_flags |=
10822                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10823                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10824
10825         bp->link_params.feature_config_flags |=
10826                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10827                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10828         bp->link_params.feature_config_flags |=
10829                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10830                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10831         bp->link_params.feature_config_flags |=
10832                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10833                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10834
10835         bp->link_params.feature_config_flags |=
10836                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10837                 FEATURE_CONFIG_MT_SUPPORT : 0;
10838
10839         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10840                         BC_SUPPORTS_PFC_STATS : 0;
10841
10842         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10843                         BC_SUPPORTS_FCOE_FEATURES : 0;
10844
10845         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10846                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10847
10848         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10849                         BC_SUPPORTS_RMMOD_CMD : 0;
10850
10851         boot_mode = SHMEM_RD(bp,
10852                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10853                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10854         switch (boot_mode) {
10855         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10856                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10857                 break;
10858         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10859                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10860                 break;
10861         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10862                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10863                 break;
10864         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10865                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10866                 break;
10867         }
10868
10869         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10870         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10871
10872         BNX2X_DEV_INFO("%sWoL capable\n",
10873                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10874
10875         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10876         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10877         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10878         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10879
10880         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10881                  val, val2, val3, val4);
10882 }
10883
10884 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10885 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10886
10887 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10888 {
10889         int pfid = BP_FUNC(bp);
10890         int igu_sb_id;
10891         u32 val;
10892         u8 fid, igu_sb_cnt = 0;
10893
10894         bp->igu_base_sb = 0xff;
10895         if (CHIP_INT_MODE_IS_BC(bp)) {
10896                 int vn = BP_VN(bp);
10897                 igu_sb_cnt = bp->igu_sb_cnt;
10898                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10899                         FP_SB_MAX_E1x;
10900
10901                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10902                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10903
10904                 return 0;
10905         }
10906
10907         /* IGU in normal mode - read CAM */
10908         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10909              igu_sb_id++) {
10910                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10911                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10912                         continue;
10913                 fid = IGU_FID(val);
10914                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10915                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10916                                 continue;
10917                         if (IGU_VEC(val) == 0)
10918                                 /* default status block */
10919                                 bp->igu_dsb_id = igu_sb_id;
10920                         else {
10921                                 if (bp->igu_base_sb == 0xff)
10922                                         bp->igu_base_sb = igu_sb_id;
10923                                 igu_sb_cnt++;
10924                         }
10925                 }
10926         }
10927
10928 #ifdef CONFIG_PCI_MSI
10929         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10930          * optional that number of CAM entries will not be equal to the value
10931          * advertised in PCI.
10932          * Driver should use the minimal value of both as the actual status
10933          * block count
10934          */
10935         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10936 #endif
10937
10938         if (igu_sb_cnt == 0) {
10939                 BNX2X_ERR("CAM configuration error\n");
10940                 return -EINVAL;
10941         }
10942
10943         return 0;
10944 }
10945
10946 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10947 {
10948         int cfg_size = 0, idx, port = BP_PORT(bp);
10949
10950         /* Aggregation of supported attributes of all external phys */
10951         bp->port.supported[0] = 0;
10952         bp->port.supported[1] = 0;
10953         switch (bp->link_params.num_phys) {
10954         case 1:
10955                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10956                 cfg_size = 1;
10957                 break;
10958         case 2:
10959                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10960                 cfg_size = 1;
10961                 break;
10962         case 3:
10963                 if (bp->link_params.multi_phy_config &
10964                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10965                         bp->port.supported[1] =
10966                                 bp->link_params.phy[EXT_PHY1].supported;
10967                         bp->port.supported[0] =
10968                                 bp->link_params.phy[EXT_PHY2].supported;
10969                 } else {
10970                         bp->port.supported[0] =
10971                                 bp->link_params.phy[EXT_PHY1].supported;
10972                         bp->port.supported[1] =
10973                                 bp->link_params.phy[EXT_PHY2].supported;
10974                 }
10975                 cfg_size = 2;
10976                 break;
10977         }
10978
10979         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10980                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10981                            SHMEM_RD(bp,
10982                            dev_info.port_hw_config[port].external_phy_config),
10983                            SHMEM_RD(bp,
10984                            dev_info.port_hw_config[port].external_phy_config2));
10985                         return;
10986         }
10987
10988         if (CHIP_IS_E3(bp))
10989                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10990         else {
10991                 switch (switch_cfg) {
10992                 case SWITCH_CFG_1G:
10993                         bp->port.phy_addr = REG_RD(
10994                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10995                         break;
10996                 case SWITCH_CFG_10G:
10997                         bp->port.phy_addr = REG_RD(
10998                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10999                         break;
11000                 default:
11001                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11002                                   bp->port.link_config[0]);
11003                         return;
11004                 }
11005         }
11006         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11007         /* mask what we support according to speed_cap_mask per configuration */
11008         for (idx = 0; idx < cfg_size; idx++) {
11009                 if (!(bp->link_params.speed_cap_mask[idx] &
11010                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11011                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11012
11013                 if (!(bp->link_params.speed_cap_mask[idx] &
11014                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11015                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11016
11017                 if (!(bp->link_params.speed_cap_mask[idx] &
11018                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11019                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11020
11021                 if (!(bp->link_params.speed_cap_mask[idx] &
11022                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11023                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11024
11025                 if (!(bp->link_params.speed_cap_mask[idx] &
11026                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11027                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11028                                                      SUPPORTED_1000baseT_Full);
11029
11030                 if (!(bp->link_params.speed_cap_mask[idx] &
11031                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11032                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11033
11034                 if (!(bp->link_params.speed_cap_mask[idx] &
11035                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11036                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11037
11038                 if (!(bp->link_params.speed_cap_mask[idx] &
11039                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11040                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11041         }
11042
11043         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11044                        bp->port.supported[1]);
11045 }
11046
11047 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11048 {
11049         u32 link_config, idx, cfg_size = 0;
11050         bp->port.advertising[0] = 0;
11051         bp->port.advertising[1] = 0;
11052         switch (bp->link_params.num_phys) {
11053         case 1:
11054         case 2:
11055                 cfg_size = 1;
11056                 break;
11057         case 3:
11058                 cfg_size = 2;
11059                 break;
11060         }
11061         for (idx = 0; idx < cfg_size; idx++) {
11062                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11063                 link_config = bp->port.link_config[idx];
11064                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11065                 case PORT_FEATURE_LINK_SPEED_AUTO:
11066                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11067                                 bp->link_params.req_line_speed[idx] =
11068                                         SPEED_AUTO_NEG;
11069                                 bp->port.advertising[idx] |=
11070                                         bp->port.supported[idx];
11071                                 if (bp->link_params.phy[EXT_PHY1].type ==
11072                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11073                                         bp->port.advertising[idx] |=
11074                                         (SUPPORTED_100baseT_Half |
11075                                          SUPPORTED_100baseT_Full);
11076                         } else {
11077                                 /* force 10G, no AN */
11078                                 bp->link_params.req_line_speed[idx] =
11079                                         SPEED_10000;
11080                                 bp->port.advertising[idx] |=
11081                                         (ADVERTISED_10000baseT_Full |
11082                                          ADVERTISED_FIBRE);
11083                                 continue;
11084                         }
11085                         break;
11086
11087                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11088                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11089                                 bp->link_params.req_line_speed[idx] =
11090                                         SPEED_10;
11091                                 bp->port.advertising[idx] |=
11092                                         (ADVERTISED_10baseT_Full |
11093                                          ADVERTISED_TP);
11094                         } else {
11095                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11096                                             link_config,
11097                                     bp->link_params.speed_cap_mask[idx]);
11098                                 return;
11099                         }
11100                         break;
11101
11102                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11103                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11104                                 bp->link_params.req_line_speed[idx] =
11105                                         SPEED_10;
11106                                 bp->link_params.req_duplex[idx] =
11107                                         DUPLEX_HALF;
11108                                 bp->port.advertising[idx] |=
11109                                         (ADVERTISED_10baseT_Half |
11110                                          ADVERTISED_TP);
11111                         } else {
11112                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11113                                             link_config,
11114                                           bp->link_params.speed_cap_mask[idx]);
11115                                 return;
11116                         }
11117                         break;
11118
11119                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11120                         if (bp->port.supported[idx] &
11121                             SUPPORTED_100baseT_Full) {
11122                                 bp->link_params.req_line_speed[idx] =
11123                                         SPEED_100;
11124                                 bp->port.advertising[idx] |=
11125                                         (ADVERTISED_100baseT_Full |
11126                                          ADVERTISED_TP);
11127                         } else {
11128                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11129                                             link_config,
11130                                           bp->link_params.speed_cap_mask[idx]);
11131                                 return;
11132                         }
11133                         break;
11134
11135                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11136                         if (bp->port.supported[idx] &
11137                             SUPPORTED_100baseT_Half) {
11138                                 bp->link_params.req_line_speed[idx] =
11139                                                                 SPEED_100;
11140                                 bp->link_params.req_duplex[idx] =
11141                                                                 DUPLEX_HALF;
11142                                 bp->port.advertising[idx] |=
11143                                         (ADVERTISED_100baseT_Half |
11144                                          ADVERTISED_TP);
11145                         } else {
11146                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11147                                     link_config,
11148                                     bp->link_params.speed_cap_mask[idx]);
11149                                 return;
11150                         }
11151                         break;
11152
11153                 case PORT_FEATURE_LINK_SPEED_1G:
11154                         if (bp->port.supported[idx] &
11155                             SUPPORTED_1000baseT_Full) {
11156                                 bp->link_params.req_line_speed[idx] =
11157                                         SPEED_1000;
11158                                 bp->port.advertising[idx] |=
11159                                         (ADVERTISED_1000baseT_Full |
11160                                          ADVERTISED_TP);
11161                         } else if (bp->port.supported[idx] &
11162                                    SUPPORTED_1000baseKX_Full) {
11163                                 bp->link_params.req_line_speed[idx] =
11164                                         SPEED_1000;
11165                                 bp->port.advertising[idx] |=
11166                                         ADVERTISED_1000baseKX_Full;
11167                         } else {
11168                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11169                                     link_config,
11170                                     bp->link_params.speed_cap_mask[idx]);
11171                                 return;
11172                         }
11173                         break;
11174
11175                 case PORT_FEATURE_LINK_SPEED_2_5G:
11176                         if (bp->port.supported[idx] &
11177                             SUPPORTED_2500baseX_Full) {
11178                                 bp->link_params.req_line_speed[idx] =
11179                                         SPEED_2500;
11180                                 bp->port.advertising[idx] |=
11181                                         (ADVERTISED_2500baseX_Full |
11182                                                 ADVERTISED_TP);
11183                         } else {
11184                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11185                                     link_config,
11186                                     bp->link_params.speed_cap_mask[idx]);
11187                                 return;
11188                         }
11189                         break;
11190
11191                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11192                         if (bp->port.supported[idx] &
11193                             SUPPORTED_10000baseT_Full) {
11194                                 bp->link_params.req_line_speed[idx] =
11195                                         SPEED_10000;
11196                                 bp->port.advertising[idx] |=
11197                                         (ADVERTISED_10000baseT_Full |
11198                                                 ADVERTISED_FIBRE);
11199                         } else if (bp->port.supported[idx] &
11200                                    SUPPORTED_10000baseKR_Full) {
11201                                 bp->link_params.req_line_speed[idx] =
11202                                         SPEED_10000;
11203                                 bp->port.advertising[idx] |=
11204                                         (ADVERTISED_10000baseKR_Full |
11205                                                 ADVERTISED_FIBRE);
11206                         } else {
11207                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11208                                     link_config,
11209                                     bp->link_params.speed_cap_mask[idx]);
11210                                 return;
11211                         }
11212                         break;
11213                 case PORT_FEATURE_LINK_SPEED_20G:
11214                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11215
11216                         break;
11217                 default:
11218                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11219                                   link_config);
11220                                 bp->link_params.req_line_speed[idx] =
11221                                                         SPEED_AUTO_NEG;
11222                                 bp->port.advertising[idx] =
11223                                                 bp->port.supported[idx];
11224                         break;
11225                 }
11226
11227                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11228                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11229                 if (bp->link_params.req_flow_ctrl[idx] ==
11230                     BNX2X_FLOW_CTRL_AUTO) {
11231                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11232                                 bp->link_params.req_flow_ctrl[idx] =
11233                                                         BNX2X_FLOW_CTRL_NONE;
11234                         else
11235                                 bnx2x_set_requested_fc(bp);
11236                 }
11237
11238                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11239                                bp->link_params.req_line_speed[idx],
11240                                bp->link_params.req_duplex[idx],
11241                                bp->link_params.req_flow_ctrl[idx],
11242                                bp->port.advertising[idx]);
11243         }
11244 }
11245
11246 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11247 {
11248         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11249         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11250         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11251         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11252 }
11253
11254 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11255 {
11256         int port = BP_PORT(bp);
11257         u32 config;
11258         u32 ext_phy_type, ext_phy_config, eee_mode;
11259
11260         bp->link_params.bp = bp;
11261         bp->link_params.port = port;
11262
11263         bp->link_params.lane_config =
11264                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11265
11266         bp->link_params.speed_cap_mask[0] =
11267                 SHMEM_RD(bp,
11268                          dev_info.port_hw_config[port].speed_capability_mask) &
11269                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11270         bp->link_params.speed_cap_mask[1] =
11271                 SHMEM_RD(bp,
11272                          dev_info.port_hw_config[port].speed_capability_mask2) &
11273                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11274         bp->port.link_config[0] =
11275                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11276
11277         bp->port.link_config[1] =
11278                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11279
11280         bp->link_params.multi_phy_config =
11281                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11282         /* If the device is capable of WoL, set the default state according
11283          * to the HW
11284          */
11285         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11286         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11287                    (config & PORT_FEATURE_WOL_ENABLED));
11288
11289         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11290             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11291                 bp->flags |= NO_ISCSI_FLAG;
11292         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11293             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11294                 bp->flags |= NO_FCOE_FLAG;
11295
11296         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11297                        bp->link_params.lane_config,
11298                        bp->link_params.speed_cap_mask[0],
11299                        bp->port.link_config[0]);
11300
11301         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11302                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11303         bnx2x_phy_probe(&bp->link_params);
11304         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11305
11306         bnx2x_link_settings_requested(bp);
11307
11308         /*
11309          * If connected directly, work with the internal PHY, otherwise, work
11310          * with the external PHY
11311          */
11312         ext_phy_config =
11313                 SHMEM_RD(bp,
11314                          dev_info.port_hw_config[port].external_phy_config);
11315         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11316         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11317                 bp->mdio.prtad = bp->port.phy_addr;
11318
11319         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11320                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11321                 bp->mdio.prtad =
11322                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11323
11324         /* Configure link feature according to nvram value */
11325         eee_mode = (((SHMEM_RD(bp, dev_info.
11326                       port_feature_config[port].eee_power_mode)) &
11327                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11328                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11329         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11330                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11331                                            EEE_MODE_ENABLE_LPI |
11332                                            EEE_MODE_OUTPUT_TIME;
11333         } else {
11334                 bp->link_params.eee_mode = 0;
11335         }
11336 }
11337
11338 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11339 {
11340         u32 no_flags = NO_ISCSI_FLAG;
11341         int port = BP_PORT(bp);
11342         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11343                                 drv_lic_key[port].max_iscsi_conn);
11344
11345         if (!CNIC_SUPPORT(bp)) {
11346                 bp->flags |= no_flags;
11347                 return;
11348         }
11349
11350         /* Get the number of maximum allowed iSCSI connections */
11351         bp->cnic_eth_dev.max_iscsi_conn =
11352                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11353                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11354
11355         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11356                        bp->cnic_eth_dev.max_iscsi_conn);
11357
11358         /*
11359          * If maximum allowed number of connections is zero -
11360          * disable the feature.
11361          */
11362         if (!bp->cnic_eth_dev.max_iscsi_conn)
11363                 bp->flags |= no_flags;
11364 }
11365
11366 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11367 {
11368         /* Port info */
11369         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11370                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11371         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11372                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11373
11374         /* Node info */
11375         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11376                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11377         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11378                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11379 }
11380
11381 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11382 {
11383         u8 count = 0;
11384
11385         if (IS_MF(bp)) {
11386                 u8 fid;
11387
11388                 /* iterate over absolute function ids for this path: */
11389                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11390                         if (IS_MF_SD(bp)) {
11391                                 u32 cfg = MF_CFG_RD(bp,
11392                                                     func_mf_config[fid].config);
11393
11394                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11395                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11396                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11397                                         count++;
11398                         } else {
11399                                 u32 cfg = MF_CFG_RD(bp,
11400                                                     func_ext_config[fid].
11401                                                                       func_cfg);
11402
11403                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11404                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11405                                         count++;
11406                         }
11407                 }
11408         } else { /* SF */
11409                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11410
11411                 for (port = 0; port < port_cnt; port++) {
11412                         u32 lic = SHMEM_RD(bp,
11413                                            drv_lic_key[port].max_fcoe_conn) ^
11414                                   FW_ENCODE_32BIT_PATTERN;
11415                         if (lic)
11416                                 count++;
11417                 }
11418         }
11419
11420         return count;
11421 }
11422
11423 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11424 {
11425         int port = BP_PORT(bp);
11426         int func = BP_ABS_FUNC(bp);
11427         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11428                                 drv_lic_key[port].max_fcoe_conn);
11429         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11430
11431         if (!CNIC_SUPPORT(bp)) {
11432                 bp->flags |= NO_FCOE_FLAG;
11433                 return;
11434         }
11435
11436         /* Get the number of maximum allowed FCoE connections */
11437         bp->cnic_eth_dev.max_fcoe_conn =
11438                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11439                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11440
11441         /* Calculate the number of maximum allowed FCoE tasks */
11442         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11443
11444         /* check if FCoE resources must be shared between different functions */
11445         if (num_fcoe_func)
11446                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11447
11448         /* Read the WWN: */
11449         if (!IS_MF(bp)) {
11450                 /* Port info */
11451                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11452                         SHMEM_RD(bp,
11453                                  dev_info.port_hw_config[port].
11454                                  fcoe_wwn_port_name_upper);
11455                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11456                         SHMEM_RD(bp,
11457                                  dev_info.port_hw_config[port].
11458                                  fcoe_wwn_port_name_lower);
11459
11460                 /* Node info */
11461                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11462                         SHMEM_RD(bp,
11463                                  dev_info.port_hw_config[port].
11464                                  fcoe_wwn_node_name_upper);
11465                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11466                         SHMEM_RD(bp,
11467                                  dev_info.port_hw_config[port].
11468                                  fcoe_wwn_node_name_lower);
11469         } else if (!IS_MF_SD(bp)) {
11470                 /* Read the WWN info only if the FCoE feature is enabled for
11471                  * this function.
11472                  */
11473                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11474                         bnx2x_get_ext_wwn_info(bp, func);
11475         } else {
11476                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11477                         bnx2x_get_ext_wwn_info(bp, func);
11478         }
11479
11480         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11481
11482         /*
11483          * If maximum allowed number of connections is zero -
11484          * disable the feature.
11485          */
11486         if (!bp->cnic_eth_dev.max_fcoe_conn)
11487                 bp->flags |= NO_FCOE_FLAG;
11488 }
11489
11490 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11491 {
11492         /*
11493          * iSCSI may be dynamically disabled but reading
11494          * info here we will decrease memory usage by driver
11495          * if the feature is disabled for good
11496          */
11497         bnx2x_get_iscsi_info(bp);
11498         bnx2x_get_fcoe_info(bp);
11499 }
11500
11501 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11502 {
11503         u32 val, val2;
11504         int func = BP_ABS_FUNC(bp);
11505         int port = BP_PORT(bp);
11506         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11507         u8 *fip_mac = bp->fip_mac;
11508
11509         if (IS_MF(bp)) {
11510                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11511                  * FCoE MAC then the appropriate feature should be disabled.
11512                  * In non SD mode features configuration comes from struct
11513                  * func_ext_config.
11514                  */
11515                 if (!IS_MF_SD(bp)) {
11516                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11517                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11518                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11519                                                  iscsi_mac_addr_upper);
11520                                 val = MF_CFG_RD(bp, func_ext_config[func].
11521                                                 iscsi_mac_addr_lower);
11522                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11523                                 BNX2X_DEV_INFO
11524                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11525                         } else {
11526                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11527                         }
11528
11529                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11530                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11531                                                  fcoe_mac_addr_upper);
11532                                 val = MF_CFG_RD(bp, func_ext_config[func].
11533                                                 fcoe_mac_addr_lower);
11534                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11535                                 BNX2X_DEV_INFO
11536                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11537                         } else {
11538                                 bp->flags |= NO_FCOE_FLAG;
11539                         }
11540
11541                         bp->mf_ext_config = cfg;
11542
11543                 } else { /* SD MODE */
11544                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11545                                 /* use primary mac as iscsi mac */
11546                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11547
11548                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11549                                 BNX2X_DEV_INFO
11550                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11551                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11552                                 /* use primary mac as fip mac */
11553                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11554                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11555                                 BNX2X_DEV_INFO
11556                                         ("Read FIP MAC: %pM\n", fip_mac);
11557                         }
11558                 }
11559
11560                 /* If this is a storage-only interface, use SAN mac as
11561                  * primary MAC. Notice that for SD this is already the case,
11562                  * as the SAN mac was copied from the primary MAC.
11563                  */
11564                 if (IS_MF_FCOE_AFEX(bp))
11565                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11566         } else {
11567                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11568                                 iscsi_mac_upper);
11569                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11570                                iscsi_mac_lower);
11571                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11572
11573                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11574                                 fcoe_fip_mac_upper);
11575                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11576                                fcoe_fip_mac_lower);
11577                 bnx2x_set_mac_buf(fip_mac, val, val2);
11578         }
11579
11580         /* Disable iSCSI OOO if MAC configuration is invalid. */
11581         if (!is_valid_ether_addr(iscsi_mac)) {
11582                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11583                 eth_zero_addr(iscsi_mac);
11584         }
11585
11586         /* Disable FCoE if MAC configuration is invalid. */
11587         if (!is_valid_ether_addr(fip_mac)) {
11588                 bp->flags |= NO_FCOE_FLAG;
11589                 eth_zero_addr(bp->fip_mac);
11590         }
11591 }
11592
11593 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11594 {
11595         u32 val, val2;
11596         int func = BP_ABS_FUNC(bp);
11597         int port = BP_PORT(bp);
11598
11599         /* Zero primary MAC configuration */
11600         eth_zero_addr(bp->dev->dev_addr);
11601
11602         if (BP_NOMCP(bp)) {
11603                 BNX2X_ERROR("warning: random MAC workaround active\n");
11604                 eth_hw_addr_random(bp->dev);
11605         } else if (IS_MF(bp)) {
11606                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11607                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11608                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11609                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11610                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11611
11612                 if (CNIC_SUPPORT(bp))
11613                         bnx2x_get_cnic_mac_hwinfo(bp);
11614         } else {
11615                 /* in SF read MACs from port configuration */
11616                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11617                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11618                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11619
11620                 if (CNIC_SUPPORT(bp))
11621                         bnx2x_get_cnic_mac_hwinfo(bp);
11622         }
11623
11624         if (!BP_NOMCP(bp)) {
11625                 /* Read physical port identifier from shmem */
11626                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11627                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11628                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11629                 bp->flags |= HAS_PHYS_PORT_ID;
11630         }
11631
11632         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11633
11634         if (!is_valid_ether_addr(bp->dev->dev_addr))
11635                 dev_err(&bp->pdev->dev,
11636                         "bad Ethernet MAC address configuration: %pM\n"
11637                         "change it manually before bringing up the appropriate network interface\n",
11638                         bp->dev->dev_addr);
11639 }
11640
11641 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11642 {
11643         int tmp;
11644         u32 cfg;
11645
11646         if (IS_VF(bp))
11647                 return false;
11648
11649         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11650                 /* Take function: tmp = func */
11651                 tmp = BP_ABS_FUNC(bp);
11652                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11653                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11654         } else {
11655                 /* Take port: tmp = port */
11656                 tmp = BP_PORT(bp);
11657                 cfg = SHMEM_RD(bp,
11658                                dev_info.port_hw_config[tmp].generic_features);
11659                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11660         }
11661         return cfg;
11662 }
11663
11664 static void validate_set_si_mode(struct bnx2x *bp)
11665 {
11666         u8 func = BP_ABS_FUNC(bp);
11667         u32 val;
11668
11669         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11670
11671         /* check for legal mac (upper bytes) */
11672         if (val != 0xffff) {
11673                 bp->mf_mode = MULTI_FUNCTION_SI;
11674                 bp->mf_config[BP_VN(bp)] =
11675                         MF_CFG_RD(bp, func_mf_config[func].config);
11676         } else
11677                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11678 }
11679
11680 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11681 {
11682         int /*abs*/func = BP_ABS_FUNC(bp);
11683         int vn;
11684         u32 val = 0, val2 = 0;
11685         int rc = 0;
11686
11687         /* Validate that chip access is feasible */
11688         if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11689                 dev_err(&bp->pdev->dev,
11690                         "Chip read returns all Fs. Preventing probe from continuing\n");
11691                 return -EINVAL;
11692         }
11693
11694         bnx2x_get_common_hwinfo(bp);
11695
11696         /*
11697          * initialize IGU parameters
11698          */
11699         if (CHIP_IS_E1x(bp)) {
11700                 bp->common.int_block = INT_BLOCK_HC;
11701
11702                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11703                 bp->igu_base_sb = 0;
11704         } else {
11705                 bp->common.int_block = INT_BLOCK_IGU;
11706
11707                 /* do not allow device reset during IGU info processing */
11708                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11709
11710                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11711
11712                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11713                         int tout = 5000;
11714
11715                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11716
11717                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11718                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11719                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11720
11721                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11722                                 tout--;
11723                                 usleep_range(1000, 2000);
11724                         }
11725
11726                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11727                                 dev_err(&bp->pdev->dev,
11728                                         "FORCING Normal Mode failed!!!\n");
11729                                 bnx2x_release_hw_lock(bp,
11730                                                       HW_LOCK_RESOURCE_RESET);
11731                                 return -EPERM;
11732                         }
11733                 }
11734
11735                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11736                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11737                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11738                 } else
11739                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11740
11741                 rc = bnx2x_get_igu_cam_info(bp);
11742                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11743                 if (rc)
11744                         return rc;
11745         }
11746
11747         /*
11748          * set base FW non-default (fast path) status block id, this value is
11749          * used to initialize the fw_sb_id saved on the fp/queue structure to
11750          * determine the id used by the FW.
11751          */
11752         if (CHIP_IS_E1x(bp))
11753                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11754         else /*
11755               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11756               * the same queue are indicated on the same IGU SB). So we prefer
11757               * FW and IGU SBs to be the same value.
11758               */
11759                 bp->base_fw_ndsb = bp->igu_base_sb;
11760
11761         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11762                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11763                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11764
11765         /*
11766          * Initialize MF configuration
11767          */
11768
11769         bp->mf_ov = 0;
11770         bp->mf_mode = 0;
11771         bp->mf_sub_mode = 0;
11772         vn = BP_VN(bp);
11773
11774         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11775                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11776                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11777                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11778
11779                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11780                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11781                 else
11782                         bp->common.mf_cfg_base = bp->common.shmem_base +
11783                                 offsetof(struct shmem_region, func_mb) +
11784                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11785                 /*
11786                  * get mf configuration:
11787                  * 1. Existence of MF configuration
11788                  * 2. MAC address must be legal (check only upper bytes)
11789                  *    for  Switch-Independent mode;
11790                  *    OVLAN must be legal for Switch-Dependent mode
11791                  * 3. SF_MODE configures specific MF mode
11792                  */
11793                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11794                         /* get mf configuration */
11795                         val = SHMEM_RD(bp,
11796                                        dev_info.shared_feature_config.config);
11797                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11798
11799                         switch (val) {
11800                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11801                                 validate_set_si_mode(bp);
11802                                 break;
11803                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11804                                 if ((!CHIP_IS_E1x(bp)) &&
11805                                     (MF_CFG_RD(bp, func_mf_config[func].
11806                                                mac_upper) != 0xffff) &&
11807                                     (SHMEM2_HAS(bp,
11808                                                 afex_driver_support))) {
11809                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11810                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11811                                                 func_mf_config[func].config);
11812                                 } else {
11813                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11814                                 }
11815                                 break;
11816                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11817                                 /* get OV configuration */
11818                                 val = MF_CFG_RD(bp,
11819                                         func_mf_config[FUNC_0].e1hov_tag);
11820                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11821
11822                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11823                                         bp->mf_mode = MULTI_FUNCTION_SD;
11824                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11825                                                 func_mf_config[func].config);
11826                                 } else
11827                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11828                                 break;
11829                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
11830                                 bp->mf_mode = MULTI_FUNCTION_SD;
11831                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
11832                                 bp->mf_config[vn] =
11833                                         MF_CFG_RD(bp,
11834                                                   func_mf_config[func].config);
11835                                 break;
11836                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11837                                 bp->mf_config[vn] = 0;
11838                                 break;
11839                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
11840                                 val2 = SHMEM_RD(bp,
11841                                         dev_info.shared_hw_config.config_3);
11842                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
11843                                 switch (val2) {
11844                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
11845                                         validate_set_si_mode(bp);
11846                                         bp->mf_sub_mode =
11847                                                         SUB_MF_MODE_NPAR1_DOT_5;
11848                                         break;
11849                                 default:
11850                                         /* Unknown configuration */
11851                                         bp->mf_config[vn] = 0;
11852                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
11853                                                        val);
11854                                 }
11855                                 break;
11856                         default:
11857                                 /* Unknown configuration: reset mf_config */
11858                                 bp->mf_config[vn] = 0;
11859                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11860                         }
11861                 }
11862
11863                 BNX2X_DEV_INFO("%s function mode\n",
11864                                IS_MF(bp) ? "multi" : "single");
11865
11866                 switch (bp->mf_mode) {
11867                 case MULTI_FUNCTION_SD:
11868                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11869                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11870                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11871                                 bp->mf_ov = val;
11872                                 bp->path_has_ovlan = true;
11873
11874                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11875                                                func, bp->mf_ov, bp->mf_ov);
11876                         } else if (bp->mf_sub_mode == SUB_MF_MODE_UFP) {
11877                                 dev_err(&bp->pdev->dev,
11878                                         "Unexpected - no valid MF OV for func %d in UFP mode\n",
11879                                         func);
11880                                 bp->path_has_ovlan = true;
11881                         } else {
11882                                 dev_err(&bp->pdev->dev,
11883                                         "No valid MF OV for func %d, aborting\n",
11884                                         func);
11885                                 return -EPERM;
11886                         }
11887                         break;
11888                 case MULTI_FUNCTION_AFEX:
11889                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11890                         break;
11891                 case MULTI_FUNCTION_SI:
11892                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11893                                        func);
11894                         break;
11895                 default:
11896                         if (vn) {
11897                                 dev_err(&bp->pdev->dev,
11898                                         "VN %d is in a single function mode, aborting\n",
11899                                         vn);
11900                                 return -EPERM;
11901                         }
11902                         break;
11903                 }
11904
11905                 /* check if other port on the path needs ovlan:
11906                  * Since MF configuration is shared between ports
11907                  * Possible mixed modes are only
11908                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11909                  */
11910                 if (CHIP_MODE_IS_4_PORT(bp) &&
11911                     !bp->path_has_ovlan &&
11912                     !IS_MF(bp) &&
11913                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11914                         u8 other_port = !BP_PORT(bp);
11915                         u8 other_func = BP_PATH(bp) + 2*other_port;
11916                         val = MF_CFG_RD(bp,
11917                                         func_mf_config[other_func].e1hov_tag);
11918                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11919                                 bp->path_has_ovlan = true;
11920                 }
11921         }
11922
11923         /* adjust igu_sb_cnt to MF for E1H */
11924         if (CHIP_IS_E1H(bp) && IS_MF(bp))
11925                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11926
11927         /* port info */
11928         bnx2x_get_port_hwinfo(bp);
11929
11930         /* Get MAC addresses */
11931         bnx2x_get_mac_hwinfo(bp);
11932
11933         bnx2x_get_cnic_info(bp);
11934
11935         return rc;
11936 }
11937
11938 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11939 {
11940         int cnt, i, block_end, rodi;
11941         char vpd_start[BNX2X_VPD_LEN+1];
11942         char str_id_reg[VENDOR_ID_LEN+1];
11943         char str_id_cap[VENDOR_ID_LEN+1];
11944         char *vpd_data;
11945         char *vpd_extended_data = NULL;
11946         u8 len;
11947
11948         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11949         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11950
11951         if (cnt < BNX2X_VPD_LEN)
11952                 goto out_not_found;
11953
11954         /* VPD RO tag should be first tag after identifier string, hence
11955          * we should be able to find it in first BNX2X_VPD_LEN chars
11956          */
11957         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11958                              PCI_VPD_LRDT_RO_DATA);
11959         if (i < 0)
11960                 goto out_not_found;
11961
11962         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11963                     pci_vpd_lrdt_size(&vpd_start[i]);
11964
11965         i += PCI_VPD_LRDT_TAG_SIZE;
11966
11967         if (block_end > BNX2X_VPD_LEN) {
11968                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11969                 if (vpd_extended_data  == NULL)
11970                         goto out_not_found;
11971
11972                 /* read rest of vpd image into vpd_extended_data */
11973                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11974                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11975                                    block_end - BNX2X_VPD_LEN,
11976                                    vpd_extended_data + BNX2X_VPD_LEN);
11977                 if (cnt < (block_end - BNX2X_VPD_LEN))
11978                         goto out_not_found;
11979                 vpd_data = vpd_extended_data;
11980         } else
11981                 vpd_data = vpd_start;
11982
11983         /* now vpd_data holds full vpd content in both cases */
11984
11985         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11986                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11987         if (rodi < 0)
11988                 goto out_not_found;
11989
11990         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11991
11992         if (len != VENDOR_ID_LEN)
11993                 goto out_not_found;
11994
11995         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11996
11997         /* vendor specific info */
11998         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11999         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12000         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12001             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12002
12003                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12004                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
12005                 if (rodi >= 0) {
12006                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
12007
12008                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12009
12010                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12011                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12012                                 bp->fw_ver[len] = ' ';
12013                         }
12014                 }
12015                 kfree(vpd_extended_data);
12016                 return;
12017         }
12018 out_not_found:
12019         kfree(vpd_extended_data);
12020         return;
12021 }
12022
12023 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12024 {
12025         u32 flags = 0;
12026
12027         if (CHIP_REV_IS_FPGA(bp))
12028                 SET_FLAGS(flags, MODE_FPGA);
12029         else if (CHIP_REV_IS_EMUL(bp))
12030                 SET_FLAGS(flags, MODE_EMUL);
12031         else
12032                 SET_FLAGS(flags, MODE_ASIC);
12033
12034         if (CHIP_MODE_IS_4_PORT(bp))
12035                 SET_FLAGS(flags, MODE_PORT4);
12036         else
12037                 SET_FLAGS(flags, MODE_PORT2);
12038
12039         if (CHIP_IS_E2(bp))
12040                 SET_FLAGS(flags, MODE_E2);
12041         else if (CHIP_IS_E3(bp)) {
12042                 SET_FLAGS(flags, MODE_E3);
12043                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12044                         SET_FLAGS(flags, MODE_E3_A0);
12045                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12046                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12047         }
12048
12049         if (IS_MF(bp)) {
12050                 SET_FLAGS(flags, MODE_MF);
12051                 switch (bp->mf_mode) {
12052                 case MULTI_FUNCTION_SD:
12053                         SET_FLAGS(flags, MODE_MF_SD);
12054                         break;
12055                 case MULTI_FUNCTION_SI:
12056                         SET_FLAGS(flags, MODE_MF_SI);
12057                         break;
12058                 case MULTI_FUNCTION_AFEX:
12059                         SET_FLAGS(flags, MODE_MF_AFEX);
12060                         break;
12061                 }
12062         } else
12063                 SET_FLAGS(flags, MODE_SF);
12064
12065 #if defined(__LITTLE_ENDIAN)
12066         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12067 #else /*(__BIG_ENDIAN)*/
12068         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12069 #endif
12070         INIT_MODE_FLAGS(bp) = flags;
12071 }
12072
12073 static int bnx2x_init_bp(struct bnx2x *bp)
12074 {
12075         int func;
12076         int rc;
12077
12078         mutex_init(&bp->port.phy_mutex);
12079         mutex_init(&bp->fw_mb_mutex);
12080         mutex_init(&bp->drv_info_mutex);
12081         sema_init(&bp->stats_lock, 1);
12082         bp->drv_info_mng_owner = false;
12083
12084         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12085         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12086         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12087         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12088         if (IS_PF(bp)) {
12089                 rc = bnx2x_get_hwinfo(bp);
12090                 if (rc)
12091                         return rc;
12092         } else {
12093                 eth_zero_addr(bp->dev->dev_addr);
12094         }
12095
12096         bnx2x_set_modes_bitmap(bp);
12097
12098         rc = bnx2x_alloc_mem_bp(bp);
12099         if (rc)
12100                 return rc;
12101
12102         bnx2x_read_fwinfo(bp);
12103
12104         func = BP_FUNC(bp);
12105
12106         /* need to reset chip if undi was active */
12107         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12108                 /* init fw_seq */
12109                 bp->fw_seq =
12110                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12111                                                         DRV_MSG_SEQ_NUMBER_MASK;
12112                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12113
12114                 rc = bnx2x_prev_unload(bp);
12115                 if (rc) {
12116                         bnx2x_free_mem_bp(bp);
12117                         return rc;
12118                 }
12119         }
12120
12121         if (CHIP_REV_IS_FPGA(bp))
12122                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12123
12124         if (BP_NOMCP(bp) && (func == 0))
12125                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12126
12127         bp->disable_tpa = disable_tpa;
12128         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12129         /* Reduce memory usage in kdump environment by disabling TPA */
12130         bp->disable_tpa |= is_kdump_kernel();
12131
12132         /* Set TPA flags */
12133         if (bp->disable_tpa) {
12134                 bp->dev->hw_features &= ~NETIF_F_LRO;
12135                 bp->dev->features &= ~NETIF_F_LRO;
12136         }
12137
12138         if (CHIP_IS_E1(bp))
12139                 bp->dropless_fc = 0;
12140         else
12141                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12142
12143         bp->mrrs = mrrs;
12144
12145         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12146         if (IS_VF(bp))
12147                 bp->rx_ring_size = MAX_RX_AVAIL;
12148
12149         /* make sure that the numbers are in the right granularity */
12150         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12151         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12152
12153         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12154
12155         init_timer(&bp->timer);
12156         bp->timer.expires = jiffies + bp->current_interval;
12157         bp->timer.data = (unsigned long) bp;
12158         bp->timer.function = bnx2x_timer;
12159
12160         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12161             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12162             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12163             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12164                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12165                 bnx2x_dcbx_init_params(bp);
12166         } else {
12167                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12168         }
12169
12170         if (CHIP_IS_E1x(bp))
12171                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12172         else
12173                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12174
12175         /* multiple tx priority */
12176         if (IS_VF(bp))
12177                 bp->max_cos = 1;
12178         else if (CHIP_IS_E1x(bp))
12179                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12180         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12181                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12182         else if (CHIP_IS_E3B0(bp))
12183                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12184         else
12185                 BNX2X_ERR("unknown chip %x revision %x\n",
12186                           CHIP_NUM(bp), CHIP_REV(bp));
12187         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12188
12189         /* We need at least one default status block for slow-path events,
12190          * second status block for the L2 queue, and a third status block for
12191          * CNIC if supported.
12192          */
12193         if (IS_VF(bp))
12194                 bp->min_msix_vec_cnt = 1;
12195         else if (CNIC_SUPPORT(bp))
12196                 bp->min_msix_vec_cnt = 3;
12197         else /* PF w/o cnic */
12198                 bp->min_msix_vec_cnt = 2;
12199         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12200
12201         bp->dump_preset_idx = 1;
12202
12203         if (CHIP_IS_E3B0(bp))
12204                 bp->flags |= PTP_SUPPORTED;
12205
12206         return rc;
12207 }
12208
12209 /****************************************************************************
12210 * General service functions
12211 ****************************************************************************/
12212
12213 /*
12214  * net_device service functions
12215  */
12216
12217 /* called with rtnl_lock */
12218 static int bnx2x_open(struct net_device *dev)
12219 {
12220         struct bnx2x *bp = netdev_priv(dev);
12221         int rc;
12222
12223         bp->stats_init = true;
12224
12225         netif_carrier_off(dev);
12226
12227         bnx2x_set_power_state(bp, PCI_D0);
12228
12229         /* If parity had happen during the unload, then attentions
12230          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12231          * want the first function loaded on the current engine to
12232          * complete the recovery.
12233          * Parity recovery is only relevant for PF driver.
12234          */
12235         if (IS_PF(bp)) {
12236                 int other_engine = BP_PATH(bp) ? 0 : 1;
12237                 bool other_load_status, load_status;
12238                 bool global = false;
12239
12240                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12241                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12242                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12243                     bnx2x_chk_parity_attn(bp, &global, true)) {
12244                         do {
12245                                 /* If there are attentions and they are in a
12246                                  * global blocks, set the GLOBAL_RESET bit
12247                                  * regardless whether it will be this function
12248                                  * that will complete the recovery or not.
12249                                  */
12250                                 if (global)
12251                                         bnx2x_set_reset_global(bp);
12252
12253                                 /* Only the first function on the current
12254                                  * engine should try to recover in open. In case
12255                                  * of attentions in global blocks only the first
12256                                  * in the chip should try to recover.
12257                                  */
12258                                 if ((!load_status &&
12259                                      (!global || !other_load_status)) &&
12260                                       bnx2x_trylock_leader_lock(bp) &&
12261                                       !bnx2x_leader_reset(bp)) {
12262                                         netdev_info(bp->dev,
12263                                                     "Recovered in open\n");
12264                                         break;
12265                                 }
12266
12267                                 /* recovery has failed... */
12268                                 bnx2x_set_power_state(bp, PCI_D3hot);
12269                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12270
12271                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12272                                           "If you still see this message after a few retries then power cycle is required.\n");
12273
12274                                 return -EAGAIN;
12275                         } while (0);
12276                 }
12277         }
12278
12279         bp->recovery_state = BNX2X_RECOVERY_DONE;
12280         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12281         if (rc)
12282                 return rc;
12283         return 0;
12284 }
12285
12286 /* called with rtnl_lock */
12287 static int bnx2x_close(struct net_device *dev)
12288 {
12289         struct bnx2x *bp = netdev_priv(dev);
12290
12291         /* Unload the driver, release IRQs */
12292         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12293
12294         return 0;
12295 }
12296
12297 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12298                                       struct bnx2x_mcast_ramrod_params *p)
12299 {
12300         int mc_count = netdev_mc_count(bp->dev);
12301         struct bnx2x_mcast_list_elem *mc_mac =
12302                 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12303         struct netdev_hw_addr *ha;
12304
12305         if (!mc_mac)
12306                 return -ENOMEM;
12307
12308         INIT_LIST_HEAD(&p->mcast_list);
12309
12310         netdev_for_each_mc_addr(ha, bp->dev) {
12311                 mc_mac->mac = bnx2x_mc_addr(ha);
12312                 list_add_tail(&mc_mac->link, &p->mcast_list);
12313                 mc_mac++;
12314         }
12315
12316         p->mcast_list_len = mc_count;
12317
12318         return 0;
12319 }
12320
12321 static void bnx2x_free_mcast_macs_list(
12322         struct bnx2x_mcast_ramrod_params *p)
12323 {
12324         struct bnx2x_mcast_list_elem *mc_mac =
12325                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12326                                  link);
12327
12328         WARN_ON(!mc_mac);
12329         kfree(mc_mac);
12330 }
12331
12332 /**
12333  * bnx2x_set_uc_list - configure a new unicast MACs list.
12334  *
12335  * @bp: driver handle
12336  *
12337  * We will use zero (0) as a MAC type for these MACs.
12338  */
12339 static int bnx2x_set_uc_list(struct bnx2x *bp)
12340 {
12341         int rc;
12342         struct net_device *dev = bp->dev;
12343         struct netdev_hw_addr *ha;
12344         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12345         unsigned long ramrod_flags = 0;
12346
12347         /* First schedule a cleanup up of old configuration */
12348         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12349         if (rc < 0) {
12350                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12351                 return rc;
12352         }
12353
12354         netdev_for_each_uc_addr(ha, dev) {
12355                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12356                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12357                 if (rc == -EEXIST) {
12358                         DP(BNX2X_MSG_SP,
12359                            "Failed to schedule ADD operations: %d\n", rc);
12360                         /* do not treat adding same MAC as error */
12361                         rc = 0;
12362
12363                 } else if (rc < 0) {
12364
12365                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12366                                   rc);
12367                         return rc;
12368                 }
12369         }
12370
12371         /* Execute the pending commands */
12372         __set_bit(RAMROD_CONT, &ramrod_flags);
12373         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12374                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12375 }
12376
12377 static int bnx2x_set_mc_list(struct bnx2x *bp)
12378 {
12379         struct net_device *dev = bp->dev;
12380         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12381         int rc = 0;
12382
12383         rparam.mcast_obj = &bp->mcast_obj;
12384
12385         /* first, clear all configured multicast MACs */
12386         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12387         if (rc < 0) {
12388                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12389                 return rc;
12390         }
12391
12392         /* then, configure a new MACs list */
12393         if (netdev_mc_count(dev)) {
12394                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12395                 if (rc) {
12396                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12397                                   rc);
12398                         return rc;
12399                 }
12400
12401                 /* Now add the new MACs */
12402                 rc = bnx2x_config_mcast(bp, &rparam,
12403                                         BNX2X_MCAST_CMD_ADD);
12404                 if (rc < 0)
12405                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12406                                   rc);
12407
12408                 bnx2x_free_mcast_macs_list(&rparam);
12409         }
12410
12411         return rc;
12412 }
12413
12414 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12415 static void bnx2x_set_rx_mode(struct net_device *dev)
12416 {
12417         struct bnx2x *bp = netdev_priv(dev);
12418
12419         if (bp->state != BNX2X_STATE_OPEN) {
12420                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12421                 return;
12422         } else {
12423                 /* Schedule an SP task to handle rest of change */
12424                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12425                                        NETIF_MSG_IFUP);
12426         }
12427 }
12428
12429 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12430 {
12431         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12432
12433         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12434
12435         netif_addr_lock_bh(bp->dev);
12436
12437         if (bp->dev->flags & IFF_PROMISC) {
12438                 rx_mode = BNX2X_RX_MODE_PROMISC;
12439         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12440                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12441                     CHIP_IS_E1(bp))) {
12442                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12443         } else {
12444                 if (IS_PF(bp)) {
12445                         /* some multicasts */
12446                         if (bnx2x_set_mc_list(bp) < 0)
12447                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12448
12449                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12450                         netif_addr_unlock_bh(bp->dev);
12451                         if (bnx2x_set_uc_list(bp) < 0)
12452                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12453                         netif_addr_lock_bh(bp->dev);
12454                 } else {
12455                         /* configuring mcast to a vf involves sleeping (when we
12456                          * wait for the pf's response).
12457                          */
12458                         bnx2x_schedule_sp_rtnl(bp,
12459                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12460                 }
12461         }
12462
12463         bp->rx_mode = rx_mode;
12464         /* handle ISCSI SD mode */
12465         if (IS_MF_ISCSI_ONLY(bp))
12466                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12467
12468         /* Schedule the rx_mode command */
12469         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12470                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12471                 netif_addr_unlock_bh(bp->dev);
12472                 return;
12473         }
12474
12475         if (IS_PF(bp)) {
12476                 bnx2x_set_storm_rx_mode(bp);
12477                 netif_addr_unlock_bh(bp->dev);
12478         } else {
12479                 /* VF will need to request the PF to make this change, and so
12480                  * the VF needs to release the bottom-half lock prior to the
12481                  * request (as it will likely require sleep on the VF side)
12482                  */
12483                 netif_addr_unlock_bh(bp->dev);
12484                 bnx2x_vfpf_storm_rx_mode(bp);
12485         }
12486 }
12487
12488 /* called with rtnl_lock */
12489 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12490                            int devad, u16 addr)
12491 {
12492         struct bnx2x *bp = netdev_priv(netdev);
12493         u16 value;
12494         int rc;
12495
12496         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12497            prtad, devad, addr);
12498
12499         /* The HW expects different devad if CL22 is used */
12500         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12501
12502         bnx2x_acquire_phy_lock(bp);
12503         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12504         bnx2x_release_phy_lock(bp);
12505         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12506
12507         if (!rc)
12508                 rc = value;
12509         return rc;
12510 }
12511
12512 /* called with rtnl_lock */
12513 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12514                             u16 addr, u16 value)
12515 {
12516         struct bnx2x *bp = netdev_priv(netdev);
12517         int rc;
12518
12519         DP(NETIF_MSG_LINK,
12520            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12521            prtad, devad, addr, value);
12522
12523         /* The HW expects different devad if CL22 is used */
12524         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12525
12526         bnx2x_acquire_phy_lock(bp);
12527         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12528         bnx2x_release_phy_lock(bp);
12529         return rc;
12530 }
12531
12532 /* called with rtnl_lock */
12533 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12534 {
12535         struct bnx2x *bp = netdev_priv(dev);
12536         struct mii_ioctl_data *mdio = if_mii(ifr);
12537
12538         if (!netif_running(dev))
12539                 return -EAGAIN;
12540
12541         switch (cmd) {
12542         case SIOCSHWTSTAMP:
12543                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12544         default:
12545                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12546                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12547                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12548         }
12549 }
12550
12551 #ifdef CONFIG_NET_POLL_CONTROLLER
12552 static void poll_bnx2x(struct net_device *dev)
12553 {
12554         struct bnx2x *bp = netdev_priv(dev);
12555         int i;
12556
12557         for_each_eth_queue(bp, i) {
12558                 struct bnx2x_fastpath *fp = &bp->fp[i];
12559                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12560         }
12561 }
12562 #endif
12563
12564 static int bnx2x_validate_addr(struct net_device *dev)
12565 {
12566         struct bnx2x *bp = netdev_priv(dev);
12567
12568         /* query the bulletin board for mac address configured by the PF */
12569         if (IS_VF(bp))
12570                 bnx2x_sample_bulletin(bp);
12571
12572         if (!is_valid_ether_addr(dev->dev_addr)) {
12573                 BNX2X_ERR("Non-valid Ethernet address\n");
12574                 return -EADDRNOTAVAIL;
12575         }
12576         return 0;
12577 }
12578
12579 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12580                                   struct netdev_phys_item_id *ppid)
12581 {
12582         struct bnx2x *bp = netdev_priv(netdev);
12583
12584         if (!(bp->flags & HAS_PHYS_PORT_ID))
12585                 return -EOPNOTSUPP;
12586
12587         ppid->id_len = sizeof(bp->phys_port_id);
12588         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12589
12590         return 0;
12591 }
12592
12593 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12594                                               struct net_device *dev,
12595                                               netdev_features_t features)
12596 {
12597         features = vlan_features_check(skb, features);
12598         return vxlan_features_check(skb, features);
12599 }
12600
12601 static const struct net_device_ops bnx2x_netdev_ops = {
12602         .ndo_open               = bnx2x_open,
12603         .ndo_stop               = bnx2x_close,
12604         .ndo_start_xmit         = bnx2x_start_xmit,
12605         .ndo_select_queue       = bnx2x_select_queue,
12606         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12607         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12608         .ndo_validate_addr      = bnx2x_validate_addr,
12609         .ndo_do_ioctl           = bnx2x_ioctl,
12610         .ndo_change_mtu         = bnx2x_change_mtu,
12611         .ndo_fix_features       = bnx2x_fix_features,
12612         .ndo_set_features       = bnx2x_set_features,
12613         .ndo_tx_timeout         = bnx2x_tx_timeout,
12614 #ifdef CONFIG_NET_POLL_CONTROLLER
12615         .ndo_poll_controller    = poll_bnx2x,
12616 #endif
12617         .ndo_setup_tc           = bnx2x_setup_tc,
12618 #ifdef CONFIG_BNX2X_SRIOV
12619         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12620         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12621         .ndo_get_vf_config      = bnx2x_get_vf_config,
12622 #endif
12623 #ifdef NETDEV_FCOE_WWNN
12624         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12625 #endif
12626
12627 #ifdef CONFIG_NET_RX_BUSY_POLL
12628         .ndo_busy_poll          = bnx2x_low_latency_recv,
12629 #endif
12630         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
12631         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
12632         .ndo_features_check     = bnx2x_features_check,
12633 };
12634
12635 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12636 {
12637         struct device *dev = &bp->pdev->dev;
12638
12639         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12640             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12641                 dev_err(dev, "System does not support DMA, aborting\n");
12642                 return -EIO;
12643         }
12644
12645         return 0;
12646 }
12647
12648 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12649 {
12650         if (bp->flags & AER_ENABLED) {
12651                 pci_disable_pcie_error_reporting(bp->pdev);
12652                 bp->flags &= ~AER_ENABLED;
12653         }
12654 }
12655
12656 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12657                           struct net_device *dev, unsigned long board_type)
12658 {
12659         int rc;
12660         u32 pci_cfg_dword;
12661         bool chip_is_e1x = (board_type == BCM57710 ||
12662                             board_type == BCM57711 ||
12663                             board_type == BCM57711E);
12664
12665         SET_NETDEV_DEV(dev, &pdev->dev);
12666
12667         bp->dev = dev;
12668         bp->pdev = pdev;
12669
12670         rc = pci_enable_device(pdev);
12671         if (rc) {
12672                 dev_err(&bp->pdev->dev,
12673                         "Cannot enable PCI device, aborting\n");
12674                 goto err_out;
12675         }
12676
12677         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12678                 dev_err(&bp->pdev->dev,
12679                         "Cannot find PCI device base address, aborting\n");
12680                 rc = -ENODEV;
12681                 goto err_out_disable;
12682         }
12683
12684         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12685                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12686                 rc = -ENODEV;
12687                 goto err_out_disable;
12688         }
12689
12690         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12691         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12692             PCICFG_REVESION_ID_ERROR_VAL) {
12693                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12694                 rc = -ENODEV;
12695                 goto err_out_disable;
12696         }
12697
12698         if (atomic_read(&pdev->enable_cnt) == 1) {
12699                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12700                 if (rc) {
12701                         dev_err(&bp->pdev->dev,
12702                                 "Cannot obtain PCI resources, aborting\n");
12703                         goto err_out_disable;
12704                 }
12705
12706                 pci_set_master(pdev);
12707                 pci_save_state(pdev);
12708         }
12709
12710         if (IS_PF(bp)) {
12711                 if (!pdev->pm_cap) {
12712                         dev_err(&bp->pdev->dev,
12713                                 "Cannot find power management capability, aborting\n");
12714                         rc = -EIO;
12715                         goto err_out_release;
12716                 }
12717         }
12718
12719         if (!pci_is_pcie(pdev)) {
12720                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12721                 rc = -EIO;
12722                 goto err_out_release;
12723         }
12724
12725         rc = bnx2x_set_coherency_mask(bp);
12726         if (rc)
12727                 goto err_out_release;
12728
12729         dev->mem_start = pci_resource_start(pdev, 0);
12730         dev->base_addr = dev->mem_start;
12731         dev->mem_end = pci_resource_end(pdev, 0);
12732
12733         dev->irq = pdev->irq;
12734
12735         bp->regview = pci_ioremap_bar(pdev, 0);
12736         if (!bp->regview) {
12737                 dev_err(&bp->pdev->dev,
12738                         "Cannot map register space, aborting\n");
12739                 rc = -ENOMEM;
12740                 goto err_out_release;
12741         }
12742
12743         /* In E1/E1H use pci device function given by kernel.
12744          * In E2/E3 read physical function from ME register since these chips
12745          * support Physical Device Assignment where kernel BDF maybe arbitrary
12746          * (depending on hypervisor).
12747          */
12748         if (chip_is_e1x) {
12749                 bp->pf_num = PCI_FUNC(pdev->devfn);
12750         } else {
12751                 /* chip is E2/3*/
12752                 pci_read_config_dword(bp->pdev,
12753                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12754                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12755                                   ME_REG_ABS_PF_NUM_SHIFT);
12756         }
12757         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12758
12759         /* clean indirect addresses */
12760         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12761                                PCICFG_VENDOR_ID_OFFSET);
12762
12763         /* Set PCIe reset type to fundamental for EEH recovery */
12764         pdev->needs_freset = 1;
12765
12766         /* AER (Advanced Error reporting) configuration */
12767         rc = pci_enable_pcie_error_reporting(pdev);
12768         if (!rc)
12769                 bp->flags |= AER_ENABLED;
12770         else
12771                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12772
12773         /*
12774          * Clean the following indirect addresses for all functions since it
12775          * is not used by the driver.
12776          */
12777         if (IS_PF(bp)) {
12778                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12779                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12780                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12781                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12782
12783                 if (chip_is_e1x) {
12784                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12785                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12786                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12787                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12788                 }
12789
12790                 /* Enable internal target-read (in case we are probed after PF
12791                  * FLR). Must be done prior to any BAR read access. Only for
12792                  * 57712 and up
12793                  */
12794                 if (!chip_is_e1x)
12795                         REG_WR(bp,
12796                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12797         }
12798
12799         dev->watchdog_timeo = TX_TIMEOUT;
12800
12801         dev->netdev_ops = &bnx2x_netdev_ops;
12802         bnx2x_set_ethtool_ops(bp, dev);
12803
12804         dev->priv_flags |= IFF_UNICAST_FLT;
12805
12806         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12807                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12808                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12809                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12810         if (!chip_is_e1x) {
12811                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12812                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12813                 dev->hw_enc_features =
12814                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12815                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12816                         NETIF_F_GSO_IPIP |
12817                         NETIF_F_GSO_SIT |
12818                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12819         }
12820
12821         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12822                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12823
12824         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12825         dev->features |= NETIF_F_HIGHDMA;
12826
12827         /* Add Loopback capability to the device */
12828         dev->hw_features |= NETIF_F_LOOPBACK;
12829
12830 #ifdef BCM_DCBNL
12831         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12832 #endif
12833
12834         /* get_port_hwinfo() will set prtad and mmds properly */
12835         bp->mdio.prtad = MDIO_PRTAD_NONE;
12836         bp->mdio.mmds = 0;
12837         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12838         bp->mdio.dev = dev;
12839         bp->mdio.mdio_read = bnx2x_mdio_read;
12840         bp->mdio.mdio_write = bnx2x_mdio_write;
12841
12842         return 0;
12843
12844 err_out_release:
12845         if (atomic_read(&pdev->enable_cnt) == 1)
12846                 pci_release_regions(pdev);
12847
12848 err_out_disable:
12849         pci_disable_device(pdev);
12850
12851 err_out:
12852         return rc;
12853 }
12854
12855 static int bnx2x_check_firmware(struct bnx2x *bp)
12856 {
12857         const struct firmware *firmware = bp->firmware;
12858         struct bnx2x_fw_file_hdr *fw_hdr;
12859         struct bnx2x_fw_file_section *sections;
12860         u32 offset, len, num_ops;
12861         __be16 *ops_offsets;
12862         int i;
12863         const u8 *fw_ver;
12864
12865         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12866                 BNX2X_ERR("Wrong FW size\n");
12867                 return -EINVAL;
12868         }
12869
12870         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12871         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12872
12873         /* Make sure none of the offsets and sizes make us read beyond
12874          * the end of the firmware data */
12875         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12876                 offset = be32_to_cpu(sections[i].offset);
12877                 len = be32_to_cpu(sections[i].len);
12878                 if (offset + len > firmware->size) {
12879                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12880                         return -EINVAL;
12881                 }
12882         }
12883
12884         /* Likewise for the init_ops offsets */
12885         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12886         ops_offsets = (__force __be16 *)(firmware->data + offset);
12887         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12888
12889         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12890                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12891                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12892                         return -EINVAL;
12893                 }
12894         }
12895
12896         /* Check FW version */
12897         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12898         fw_ver = firmware->data + offset;
12899         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12900             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12901             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12902             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12903                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12904                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12905                        BCM_5710_FW_MAJOR_VERSION,
12906                        BCM_5710_FW_MINOR_VERSION,
12907                        BCM_5710_FW_REVISION_VERSION,
12908                        BCM_5710_FW_ENGINEERING_VERSION);
12909                 return -EINVAL;
12910         }
12911
12912         return 0;
12913 }
12914
12915 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12916 {
12917         const __be32 *source = (const __be32 *)_source;
12918         u32 *target = (u32 *)_target;
12919         u32 i;
12920
12921         for (i = 0; i < n/4; i++)
12922                 target[i] = be32_to_cpu(source[i]);
12923 }
12924
12925 /*
12926    Ops array is stored in the following format:
12927    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12928  */
12929 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12930 {
12931         const __be32 *source = (const __be32 *)_source;
12932         struct raw_op *target = (struct raw_op *)_target;
12933         u32 i, j, tmp;
12934
12935         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12936                 tmp = be32_to_cpu(source[j]);
12937                 target[i].op = (tmp >> 24) & 0xff;
12938                 target[i].offset = tmp & 0xffffff;
12939                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12940         }
12941 }
12942
12943 /* IRO array is stored in the following format:
12944  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12945  */
12946 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12947 {
12948         const __be32 *source = (const __be32 *)_source;
12949         struct iro *target = (struct iro *)_target;
12950         u32 i, j, tmp;
12951
12952         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12953                 target[i].base = be32_to_cpu(source[j]);
12954                 j++;
12955                 tmp = be32_to_cpu(source[j]);
12956                 target[i].m1 = (tmp >> 16) & 0xffff;
12957                 target[i].m2 = tmp & 0xffff;
12958                 j++;
12959                 tmp = be32_to_cpu(source[j]);
12960                 target[i].m3 = (tmp >> 16) & 0xffff;
12961                 target[i].size = tmp & 0xffff;
12962                 j++;
12963         }
12964 }
12965
12966 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12967 {
12968         const __be16 *source = (const __be16 *)_source;
12969         u16 *target = (u16 *)_target;
12970         u32 i;
12971
12972         for (i = 0; i < n/2; i++)
12973                 target[i] = be16_to_cpu(source[i]);
12974 }
12975
12976 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12977 do {                                                                    \
12978         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12979         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12980         if (!bp->arr)                                                   \
12981                 goto lbl;                                               \
12982         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12983              (u8 *)bp->arr, len);                                       \
12984 } while (0)
12985
12986 static int bnx2x_init_firmware(struct bnx2x *bp)
12987 {
12988         const char *fw_file_name;
12989         struct bnx2x_fw_file_hdr *fw_hdr;
12990         int rc;
12991
12992         if (bp->firmware)
12993                 return 0;
12994
12995         if (CHIP_IS_E1(bp))
12996                 fw_file_name = FW_FILE_NAME_E1;
12997         else if (CHIP_IS_E1H(bp))
12998                 fw_file_name = FW_FILE_NAME_E1H;
12999         else if (!CHIP_IS_E1x(bp))
13000                 fw_file_name = FW_FILE_NAME_E2;
13001         else {
13002                 BNX2X_ERR("Unsupported chip revision\n");
13003                 return -EINVAL;
13004         }
13005         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13006
13007         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13008         if (rc) {
13009                 BNX2X_ERR("Can't load firmware file %s\n",
13010                           fw_file_name);
13011                 goto request_firmware_exit;
13012         }
13013
13014         rc = bnx2x_check_firmware(bp);
13015         if (rc) {
13016                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13017                 goto request_firmware_exit;
13018         }
13019
13020         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13021
13022         /* Initialize the pointers to the init arrays */
13023         /* Blob */
13024         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13025
13026         /* Opcodes */
13027         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13028
13029         /* Offsets */
13030         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13031                             be16_to_cpu_n);
13032
13033         /* STORMs firmware */
13034         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13035                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13036         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
13037                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13038         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13039                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13040         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
13041                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
13042         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13043                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13044         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
13045                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13046         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13047                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13048         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
13049                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13050         /* IRO */
13051         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13052
13053         return 0;
13054
13055 iro_alloc_err:
13056         kfree(bp->init_ops_offsets);
13057 init_offsets_alloc_err:
13058         kfree(bp->init_ops);
13059 init_ops_alloc_err:
13060         kfree(bp->init_data);
13061 request_firmware_exit:
13062         release_firmware(bp->firmware);
13063         bp->firmware = NULL;
13064
13065         return rc;
13066 }
13067
13068 static void bnx2x_release_firmware(struct bnx2x *bp)
13069 {
13070         kfree(bp->init_ops_offsets);
13071         kfree(bp->init_ops);
13072         kfree(bp->init_data);
13073         release_firmware(bp->firmware);
13074         bp->firmware = NULL;
13075 }
13076
13077 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13078         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13079         .init_hw_cmn      = bnx2x_init_hw_common,
13080         .init_hw_port     = bnx2x_init_hw_port,
13081         .init_hw_func     = bnx2x_init_hw_func,
13082
13083         .reset_hw_cmn     = bnx2x_reset_common,
13084         .reset_hw_port    = bnx2x_reset_port,
13085         .reset_hw_func    = bnx2x_reset_func,
13086
13087         .gunzip_init      = bnx2x_gunzip_init,
13088         .gunzip_end       = bnx2x_gunzip_end,
13089
13090         .init_fw          = bnx2x_init_firmware,
13091         .release_fw       = bnx2x_release_firmware,
13092 };
13093
13094 void bnx2x__init_func_obj(struct bnx2x *bp)
13095 {
13096         /* Prepare DMAE related driver resources */
13097         bnx2x_setup_dmae(bp);
13098
13099         bnx2x_init_func_obj(bp, &bp->func_obj,
13100                             bnx2x_sp(bp, func_rdata),
13101                             bnx2x_sp_mapping(bp, func_rdata),
13102                             bnx2x_sp(bp, func_afex_rdata),
13103                             bnx2x_sp_mapping(bp, func_afex_rdata),
13104                             &bnx2x_func_sp_drv);
13105 }
13106
13107 /* must be called after sriov-enable */
13108 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13109 {
13110         int cid_count = BNX2X_L2_MAX_CID(bp);
13111
13112         if (IS_SRIOV(bp))
13113                 cid_count += BNX2X_VF_CIDS;
13114
13115         if (CNIC_SUPPORT(bp))
13116                 cid_count += CNIC_CID_MAX;
13117
13118         return roundup(cid_count, QM_CID_ROUND);
13119 }
13120
13121 /**
13122  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13123  *
13124  * @dev:        pci device
13125  *
13126  */
13127 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13128 {
13129         int index;
13130         u16 control = 0;
13131
13132         /*
13133          * If MSI-X is not supported - return number of SBs needed to support
13134          * one fast path queue: one FP queue + SB for CNIC
13135          */
13136         if (!pdev->msix_cap) {
13137                 dev_info(&pdev->dev, "no msix capability found\n");
13138                 return 1 + cnic_cnt;
13139         }
13140         dev_info(&pdev->dev, "msix capability found\n");
13141
13142         /*
13143          * The value in the PCI configuration space is the index of the last
13144          * entry, namely one less than the actual size of the table, which is
13145          * exactly what we want to return from this function: number of all SBs
13146          * without the default SB.
13147          * For VFs there is no default SB, then we return (index+1).
13148          */
13149         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13150
13151         index = control & PCI_MSIX_FLAGS_QSIZE;
13152
13153         return index;
13154 }
13155
13156 static int set_max_cos_est(int chip_id)
13157 {
13158         switch (chip_id) {
13159         case BCM57710:
13160         case BCM57711:
13161         case BCM57711E:
13162                 return BNX2X_MULTI_TX_COS_E1X;
13163         case BCM57712:
13164         case BCM57712_MF:
13165                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13166         case BCM57800:
13167         case BCM57800_MF:
13168         case BCM57810:
13169         case BCM57810_MF:
13170         case BCM57840_4_10:
13171         case BCM57840_2_20:
13172         case BCM57840_O:
13173         case BCM57840_MFO:
13174         case BCM57840_MF:
13175         case BCM57811:
13176         case BCM57811_MF:
13177                 return BNX2X_MULTI_TX_COS_E3B0;
13178         case BCM57712_VF:
13179         case BCM57800_VF:
13180         case BCM57810_VF:
13181         case BCM57840_VF:
13182         case BCM57811_VF:
13183                 return 1;
13184         default:
13185                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13186                 return -ENODEV;
13187         }
13188 }
13189
13190 static int set_is_vf(int chip_id)
13191 {
13192         switch (chip_id) {
13193         case BCM57712_VF:
13194         case BCM57800_VF:
13195         case BCM57810_VF:
13196         case BCM57840_VF:
13197         case BCM57811_VF:
13198                 return true;
13199         default:
13200                 return false;
13201         }
13202 }
13203
13204 /* nig_tsgen registers relative address */
13205 #define tsgen_ctrl 0x0
13206 #define tsgen_freecount 0x10
13207 #define tsgen_synctime_t0 0x20
13208 #define tsgen_offset_t0 0x28
13209 #define tsgen_drift_t0 0x30
13210 #define tsgen_synctime_t1 0x58
13211 #define tsgen_offset_t1 0x60
13212 #define tsgen_drift_t1 0x68
13213
13214 /* FW workaround for setting drift */
13215 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13216                                           int best_val, int best_period)
13217 {
13218         struct bnx2x_func_state_params func_params = {NULL};
13219         struct bnx2x_func_set_timesync_params *set_timesync_params =
13220                 &func_params.params.set_timesync;
13221
13222         /* Prepare parameters for function state transitions */
13223         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13224         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13225
13226         func_params.f_obj = &bp->func_obj;
13227         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13228
13229         /* Function parameters */
13230         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13231         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13232         set_timesync_params->add_sub_drift_adjust_value =
13233                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13234         set_timesync_params->drift_adjust_value = best_val;
13235         set_timesync_params->drift_adjust_period = best_period;
13236
13237         return bnx2x_func_state_change(bp, &func_params);
13238 }
13239
13240 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13241 {
13242         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13243         int rc;
13244         int drift_dir = 1;
13245         int val, period, period1, period2, dif, dif1, dif2;
13246         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13247
13248         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13249
13250         if (!netif_running(bp->dev)) {
13251                 DP(BNX2X_MSG_PTP,
13252                    "PTP adjfreq called while the interface is down\n");
13253                 return -EFAULT;
13254         }
13255
13256         if (ppb < 0) {
13257                 ppb = -ppb;
13258                 drift_dir = 0;
13259         }
13260
13261         if (ppb == 0) {
13262                 best_val = 1;
13263                 best_period = 0x1FFFFFF;
13264         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13265                 best_val = 31;
13266                 best_period = 1;
13267         } else {
13268                 /* Changed not to allow val = 8, 16, 24 as these values
13269                  * are not supported in workaround.
13270                  */
13271                 for (val = 0; val <= 31; val++) {
13272                         if ((val & 0x7) == 0)
13273                                 continue;
13274                         period1 = val * 1000000 / ppb;
13275                         period2 = period1 + 1;
13276                         if (period1 != 0)
13277                                 dif1 = ppb - (val * 1000000 / period1);
13278                         else
13279                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13280                         if (dif1 < 0)
13281                                 dif1 = -dif1;
13282                         dif2 = ppb - (val * 1000000 / period2);
13283                         if (dif2 < 0)
13284                                 dif2 = -dif2;
13285                         dif = (dif1 < dif2) ? dif1 : dif2;
13286                         period = (dif1 < dif2) ? period1 : period2;
13287                         if (dif < best_dif) {
13288                                 best_dif = dif;
13289                                 best_val = val;
13290                                 best_period = period;
13291                         }
13292                 }
13293         }
13294
13295         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13296                                             best_period);
13297         if (rc) {
13298                 BNX2X_ERR("Failed to set drift\n");
13299                 return -EFAULT;
13300         }
13301
13302         DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13303            best_period);
13304
13305         return 0;
13306 }
13307
13308 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13309 {
13310         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13311
13312         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13313
13314         timecounter_adjtime(&bp->timecounter, delta);
13315
13316         return 0;
13317 }
13318
13319 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13320 {
13321         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13322         u64 ns;
13323
13324         ns = timecounter_read(&bp->timecounter);
13325
13326         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13327
13328         *ts = ns_to_timespec64(ns);
13329
13330         return 0;
13331 }
13332
13333 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13334                              const struct timespec64 *ts)
13335 {
13336         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13337         u64 ns;
13338
13339         ns = timespec64_to_ns(ts);
13340
13341         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13342
13343         /* Re-init the timecounter */
13344         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13345
13346         return 0;
13347 }
13348
13349 /* Enable (or disable) ancillary features of the phc subsystem */
13350 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13351                             struct ptp_clock_request *rq, int on)
13352 {
13353         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13354
13355         BNX2X_ERR("PHC ancillary features are not supported\n");
13356         return -ENOTSUPP;
13357 }
13358
13359 static void bnx2x_register_phc(struct bnx2x *bp)
13360 {
13361         /* Fill the ptp_clock_info struct and register PTP clock*/
13362         bp->ptp_clock_info.owner = THIS_MODULE;
13363         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13364         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13365         bp->ptp_clock_info.n_alarm = 0;
13366         bp->ptp_clock_info.n_ext_ts = 0;
13367         bp->ptp_clock_info.n_per_out = 0;
13368         bp->ptp_clock_info.pps = 0;
13369         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13370         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13371         bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13372         bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13373         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13374
13375         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13376         if (IS_ERR(bp->ptp_clock)) {
13377                 bp->ptp_clock = NULL;
13378                 BNX2X_ERR("PTP clock registeration failed\n");
13379         }
13380 }
13381
13382 static int bnx2x_init_one(struct pci_dev *pdev,
13383                                     const struct pci_device_id *ent)
13384 {
13385         struct net_device *dev = NULL;
13386         struct bnx2x *bp;
13387         enum pcie_link_width pcie_width;
13388         enum pci_bus_speed pcie_speed;
13389         int rc, max_non_def_sbs;
13390         int rx_count, tx_count, rss_count, doorbell_size;
13391         int max_cos_est;
13392         bool is_vf;
13393         int cnic_cnt;
13394
13395         /* Management FW 'remembers' living interfaces. Allow it some time
13396          * to forget previously living interfaces, allowing a proper re-load.
13397          */
13398         if (is_kdump_kernel()) {
13399                 ktime_t now = ktime_get_boottime();
13400                 ktime_t fw_ready_time = ktime_set(5, 0);
13401
13402                 if (ktime_before(now, fw_ready_time))
13403                         msleep(ktime_ms_delta(fw_ready_time, now));
13404         }
13405
13406         /* An estimated maximum supported CoS number according to the chip
13407          * version.
13408          * We will try to roughly estimate the maximum number of CoSes this chip
13409          * may support in order to minimize the memory allocated for Tx
13410          * netdev_queue's. This number will be accurately calculated during the
13411          * initialization of bp->max_cos based on the chip versions AND chip
13412          * revision in the bnx2x_init_bp().
13413          */
13414         max_cos_est = set_max_cos_est(ent->driver_data);
13415         if (max_cos_est < 0)
13416                 return max_cos_est;
13417         is_vf = set_is_vf(ent->driver_data);
13418         cnic_cnt = is_vf ? 0 : 1;
13419
13420         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13421
13422         /* add another SB for VF as it has no default SB */
13423         max_non_def_sbs += is_vf ? 1 : 0;
13424
13425         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13426         rss_count = max_non_def_sbs - cnic_cnt;
13427
13428         if (rss_count < 1)
13429                 return -EINVAL;
13430
13431         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13432         rx_count = rss_count + cnic_cnt;
13433
13434         /* Maximum number of netdev Tx queues:
13435          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13436          */
13437         tx_count = rss_count * max_cos_est + cnic_cnt;
13438
13439         /* dev zeroed in init_etherdev */
13440         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13441         if (!dev)
13442                 return -ENOMEM;
13443
13444         bp = netdev_priv(dev);
13445
13446         bp->flags = 0;
13447         if (is_vf)
13448                 bp->flags |= IS_VF_FLAG;
13449
13450         bp->igu_sb_cnt = max_non_def_sbs;
13451         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13452         bp->msg_enable = debug;
13453         bp->cnic_support = cnic_cnt;
13454         bp->cnic_probe = bnx2x_cnic_probe;
13455
13456         pci_set_drvdata(pdev, dev);
13457
13458         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13459         if (rc < 0) {
13460                 free_netdev(dev);
13461                 return rc;
13462         }
13463
13464         BNX2X_DEV_INFO("This is a %s function\n",
13465                        IS_PF(bp) ? "physical" : "virtual");
13466         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13467         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13468         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13469                        tx_count, rx_count);
13470
13471         rc = bnx2x_init_bp(bp);
13472         if (rc)
13473                 goto init_one_exit;
13474
13475         /* Map doorbells here as we need the real value of bp->max_cos which
13476          * is initialized in bnx2x_init_bp() to determine the number of
13477          * l2 connections.
13478          */
13479         if (IS_VF(bp)) {
13480                 bp->doorbells = bnx2x_vf_doorbells(bp);
13481                 rc = bnx2x_vf_pci_alloc(bp);
13482                 if (rc)
13483                         goto init_one_exit;
13484         } else {
13485                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13486                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13487                         dev_err(&bp->pdev->dev,
13488                                 "Cannot map doorbells, bar size too small, aborting\n");
13489                         rc = -ENOMEM;
13490                         goto init_one_exit;
13491                 }
13492                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13493                                                 doorbell_size);
13494         }
13495         if (!bp->doorbells) {
13496                 dev_err(&bp->pdev->dev,
13497                         "Cannot map doorbell space, aborting\n");
13498                 rc = -ENOMEM;
13499                 goto init_one_exit;
13500         }
13501
13502         if (IS_VF(bp)) {
13503                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13504                 if (rc)
13505                         goto init_one_exit;
13506         }
13507
13508         /* Enable SRIOV if capability found in configuration space */
13509         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13510         if (rc)
13511                 goto init_one_exit;
13512
13513         /* calc qm_cid_count */
13514         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13515         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13516
13517         /* disable FCOE L2 queue for E1x*/
13518         if (CHIP_IS_E1x(bp))
13519                 bp->flags |= NO_FCOE_FLAG;
13520
13521         /* Set bp->num_queues for MSI-X mode*/
13522         bnx2x_set_num_queues(bp);
13523
13524         /* Configure interrupt mode: try to enable MSI-X/MSI if
13525          * needed.
13526          */
13527         rc = bnx2x_set_int_mode(bp);
13528         if (rc) {
13529                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13530                 goto init_one_exit;
13531         }
13532         BNX2X_DEV_INFO("set interrupts successfully\n");
13533
13534         /* register the net device */
13535         rc = register_netdev(dev);
13536         if (rc) {
13537                 dev_err(&pdev->dev, "Cannot register net device\n");
13538                 goto init_one_exit;
13539         }
13540         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13541
13542         if (!NO_FCOE(bp)) {
13543                 /* Add storage MAC address */
13544                 rtnl_lock();
13545                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13546                 rtnl_unlock();
13547         }
13548         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13549             pcie_speed == PCI_SPEED_UNKNOWN ||
13550             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13551                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13552         else
13553                 BNX2X_DEV_INFO(
13554                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13555                        board_info[ent->driver_data].name,
13556                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13557                        pcie_width,
13558                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13559                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13560                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13561                        "Unknown",
13562                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13563
13564         bnx2x_register_phc(bp);
13565
13566         return 0;
13567
13568 init_one_exit:
13569         bnx2x_disable_pcie_error_reporting(bp);
13570
13571         if (bp->regview)
13572                 iounmap(bp->regview);
13573
13574         if (IS_PF(bp) && bp->doorbells)
13575                 iounmap(bp->doorbells);
13576
13577         free_netdev(dev);
13578
13579         if (atomic_read(&pdev->enable_cnt) == 1)
13580                 pci_release_regions(pdev);
13581
13582         pci_disable_device(pdev);
13583
13584         return rc;
13585 }
13586
13587 static void __bnx2x_remove(struct pci_dev *pdev,
13588                            struct net_device *dev,
13589                            struct bnx2x *bp,
13590                            bool remove_netdev)
13591 {
13592         if (bp->ptp_clock) {
13593                 ptp_clock_unregister(bp->ptp_clock);
13594                 bp->ptp_clock = NULL;
13595         }
13596
13597         /* Delete storage MAC address */
13598         if (!NO_FCOE(bp)) {
13599                 rtnl_lock();
13600                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13601                 rtnl_unlock();
13602         }
13603
13604 #ifdef BCM_DCBNL
13605         /* Delete app tlvs from dcbnl */
13606         bnx2x_dcbnl_update_applist(bp, true);
13607 #endif
13608
13609         if (IS_PF(bp) &&
13610             !BP_NOMCP(bp) &&
13611             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13612                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13613
13614         /* Close the interface - either directly or implicitly */
13615         if (remove_netdev) {
13616                 unregister_netdev(dev);
13617         } else {
13618                 rtnl_lock();
13619                 dev_close(dev);
13620                 rtnl_unlock();
13621         }
13622
13623         bnx2x_iov_remove_one(bp);
13624
13625         /* Power on: we can't let PCI layer write to us while we are in D3 */
13626         if (IS_PF(bp)) {
13627                 bnx2x_set_power_state(bp, PCI_D0);
13628
13629                 /* Set endianity registers to reset values in case next driver
13630                  * boots in different endianty environment.
13631                  */
13632                 bnx2x_reset_endianity(bp);
13633         }
13634
13635         /* Disable MSI/MSI-X */
13636         bnx2x_disable_msi(bp);
13637
13638         /* Power off */
13639         if (IS_PF(bp))
13640                 bnx2x_set_power_state(bp, PCI_D3hot);
13641
13642         /* Make sure RESET task is not scheduled before continuing */
13643         cancel_delayed_work_sync(&bp->sp_rtnl_task);
13644
13645         /* send message via vfpf channel to release the resources of this vf */
13646         if (IS_VF(bp))
13647                 bnx2x_vfpf_release(bp);
13648
13649         /* Assumes no further PCIe PM changes will occur */
13650         if (system_state == SYSTEM_POWER_OFF) {
13651                 pci_wake_from_d3(pdev, bp->wol);
13652                 pci_set_power_state(pdev, PCI_D3hot);
13653         }
13654
13655         bnx2x_disable_pcie_error_reporting(bp);
13656         if (remove_netdev) {
13657                 if (bp->regview)
13658                         iounmap(bp->regview);
13659
13660                 /* For vfs, doorbells are part of the regview and were unmapped
13661                  * along with it. FW is only loaded by PF.
13662                  */
13663                 if (IS_PF(bp)) {
13664                         if (bp->doorbells)
13665                                 iounmap(bp->doorbells);
13666
13667                         bnx2x_release_firmware(bp);
13668                 } else {
13669                         bnx2x_vf_pci_dealloc(bp);
13670                 }
13671                 bnx2x_free_mem_bp(bp);
13672
13673                 free_netdev(dev);
13674
13675                 if (atomic_read(&pdev->enable_cnt) == 1)
13676                         pci_release_regions(pdev);
13677
13678                 pci_disable_device(pdev);
13679         }
13680 }
13681
13682 static void bnx2x_remove_one(struct pci_dev *pdev)
13683 {
13684         struct net_device *dev = pci_get_drvdata(pdev);
13685         struct bnx2x *bp;
13686
13687         if (!dev) {
13688                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13689                 return;
13690         }
13691         bp = netdev_priv(dev);
13692
13693         __bnx2x_remove(pdev, dev, bp, true);
13694 }
13695
13696 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13697 {
13698         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13699
13700         bp->rx_mode = BNX2X_RX_MODE_NONE;
13701
13702         if (CNIC_LOADED(bp))
13703                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13704
13705         /* Stop Tx */
13706         bnx2x_tx_disable(bp);
13707         /* Delete all NAPI objects */
13708         bnx2x_del_all_napi(bp);
13709         if (CNIC_LOADED(bp))
13710                 bnx2x_del_all_napi_cnic(bp);
13711         netdev_reset_tc(bp->dev);
13712
13713         del_timer_sync(&bp->timer);
13714         cancel_delayed_work_sync(&bp->sp_task);
13715         cancel_delayed_work_sync(&bp->period_task);
13716
13717         if (!down_timeout(&bp->stats_lock, HZ / 10)) {
13718                 bp->stats_state = STATS_STATE_DISABLED;
13719                 up(&bp->stats_lock);
13720         }
13721
13722         bnx2x_save_statistics(bp);
13723
13724         netif_carrier_off(bp->dev);
13725
13726         return 0;
13727 }
13728
13729 /**
13730  * bnx2x_io_error_detected - called when PCI error is detected
13731  * @pdev: Pointer to PCI device
13732  * @state: The current pci connection state
13733  *
13734  * This function is called after a PCI bus error affecting
13735  * this device has been detected.
13736  */
13737 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13738                                                 pci_channel_state_t state)
13739 {
13740         struct net_device *dev = pci_get_drvdata(pdev);
13741         struct bnx2x *bp = netdev_priv(dev);
13742
13743         rtnl_lock();
13744
13745         BNX2X_ERR("IO error detected\n");
13746
13747         netif_device_detach(dev);
13748
13749         if (state == pci_channel_io_perm_failure) {
13750                 rtnl_unlock();
13751                 return PCI_ERS_RESULT_DISCONNECT;
13752         }
13753
13754         if (netif_running(dev))
13755                 bnx2x_eeh_nic_unload(bp);
13756
13757         bnx2x_prev_path_mark_eeh(bp);
13758
13759         pci_disable_device(pdev);
13760
13761         rtnl_unlock();
13762
13763         /* Request a slot reset */
13764         return PCI_ERS_RESULT_NEED_RESET;
13765 }
13766
13767 /**
13768  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13769  * @pdev: Pointer to PCI device
13770  *
13771  * Restart the card from scratch, as if from a cold-boot.
13772  */
13773 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13774 {
13775         struct net_device *dev = pci_get_drvdata(pdev);
13776         struct bnx2x *bp = netdev_priv(dev);
13777         int i;
13778
13779         rtnl_lock();
13780         BNX2X_ERR("IO slot reset initializing...\n");
13781         if (pci_enable_device(pdev)) {
13782                 dev_err(&pdev->dev,
13783                         "Cannot re-enable PCI device after reset\n");
13784                 rtnl_unlock();
13785                 return PCI_ERS_RESULT_DISCONNECT;
13786         }
13787
13788         pci_set_master(pdev);
13789         pci_restore_state(pdev);
13790         pci_save_state(pdev);
13791
13792         if (netif_running(dev))
13793                 bnx2x_set_power_state(bp, PCI_D0);
13794
13795         if (netif_running(dev)) {
13796                 BNX2X_ERR("IO slot reset --> driver unload\n");
13797
13798                 /* MCP should have been reset; Need to wait for validity */
13799                 bnx2x_init_shmem(bp);
13800
13801                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13802                         u32 v;
13803
13804                         v = SHMEM2_RD(bp,
13805                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13806                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13807                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13808                 }
13809                 bnx2x_drain_tx_queues(bp);
13810                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13811                 bnx2x_netif_stop(bp, 1);
13812                 bnx2x_free_irq(bp);
13813
13814                 /* Report UNLOAD_DONE to MCP */
13815                 bnx2x_send_unload_done(bp, true);
13816
13817                 bp->sp_state = 0;
13818                 bp->port.pmf = 0;
13819
13820                 bnx2x_prev_unload(bp);
13821
13822                 /* We should have reseted the engine, so It's fair to
13823                  * assume the FW will no longer write to the bnx2x driver.
13824                  */
13825                 bnx2x_squeeze_objects(bp);
13826                 bnx2x_free_skbs(bp);
13827                 for_each_rx_queue(bp, i)
13828                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13829                 bnx2x_free_fp_mem(bp);
13830                 bnx2x_free_mem(bp);
13831
13832                 bp->state = BNX2X_STATE_CLOSED;
13833         }
13834
13835         rtnl_unlock();
13836
13837         /* If AER, perform cleanup of the PCIe registers */
13838         if (bp->flags & AER_ENABLED) {
13839                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13840                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13841                 else
13842                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13843         }
13844
13845         return PCI_ERS_RESULT_RECOVERED;
13846 }
13847
13848 /**
13849  * bnx2x_io_resume - called when traffic can start flowing again
13850  * @pdev: Pointer to PCI device
13851  *
13852  * This callback is called when the error recovery driver tells us that
13853  * its OK to resume normal operation.
13854  */
13855 static void bnx2x_io_resume(struct pci_dev *pdev)
13856 {
13857         struct net_device *dev = pci_get_drvdata(pdev);
13858         struct bnx2x *bp = netdev_priv(dev);
13859
13860         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13861                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13862                 return;
13863         }
13864
13865         rtnl_lock();
13866
13867         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13868                                                         DRV_MSG_SEQ_NUMBER_MASK;
13869
13870         if (netif_running(dev))
13871                 bnx2x_nic_load(bp, LOAD_NORMAL);
13872
13873         netif_device_attach(dev);
13874
13875         rtnl_unlock();
13876 }
13877
13878 static const struct pci_error_handlers bnx2x_err_handler = {
13879         .error_detected = bnx2x_io_error_detected,
13880         .slot_reset     = bnx2x_io_slot_reset,
13881         .resume         = bnx2x_io_resume,
13882 };
13883
13884 static void bnx2x_shutdown(struct pci_dev *pdev)
13885 {
13886         struct net_device *dev = pci_get_drvdata(pdev);
13887         struct bnx2x *bp;
13888
13889         if (!dev)
13890                 return;
13891
13892         bp = netdev_priv(dev);
13893         if (!bp)
13894                 return;
13895
13896         rtnl_lock();
13897         netif_device_detach(dev);
13898         rtnl_unlock();
13899
13900         /* Don't remove the netdevice, as there are scenarios which will cause
13901          * the kernel to hang, e.g., when trying to remove bnx2i while the
13902          * rootfs is mounted from SAN.
13903          */
13904         __bnx2x_remove(pdev, dev, bp, false);
13905 }
13906
13907 static struct pci_driver bnx2x_pci_driver = {
13908         .name        = DRV_MODULE_NAME,
13909         .id_table    = bnx2x_pci_tbl,
13910         .probe       = bnx2x_init_one,
13911         .remove      = bnx2x_remove_one,
13912         .suspend     = bnx2x_suspend,
13913         .resume      = bnx2x_resume,
13914         .err_handler = &bnx2x_err_handler,
13915 #ifdef CONFIG_BNX2X_SRIOV
13916         .sriov_configure = bnx2x_sriov_configure,
13917 #endif
13918         .shutdown    = bnx2x_shutdown,
13919 };
13920
13921 static int __init bnx2x_init(void)
13922 {
13923         int ret;
13924
13925         pr_info("%s", version);
13926
13927         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13928         if (bnx2x_wq == NULL) {
13929                 pr_err("Cannot create workqueue\n");
13930                 return -ENOMEM;
13931         }
13932         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13933         if (!bnx2x_iov_wq) {
13934                 pr_err("Cannot create iov workqueue\n");
13935                 destroy_workqueue(bnx2x_wq);
13936                 return -ENOMEM;
13937         }
13938
13939         ret = pci_register_driver(&bnx2x_pci_driver);
13940         if (ret) {
13941                 pr_err("Cannot register driver\n");
13942                 destroy_workqueue(bnx2x_wq);
13943                 destroy_workqueue(bnx2x_iov_wq);
13944         }
13945         return ret;
13946 }
13947
13948 static void __exit bnx2x_cleanup(void)
13949 {
13950         struct list_head *pos, *q;
13951
13952         pci_unregister_driver(&bnx2x_pci_driver);
13953
13954         destroy_workqueue(bnx2x_wq);
13955         destroy_workqueue(bnx2x_iov_wq);
13956
13957         /* Free globally allocated resources */
13958         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13959                 struct bnx2x_prev_path_list *tmp =
13960                         list_entry(pos, struct bnx2x_prev_path_list, list);
13961                 list_del(pos);
13962                 kfree(tmp);
13963         }
13964 }
13965
13966 void bnx2x_notify_link_changed(struct bnx2x *bp)
13967 {
13968         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13969 }
13970
13971 module_init(bnx2x_init);
13972 module_exit(bnx2x_cleanup);
13973
13974 /**
13975  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13976  *
13977  * @bp:         driver handle
13978  * @set:        set or clear the CAM entry
13979  *
13980  * This function will wait until the ramrod completion returns.
13981  * Return 0 if success, -ENODEV if ramrod doesn't return.
13982  */
13983 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13984 {
13985         unsigned long ramrod_flags = 0;
13986
13987         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13988         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13989                                  &bp->iscsi_l2_mac_obj, true,
13990                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13991 }
13992
13993 /* count denotes the number of new completions we have seen */
13994 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13995 {
13996         struct eth_spe *spe;
13997         int cxt_index, cxt_offset;
13998
13999 #ifdef BNX2X_STOP_ON_ERROR
14000         if (unlikely(bp->panic))
14001                 return;
14002 #endif
14003
14004         spin_lock_bh(&bp->spq_lock);
14005         BUG_ON(bp->cnic_spq_pending < count);
14006         bp->cnic_spq_pending -= count;
14007
14008         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14009                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14010                                 & SPE_HDR_CONN_TYPE) >>
14011                                 SPE_HDR_CONN_TYPE_SHIFT;
14012                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14013                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14014
14015                 /* Set validation for iSCSI L2 client before sending SETUP
14016                  *  ramrod
14017                  */
14018                 if (type == ETH_CONNECTION_TYPE) {
14019                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14020                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14021                                         ILT_PAGE_CIDS;
14022                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14023                                         (cxt_index * ILT_PAGE_CIDS);
14024                                 bnx2x_set_ctx_validation(bp,
14025                                         &bp->context[cxt_index].
14026                                                          vcxt[cxt_offset].eth,
14027                                         BNX2X_ISCSI_ETH_CID(bp));
14028                         }
14029                 }
14030
14031                 /*
14032                  * There may be not more than 8 L2, not more than 8 L5 SPEs
14033                  * and in the air. We also check that number of outstanding
14034                  * COMMON ramrods is not more than the EQ and SPQ can
14035                  * accommodate.
14036                  */
14037                 if (type == ETH_CONNECTION_TYPE) {
14038                         if (!atomic_read(&bp->cq_spq_left))
14039                                 break;
14040                         else
14041                                 atomic_dec(&bp->cq_spq_left);
14042                 } else if (type == NONE_CONNECTION_TYPE) {
14043                         if (!atomic_read(&bp->eq_spq_left))
14044                                 break;
14045                         else
14046                                 atomic_dec(&bp->eq_spq_left);
14047                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14048                            (type == FCOE_CONNECTION_TYPE)) {
14049                         if (bp->cnic_spq_pending >=
14050                             bp->cnic_eth_dev.max_kwqe_pending)
14051                                 break;
14052                         else
14053                                 bp->cnic_spq_pending++;
14054                 } else {
14055                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14056                         bnx2x_panic();
14057                         break;
14058                 }
14059
14060                 spe = bnx2x_sp_get_next(bp);
14061                 *spe = *bp->cnic_kwq_cons;
14062
14063                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14064                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14065
14066                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14067                         bp->cnic_kwq_cons = bp->cnic_kwq;
14068                 else
14069                         bp->cnic_kwq_cons++;
14070         }
14071         bnx2x_sp_prod_update(bp);
14072         spin_unlock_bh(&bp->spq_lock);
14073 }
14074
14075 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14076                                struct kwqe_16 *kwqes[], u32 count)
14077 {
14078         struct bnx2x *bp = netdev_priv(dev);
14079         int i;
14080
14081 #ifdef BNX2X_STOP_ON_ERROR
14082         if (unlikely(bp->panic)) {
14083                 BNX2X_ERR("Can't post to SP queue while panic\n");
14084                 return -EIO;
14085         }
14086 #endif
14087
14088         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14089             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14090                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14091                 return -EAGAIN;
14092         }
14093
14094         spin_lock_bh(&bp->spq_lock);
14095
14096         for (i = 0; i < count; i++) {
14097                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14098
14099                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14100                         break;
14101
14102                 *bp->cnic_kwq_prod = *spe;
14103
14104                 bp->cnic_kwq_pending++;
14105
14106                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14107                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14108                    spe->data.update_data_addr.hi,
14109                    spe->data.update_data_addr.lo,
14110                    bp->cnic_kwq_pending);
14111
14112                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14113                         bp->cnic_kwq_prod = bp->cnic_kwq;
14114                 else
14115                         bp->cnic_kwq_prod++;
14116         }
14117
14118         spin_unlock_bh(&bp->spq_lock);
14119
14120         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14121                 bnx2x_cnic_sp_post(bp, 0);
14122
14123         return i;
14124 }
14125
14126 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14127 {
14128         struct cnic_ops *c_ops;
14129         int rc = 0;
14130
14131         mutex_lock(&bp->cnic_mutex);
14132         c_ops = rcu_dereference_protected(bp->cnic_ops,
14133                                           lockdep_is_held(&bp->cnic_mutex));
14134         if (c_ops)
14135                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14136         mutex_unlock(&bp->cnic_mutex);
14137
14138         return rc;
14139 }
14140
14141 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14142 {
14143         struct cnic_ops *c_ops;
14144         int rc = 0;
14145
14146         rcu_read_lock();
14147         c_ops = rcu_dereference(bp->cnic_ops);
14148         if (c_ops)
14149                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14150         rcu_read_unlock();
14151
14152         return rc;
14153 }
14154
14155 /*
14156  * for commands that have no data
14157  */
14158 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14159 {
14160         struct cnic_ctl_info ctl = {0};
14161
14162         ctl.cmd = cmd;
14163
14164         return bnx2x_cnic_ctl_send(bp, &ctl);
14165 }
14166
14167 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14168 {
14169         struct cnic_ctl_info ctl = {0};
14170
14171         /* first we tell CNIC and only then we count this as a completion */
14172         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14173         ctl.data.comp.cid = cid;
14174         ctl.data.comp.error = err;
14175
14176         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14177         bnx2x_cnic_sp_post(bp, 0);
14178 }
14179
14180 /* Called with netif_addr_lock_bh() taken.
14181  * Sets an rx_mode config for an iSCSI ETH client.
14182  * Doesn't block.
14183  * Completion should be checked outside.
14184  */
14185 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14186 {
14187         unsigned long accept_flags = 0, ramrod_flags = 0;
14188         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14189         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14190
14191         if (start) {
14192                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14193                  * because it's the only way for UIO Queue to accept
14194                  * multicasts (in non-promiscuous mode only one Queue per
14195                  * function will receive multicast packets (leading in our
14196                  * case).
14197                  */
14198                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14199                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14200                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14201                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14202
14203                 /* Clear STOP_PENDING bit if START is requested */
14204                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14205
14206                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14207         } else
14208                 /* Clear START_PENDING bit if STOP is requested */
14209                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14210
14211         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14212                 set_bit(sched_state, &bp->sp_state);
14213         else {
14214                 __set_bit(RAMROD_RX, &ramrod_flags);
14215                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14216                                     ramrod_flags);
14217         }
14218 }
14219
14220 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14221 {
14222         struct bnx2x *bp = netdev_priv(dev);
14223         int rc = 0;
14224
14225         switch (ctl->cmd) {
14226         case DRV_CTL_CTXTBL_WR_CMD: {
14227                 u32 index = ctl->data.io.offset;
14228                 dma_addr_t addr = ctl->data.io.dma_addr;
14229
14230                 bnx2x_ilt_wr(bp, index, addr);
14231                 break;
14232         }
14233
14234         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14235                 int count = ctl->data.credit.credit_count;
14236
14237                 bnx2x_cnic_sp_post(bp, count);
14238                 break;
14239         }
14240
14241         /* rtnl_lock is held.  */
14242         case DRV_CTL_START_L2_CMD: {
14243                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14244                 unsigned long sp_bits = 0;
14245
14246                 /* Configure the iSCSI classification object */
14247                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14248                                    cp->iscsi_l2_client_id,
14249                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14250                                    bnx2x_sp(bp, mac_rdata),
14251                                    bnx2x_sp_mapping(bp, mac_rdata),
14252                                    BNX2X_FILTER_MAC_PENDING,
14253                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14254                                    &bp->macs_pool);
14255
14256                 /* Set iSCSI MAC address */
14257                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14258                 if (rc)
14259                         break;
14260
14261                 mmiowb();
14262                 barrier();
14263
14264                 /* Start accepting on iSCSI L2 ring */
14265
14266                 netif_addr_lock_bh(dev);
14267                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14268                 netif_addr_unlock_bh(dev);
14269
14270                 /* bits to wait on */
14271                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14272                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14273
14274                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14275                         BNX2X_ERR("rx_mode completion timed out!\n");
14276
14277                 break;
14278         }
14279
14280         /* rtnl_lock is held.  */
14281         case DRV_CTL_STOP_L2_CMD: {
14282                 unsigned long sp_bits = 0;
14283
14284                 /* Stop accepting on iSCSI L2 ring */
14285                 netif_addr_lock_bh(dev);
14286                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14287                 netif_addr_unlock_bh(dev);
14288
14289                 /* bits to wait on */
14290                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14291                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14292
14293                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14294                         BNX2X_ERR("rx_mode completion timed out!\n");
14295
14296                 mmiowb();
14297                 barrier();
14298
14299                 /* Unset iSCSI L2 MAC */
14300                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14301                                         BNX2X_ISCSI_ETH_MAC, true);
14302                 break;
14303         }
14304         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14305                 int count = ctl->data.credit.credit_count;
14306
14307                 smp_mb__before_atomic();
14308                 atomic_add(count, &bp->cq_spq_left);
14309                 smp_mb__after_atomic();
14310                 break;
14311         }
14312         case DRV_CTL_ULP_REGISTER_CMD: {
14313                 int ulp_type = ctl->data.register_data.ulp_type;
14314
14315                 if (CHIP_IS_E3(bp)) {
14316                         int idx = BP_FW_MB_IDX(bp);
14317                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14318                         int path = BP_PATH(bp);
14319                         int port = BP_PORT(bp);
14320                         int i;
14321                         u32 scratch_offset;
14322                         u32 *host_addr;
14323
14324                         /* first write capability to shmem2 */
14325                         if (ulp_type == CNIC_ULP_ISCSI)
14326                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14327                         else if (ulp_type == CNIC_ULP_FCOE)
14328                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14329                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14330
14331                         if ((ulp_type != CNIC_ULP_FCOE) ||
14332                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14333                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14334                                 break;
14335
14336                         /* if reached here - should write fcoe capabilities */
14337                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14338                         if (!scratch_offset)
14339                                 break;
14340                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14341                                                    fcoe_features[path][port]);
14342                         host_addr = (u32 *) &(ctl->data.register_data.
14343                                               fcoe_features);
14344                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14345                              i += 4)
14346                                 REG_WR(bp, scratch_offset + i,
14347                                        *(host_addr + i/4));
14348                 }
14349                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14350                 break;
14351         }
14352
14353         case DRV_CTL_ULP_UNREGISTER_CMD: {
14354                 int ulp_type = ctl->data.ulp_type;
14355
14356                 if (CHIP_IS_E3(bp)) {
14357                         int idx = BP_FW_MB_IDX(bp);
14358                         u32 cap;
14359
14360                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14361                         if (ulp_type == CNIC_ULP_ISCSI)
14362                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14363                         else if (ulp_type == CNIC_ULP_FCOE)
14364                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14365                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14366                 }
14367                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14368                 break;
14369         }
14370
14371         default:
14372                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14373                 rc = -EINVAL;
14374         }
14375
14376         return rc;
14377 }
14378
14379 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14380 {
14381         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14382
14383         if (bp->flags & USING_MSIX_FLAG) {
14384                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14385                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14386                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14387         } else {
14388                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14389                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14390         }
14391         if (!CHIP_IS_E1x(bp))
14392                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14393         else
14394                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14395
14396         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14397         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14398         cp->irq_arr[1].status_blk = bp->def_status_blk;
14399         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14400         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14401
14402         cp->num_irq = 2;
14403 }
14404
14405 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14406 {
14407         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14408
14409         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14410                              bnx2x_cid_ilt_lines(bp);
14411         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14412         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14413         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14414
14415         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14416            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14417            cp->iscsi_l2_cid);
14418
14419         if (NO_ISCSI_OOO(bp))
14420                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14421 }
14422
14423 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14424                                void *data)
14425 {
14426         struct bnx2x *bp = netdev_priv(dev);
14427         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14428         int rc;
14429
14430         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14431
14432         if (ops == NULL) {
14433                 BNX2X_ERR("NULL ops received\n");
14434                 return -EINVAL;
14435         }
14436
14437         if (!CNIC_SUPPORT(bp)) {
14438                 BNX2X_ERR("Can't register CNIC when not supported\n");
14439                 return -EOPNOTSUPP;
14440         }
14441
14442         if (!CNIC_LOADED(bp)) {
14443                 rc = bnx2x_load_cnic(bp);
14444                 if (rc) {
14445                         BNX2X_ERR("CNIC-related load failed\n");
14446                         return rc;
14447                 }
14448         }
14449
14450         bp->cnic_enabled = true;
14451
14452         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14453         if (!bp->cnic_kwq)
14454                 return -ENOMEM;
14455
14456         bp->cnic_kwq_cons = bp->cnic_kwq;
14457         bp->cnic_kwq_prod = bp->cnic_kwq;
14458         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14459
14460         bp->cnic_spq_pending = 0;
14461         bp->cnic_kwq_pending = 0;
14462
14463         bp->cnic_data = data;
14464
14465         cp->num_irq = 0;
14466         cp->drv_state |= CNIC_DRV_STATE_REGD;
14467         cp->iro_arr = bp->iro_arr;
14468
14469         bnx2x_setup_cnic_irq_info(bp);
14470
14471         rcu_assign_pointer(bp->cnic_ops, ops);
14472
14473         /* Schedule driver to read CNIC driver versions */
14474         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14475
14476         return 0;
14477 }
14478
14479 static int bnx2x_unregister_cnic(struct net_device *dev)
14480 {
14481         struct bnx2x *bp = netdev_priv(dev);
14482         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14483
14484         mutex_lock(&bp->cnic_mutex);
14485         cp->drv_state = 0;
14486         RCU_INIT_POINTER(bp->cnic_ops, NULL);
14487         mutex_unlock(&bp->cnic_mutex);
14488         synchronize_rcu();
14489         bp->cnic_enabled = false;
14490         kfree(bp->cnic_kwq);
14491         bp->cnic_kwq = NULL;
14492
14493         return 0;
14494 }
14495
14496 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14497 {
14498         struct bnx2x *bp = netdev_priv(dev);
14499         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14500
14501         /* If both iSCSI and FCoE are disabled - return NULL in
14502          * order to indicate CNIC that it should not try to work
14503          * with this device.
14504          */
14505         if (NO_ISCSI(bp) && NO_FCOE(bp))
14506                 return NULL;
14507
14508         cp->drv_owner = THIS_MODULE;
14509         cp->chip_id = CHIP_ID(bp);
14510         cp->pdev = bp->pdev;
14511         cp->io_base = bp->regview;
14512         cp->io_base2 = bp->doorbells;
14513         cp->max_kwqe_pending = 8;
14514         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14515         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14516                              bnx2x_cid_ilt_lines(bp);
14517         cp->ctx_tbl_len = CNIC_ILT_LINES;
14518         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14519         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14520         cp->drv_ctl = bnx2x_drv_ctl;
14521         cp->drv_register_cnic = bnx2x_register_cnic;
14522         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14523         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14524         cp->iscsi_l2_client_id =
14525                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14526         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14527
14528         if (NO_ISCSI_OOO(bp))
14529                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14530
14531         if (NO_ISCSI(bp))
14532                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14533
14534         if (NO_FCOE(bp))
14535                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14536
14537         BNX2X_DEV_INFO(
14538                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14539            cp->ctx_blk_size,
14540            cp->ctx_tbl_offset,
14541            cp->ctx_tbl_len,
14542            cp->starting_cid);
14543         return cp;
14544 }
14545
14546 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14547 {
14548         struct bnx2x *bp = fp->bp;
14549         u32 offset = BAR_USTRORM_INTMEM;
14550
14551         if (IS_VF(bp))
14552                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14553         else if (!CHIP_IS_E1x(bp))
14554                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14555         else
14556                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14557
14558         return offset;
14559 }
14560
14561 /* called only on E1H or E2.
14562  * When pretending to be PF, the pretend value is the function number 0...7
14563  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14564  * combination
14565  */
14566 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14567 {
14568         u32 pretend_reg;
14569
14570         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14571                 return -1;
14572
14573         /* get my own pretend register */
14574         pretend_reg = bnx2x_get_pretend_reg(bp);
14575         REG_WR(bp, pretend_reg, pretend_func_val);
14576         REG_RD(bp, pretend_reg);
14577         return 0;
14578 }
14579
14580 static void bnx2x_ptp_task(struct work_struct *work)
14581 {
14582         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14583         int port = BP_PORT(bp);
14584         u32 val_seq;
14585         u64 timestamp, ns;
14586         struct skb_shared_hwtstamps shhwtstamps;
14587
14588         /* Read Tx timestamp registers */
14589         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14590                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14591         if (val_seq & 0x10000) {
14592                 /* There is a valid timestamp value */
14593                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14594                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14595                 timestamp <<= 32;
14596                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14597                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14598                 /* Reset timestamp register to allow new timestamp */
14599                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14600                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14601                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14602
14603                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14604                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14605                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14606                 dev_kfree_skb_any(bp->ptp_tx_skb);
14607                 bp->ptp_tx_skb = NULL;
14608
14609                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14610                    timestamp, ns);
14611         } else {
14612                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14613                 /* Reschedule to keep checking for a valid timestamp value */
14614                 schedule_work(&bp->ptp_task);
14615         }
14616 }
14617
14618 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14619 {
14620         int port = BP_PORT(bp);
14621         u64 timestamp, ns;
14622
14623         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14624                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14625         timestamp <<= 32;
14626         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14627                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14628
14629         /* Reset timestamp register to allow new timestamp */
14630         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14631                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14632
14633         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14634
14635         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14636
14637         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14638            timestamp, ns);
14639 }
14640
14641 /* Read the PHC */
14642 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14643 {
14644         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14645         int port = BP_PORT(bp);
14646         u32 wb_data[2];
14647         u64 phc_cycles;
14648
14649         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14650                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14651         phc_cycles = wb_data[1];
14652         phc_cycles = (phc_cycles << 32) + wb_data[0];
14653
14654         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14655
14656         return phc_cycles;
14657 }
14658
14659 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14660 {
14661         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14662         bp->cyclecounter.read = bnx2x_cyclecounter_read;
14663         bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
14664         bp->cyclecounter.shift = 1;
14665         bp->cyclecounter.mult = 1;
14666 }
14667
14668 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14669 {
14670         struct bnx2x_func_state_params func_params = {NULL};
14671         struct bnx2x_func_set_timesync_params *set_timesync_params =
14672                 &func_params.params.set_timesync;
14673
14674         /* Prepare parameters for function state transitions */
14675         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14676         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14677
14678         func_params.f_obj = &bp->func_obj;
14679         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14680
14681         /* Function parameters */
14682         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14683         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14684
14685         return bnx2x_func_state_change(bp, &func_params);
14686 }
14687
14688 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14689 {
14690         struct bnx2x_queue_state_params q_params;
14691         int rc, i;
14692
14693         /* send queue update ramrod to enable PTP packets */
14694         memset(&q_params, 0, sizeof(q_params));
14695         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14696         q_params.cmd = BNX2X_Q_CMD_UPDATE;
14697         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14698                   &q_params.params.update.update_flags);
14699         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14700                   &q_params.params.update.update_flags);
14701
14702         /* send the ramrod on all the queues of the PF */
14703         for_each_eth_queue(bp, i) {
14704                 struct bnx2x_fastpath *fp = &bp->fp[i];
14705
14706                 /* Set the appropriate Queue object */
14707                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14708
14709                 /* Update the Queue state */
14710                 rc = bnx2x_queue_state_change(bp, &q_params);
14711                 if (rc) {
14712                         BNX2X_ERR("Failed to enable PTP packets\n");
14713                         return rc;
14714                 }
14715         }
14716
14717         return 0;
14718 }
14719
14720 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14721 {
14722         int port = BP_PORT(bp);
14723         int rc;
14724
14725         if (!bp->hwtstamp_ioctl_called)
14726                 return 0;
14727
14728         switch (bp->tx_type) {
14729         case HWTSTAMP_TX_ON:
14730                 bp->flags |= TX_TIMESTAMPING_EN;
14731                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14732                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14733                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14734                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14735                 break;
14736         case HWTSTAMP_TX_ONESTEP_SYNC:
14737                 BNX2X_ERR("One-step timestamping is not supported\n");
14738                 return -ERANGE;
14739         }
14740
14741         switch (bp->rx_filter) {
14742         case HWTSTAMP_FILTER_NONE:
14743                 break;
14744         case HWTSTAMP_FILTER_ALL:
14745         case HWTSTAMP_FILTER_SOME:
14746                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14747                 break;
14748         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14749         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14750         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14751                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14752                 /* Initialize PTP detection for UDP/IPv4 events */
14753                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14754                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14755                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14756                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14757                 break;
14758         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14759         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14760         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14761                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14762                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14763                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14764                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14765                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14766                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14767                 break;
14768         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14769         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14770         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14771                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14772                 /* Initialize PTP detection L2 events */
14773                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14774                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14775                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14776                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14777
14778                 break;
14779         case HWTSTAMP_FILTER_PTP_V2_EVENT:
14780         case HWTSTAMP_FILTER_PTP_V2_SYNC:
14781         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14782                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14783                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14784                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14785                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14786                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14787                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14788                 break;
14789         }
14790
14791         /* Indicate to FW that this PF expects recorded PTP packets */
14792         rc = bnx2x_enable_ptp_packets(bp);
14793         if (rc)
14794                 return rc;
14795
14796         /* Enable sending PTP packets to host */
14797         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14798                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14799
14800         return 0;
14801 }
14802
14803 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14804 {
14805         struct hwtstamp_config config;
14806         int rc;
14807
14808         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14809
14810         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14811                 return -EFAULT;
14812
14813         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14814            config.tx_type, config.rx_filter);
14815
14816         if (config.flags) {
14817                 BNX2X_ERR("config.flags is reserved for future use\n");
14818                 return -EINVAL;
14819         }
14820
14821         bp->hwtstamp_ioctl_called = 1;
14822         bp->tx_type = config.tx_type;
14823         bp->rx_filter = config.rx_filter;
14824
14825         rc = bnx2x_configure_ptp_filters(bp);
14826         if (rc)
14827                 return rc;
14828
14829         config.rx_filter = bp->rx_filter;
14830
14831         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14832                 -EFAULT : 0;
14833 }
14834
14835 /* Configures HW for PTP */
14836 static int bnx2x_configure_ptp(struct bnx2x *bp)
14837 {
14838         int rc, port = BP_PORT(bp);
14839         u32 wb_data[2];
14840
14841         /* Reset PTP event detection rules - will be configured in the IOCTL */
14842         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14843                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14844         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14845                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14846         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14847                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14848         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14849                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14850
14851         /* Disable PTP packets to host - will be configured in the IOCTL*/
14852         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14853                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14854
14855         /* Enable the PTP feature */
14856         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14857                NIG_REG_P0_PTP_EN, 0x3F);
14858
14859         /* Enable the free-running counter */
14860         wb_data[0] = 0;
14861         wb_data[1] = 0;
14862         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14863
14864         /* Reset drift register (offset register is not reset) */
14865         rc = bnx2x_send_reset_timesync_ramrod(bp);
14866         if (rc) {
14867                 BNX2X_ERR("Failed to reset PHC drift register\n");
14868                 return -EFAULT;
14869         }
14870
14871         /* Reset possibly old timestamps */
14872         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14873                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14874         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14875                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14876
14877         return 0;
14878 }
14879
14880 /* Called during load, to initialize PTP-related stuff */
14881 void bnx2x_init_ptp(struct bnx2x *bp)
14882 {
14883         int rc;
14884
14885         /* Configure PTP in HW */
14886         rc = bnx2x_configure_ptp(bp);
14887         if (rc) {
14888                 BNX2X_ERR("Stopping PTP initialization\n");
14889                 return;
14890         }
14891
14892         /* Init work queue for Tx timestamping */
14893         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14894
14895         /* Init cyclecounter and timecounter. This is done only in the first
14896          * load. If done in every load, PTP application will fail when doing
14897          * unload / load (e.g. MTU change) while it is running.
14898          */
14899         if (!bp->timecounter_init_done) {
14900                 bnx2x_init_cyclecounter(bp);
14901                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14902                                  ktime_to_ns(ktime_get_real()));
14903                 bp->timecounter_init_done = 1;
14904         }
14905
14906         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14907 }