1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_vfpf.h"
63 #include "bnx2x_dcb.h"
66 #include <linux/firmware.h>
67 #include "bnx2x_fw_file_hdr.h"
69 #define FW_FILE_VERSION \
70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
73 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
74 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
76 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
78 /* Time in jiffies before concluding the transmitter is hung */
79 #define TX_TIMEOUT (5*HZ)
81 static char version[] =
82 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
83 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85 MODULE_AUTHOR("Eliezer Tamir");
86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
87 "BCM57710/57711/57711E/"
88 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
89 "57840/57840_MF Driver");
90 MODULE_LICENSE("GPL");
91 MODULE_VERSION(DRV_MODULE_VERSION);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1);
93 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
94 MODULE_FIRMWARE(FW_FILE_NAME_E2);
97 module_param(num_queues, int, 0);
98 MODULE_PARM_DESC(num_queues,
99 " Set number of queues (default is as a number of CPUs)");
101 static int disable_tpa;
102 module_param(disable_tpa, int, 0);
103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106 module_param(int_mode, int, 0);
107 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
110 static int dropless_fc;
111 module_param(dropless_fc, int, 0);
112 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114 static int mrrs = -1;
115 module_param(mrrs, int, 0);
116 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
119 module_param(debug, int, 0);
120 MODULE_PARM_DESC(debug, " Default debug msglevel");
122 struct workqueue_struct *bnx2x_wq;
124 struct bnx2x_mac_vals {
135 enum bnx2x_board_type {
159 /* indexed by board_type, above */
163 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
164 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
165 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
166 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
167 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
168 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
169 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
170 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
171 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
172 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
173 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
174 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
175 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
176 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
177 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
178 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
179 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
180 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
181 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
182 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
183 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
186 #ifndef PCI_DEVICE_ID_NX2_57710
187 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
189 #ifndef PCI_DEVICE_ID_NX2_57711
190 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
192 #ifndef PCI_DEVICE_ID_NX2_57711E
193 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
195 #ifndef PCI_DEVICE_ID_NX2_57712
196 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
198 #ifndef PCI_DEVICE_ID_NX2_57712_MF
199 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
201 #ifndef PCI_DEVICE_ID_NX2_57712_VF
202 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
204 #ifndef PCI_DEVICE_ID_NX2_57800
205 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
207 #ifndef PCI_DEVICE_ID_NX2_57800_MF
208 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
210 #ifndef PCI_DEVICE_ID_NX2_57800_VF
211 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
213 #ifndef PCI_DEVICE_ID_NX2_57810
214 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
216 #ifndef PCI_DEVICE_ID_NX2_57810_MF
217 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
219 #ifndef PCI_DEVICE_ID_NX2_57840_O
220 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
222 #ifndef PCI_DEVICE_ID_NX2_57810_VF
223 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
225 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
226 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
228 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
229 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
231 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
232 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
234 #ifndef PCI_DEVICE_ID_NX2_57840_MF
235 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
237 #ifndef PCI_DEVICE_ID_NX2_57840_VF
238 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
240 #ifndef PCI_DEVICE_ID_NX2_57811
241 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
243 #ifndef PCI_DEVICE_ID_NX2_57811_MF
244 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
246 #ifndef PCI_DEVICE_ID_NX2_57811_VF
247 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
250 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
251 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
252 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
275 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
277 /* Global resources for unloading a previously loaded device */
278 #define BNX2X_PREV_WAIT_NEEDED 1
279 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
280 static LIST_HEAD(bnx2x_prev_list);
281 /****************************************************************************
282 * General service functions
283 ****************************************************************************/
285 static void __storm_memset_dma_mapping(struct bnx2x *bp,
286 u32 addr, dma_addr_t mapping)
288 REG_WR(bp, addr, U64_LO(mapping));
289 REG_WR(bp, addr + 4, U64_HI(mapping));
292 static void storm_memset_spq_addr(struct bnx2x *bp,
293 dma_addr_t mapping, u16 abs_fid)
295 u32 addr = XSEM_REG_FAST_MEMORY +
296 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
298 __storm_memset_dma_mapping(bp, addr, mapping);
301 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
304 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
306 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
308 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
310 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
314 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
317 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
319 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
321 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
323 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
327 static void storm_memset_eq_data(struct bnx2x *bp,
328 struct event_ring_data *eq_data,
331 size_t size = sizeof(struct event_ring_data);
333 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
335 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
338 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
341 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
342 REG_WR16(bp, addr, eq_prod);
346 * locking is done by mcp
348 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
350 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
351 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
352 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
353 PCICFG_VENDOR_ID_OFFSET);
356 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
360 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
361 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
362 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
363 PCICFG_VENDOR_ID_OFFSET);
368 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
369 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
370 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
371 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
372 #define DMAE_DP_DST_NONE "dst_addr [none]"
374 static void bnx2x_dp_dmae(struct bnx2x *bp,
375 struct dmae_command *dmae, int msglvl)
377 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
380 switch (dmae->opcode & DMAE_COMMAND_DST) {
381 case DMAE_CMD_DST_PCI:
382 if (src_type == DMAE_CMD_SRC_PCI)
383 DP(msglvl, "DMAE: opcode 0x%08x\n"
384 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
385 "comp_addr [%x:%08x], comp_val 0x%08x\n",
386 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
387 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
388 dmae->comp_addr_hi, dmae->comp_addr_lo,
391 DP(msglvl, "DMAE: opcode 0x%08x\n"
392 "src [%08x], len [%d*4], dst [%x:%08x]\n"
393 "comp_addr [%x:%08x], comp_val 0x%08x\n",
394 dmae->opcode, dmae->src_addr_lo >> 2,
395 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
396 dmae->comp_addr_hi, dmae->comp_addr_lo,
399 case DMAE_CMD_DST_GRC:
400 if (src_type == DMAE_CMD_SRC_PCI)
401 DP(msglvl, "DMAE: opcode 0x%08x\n"
402 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
403 "comp_addr [%x:%08x], comp_val 0x%08x\n",
404 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
405 dmae->len, dmae->dst_addr_lo >> 2,
406 dmae->comp_addr_hi, dmae->comp_addr_lo,
409 DP(msglvl, "DMAE: opcode 0x%08x\n"
410 "src [%08x], len [%d*4], dst [%08x]\n"
411 "comp_addr [%x:%08x], comp_val 0x%08x\n",
412 dmae->opcode, dmae->src_addr_lo >> 2,
413 dmae->len, dmae->dst_addr_lo >> 2,
414 dmae->comp_addr_hi, dmae->comp_addr_lo,
418 if (src_type == DMAE_CMD_SRC_PCI)
419 DP(msglvl, "DMAE: opcode 0x%08x\n"
420 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
421 "comp_addr [%x:%08x] comp_val 0x%08x\n",
422 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
423 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
426 DP(msglvl, "DMAE: opcode 0x%08x\n"
427 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
428 "comp_addr [%x:%08x] comp_val 0x%08x\n",
429 dmae->opcode, dmae->src_addr_lo >> 2,
430 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
435 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
436 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
437 i, *(((u32 *)dmae) + i));
440 /* copy command into DMAE command memory and set DMAE command go */
441 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
446 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
447 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
448 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
450 REG_WR(bp, dmae_reg_go_c[idx], 1);
453 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
455 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
459 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
461 return opcode & ~DMAE_CMD_SRC_RESET;
464 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
465 bool with_comp, u8 comp_type)
469 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
470 (dst_type << DMAE_COMMAND_DST_SHIFT));
472 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
474 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
475 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
476 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
477 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
480 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
482 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
485 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
489 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
490 struct dmae_command *dmae,
491 u8 src_type, u8 dst_type)
493 memset(dmae, 0, sizeof(struct dmae_command));
496 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
497 true, DMAE_COMP_PCI);
499 /* fill in the completion parameters */
500 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
501 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
502 dmae->comp_val = DMAE_COMP_VAL;
505 /* issue a dmae command over the init-channel and wait for completion */
506 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
508 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
509 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
512 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
514 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
515 * as long as this code is called both from syscall context and
516 * from ndo_set_rx_mode() flow that may be called from BH.
518 spin_lock_bh(&bp->dmae_lock);
520 /* reset completion */
523 /* post the command on the channel used for initializations */
524 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
526 /* wait for completion */
528 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
531 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
532 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
533 BNX2X_ERR("DMAE timeout!\n");
540 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
541 BNX2X_ERR("DMAE PCI error!\n");
546 spin_unlock_bh(&bp->dmae_lock);
550 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
554 struct dmae_command dmae;
556 if (!bp->dmae_ready) {
557 u32 *data = bnx2x_sp(bp, wb_data[0]);
560 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
562 bnx2x_init_str_wr(bp, dst_addr, data, len32);
566 /* set opcode and fixed command fields */
567 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
569 /* fill in addresses and len */
570 dmae.src_addr_lo = U64_LO(dma_addr);
571 dmae.src_addr_hi = U64_HI(dma_addr);
572 dmae.dst_addr_lo = dst_addr >> 2;
573 dmae.dst_addr_hi = 0;
576 /* issue the command and wait for completion */
577 rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
579 BNX2X_ERR("DMAE returned failure %d\n", rc);
584 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
587 struct dmae_command dmae;
589 if (!bp->dmae_ready) {
590 u32 *data = bnx2x_sp(bp, wb_data[0]);
594 for (i = 0; i < len32; i++)
595 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
597 for (i = 0; i < len32; i++)
598 data[i] = REG_RD(bp, src_addr + i*4);
603 /* set opcode and fixed command fields */
604 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
606 /* fill in addresses and len */
607 dmae.src_addr_lo = src_addr >> 2;
608 dmae.src_addr_hi = 0;
609 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
610 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
613 /* issue the command and wait for completion */
614 rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
616 BNX2X_ERR("DMAE returned failure %d\n", rc);
621 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
624 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
627 while (len > dmae_wr_max) {
628 bnx2x_write_dmae(bp, phys_addr + offset,
629 addr + offset, dmae_wr_max);
630 offset += dmae_wr_max * 4;
634 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
637 static int bnx2x_mc_assert(struct bnx2x *bp)
641 u32 row0, row1, row2, row3;
644 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
645 XSTORM_ASSERT_LIST_INDEX_OFFSET);
647 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
649 /* print the asserts */
650 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
652 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
653 XSTORM_ASSERT_LIST_OFFSET(i));
654 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
655 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
656 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
657 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
658 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
659 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
661 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
662 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
663 i, row3, row2, row1, row0);
671 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
672 TSTORM_ASSERT_LIST_INDEX_OFFSET);
674 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
676 /* print the asserts */
677 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
679 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
680 TSTORM_ASSERT_LIST_OFFSET(i));
681 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
682 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
683 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
684 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
685 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
686 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
688 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
689 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
690 i, row3, row2, row1, row0);
698 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
699 CSTORM_ASSERT_LIST_INDEX_OFFSET);
701 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
703 /* print the asserts */
704 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
706 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
707 CSTORM_ASSERT_LIST_OFFSET(i));
708 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
709 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
710 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
711 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
712 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
713 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
715 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
716 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
717 i, row3, row2, row1, row0);
725 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
726 USTORM_ASSERT_LIST_INDEX_OFFSET);
728 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
730 /* print the asserts */
731 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
733 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
734 USTORM_ASSERT_LIST_OFFSET(i));
735 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
736 USTORM_ASSERT_LIST_OFFSET(i) + 4);
737 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
738 USTORM_ASSERT_LIST_OFFSET(i) + 8);
739 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
740 USTORM_ASSERT_LIST_OFFSET(i) + 12);
742 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
743 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
744 i, row3, row2, row1, row0);
754 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
760 u32 trace_shmem_base;
762 BNX2X_ERR("NO MCP - can not dump\n");
765 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
766 (bp->common.bc_ver & 0xff0000) >> 16,
767 (bp->common.bc_ver & 0xff00) >> 8,
768 (bp->common.bc_ver & 0xff));
770 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
771 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
772 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
774 if (BP_PATH(bp) == 0)
775 trace_shmem_base = bp->common.shmem_base;
777 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
778 addr = trace_shmem_base - 0x800;
780 /* validate TRCB signature */
781 mark = REG_RD(bp, addr);
782 if (mark != MFW_TRACE_SIGNATURE) {
783 BNX2X_ERR("Trace buffer signature is missing.");
787 /* read cyclic buffer pointer */
789 mark = REG_RD(bp, addr);
790 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
791 + ((mark + 0x3) & ~0x3) - 0x08000000;
792 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
796 /* dump buffer after the mark */
797 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
798 for (word = 0; word < 8; word++)
799 data[word] = htonl(REG_RD(bp, offset + 4*word));
801 pr_cont("%s", (char *)data);
804 /* dump buffer before the mark */
805 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
806 for (word = 0; word < 8; word++)
807 data[word] = htonl(REG_RD(bp, offset + 4*word));
809 pr_cont("%s", (char *)data);
811 printk("%s" "end of fw dump\n", lvl);
814 static void bnx2x_fw_dump(struct bnx2x *bp)
816 bnx2x_fw_dump_lvl(bp, KERN_ERR);
819 static void bnx2x_hc_int_disable(struct bnx2x *bp)
821 int port = BP_PORT(bp);
822 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
823 u32 val = REG_RD(bp, addr);
825 /* in E1 we must use only PCI configuration space to disable
826 * MSI/MSIX capability
827 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
829 if (CHIP_IS_E1(bp)) {
830 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
831 * Use mask register to prevent from HC sending interrupts
832 * after we exit the function
834 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
836 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
837 HC_CONFIG_0_REG_INT_LINE_EN_0 |
838 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
840 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
841 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
842 HC_CONFIG_0_REG_INT_LINE_EN_0 |
843 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
846 "write %x to HC %d (addr 0x%x)\n",
849 /* flush all outstanding writes */
852 REG_WR(bp, addr, val);
853 if (REG_RD(bp, addr) != val)
854 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
857 static void bnx2x_igu_int_disable(struct bnx2x *bp)
859 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
861 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
862 IGU_PF_CONF_INT_LINE_EN |
863 IGU_PF_CONF_ATTN_BIT_EN);
865 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
867 /* flush all outstanding writes */
870 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
871 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
872 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
875 static void bnx2x_int_disable(struct bnx2x *bp)
877 if (bp->common.int_block == INT_BLOCK_HC)
878 bnx2x_hc_int_disable(bp);
880 bnx2x_igu_int_disable(bp);
883 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
887 struct hc_sp_status_block_data sp_sb_data;
888 int func = BP_FUNC(bp);
889 #ifdef BNX2X_STOP_ON_ERROR
890 u16 start = 0, end = 0;
894 bnx2x_int_disable(bp);
896 bp->stats_state = STATS_STATE_DISABLED;
897 bp->eth_stats.unrecoverable_error++;
898 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
900 BNX2X_ERR("begin crash dump -----------------\n");
904 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
905 bp->def_idx, bp->def_att_idx, bp->attn_state,
906 bp->spq_prod_idx, bp->stats_counter);
907 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
908 bp->def_status_blk->atten_status_block.attn_bits,
909 bp->def_status_blk->atten_status_block.attn_bits_ack,
910 bp->def_status_blk->atten_status_block.status_block_id,
911 bp->def_status_blk->atten_status_block.attn_bits_index);
913 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
915 bp->def_status_blk->sp_sb.index_values[i],
916 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
918 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
919 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
920 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
923 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
924 sp_sb_data.igu_sb_id,
925 sp_sb_data.igu_seg_id,
926 sp_sb_data.p_func.pf_id,
927 sp_sb_data.p_func.vnic_id,
928 sp_sb_data.p_func.vf_id,
929 sp_sb_data.p_func.vf_valid,
932 for_each_eth_queue(bp, i) {
933 struct bnx2x_fastpath *fp = &bp->fp[i];
935 struct hc_status_block_data_e2 sb_data_e2;
936 struct hc_status_block_data_e1x sb_data_e1x;
937 struct hc_status_block_sm *hc_sm_p =
939 sb_data_e1x.common.state_machine :
940 sb_data_e2.common.state_machine;
941 struct hc_index_data *hc_index_p =
943 sb_data_e1x.index_data :
944 sb_data_e2.index_data;
947 struct bnx2x_fp_txdata txdata;
950 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
951 i, fp->rx_bd_prod, fp->rx_bd_cons,
953 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
954 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
955 fp->rx_sge_prod, fp->last_max_sge,
956 le16_to_cpu(fp->fp_hc_idx));
959 for_each_cos_in_tx_queue(fp, cos)
961 txdata = *fp->txdata_ptr[cos];
962 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
963 i, txdata.tx_pkt_prod,
964 txdata.tx_pkt_cons, txdata.tx_bd_prod,
966 le16_to_cpu(*txdata.tx_cons_sb));
969 loop = CHIP_IS_E1x(bp) ?
970 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
977 BNX2X_ERR(" run indexes (");
978 for (j = 0; j < HC_SB_MAX_SM; j++)
980 fp->sb_running_index[j],
981 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
983 BNX2X_ERR(" indexes (");
984 for (j = 0; j < loop; j++)
986 fp->sb_index_values[j],
987 (j == loop - 1) ? ")" : " ");
989 data_size = CHIP_IS_E1x(bp) ?
990 sizeof(struct hc_status_block_data_e1x) :
991 sizeof(struct hc_status_block_data_e2);
992 data_size /= sizeof(u32);
993 sb_data_p = CHIP_IS_E1x(bp) ?
994 (u32 *)&sb_data_e1x :
996 /* copy sb data in here */
997 for (j = 0; j < data_size; j++)
998 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
999 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1002 if (!CHIP_IS_E1x(bp)) {
1003 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1004 sb_data_e2.common.p_func.pf_id,
1005 sb_data_e2.common.p_func.vf_id,
1006 sb_data_e2.common.p_func.vf_valid,
1007 sb_data_e2.common.p_func.vnic_id,
1008 sb_data_e2.common.same_igu_sb_1b,
1009 sb_data_e2.common.state);
1011 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1012 sb_data_e1x.common.p_func.pf_id,
1013 sb_data_e1x.common.p_func.vf_id,
1014 sb_data_e1x.common.p_func.vf_valid,
1015 sb_data_e1x.common.p_func.vnic_id,
1016 sb_data_e1x.common.same_igu_sb_1b,
1017 sb_data_e1x.common.state);
1021 for (j = 0; j < HC_SB_MAX_SM; j++) {
1022 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1023 j, hc_sm_p[j].__flags,
1024 hc_sm_p[j].igu_sb_id,
1025 hc_sm_p[j].igu_seg_id,
1026 hc_sm_p[j].time_to_expire,
1027 hc_sm_p[j].timer_value);
1031 for (j = 0; j < loop; j++) {
1032 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1033 hc_index_p[j].flags,
1034 hc_index_p[j].timeout);
1038 #ifdef BNX2X_STOP_ON_ERROR
1041 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1042 for (i = 0; i < NUM_EQ_DESC; i++) {
1043 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1045 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1046 i, bp->eq_ring[i].message.opcode,
1047 bp->eq_ring[i].message.error);
1048 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1053 for_each_valid_rx_queue(bp, i) {
1054 struct bnx2x_fastpath *fp = &bp->fp[i];
1056 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1057 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1058 for (j = start; j != end; j = RX_BD(j + 1)) {
1059 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1060 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1062 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1063 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1066 start = RX_SGE(fp->rx_sge_prod);
1067 end = RX_SGE(fp->last_max_sge);
1068 for (j = start; j != end; j = RX_SGE(j + 1)) {
1069 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1070 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1072 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1073 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1076 start = RCQ_BD(fp->rx_comp_cons - 10);
1077 end = RCQ_BD(fp->rx_comp_cons + 503);
1078 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1079 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1081 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1082 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1087 for_each_valid_tx_queue(bp, i) {
1088 struct bnx2x_fastpath *fp = &bp->fp[i];
1089 for_each_cos_in_tx_queue(fp, cos) {
1090 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1092 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1093 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1094 for (j = start; j != end; j = TX_BD(j + 1)) {
1095 struct sw_tx_bd *sw_bd =
1096 &txdata->tx_buf_ring[j];
1098 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1099 i, cos, j, sw_bd->skb,
1103 start = TX_BD(txdata->tx_bd_cons - 10);
1104 end = TX_BD(txdata->tx_bd_cons + 254);
1105 for (j = start; j != end; j = TX_BD(j + 1)) {
1106 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1108 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1109 i, cos, j, tx_bd[0], tx_bd[1],
1110 tx_bd[2], tx_bd[3]);
1116 bnx2x_mc_assert(bp);
1117 BNX2X_ERR("end crash dump -----------------\n");
1121 * FLR Support for E2
1123 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1126 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1127 #define FLR_WAIT_INTERVAL 50 /* usec */
1128 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1130 struct pbf_pN_buf_regs {
1137 struct pbf_pN_cmd_regs {
1143 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1144 struct pbf_pN_buf_regs *regs,
1147 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1148 u32 cur_cnt = poll_count;
1150 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1151 crd = crd_start = REG_RD(bp, regs->crd);
1152 init_crd = REG_RD(bp, regs->init_crd);
1154 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1155 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1156 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1158 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1159 (init_crd - crd_start))) {
1161 udelay(FLR_WAIT_INTERVAL);
1162 crd = REG_RD(bp, regs->crd);
1163 crd_freed = REG_RD(bp, regs->crd_freed);
1165 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1167 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1169 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1170 regs->pN, crd_freed);
1174 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1175 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1178 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1179 struct pbf_pN_cmd_regs *regs,
1182 u32 occup, to_free, freed, freed_start;
1183 u32 cur_cnt = poll_count;
1185 occup = to_free = REG_RD(bp, regs->lines_occup);
1186 freed = freed_start = REG_RD(bp, regs->lines_freed);
1188 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1189 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1191 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1193 udelay(FLR_WAIT_INTERVAL);
1194 occup = REG_RD(bp, regs->lines_occup);
1195 freed = REG_RD(bp, regs->lines_freed);
1197 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1199 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1201 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1206 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1207 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1210 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1211 u32 expected, u32 poll_count)
1213 u32 cur_cnt = poll_count;
1216 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1217 udelay(FLR_WAIT_INTERVAL);
1222 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1223 char *msg, u32 poll_cnt)
1225 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1227 BNX2X_ERR("%s usage count=%d\n", msg, val);
1233 /* Common routines with VF FLR cleanup */
1234 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1236 /* adjust polling timeout */
1237 if (CHIP_REV_IS_EMUL(bp))
1238 return FLR_POLL_CNT * 2000;
1240 if (CHIP_REV_IS_FPGA(bp))
1241 return FLR_POLL_CNT * 120;
1243 return FLR_POLL_CNT;
1246 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1248 struct pbf_pN_cmd_regs cmd_regs[] = {
1249 {0, (CHIP_IS_E3B0(bp)) ?
1250 PBF_REG_TQ_OCCUPANCY_Q0 :
1251 PBF_REG_P0_TQ_OCCUPANCY,
1252 (CHIP_IS_E3B0(bp)) ?
1253 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1254 PBF_REG_P0_TQ_LINES_FREED_CNT},
1255 {1, (CHIP_IS_E3B0(bp)) ?
1256 PBF_REG_TQ_OCCUPANCY_Q1 :
1257 PBF_REG_P1_TQ_OCCUPANCY,
1258 (CHIP_IS_E3B0(bp)) ?
1259 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1260 PBF_REG_P1_TQ_LINES_FREED_CNT},
1261 {4, (CHIP_IS_E3B0(bp)) ?
1262 PBF_REG_TQ_OCCUPANCY_LB_Q :
1263 PBF_REG_P4_TQ_OCCUPANCY,
1264 (CHIP_IS_E3B0(bp)) ?
1265 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1266 PBF_REG_P4_TQ_LINES_FREED_CNT}
1269 struct pbf_pN_buf_regs buf_regs[] = {
1270 {0, (CHIP_IS_E3B0(bp)) ?
1271 PBF_REG_INIT_CRD_Q0 :
1272 PBF_REG_P0_INIT_CRD ,
1273 (CHIP_IS_E3B0(bp)) ?
1276 (CHIP_IS_E3B0(bp)) ?
1277 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1278 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1279 {1, (CHIP_IS_E3B0(bp)) ?
1280 PBF_REG_INIT_CRD_Q1 :
1281 PBF_REG_P1_INIT_CRD,
1282 (CHIP_IS_E3B0(bp)) ?
1285 (CHIP_IS_E3B0(bp)) ?
1286 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1287 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1288 {4, (CHIP_IS_E3B0(bp)) ?
1289 PBF_REG_INIT_CRD_LB_Q :
1290 PBF_REG_P4_INIT_CRD,
1291 (CHIP_IS_E3B0(bp)) ?
1292 PBF_REG_CREDIT_LB_Q :
1294 (CHIP_IS_E3B0(bp)) ?
1295 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1296 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1301 /* Verify the command queues are flushed P0, P1, P4 */
1302 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1303 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1305 /* Verify the transmission buffers are flushed P0, P1, P4 */
1306 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1307 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1310 #define OP_GEN_PARAM(param) \
1311 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1313 #define OP_GEN_TYPE(type) \
1314 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1316 #define OP_GEN_AGG_VECT(index) \
1317 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1319 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1321 u32 op_gen_command = 0;
1322 u32 comp_addr = BAR_CSTRORM_INTMEM +
1323 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1326 if (REG_RD(bp, comp_addr)) {
1327 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1331 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1332 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1333 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1334 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1336 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1337 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1339 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1340 BNX2X_ERR("FW final cleanup did not succeed\n");
1341 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1342 (REG_RD(bp, comp_addr)));
1346 /* Zero completion for next FLR */
1347 REG_WR(bp, comp_addr, 0);
1352 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1356 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1357 return status & PCI_EXP_DEVSTA_TRPND;
1360 /* PF FLR specific routines
1362 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1364 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1365 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1366 CFC_REG_NUM_LCIDS_INSIDE_PF,
1367 "CFC PF usage counter timed out",
1371 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1372 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1373 DORQ_REG_PF_USAGE_CNT,
1374 "DQ PF usage counter timed out",
1378 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1379 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1380 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1381 "QM PF usage counter timed out",
1385 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1386 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1387 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1388 "Timers VNIC usage counter timed out",
1391 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1392 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1393 "Timers NUM_SCANS usage counter timed out",
1397 /* Wait DMAE PF usage counter to zero */
1398 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1399 dmae_reg_go_c[INIT_DMAE_C(bp)],
1400 "DMAE command register timed out",
1407 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1411 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1412 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1414 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1415 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1417 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1418 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1420 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1421 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1423 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1424 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1426 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1427 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1429 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1430 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1432 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1433 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1437 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1439 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1441 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1443 /* Re-enable PF target read access */
1444 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1446 /* Poll HW usage counters */
1447 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1448 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1451 /* Zero the igu 'trailing edge' and 'leading edge' */
1453 /* Send the FW cleanup command */
1454 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1459 /* Verify TX hw is flushed */
1460 bnx2x_tx_hw_flushed(bp, poll_cnt);
1462 /* Wait 100ms (not adjusted according to platform) */
1465 /* Verify no pending pci transactions */
1466 if (bnx2x_is_pcie_pending(bp->pdev))
1467 BNX2X_ERR("PCIE Transactions still pending\n");
1470 bnx2x_hw_enable_status(bp);
1473 * Master enable - Due to WB DMAE writes performed before this
1474 * register is re-initialized as part of the regular function init
1476 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1481 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1483 int port = BP_PORT(bp);
1484 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1485 u32 val = REG_RD(bp, addr);
1486 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1487 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1488 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1491 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1492 HC_CONFIG_0_REG_INT_LINE_EN_0);
1493 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1494 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1496 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1498 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1499 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1500 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1501 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1503 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1504 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1505 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1506 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1508 if (!CHIP_IS_E1(bp)) {
1510 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1512 REG_WR(bp, addr, val);
1514 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1519 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1522 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1523 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1525 REG_WR(bp, addr, val);
1527 * Ensure that HC_CONFIG is written before leading/trailing edge config
1532 if (!CHIP_IS_E1(bp)) {
1533 /* init leading/trailing edge */
1535 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1537 /* enable nig and gpio3 attention */
1542 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1543 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1546 /* Make sure that interrupts are indeed enabled from here on */
1550 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1553 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1554 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1555 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1557 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1560 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1561 IGU_PF_CONF_SINGLE_ISR_EN);
1562 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1563 IGU_PF_CONF_ATTN_BIT_EN);
1566 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1568 val &= ~IGU_PF_CONF_INT_LINE_EN;
1569 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1570 IGU_PF_CONF_ATTN_BIT_EN |
1571 IGU_PF_CONF_SINGLE_ISR_EN);
1573 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1574 val |= (IGU_PF_CONF_INT_LINE_EN |
1575 IGU_PF_CONF_ATTN_BIT_EN |
1576 IGU_PF_CONF_SINGLE_ISR_EN);
1579 /* Clean previous status - need to configure igu prior to ack*/
1580 if ((!msix) || single_msix) {
1581 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1585 val |= IGU_PF_CONF_FUNC_EN;
1587 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1588 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1590 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1592 if (val & IGU_PF_CONF_INT_LINE_EN)
1593 pci_intx(bp->pdev, true);
1597 /* init leading/trailing edge */
1599 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1601 /* enable nig and gpio3 attention */
1606 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1607 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1609 /* Make sure that interrupts are indeed enabled from here on */
1613 void bnx2x_int_enable(struct bnx2x *bp)
1615 if (bp->common.int_block == INT_BLOCK_HC)
1616 bnx2x_hc_int_enable(bp);
1618 bnx2x_igu_int_enable(bp);
1621 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1623 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1627 /* prevent the HW from sending interrupts */
1628 bnx2x_int_disable(bp);
1630 /* make sure all ISRs are done */
1632 synchronize_irq(bp->msix_table[0].vector);
1634 if (CNIC_SUPPORT(bp))
1636 for_each_eth_queue(bp, i)
1637 synchronize_irq(bp->msix_table[offset++].vector);
1639 synchronize_irq(bp->pdev->irq);
1641 /* make sure sp_task is not running */
1642 cancel_delayed_work(&bp->sp_task);
1643 cancel_delayed_work(&bp->period_task);
1644 flush_workqueue(bnx2x_wq);
1650 * General service functions
1653 /* Return true if succeeded to acquire the lock */
1654 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1657 u32 resource_bit = (1 << resource);
1658 int func = BP_FUNC(bp);
1659 u32 hw_lock_control_reg;
1661 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1662 "Trying to take a lock on resource %d\n", resource);
1664 /* Validating that the resource is within range */
1665 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1666 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1667 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1668 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1673 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1675 hw_lock_control_reg =
1676 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1678 /* Try to acquire the lock */
1679 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1680 lock_status = REG_RD(bp, hw_lock_control_reg);
1681 if (lock_status & resource_bit)
1684 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1685 "Failed to get a lock on resource %d\n", resource);
1690 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1692 * @bp: driver handle
1694 * Returns the recovery leader resource id according to the engine this function
1695 * belongs to. Currently only only 2 engines is supported.
1697 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1700 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1702 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1706 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1708 * @bp: driver handle
1710 * Tries to acquire a leader lock for current engine.
1712 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1714 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1717 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1719 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1720 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1722 /* Set the interrupt occurred bit for the sp-task to recognize it
1723 * must ack the interrupt and transition according to the IGU
1726 atomic_set(&bp->interrupt_occurred, 1);
1728 /* The sp_task must execute only after this bit
1729 * is set, otherwise we will get out of sync and miss all
1730 * further interrupts. Hence, the barrier.
1734 /* schedule sp_task to workqueue */
1735 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1738 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1740 struct bnx2x *bp = fp->bp;
1741 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1742 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1743 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1744 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1747 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1748 fp->index, cid, command, bp->state,
1749 rr_cqe->ramrod_cqe.ramrod_type);
1751 /* If cid is within VF range, replace the slowpath object with the
1752 * one corresponding to this VF
1754 if (cid >= BNX2X_FIRST_VF_CID &&
1755 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1756 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1759 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1760 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1761 drv_cmd = BNX2X_Q_CMD_UPDATE;
1764 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1765 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1766 drv_cmd = BNX2X_Q_CMD_SETUP;
1769 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1770 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1771 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1774 case (RAMROD_CMD_ID_ETH_HALT):
1775 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1776 drv_cmd = BNX2X_Q_CMD_HALT;
1779 case (RAMROD_CMD_ID_ETH_TERMINATE):
1780 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1781 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1784 case (RAMROD_CMD_ID_ETH_EMPTY):
1785 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1786 drv_cmd = BNX2X_Q_CMD_EMPTY;
1790 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1791 command, fp->index);
1795 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1796 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1797 /* q_obj->complete_cmd() failure means that this was
1798 * an unexpected completion.
1800 * In this case we don't want to increase the bp->spq_left
1801 * because apparently we haven't sent this command the first
1804 #ifdef BNX2X_STOP_ON_ERROR
1809 /* SRIOV: reschedule any 'in_progress' operations */
1810 bnx2x_iov_sp_event(bp, cid, true);
1812 smp_mb__before_atomic_inc();
1813 atomic_inc(&bp->cq_spq_left);
1814 /* push the change in bp->spq_left and towards the memory */
1815 smp_mb__after_atomic_inc();
1817 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1819 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1820 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1821 /* if Q update ramrod is completed for last Q in AFEX vif set
1822 * flow, then ACK MCP at the end
1824 * mark pending ACK to MCP bit.
1825 * prevent case that both bits are cleared.
1826 * At the end of load/unload driver checks that
1827 * sp_state is cleared, and this order prevents
1830 smp_mb__before_clear_bit();
1831 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1833 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1834 smp_mb__after_clear_bit();
1836 /* schedule the sp task as mcp ack is required */
1837 bnx2x_schedule_sp_task(bp);
1843 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1845 struct bnx2x *bp = netdev_priv(dev_instance);
1846 u16 status = bnx2x_ack_int(bp);
1851 /* Return here if interrupt is shared and it's not for us */
1852 if (unlikely(status == 0)) {
1853 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1856 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1858 #ifdef BNX2X_STOP_ON_ERROR
1859 if (unlikely(bp->panic))
1863 for_each_eth_queue(bp, i) {
1864 struct bnx2x_fastpath *fp = &bp->fp[i];
1866 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1867 if (status & mask) {
1868 /* Handle Rx or Tx according to SB id */
1869 for_each_cos_in_tx_queue(fp, cos)
1870 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1871 prefetch(&fp->sb_running_index[SM_RX_ID]);
1872 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1877 if (CNIC_SUPPORT(bp)) {
1879 if (status & (mask | 0x1)) {
1880 struct cnic_ops *c_ops = NULL;
1883 c_ops = rcu_dereference(bp->cnic_ops);
1884 if (c_ops && (bp->cnic_eth_dev.drv_state &
1885 CNIC_DRV_STATE_HANDLES_IRQ))
1886 c_ops->cnic_handler(bp->cnic_data, NULL);
1893 if (unlikely(status & 0x1)) {
1895 /* schedule sp task to perform default status block work, ack
1896 * attentions and enable interrupts.
1898 bnx2x_schedule_sp_task(bp);
1905 if (unlikely(status))
1906 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1915 * General service functions
1918 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1921 u32 resource_bit = (1 << resource);
1922 int func = BP_FUNC(bp);
1923 u32 hw_lock_control_reg;
1926 /* Validating that the resource is within range */
1927 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1928 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1929 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1934 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1936 hw_lock_control_reg =
1937 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1940 /* Validating that the resource is not already taken */
1941 lock_status = REG_RD(bp, hw_lock_control_reg);
1942 if (lock_status & resource_bit) {
1943 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1944 lock_status, resource_bit);
1948 /* Try for 5 second every 5ms */
1949 for (cnt = 0; cnt < 1000; cnt++) {
1950 /* Try to acquire the lock */
1951 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1952 lock_status = REG_RD(bp, hw_lock_control_reg);
1953 if (lock_status & resource_bit)
1956 usleep_range(5000, 10000);
1958 BNX2X_ERR("Timeout\n");
1962 int bnx2x_release_leader_lock(struct bnx2x *bp)
1964 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1967 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1970 u32 resource_bit = (1 << resource);
1971 int func = BP_FUNC(bp);
1972 u32 hw_lock_control_reg;
1974 /* Validating that the resource is within range */
1975 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1976 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1977 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1982 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1984 hw_lock_control_reg =
1985 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1988 /* Validating that the resource is currently taken */
1989 lock_status = REG_RD(bp, hw_lock_control_reg);
1990 if (!(lock_status & resource_bit)) {
1991 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
1992 lock_status, resource_bit);
1996 REG_WR(bp, hw_lock_control_reg, resource_bit);
2000 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2002 /* The GPIO should be swapped if swap register is set and active */
2003 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2004 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2005 int gpio_shift = gpio_num +
2006 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2007 u32 gpio_mask = (1 << gpio_shift);
2011 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2012 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2016 /* read GPIO value */
2017 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2019 /* get the requested pin value */
2020 if ((gpio_reg & gpio_mask) == gpio_mask)
2025 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2030 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2032 /* The GPIO should be swapped if swap register is set and active */
2033 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2034 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2035 int gpio_shift = gpio_num +
2036 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2037 u32 gpio_mask = (1 << gpio_shift);
2040 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2041 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2045 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2046 /* read GPIO and mask except the float bits */
2047 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2050 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2052 "Set GPIO %d (shift %d) -> output low\n",
2053 gpio_num, gpio_shift);
2054 /* clear FLOAT and set CLR */
2055 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2056 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2059 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2061 "Set GPIO %d (shift %d) -> output high\n",
2062 gpio_num, gpio_shift);
2063 /* clear FLOAT and set SET */
2064 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2065 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2068 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2070 "Set GPIO %d (shift %d) -> input\n",
2071 gpio_num, gpio_shift);
2073 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2080 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2081 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2086 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2091 /* Any port swapping should be handled by caller. */
2093 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2094 /* read GPIO and mask except the float bits */
2095 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2096 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2097 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2098 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2101 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2102 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2104 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2107 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2108 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2110 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2113 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2114 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2116 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2120 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2126 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2128 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2133 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2135 /* The GPIO should be swapped if swap register is set and active */
2136 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2137 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2138 int gpio_shift = gpio_num +
2139 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2140 u32 gpio_mask = (1 << gpio_shift);
2143 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2144 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2148 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2150 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2153 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2155 "Clear GPIO INT %d (shift %d) -> output low\n",
2156 gpio_num, gpio_shift);
2157 /* clear SET and set CLR */
2158 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2159 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2162 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2164 "Set GPIO INT %d (shift %d) -> output high\n",
2165 gpio_num, gpio_shift);
2166 /* clear CLR and set SET */
2167 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2168 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2175 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2176 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2181 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2185 /* Only 2 SPIOs are configurable */
2186 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2187 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2191 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2192 /* read SPIO and mask except the float bits */
2193 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2196 case MISC_SPIO_OUTPUT_LOW:
2197 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2198 /* clear FLOAT and set CLR */
2199 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2200 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2203 case MISC_SPIO_OUTPUT_HIGH:
2204 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2205 /* clear FLOAT and set SET */
2206 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2207 spio_reg |= (spio << MISC_SPIO_SET_POS);
2210 case MISC_SPIO_INPUT_HI_Z:
2211 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2213 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2220 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2221 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2226 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2228 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2229 switch (bp->link_vars.ieee_fc &
2230 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2231 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2232 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2236 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2237 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2241 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2242 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2246 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2252 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2254 /* Initialize link parameters structure variables
2255 * It is recommended to turn off RX FC for jumbo frames
2256 * for better performance
2258 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2259 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2261 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2264 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2266 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2267 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2269 if (!BP_NOMCP(bp)) {
2270 bnx2x_set_requested_fc(bp);
2271 bnx2x_acquire_phy_lock(bp);
2273 if (load_mode == LOAD_DIAG) {
2274 struct link_params *lp = &bp->link_params;
2275 lp->loopback_mode = LOOPBACK_XGXS;
2276 /* do PHY loopback at 10G speed, if possible */
2277 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2278 if (lp->speed_cap_mask[cfx_idx] &
2279 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2280 lp->req_line_speed[cfx_idx] =
2283 lp->req_line_speed[cfx_idx] =
2288 if (load_mode == LOAD_LOOPBACK_EXT) {
2289 struct link_params *lp = &bp->link_params;
2290 lp->loopback_mode = LOOPBACK_EXT;
2293 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2295 bnx2x_release_phy_lock(bp);
2297 bnx2x_calc_fc_adv(bp);
2299 if (bp->link_vars.link_up) {
2300 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2301 bnx2x_link_report(bp);
2303 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2304 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2307 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2311 void bnx2x_link_set(struct bnx2x *bp)
2313 if (!BP_NOMCP(bp)) {
2314 bnx2x_acquire_phy_lock(bp);
2315 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2316 bnx2x_release_phy_lock(bp);
2318 bnx2x_calc_fc_adv(bp);
2320 BNX2X_ERR("Bootcode is missing - can not set link\n");
2323 static void bnx2x__link_reset(struct bnx2x *bp)
2325 if (!BP_NOMCP(bp)) {
2326 bnx2x_acquire_phy_lock(bp);
2327 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2328 bnx2x_release_phy_lock(bp);
2330 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2333 void bnx2x_force_link_reset(struct bnx2x *bp)
2335 bnx2x_acquire_phy_lock(bp);
2336 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2337 bnx2x_release_phy_lock(bp);
2340 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2344 if (!BP_NOMCP(bp)) {
2345 bnx2x_acquire_phy_lock(bp);
2346 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2348 bnx2x_release_phy_lock(bp);
2350 BNX2X_ERR("Bootcode is missing - can not test link\n");
2355 /* Calculates the sum of vn_min_rates.
2356 It's needed for further normalizing of the min_rates.
2358 sum of vn_min_rates.
2360 0 - if all the min_rates are 0.
2361 In the later case fairness algorithm should be deactivated.
2362 If not all min_rates are zero then those that are zeroes will be set to 1.
2364 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2365 struct cmng_init_input *input)
2370 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2371 u32 vn_cfg = bp->mf_config[vn];
2372 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2373 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2375 /* Skip hidden vns */
2376 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2378 /* If min rate is zero - set it to 1 */
2379 else if (!vn_min_rate)
2380 vn_min_rate = DEF_MIN_RATE;
2384 input->vnic_min_rate[vn] = vn_min_rate;
2387 /* if ETS or all min rates are zeros - disable fairness */
2388 if (BNX2X_IS_ETS_ENABLED(bp)) {
2389 input->flags.cmng_enables &=
2390 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2391 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2392 } else if (all_zero) {
2393 input->flags.cmng_enables &=
2394 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2396 "All MIN values are zeroes fairness will be disabled\n");
2398 input->flags.cmng_enables |=
2399 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2402 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2403 struct cmng_init_input *input)
2406 u32 vn_cfg = bp->mf_config[vn];
2408 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2411 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2414 /* maxCfg in percents of linkspeed */
2415 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2416 } else /* SD modes */
2417 /* maxCfg is absolute in 100Mb units */
2418 vn_max_rate = maxCfg * 100;
2421 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2423 input->vnic_max_rate[vn] = vn_max_rate;
2426 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2428 if (CHIP_REV_IS_SLOW(bp))
2429 return CMNG_FNS_NONE;
2431 return CMNG_FNS_MINMAX;
2433 return CMNG_FNS_NONE;
2436 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2438 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2441 return; /* what should be the default value in this case */
2443 /* For 2 port configuration the absolute function number formula
2445 * abs_func = 2 * vn + BP_PORT + BP_PATH
2447 * and there are 4 functions per port
2449 * For 4 port configuration it is
2450 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2452 * and there are 2 functions per port
2454 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2455 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2457 if (func >= E1H_FUNC_MAX)
2461 MF_CFG_RD(bp, func_mf_config[func].config);
2463 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2464 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2465 bp->flags |= MF_FUNC_DIS;
2467 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2468 bp->flags &= ~MF_FUNC_DIS;
2472 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2474 struct cmng_init_input input;
2475 memset(&input, 0, sizeof(struct cmng_init_input));
2477 input.port_rate = bp->link_vars.line_speed;
2479 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2482 /* read mf conf from shmem */
2484 bnx2x_read_mf_cfg(bp);
2486 /* vn_weight_sum and enable fairness if not 0 */
2487 bnx2x_calc_vn_min(bp, &input);
2489 /* calculate and set min-max rate for each vn */
2491 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2492 bnx2x_calc_vn_max(bp, vn, &input);
2494 /* always enable rate shaping and fairness */
2495 input.flags.cmng_enables |=
2496 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2498 bnx2x_init_cmng(&input, &bp->cmng);
2502 /* rate shaping and fairness are disabled */
2504 "rate shaping and fairness are disabled\n");
2507 static void storm_memset_cmng(struct bnx2x *bp,
2508 struct cmng_init *cmng,
2512 size_t size = sizeof(struct cmng_struct_per_port);
2514 u32 addr = BAR_XSTRORM_INTMEM +
2515 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2517 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2519 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2520 int func = func_by_vn(bp, vn);
2522 addr = BAR_XSTRORM_INTMEM +
2523 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2524 size = sizeof(struct rate_shaping_vars_per_vn);
2525 __storm_memset_struct(bp, addr, size,
2526 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2528 addr = BAR_XSTRORM_INTMEM +
2529 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2530 size = sizeof(struct fairness_vars_per_vn);
2531 __storm_memset_struct(bp, addr, size,
2532 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2536 /* init cmng mode in HW according to local configuration */
2537 void bnx2x_set_local_cmng(struct bnx2x *bp)
2539 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2541 if (cmng_fns != CMNG_FNS_NONE) {
2542 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2543 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2545 /* rate shaping and fairness are disabled */
2547 "single function mode without fairness\n");
2551 /* This function is called upon link interrupt */
2552 static void bnx2x_link_attn(struct bnx2x *bp)
2554 /* Make sure that we are synced with the current statistics */
2555 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2557 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2559 if (bp->link_vars.link_up) {
2561 /* dropless flow control */
2562 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2563 int port = BP_PORT(bp);
2564 u32 pause_enabled = 0;
2566 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2569 REG_WR(bp, BAR_USTRORM_INTMEM +
2570 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2574 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2575 struct host_port_stats *pstats;
2577 pstats = bnx2x_sp(bp, port_stats);
2578 /* reset old mac stats */
2579 memset(&(pstats->mac_stx[0]), 0,
2580 sizeof(struct mac_stx));
2582 if (bp->state == BNX2X_STATE_OPEN)
2583 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2586 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2587 bnx2x_set_local_cmng(bp);
2589 __bnx2x_link_report(bp);
2592 bnx2x_link_sync_notify(bp);
2595 void bnx2x__link_status_update(struct bnx2x *bp)
2597 if (bp->state != BNX2X_STATE_OPEN)
2600 /* read updated dcb configuration */
2602 bnx2x_dcbx_pmf_update(bp);
2603 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2604 if (bp->link_vars.link_up)
2605 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2607 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2608 /* indicate link status */
2609 bnx2x_link_report(bp);
2612 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2613 SUPPORTED_10baseT_Full |
2614 SUPPORTED_100baseT_Half |
2615 SUPPORTED_100baseT_Full |
2616 SUPPORTED_1000baseT_Full |
2617 SUPPORTED_2500baseX_Full |
2618 SUPPORTED_10000baseT_Full |
2623 SUPPORTED_Asym_Pause);
2624 bp->port.advertising[0] = bp->port.supported[0];
2626 bp->link_params.bp = bp;
2627 bp->link_params.port = BP_PORT(bp);
2628 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2629 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2630 bp->link_params.req_line_speed[0] = SPEED_10000;
2631 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2632 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2633 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2634 bp->link_vars.line_speed = SPEED_10000;
2635 bp->link_vars.link_status =
2636 (LINK_STATUS_LINK_UP |
2637 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2638 bp->link_vars.link_up = 1;
2639 bp->link_vars.duplex = DUPLEX_FULL;
2640 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2641 __bnx2x_link_report(bp);
2642 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2646 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2647 u16 vlan_val, u8 allowed_prio)
2649 struct bnx2x_func_state_params func_params = {NULL};
2650 struct bnx2x_func_afex_update_params *f_update_params =
2651 &func_params.params.afex_update;
2653 func_params.f_obj = &bp->func_obj;
2654 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2656 /* no need to wait for RAMROD completion, so don't
2657 * set RAMROD_COMP_WAIT flag
2660 f_update_params->vif_id = vifid;
2661 f_update_params->afex_default_vlan = vlan_val;
2662 f_update_params->allowed_priorities = allowed_prio;
2664 /* if ramrod can not be sent, response to MCP immediately */
2665 if (bnx2x_func_state_change(bp, &func_params) < 0)
2666 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2671 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2672 u16 vif_index, u8 func_bit_map)
2674 struct bnx2x_func_state_params func_params = {NULL};
2675 struct bnx2x_func_afex_viflists_params *update_params =
2676 &func_params.params.afex_viflists;
2680 /* validate only LIST_SET and LIST_GET are received from switch */
2681 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2682 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2685 func_params.f_obj = &bp->func_obj;
2686 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2688 /* set parameters according to cmd_type */
2689 update_params->afex_vif_list_command = cmd_type;
2690 update_params->vif_list_index = vif_index;
2691 update_params->func_bit_map =
2692 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2693 update_params->func_to_clear = 0;
2695 (cmd_type == VIF_LIST_RULE_GET) ?
2696 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2697 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2699 /* if ramrod can not be sent, respond to MCP immediately for
2700 * SET and GET requests (other are not triggered from MCP)
2702 rc = bnx2x_func_state_change(bp, &func_params);
2704 bnx2x_fw_command(bp, drv_msg_code, 0);
2709 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2711 struct afex_stats afex_stats;
2712 u32 func = BP_ABS_FUNC(bp);
2719 u32 addr_to_write, vifid, addrs, stats_type, i;
2721 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2722 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2724 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2725 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2728 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2729 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2730 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2732 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2734 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2738 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2739 addr_to_write = SHMEM2_RD(bp,
2740 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2741 stats_type = SHMEM2_RD(bp,
2742 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2745 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2748 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2750 /* write response to scratchpad, for MCP */
2751 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2752 REG_WR(bp, addr_to_write + i*sizeof(u32),
2753 *(((u32 *)(&afex_stats))+i));
2755 /* send ack message to MCP */
2756 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2759 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2760 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2761 bp->mf_config[BP_VN(bp)] = mf_config;
2763 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2766 /* if VIF_SET is "enabled" */
2767 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2768 /* set rate limit directly to internal RAM */
2769 struct cmng_init_input cmng_input;
2770 struct rate_shaping_vars_per_vn m_rs_vn;
2771 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2772 u32 addr = BAR_XSTRORM_INTMEM +
2773 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2775 bp->mf_config[BP_VN(bp)] = mf_config;
2777 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2778 m_rs_vn.vn_counter.rate =
2779 cmng_input.vnic_max_rate[BP_VN(bp)];
2780 m_rs_vn.vn_counter.quota =
2781 (m_rs_vn.vn_counter.rate *
2782 RS_PERIODIC_TIMEOUT_USEC) / 8;
2784 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2786 /* read relevant values from mf_cfg struct in shmem */
2788 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2789 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2790 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2792 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2793 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2794 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2795 vlan_prio = (mf_config &
2796 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2797 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2798 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2801 func_mf_config[func].afex_config) &
2802 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2803 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2806 func_mf_config[func].afex_config) &
2807 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2808 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2810 /* send ramrod to FW, return in case of failure */
2811 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2815 bp->afex_def_vlan_tag = vlan_val;
2816 bp->afex_vlan_mode = vlan_mode;
2818 /* notify link down because BP->flags is disabled */
2819 bnx2x_link_report(bp);
2821 /* send INVALID VIF ramrod to FW */
2822 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2824 /* Reset the default afex VLAN */
2825 bp->afex_def_vlan_tag = -1;
2830 static void bnx2x_pmf_update(struct bnx2x *bp)
2832 int port = BP_PORT(bp);
2836 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2839 * We need the mb() to ensure the ordering between the writing to
2840 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2844 /* queue a periodic task */
2845 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2847 bnx2x_dcbx_pmf_update(bp);
2849 /* enable nig attention */
2850 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2851 if (bp->common.int_block == INT_BLOCK_HC) {
2852 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2853 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2854 } else if (!CHIP_IS_E1x(bp)) {
2855 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2856 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2859 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2867 * General service functions
2870 /* send the MCP a request, block until there is a reply */
2871 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2873 int mb_idx = BP_FW_MB_IDX(bp);
2877 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2879 mutex_lock(&bp->fw_mb_mutex);
2881 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2882 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2884 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2885 (command | seq), param);
2888 /* let the FW do it's magic ... */
2891 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2893 /* Give the FW up to 5 second (500*10ms) */
2894 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2896 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2897 cnt*delay, rc, seq);
2899 /* is this a reply to our command? */
2900 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2901 rc &= FW_MSG_CODE_MASK;
2904 BNX2X_ERR("FW failed to respond!\n");
2908 mutex_unlock(&bp->fw_mb_mutex);
2913 static void storm_memset_func_cfg(struct bnx2x *bp,
2914 struct tstorm_eth_function_common_config *tcfg,
2917 size_t size = sizeof(struct tstorm_eth_function_common_config);
2919 u32 addr = BAR_TSTRORM_INTMEM +
2920 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2922 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2925 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2927 if (CHIP_IS_E1x(bp)) {
2928 struct tstorm_eth_function_common_config tcfg = {0};
2930 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2933 /* Enable the function in the FW */
2934 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2935 storm_memset_func_en(bp, p->func_id, 1);
2938 if (p->func_flgs & FUNC_FLG_SPQ) {
2939 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2940 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2941 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2946 * bnx2x_get_common_flags - Return common flags
2950 * @zero_stats TRUE if statistics zeroing is needed
2952 * Return the flags that are common for the Tx-only and not normal connections.
2954 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2955 struct bnx2x_fastpath *fp,
2958 unsigned long flags = 0;
2960 /* PF driver will always initialize the Queue to an ACTIVE state */
2961 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2963 /* tx only connections collect statistics (on the same index as the
2964 * parent connection). The statistics are zeroed when the parent
2965 * connection is initialized.
2968 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2970 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2972 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
2973 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
2975 #ifdef BNX2X_STOP_ON_ERROR
2976 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
2982 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2983 struct bnx2x_fastpath *fp,
2986 unsigned long flags = 0;
2988 /* calculate other queue flags */
2990 __set_bit(BNX2X_Q_FLG_OV, &flags);
2992 if (IS_FCOE_FP(fp)) {
2993 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2994 /* For FCoE - force usage of default priority (for afex) */
2995 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2998 if (!fp->disable_tpa) {
2999 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3000 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3001 if (fp->mode == TPA_MODE_GRO)
3002 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3006 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3007 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3010 /* Always set HW VLAN stripping */
3011 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3013 /* configure silent vlan removal */
3015 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3017 return flags | bnx2x_get_common_flags(bp, fp, true);
3020 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3021 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3024 gen_init->stat_id = bnx2x_stats_id(fp);
3025 gen_init->spcl_id = fp->cl_id;
3027 /* Always use mini-jumbo MTU for FCoE L2 ring */
3029 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3031 gen_init->mtu = bp->dev->mtu;
3033 gen_init->cos = cos;
3036 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3037 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3038 struct bnx2x_rxq_setup_params *rxq_init)
3042 u16 tpa_agg_size = 0;
3044 if (!fp->disable_tpa) {
3045 pause->sge_th_lo = SGE_TH_LO(bp);
3046 pause->sge_th_hi = SGE_TH_HI(bp);
3048 /* validate SGE ring has enough to cross high threshold */
3049 WARN_ON(bp->dropless_fc &&
3050 pause->sge_th_hi + FW_PREFETCH_CNT >
3051 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3053 tpa_agg_size = TPA_AGG_SIZE;
3054 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3056 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3057 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3058 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3061 /* pause - not for e1 */
3062 if (!CHIP_IS_E1(bp)) {
3063 pause->bd_th_lo = BD_TH_LO(bp);
3064 pause->bd_th_hi = BD_TH_HI(bp);
3066 pause->rcq_th_lo = RCQ_TH_LO(bp);
3067 pause->rcq_th_hi = RCQ_TH_HI(bp);
3069 * validate that rings have enough entries to cross
3072 WARN_ON(bp->dropless_fc &&
3073 pause->bd_th_hi + FW_PREFETCH_CNT >
3075 WARN_ON(bp->dropless_fc &&
3076 pause->rcq_th_hi + FW_PREFETCH_CNT >
3077 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3083 rxq_init->dscr_map = fp->rx_desc_mapping;
3084 rxq_init->sge_map = fp->rx_sge_mapping;
3085 rxq_init->rcq_map = fp->rx_comp_mapping;
3086 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3088 /* This should be a maximum number of data bytes that may be
3089 * placed on the BD (not including paddings).
3091 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3092 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3094 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3095 rxq_init->tpa_agg_sz = tpa_agg_size;
3096 rxq_init->sge_buf_sz = sge_sz;
3097 rxq_init->max_sges_pkt = max_sge;
3098 rxq_init->rss_engine_id = BP_FUNC(bp);
3099 rxq_init->mcast_engine_id = BP_FUNC(bp);
3101 /* Maximum number or simultaneous TPA aggregation for this Queue.
3103 * For PF Clients it should be the maximum available number.
3104 * VF driver(s) may want to define it to a smaller value.
3106 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3108 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3109 rxq_init->fw_sb_id = fp->fw_sb_id;
3112 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3114 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3115 /* configure silent vlan removal
3116 * if multi function mode is afex, then mask default vlan
3118 if (IS_MF_AFEX(bp)) {
3119 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3120 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3124 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3125 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3128 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3129 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3130 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3131 txq_init->fw_sb_id = fp->fw_sb_id;
3134 * set the tss leading client id for TX classification ==
3135 * leading RSS client id
3137 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3139 if (IS_FCOE_FP(fp)) {
3140 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3141 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3145 static void bnx2x_pf_init(struct bnx2x *bp)
3147 struct bnx2x_func_init_params func_init = {0};
3148 struct event_ring_data eq_data = { {0} };
3151 if (!CHIP_IS_E1x(bp)) {
3152 /* reset IGU PF statistics: MSIX + ATTN */
3154 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3155 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3156 (CHIP_MODE_IS_4_PORT(bp) ?
3157 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3159 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3160 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3161 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3162 (CHIP_MODE_IS_4_PORT(bp) ?
3163 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3166 /* function setup flags */
3167 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3169 /* This flag is relevant for E1x only.
3170 * E2 doesn't have a TPA configuration in a function level.
3172 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3174 func_init.func_flgs = flags;
3175 func_init.pf_id = BP_FUNC(bp);
3176 func_init.func_id = BP_FUNC(bp);
3177 func_init.spq_map = bp->spq_mapping;
3178 func_init.spq_prod = bp->spq_prod_idx;
3180 bnx2x_func_init(bp, &func_init);
3182 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3185 * Congestion management values depend on the link rate
3186 * There is no active link so initial link rate is set to 10 Gbps.
3187 * When the link comes up The congestion management values are
3188 * re-calculated according to the actual link rate.
3190 bp->link_vars.line_speed = SPEED_10000;
3191 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3193 /* Only the PMF sets the HW */
3195 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3197 /* init Event Queue - PCI bus guarantees correct endianity*/
3198 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3199 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3200 eq_data.producer = bp->eq_prod;
3201 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3202 eq_data.sb_id = DEF_SB_ID;
3203 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3206 static void bnx2x_e1h_disable(struct bnx2x *bp)
3208 int port = BP_PORT(bp);
3210 bnx2x_tx_disable(bp);
3212 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3215 static void bnx2x_e1h_enable(struct bnx2x *bp)
3217 int port = BP_PORT(bp);
3219 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3221 /* Tx queue should be only re-enabled */
3222 netif_tx_wake_all_queues(bp->dev);
3225 * Should not call netif_carrier_on since it will be called if the link
3226 * is up when checking for link state
3230 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3232 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3234 struct eth_stats_info *ether_stat =
3235 &bp->slowpath->drv_info_to_mcp.ether_stat;
3236 struct bnx2x_vlan_mac_obj *mac_obj =
3237 &bp->sp_objs->mac_obj;
3240 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3241 ETH_STAT_INFO_VERSION_LEN);
3243 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3244 * mac_local field in ether_stat struct. The base address is offset by 2
3245 * bytes to account for the field being 8 bytes but a mac address is
3246 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3247 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3248 * allocated by the ether_stat struct, so the macs will land in their
3251 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3252 memset(ether_stat->mac_local + i, 0,
3253 sizeof(ether_stat->mac_local[0]));
3254 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3255 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3256 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3258 ether_stat->mtu_size = bp->dev->mtu;
3259 if (bp->dev->features & NETIF_F_RXCSUM)
3260 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3261 if (bp->dev->features & NETIF_F_TSO)
3262 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3263 ether_stat->feature_flags |= bp->common.boot_mode;
3265 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3267 ether_stat->txq_size = bp->tx_ring_size;
3268 ether_stat->rxq_size = bp->rx_ring_size;
3271 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3273 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3274 struct fcoe_stats_info *fcoe_stat =
3275 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3277 if (!CNIC_LOADED(bp))
3280 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3282 fcoe_stat->qos_priority =
3283 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3285 /* insert FCoE stats from ramrod response */
3287 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3288 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3289 tstorm_queue_statistics;
3291 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3292 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3293 xstorm_queue_statistics;
3295 struct fcoe_statistics_params *fw_fcoe_stat =
3296 &bp->fw_stats_data->fcoe;
3298 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3299 fcoe_stat->rx_bytes_lo,
3300 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3302 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3303 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3304 fcoe_stat->rx_bytes_lo,
3305 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3307 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3308 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3309 fcoe_stat->rx_bytes_lo,
3310 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3312 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3313 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3314 fcoe_stat->rx_bytes_lo,
3315 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3317 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3318 fcoe_stat->rx_frames_lo,
3319 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3321 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3322 fcoe_stat->rx_frames_lo,
3323 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3325 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3326 fcoe_stat->rx_frames_lo,
3327 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3329 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3330 fcoe_stat->rx_frames_lo,
3331 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3333 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3334 fcoe_stat->tx_bytes_lo,
3335 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3337 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3338 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3339 fcoe_stat->tx_bytes_lo,
3340 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3342 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3343 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3344 fcoe_stat->tx_bytes_lo,
3345 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3347 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3348 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3349 fcoe_stat->tx_bytes_lo,
3350 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3352 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3353 fcoe_stat->tx_frames_lo,
3354 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3356 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3357 fcoe_stat->tx_frames_lo,
3358 fcoe_q_xstorm_stats->ucast_pkts_sent);
3360 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3361 fcoe_stat->tx_frames_lo,
3362 fcoe_q_xstorm_stats->bcast_pkts_sent);
3364 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3365 fcoe_stat->tx_frames_lo,
3366 fcoe_q_xstorm_stats->mcast_pkts_sent);
3369 /* ask L5 driver to add data to the struct */
3370 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3373 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3375 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3376 struct iscsi_stats_info *iscsi_stat =
3377 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3379 if (!CNIC_LOADED(bp))
3382 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3385 iscsi_stat->qos_priority =
3386 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3388 /* ask L5 driver to add data to the struct */
3389 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3392 /* called due to MCP event (on pmf):
3393 * reread new bandwidth configuration
3395 * notify others function about the change
3397 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3399 if (bp->link_vars.link_up) {
3400 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3401 bnx2x_link_sync_notify(bp);
3403 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3406 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3408 bnx2x_config_mf_bw(bp);
3409 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3412 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3414 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3415 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3418 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3420 enum drv_info_opcode op_code;
3421 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3423 /* if drv_info version supported by MFW doesn't match - send NACK */
3424 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3425 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3429 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3430 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3432 memset(&bp->slowpath->drv_info_to_mcp, 0,
3433 sizeof(union drv_info_to_mcp));
3436 case ETH_STATS_OPCODE:
3437 bnx2x_drv_info_ether_stat(bp);
3439 case FCOE_STATS_OPCODE:
3440 bnx2x_drv_info_fcoe_stat(bp);
3442 case ISCSI_STATS_OPCODE:
3443 bnx2x_drv_info_iscsi_stat(bp);
3446 /* if op code isn't supported - send NACK */
3447 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3451 /* if we got drv_info attn from MFW then these fields are defined in
3454 SHMEM2_WR(bp, drv_info_host_addr_lo,
3455 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3456 SHMEM2_WR(bp, drv_info_host_addr_hi,
3457 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3459 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3462 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3464 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3466 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3469 * This is the only place besides the function initialization
3470 * where the bp->flags can change so it is done without any
3473 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3474 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3475 bp->flags |= MF_FUNC_DIS;
3477 bnx2x_e1h_disable(bp);
3479 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3480 bp->flags &= ~MF_FUNC_DIS;
3482 bnx2x_e1h_enable(bp);
3484 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3486 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3487 bnx2x_config_mf_bw(bp);
3488 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3491 /* Report results to MCP */
3493 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3495 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3498 /* must be called under the spq lock */
3499 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3501 struct eth_spe *next_spe = bp->spq_prod_bd;
3503 if (bp->spq_prod_bd == bp->spq_last_bd) {
3504 bp->spq_prod_bd = bp->spq;
3505 bp->spq_prod_idx = 0;
3506 DP(BNX2X_MSG_SP, "end of spq\n");
3514 /* must be called under the spq lock */
3515 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3517 int func = BP_FUNC(bp);
3520 * Make sure that BD data is updated before writing the producer:
3521 * BD data is written to the memory, the producer is read from the
3522 * memory, thus we need a full memory barrier to ensure the ordering.
3526 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3532 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3534 * @cmd: command to check
3535 * @cmd_type: command type
3537 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3539 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3540 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3541 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3542 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3543 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3544 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3545 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3552 * bnx2x_sp_post - place a single command on an SP ring
3554 * @bp: driver handle
3555 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3556 * @cid: SW CID the command is related to
3557 * @data_hi: command private data address (high 32 bits)
3558 * @data_lo: command private data address (low 32 bits)
3559 * @cmd_type: command type (e.g. NONE, ETH)
3561 * SP data is handled as if it's always an address pair, thus data fields are
3562 * not swapped to little endian in upper functions. Instead this function swaps
3563 * data as if it's two u32 fields.
3565 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3566 u32 data_hi, u32 data_lo, int cmd_type)
3568 struct eth_spe *spe;
3570 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3572 #ifdef BNX2X_STOP_ON_ERROR
3573 if (unlikely(bp->panic)) {
3574 BNX2X_ERR("Can't post SP when there is panic\n");
3579 spin_lock_bh(&bp->spq_lock);
3582 if (!atomic_read(&bp->eq_spq_left)) {
3583 BNX2X_ERR("BUG! EQ ring full!\n");
3584 spin_unlock_bh(&bp->spq_lock);
3588 } else if (!atomic_read(&bp->cq_spq_left)) {
3589 BNX2X_ERR("BUG! SPQ ring full!\n");
3590 spin_unlock_bh(&bp->spq_lock);
3595 spe = bnx2x_sp_get_next(bp);
3597 /* CID needs port number to be encoded int it */
3598 spe->hdr.conn_and_cmd_data =
3599 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3602 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3604 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3605 SPE_HDR_FUNCTION_ID);
3607 spe->hdr.type = cpu_to_le16(type);
3609 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3610 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3613 * It's ok if the actual decrement is issued towards the memory
3614 * somewhere between the spin_lock and spin_unlock. Thus no
3615 * more explicit memory barrier is needed.
3618 atomic_dec(&bp->eq_spq_left);
3620 atomic_dec(&bp->cq_spq_left);
3623 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3624 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3625 (u32)(U64_LO(bp->spq_mapping) +
3626 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3627 HW_CID(bp, cid), data_hi, data_lo, type,
3628 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3630 bnx2x_sp_prod_update(bp);
3631 spin_unlock_bh(&bp->spq_lock);
3635 /* acquire split MCP access lock register */
3636 static int bnx2x_acquire_alr(struct bnx2x *bp)
3642 for (j = 0; j < 1000; j++) {
3643 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3644 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3645 if (val & MCPR_ACCESS_LOCK_LOCK)
3648 usleep_range(5000, 10000);
3650 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3651 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3658 /* release split MCP access lock register */
3659 static void bnx2x_release_alr(struct bnx2x *bp)
3661 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3664 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3665 #define BNX2X_DEF_SB_IDX 0x0002
3667 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3669 struct host_sp_status_block *def_sb = bp->def_status_blk;
3672 barrier(); /* status block is written to by the chip */
3673 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3674 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3675 rc |= BNX2X_DEF_SB_ATT_IDX;
3678 if (bp->def_idx != def_sb->sp_sb.running_index) {
3679 bp->def_idx = def_sb->sp_sb.running_index;
3680 rc |= BNX2X_DEF_SB_IDX;
3683 /* Do not reorder: indices reading should complete before handling */
3689 * slow path service functions
3692 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3694 int port = BP_PORT(bp);
3695 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3696 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3697 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3698 NIG_REG_MASK_INTERRUPT_PORT0;
3703 if (bp->attn_state & asserted)
3704 BNX2X_ERR("IGU ERROR\n");
3706 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3707 aeu_mask = REG_RD(bp, aeu_addr);
3709 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3710 aeu_mask, asserted);
3711 aeu_mask &= ~(asserted & 0x3ff);
3712 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3714 REG_WR(bp, aeu_addr, aeu_mask);
3715 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3717 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3718 bp->attn_state |= asserted;
3719 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3721 if (asserted & ATTN_HARD_WIRED_MASK) {
3722 if (asserted & ATTN_NIG_FOR_FUNC) {
3724 bnx2x_acquire_phy_lock(bp);
3726 /* save nig interrupt mask */
3727 nig_mask = REG_RD(bp, nig_int_mask_addr);
3729 /* If nig_mask is not set, no need to call the update
3733 REG_WR(bp, nig_int_mask_addr, 0);
3735 bnx2x_link_attn(bp);
3738 /* handle unicore attn? */
3740 if (asserted & ATTN_SW_TIMER_4_FUNC)
3741 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3743 if (asserted & GPIO_2_FUNC)
3744 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3746 if (asserted & GPIO_3_FUNC)
3747 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3749 if (asserted & GPIO_4_FUNC)
3750 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3753 if (asserted & ATTN_GENERAL_ATTN_1) {
3754 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3755 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3757 if (asserted & ATTN_GENERAL_ATTN_2) {
3758 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3759 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3761 if (asserted & ATTN_GENERAL_ATTN_3) {
3762 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3763 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3766 if (asserted & ATTN_GENERAL_ATTN_4) {
3767 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3768 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3770 if (asserted & ATTN_GENERAL_ATTN_5) {
3771 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3772 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3774 if (asserted & ATTN_GENERAL_ATTN_6) {
3775 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3776 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3780 } /* if hardwired */
3782 if (bp->common.int_block == INT_BLOCK_HC)
3783 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3784 COMMAND_REG_ATTN_BITS_SET);
3786 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3788 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3789 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3790 REG_WR(bp, reg_addr, asserted);
3792 /* now set back the mask */
3793 if (asserted & ATTN_NIG_FOR_FUNC) {
3794 /* Verify that IGU ack through BAR was written before restoring
3795 * NIG mask. This loop should exit after 2-3 iterations max.
3797 if (bp->common.int_block != INT_BLOCK_HC) {
3798 u32 cnt = 0, igu_acked;
3800 igu_acked = REG_RD(bp,
3801 IGU_REG_ATTENTION_ACK_BITS);
3802 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3803 (++cnt < MAX_IGU_ATTN_ACK_TO));
3806 "Failed to verify IGU ack on time\n");
3809 REG_WR(bp, nig_int_mask_addr, nig_mask);
3810 bnx2x_release_phy_lock(bp);
3814 static void bnx2x_fan_failure(struct bnx2x *bp)
3816 int port = BP_PORT(bp);
3818 /* mark the failure */
3821 dev_info.port_hw_config[port].external_phy_config);
3823 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3824 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3825 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3828 /* log the failure */
3829 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3830 "Please contact OEM Support for assistance\n");
3832 /* Schedule device reset (unload)
3833 * This is due to some boards consuming sufficient power when driver is
3834 * up to overheat if fan fails.
3836 smp_mb__before_clear_bit();
3837 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3838 smp_mb__after_clear_bit();
3839 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3842 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3844 int port = BP_PORT(bp);
3848 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3849 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3851 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3853 val = REG_RD(bp, reg_offset);
3854 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3855 REG_WR(bp, reg_offset, val);
3857 BNX2X_ERR("SPIO5 hw attention\n");
3859 /* Fan failure attention */
3860 bnx2x_hw_reset_phy(&bp->link_params);
3861 bnx2x_fan_failure(bp);
3864 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3865 bnx2x_acquire_phy_lock(bp);
3866 bnx2x_handle_module_detect_int(&bp->link_params);
3867 bnx2x_release_phy_lock(bp);
3870 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3872 val = REG_RD(bp, reg_offset);
3873 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3874 REG_WR(bp, reg_offset, val);
3876 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3877 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3882 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3886 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3888 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3889 BNX2X_ERR("DB hw attention 0x%x\n", val);
3890 /* DORQ discard attention */
3892 BNX2X_ERR("FATAL error from DORQ\n");
3895 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3897 int port = BP_PORT(bp);
3900 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3901 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3903 val = REG_RD(bp, reg_offset);
3904 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3905 REG_WR(bp, reg_offset, val);
3907 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3908 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3913 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3917 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3919 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3920 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3921 /* CFC error attention */
3923 BNX2X_ERR("FATAL error from CFC\n");
3926 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3927 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3928 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3929 /* RQ_USDMDP_FIFO_OVERFLOW */
3931 BNX2X_ERR("FATAL error from PXP\n");
3933 if (!CHIP_IS_E1x(bp)) {
3934 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3935 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3939 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3941 int port = BP_PORT(bp);
3944 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3945 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3947 val = REG_RD(bp, reg_offset);
3948 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3949 REG_WR(bp, reg_offset, val);
3951 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3952 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3957 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3961 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3963 if (attn & BNX2X_PMF_LINK_ASSERT) {
3964 int func = BP_FUNC(bp);
3966 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3967 bnx2x_read_mf_cfg(bp);
3968 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3969 func_mf_config[BP_ABS_FUNC(bp)].config);
3971 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3972 if (val & DRV_STATUS_DCC_EVENT_MASK)
3974 (val & DRV_STATUS_DCC_EVENT_MASK));
3976 if (val & DRV_STATUS_SET_MF_BW)
3977 bnx2x_set_mf_bw(bp);
3979 if (val & DRV_STATUS_DRV_INFO_REQ)
3980 bnx2x_handle_drv_info_req(bp);
3982 if (val & DRV_STATUS_VF_DISABLED)
3983 bnx2x_vf_handle_flr_event(bp);
3985 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3986 bnx2x_pmf_update(bp);
3989 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3990 bp->dcbx_enabled > 0)
3991 /* start dcbx state machine */
3992 bnx2x_dcbx_set_params(bp,
3993 BNX2X_DCBX_STATE_NEG_RECEIVED);
3994 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3995 bnx2x_handle_afex_cmd(bp,
3996 val & DRV_STATUS_AFEX_EVENT_MASK);
3997 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3998 bnx2x_handle_eee_event(bp);
3999 if (bp->link_vars.periodic_flags &
4000 PERIODIC_FLAGS_LINK_EVENT) {
4001 /* sync with link */
4002 bnx2x_acquire_phy_lock(bp);
4003 bp->link_vars.periodic_flags &=
4004 ~PERIODIC_FLAGS_LINK_EVENT;
4005 bnx2x_release_phy_lock(bp);
4007 bnx2x_link_sync_notify(bp);
4008 bnx2x_link_report(bp);
4010 /* Always call it here: bnx2x_link_report() will
4011 * prevent the link indication duplication.
4013 bnx2x__link_status_update(bp);
4014 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4016 BNX2X_ERR("MC assert!\n");
4017 bnx2x_mc_assert(bp);
4018 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4019 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4020 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4021 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4024 } else if (attn & BNX2X_MCP_ASSERT) {
4026 BNX2X_ERR("MCP assert!\n");
4027 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4031 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4034 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4035 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4036 if (attn & BNX2X_GRC_TIMEOUT) {
4037 val = CHIP_IS_E1(bp) ? 0 :
4038 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4039 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4041 if (attn & BNX2X_GRC_RSV) {
4042 val = CHIP_IS_E1(bp) ? 0 :
4043 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4044 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4046 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4052 * 0-7 - Engine0 load counter.
4053 * 8-15 - Engine1 load counter.
4054 * 16 - Engine0 RESET_IN_PROGRESS bit.
4055 * 17 - Engine1 RESET_IN_PROGRESS bit.
4056 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4058 * 19 - Engine1 ONE_IS_LOADED.
4059 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4060 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4061 * just the one belonging to its engine).
4064 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4066 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4067 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4068 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4069 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4070 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4071 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4072 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4075 * Set the GLOBAL_RESET bit.
4077 * Should be run under rtnl lock
4079 void bnx2x_set_reset_global(struct bnx2x *bp)
4082 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4083 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4084 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4085 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4089 * Clear the GLOBAL_RESET bit.
4091 * Should be run under rtnl lock
4093 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4096 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4097 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4098 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4099 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4103 * Checks the GLOBAL_RESET bit.
4105 * should be run under rtnl lock
4107 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4109 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4111 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4112 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4116 * Clear RESET_IN_PROGRESS bit for the current engine.
4118 * Should be run under rtnl lock
4120 static void bnx2x_set_reset_done(struct bnx2x *bp)
4123 u32 bit = BP_PATH(bp) ?
4124 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4125 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4126 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4130 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4132 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4136 * Set RESET_IN_PROGRESS for the current engine.
4138 * should be run under rtnl lock
4140 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4143 u32 bit = BP_PATH(bp) ?
4144 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4145 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4146 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4150 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4151 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4155 * Checks the RESET_IN_PROGRESS bit for the given engine.
4156 * should be run under rtnl lock
4158 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4160 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4162 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4164 /* return false if bit is set */
4165 return (val & bit) ? false : true;
4169 * set pf load for the current pf.
4171 * should be run under rtnl lock
4173 void bnx2x_set_pf_load(struct bnx2x *bp)
4176 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4177 BNX2X_PATH0_LOAD_CNT_MASK;
4178 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4179 BNX2X_PATH0_LOAD_CNT_SHIFT;
4181 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4182 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4184 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4186 /* get the current counter value */
4187 val1 = (val & mask) >> shift;
4189 /* set bit of that PF */
4190 val1 |= (1 << bp->pf_num);
4192 /* clear the old value */
4195 /* set the new one */
4196 val |= ((val1 << shift) & mask);
4198 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4199 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4203 * bnx2x_clear_pf_load - clear pf load mark
4205 * @bp: driver handle
4207 * Should be run under rtnl lock.
4208 * Decrements the load counter for the current engine. Returns
4209 * whether other functions are still loaded
4211 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4214 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4215 BNX2X_PATH0_LOAD_CNT_MASK;
4216 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4217 BNX2X_PATH0_LOAD_CNT_SHIFT;
4219 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4220 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4221 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4223 /* get the current counter value */
4224 val1 = (val & mask) >> shift;
4226 /* clear bit of that PF */
4227 val1 &= ~(1 << bp->pf_num);
4229 /* clear the old value */
4232 /* set the new one */
4233 val |= ((val1 << shift) & mask);
4235 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4236 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4241 * Read the load status for the current engine.
4243 * should be run under rtnl lock
4245 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4247 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4248 BNX2X_PATH0_LOAD_CNT_MASK);
4249 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4250 BNX2X_PATH0_LOAD_CNT_SHIFT);
4251 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4253 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4255 val = (val & mask) >> shift;
4257 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4263 static void _print_parity(struct bnx2x *bp, u32 reg)
4265 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4268 static void _print_next_block(int idx, const char *blk)
4270 pr_cont("%s%s", idx ? ", " : "", blk);
4273 static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4274 int par_num, bool print)
4278 for (i = 0; sig; i++) {
4279 cur_bit = ((u32)0x1 << i);
4280 if (sig & cur_bit) {
4282 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4284 _print_next_block(par_num++, "BRB");
4286 BRB1_REG_BRB1_PRTY_STS);
4289 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4291 _print_next_block(par_num++, "PARSER");
4292 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4295 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4297 _print_next_block(par_num++, "TSDM");
4299 TSDM_REG_TSDM_PRTY_STS);
4302 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4304 _print_next_block(par_num++,
4306 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4309 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4311 _print_next_block(par_num++, "TCM");
4313 TCM_REG_TCM_PRTY_STS);
4316 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4318 _print_next_block(par_num++, "TSEMI");
4320 TSEM_REG_TSEM_PRTY_STS_0);
4322 TSEM_REG_TSEM_PRTY_STS_1);
4325 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4327 _print_next_block(par_num++, "XPB");
4328 _print_parity(bp, GRCBASE_XPB +
4329 PB_REG_PB_PRTY_STS);
4342 static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4343 int par_num, bool *global,
4348 for (i = 0; sig; i++) {
4349 cur_bit = ((u32)0x1 << i);
4350 if (sig & cur_bit) {
4352 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4354 _print_next_block(par_num++, "PBF");
4355 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4358 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4360 _print_next_block(par_num++, "QM");
4361 _print_parity(bp, QM_REG_QM_PRTY_STS);
4364 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4366 _print_next_block(par_num++, "TM");
4367 _print_parity(bp, TM_REG_TM_PRTY_STS);
4370 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4372 _print_next_block(par_num++, "XSDM");
4374 XSDM_REG_XSDM_PRTY_STS);
4377 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4379 _print_next_block(par_num++, "XCM");
4380 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4383 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4385 _print_next_block(par_num++, "XSEMI");
4387 XSEM_REG_XSEM_PRTY_STS_0);
4389 XSEM_REG_XSEM_PRTY_STS_1);
4392 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4394 _print_next_block(par_num++,
4397 DORQ_REG_DORQ_PRTY_STS);
4400 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4402 _print_next_block(par_num++, "NIG");
4403 if (CHIP_IS_E1x(bp)) {
4405 NIG_REG_NIG_PRTY_STS);
4408 NIG_REG_NIG_PRTY_STS_0);
4410 NIG_REG_NIG_PRTY_STS_1);
4414 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4416 _print_next_block(par_num++,
4420 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4422 _print_next_block(par_num++, "DEBUG");
4423 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4426 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4428 _print_next_block(par_num++, "USDM");
4430 USDM_REG_USDM_PRTY_STS);
4433 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4435 _print_next_block(par_num++, "UCM");
4436 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4439 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4441 _print_next_block(par_num++, "USEMI");
4443 USEM_REG_USEM_PRTY_STS_0);
4445 USEM_REG_USEM_PRTY_STS_1);
4448 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4450 _print_next_block(par_num++, "UPB");
4451 _print_parity(bp, GRCBASE_UPB +
4452 PB_REG_PB_PRTY_STS);
4455 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4457 _print_next_block(par_num++, "CSDM");
4459 CSDM_REG_CSDM_PRTY_STS);
4462 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4464 _print_next_block(par_num++, "CCM");
4465 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4478 static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4479 int par_num, bool print)
4483 for (i = 0; sig; i++) {
4484 cur_bit = ((u32)0x1 << i);
4485 if (sig & cur_bit) {
4487 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4489 _print_next_block(par_num++, "CSEMI");
4491 CSEM_REG_CSEM_PRTY_STS_0);
4493 CSEM_REG_CSEM_PRTY_STS_1);
4496 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4498 _print_next_block(par_num++, "PXP");
4499 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4501 PXP2_REG_PXP2_PRTY_STS_0);
4503 PXP2_REG_PXP2_PRTY_STS_1);
4506 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4508 _print_next_block(par_num++,
4509 "PXPPCICLOCKCLIENT");
4511 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4513 _print_next_block(par_num++, "CFC");
4515 CFC_REG_CFC_PRTY_STS);
4518 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4520 _print_next_block(par_num++, "CDU");
4521 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4524 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4526 _print_next_block(par_num++, "DMAE");
4528 DMAE_REG_DMAE_PRTY_STS);
4531 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4533 _print_next_block(par_num++, "IGU");
4534 if (CHIP_IS_E1x(bp))
4536 HC_REG_HC_PRTY_STS);
4539 IGU_REG_IGU_PRTY_STS);
4542 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4544 _print_next_block(par_num++, "MISC");
4546 MISC_REG_MISC_PRTY_STS);
4559 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4560 bool *global, bool print)
4564 for (i = 0; sig; i++) {
4565 cur_bit = ((u32)0x1 << i);
4566 if (sig & cur_bit) {
4568 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4570 _print_next_block(par_num++, "MCP ROM");
4573 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4575 _print_next_block(par_num++,
4579 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4581 _print_next_block(par_num++,
4585 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4587 _print_next_block(par_num++,
4601 static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4602 int par_num, bool print)
4606 for (i = 0; sig; i++) {
4607 cur_bit = ((u32)0x1 << i);
4608 if (sig & cur_bit) {
4610 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4612 _print_next_block(par_num++, "PGLUE_B");
4614 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4617 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4619 _print_next_block(par_num++, "ATC");
4621 ATC_REG_ATC_PRTY_STS);
4634 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4637 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4638 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4639 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4640 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4641 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4643 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4644 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4645 sig[0] & HW_PRTY_ASSERT_SET_0,
4646 sig[1] & HW_PRTY_ASSERT_SET_1,
4647 sig[2] & HW_PRTY_ASSERT_SET_2,
4648 sig[3] & HW_PRTY_ASSERT_SET_3,
4649 sig[4] & HW_PRTY_ASSERT_SET_4);
4652 "Parity errors detected in blocks: ");
4653 par_num = bnx2x_check_blocks_with_parity0(bp,
4654 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4655 par_num = bnx2x_check_blocks_with_parity1(bp,
4656 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4657 par_num = bnx2x_check_blocks_with_parity2(bp,
4658 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4659 par_num = bnx2x_check_blocks_with_parity3(
4660 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4661 par_num = bnx2x_check_blocks_with_parity4(bp,
4662 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4673 * bnx2x_chk_parity_attn - checks for parity attentions.
4675 * @bp: driver handle
4676 * @global: true if there was a global attention
4677 * @print: show parity attention in syslog
4679 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4681 struct attn_route attn = { {0} };
4682 int port = BP_PORT(bp);
4684 attn.sig[0] = REG_RD(bp,
4685 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4687 attn.sig[1] = REG_RD(bp,
4688 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4690 attn.sig[2] = REG_RD(bp,
4691 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4693 attn.sig[3] = REG_RD(bp,
4694 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4697 if (!CHIP_IS_E1x(bp))
4698 attn.sig[4] = REG_RD(bp,
4699 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4702 return bnx2x_parity_attn(bp, global, print, attn.sig);
4705 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4708 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4710 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4711 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4712 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4713 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4714 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4715 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4716 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4717 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4718 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4719 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4721 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4722 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4724 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4725 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4726 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4727 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4728 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4729 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4730 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4731 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4733 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4734 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4735 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4736 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4737 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4738 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4739 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4740 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4741 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4742 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4743 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4744 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4745 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4746 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4747 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4750 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4751 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4752 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4753 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4754 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4758 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4760 struct attn_route attn, *group_mask;
4761 int port = BP_PORT(bp);
4766 bool global = false;
4768 /* need to take HW lock because MCP or other port might also
4769 try to handle this event */
4770 bnx2x_acquire_alr(bp);
4772 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4773 #ifndef BNX2X_STOP_ON_ERROR
4774 bp->recovery_state = BNX2X_RECOVERY_INIT;
4775 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4776 /* Disable HW interrupts */
4777 bnx2x_int_disable(bp);
4778 /* In case of parity errors don't handle attentions so that
4779 * other function would "see" parity errors.
4784 bnx2x_release_alr(bp);
4788 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4789 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4790 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4791 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4792 if (!CHIP_IS_E1x(bp))
4794 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4798 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4799 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4801 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4802 if (deasserted & (1 << index)) {
4803 group_mask = &bp->attn_group[index];
4805 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4807 group_mask->sig[0], group_mask->sig[1],
4808 group_mask->sig[2], group_mask->sig[3],
4809 group_mask->sig[4]);
4811 bnx2x_attn_int_deasserted4(bp,
4812 attn.sig[4] & group_mask->sig[4]);
4813 bnx2x_attn_int_deasserted3(bp,
4814 attn.sig[3] & group_mask->sig[3]);
4815 bnx2x_attn_int_deasserted1(bp,
4816 attn.sig[1] & group_mask->sig[1]);
4817 bnx2x_attn_int_deasserted2(bp,
4818 attn.sig[2] & group_mask->sig[2]);
4819 bnx2x_attn_int_deasserted0(bp,
4820 attn.sig[0] & group_mask->sig[0]);
4824 bnx2x_release_alr(bp);
4826 if (bp->common.int_block == INT_BLOCK_HC)
4827 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4828 COMMAND_REG_ATTN_BITS_CLR);
4830 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4833 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4834 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4835 REG_WR(bp, reg_addr, val);
4837 if (~bp->attn_state & deasserted)
4838 BNX2X_ERR("IGU ERROR\n");
4840 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4841 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4843 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4844 aeu_mask = REG_RD(bp, reg_addr);
4846 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4847 aeu_mask, deasserted);
4848 aeu_mask |= (deasserted & 0x3ff);
4849 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4851 REG_WR(bp, reg_addr, aeu_mask);
4852 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4854 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4855 bp->attn_state &= ~deasserted;
4856 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4859 static void bnx2x_attn_int(struct bnx2x *bp)
4861 /* read local copy of bits */
4862 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4864 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4866 u32 attn_state = bp->attn_state;
4868 /* look for changed bits */
4869 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4870 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4873 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4874 attn_bits, attn_ack, asserted, deasserted);
4876 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4877 BNX2X_ERR("BAD attention state\n");
4879 /* handle bits that were raised */
4881 bnx2x_attn_int_asserted(bp, asserted);
4884 bnx2x_attn_int_deasserted(bp, deasserted);
4887 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4888 u16 index, u8 op, u8 update)
4890 u32 igu_addr = bp->igu_base_addr;
4891 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4892 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4896 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4898 /* No memory barriers */
4899 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4900 mmiowb(); /* keep prod updates ordered */
4903 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4904 union event_ring_elem *elem)
4906 u8 err = elem->message.error;
4908 if (!bp->cnic_eth_dev.starting_cid ||
4909 (cid < bp->cnic_eth_dev.starting_cid &&
4910 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4913 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4915 if (unlikely(err)) {
4917 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4919 bnx2x_panic_dump(bp, false);
4921 bnx2x_cnic_cfc_comp(bp, cid, err);
4925 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4927 struct bnx2x_mcast_ramrod_params rparam;
4930 memset(&rparam, 0, sizeof(rparam));
4932 rparam.mcast_obj = &bp->mcast_obj;
4934 netif_addr_lock_bh(bp->dev);
4936 /* Clear pending state for the last command */
4937 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4939 /* If there are pending mcast commands - send them */
4940 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4941 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4943 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4947 netif_addr_unlock_bh(bp->dev);
4950 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4951 union event_ring_elem *elem)
4953 unsigned long ramrod_flags = 0;
4955 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4956 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4958 /* Always push next commands out, don't wait here */
4959 __set_bit(RAMROD_CONT, &ramrod_flags);
4961 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
4962 >> BNX2X_SWCID_SHIFT) {
4963 case BNX2X_FILTER_MAC_PENDING:
4964 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4965 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4966 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4968 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4971 case BNX2X_FILTER_MCAST_PENDING:
4972 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4973 /* This is only relevant for 57710 where multicast MACs are
4974 * configured as unicast MACs using the same ramrod.
4976 bnx2x_handle_mcast_eqe(bp);
4979 BNX2X_ERR("Unsupported classification command: %d\n",
4980 elem->message.data.eth_event.echo);
4984 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4987 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4989 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4992 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4994 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4996 netif_addr_lock_bh(bp->dev);
4998 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5000 /* Send rx_mode command again if was requested */
5001 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5002 bnx2x_set_storm_rx_mode(bp);
5003 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5005 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5006 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5008 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5010 netif_addr_unlock_bh(bp->dev);
5013 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5014 union event_ring_elem *elem)
5016 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5018 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5019 elem->message.data.vif_list_event.func_bit_map);
5020 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5021 elem->message.data.vif_list_event.func_bit_map);
5022 } else if (elem->message.data.vif_list_event.echo ==
5023 VIF_LIST_RULE_SET) {
5024 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5025 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5029 /* called with rtnl_lock */
5030 static void bnx2x_after_function_update(struct bnx2x *bp)
5033 struct bnx2x_fastpath *fp;
5034 struct bnx2x_queue_state_params queue_params = {NULL};
5035 struct bnx2x_queue_update_params *q_update_params =
5036 &queue_params.params.update;
5038 /* Send Q update command with afex vlan removal values for all Qs */
5039 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5041 /* set silent vlan removal values according to vlan mode */
5042 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5043 &q_update_params->update_flags);
5044 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5045 &q_update_params->update_flags);
5046 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5048 /* in access mode mark mask and value are 0 to strip all vlans */
5049 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5050 q_update_params->silent_removal_value = 0;
5051 q_update_params->silent_removal_mask = 0;
5053 q_update_params->silent_removal_value =
5054 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5055 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5058 for_each_eth_queue(bp, q) {
5059 /* Set the appropriate Queue object */
5061 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5063 /* send the ramrod */
5064 rc = bnx2x_queue_state_change(bp, &queue_params);
5066 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5070 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5071 fp = &bp->fp[FCOE_IDX(bp)];
5072 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5074 /* clear pending completion bit */
5075 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5077 /* mark latest Q bit */
5078 smp_mb__before_clear_bit();
5079 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5080 smp_mb__after_clear_bit();
5082 /* send Q update ramrod for FCoE Q */
5083 rc = bnx2x_queue_state_change(bp, &queue_params);
5085 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5088 /* If no FCoE ring - ACK MCP now */
5089 bnx2x_link_report(bp);
5090 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5094 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5095 struct bnx2x *bp, u32 cid)
5097 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5099 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5100 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5102 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5105 static void bnx2x_eq_int(struct bnx2x *bp)
5107 u16 hw_cons, sw_cons, sw_prod;
5108 union event_ring_elem *elem;
5112 int rc, spqe_cnt = 0;
5113 struct bnx2x_queue_sp_obj *q_obj;
5114 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5115 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5117 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5119 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5120 * when we get the next-page we need to adjust so the loop
5121 * condition below will be met. The next element is the size of a
5122 * regular element and hence incrementing by 1
5124 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5127 /* This function may never run in parallel with itself for a
5128 * specific bp, thus there is no need in "paired" read memory
5131 sw_cons = bp->eq_cons;
5132 sw_prod = bp->eq_prod;
5134 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5135 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5137 for (; sw_cons != hw_cons;
5138 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5140 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5142 rc = bnx2x_iov_eq_sp_event(bp, elem);
5144 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5149 /* elem CID originates from FW; actually LE */
5150 cid = SW_CID((__force __le32)
5151 elem->message.data.cfc_del_event.cid);
5152 opcode = elem->message.opcode;
5154 /* handle eq element */
5156 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5157 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5158 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5161 case EVENT_RING_OPCODE_STAT_QUERY:
5162 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5163 "got statistics comp event %d\n",
5165 /* nothing to do with stats comp */
5168 case EVENT_RING_OPCODE_CFC_DEL:
5169 /* handle according to cid range */
5171 * we may want to verify here that the bp state is
5175 "got delete ramrod for MULTI[%d]\n", cid);
5177 if (CNIC_LOADED(bp) &&
5178 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5181 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5183 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5188 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5189 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5190 if (f_obj->complete_cmd(bp, f_obj,
5191 BNX2X_F_CMD_TX_STOP))
5193 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5196 case EVENT_RING_OPCODE_START_TRAFFIC:
5197 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5198 if (f_obj->complete_cmd(bp, f_obj,
5199 BNX2X_F_CMD_TX_START))
5201 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5204 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5205 echo = elem->message.data.function_update_event.echo;
5206 if (echo == SWITCH_UPDATE) {
5207 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5208 "got FUNC_SWITCH_UPDATE ramrod\n");
5209 if (f_obj->complete_cmd(
5210 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5214 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5215 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5216 f_obj->complete_cmd(bp, f_obj,
5217 BNX2X_F_CMD_AFEX_UPDATE);
5219 /* We will perform the Queues update from
5220 * sp_rtnl task as all Queue SP operations
5221 * should run under rtnl_lock.
5223 smp_mb__before_clear_bit();
5224 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5225 &bp->sp_rtnl_state);
5226 smp_mb__after_clear_bit();
5228 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5233 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5234 f_obj->complete_cmd(bp, f_obj,
5235 BNX2X_F_CMD_AFEX_VIFLISTS);
5236 bnx2x_after_afex_vif_lists(bp, elem);
5238 case EVENT_RING_OPCODE_FUNCTION_START:
5239 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5240 "got FUNC_START ramrod\n");
5241 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5246 case EVENT_RING_OPCODE_FUNCTION_STOP:
5247 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5248 "got FUNC_STOP ramrod\n");
5249 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5255 switch (opcode | bp->state) {
5256 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5258 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5259 BNX2X_STATE_OPENING_WAIT4_PORT):
5260 cid = elem->message.data.eth_event.echo &
5262 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5264 rss_raw->clear_pending(rss_raw);
5267 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5268 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5269 case (EVENT_RING_OPCODE_SET_MAC |
5270 BNX2X_STATE_CLOSING_WAIT4_HALT):
5271 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5273 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5275 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5276 BNX2X_STATE_CLOSING_WAIT4_HALT):
5277 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5278 bnx2x_handle_classification_eqe(bp, elem);
5281 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5283 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5285 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5286 BNX2X_STATE_CLOSING_WAIT4_HALT):
5287 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5288 bnx2x_handle_mcast_eqe(bp);
5291 case (EVENT_RING_OPCODE_FILTERS_RULES |
5293 case (EVENT_RING_OPCODE_FILTERS_RULES |
5295 case (EVENT_RING_OPCODE_FILTERS_RULES |
5296 BNX2X_STATE_CLOSING_WAIT4_HALT):
5297 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5298 bnx2x_handle_rx_mode_eqe(bp);
5301 /* unknown event log error and continue */
5302 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5303 elem->message.opcode, bp->state);
5309 smp_mb__before_atomic_inc();
5310 atomic_add(spqe_cnt, &bp->eq_spq_left);
5312 bp->eq_cons = sw_cons;
5313 bp->eq_prod = sw_prod;
5314 /* Make sure that above mem writes were issued towards the memory */
5317 /* update producer */
5318 bnx2x_update_eq_prod(bp, bp->eq_prod);
5321 static void bnx2x_sp_task(struct work_struct *work)
5323 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5325 DP(BNX2X_MSG_SP, "sp task invoked\n");
5327 /* make sure the atomic interrupt_occurred has been written */
5329 if (atomic_read(&bp->interrupt_occurred)) {
5331 /* what work needs to be performed? */
5332 u16 status = bnx2x_update_dsb_idx(bp);
5334 DP(BNX2X_MSG_SP, "status %x\n", status);
5335 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5336 atomic_set(&bp->interrupt_occurred, 0);
5339 if (status & BNX2X_DEF_SB_ATT_IDX) {
5341 status &= ~BNX2X_DEF_SB_ATT_IDX;
5344 /* SP events: STAT_QUERY and others */
5345 if (status & BNX2X_DEF_SB_IDX) {
5346 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5348 if (FCOE_INIT(bp) &&
5349 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5350 /* Prevent local bottom-halves from running as
5351 * we are going to change the local NAPI list.
5354 napi_schedule(&bnx2x_fcoe(bp, napi));
5358 /* Handle EQ completions */
5360 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5361 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5363 status &= ~BNX2X_DEF_SB_IDX;
5366 /* if status is non zero then perhaps something went wrong */
5367 if (unlikely(status))
5369 "got an unknown interrupt! (status 0x%x)\n", status);
5371 /* ack status block only if something was actually handled */
5372 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5373 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5376 /* must be called after the EQ processing (since eq leads to sriov
5377 * ramrod completion flows).
5378 * This flow may have been scheduled by the arrival of a ramrod
5379 * completion, or by the sriov code rescheduling itself.
5381 bnx2x_iov_sp_task(bp);
5383 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5384 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5386 bnx2x_link_report(bp);
5387 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5391 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5393 struct net_device *dev = dev_instance;
5394 struct bnx2x *bp = netdev_priv(dev);
5396 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5397 IGU_INT_DISABLE, 0);
5399 #ifdef BNX2X_STOP_ON_ERROR
5400 if (unlikely(bp->panic))
5404 if (CNIC_LOADED(bp)) {
5405 struct cnic_ops *c_ops;
5408 c_ops = rcu_dereference(bp->cnic_ops);
5410 c_ops->cnic_handler(bp->cnic_data, NULL);
5414 /* schedule sp task to perform default status block work, ack
5415 * attentions and enable interrupts.
5417 bnx2x_schedule_sp_task(bp);
5422 /* end of slow path */
5424 void bnx2x_drv_pulse(struct bnx2x *bp)
5426 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5427 bp->fw_drv_pulse_wr_seq);
5430 static void bnx2x_timer(unsigned long data)
5432 struct bnx2x *bp = (struct bnx2x *) data;
5434 if (!netif_running(bp->dev))
5439 int mb_idx = BP_FW_MB_IDX(bp);
5443 ++bp->fw_drv_pulse_wr_seq;
5444 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5445 /* TBD - add SYSTEM_TIME */
5446 drv_pulse = bp->fw_drv_pulse_wr_seq;
5447 bnx2x_drv_pulse(bp);
5449 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5450 MCP_PULSE_SEQ_MASK);
5451 /* The delta between driver pulse and mcp response
5452 * should be 1 (before mcp response) or 0 (after mcp response)
5454 if ((drv_pulse != mcp_pulse) &&
5455 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5456 /* someone lost a heartbeat... */
5457 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5458 drv_pulse, mcp_pulse);
5462 if (bp->state == BNX2X_STATE_OPEN)
5463 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5465 /* sample pf vf bulletin board for new posts from pf */
5467 bnx2x_timer_sriov(bp);
5469 mod_timer(&bp->timer, jiffies + bp->current_interval);
5472 /* end of Statistics */
5477 * nic init service functions
5480 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5483 if (!(len%4) && !(addr%4))
5484 for (i = 0; i < len; i += 4)
5485 REG_WR(bp, addr + i, fill);
5487 for (i = 0; i < len; i++)
5488 REG_WR8(bp, addr + i, fill);
5491 /* helper: writes FP SP data to FW - data_size in dwords */
5492 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5498 for (index = 0; index < data_size; index++)
5499 REG_WR(bp, BAR_CSTRORM_INTMEM +
5500 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5502 *(sb_data_p + index));
5505 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5509 struct hc_status_block_data_e2 sb_data_e2;
5510 struct hc_status_block_data_e1x sb_data_e1x;
5512 /* disable the function first */
5513 if (!CHIP_IS_E1x(bp)) {
5514 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5515 sb_data_e2.common.state = SB_DISABLED;
5516 sb_data_e2.common.p_func.vf_valid = false;
5517 sb_data_p = (u32 *)&sb_data_e2;
5518 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5520 memset(&sb_data_e1x, 0,
5521 sizeof(struct hc_status_block_data_e1x));
5522 sb_data_e1x.common.state = SB_DISABLED;
5523 sb_data_e1x.common.p_func.vf_valid = false;
5524 sb_data_p = (u32 *)&sb_data_e1x;
5525 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5527 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5529 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5530 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5531 CSTORM_STATUS_BLOCK_SIZE);
5532 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5533 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5534 CSTORM_SYNC_BLOCK_SIZE);
5537 /* helper: writes SP SB data to FW */
5538 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5539 struct hc_sp_status_block_data *sp_sb_data)
5541 int func = BP_FUNC(bp);
5543 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5544 REG_WR(bp, BAR_CSTRORM_INTMEM +
5545 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5547 *((u32 *)sp_sb_data + i));
5550 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5552 int func = BP_FUNC(bp);
5553 struct hc_sp_status_block_data sp_sb_data;
5554 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5556 sp_sb_data.state = SB_DISABLED;
5557 sp_sb_data.p_func.vf_valid = false;
5559 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5561 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5562 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5563 CSTORM_SP_STATUS_BLOCK_SIZE);
5564 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5565 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5566 CSTORM_SP_SYNC_BLOCK_SIZE);
5569 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5570 int igu_sb_id, int igu_seg_id)
5572 hc_sm->igu_sb_id = igu_sb_id;
5573 hc_sm->igu_seg_id = igu_seg_id;
5574 hc_sm->timer_value = 0xFF;
5575 hc_sm->time_to_expire = 0xFFFFFFFF;
5578 /* allocates state machine ids. */
5579 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5581 /* zero out state machine indices */
5583 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5586 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5587 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5588 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5589 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5593 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5594 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5597 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5598 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5599 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5600 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5601 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5602 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5603 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5604 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5607 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5608 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5612 struct hc_status_block_data_e2 sb_data_e2;
5613 struct hc_status_block_data_e1x sb_data_e1x;
5614 struct hc_status_block_sm *hc_sm_p;
5618 if (CHIP_INT_MODE_IS_BC(bp))
5619 igu_seg_id = HC_SEG_ACCESS_NORM;
5621 igu_seg_id = IGU_SEG_ACCESS_NORM;
5623 bnx2x_zero_fp_sb(bp, fw_sb_id);
5625 if (!CHIP_IS_E1x(bp)) {
5626 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5627 sb_data_e2.common.state = SB_ENABLED;
5628 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5629 sb_data_e2.common.p_func.vf_id = vfid;
5630 sb_data_e2.common.p_func.vf_valid = vf_valid;
5631 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5632 sb_data_e2.common.same_igu_sb_1b = true;
5633 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5634 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5635 hc_sm_p = sb_data_e2.common.state_machine;
5636 sb_data_p = (u32 *)&sb_data_e2;
5637 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5638 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5640 memset(&sb_data_e1x, 0,
5641 sizeof(struct hc_status_block_data_e1x));
5642 sb_data_e1x.common.state = SB_ENABLED;
5643 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5644 sb_data_e1x.common.p_func.vf_id = 0xff;
5645 sb_data_e1x.common.p_func.vf_valid = false;
5646 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5647 sb_data_e1x.common.same_igu_sb_1b = true;
5648 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5649 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5650 hc_sm_p = sb_data_e1x.common.state_machine;
5651 sb_data_p = (u32 *)&sb_data_e1x;
5652 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5653 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5656 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5657 igu_sb_id, igu_seg_id);
5658 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5659 igu_sb_id, igu_seg_id);
5661 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5663 /* write indices to HW - PCI guarantees endianity of regpairs */
5664 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5667 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5668 u16 tx_usec, u16 rx_usec)
5670 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5672 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5673 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5675 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5676 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5678 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5679 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5683 static void bnx2x_init_def_sb(struct bnx2x *bp)
5685 struct host_sp_status_block *def_sb = bp->def_status_blk;
5686 dma_addr_t mapping = bp->def_status_blk_mapping;
5687 int igu_sp_sb_index;
5689 int port = BP_PORT(bp);
5690 int func = BP_FUNC(bp);
5691 int reg_offset, reg_offset_en5;
5694 struct hc_sp_status_block_data sp_sb_data;
5695 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5697 if (CHIP_INT_MODE_IS_BC(bp)) {
5698 igu_sp_sb_index = DEF_SB_IGU_ID;
5699 igu_seg_id = HC_SEG_ACCESS_DEF;
5701 igu_sp_sb_index = bp->igu_dsb_id;
5702 igu_seg_id = IGU_SEG_ACCESS_DEF;
5706 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5707 atten_status_block);
5708 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5712 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5713 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5714 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5715 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5716 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5718 /* take care of sig[0]..sig[4] */
5719 for (sindex = 0; sindex < 4; sindex++)
5720 bp->attn_group[index].sig[sindex] =
5721 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5723 if (!CHIP_IS_E1x(bp))
5725 * enable5 is separate from the rest of the registers,
5726 * and therefore the address skip is 4
5727 * and not 16 between the different groups
5729 bp->attn_group[index].sig[4] = REG_RD(bp,
5730 reg_offset_en5 + 0x4*index);
5732 bp->attn_group[index].sig[4] = 0;
5735 if (bp->common.int_block == INT_BLOCK_HC) {
5736 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5737 HC_REG_ATTN_MSG0_ADDR_L);
5739 REG_WR(bp, reg_offset, U64_LO(section));
5740 REG_WR(bp, reg_offset + 4, U64_HI(section));
5741 } else if (!CHIP_IS_E1x(bp)) {
5742 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5743 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5746 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5749 bnx2x_zero_sp_sb(bp);
5751 /* PCI guarantees endianity of regpairs */
5752 sp_sb_data.state = SB_ENABLED;
5753 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5754 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5755 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5756 sp_sb_data.igu_seg_id = igu_seg_id;
5757 sp_sb_data.p_func.pf_id = func;
5758 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5759 sp_sb_data.p_func.vf_id = 0xff;
5761 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5763 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5766 void bnx2x_update_coalesce(struct bnx2x *bp)
5770 for_each_eth_queue(bp, i)
5771 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5772 bp->tx_ticks, bp->rx_ticks);
5775 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5777 spin_lock_init(&bp->spq_lock);
5778 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5780 bp->spq_prod_idx = 0;
5781 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5782 bp->spq_prod_bd = bp->spq;
5783 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5786 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5789 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5790 union event_ring_elem *elem =
5791 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5793 elem->next_page.addr.hi =
5794 cpu_to_le32(U64_HI(bp->eq_mapping +
5795 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5796 elem->next_page.addr.lo =
5797 cpu_to_le32(U64_LO(bp->eq_mapping +
5798 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5801 bp->eq_prod = NUM_EQ_DESC;
5802 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5803 /* we want a warning message before it gets wrought... */
5804 atomic_set(&bp->eq_spq_left,
5805 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5808 /* called with netif_addr_lock_bh() */
5809 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5810 unsigned long rx_mode_flags,
5811 unsigned long rx_accept_flags,
5812 unsigned long tx_accept_flags,
5813 unsigned long ramrod_flags)
5815 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5818 memset(&ramrod_param, 0, sizeof(ramrod_param));
5820 /* Prepare ramrod parameters */
5821 ramrod_param.cid = 0;
5822 ramrod_param.cl_id = cl_id;
5823 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5824 ramrod_param.func_id = BP_FUNC(bp);
5826 ramrod_param.pstate = &bp->sp_state;
5827 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5829 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5830 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5832 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5834 ramrod_param.ramrod_flags = ramrod_flags;
5835 ramrod_param.rx_mode_flags = rx_mode_flags;
5837 ramrod_param.rx_accept_flags = rx_accept_flags;
5838 ramrod_param.tx_accept_flags = tx_accept_flags;
5840 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5842 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5849 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5850 unsigned long *rx_accept_flags,
5851 unsigned long *tx_accept_flags)
5853 /* Clear the flags first */
5854 *rx_accept_flags = 0;
5855 *tx_accept_flags = 0;
5858 case BNX2X_RX_MODE_NONE:
5860 * 'drop all' supersedes any accept flags that may have been
5861 * passed to the function.
5864 case BNX2X_RX_MODE_NORMAL:
5865 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5866 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5867 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5869 /* internal switching mode */
5870 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5871 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5872 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5875 case BNX2X_RX_MODE_ALLMULTI:
5876 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5877 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5878 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5880 /* internal switching mode */
5881 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5882 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5883 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5886 case BNX2X_RX_MODE_PROMISC:
5887 /* According to definition of SI mode, iface in promisc mode
5888 * should receive matched and unmatched (in resolution of port)
5891 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5892 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5893 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5894 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5896 /* internal switching mode */
5897 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5898 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5901 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5903 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5907 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5911 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5912 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5913 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5914 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5920 /* called with netif_addr_lock_bh() */
5921 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5923 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5924 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5928 /* Configure rx_mode of FCoE Queue */
5929 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5931 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5936 __set_bit(RAMROD_RX, &ramrod_flags);
5937 __set_bit(RAMROD_TX, &ramrod_flags);
5939 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5940 rx_accept_flags, tx_accept_flags,
5944 static void bnx2x_init_internal_common(struct bnx2x *bp)
5950 * In switch independent mode, the TSTORM needs to accept
5951 * packets that failed classification, since approximate match
5952 * mac addresses aren't written to NIG LLH
5954 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5955 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5956 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5957 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5958 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5960 /* Zero this manually as its initialization is
5961 currently missing in the initTool */
5962 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5963 REG_WR(bp, BAR_USTRORM_INTMEM +
5964 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5965 if (!CHIP_IS_E1x(bp)) {
5966 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5967 CHIP_INT_MODE_IS_BC(bp) ?
5968 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5972 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5974 switch (load_code) {
5975 case FW_MSG_CODE_DRV_LOAD_COMMON:
5976 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5977 bnx2x_init_internal_common(bp);
5980 case FW_MSG_CODE_DRV_LOAD_PORT:
5984 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5985 /* internal memory per function is
5986 initialized inside bnx2x_pf_init */
5990 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5995 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5997 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6000 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6002 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6005 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6007 if (CHIP_IS_E1x(fp->bp))
6008 return BP_L_ID(fp->bp) + fp->index;
6009 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6010 return bnx2x_fp_igu_sb_id(fp);
6013 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6015 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6017 unsigned long q_type = 0;
6018 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6019 fp->rx_queue = fp_idx;
6021 fp->cl_id = bnx2x_fp_cl_id(fp);
6022 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6023 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6024 /* qZone id equals to FW (per path) client id */
6025 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6028 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6030 /* Setup SB indices */
6031 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6033 /* Configure Queue State object */
6034 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6035 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6037 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6040 for_each_cos_in_tx_queue(fp, cos) {
6041 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6042 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6043 FP_COS_TO_TXQ(fp, cos, bp),
6044 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6045 cids[cos] = fp->txdata_ptr[cos]->cid;
6048 /* nothing more for vf to do here */
6052 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6053 fp->fw_sb_id, fp->igu_sb_id);
6054 bnx2x_update_fpsb_idx(fp);
6055 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6056 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6057 bnx2x_sp_mapping(bp, q_rdata), q_type);
6060 * Configure classification DBs: Always enable Tx switching
6062 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6065 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6066 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6070 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6074 for (i = 1; i <= NUM_TX_RINGS; i++) {
6075 struct eth_tx_next_bd *tx_next_bd =
6076 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6078 tx_next_bd->addr_hi =
6079 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6080 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6081 tx_next_bd->addr_lo =
6082 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6083 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6086 *txdata->tx_cons_sb = cpu_to_le16(0);
6088 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6089 txdata->tx_db.data.zero_fill1 = 0;
6090 txdata->tx_db.data.prod = 0;
6092 txdata->tx_pkt_prod = 0;
6093 txdata->tx_pkt_cons = 0;
6094 txdata->tx_bd_prod = 0;
6095 txdata->tx_bd_cons = 0;
6099 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6103 for_each_tx_queue_cnic(bp, i)
6104 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6107 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6112 for_each_eth_queue(bp, i)
6113 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6114 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6117 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6120 bnx2x_init_fcoe_fp(bp);
6122 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6123 BNX2X_VF_ID_INVALID, false,
6124 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6126 /* ensure status block indices were read */
6128 bnx2x_init_rx_rings_cnic(bp);
6129 bnx2x_init_tx_rings_cnic(bp);
6136 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6140 /* Setup NIC internals and enable interrupts */
6141 for_each_eth_queue(bp, i)
6142 bnx2x_init_eth_fp(bp, i);
6144 /* ensure status block indices were read */
6146 bnx2x_init_rx_rings(bp);
6147 bnx2x_init_tx_rings(bp);
6150 /* Initialize MOD_ABS interrupts */
6151 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6152 bp->common.shmem_base,
6153 bp->common.shmem2_base, BP_PORT(bp));
6155 /* initialize the default status block and sp ring */
6156 bnx2x_init_def_sb(bp);
6157 bnx2x_update_dsb_idx(bp);
6158 bnx2x_init_sp_ring(bp);
6160 bnx2x_memset_stats(bp);
6164 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6166 bnx2x_init_eq_ring(bp);
6167 bnx2x_init_internal(bp, load_code);
6169 bnx2x_stats_init(bp);
6171 /* flush all before enabling interrupts */
6175 bnx2x_int_enable(bp);
6177 /* Check for SPIO5 */
6178 bnx2x_attn_int_deasserted0(bp,
6179 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6180 AEU_INPUTS_ATTN_BITS_SPIO5);
6183 /* gzip service functions */
6184 static int bnx2x_gunzip_init(struct bnx2x *bp)
6186 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6187 &bp->gunzip_mapping, GFP_KERNEL);
6188 if (bp->gunzip_buf == NULL)
6191 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6192 if (bp->strm == NULL)
6195 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6196 if (bp->strm->workspace == NULL)
6206 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6207 bp->gunzip_mapping);
6208 bp->gunzip_buf = NULL;
6211 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6215 static void bnx2x_gunzip_end(struct bnx2x *bp)
6218 vfree(bp->strm->workspace);
6223 if (bp->gunzip_buf) {
6224 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6225 bp->gunzip_mapping);
6226 bp->gunzip_buf = NULL;
6230 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6234 /* check gzip header */
6235 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6236 BNX2X_ERR("Bad gzip header\n");
6244 if (zbuf[3] & FNAME)
6245 while ((zbuf[n++] != 0) && (n < len));
6247 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6248 bp->strm->avail_in = len - n;
6249 bp->strm->next_out = bp->gunzip_buf;
6250 bp->strm->avail_out = FW_BUF_SIZE;
6252 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6256 rc = zlib_inflate(bp->strm, Z_FINISH);
6257 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6258 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6261 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6262 if (bp->gunzip_outlen & 0x3)
6264 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6266 bp->gunzip_outlen >>= 2;
6268 zlib_inflateEnd(bp->strm);
6270 if (rc == Z_STREAM_END)
6276 /* nic load/unload */
6279 * General service functions
6282 /* send a NIG loopback debug packet */
6283 static void bnx2x_lb_pckt(struct bnx2x *bp)
6287 /* Ethernet source and destination addresses */
6288 wb_write[0] = 0x55555555;
6289 wb_write[1] = 0x55555555;
6290 wb_write[2] = 0x20; /* SOP */
6291 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6293 /* NON-IP protocol */
6294 wb_write[0] = 0x09000000;
6295 wb_write[1] = 0x55555555;
6296 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6297 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6300 /* some of the internal memories
6301 * are not directly readable from the driver
6302 * to test them we send debug packets
6304 static int bnx2x_int_mem_test(struct bnx2x *bp)
6310 if (CHIP_REV_IS_FPGA(bp))
6312 else if (CHIP_REV_IS_EMUL(bp))
6317 /* Disable inputs of parser neighbor blocks */
6318 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6319 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6320 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6321 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6323 /* Write 0 to parser credits for CFC search request */
6324 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6326 /* send Ethernet packet */
6329 /* TODO do i reset NIG statistic? */
6330 /* Wait until NIG register shows 1 packet of size 0x10 */
6331 count = 1000 * factor;
6334 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6335 val = *bnx2x_sp(bp, wb_data[0]);
6339 usleep_range(10000, 20000);
6343 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6347 /* Wait until PRS register shows 1 packet */
6348 count = 1000 * factor;
6350 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6354 usleep_range(10000, 20000);
6358 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6362 /* Reset and init BRB, PRS */
6363 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6365 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6367 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6368 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6370 DP(NETIF_MSG_HW, "part2\n");
6372 /* Disable inputs of parser neighbor blocks */
6373 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6374 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6375 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6376 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6378 /* Write 0 to parser credits for CFC search request */
6379 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6381 /* send 10 Ethernet packets */
6382 for (i = 0; i < 10; i++)
6385 /* Wait until NIG register shows 10 + 1
6386 packets of size 11*0x10 = 0xb0 */
6387 count = 1000 * factor;
6390 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6391 val = *bnx2x_sp(bp, wb_data[0]);
6395 usleep_range(10000, 20000);
6399 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6403 /* Wait until PRS register shows 2 packets */
6404 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6406 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6408 /* Write 1 to parser credits for CFC search request */
6409 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6411 /* Wait until PRS register shows 3 packets */
6412 msleep(10 * factor);
6413 /* Wait until NIG register shows 1 packet of size 0x10 */
6414 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6416 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6418 /* clear NIG EOP FIFO */
6419 for (i = 0; i < 11; i++)
6420 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6421 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6423 BNX2X_ERR("clear of NIG failed\n");
6427 /* Reset and init BRB, PRS, NIG */
6428 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6430 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6432 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6433 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6434 if (!CNIC_SUPPORT(bp))
6436 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6438 /* Enable inputs of parser neighbor blocks */
6439 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6440 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6441 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6442 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6444 DP(NETIF_MSG_HW, "done\n");
6449 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6453 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6454 if (!CHIP_IS_E1x(bp))
6455 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6457 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6458 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6459 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6461 * mask read length error interrupts in brb for parser
6462 * (parsing unit and 'checksum and crc' unit)
6463 * these errors are legal (PU reads fixed length and CAC can cause
6464 * read length error on truncated packets)
6466 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6467 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6468 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6469 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6470 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6471 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6472 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6473 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6474 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6475 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6476 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6477 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6478 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6479 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6480 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6481 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6482 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6483 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6484 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6486 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6487 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6488 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6489 if (!CHIP_IS_E1x(bp))
6490 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6491 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6492 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6494 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6495 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6496 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6497 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6499 if (!CHIP_IS_E1x(bp))
6500 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6501 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6503 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6504 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6505 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6506 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6509 static void bnx2x_reset_common(struct bnx2x *bp)
6514 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6517 if (CHIP_IS_E3(bp)) {
6518 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6519 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6522 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6525 static void bnx2x_setup_dmae(struct bnx2x *bp)
6528 spin_lock_init(&bp->dmae_lock);
6531 static void bnx2x_init_pxp(struct bnx2x *bp)
6534 int r_order, w_order;
6536 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6537 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6538 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6540 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6542 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6546 bnx2x_init_pxp_arb(bp, r_order, w_order);
6549 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6559 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6560 SHARED_HW_CFG_FAN_FAILURE_MASK;
6562 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6566 * The fan failure mechanism is usually related to the PHY type since
6567 * the power consumption of the board is affected by the PHY. Currently,
6568 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6570 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6571 for (port = PORT_0; port < PORT_MAX; port++) {
6573 bnx2x_fan_failure_det_req(
6575 bp->common.shmem_base,
6576 bp->common.shmem2_base,
6580 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6582 if (is_required == 0)
6585 /* Fan failure is indicated by SPIO 5 */
6586 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6588 /* set to active low mode */
6589 val = REG_RD(bp, MISC_REG_SPIO_INT);
6590 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6591 REG_WR(bp, MISC_REG_SPIO_INT, val);
6593 /* enable interrupt to signal the IGU */
6594 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6595 val |= MISC_SPIO_SPIO5;
6596 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6599 void bnx2x_pf_disable(struct bnx2x *bp)
6601 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6602 val &= ~IGU_PF_CONF_FUNC_EN;
6604 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6605 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6606 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6609 static void bnx2x__common_init_phy(struct bnx2x *bp)
6611 u32 shmem_base[2], shmem2_base[2];
6612 /* Avoid common init in case MFW supports LFA */
6613 if (SHMEM2_RD(bp, size) >
6614 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6616 shmem_base[0] = bp->common.shmem_base;
6617 shmem2_base[0] = bp->common.shmem2_base;
6618 if (!CHIP_IS_E1x(bp)) {
6620 SHMEM2_RD(bp, other_shmem_base_addr);
6622 SHMEM2_RD(bp, other_shmem2_base_addr);
6624 bnx2x_acquire_phy_lock(bp);
6625 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6626 bp->common.chip_id);
6627 bnx2x_release_phy_lock(bp);
6631 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6633 * @bp: driver handle
6635 static int bnx2x_init_hw_common(struct bnx2x *bp)
6639 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6642 * take the RESET lock to protect undi_unload flow from accessing
6643 * registers while we're resetting the chip
6645 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6647 bnx2x_reset_common(bp);
6648 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6651 if (CHIP_IS_E3(bp)) {
6652 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6653 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6655 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6657 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6659 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6661 if (!CHIP_IS_E1x(bp)) {
6665 * 4-port mode or 2-port mode we need to turn of master-enable
6666 * for everyone, after that, turn it back on for self.
6667 * so, we disregard multi-function or not, and always disable
6668 * for all functions on the given path, this means 0,2,4,6 for
6669 * path 0 and 1,3,5,7 for path 1
6671 for (abs_func_id = BP_PATH(bp);
6672 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6673 if (abs_func_id == BP_ABS_FUNC(bp)) {
6675 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6680 bnx2x_pretend_func(bp, abs_func_id);
6681 /* clear pf enable */
6682 bnx2x_pf_disable(bp);
6683 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6687 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6688 if (CHIP_IS_E1(bp)) {
6689 /* enable HW interrupt from PXP on USDM overflow
6690 bit 16 on INT_MASK_0 */
6691 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6694 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6698 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6699 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6700 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6701 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6702 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6703 /* make sure this value is 0 */
6704 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6706 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6707 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6708 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6709 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6710 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6713 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6715 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6716 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6718 /* let the HW do it's magic ... */
6720 /* finish PXP init */
6721 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6723 BNX2X_ERR("PXP2 CFG failed\n");
6726 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6728 BNX2X_ERR("PXP2 RD_INIT failed\n");
6732 /* Timers bug workaround E2 only. We need to set the entire ILT to
6733 * have entries with value "0" and valid bit on.
6734 * This needs to be done by the first PF that is loaded in a path
6735 * (i.e. common phase)
6737 if (!CHIP_IS_E1x(bp)) {
6738 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6739 * (i.e. vnic3) to start even if it is marked as "scan-off".
6740 * This occurs when a different function (func2,3) is being marked
6741 * as "scan-off". Real-life scenario for example: if a driver is being
6742 * load-unloaded while func6,7 are down. This will cause the timer to access
6743 * the ilt, translate to a logical address and send a request to read/write.
6744 * Since the ilt for the function that is down is not valid, this will cause
6745 * a translation error which is unrecoverable.
6746 * The Workaround is intended to make sure that when this happens nothing fatal
6747 * will occur. The workaround:
6748 * 1. First PF driver which loads on a path will:
6749 * a. After taking the chip out of reset, by using pretend,
6750 * it will write "0" to the following registers of
6752 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6753 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6754 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6755 * And for itself it will write '1' to
6756 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6757 * dmae-operations (writing to pram for example.)
6758 * note: can be done for only function 6,7 but cleaner this
6760 * b. Write zero+valid to the entire ILT.
6761 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6762 * VNIC3 (of that port). The range allocated will be the
6763 * entire ILT. This is needed to prevent ILT range error.
6764 * 2. Any PF driver load flow:
6765 * a. ILT update with the physical addresses of the allocated
6767 * b. Wait 20msec. - note that this timeout is needed to make
6768 * sure there are no requests in one of the PXP internal
6769 * queues with "old" ILT addresses.
6770 * c. PF enable in the PGLC.
6771 * d. Clear the was_error of the PF in the PGLC. (could have
6772 * occurred while driver was down)
6773 * e. PF enable in the CFC (WEAK + STRONG)
6774 * f. Timers scan enable
6775 * 3. PF driver unload flow:
6776 * a. Clear the Timers scan_en.
6777 * b. Polling for scan_on=0 for that PF.
6778 * c. Clear the PF enable bit in the PXP.
6779 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6780 * e. Write zero+valid to all ILT entries (The valid bit must
6782 * f. If this is VNIC 3 of a port then also init
6783 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6784 * to the last entry in the ILT.
6787 * Currently the PF error in the PGLC is non recoverable.
6788 * In the future the there will be a recovery routine for this error.
6789 * Currently attention is masked.
6790 * Having an MCP lock on the load/unload process does not guarantee that
6791 * there is no Timer disable during Func6/7 enable. This is because the
6792 * Timers scan is currently being cleared by the MCP on FLR.
6793 * Step 2.d can be done only for PF6/7 and the driver can also check if
6794 * there is error before clearing it. But the flow above is simpler and
6796 * All ILT entries are written by zero+valid and not just PF6/7
6797 * ILT entries since in the future the ILT entries allocation for
6798 * PF-s might be dynamic.
6800 struct ilt_client_info ilt_cli;
6801 struct bnx2x_ilt ilt;
6802 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6803 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6805 /* initialize dummy TM client */
6807 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6808 ilt_cli.client_num = ILT_CLIENT_TM;
6810 /* Step 1: set zeroes to all ilt page entries with valid bit on
6811 * Step 2: set the timers first/last ilt entry to point
6812 * to the entire range to prevent ILT range error for 3rd/4th
6813 * vnic (this code assumes existence of the vnic)
6815 * both steps performed by call to bnx2x_ilt_client_init_op()
6816 * with dummy TM client
6818 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6819 * and his brother are split registers
6821 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6822 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6823 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6825 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6826 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6827 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6830 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6831 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6833 if (!CHIP_IS_E1x(bp)) {
6834 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6835 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6836 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6838 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6840 /* let the HW do it's magic ... */
6843 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6844 } while (factor-- && (val != 1));
6847 BNX2X_ERR("ATC_INIT failed\n");
6852 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6854 bnx2x_iov_init_dmae(bp);
6856 /* clean the DMAE memory */
6858 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6860 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6862 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6864 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6866 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6868 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6869 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6870 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6871 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6873 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6875 /* QM queues pointers table */
6876 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6878 /* soft reset pulse */
6879 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6880 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6882 if (CNIC_SUPPORT(bp))
6883 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6885 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6886 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6887 if (!CHIP_REV_IS_SLOW(bp))
6888 /* enable hw interrupt from doorbell Q */
6889 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6891 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6893 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6894 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6896 if (!CHIP_IS_E1(bp))
6897 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6899 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6900 if (IS_MF_AFEX(bp)) {
6901 /* configure that VNTag and VLAN headers must be
6902 * received in afex mode
6904 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6905 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6906 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6907 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6908 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6910 /* Bit-map indicating which L2 hdrs may appear
6911 * after the basic Ethernet header
6913 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6914 bp->path_has_ovlan ? 7 : 6);
6918 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6919 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6920 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6921 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6923 if (!CHIP_IS_E1x(bp)) {
6924 /* reset VFC memories */
6925 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6926 VFC_MEMORIES_RST_REG_CAM_RST |
6927 VFC_MEMORIES_RST_REG_RAM_RST);
6928 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6929 VFC_MEMORIES_RST_REG_CAM_RST |
6930 VFC_MEMORIES_RST_REG_RAM_RST);
6935 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6936 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6937 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6938 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6941 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6943 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6946 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6947 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6948 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6950 if (!CHIP_IS_E1x(bp)) {
6951 if (IS_MF_AFEX(bp)) {
6952 /* configure that VNTag and VLAN headers must be
6955 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6956 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6957 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6958 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6959 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6961 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6962 bp->path_has_ovlan ? 7 : 6);
6966 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6968 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6970 if (CNIC_SUPPORT(bp)) {
6971 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6972 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6973 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6974 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6975 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6976 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6977 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6978 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6979 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6980 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6982 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6984 if (sizeof(union cdu_context) != 1024)
6985 /* we currently assume that a context is 1024 bytes */
6986 dev_alert(&bp->pdev->dev,
6987 "please adjust the size of cdu_context(%ld)\n",
6988 (long)sizeof(union cdu_context));
6990 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6991 val = (4 << 24) + (0 << 12) + 1024;
6992 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6994 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6995 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6996 /* enable context validation interrupt from CFC */
6997 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6999 /* set the thresholds to prevent CFC/CDU race */
7000 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7002 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7004 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7005 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7007 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7008 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7010 /* Reset PCIE errors for debug */
7011 REG_WR(bp, 0x2814, 0xffffffff);
7012 REG_WR(bp, 0x3820, 0xffffffff);
7014 if (!CHIP_IS_E1x(bp)) {
7015 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7016 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7017 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7018 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7019 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7020 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7021 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7022 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7023 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7024 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7025 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7028 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7029 if (!CHIP_IS_E1(bp)) {
7030 /* in E3 this done in per-port section */
7031 if (!CHIP_IS_E3(bp))
7032 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7034 if (CHIP_IS_E1H(bp))
7035 /* not applicable for E2 (and above ...) */
7036 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7038 if (CHIP_REV_IS_SLOW(bp))
7041 /* finish CFC init */
7042 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7044 BNX2X_ERR("CFC LL_INIT failed\n");
7047 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7049 BNX2X_ERR("CFC AC_INIT failed\n");
7052 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7054 BNX2X_ERR("CFC CAM_INIT failed\n");
7057 REG_WR(bp, CFC_REG_DEBUG0, 0);
7059 if (CHIP_IS_E1(bp)) {
7060 /* read NIG statistic
7061 to see if this is our first up since powerup */
7062 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7063 val = *bnx2x_sp(bp, wb_data[0]);
7065 /* do internal memory self test */
7066 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7067 BNX2X_ERR("internal mem self test failed\n");
7072 bnx2x_setup_fan_failure_detection(bp);
7074 /* clear PXP2 attentions */
7075 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7077 bnx2x_enable_blocks_attention(bp);
7078 bnx2x_enable_blocks_parity(bp);
7080 if (!BP_NOMCP(bp)) {
7081 if (CHIP_IS_E1x(bp))
7082 bnx2x__common_init_phy(bp);
7084 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7090 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7092 * @bp: driver handle
7094 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7096 int rc = bnx2x_init_hw_common(bp);
7101 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7103 bnx2x__common_init_phy(bp);
7108 static int bnx2x_init_hw_port(struct bnx2x *bp)
7110 int port = BP_PORT(bp);
7111 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7115 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7117 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7119 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7120 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7121 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7123 /* Timers bug workaround: disables the pf_master bit in pglue at
7124 * common phase, we need to enable it here before any dmae access are
7125 * attempted. Therefore we manually added the enable-master to the
7126 * port phase (it also happens in the function phase)
7128 if (!CHIP_IS_E1x(bp))
7129 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7131 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7132 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7133 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7134 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7136 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7137 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7138 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7139 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7141 /* QM cid (connection) count */
7142 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7144 if (CNIC_SUPPORT(bp)) {
7145 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7146 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7147 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7150 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7152 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7154 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7157 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7158 else if (bp->dev->mtu > 4096) {
7159 if (bp->flags & ONE_PORT_FLAG)
7163 /* (24*1024 + val*4)/256 */
7164 low = 96 + (val/64) +
7165 ((val % 64) ? 1 : 0);
7168 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7169 high = low + 56; /* 14*1024/256 */
7170 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7171 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7174 if (CHIP_MODE_IS_4_PORT(bp))
7175 REG_WR(bp, (BP_PORT(bp) ?
7176 BRB1_REG_MAC_GUARANTIED_1 :
7177 BRB1_REG_MAC_GUARANTIED_0), 40);
7179 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7180 if (CHIP_IS_E3B0(bp)) {
7181 if (IS_MF_AFEX(bp)) {
7182 /* configure headers for AFEX mode */
7183 REG_WR(bp, BP_PORT(bp) ?
7184 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7185 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7186 REG_WR(bp, BP_PORT(bp) ?
7187 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7188 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7189 REG_WR(bp, BP_PORT(bp) ?
7190 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7191 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7193 /* Ovlan exists only if we are in multi-function +
7194 * switch-dependent mode, in switch-independent there
7195 * is no ovlan headers
7197 REG_WR(bp, BP_PORT(bp) ?
7198 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7199 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7200 (bp->path_has_ovlan ? 7 : 6));
7204 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7205 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7206 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7207 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7209 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7210 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7211 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7212 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7214 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7215 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7217 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7219 if (CHIP_IS_E1x(bp)) {
7220 /* configure PBF to work without PAUSE mtu 9000 */
7221 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7223 /* update threshold */
7224 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7225 /* update init credit */
7226 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7229 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7231 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7234 if (CNIC_SUPPORT(bp))
7235 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7237 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7238 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7240 if (CHIP_IS_E1(bp)) {
7241 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7242 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7244 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7246 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7248 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7249 /* init aeu_mask_attn_func_0/1:
7250 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7251 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7252 * bits 4-7 are used for "per vn group attention" */
7253 val = IS_MF(bp) ? 0xF7 : 0x7;
7254 /* Enable DCBX attention for all but E1 */
7255 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7256 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7258 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7260 if (!CHIP_IS_E1x(bp)) {
7261 /* Bit-map indicating which L2 hdrs may appear after the
7262 * basic Ethernet header
7265 REG_WR(bp, BP_PORT(bp) ?
7266 NIG_REG_P1_HDRS_AFTER_BASIC :
7267 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7269 REG_WR(bp, BP_PORT(bp) ?
7270 NIG_REG_P1_HDRS_AFTER_BASIC :
7271 NIG_REG_P0_HDRS_AFTER_BASIC,
7272 IS_MF_SD(bp) ? 7 : 6);
7275 REG_WR(bp, BP_PORT(bp) ?
7276 NIG_REG_LLH1_MF_MODE :
7277 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7279 if (!CHIP_IS_E3(bp))
7280 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7282 if (!CHIP_IS_E1(bp)) {
7283 /* 0x2 disable mf_ov, 0x1 enable */
7284 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7285 (IS_MF_SD(bp) ? 0x1 : 0x2));
7287 if (!CHIP_IS_E1x(bp)) {
7289 switch (bp->mf_mode) {
7290 case MULTI_FUNCTION_SD:
7293 case MULTI_FUNCTION_SI:
7294 case MULTI_FUNCTION_AFEX:
7299 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7300 NIG_REG_LLH0_CLS_TYPE), val);
7303 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7304 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7305 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7309 /* If SPIO5 is set to generate interrupts, enable it for this port */
7310 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7311 if (val & MISC_SPIO_SPIO5) {
7312 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7313 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7314 val = REG_RD(bp, reg_addr);
7315 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7316 REG_WR(bp, reg_addr, val);
7322 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7328 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7330 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7332 wb_write[0] = ONCHIP_ADDR1(addr);
7333 wb_write[1] = ONCHIP_ADDR2(addr);
7334 REG_WR_DMAE(bp, reg, wb_write, 2);
7337 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7339 u32 data, ctl, cnt = 100;
7340 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7341 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7342 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7343 u32 sb_bit = 1 << (idu_sb_id%32);
7344 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7345 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7347 /* Not supported in BC mode */
7348 if (CHIP_INT_MODE_IS_BC(bp))
7351 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7352 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7353 IGU_REGULAR_CLEANUP_SET |
7354 IGU_REGULAR_BCLEANUP;
7356 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7357 func_encode << IGU_CTRL_REG_FID_SHIFT |
7358 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7360 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7361 data, igu_addr_data);
7362 REG_WR(bp, igu_addr_data, data);
7365 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7367 REG_WR(bp, igu_addr_ctl, ctl);
7371 /* wait for clean up to finish */
7372 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7375 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7377 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7378 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7382 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7384 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7387 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7389 u32 i, base = FUNC_ILT_BASE(func);
7390 for (i = base; i < base + ILT_PER_FUNC; i++)
7391 bnx2x_ilt_wr(bp, i, 0);
7394 static void bnx2x_init_searcher(struct bnx2x *bp)
7396 int port = BP_PORT(bp);
7397 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7398 /* T1 hash bits value determines the T1 number of entries */
7399 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7402 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7405 struct bnx2x_func_state_params func_params = {NULL};
7406 struct bnx2x_func_switch_update_params *switch_update_params =
7407 &func_params.params.switch_update;
7409 /* Prepare parameters for function state transitions */
7410 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7411 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7413 func_params.f_obj = &bp->func_obj;
7414 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7416 /* Function parameters */
7417 switch_update_params->suspend = suspend;
7419 rc = bnx2x_func_state_change(bp, &func_params);
7424 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7426 int rc, i, port = BP_PORT(bp);
7427 int vlan_en = 0, mac_en[NUM_MACS];
7429 /* Close input from network */
7430 if (bp->mf_mode == SINGLE_FUNCTION) {
7431 bnx2x_set_rx_filter(&bp->link_params, 0);
7433 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7434 NIG_REG_LLH0_FUNC_EN);
7435 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7436 NIG_REG_LLH0_FUNC_EN, 0);
7437 for (i = 0; i < NUM_MACS; i++) {
7438 mac_en[i] = REG_RD(bp, port ?
7439 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7441 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7443 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7445 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7449 /* Close BMC to host */
7450 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7451 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7453 /* Suspend Tx switching to the PF. Completion of this ramrod
7454 * further guarantees that all the packets of that PF / child
7455 * VFs in BRB were processed by the Parser, so it is safe to
7456 * change the NIC_MODE register.
7458 rc = bnx2x_func_switch_update(bp, 1);
7460 BNX2X_ERR("Can't suspend tx-switching!\n");
7464 /* Change NIC_MODE register */
7465 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7467 /* Open input from network */
7468 if (bp->mf_mode == SINGLE_FUNCTION) {
7469 bnx2x_set_rx_filter(&bp->link_params, 1);
7471 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7472 NIG_REG_LLH0_FUNC_EN, vlan_en);
7473 for (i = 0; i < NUM_MACS; i++) {
7474 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7476 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7481 /* Enable BMC to host */
7482 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7483 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7485 /* Resume Tx switching to the PF */
7486 rc = bnx2x_func_switch_update(bp, 0);
7488 BNX2X_ERR("Can't resume tx-switching!\n");
7492 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7496 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7500 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7502 if (CONFIGURE_NIC_MODE(bp)) {
7503 /* Configure searcher as part of function hw init */
7504 bnx2x_init_searcher(bp);
7506 /* Reset NIC mode */
7507 rc = bnx2x_reset_nic_mode(bp);
7509 BNX2X_ERR("Can't change NIC mode!\n");
7516 static int bnx2x_init_hw_func(struct bnx2x *bp)
7518 int port = BP_PORT(bp);
7519 int func = BP_FUNC(bp);
7520 int init_phase = PHASE_PF0 + func;
7521 struct bnx2x_ilt *ilt = BP_ILT(bp);
7524 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7525 int i, main_mem_width, rc;
7527 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7529 /* FLR cleanup - hmmm */
7530 if (!CHIP_IS_E1x(bp)) {
7531 rc = bnx2x_pf_flr_clnup(bp);
7538 /* set MSI reconfigure capability */
7539 if (bp->common.int_block == INT_BLOCK_HC) {
7540 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7541 val = REG_RD(bp, addr);
7542 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7543 REG_WR(bp, addr, val);
7546 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7547 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7550 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7553 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7554 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7556 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7557 * those of the VFs, so start line should be reset
7559 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7560 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7561 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7562 ilt->lines[cdu_ilt_start + i].page_mapping =
7563 bp->context[i].cxt_mapping;
7564 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7567 bnx2x_ilt_init_op(bp, INITOP_SET);
7569 if (!CONFIGURE_NIC_MODE(bp)) {
7570 bnx2x_init_searcher(bp);
7571 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7572 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7575 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7576 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7579 if (!CHIP_IS_E1x(bp)) {
7580 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7582 /* Turn on a single ISR mode in IGU if driver is going to use
7585 if (!(bp->flags & USING_MSIX_FLAG))
7586 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7588 * Timers workaround bug: function init part.
7589 * Need to wait 20msec after initializing ILT,
7590 * needed to make sure there are no requests in
7591 * one of the PXP internal queues with "old" ILT addresses
7595 * Master enable - Due to WB DMAE writes performed before this
7596 * register is re-initialized as part of the regular function
7599 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7600 /* Enable the function in IGU */
7601 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7606 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7608 if (!CHIP_IS_E1x(bp))
7609 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7611 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7612 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7613 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7614 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7615 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7616 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7617 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7618 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7619 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7620 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7621 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7622 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7623 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7625 if (!CHIP_IS_E1x(bp))
7626 REG_WR(bp, QM_REG_PF_EN, 1);
7628 if (!CHIP_IS_E1x(bp)) {
7629 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7630 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7631 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7632 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7634 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7636 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7637 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7639 bnx2x_iov_init_dq(bp);
7641 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7642 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7643 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7644 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7645 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7646 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7647 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7648 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7649 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7650 if (!CHIP_IS_E1x(bp))
7651 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7653 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7655 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7657 if (!CHIP_IS_E1x(bp))
7658 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7661 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7662 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7665 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7667 /* HC init per function */
7668 if (bp->common.int_block == INT_BLOCK_HC) {
7669 if (CHIP_IS_E1H(bp)) {
7670 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7672 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7673 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7675 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7678 int num_segs, sb_idx, prod_offset;
7680 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7682 if (!CHIP_IS_E1x(bp)) {
7683 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7684 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7687 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7689 if (!CHIP_IS_E1x(bp)) {
7693 * E2 mode: address 0-135 match to the mapping memory;
7694 * 136 - PF0 default prod; 137 - PF1 default prod;
7695 * 138 - PF2 default prod; 139 - PF3 default prod;
7696 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7697 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7700 * E1.5 mode - In backward compatible mode;
7701 * for non default SB; each even line in the memory
7702 * holds the U producer and each odd line hold
7703 * the C producer. The first 128 producers are for
7704 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7705 * producers are for the DSB for each PF.
7706 * Each PF has five segments: (the order inside each
7707 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7708 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7709 * 144-147 attn prods;
7711 /* non-default-status-blocks */
7712 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7713 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7714 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7715 prod_offset = (bp->igu_base_sb + sb_idx) *
7718 for (i = 0; i < num_segs; i++) {
7719 addr = IGU_REG_PROD_CONS_MEMORY +
7720 (prod_offset + i) * 4;
7721 REG_WR(bp, addr, 0);
7723 /* send consumer update with value 0 */
7724 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7725 USTORM_ID, 0, IGU_INT_NOP, 1);
7726 bnx2x_igu_clear_sb(bp,
7727 bp->igu_base_sb + sb_idx);
7730 /* default-status-blocks */
7731 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7732 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7734 if (CHIP_MODE_IS_4_PORT(bp))
7735 dsb_idx = BP_FUNC(bp);
7737 dsb_idx = BP_VN(bp);
7739 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7740 IGU_BC_BASE_DSB_PROD + dsb_idx :
7741 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7744 * igu prods come in chunks of E1HVN_MAX (4) -
7745 * does not matters what is the current chip mode
7747 for (i = 0; i < (num_segs * E1HVN_MAX);
7749 addr = IGU_REG_PROD_CONS_MEMORY +
7750 (prod_offset + i)*4;
7751 REG_WR(bp, addr, 0);
7753 /* send consumer update with 0 */
7754 if (CHIP_INT_MODE_IS_BC(bp)) {
7755 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7756 USTORM_ID, 0, IGU_INT_NOP, 1);
7757 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7758 CSTORM_ID, 0, IGU_INT_NOP, 1);
7759 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7760 XSTORM_ID, 0, IGU_INT_NOP, 1);
7761 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7762 TSTORM_ID, 0, IGU_INT_NOP, 1);
7763 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7764 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7766 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7767 USTORM_ID, 0, IGU_INT_NOP, 1);
7768 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7769 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7771 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7773 /* !!! These should become driver const once
7774 rf-tool supports split-68 const */
7775 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7776 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7777 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7778 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7779 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7780 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7784 /* Reset PCIE errors for debug */
7785 REG_WR(bp, 0x2114, 0xffffffff);
7786 REG_WR(bp, 0x2120, 0xffffffff);
7788 if (CHIP_IS_E1x(bp)) {
7789 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7790 main_mem_base = HC_REG_MAIN_MEMORY +
7791 BP_PORT(bp) * (main_mem_size * 4);
7792 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7795 val = REG_RD(bp, main_mem_prty_clr);
7798 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7801 /* Clear "false" parity errors in MSI-X table */
7802 for (i = main_mem_base;
7803 i < main_mem_base + main_mem_size * 4;
7804 i += main_mem_width) {
7805 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7806 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7807 i, main_mem_width / 4);
7809 /* Clear HC parity attention */
7810 REG_RD(bp, main_mem_prty_clr);
7813 #ifdef BNX2X_STOP_ON_ERROR
7814 /* Enable STORMs SP logging */
7815 REG_WR8(bp, BAR_USTRORM_INTMEM +
7816 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7817 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7818 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7819 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7820 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7821 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7822 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7825 bnx2x_phy_probe(&bp->link_params);
7830 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7832 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7834 if (!CHIP_IS_E1x(bp))
7835 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7836 sizeof(struct host_hc_status_block_e2));
7838 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7839 sizeof(struct host_hc_status_block_e1x));
7841 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7844 void bnx2x_free_mem(struct bnx2x *bp)
7848 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7849 sizeof(struct host_sp_status_block));
7851 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7852 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7854 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7855 sizeof(struct bnx2x_slowpath));
7857 for (i = 0; i < L2_ILT_LINES(bp); i++)
7858 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7859 bp->context[i].size);
7860 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7862 BNX2X_FREE(bp->ilt->lines);
7864 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7866 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7867 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7869 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7871 bnx2x_iov_free_mem(bp);
7874 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7876 if (!CHIP_IS_E1x(bp))
7877 /* size = the status block + ramrod buffers */
7878 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7879 sizeof(struct host_hc_status_block_e2));
7881 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7882 &bp->cnic_sb_mapping,
7884 host_hc_status_block_e1x));
7886 if (CONFIGURE_NIC_MODE(bp) && !bp->t2)
7887 /* allocate searcher T2 table, as it wasn't allocated before */
7888 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7890 /* write address to which L5 should insert its values */
7891 bp->cnic_eth_dev.addr_drv_info_to_mcp =
7892 &bp->slowpath->drv_info_to_mcp;
7894 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7900 bnx2x_free_mem_cnic(bp);
7901 BNX2X_ERR("Can't allocate memory\n");
7905 int bnx2x_alloc_mem(struct bnx2x *bp)
7907 int i, allocated, context_size;
7909 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2)
7910 /* allocate searcher T2 table */
7911 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7913 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7914 sizeof(struct host_sp_status_block));
7916 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7917 sizeof(struct bnx2x_slowpath));
7919 /* Allocate memory for CDU context:
7920 * This memory is allocated separately and not in the generic ILT
7921 * functions because CDU differs in few aspects:
7922 * 1. There are multiple entities allocating memory for context -
7923 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7924 * its own ILT lines.
7925 * 2. Since CDU page-size is not a single 4KB page (which is the case
7926 * for the other ILT clients), to be efficient we want to support
7927 * allocation of sub-page-size in the last entry.
7928 * 3. Context pointers are used by the driver to pass to FW / update
7929 * the context (for the other ILT clients the pointers are used just to
7930 * free the memory during unload).
7932 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7934 for (i = 0, allocated = 0; allocated < context_size; i++) {
7935 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7936 (context_size - allocated));
7937 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7938 &bp->context[i].cxt_mapping,
7939 bp->context[i].size);
7940 allocated += bp->context[i].size;
7942 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7944 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7947 if (bnx2x_iov_alloc_mem(bp))
7950 /* Slow path ring */
7951 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7954 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7955 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7961 BNX2X_ERR("Can't allocate memory\n");
7966 * Init service functions
7969 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7970 struct bnx2x_vlan_mac_obj *obj, bool set,
7971 int mac_type, unsigned long *ramrod_flags)
7974 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7976 memset(&ramrod_param, 0, sizeof(ramrod_param));
7978 /* Fill general parameters */
7979 ramrod_param.vlan_mac_obj = obj;
7980 ramrod_param.ramrod_flags = *ramrod_flags;
7982 /* Fill a user request section if needed */
7983 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7984 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7986 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7988 /* Set the command: ADD or DEL */
7990 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7992 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7995 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7997 if (rc == -EEXIST) {
7998 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7999 /* do not treat adding same MAC as error */
8002 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8007 int bnx2x_del_all_macs(struct bnx2x *bp,
8008 struct bnx2x_vlan_mac_obj *mac_obj,
8009 int mac_type, bool wait_for_comp)
8012 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8014 /* Wait for completion of requested */
8016 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8018 /* Set the mac type of addresses we want to clear */
8019 __set_bit(mac_type, &vlan_mac_flags);
8021 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8023 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8028 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8030 if (is_zero_ether_addr(bp->dev->dev_addr) &&
8031 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
8032 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8033 "Ignoring Zero MAC for STORAGE SD mode\n");
8038 unsigned long ramrod_flags = 0;
8040 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8041 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8042 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8043 &bp->sp_objs->mac_obj, set,
8044 BNX2X_ETH_MAC, &ramrod_flags);
8046 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8047 bp->fp->index, true);
8051 int bnx2x_setup_leading(struct bnx2x *bp)
8053 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
8057 * bnx2x_set_int_mode - configure interrupt mode
8059 * @bp: driver handle
8061 * In case of MSI-X it will also try to enable MSI-X.
8063 int bnx2x_set_int_mode(struct bnx2x *bp)
8067 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
8071 case BNX2X_INT_MODE_MSIX:
8072 /* attempt to enable msix */
8073 rc = bnx2x_enable_msix(bp);
8079 /* vfs use only msix */
8080 if (rc && IS_VF(bp))
8083 /* failed to enable multiple MSI-X */
8084 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8086 1 + bp->num_cnic_queues);
8088 /* falling through... */
8089 case BNX2X_INT_MODE_MSI:
8090 bnx2x_enable_msi(bp);
8092 /* falling through... */
8093 case BNX2X_INT_MODE_INTX:
8094 bp->num_ethernet_queues = 1;
8095 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8096 BNX2X_DEV_INFO("set number of queues to 1\n");
8099 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8105 /* must be called prior to any HW initializations */
8106 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8109 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8110 return L2_ILT_LINES(bp);
8113 void bnx2x_ilt_set_info(struct bnx2x *bp)
8115 struct ilt_client_info *ilt_client;
8116 struct bnx2x_ilt *ilt = BP_ILT(bp);
8119 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8120 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8123 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8124 ilt_client->client_num = ILT_CLIENT_CDU;
8125 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8126 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8127 ilt_client->start = line;
8128 line += bnx2x_cid_ilt_lines(bp);
8130 if (CNIC_SUPPORT(bp))
8131 line += CNIC_ILT_LINES;
8132 ilt_client->end = line - 1;
8134 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8137 ilt_client->page_size,
8139 ilog2(ilt_client->page_size >> 12));
8142 if (QM_INIT(bp->qm_cid_count)) {
8143 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8144 ilt_client->client_num = ILT_CLIENT_QM;
8145 ilt_client->page_size = QM_ILT_PAGE_SZ;
8146 ilt_client->flags = 0;
8147 ilt_client->start = line;
8149 /* 4 bytes for each cid */
8150 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8153 ilt_client->end = line - 1;
8156 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8159 ilt_client->page_size,
8161 ilog2(ilt_client->page_size >> 12));
8164 if (CNIC_SUPPORT(bp)) {
8166 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8167 ilt_client->client_num = ILT_CLIENT_SRC;
8168 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8169 ilt_client->flags = 0;
8170 ilt_client->start = line;
8171 line += SRC_ILT_LINES;
8172 ilt_client->end = line - 1;
8175 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8178 ilt_client->page_size,
8180 ilog2(ilt_client->page_size >> 12));
8183 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8184 ilt_client->client_num = ILT_CLIENT_TM;
8185 ilt_client->page_size = TM_ILT_PAGE_SZ;
8186 ilt_client->flags = 0;
8187 ilt_client->start = line;
8188 line += TM_ILT_LINES;
8189 ilt_client->end = line - 1;
8192 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8195 ilt_client->page_size,
8197 ilog2(ilt_client->page_size >> 12));
8200 BUG_ON(line > ILT_MAX_LINES);
8204 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8206 * @bp: driver handle
8207 * @fp: pointer to fastpath
8208 * @init_params: pointer to parameters structure
8210 * parameters configured:
8211 * - HC configuration
8212 * - Queue's CDU context
8214 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8215 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8218 int cxt_index, cxt_offset;
8220 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8221 if (!IS_FCOE_FP(fp)) {
8222 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8223 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8225 /* If HC is supported, enable host coalescing in the transition
8228 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8229 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8232 init_params->rx.hc_rate = bp->rx_ticks ?
8233 (1000000 / bp->rx_ticks) : 0;
8234 init_params->tx.hc_rate = bp->tx_ticks ?
8235 (1000000 / bp->tx_ticks) : 0;
8238 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8242 * CQ index among the SB indices: FCoE clients uses the default
8243 * SB, therefore it's different.
8245 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8246 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8249 /* set maximum number of COSs supported by this queue */
8250 init_params->max_cos = fp->max_cos;
8252 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8253 fp->index, init_params->max_cos);
8255 /* set the context pointers queue object */
8256 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8257 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8258 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8260 init_params->cxts[cos] =
8261 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8265 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8266 struct bnx2x_queue_state_params *q_params,
8267 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8268 int tx_index, bool leading)
8270 memset(tx_only_params, 0, sizeof(*tx_only_params));
8272 /* Set the command */
8273 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8275 /* Set tx-only QUEUE flags: don't zero statistics */
8276 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8278 /* choose the index of the cid to send the slow path on */
8279 tx_only_params->cid_index = tx_index;
8281 /* Set general TX_ONLY_SETUP parameters */
8282 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8284 /* Set Tx TX_ONLY_SETUP parameters */
8285 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8288 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8289 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8290 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8291 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8293 /* send the ramrod */
8294 return bnx2x_queue_state_change(bp, q_params);
8298 * bnx2x_setup_queue - setup queue
8300 * @bp: driver handle
8301 * @fp: pointer to fastpath
8302 * @leading: is leading
8304 * This function performs 2 steps in a Queue state machine
8305 * actually: 1) RESET->INIT 2) INIT->SETUP
8308 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8311 struct bnx2x_queue_state_params q_params = {NULL};
8312 struct bnx2x_queue_setup_params *setup_params =
8313 &q_params.params.setup;
8314 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8315 &q_params.params.tx_only;
8319 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8321 /* reset IGU state skip FCoE L2 queue */
8322 if (!IS_FCOE_FP(fp))
8323 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8326 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8327 /* We want to wait for completion in this context */
8328 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8330 /* Prepare the INIT parameters */
8331 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8333 /* Set the command */
8334 q_params.cmd = BNX2X_Q_CMD_INIT;
8336 /* Change the state to INIT */
8337 rc = bnx2x_queue_state_change(bp, &q_params);
8339 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8343 DP(NETIF_MSG_IFUP, "init complete\n");
8345 /* Now move the Queue to the SETUP state... */
8346 memset(setup_params, 0, sizeof(*setup_params));
8348 /* Set QUEUE flags */
8349 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8351 /* Set general SETUP parameters */
8352 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8353 FIRST_TX_COS_INDEX);
8355 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8356 &setup_params->rxq_params);
8358 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8359 FIRST_TX_COS_INDEX);
8361 /* Set the command */
8362 q_params.cmd = BNX2X_Q_CMD_SETUP;
8365 bp->fcoe_init = true;
8367 /* Change the state to SETUP */
8368 rc = bnx2x_queue_state_change(bp, &q_params);
8370 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8374 /* loop through the relevant tx-only indices */
8375 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8376 tx_index < fp->max_cos;
8379 /* prepare and send tx-only ramrod*/
8380 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8381 tx_only_params, tx_index, leading);
8383 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8384 fp->index, tx_index);
8392 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8394 struct bnx2x_fastpath *fp = &bp->fp[index];
8395 struct bnx2x_fp_txdata *txdata;
8396 struct bnx2x_queue_state_params q_params = {NULL};
8399 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8401 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8402 /* We want to wait for completion in this context */
8403 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8405 /* close tx-only connections */
8406 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8407 tx_index < fp->max_cos;
8410 /* ascertain this is a normal queue*/
8411 txdata = fp->txdata_ptr[tx_index];
8413 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8416 /* send halt terminate on tx-only connection */
8417 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8418 memset(&q_params.params.terminate, 0,
8419 sizeof(q_params.params.terminate));
8420 q_params.params.terminate.cid_index = tx_index;
8422 rc = bnx2x_queue_state_change(bp, &q_params);
8426 /* send halt terminate on tx-only connection */
8427 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8428 memset(&q_params.params.cfc_del, 0,
8429 sizeof(q_params.params.cfc_del));
8430 q_params.params.cfc_del.cid_index = tx_index;
8431 rc = bnx2x_queue_state_change(bp, &q_params);
8435 /* Stop the primary connection: */
8436 /* ...halt the connection */
8437 q_params.cmd = BNX2X_Q_CMD_HALT;
8438 rc = bnx2x_queue_state_change(bp, &q_params);
8442 /* ...terminate the connection */
8443 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8444 memset(&q_params.params.terminate, 0,
8445 sizeof(q_params.params.terminate));
8446 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8447 rc = bnx2x_queue_state_change(bp, &q_params);
8450 /* ...delete cfc entry */
8451 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8452 memset(&q_params.params.cfc_del, 0,
8453 sizeof(q_params.params.cfc_del));
8454 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8455 return bnx2x_queue_state_change(bp, &q_params);
8458 static void bnx2x_reset_func(struct bnx2x *bp)
8460 int port = BP_PORT(bp);
8461 int func = BP_FUNC(bp);
8464 /* Disable the function in the FW */
8465 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8466 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8467 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8468 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8471 for_each_eth_queue(bp, i) {
8472 struct bnx2x_fastpath *fp = &bp->fp[i];
8473 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8474 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8478 if (CNIC_LOADED(bp))
8480 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8481 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8482 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8485 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8486 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8489 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8490 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8494 if (bp->common.int_block == INT_BLOCK_HC) {
8495 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8496 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8498 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8499 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8502 if (CNIC_LOADED(bp)) {
8503 /* Disable Timer scan */
8504 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8506 * Wait for at least 10ms and up to 2 second for the timers
8509 for (i = 0; i < 200; i++) {
8510 usleep_range(10000, 20000);
8511 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8516 bnx2x_clear_func_ilt(bp, func);
8518 /* Timers workaround bug for E2: if this is vnic-3,
8519 * we need to set the entire ilt range for this timers.
8521 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8522 struct ilt_client_info ilt_cli;
8523 /* use dummy TM client */
8524 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8526 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8527 ilt_cli.client_num = ILT_CLIENT_TM;
8529 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8532 /* this assumes that reset_port() called before reset_func()*/
8533 if (!CHIP_IS_E1x(bp))
8534 bnx2x_pf_disable(bp);
8539 static void bnx2x_reset_port(struct bnx2x *bp)
8541 int port = BP_PORT(bp);
8544 /* Reset physical Link */
8545 bnx2x__link_reset(bp);
8547 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8549 /* Do not rcv packets to BRB */
8550 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8551 /* Do not direct rcv packets that are not for MCP to the BRB */
8552 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8553 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8556 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8559 /* Check for BRB port occupancy */
8560 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8562 DP(NETIF_MSG_IFDOWN,
8563 "BRB1 is not empty %d blocks are occupied\n", val);
8565 /* TODO: Close Doorbell port? */
8568 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8570 struct bnx2x_func_state_params func_params = {NULL};
8572 /* Prepare parameters for function state transitions */
8573 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8575 func_params.f_obj = &bp->func_obj;
8576 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8578 func_params.params.hw_init.load_phase = load_code;
8580 return bnx2x_func_state_change(bp, &func_params);
8583 static int bnx2x_func_stop(struct bnx2x *bp)
8585 struct bnx2x_func_state_params func_params = {NULL};
8588 /* Prepare parameters for function state transitions */
8589 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8590 func_params.f_obj = &bp->func_obj;
8591 func_params.cmd = BNX2X_F_CMD_STOP;
8594 * Try to stop the function the 'good way'. If fails (in case
8595 * of a parity error during bnx2x_chip_cleanup()) and we are
8596 * not in a debug mode, perform a state transaction in order to
8597 * enable further HW_RESET transaction.
8599 rc = bnx2x_func_state_change(bp, &func_params);
8601 #ifdef BNX2X_STOP_ON_ERROR
8604 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8605 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8606 return bnx2x_func_state_change(bp, &func_params);
8614 * bnx2x_send_unload_req - request unload mode from the MCP.
8616 * @bp: driver handle
8617 * @unload_mode: requested function's unload mode
8619 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8621 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8624 int port = BP_PORT(bp);
8626 /* Select the UNLOAD request mode */
8627 if (unload_mode == UNLOAD_NORMAL)
8628 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8630 else if (bp->flags & NO_WOL_FLAG)
8631 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8634 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8635 u8 *mac_addr = bp->dev->dev_addr;
8639 /* The mac address is written to entries 1-4 to
8640 * preserve entry 0 which is used by the PMF
8642 u8 entry = (BP_VN(bp) + 1)*8;
8644 val = (mac_addr[0] << 8) | mac_addr[1];
8645 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8647 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8648 (mac_addr[4] << 8) | mac_addr[5];
8649 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8651 /* Enable the PME and clear the status */
8652 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8653 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8654 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8656 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8659 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8661 /* Send the request to the MCP */
8663 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8665 int path = BP_PATH(bp);
8667 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8668 path, load_count[path][0], load_count[path][1],
8669 load_count[path][2]);
8670 load_count[path][0]--;
8671 load_count[path][1 + port]--;
8672 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8673 path, load_count[path][0], load_count[path][1],
8674 load_count[path][2]);
8675 if (load_count[path][0] == 0)
8676 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8677 else if (load_count[path][1 + port] == 0)
8678 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8680 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8687 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8689 * @bp: driver handle
8690 * @keep_link: true iff link should be kept up
8692 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8694 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8696 /* Report UNLOAD_DONE to MCP */
8698 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8701 static int bnx2x_func_wait_started(struct bnx2x *bp)
8704 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8710 * (assumption: No Attention from MCP at this stage)
8711 * PMF probably in the middle of TX disable/enable transaction
8712 * 1. Sync IRS for default SB
8713 * 2. Sync SP queue - this guarantees us that attention handling started
8714 * 3. Wait, that TX disable/enable transaction completes
8716 * 1+2 guarantee that if DCBx attention was scheduled it already changed
8717 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8718 * received completion for the transaction the state is TX_STOPPED.
8719 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8723 /* make sure default SB ISR is done */
8725 synchronize_irq(bp->msix_table[0].vector);
8727 synchronize_irq(bp->pdev->irq);
8729 flush_workqueue(bnx2x_wq);
8731 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8732 BNX2X_F_STATE_STARTED && tout--)
8735 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8736 BNX2X_F_STATE_STARTED) {
8737 #ifdef BNX2X_STOP_ON_ERROR
8738 BNX2X_ERR("Wrong function state\n");
8742 * Failed to complete the transaction in a "good way"
8743 * Force both transactions with CLR bit
8745 struct bnx2x_func_state_params func_params = {NULL};
8747 DP(NETIF_MSG_IFDOWN,
8748 "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8750 func_params.f_obj = &bp->func_obj;
8751 __set_bit(RAMROD_DRV_CLR_ONLY,
8752 &func_params.ramrod_flags);
8754 /* STARTED-->TX_ST0PPED */
8755 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8756 bnx2x_func_state_change(bp, &func_params);
8758 /* TX_ST0PPED-->STARTED */
8759 func_params.cmd = BNX2X_F_CMD_TX_START;
8760 return bnx2x_func_state_change(bp, &func_params);
8767 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8769 int port = BP_PORT(bp);
8772 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8775 /* Wait until tx fastpath tasks complete */
8776 for_each_tx_queue(bp, i) {
8777 struct bnx2x_fastpath *fp = &bp->fp[i];
8779 for_each_cos_in_tx_queue(fp, cos)
8780 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8781 #ifdef BNX2X_STOP_ON_ERROR
8787 /* Give HW time to discard old tx messages */
8788 usleep_range(1000, 2000);
8790 /* Clean all ETH MACs */
8791 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8794 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8796 /* Clean up UC list */
8797 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8800 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8804 if (!CHIP_IS_E1(bp))
8805 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8807 /* Set "drop all" (stop Rx).
8808 * We need to take a netif_addr_lock() here in order to prevent
8809 * a race between the completion code and this code.
8811 netif_addr_lock_bh(bp->dev);
8812 /* Schedule the rx_mode command */
8813 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8814 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8816 bnx2x_set_storm_rx_mode(bp);
8818 /* Cleanup multicast configuration */
8819 rparam.mcast_obj = &bp->mcast_obj;
8820 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8822 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8824 netif_addr_unlock_bh(bp->dev);
8826 bnx2x_iov_chip_cleanup(bp);
8829 * Send the UNLOAD_REQUEST to the MCP. This will return if
8830 * this function should perform FUNC, PORT or COMMON HW
8833 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8836 * (assumption: No Attention from MCP at this stage)
8837 * PMF probably in the middle of TX disable/enable transaction
8839 rc = bnx2x_func_wait_started(bp);
8841 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8842 #ifdef BNX2X_STOP_ON_ERROR
8847 /* Close multi and leading connections
8848 * Completions for ramrods are collected in a synchronous way
8850 for_each_eth_queue(bp, i)
8851 if (bnx2x_stop_queue(bp, i))
8852 #ifdef BNX2X_STOP_ON_ERROR
8858 if (CNIC_LOADED(bp)) {
8859 for_each_cnic_queue(bp, i)
8860 if (bnx2x_stop_queue(bp, i))
8861 #ifdef BNX2X_STOP_ON_ERROR
8868 /* If SP settings didn't get completed so far - something
8869 * very wrong has happen.
8871 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8872 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8874 #ifndef BNX2X_STOP_ON_ERROR
8877 rc = bnx2x_func_stop(bp);
8879 BNX2X_ERR("Function stop failed!\n");
8880 #ifdef BNX2X_STOP_ON_ERROR
8885 /* Disable HW interrupts, NAPI */
8886 bnx2x_netif_stop(bp, 1);
8887 /* Delete all NAPI objects */
8888 bnx2x_del_all_napi(bp);
8889 if (CNIC_LOADED(bp))
8890 bnx2x_del_all_napi_cnic(bp);
8895 /* Reset the chip */
8896 rc = bnx2x_reset_hw(bp, reset_code);
8898 BNX2X_ERR("HW_RESET failed\n");
8900 /* Report UNLOAD_DONE to MCP */
8901 bnx2x_send_unload_done(bp, keep_link);
8904 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8908 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8910 if (CHIP_IS_E1(bp)) {
8911 int port = BP_PORT(bp);
8912 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8913 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8915 val = REG_RD(bp, addr);
8917 REG_WR(bp, addr, val);
8919 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8920 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8921 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8922 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8926 /* Close gates #2, #3 and #4: */
8927 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8931 /* Gates #2 and #4a are closed/opened for "not E1" only */
8932 if (!CHIP_IS_E1(bp)) {
8934 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8936 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8940 if (CHIP_IS_E1x(bp)) {
8941 /* Prevent interrupts from HC on both ports */
8942 val = REG_RD(bp, HC_REG_CONFIG_1);
8943 REG_WR(bp, HC_REG_CONFIG_1,
8944 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8945 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8947 val = REG_RD(bp, HC_REG_CONFIG_0);
8948 REG_WR(bp, HC_REG_CONFIG_0,
8949 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8950 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8952 /* Prevent incoming interrupts in IGU */
8953 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8955 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8957 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8958 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8961 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8962 close ? "closing" : "opening");
8966 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8968 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8970 /* Do some magic... */
8971 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8972 *magic_val = val & SHARED_MF_CLP_MAGIC;
8973 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8977 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8979 * @bp: driver handle
8980 * @magic_val: old value of the `magic' bit.
8982 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8984 /* Restore the `magic' bit value... */
8985 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8986 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8987 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8991 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8993 * @bp: driver handle
8994 * @magic_val: old value of 'magic' bit.
8996 * Takes care of CLP configurations.
8998 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9001 u32 validity_offset;
9003 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9005 /* Set `magic' bit in order to save MF config */
9006 if (!CHIP_IS_E1(bp))
9007 bnx2x_clp_reset_prep(bp, magic_val);
9009 /* Get shmem offset */
9010 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9012 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9014 /* Clear validity map flags */
9016 REG_WR(bp, shmem + validity_offset, 0);
9019 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9020 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9023 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9025 * @bp: driver handle
9027 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9029 /* special handling for emulation and FPGA,
9030 wait 10 times longer */
9031 if (CHIP_REV_IS_SLOW(bp))
9032 msleep(MCP_ONE_TIMEOUT*10);
9034 msleep(MCP_ONE_TIMEOUT);
9038 * initializes bp->common.shmem_base and waits for validity signature to appear
9040 static int bnx2x_init_shmem(struct bnx2x *bp)
9046 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9047 if (bp->common.shmem_base) {
9048 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9049 if (val & SHR_MEM_VALIDITY_MB)
9053 bnx2x_mcp_wait_one(bp);
9055 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9057 BNX2X_ERR("BAD MCP validity signature\n");
9062 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9064 int rc = bnx2x_init_shmem(bp);
9066 /* Restore the `magic' bit value */
9067 if (!CHIP_IS_E1(bp))
9068 bnx2x_clp_reset_done(bp, magic_val);
9073 static void bnx2x_pxp_prep(struct bnx2x *bp)
9075 if (!CHIP_IS_E1(bp)) {
9076 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9077 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9083 * Reset the whole chip except for:
9085 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9088 * - MISC (including AEU)
9092 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9094 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9095 u32 global_bits2, stay_reset2;
9098 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9099 * (per chip) blocks.
9102 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9103 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9105 /* Don't reset the following blocks.
9106 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9107 * reset, as in 4 port device they might still be owned
9108 * by the MCP (there is only one leader per path).
9111 MISC_REGISTERS_RESET_REG_1_RST_HC |
9112 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9113 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9116 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9117 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9118 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9119 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9120 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9121 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9122 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9123 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9124 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9125 MISC_REGISTERS_RESET_REG_2_PGLC |
9126 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9127 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9128 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9129 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9130 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9131 MISC_REGISTERS_RESET_REG_2_UMAC1;
9134 * Keep the following blocks in reset:
9135 * - all xxMACs are handled by the bnx2x_link code.
9138 MISC_REGISTERS_RESET_REG_2_XMAC |
9139 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9141 /* Full reset masks according to the chip */
9142 reset_mask1 = 0xffffffff;
9145 reset_mask2 = 0xffff;
9146 else if (CHIP_IS_E1H(bp))
9147 reset_mask2 = 0x1ffff;
9148 else if (CHIP_IS_E2(bp))
9149 reset_mask2 = 0xfffff;
9150 else /* CHIP_IS_E3 */
9151 reset_mask2 = 0x3ffffff;
9153 /* Don't reset global blocks unless we need to */
9155 reset_mask2 &= ~global_bits2;
9158 * In case of attention in the QM, we need to reset PXP
9159 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9160 * because otherwise QM reset would release 'close the gates' shortly
9161 * before resetting the PXP, then the PSWRQ would send a write
9162 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9163 * read the payload data from PSWWR, but PSWWR would not
9164 * respond. The write queue in PGLUE would stuck, dmae commands
9165 * would not return. Therefore it's important to reset the second
9166 * reset register (containing the
9167 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9168 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9171 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9172 reset_mask2 & (~not_reset_mask2));
9174 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9175 reset_mask1 & (~not_reset_mask1));
9180 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9181 reset_mask2 & (~stay_reset2));
9186 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9191 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9192 * It should get cleared in no more than 1s.
9194 * @bp: driver handle
9196 * It should get cleared in no more than 1s. Returns 0 if
9197 * pending writes bit gets cleared.
9199 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9205 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9210 usleep_range(1000, 2000);
9211 } while (cnt-- > 0);
9214 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9222 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9226 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9229 /* Empty the Tetris buffer, wait for 1s */
9231 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9232 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9233 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9234 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9235 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9237 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9239 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9240 ((port_is_idle_0 & 0x1) == 0x1) &&
9241 ((port_is_idle_1 & 0x1) == 0x1) &&
9242 (pgl_exp_rom2 == 0xffffffff) &&
9243 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9245 usleep_range(1000, 2000);
9246 } while (cnt-- > 0);
9249 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9250 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9251 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9258 /* Close gates #2, #3 and #4 */
9259 bnx2x_set_234_gates(bp, true);
9261 /* Poll for IGU VQs for 57712 and newer chips */
9262 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9265 /* TBD: Indicate that "process kill" is in progress to MCP */
9267 /* Clear "unprepared" bit */
9268 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9271 /* Make sure all is written to the chip before the reset */
9274 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9275 * PSWHST, GRC and PSWRD Tetris buffer.
9277 usleep_range(1000, 2000);
9279 /* Prepare to chip reset: */
9282 bnx2x_reset_mcp_prep(bp, &val);
9288 /* reset the chip */
9289 bnx2x_process_kill_chip_reset(bp, global);
9292 /* Recover after reset: */
9294 if (global && bnx2x_reset_mcp_comp(bp, val))
9297 /* TBD: Add resetting the NO_MCP mode DB here */
9299 /* Open the gates #2, #3 and #4 */
9300 bnx2x_set_234_gates(bp, false);
9302 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9303 * reset state, re-enable attentions. */
9308 static int bnx2x_leader_reset(struct bnx2x *bp)
9311 bool global = bnx2x_reset_is_global(bp);
9314 /* if not going to reset MCP - load "fake" driver to reset HW while
9315 * driver is owner of the HW
9317 if (!global && !BP_NOMCP(bp)) {
9318 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9319 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9321 BNX2X_ERR("MCP response failure, aborting\n");
9323 goto exit_leader_reset;
9325 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9326 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9327 BNX2X_ERR("MCP unexpected resp, aborting\n");
9329 goto exit_leader_reset2;
9331 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9333 BNX2X_ERR("MCP response failure, aborting\n");
9335 goto exit_leader_reset2;
9339 /* Try to recover after the failure */
9340 if (bnx2x_process_kill(bp, global)) {
9341 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9344 goto exit_leader_reset2;
9348 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9351 bnx2x_set_reset_done(bp);
9353 bnx2x_clear_reset_global(bp);
9356 /* unload "fake driver" if it was loaded */
9357 if (!global && !BP_NOMCP(bp)) {
9358 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9359 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9363 bnx2x_release_leader_lock(bp);
9368 static void bnx2x_recovery_failed(struct bnx2x *bp)
9370 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9372 /* Disconnect this device */
9373 netif_device_detach(bp->dev);
9376 * Block ifup for all function on this engine until "process kill"
9379 bnx2x_set_reset_in_progress(bp);
9381 /* Shut down the power */
9382 bnx2x_set_power_state(bp, PCI_D3hot);
9384 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9390 * Assumption: runs under rtnl lock. This together with the fact
9391 * that it's called only from bnx2x_sp_rtnl() ensure that it
9392 * will never be called when netif_running(bp->dev) is false.
9394 static void bnx2x_parity_recover(struct bnx2x *bp)
9396 bool global = false;
9397 u32 error_recovered, error_unrecovered;
9400 DP(NETIF_MSG_HW, "Handling parity\n");
9402 switch (bp->recovery_state) {
9403 case BNX2X_RECOVERY_INIT:
9404 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9405 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9406 WARN_ON(!is_parity);
9408 /* Try to get a LEADER_LOCK HW lock */
9409 if (bnx2x_trylock_leader_lock(bp)) {
9410 bnx2x_set_reset_in_progress(bp);
9412 * Check if there is a global attention and if
9413 * there was a global attention, set the global
9418 bnx2x_set_reset_global(bp);
9423 /* Stop the driver */
9424 /* If interface has been removed - break */
9425 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9428 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9430 /* Ensure "is_leader", MCP command sequence and
9431 * "recovery_state" update values are seen on other
9437 case BNX2X_RECOVERY_WAIT:
9438 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9439 if (bp->is_leader) {
9440 int other_engine = BP_PATH(bp) ? 0 : 1;
9441 bool other_load_status =
9442 bnx2x_get_load_status(bp, other_engine);
9444 bnx2x_get_load_status(bp, BP_PATH(bp));
9445 global = bnx2x_reset_is_global(bp);
9448 * In case of a parity in a global block, let
9449 * the first leader that performs a
9450 * leader_reset() reset the global blocks in
9451 * order to clear global attentions. Otherwise
9452 * the gates will remain closed for that
9456 (global && other_load_status)) {
9457 /* Wait until all other functions get
9460 schedule_delayed_work(&bp->sp_rtnl_task,
9464 /* If all other functions got down -
9465 * try to bring the chip back to
9466 * normal. In any case it's an exit
9467 * point for a leader.
9469 if (bnx2x_leader_reset(bp)) {
9470 bnx2x_recovery_failed(bp);
9474 /* If we are here, means that the
9475 * leader has succeeded and doesn't
9476 * want to be a leader any more. Try
9477 * to continue as a none-leader.
9481 } else { /* non-leader */
9482 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9483 /* Try to get a LEADER_LOCK HW lock as
9484 * long as a former leader may have
9485 * been unloaded by the user or
9486 * released a leadership by another
9489 if (bnx2x_trylock_leader_lock(bp)) {
9490 /* I'm a leader now! Restart a
9497 schedule_delayed_work(&bp->sp_rtnl_task,
9503 * If there was a global attention, wait
9504 * for it to be cleared.
9506 if (bnx2x_reset_is_global(bp)) {
9507 schedule_delayed_work(
9514 bp->eth_stats.recoverable_error;
9516 bp->eth_stats.unrecoverable_error;
9517 bp->recovery_state =
9518 BNX2X_RECOVERY_NIC_LOADING;
9519 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9520 error_unrecovered++;
9522 "Recovery failed. Power cycle needed\n");
9523 /* Disconnect this device */
9524 netif_device_detach(bp->dev);
9525 /* Shut down the power */
9526 bnx2x_set_power_state(
9530 bp->recovery_state =
9531 BNX2X_RECOVERY_DONE;
9535 bp->eth_stats.recoverable_error =
9537 bp->eth_stats.unrecoverable_error =
9549 static int bnx2x_close(struct net_device *dev);
9551 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9552 * scheduled on a general queue in order to prevent a dead lock.
9554 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9556 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9560 if (!netif_running(bp->dev)) {
9565 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9566 #ifdef BNX2X_STOP_ON_ERROR
9567 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9568 "you will need to reboot when done\n");
9569 goto sp_rtnl_not_reset;
9572 * Clear all pending SP commands as we are going to reset the
9575 bp->sp_rtnl_state = 0;
9578 bnx2x_parity_recover(bp);
9584 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9585 #ifdef BNX2X_STOP_ON_ERROR
9586 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9587 "you will need to reboot when done\n");
9588 goto sp_rtnl_not_reset;
9592 * Clear all pending SP commands as we are going to reset the
9595 bp->sp_rtnl_state = 0;
9598 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9599 bnx2x_nic_load(bp, LOAD_NORMAL);
9604 #ifdef BNX2X_STOP_ON_ERROR
9607 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9608 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9609 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9610 bnx2x_after_function_update(bp);
9612 * in case of fan failure we need to reset id if the "stop on error"
9613 * debug flag is set, since we trying to prevent permanent overheating
9616 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9617 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9618 netif_device_detach(bp->dev);
9619 bnx2x_close(bp->dev);
9624 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9626 "sending set mcast vf pf channel message from rtnl sp-task\n");
9627 bnx2x_vfpf_set_mcast(bp->dev);
9629 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9630 &bp->sp_rtnl_state)){
9631 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9632 bnx2x_tx_disable(bp);
9633 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9637 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9638 &bp->sp_rtnl_state)) {
9640 "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9641 bnx2x_vfpf_storm_rx_mode(bp);
9644 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9645 &bp->sp_rtnl_state))
9646 bnx2x_pf_set_vfs_vlan(bp);
9648 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9649 * can be called from other contexts as well)
9653 /* enable SR-IOV if applicable */
9654 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9655 &bp->sp_rtnl_state)) {
9656 bnx2x_disable_sriov(bp);
9657 bnx2x_enable_sriov(bp);
9661 static void bnx2x_period_task(struct work_struct *work)
9663 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9665 if (!netif_running(bp->dev))
9666 goto period_task_exit;
9668 if (CHIP_REV_IS_SLOW(bp)) {
9669 BNX2X_ERR("period task called on emulation, ignoring\n");
9670 goto period_task_exit;
9673 bnx2x_acquire_phy_lock(bp);
9675 * The barrier is needed to ensure the ordering between the writing to
9676 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9681 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9683 /* Re-queue task in 1 sec */
9684 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9687 bnx2x_release_phy_lock(bp);
9693 * Init service functions
9696 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9698 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9699 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9700 return base + (BP_ABS_FUNC(bp)) * stride;
9703 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9704 struct bnx2x_mac_vals *vals)
9706 u32 val, base_addr, offset, mask, reset_reg;
9707 bool mac_stopped = false;
9708 u8 port = BP_PORT(bp);
9710 /* reset addresses as they also mark which values were changed */
9711 vals->bmac_addr = 0;
9712 vals->umac_addr = 0;
9713 vals->xmac_addr = 0;
9714 vals->emac_addr = 0;
9716 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9718 if (!CHIP_IS_E3(bp)) {
9719 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9720 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9721 if ((mask & reset_reg) && val) {
9723 BNX2X_DEV_INFO("Disable bmac Rx\n");
9724 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9725 : NIG_REG_INGRESS_BMAC0_MEM;
9726 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9727 : BIGMAC_REGISTER_BMAC_CONTROL;
9730 * use rd/wr since we cannot use dmae. This is safe
9731 * since MCP won't access the bus due to the request
9732 * to unload, and no function on the path can be
9733 * loaded at this time.
9735 wb_data[0] = REG_RD(bp, base_addr + offset);
9736 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9737 vals->bmac_addr = base_addr + offset;
9738 vals->bmac_val[0] = wb_data[0];
9739 vals->bmac_val[1] = wb_data[1];
9740 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9741 REG_WR(bp, vals->bmac_addr, wb_data[0]);
9742 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9744 BNX2X_DEV_INFO("Disable emac Rx\n");
9745 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9746 vals->emac_val = REG_RD(bp, vals->emac_addr);
9747 REG_WR(bp, vals->emac_addr, 0);
9750 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9751 BNX2X_DEV_INFO("Disable xmac Rx\n");
9752 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9753 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9754 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9756 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9758 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9759 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9760 REG_WR(bp, vals->xmac_addr, 0);
9763 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9764 if (mask & reset_reg) {
9765 BNX2X_DEV_INFO("Disable umac Rx\n");
9766 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9767 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9768 vals->umac_val = REG_RD(bp, vals->umac_addr);
9769 REG_WR(bp, vals->umac_addr, 0);
9778 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9779 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9780 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9781 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9783 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9786 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9788 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9789 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9791 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9792 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9794 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9798 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9800 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9801 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9803 BNX2X_ERR("MCP response failure, aborting\n");
9810 static struct bnx2x_prev_path_list *
9811 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9813 struct bnx2x_prev_path_list *tmp_list;
9815 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9816 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9817 bp->pdev->bus->number == tmp_list->bus &&
9818 BP_PATH(bp) == tmp_list->path)
9824 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9826 struct bnx2x_prev_path_list *tmp_list;
9829 rc = down_interruptible(&bnx2x_prev_sem);
9831 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9835 tmp_list = bnx2x_prev_path_get_entry(bp);
9840 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9844 up(&bnx2x_prev_sem);
9849 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9851 struct bnx2x_prev_path_list *tmp_list;
9854 if (down_trylock(&bnx2x_prev_sem))
9857 tmp_list = bnx2x_prev_path_get_entry(bp);
9859 if (tmp_list->aer) {
9860 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9864 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9869 up(&bnx2x_prev_sem);
9874 bool bnx2x_port_after_undi(struct bnx2x *bp)
9876 struct bnx2x_prev_path_list *entry;
9879 down(&bnx2x_prev_sem);
9881 entry = bnx2x_prev_path_get_entry(bp);
9882 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
9884 up(&bnx2x_prev_sem);
9889 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9891 struct bnx2x_prev_path_list *tmp_list;
9894 rc = down_interruptible(&bnx2x_prev_sem);
9896 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9900 /* Check whether the entry for this path already exists */
9901 tmp_list = bnx2x_prev_path_get_entry(bp);
9903 if (!tmp_list->aer) {
9904 BNX2X_ERR("Re-Marking the path.\n");
9906 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
9910 up(&bnx2x_prev_sem);
9913 up(&bnx2x_prev_sem);
9915 /* Create an entry for this path and add it */
9916 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9918 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9922 tmp_list->bus = bp->pdev->bus->number;
9923 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9924 tmp_list->path = BP_PATH(bp);
9926 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9928 rc = down_interruptible(&bnx2x_prev_sem);
9930 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9933 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
9935 list_add(&tmp_list->list, &bnx2x_prev_list);
9936 up(&bnx2x_prev_sem);
9942 static int bnx2x_do_flr(struct bnx2x *bp)
9946 struct pci_dev *dev = bp->pdev;
9948 if (CHIP_IS_E1x(bp)) {
9949 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9953 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9954 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9955 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9960 /* Wait for Transaction Pending bit clean */
9961 for (i = 0; i < 4; i++) {
9963 msleep((1 << (i - 1)) * 100);
9965 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9966 if (!(status & PCI_EXP_DEVSTA_TRPND))
9971 "transaction is not cleared; proceeding with reset anyway\n");
9975 BNX2X_DEV_INFO("Initiating FLR\n");
9976 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9981 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9985 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9987 /* Test if previous unload process was already finished for this path */
9988 if (bnx2x_prev_is_path_marked(bp))
9989 return bnx2x_prev_mcp_done(bp);
9991 BNX2X_DEV_INFO("Path is unmarked\n");
9993 /* If function has FLR capabilities, and existing FW version matches
9994 * the one required, then FLR will be sufficient to clean any residue
9995 * left by previous driver
9997 rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
10000 /* fw version is good */
10001 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10002 rc = bnx2x_do_flr(bp);
10006 /* FLR was performed */
10007 BNX2X_DEV_INFO("FLR successful\n");
10011 BNX2X_DEV_INFO("Could not FLR\n");
10013 /* Close the MCP request, return failure*/
10014 rc = bnx2x_prev_mcp_done(bp);
10016 rc = BNX2X_PREV_WAIT_NEEDED;
10021 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10023 u32 reset_reg, tmp_reg = 0, rc;
10024 bool prev_undi = false;
10025 struct bnx2x_mac_vals mac_vals;
10027 /* It is possible a previous function received 'common' answer,
10028 * but hasn't loaded yet, therefore creating a scenario of
10029 * multiple functions receiving 'common' on the same path.
10031 BNX2X_DEV_INFO("Common unload Flow\n");
10033 memset(&mac_vals, 0, sizeof(mac_vals));
10035 if (bnx2x_prev_is_path_marked(bp))
10036 return bnx2x_prev_mcp_done(bp);
10038 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10040 /* Reset should be performed after BRB is emptied */
10041 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10042 u32 timer_count = 1000;
10044 /* Close the MAC Rx to prevent BRB from filling up */
10045 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10047 /* close LLH filters towards the BRB */
10048 bnx2x_set_rx_filter(&bp->link_params, 0);
10050 /* Check if the UNDI driver was previously loaded
10051 * UNDI driver initializes CID offset for normal bell to 0x7
10053 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10054 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10055 if (tmp_reg == 0x7) {
10056 BNX2X_DEV_INFO("UNDI previously loaded\n");
10058 /* clear the UNDI indication */
10059 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10060 /* clear possible idle check errors */
10061 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10064 if (!CHIP_IS_E1x(bp))
10065 /* block FW from writing to host */
10066 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10068 /* wait until BRB is empty */
10069 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10070 while (timer_count) {
10071 u32 prev_brb = tmp_reg;
10073 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10077 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10079 /* reset timer as long as BRB actually gets emptied */
10080 if (prev_brb > tmp_reg)
10081 timer_count = 1000;
10085 /* If UNDI resides in memory, manually increment it */
10087 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
10093 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10096 /* No packets are in the pipeline, path is ready for reset */
10097 bnx2x_reset_common(bp);
10099 if (mac_vals.xmac_addr)
10100 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10101 if (mac_vals.umac_addr)
10102 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10103 if (mac_vals.emac_addr)
10104 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10105 if (mac_vals.bmac_addr) {
10106 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10107 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10110 rc = bnx2x_prev_mark_path(bp, prev_undi);
10112 bnx2x_prev_mcp_done(bp);
10116 return bnx2x_prev_mcp_done(bp);
10119 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10120 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10121 * the addresses of the transaction, resulting in was-error bit set in the pci
10122 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10123 * to clear the interrupt which detected this from the pglueb and the was done
10126 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10128 if (!CHIP_IS_E1x(bp)) {
10129 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10130 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10132 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10133 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10139 static int bnx2x_prev_unload(struct bnx2x *bp)
10141 int time_counter = 10;
10142 u32 rc, fw, hw_lock_reg, hw_lock_val;
10143 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10145 /* clear hw from errors which may have resulted from an interrupted
10146 * dmae transaction.
10148 bnx2x_prev_interrupted_dmae(bp);
10150 /* Release previously held locks */
10151 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10152 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10153 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10155 hw_lock_val = REG_RD(bp, hw_lock_reg);
10157 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10158 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10159 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10160 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10163 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10164 REG_WR(bp, hw_lock_reg, 0xffffffff);
10166 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10168 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10169 BNX2X_DEV_INFO("Release previously held alr\n");
10170 bnx2x_release_alr(bp);
10175 /* Lock MCP using an unload request */
10176 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10178 BNX2X_ERR("MCP response failure, aborting\n");
10183 rc = down_interruptible(&bnx2x_prev_sem);
10185 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10188 /* If Path is marked by EEH, ignore unload status */
10189 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10190 bnx2x_prev_path_get_entry(bp)->aer);
10191 up(&bnx2x_prev_sem);
10194 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10195 rc = bnx2x_prev_unload_common(bp);
10199 /* non-common reply from MCP might require looping */
10200 rc = bnx2x_prev_unload_uncommon(bp);
10201 if (rc != BNX2X_PREV_WAIT_NEEDED)
10205 } while (--time_counter);
10207 if (!time_counter || rc) {
10208 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10212 /* Mark function if its port was used to boot from SAN */
10213 if (bnx2x_port_after_undi(bp))
10214 bp->link_params.feature_config_flags |=
10215 FEATURE_CONFIG_BOOT_FROM_SAN;
10217 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10222 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10224 u32 val, val2, val3, val4, id, boot_mode;
10227 /* Get the chip revision id and number. */
10228 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10229 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10230 id = ((val & 0xffff) << 16);
10231 val = REG_RD(bp, MISC_REG_CHIP_REV);
10232 id |= ((val & 0xf) << 12);
10234 /* Metal is read from PCI regs, but we can't access >=0x400 from
10235 * the configuration space (so we need to reg_rd)
10237 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10238 id |= (((val >> 24) & 0xf) << 4);
10239 val = REG_RD(bp, MISC_REG_BOND_ID);
10241 bp->common.chip_id = id;
10243 /* force 57811 according to MISC register */
10244 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10245 if (CHIP_IS_57810(bp))
10246 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10247 (bp->common.chip_id & 0x0000FFFF);
10248 else if (CHIP_IS_57810_MF(bp))
10249 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10250 (bp->common.chip_id & 0x0000FFFF);
10251 bp->common.chip_id |= 0x1;
10254 /* Set doorbell size */
10255 bp->db_size = (1 << BNX2X_DB_SHIFT);
10257 if (!CHIP_IS_E1x(bp)) {
10258 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10259 if ((val & 1) == 0)
10260 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10262 val = (val >> 1) & 1;
10263 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10265 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10268 if (CHIP_MODE_IS_4_PORT(bp))
10269 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10271 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10273 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10274 bp->pfid = bp->pf_num; /* 0..7 */
10277 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10279 bp->link_params.chip_id = bp->common.chip_id;
10280 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10282 val = (REG_RD(bp, 0x2874) & 0x55);
10283 if ((bp->common.chip_id & 0x1) ||
10284 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10285 bp->flags |= ONE_PORT_FLAG;
10286 BNX2X_DEV_INFO("single port device\n");
10289 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10290 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10291 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10292 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10293 bp->common.flash_size, bp->common.flash_size);
10295 bnx2x_init_shmem(bp);
10297 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10298 MISC_REG_GENERIC_CR_1 :
10299 MISC_REG_GENERIC_CR_0));
10301 bp->link_params.shmem_base = bp->common.shmem_base;
10302 bp->link_params.shmem2_base = bp->common.shmem2_base;
10303 if (SHMEM2_RD(bp, size) >
10304 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10305 bp->link_params.lfa_base =
10306 REG_RD(bp, bp->common.shmem2_base +
10307 (u32)offsetof(struct shmem2_region,
10308 lfa_host_addr[BP_PORT(bp)]));
10310 bp->link_params.lfa_base = 0;
10311 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10312 bp->common.shmem_base, bp->common.shmem2_base);
10314 if (!bp->common.shmem_base) {
10315 BNX2X_DEV_INFO("MCP not active\n");
10316 bp->flags |= NO_MCP_FLAG;
10320 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10321 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10323 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10324 SHARED_HW_CFG_LED_MODE_MASK) >>
10325 SHARED_HW_CFG_LED_MODE_SHIFT);
10327 bp->link_params.feature_config_flags = 0;
10328 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10329 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10330 bp->link_params.feature_config_flags |=
10331 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10333 bp->link_params.feature_config_flags &=
10334 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10336 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10337 bp->common.bc_ver = val;
10338 BNX2X_DEV_INFO("bc_ver %X\n", val);
10339 if (val < BNX2X_BC_VER) {
10340 /* for now only warn
10341 * later we might need to enforce this */
10342 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10343 BNX2X_BC_VER, val);
10345 bp->link_params.feature_config_flags |=
10346 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10347 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10349 bp->link_params.feature_config_flags |=
10350 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10351 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10352 bp->link_params.feature_config_flags |=
10353 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10354 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10355 bp->link_params.feature_config_flags |=
10356 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10357 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10359 bp->link_params.feature_config_flags |=
10360 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10361 FEATURE_CONFIG_MT_SUPPORT : 0;
10363 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10364 BC_SUPPORTS_PFC_STATS : 0;
10366 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10367 BC_SUPPORTS_FCOE_FEATURES : 0;
10369 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10370 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10372 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10373 BC_SUPPORTS_RMMOD_CMD : 0;
10375 boot_mode = SHMEM_RD(bp,
10376 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10377 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10378 switch (boot_mode) {
10379 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10380 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10382 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10383 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10385 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10386 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10388 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10389 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10393 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10394 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10396 BNX2X_DEV_INFO("%sWoL capable\n",
10397 (bp->flags & NO_WOL_FLAG) ? "not " : "");
10399 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10400 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10401 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10402 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10404 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10405 val, val2, val3, val4);
10408 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10409 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10411 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10413 int pfid = BP_FUNC(bp);
10416 u8 fid, igu_sb_cnt = 0;
10418 bp->igu_base_sb = 0xff;
10419 if (CHIP_INT_MODE_IS_BC(bp)) {
10420 int vn = BP_VN(bp);
10421 igu_sb_cnt = bp->igu_sb_cnt;
10422 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10425 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10426 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10431 /* IGU in normal mode - read CAM */
10432 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10434 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10435 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10437 fid = IGU_FID(val);
10438 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10439 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10441 if (IGU_VEC(val) == 0)
10442 /* default status block */
10443 bp->igu_dsb_id = igu_sb_id;
10445 if (bp->igu_base_sb == 0xff)
10446 bp->igu_base_sb = igu_sb_id;
10452 #ifdef CONFIG_PCI_MSI
10453 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10454 * optional that number of CAM entries will not be equal to the value
10455 * advertised in PCI.
10456 * Driver should use the minimal value of both as the actual status
10459 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10462 if (igu_sb_cnt == 0) {
10463 BNX2X_ERR("CAM configuration error\n");
10470 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10472 int cfg_size = 0, idx, port = BP_PORT(bp);
10474 /* Aggregation of supported attributes of all external phys */
10475 bp->port.supported[0] = 0;
10476 bp->port.supported[1] = 0;
10477 switch (bp->link_params.num_phys) {
10479 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10483 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10487 if (bp->link_params.multi_phy_config &
10488 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10489 bp->port.supported[1] =
10490 bp->link_params.phy[EXT_PHY1].supported;
10491 bp->port.supported[0] =
10492 bp->link_params.phy[EXT_PHY2].supported;
10494 bp->port.supported[0] =
10495 bp->link_params.phy[EXT_PHY1].supported;
10496 bp->port.supported[1] =
10497 bp->link_params.phy[EXT_PHY2].supported;
10503 if (!(bp->port.supported[0] || bp->port.supported[1])) {
10504 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10506 dev_info.port_hw_config[port].external_phy_config),
10508 dev_info.port_hw_config[port].external_phy_config2));
10512 if (CHIP_IS_E3(bp))
10513 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10515 switch (switch_cfg) {
10516 case SWITCH_CFG_1G:
10517 bp->port.phy_addr = REG_RD(
10518 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10520 case SWITCH_CFG_10G:
10521 bp->port.phy_addr = REG_RD(
10522 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10525 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10526 bp->port.link_config[0]);
10530 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10531 /* mask what we support according to speed_cap_mask per configuration */
10532 for (idx = 0; idx < cfg_size; idx++) {
10533 if (!(bp->link_params.speed_cap_mask[idx] &
10534 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10535 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10537 if (!(bp->link_params.speed_cap_mask[idx] &
10538 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10539 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10541 if (!(bp->link_params.speed_cap_mask[idx] &
10542 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10543 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10545 if (!(bp->link_params.speed_cap_mask[idx] &
10546 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10547 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10549 if (!(bp->link_params.speed_cap_mask[idx] &
10550 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10551 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10552 SUPPORTED_1000baseT_Full);
10554 if (!(bp->link_params.speed_cap_mask[idx] &
10555 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10556 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10558 if (!(bp->link_params.speed_cap_mask[idx] &
10559 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10560 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10562 if (!(bp->link_params.speed_cap_mask[idx] &
10563 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10564 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
10567 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10568 bp->port.supported[1]);
10571 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10573 u32 link_config, idx, cfg_size = 0;
10574 bp->port.advertising[0] = 0;
10575 bp->port.advertising[1] = 0;
10576 switch (bp->link_params.num_phys) {
10585 for (idx = 0; idx < cfg_size; idx++) {
10586 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10587 link_config = bp->port.link_config[idx];
10588 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10589 case PORT_FEATURE_LINK_SPEED_AUTO:
10590 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10591 bp->link_params.req_line_speed[idx] =
10593 bp->port.advertising[idx] |=
10594 bp->port.supported[idx];
10595 if (bp->link_params.phy[EXT_PHY1].type ==
10596 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10597 bp->port.advertising[idx] |=
10598 (SUPPORTED_100baseT_Half |
10599 SUPPORTED_100baseT_Full);
10601 /* force 10G, no AN */
10602 bp->link_params.req_line_speed[idx] =
10604 bp->port.advertising[idx] |=
10605 (ADVERTISED_10000baseT_Full |
10611 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10612 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10613 bp->link_params.req_line_speed[idx] =
10615 bp->port.advertising[idx] |=
10616 (ADVERTISED_10baseT_Full |
10619 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10621 bp->link_params.speed_cap_mask[idx]);
10626 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10627 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10628 bp->link_params.req_line_speed[idx] =
10630 bp->link_params.req_duplex[idx] =
10632 bp->port.advertising[idx] |=
10633 (ADVERTISED_10baseT_Half |
10636 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10638 bp->link_params.speed_cap_mask[idx]);
10643 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10644 if (bp->port.supported[idx] &
10645 SUPPORTED_100baseT_Full) {
10646 bp->link_params.req_line_speed[idx] =
10648 bp->port.advertising[idx] |=
10649 (ADVERTISED_100baseT_Full |
10652 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10654 bp->link_params.speed_cap_mask[idx]);
10659 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10660 if (bp->port.supported[idx] &
10661 SUPPORTED_100baseT_Half) {
10662 bp->link_params.req_line_speed[idx] =
10664 bp->link_params.req_duplex[idx] =
10666 bp->port.advertising[idx] |=
10667 (ADVERTISED_100baseT_Half |
10670 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10672 bp->link_params.speed_cap_mask[idx]);
10677 case PORT_FEATURE_LINK_SPEED_1G:
10678 if (bp->port.supported[idx] &
10679 SUPPORTED_1000baseT_Full) {
10680 bp->link_params.req_line_speed[idx] =
10682 bp->port.advertising[idx] |=
10683 (ADVERTISED_1000baseT_Full |
10686 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10688 bp->link_params.speed_cap_mask[idx]);
10693 case PORT_FEATURE_LINK_SPEED_2_5G:
10694 if (bp->port.supported[idx] &
10695 SUPPORTED_2500baseX_Full) {
10696 bp->link_params.req_line_speed[idx] =
10698 bp->port.advertising[idx] |=
10699 (ADVERTISED_2500baseX_Full |
10702 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10704 bp->link_params.speed_cap_mask[idx]);
10709 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10710 if (bp->port.supported[idx] &
10711 SUPPORTED_10000baseT_Full) {
10712 bp->link_params.req_line_speed[idx] =
10714 bp->port.advertising[idx] |=
10715 (ADVERTISED_10000baseT_Full |
10718 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10720 bp->link_params.speed_cap_mask[idx]);
10724 case PORT_FEATURE_LINK_SPEED_20G:
10725 bp->link_params.req_line_speed[idx] = SPEED_20000;
10729 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10731 bp->link_params.req_line_speed[idx] =
10733 bp->port.advertising[idx] =
10734 bp->port.supported[idx];
10738 bp->link_params.req_flow_ctrl[idx] = (link_config &
10739 PORT_FEATURE_FLOW_CONTROL_MASK);
10740 if (bp->link_params.req_flow_ctrl[idx] ==
10741 BNX2X_FLOW_CTRL_AUTO) {
10742 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10743 bp->link_params.req_flow_ctrl[idx] =
10744 BNX2X_FLOW_CTRL_NONE;
10746 bnx2x_set_requested_fc(bp);
10749 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10750 bp->link_params.req_line_speed[idx],
10751 bp->link_params.req_duplex[idx],
10752 bp->link_params.req_flow_ctrl[idx],
10753 bp->port.advertising[idx]);
10757 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10759 __be16 mac_hi_be = cpu_to_be16(mac_hi);
10760 __be32 mac_lo_be = cpu_to_be32(mac_lo);
10761 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10762 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10765 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10767 int port = BP_PORT(bp);
10769 u32 ext_phy_type, ext_phy_config, eee_mode;
10771 bp->link_params.bp = bp;
10772 bp->link_params.port = port;
10774 bp->link_params.lane_config =
10775 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10777 bp->link_params.speed_cap_mask[0] =
10779 dev_info.port_hw_config[port].speed_capability_mask) &
10780 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10781 bp->link_params.speed_cap_mask[1] =
10783 dev_info.port_hw_config[port].speed_capability_mask2) &
10784 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10785 bp->port.link_config[0] =
10786 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10788 bp->port.link_config[1] =
10789 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10791 bp->link_params.multi_phy_config =
10792 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10793 /* If the device is capable of WoL, set the default state according
10796 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10797 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10798 (config & PORT_FEATURE_WOL_ENABLED));
10800 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10801 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10802 bp->flags |= NO_ISCSI_FLAG;
10803 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10804 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10805 bp->flags |= NO_FCOE_FLAG;
10807 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10808 bp->link_params.lane_config,
10809 bp->link_params.speed_cap_mask[0],
10810 bp->port.link_config[0]);
10812 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10813 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10814 bnx2x_phy_probe(&bp->link_params);
10815 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10817 bnx2x_link_settings_requested(bp);
10820 * If connected directly, work with the internal PHY, otherwise, work
10821 * with the external PHY
10825 dev_info.port_hw_config[port].external_phy_config);
10826 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10827 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10828 bp->mdio.prtad = bp->port.phy_addr;
10830 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10831 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10833 XGXS_EXT_PHY_ADDR(ext_phy_config);
10835 /* Configure link feature according to nvram value */
10836 eee_mode = (((SHMEM_RD(bp, dev_info.
10837 port_feature_config[port].eee_power_mode)) &
10838 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10839 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10840 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10841 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10842 EEE_MODE_ENABLE_LPI |
10843 EEE_MODE_OUTPUT_TIME;
10845 bp->link_params.eee_mode = 0;
10849 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10851 u32 no_flags = NO_ISCSI_FLAG;
10852 int port = BP_PORT(bp);
10853 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10854 drv_lic_key[port].max_iscsi_conn);
10856 if (!CNIC_SUPPORT(bp)) {
10857 bp->flags |= no_flags;
10861 /* Get the number of maximum allowed iSCSI connections */
10862 bp->cnic_eth_dev.max_iscsi_conn =
10863 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10864 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10866 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10867 bp->cnic_eth_dev.max_iscsi_conn);
10870 * If maximum allowed number of connections is zero -
10871 * disable the feature.
10873 if (!bp->cnic_eth_dev.max_iscsi_conn)
10874 bp->flags |= no_flags;
10877 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10880 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10881 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10882 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10883 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10886 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10887 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10888 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10889 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10892 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
10899 /* iterate over absolute function ids for this path: */
10900 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
10901 if (IS_MF_SD(bp)) {
10902 u32 cfg = MF_CFG_RD(bp,
10903 func_mf_config[fid].config);
10905 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
10906 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
10907 FUNC_MF_CFG_PROTOCOL_FCOE))
10910 u32 cfg = MF_CFG_RD(bp,
10911 func_ext_config[fid].
10914 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
10915 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
10920 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
10922 for (port = 0; port < port_cnt; port++) {
10923 u32 lic = SHMEM_RD(bp,
10924 drv_lic_key[port].max_fcoe_conn) ^
10925 FW_ENCODE_32BIT_PATTERN;
10934 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10936 int port = BP_PORT(bp);
10937 int func = BP_ABS_FUNC(bp);
10938 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10939 drv_lic_key[port].max_fcoe_conn);
10940 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
10942 if (!CNIC_SUPPORT(bp)) {
10943 bp->flags |= NO_FCOE_FLAG;
10947 /* Get the number of maximum allowed FCoE connections */
10948 bp->cnic_eth_dev.max_fcoe_conn =
10949 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10950 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10952 /* Calculate the number of maximum allowed FCoE tasks */
10953 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
10955 /* check if FCoE resources must be shared between different functions */
10957 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
10959 /* Read the WWN: */
10962 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10964 dev_info.port_hw_config[port].
10965 fcoe_wwn_port_name_upper);
10966 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10968 dev_info.port_hw_config[port].
10969 fcoe_wwn_port_name_lower);
10972 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10974 dev_info.port_hw_config[port].
10975 fcoe_wwn_node_name_upper);
10976 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10978 dev_info.port_hw_config[port].
10979 fcoe_wwn_node_name_lower);
10980 } else if (!IS_MF_SD(bp)) {
10982 * Read the WWN info only if the FCoE feature is enabled for
10985 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10986 bnx2x_get_ext_wwn_info(bp, func);
10988 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10989 bnx2x_get_ext_wwn_info(bp, func);
10992 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10995 * If maximum allowed number of connections is zero -
10996 * disable the feature.
10998 if (!bp->cnic_eth_dev.max_fcoe_conn)
10999 bp->flags |= NO_FCOE_FLAG;
11002 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11005 * iSCSI may be dynamically disabled but reading
11006 * info here we will decrease memory usage by driver
11007 * if the feature is disabled for good
11009 bnx2x_get_iscsi_info(bp);
11010 bnx2x_get_fcoe_info(bp);
11013 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11016 int func = BP_ABS_FUNC(bp);
11017 int port = BP_PORT(bp);
11018 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11019 u8 *fip_mac = bp->fip_mac;
11022 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11023 * FCoE MAC then the appropriate feature should be disabled.
11024 * In non SD mode features configuration comes from struct
11027 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
11028 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11029 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11030 val2 = MF_CFG_RD(bp, func_ext_config[func].
11031 iscsi_mac_addr_upper);
11032 val = MF_CFG_RD(bp, func_ext_config[func].
11033 iscsi_mac_addr_lower);
11034 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11036 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11038 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11041 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11042 val2 = MF_CFG_RD(bp, func_ext_config[func].
11043 fcoe_mac_addr_upper);
11044 val = MF_CFG_RD(bp, func_ext_config[func].
11045 fcoe_mac_addr_lower);
11046 bnx2x_set_mac_buf(fip_mac, val, val2);
11048 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11050 bp->flags |= NO_FCOE_FLAG;
11053 bp->mf_ext_config = cfg;
11055 } else { /* SD MODE */
11056 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11057 /* use primary mac as iscsi mac */
11058 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11060 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11062 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11063 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11064 /* use primary mac as fip mac */
11065 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11066 BNX2X_DEV_INFO("SD FCoE MODE\n");
11068 ("Read FIP MAC: %pM\n", fip_mac);
11072 /* If this is a storage-only interface, use SAN mac as
11073 * primary MAC. Notice that for SD this is already the case,
11074 * as the SAN mac was copied from the primary MAC.
11076 if (IS_MF_FCOE_AFEX(bp))
11077 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11079 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11081 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11083 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11085 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11086 fcoe_fip_mac_upper);
11087 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11088 fcoe_fip_mac_lower);
11089 bnx2x_set_mac_buf(fip_mac, val, val2);
11092 /* Disable iSCSI OOO if MAC configuration is invalid. */
11093 if (!is_valid_ether_addr(iscsi_mac)) {
11094 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11095 memset(iscsi_mac, 0, ETH_ALEN);
11098 /* Disable FCoE if MAC configuration is invalid. */
11099 if (!is_valid_ether_addr(fip_mac)) {
11100 bp->flags |= NO_FCOE_FLAG;
11101 memset(bp->fip_mac, 0, ETH_ALEN);
11105 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11108 int func = BP_ABS_FUNC(bp);
11109 int port = BP_PORT(bp);
11111 /* Zero primary MAC configuration */
11112 memset(bp->dev->dev_addr, 0, ETH_ALEN);
11114 if (BP_NOMCP(bp)) {
11115 BNX2X_ERROR("warning: random MAC workaround active\n");
11116 eth_hw_addr_random(bp->dev);
11117 } else if (IS_MF(bp)) {
11118 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11119 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11120 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11121 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11122 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11124 if (CNIC_SUPPORT(bp))
11125 bnx2x_get_cnic_mac_hwinfo(bp);
11127 /* in SF read MACs from port configuration */
11128 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11129 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11130 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11132 if (CNIC_SUPPORT(bp))
11133 bnx2x_get_cnic_mac_hwinfo(bp);
11136 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11138 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
11139 dev_err(&bp->pdev->dev,
11140 "bad Ethernet MAC address configuration: %pM\n"
11141 "change it manually before bringing up the appropriate network interface\n",
11142 bp->dev->dev_addr);
11145 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11150 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11151 /* Take function: tmp = func */
11152 tmp = BP_ABS_FUNC(bp);
11153 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11154 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11156 /* Take port: tmp = port */
11159 dev_info.port_hw_config[tmp].generic_features);
11160 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11165 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11167 int /*abs*/func = BP_ABS_FUNC(bp);
11172 bnx2x_get_common_hwinfo(bp);
11175 * initialize IGU parameters
11177 if (CHIP_IS_E1x(bp)) {
11178 bp->common.int_block = INT_BLOCK_HC;
11180 bp->igu_dsb_id = DEF_SB_IGU_ID;
11181 bp->igu_base_sb = 0;
11183 bp->common.int_block = INT_BLOCK_IGU;
11185 /* do not allow device reset during IGU info processing */
11186 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11188 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11190 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11193 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11195 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11196 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11197 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11199 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11201 usleep_range(1000, 2000);
11204 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11205 dev_err(&bp->pdev->dev,
11206 "FORCING Normal Mode failed!!!\n");
11207 bnx2x_release_hw_lock(bp,
11208 HW_LOCK_RESOURCE_RESET);
11213 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11214 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11215 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11217 BNX2X_DEV_INFO("IGU Normal Mode\n");
11219 rc = bnx2x_get_igu_cam_info(bp);
11220 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11226 * set base FW non-default (fast path) status block id, this value is
11227 * used to initialize the fw_sb_id saved on the fp/queue structure to
11228 * determine the id used by the FW.
11230 if (CHIP_IS_E1x(bp))
11231 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11233 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11234 * the same queue are indicated on the same IGU SB). So we prefer
11235 * FW and IGU SBs to be the same value.
11237 bp->base_fw_ndsb = bp->igu_base_sb;
11239 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11240 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11241 bp->igu_sb_cnt, bp->base_fw_ndsb);
11244 * Initialize MF configuration
11251 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11252 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11253 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11254 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11256 if (SHMEM2_HAS(bp, mf_cfg_addr))
11257 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11259 bp->common.mf_cfg_base = bp->common.shmem_base +
11260 offsetof(struct shmem_region, func_mb) +
11261 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11263 * get mf configuration:
11264 * 1. Existence of MF configuration
11265 * 2. MAC address must be legal (check only upper bytes)
11266 * for Switch-Independent mode;
11267 * OVLAN must be legal for Switch-Dependent mode
11268 * 3. SF_MODE configures specific MF mode
11270 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11271 /* get mf configuration */
11273 dev_info.shared_feature_config.config);
11274 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11277 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11278 val = MF_CFG_RD(bp, func_mf_config[func].
11280 /* check for legal mac (upper bytes)*/
11281 if (val != 0xffff) {
11282 bp->mf_mode = MULTI_FUNCTION_SI;
11283 bp->mf_config[vn] = MF_CFG_RD(bp,
11284 func_mf_config[func].config);
11286 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11288 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11289 if ((!CHIP_IS_E1x(bp)) &&
11290 (MF_CFG_RD(bp, func_mf_config[func].
11291 mac_upper) != 0xffff) &&
11293 afex_driver_support))) {
11294 bp->mf_mode = MULTI_FUNCTION_AFEX;
11295 bp->mf_config[vn] = MF_CFG_RD(bp,
11296 func_mf_config[func].config);
11298 BNX2X_DEV_INFO("can not configure afex mode\n");
11301 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11302 /* get OV configuration */
11303 val = MF_CFG_RD(bp,
11304 func_mf_config[FUNC_0].e1hov_tag);
11305 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11307 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11308 bp->mf_mode = MULTI_FUNCTION_SD;
11309 bp->mf_config[vn] = MF_CFG_RD(bp,
11310 func_mf_config[func].config);
11312 BNX2X_DEV_INFO("illegal OV for SD\n");
11314 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11315 bp->mf_config[vn] = 0;
11318 /* Unknown configuration: reset mf_config */
11319 bp->mf_config[vn] = 0;
11320 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11324 BNX2X_DEV_INFO("%s function mode\n",
11325 IS_MF(bp) ? "multi" : "single");
11327 switch (bp->mf_mode) {
11328 case MULTI_FUNCTION_SD:
11329 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11330 FUNC_MF_CFG_E1HOV_TAG_MASK;
11331 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11333 bp->path_has_ovlan = true;
11335 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11336 func, bp->mf_ov, bp->mf_ov);
11338 dev_err(&bp->pdev->dev,
11339 "No valid MF OV for func %d, aborting\n",
11344 case MULTI_FUNCTION_AFEX:
11345 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11347 case MULTI_FUNCTION_SI:
11348 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11353 dev_err(&bp->pdev->dev,
11354 "VN %d is in a single function mode, aborting\n",
11361 /* check if other port on the path needs ovlan:
11362 * Since MF configuration is shared between ports
11363 * Possible mixed modes are only
11364 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11366 if (CHIP_MODE_IS_4_PORT(bp) &&
11367 !bp->path_has_ovlan &&
11369 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11370 u8 other_port = !BP_PORT(bp);
11371 u8 other_func = BP_PATH(bp) + 2*other_port;
11372 val = MF_CFG_RD(bp,
11373 func_mf_config[other_func].e1hov_tag);
11374 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11375 bp->path_has_ovlan = true;
11379 /* adjust igu_sb_cnt to MF for E1x */
11380 if (CHIP_IS_E1x(bp) && IS_MF(bp))
11381 bp->igu_sb_cnt /= E1HVN_MAX;
11384 bnx2x_get_port_hwinfo(bp);
11386 /* Get MAC addresses */
11387 bnx2x_get_mac_hwinfo(bp);
11389 bnx2x_get_cnic_info(bp);
11394 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11396 int cnt, i, block_end, rodi;
11397 char vpd_start[BNX2X_VPD_LEN+1];
11398 char str_id_reg[VENDOR_ID_LEN+1];
11399 char str_id_cap[VENDOR_ID_LEN+1];
11401 char *vpd_extended_data = NULL;
11404 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11405 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11407 if (cnt < BNX2X_VPD_LEN)
11408 goto out_not_found;
11410 /* VPD RO tag should be first tag after identifier string, hence
11411 * we should be able to find it in first BNX2X_VPD_LEN chars
11413 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11414 PCI_VPD_LRDT_RO_DATA);
11416 goto out_not_found;
11418 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11419 pci_vpd_lrdt_size(&vpd_start[i]);
11421 i += PCI_VPD_LRDT_TAG_SIZE;
11423 if (block_end > BNX2X_VPD_LEN) {
11424 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11425 if (vpd_extended_data == NULL)
11426 goto out_not_found;
11428 /* read rest of vpd image into vpd_extended_data */
11429 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11430 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11431 block_end - BNX2X_VPD_LEN,
11432 vpd_extended_data + BNX2X_VPD_LEN);
11433 if (cnt < (block_end - BNX2X_VPD_LEN))
11434 goto out_not_found;
11435 vpd_data = vpd_extended_data;
11437 vpd_data = vpd_start;
11439 /* now vpd_data holds full vpd content in both cases */
11441 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11442 PCI_VPD_RO_KEYWORD_MFR_ID);
11444 goto out_not_found;
11446 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11448 if (len != VENDOR_ID_LEN)
11449 goto out_not_found;
11451 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11453 /* vendor specific info */
11454 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11455 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11456 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11457 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11459 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11460 PCI_VPD_RO_KEYWORD_VENDOR0);
11462 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11464 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11466 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11467 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11468 bp->fw_ver[len] = ' ';
11471 kfree(vpd_extended_data);
11475 kfree(vpd_extended_data);
11479 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11483 if (CHIP_REV_IS_FPGA(bp))
11484 SET_FLAGS(flags, MODE_FPGA);
11485 else if (CHIP_REV_IS_EMUL(bp))
11486 SET_FLAGS(flags, MODE_EMUL);
11488 SET_FLAGS(flags, MODE_ASIC);
11490 if (CHIP_MODE_IS_4_PORT(bp))
11491 SET_FLAGS(flags, MODE_PORT4);
11493 SET_FLAGS(flags, MODE_PORT2);
11495 if (CHIP_IS_E2(bp))
11496 SET_FLAGS(flags, MODE_E2);
11497 else if (CHIP_IS_E3(bp)) {
11498 SET_FLAGS(flags, MODE_E3);
11499 if (CHIP_REV(bp) == CHIP_REV_Ax)
11500 SET_FLAGS(flags, MODE_E3_A0);
11501 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11502 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11506 SET_FLAGS(flags, MODE_MF);
11507 switch (bp->mf_mode) {
11508 case MULTI_FUNCTION_SD:
11509 SET_FLAGS(flags, MODE_MF_SD);
11511 case MULTI_FUNCTION_SI:
11512 SET_FLAGS(flags, MODE_MF_SI);
11514 case MULTI_FUNCTION_AFEX:
11515 SET_FLAGS(flags, MODE_MF_AFEX);
11519 SET_FLAGS(flags, MODE_SF);
11521 #if defined(__LITTLE_ENDIAN)
11522 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11523 #else /*(__BIG_ENDIAN)*/
11524 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11526 INIT_MODE_FLAGS(bp) = flags;
11529 static int bnx2x_init_bp(struct bnx2x *bp)
11534 mutex_init(&bp->port.phy_mutex);
11535 mutex_init(&bp->fw_mb_mutex);
11536 spin_lock_init(&bp->stats_lock);
11537 sema_init(&bp->stats_sema, 1);
11539 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11540 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11541 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11543 rc = bnx2x_get_hwinfo(bp);
11547 eth_zero_addr(bp->dev->dev_addr);
11550 bnx2x_set_modes_bitmap(bp);
11552 rc = bnx2x_alloc_mem_bp(bp);
11556 bnx2x_read_fwinfo(bp);
11558 func = BP_FUNC(bp);
11560 /* need to reset chip if undi was active */
11561 if (IS_PF(bp) && !BP_NOMCP(bp)) {
11564 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11565 DRV_MSG_SEQ_NUMBER_MASK;
11566 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11568 bnx2x_prev_unload(bp);
11571 if (CHIP_REV_IS_FPGA(bp))
11572 dev_err(&bp->pdev->dev, "FPGA detected\n");
11574 if (BP_NOMCP(bp) && (func == 0))
11575 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11577 bp->disable_tpa = disable_tpa;
11578 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11580 /* Set TPA flags */
11581 if (bp->disable_tpa) {
11582 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11583 bp->dev->features &= ~NETIF_F_LRO;
11585 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11586 bp->dev->features |= NETIF_F_LRO;
11589 if (CHIP_IS_E1(bp))
11590 bp->dropless_fc = 0;
11592 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11596 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11598 bp->rx_ring_size = MAX_RX_AVAIL;
11600 /* make sure that the numbers are in the right granularity */
11601 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11602 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11604 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11606 init_timer(&bp->timer);
11607 bp->timer.expires = jiffies + bp->current_interval;
11608 bp->timer.data = (unsigned long) bp;
11609 bp->timer.function = bnx2x_timer;
11611 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11612 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11613 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11614 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11615 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11616 bnx2x_dcbx_init_params(bp);
11618 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11621 if (CHIP_IS_E1x(bp))
11622 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11624 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11626 /* multiple tx priority */
11629 else if (CHIP_IS_E1x(bp))
11630 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11631 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11632 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11633 else if (CHIP_IS_E3B0(bp))
11634 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11636 BNX2X_ERR("unknown chip %x revision %x\n",
11637 CHIP_NUM(bp), CHIP_REV(bp));
11638 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11640 /* We need at least one default status block for slow-path events,
11641 * second status block for the L2 queue, and a third status block for
11642 * CNIC if supported.
11644 if (CNIC_SUPPORT(bp))
11645 bp->min_msix_vec_cnt = 3;
11647 bp->min_msix_vec_cnt = 2;
11648 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11650 bp->dump_preset_idx = 1;
11655 /****************************************************************************
11656 * General service functions
11657 ****************************************************************************/
11660 * net_device service functions
11663 /* called with rtnl_lock */
11664 static int bnx2x_open(struct net_device *dev)
11666 struct bnx2x *bp = netdev_priv(dev);
11667 bool global = false;
11668 int other_engine = BP_PATH(bp) ? 0 : 1;
11669 bool other_load_status, load_status;
11672 bp->stats_init = true;
11674 netif_carrier_off(dev);
11676 bnx2x_set_power_state(bp, PCI_D0);
11678 /* If parity had happen during the unload, then attentions
11679 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11680 * want the first function loaded on the current engine to
11681 * complete the recovery.
11682 * Parity recovery is only relevant for PF driver.
11685 other_load_status = bnx2x_get_load_status(bp, other_engine);
11686 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11687 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11688 bnx2x_chk_parity_attn(bp, &global, true)) {
11690 /* If there are attentions and they are in a
11691 * global blocks, set the GLOBAL_RESET bit
11692 * regardless whether it will be this function
11693 * that will complete the recovery or not.
11696 bnx2x_set_reset_global(bp);
11698 /* Only the first function on the current
11699 * engine should try to recover in open. In case
11700 * of attentions in global blocks only the first
11701 * in the chip should try to recover.
11703 if ((!load_status &&
11704 (!global || !other_load_status)) &&
11705 bnx2x_trylock_leader_lock(bp) &&
11706 !bnx2x_leader_reset(bp)) {
11707 netdev_info(bp->dev,
11708 "Recovered in open\n");
11712 /* recovery has failed... */
11713 bnx2x_set_power_state(bp, PCI_D3hot);
11714 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11716 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11717 "If you still see this message after a few retries then power cycle is required.\n");
11724 bp->recovery_state = BNX2X_RECOVERY_DONE;
11725 rc = bnx2x_nic_load(bp, LOAD_OPEN);
11728 return bnx2x_open_epilog(bp);
11731 /* called with rtnl_lock */
11732 static int bnx2x_close(struct net_device *dev)
11734 struct bnx2x *bp = netdev_priv(dev);
11736 /* Unload the driver, release IRQs */
11737 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11742 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11743 struct bnx2x_mcast_ramrod_params *p)
11745 int mc_count = netdev_mc_count(bp->dev);
11746 struct bnx2x_mcast_list_elem *mc_mac =
11747 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11748 struct netdev_hw_addr *ha;
11753 INIT_LIST_HEAD(&p->mcast_list);
11755 netdev_for_each_mc_addr(ha, bp->dev) {
11756 mc_mac->mac = bnx2x_mc_addr(ha);
11757 list_add_tail(&mc_mac->link, &p->mcast_list);
11761 p->mcast_list_len = mc_count;
11766 static void bnx2x_free_mcast_macs_list(
11767 struct bnx2x_mcast_ramrod_params *p)
11769 struct bnx2x_mcast_list_elem *mc_mac =
11770 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11778 * bnx2x_set_uc_list - configure a new unicast MACs list.
11780 * @bp: driver handle
11782 * We will use zero (0) as a MAC type for these MACs.
11784 static int bnx2x_set_uc_list(struct bnx2x *bp)
11787 struct net_device *dev = bp->dev;
11788 struct netdev_hw_addr *ha;
11789 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11790 unsigned long ramrod_flags = 0;
11792 /* First schedule a cleanup up of old configuration */
11793 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11795 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11799 netdev_for_each_uc_addr(ha, dev) {
11800 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11801 BNX2X_UC_LIST_MAC, &ramrod_flags);
11802 if (rc == -EEXIST) {
11804 "Failed to schedule ADD operations: %d\n", rc);
11805 /* do not treat adding same MAC as error */
11808 } else if (rc < 0) {
11810 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11816 /* Execute the pending commands */
11817 __set_bit(RAMROD_CONT, &ramrod_flags);
11818 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11819 BNX2X_UC_LIST_MAC, &ramrod_flags);
11822 static int bnx2x_set_mc_list(struct bnx2x *bp)
11824 struct net_device *dev = bp->dev;
11825 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11828 rparam.mcast_obj = &bp->mcast_obj;
11830 /* first, clear all configured multicast MACs */
11831 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11833 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11837 /* then, configure a new MACs list */
11838 if (netdev_mc_count(dev)) {
11839 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11841 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11846 /* Now add the new MACs */
11847 rc = bnx2x_config_mcast(bp, &rparam,
11848 BNX2X_MCAST_CMD_ADD);
11850 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11853 bnx2x_free_mcast_macs_list(&rparam);
11859 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11860 void bnx2x_set_rx_mode(struct net_device *dev)
11862 struct bnx2x *bp = netdev_priv(dev);
11863 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11865 if (bp->state != BNX2X_STATE_OPEN) {
11866 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11870 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11872 if (dev->flags & IFF_PROMISC)
11873 rx_mode = BNX2X_RX_MODE_PROMISC;
11874 else if ((dev->flags & IFF_ALLMULTI) ||
11875 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11877 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11880 /* some multicasts */
11881 if (bnx2x_set_mc_list(bp) < 0)
11882 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11884 if (bnx2x_set_uc_list(bp) < 0)
11885 rx_mode = BNX2X_RX_MODE_PROMISC;
11887 /* configuring mcast to a vf involves sleeping (when we
11888 * wait for the pf's response). Since this function is
11889 * called from non sleepable context we must schedule
11890 * a work item for this purpose
11892 smp_mb__before_clear_bit();
11893 set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11894 &bp->sp_rtnl_state);
11895 smp_mb__after_clear_bit();
11896 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11900 bp->rx_mode = rx_mode;
11901 /* handle ISCSI SD mode */
11902 if (IS_MF_ISCSI_SD(bp))
11903 bp->rx_mode = BNX2X_RX_MODE_NONE;
11905 /* Schedule the rx_mode command */
11906 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11907 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11912 bnx2x_set_storm_rx_mode(bp);
11914 /* configuring rx mode to storms in a vf involves sleeping (when
11915 * we wait for the pf's response). Since this function is
11916 * called from non sleepable context we must schedule
11917 * a work item for this purpose
11919 smp_mb__before_clear_bit();
11920 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11921 &bp->sp_rtnl_state);
11922 smp_mb__after_clear_bit();
11923 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11927 /* called with rtnl_lock */
11928 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11929 int devad, u16 addr)
11931 struct bnx2x *bp = netdev_priv(netdev);
11935 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11936 prtad, devad, addr);
11938 /* The HW expects different devad if CL22 is used */
11939 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11941 bnx2x_acquire_phy_lock(bp);
11942 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11943 bnx2x_release_phy_lock(bp);
11944 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11951 /* called with rtnl_lock */
11952 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11953 u16 addr, u16 value)
11955 struct bnx2x *bp = netdev_priv(netdev);
11959 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11960 prtad, devad, addr, value);
11962 /* The HW expects different devad if CL22 is used */
11963 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11965 bnx2x_acquire_phy_lock(bp);
11966 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11967 bnx2x_release_phy_lock(bp);
11971 /* called with rtnl_lock */
11972 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11974 struct bnx2x *bp = netdev_priv(dev);
11975 struct mii_ioctl_data *mdio = if_mii(ifr);
11977 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11978 mdio->phy_id, mdio->reg_num, mdio->val_in);
11980 if (!netif_running(dev))
11983 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11986 #ifdef CONFIG_NET_POLL_CONTROLLER
11987 static void poll_bnx2x(struct net_device *dev)
11989 struct bnx2x *bp = netdev_priv(dev);
11992 for_each_eth_queue(bp, i) {
11993 struct bnx2x_fastpath *fp = &bp->fp[i];
11994 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11999 static int bnx2x_validate_addr(struct net_device *dev)
12001 struct bnx2x *bp = netdev_priv(dev);
12003 /* query the bulletin board for mac address configured by the PF */
12005 bnx2x_sample_bulletin(bp);
12007 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12008 BNX2X_ERR("Non-valid Ethernet address\n");
12009 return -EADDRNOTAVAIL;
12014 static const struct net_device_ops bnx2x_netdev_ops = {
12015 .ndo_open = bnx2x_open,
12016 .ndo_stop = bnx2x_close,
12017 .ndo_start_xmit = bnx2x_start_xmit,
12018 .ndo_select_queue = bnx2x_select_queue,
12019 .ndo_set_rx_mode = bnx2x_set_rx_mode,
12020 .ndo_set_mac_address = bnx2x_change_mac_addr,
12021 .ndo_validate_addr = bnx2x_validate_addr,
12022 .ndo_do_ioctl = bnx2x_ioctl,
12023 .ndo_change_mtu = bnx2x_change_mtu,
12024 .ndo_fix_features = bnx2x_fix_features,
12025 .ndo_set_features = bnx2x_set_features,
12026 .ndo_tx_timeout = bnx2x_tx_timeout,
12027 #ifdef CONFIG_NET_POLL_CONTROLLER
12028 .ndo_poll_controller = poll_bnx2x,
12030 .ndo_setup_tc = bnx2x_setup_tc,
12031 #ifdef CONFIG_BNX2X_SRIOV
12032 .ndo_set_vf_mac = bnx2x_set_vf_mac,
12033 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
12034 .ndo_get_vf_config = bnx2x_get_vf_config,
12036 #ifdef NETDEV_FCOE_WWNN
12037 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12040 #ifdef CONFIG_NET_RX_BUSY_POLL
12041 .ndo_busy_poll = bnx2x_low_latency_recv,
12045 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12047 struct device *dev = &bp->pdev->dev;
12049 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
12050 bp->flags |= USING_DAC_FLAG;
12051 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
12052 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
12055 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
12056 dev_err(dev, "System does not support DMA, aborting\n");
12063 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12064 struct net_device *dev, unsigned long board_type)
12068 bool chip_is_e1x = (board_type == BCM57710 ||
12069 board_type == BCM57711 ||
12070 board_type == BCM57711E);
12072 SET_NETDEV_DEV(dev, &pdev->dev);
12077 rc = pci_enable_device(pdev);
12079 dev_err(&bp->pdev->dev,
12080 "Cannot enable PCI device, aborting\n");
12084 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12085 dev_err(&bp->pdev->dev,
12086 "Cannot find PCI device base address, aborting\n");
12088 goto err_out_disable;
12091 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12092 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12094 goto err_out_disable;
12097 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12098 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12099 PCICFG_REVESION_ID_ERROR_VAL) {
12100 pr_err("PCI device error, probably due to fan failure, aborting\n");
12102 goto err_out_disable;
12105 if (atomic_read(&pdev->enable_cnt) == 1) {
12106 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12108 dev_err(&bp->pdev->dev,
12109 "Cannot obtain PCI resources, aborting\n");
12110 goto err_out_disable;
12113 pci_set_master(pdev);
12114 pci_save_state(pdev);
12118 bp->pm_cap = pdev->pm_cap;
12119 if (bp->pm_cap == 0) {
12120 dev_err(&bp->pdev->dev,
12121 "Cannot find power management capability, aborting\n");
12123 goto err_out_release;
12127 if (!pci_is_pcie(pdev)) {
12128 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12130 goto err_out_release;
12133 rc = bnx2x_set_coherency_mask(bp);
12135 goto err_out_release;
12137 dev->mem_start = pci_resource_start(pdev, 0);
12138 dev->base_addr = dev->mem_start;
12139 dev->mem_end = pci_resource_end(pdev, 0);
12141 dev->irq = pdev->irq;
12143 bp->regview = pci_ioremap_bar(pdev, 0);
12144 if (!bp->regview) {
12145 dev_err(&bp->pdev->dev,
12146 "Cannot map register space, aborting\n");
12148 goto err_out_release;
12151 /* In E1/E1H use pci device function given by kernel.
12152 * In E2/E3 read physical function from ME register since these chips
12153 * support Physical Device Assignment where kernel BDF maybe arbitrary
12154 * (depending on hypervisor).
12157 bp->pf_num = PCI_FUNC(pdev->devfn);
12160 pci_read_config_dword(bp->pdev,
12161 PCICFG_ME_REGISTER, &pci_cfg_dword);
12162 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12163 ME_REG_ABS_PF_NUM_SHIFT);
12165 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12167 /* clean indirect addresses */
12168 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12169 PCICFG_VENDOR_ID_OFFSET);
12171 * Clean the following indirect addresses for all functions since it
12172 * is not used by the driver.
12175 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12176 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12177 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12178 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12181 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12182 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12183 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12184 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12187 /* Enable internal target-read (in case we are probed after PF
12188 * FLR). Must be done prior to any BAR read access. Only for
12193 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12196 dev->watchdog_timeo = TX_TIMEOUT;
12198 dev->netdev_ops = &bnx2x_netdev_ops;
12199 bnx2x_set_ethtool_ops(bp, dev);
12201 dev->priv_flags |= IFF_UNICAST_FLT;
12203 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12204 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12205 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12206 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12207 if (!CHIP_IS_E1x(bp)) {
12208 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12209 dev->hw_enc_features =
12210 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12211 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12212 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12215 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12216 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12218 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12219 if (bp->flags & USING_DAC_FLAG)
12220 dev->features |= NETIF_F_HIGHDMA;
12222 /* Add Loopback capability to the device */
12223 dev->hw_features |= NETIF_F_LOOPBACK;
12226 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12229 /* get_port_hwinfo() will set prtad and mmds properly */
12230 bp->mdio.prtad = MDIO_PRTAD_NONE;
12232 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12233 bp->mdio.dev = dev;
12234 bp->mdio.mdio_read = bnx2x_mdio_read;
12235 bp->mdio.mdio_write = bnx2x_mdio_write;
12240 if (atomic_read(&pdev->enable_cnt) == 1)
12241 pci_release_regions(pdev);
12244 pci_disable_device(pdev);
12245 pci_set_drvdata(pdev, NULL);
12251 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width,
12252 enum bnx2x_pci_bus_speed *speed)
12254 u32 link_speed, val = 0;
12256 pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
12257 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12259 link_speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12261 switch (link_speed) {
12263 *speed = BNX2X_PCI_LINK_SPEED_8000;
12266 *speed = BNX2X_PCI_LINK_SPEED_5000;
12269 *speed = BNX2X_PCI_LINK_SPEED_2500;
12273 static int bnx2x_check_firmware(struct bnx2x *bp)
12275 const struct firmware *firmware = bp->firmware;
12276 struct bnx2x_fw_file_hdr *fw_hdr;
12277 struct bnx2x_fw_file_section *sections;
12278 u32 offset, len, num_ops;
12279 __be16 *ops_offsets;
12283 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12284 BNX2X_ERR("Wrong FW size\n");
12288 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12289 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12291 /* Make sure none of the offsets and sizes make us read beyond
12292 * the end of the firmware data */
12293 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12294 offset = be32_to_cpu(sections[i].offset);
12295 len = be32_to_cpu(sections[i].len);
12296 if (offset + len > firmware->size) {
12297 BNX2X_ERR("Section %d length is out of bounds\n", i);
12302 /* Likewise for the init_ops offsets */
12303 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12304 ops_offsets = (__force __be16 *)(firmware->data + offset);
12305 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12307 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12308 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12309 BNX2X_ERR("Section offset %d is out of bounds\n", i);
12314 /* Check FW version */
12315 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12316 fw_ver = firmware->data + offset;
12317 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12318 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12319 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12320 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12321 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12322 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12323 BCM_5710_FW_MAJOR_VERSION,
12324 BCM_5710_FW_MINOR_VERSION,
12325 BCM_5710_FW_REVISION_VERSION,
12326 BCM_5710_FW_ENGINEERING_VERSION);
12333 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12335 const __be32 *source = (const __be32 *)_source;
12336 u32 *target = (u32 *)_target;
12339 for (i = 0; i < n/4; i++)
12340 target[i] = be32_to_cpu(source[i]);
12344 Ops array is stored in the following format:
12345 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12347 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12349 const __be32 *source = (const __be32 *)_source;
12350 struct raw_op *target = (struct raw_op *)_target;
12353 for (i = 0, j = 0; i < n/8; i++, j += 2) {
12354 tmp = be32_to_cpu(source[j]);
12355 target[i].op = (tmp >> 24) & 0xff;
12356 target[i].offset = tmp & 0xffffff;
12357 target[i].raw_data = be32_to_cpu(source[j + 1]);
12361 /* IRO array is stored in the following format:
12362 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12364 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12366 const __be32 *source = (const __be32 *)_source;
12367 struct iro *target = (struct iro *)_target;
12370 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12371 target[i].base = be32_to_cpu(source[j]);
12373 tmp = be32_to_cpu(source[j]);
12374 target[i].m1 = (tmp >> 16) & 0xffff;
12375 target[i].m2 = tmp & 0xffff;
12377 tmp = be32_to_cpu(source[j]);
12378 target[i].m3 = (tmp >> 16) & 0xffff;
12379 target[i].size = tmp & 0xffff;
12384 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12386 const __be16 *source = (const __be16 *)_source;
12387 u16 *target = (u16 *)_target;
12390 for (i = 0; i < n/2; i++)
12391 target[i] = be16_to_cpu(source[i]);
12394 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12396 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12397 bp->arr = kmalloc(len, GFP_KERNEL); \
12400 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12401 (u8 *)bp->arr, len); \
12404 static int bnx2x_init_firmware(struct bnx2x *bp)
12406 const char *fw_file_name;
12407 struct bnx2x_fw_file_hdr *fw_hdr;
12413 if (CHIP_IS_E1(bp))
12414 fw_file_name = FW_FILE_NAME_E1;
12415 else if (CHIP_IS_E1H(bp))
12416 fw_file_name = FW_FILE_NAME_E1H;
12417 else if (!CHIP_IS_E1x(bp))
12418 fw_file_name = FW_FILE_NAME_E2;
12420 BNX2X_ERR("Unsupported chip revision\n");
12423 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12425 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12427 BNX2X_ERR("Can't load firmware file %s\n",
12429 goto request_firmware_exit;
12432 rc = bnx2x_check_firmware(bp);
12434 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12435 goto request_firmware_exit;
12438 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12440 /* Initialize the pointers to the init arrays */
12442 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12445 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12448 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12451 /* STORMs firmware */
12452 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12453 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12454 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12455 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12456 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12457 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12458 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12459 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12460 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12461 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12462 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12463 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12464 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12465 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12466 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12467 be32_to_cpu(fw_hdr->csem_pram_data.offset);
12469 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12474 kfree(bp->init_ops_offsets);
12475 init_offsets_alloc_err:
12476 kfree(bp->init_ops);
12477 init_ops_alloc_err:
12478 kfree(bp->init_data);
12479 request_firmware_exit:
12480 release_firmware(bp->firmware);
12481 bp->firmware = NULL;
12486 static void bnx2x_release_firmware(struct bnx2x *bp)
12488 kfree(bp->init_ops_offsets);
12489 kfree(bp->init_ops);
12490 kfree(bp->init_data);
12491 release_firmware(bp->firmware);
12492 bp->firmware = NULL;
12495 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12496 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12497 .init_hw_cmn = bnx2x_init_hw_common,
12498 .init_hw_port = bnx2x_init_hw_port,
12499 .init_hw_func = bnx2x_init_hw_func,
12501 .reset_hw_cmn = bnx2x_reset_common,
12502 .reset_hw_port = bnx2x_reset_port,
12503 .reset_hw_func = bnx2x_reset_func,
12505 .gunzip_init = bnx2x_gunzip_init,
12506 .gunzip_end = bnx2x_gunzip_end,
12508 .init_fw = bnx2x_init_firmware,
12509 .release_fw = bnx2x_release_firmware,
12512 void bnx2x__init_func_obj(struct bnx2x *bp)
12514 /* Prepare DMAE related driver resources */
12515 bnx2x_setup_dmae(bp);
12517 bnx2x_init_func_obj(bp, &bp->func_obj,
12518 bnx2x_sp(bp, func_rdata),
12519 bnx2x_sp_mapping(bp, func_rdata),
12520 bnx2x_sp(bp, func_afex_rdata),
12521 bnx2x_sp_mapping(bp, func_afex_rdata),
12522 &bnx2x_func_sp_drv);
12525 /* must be called after sriov-enable */
12526 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12528 int cid_count = BNX2X_L2_MAX_CID(bp);
12531 cid_count += BNX2X_VF_CIDS;
12533 if (CNIC_SUPPORT(bp))
12534 cid_count += CNIC_CID_MAX;
12536 return roundup(cid_count, QM_CID_ROUND);
12540 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12545 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12546 int cnic_cnt, bool is_vf)
12551 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12554 * If MSI-X is not supported - return number of SBs needed to support
12555 * one fast path queue: one FP queue + SB for CNIC
12558 dev_info(&pdev->dev, "no msix capability found\n");
12559 return 1 + cnic_cnt;
12561 dev_info(&pdev->dev, "msix capability found\n");
12564 * The value in the PCI configuration space is the index of the last
12565 * entry, namely one less than the actual size of the table, which is
12566 * exactly what we want to return from this function: number of all SBs
12567 * without the default SB.
12568 * For VFs there is no default SB, then we return (index+1).
12570 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
12572 index = control & PCI_MSIX_FLAGS_QSIZE;
12574 return is_vf ? index + 1 : index;
12577 static int set_max_cos_est(int chip_id)
12583 return BNX2X_MULTI_TX_COS_E1X;
12587 return BNX2X_MULTI_TX_COS_E2_E3A0;
12593 case BCM57840_4_10:
12594 case BCM57840_2_20:
12603 return BNX2X_MULTI_TX_COS_E3B0;
12606 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12611 static int set_is_vf(int chip_id)
12625 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12627 static int bnx2x_init_one(struct pci_dev *pdev,
12628 const struct pci_device_id *ent)
12630 struct net_device *dev = NULL;
12633 enum bnx2x_pci_bus_speed pcie_speed;
12634 int rc, max_non_def_sbs;
12635 int rx_count, tx_count, rss_count, doorbell_size;
12640 /* An estimated maximum supported CoS number according to the chip
12642 * We will try to roughly estimate the maximum number of CoSes this chip
12643 * may support in order to minimize the memory allocated for Tx
12644 * netdev_queue's. This number will be accurately calculated during the
12645 * initialization of bp->max_cos based on the chip versions AND chip
12646 * revision in the bnx2x_init_bp().
12648 max_cos_est = set_max_cos_est(ent->driver_data);
12649 if (max_cos_est < 0)
12650 return max_cos_est;
12651 is_vf = set_is_vf(ent->driver_data);
12652 cnic_cnt = is_vf ? 0 : 1;
12654 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12656 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12657 rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12662 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12663 rx_count = rss_count + cnic_cnt;
12665 /* Maximum number of netdev Tx queues:
12666 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
12668 tx_count = rss_count * max_cos_est + cnic_cnt;
12670 /* dev zeroed in init_etherdev */
12671 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12675 bp = netdev_priv(dev);
12679 bp->flags |= IS_VF_FLAG;
12681 bp->igu_sb_cnt = max_non_def_sbs;
12682 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12683 bp->msg_enable = debug;
12684 bp->cnic_support = cnic_cnt;
12685 bp->cnic_probe = bnx2x_cnic_probe;
12687 pci_set_drvdata(pdev, dev);
12689 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12695 BNX2X_DEV_INFO("This is a %s function\n",
12696 IS_PF(bp) ? "physical" : "virtual");
12697 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12698 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12699 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12700 tx_count, rx_count);
12702 rc = bnx2x_init_bp(bp);
12704 goto init_one_exit;
12706 /* Map doorbells here as we need the real value of bp->max_cos which
12707 * is initialized in bnx2x_init_bp() to determine the number of
12711 bp->doorbells = bnx2x_vf_doorbells(bp);
12712 rc = bnx2x_vf_pci_alloc(bp);
12714 goto init_one_exit;
12716 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12717 if (doorbell_size > pci_resource_len(pdev, 2)) {
12718 dev_err(&bp->pdev->dev,
12719 "Cannot map doorbells, bar size too small, aborting\n");
12721 goto init_one_exit;
12723 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12726 if (!bp->doorbells) {
12727 dev_err(&bp->pdev->dev,
12728 "Cannot map doorbell space, aborting\n");
12730 goto init_one_exit;
12734 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12736 goto init_one_exit;
12739 /* Enable SRIOV if capability found in configuration space */
12740 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12742 goto init_one_exit;
12744 /* calc qm_cid_count */
12745 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12746 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12748 /* disable FCOE L2 queue for E1x*/
12749 if (CHIP_IS_E1x(bp))
12750 bp->flags |= NO_FCOE_FLAG;
12752 /* Set bp->num_queues for MSI-X mode*/
12753 bnx2x_set_num_queues(bp);
12755 /* Configure interrupt mode: try to enable MSI-X/MSI if
12758 rc = bnx2x_set_int_mode(bp);
12760 dev_err(&pdev->dev, "Cannot set interrupts\n");
12761 goto init_one_exit;
12763 BNX2X_DEV_INFO("set interrupts successfully\n");
12765 /* register the net device */
12766 rc = register_netdev(dev);
12768 dev_err(&pdev->dev, "Cannot register net device\n");
12769 goto init_one_exit;
12771 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12773 if (!NO_FCOE(bp)) {
12774 /* Add storage MAC address */
12776 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12780 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12781 BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12782 pcie_width, pcie_speed);
12784 BNX2X_DEV_INFO("%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12785 board_info[ent->driver_data].name,
12786 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12788 pcie_speed == BNX2X_PCI_LINK_SPEED_2500 ? "2.5GHz" :
12789 pcie_speed == BNX2X_PCI_LINK_SPEED_5000 ? "5.0GHz" :
12790 pcie_speed == BNX2X_PCI_LINK_SPEED_8000 ? "8.0GHz" :
12792 dev->base_addr, bp->pdev->irq, dev->dev_addr);
12798 iounmap(bp->regview);
12800 if (IS_PF(bp) && bp->doorbells)
12801 iounmap(bp->doorbells);
12805 if (atomic_read(&pdev->enable_cnt) == 1)
12806 pci_release_regions(pdev);
12808 pci_disable_device(pdev);
12809 pci_set_drvdata(pdev, NULL);
12814 static void __bnx2x_remove(struct pci_dev *pdev,
12815 struct net_device *dev,
12817 bool remove_netdev)
12819 /* Delete storage MAC address */
12820 if (!NO_FCOE(bp)) {
12822 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12827 /* Delete app tlvs from dcbnl */
12828 bnx2x_dcbnl_update_applist(bp, true);
12833 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
12834 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
12836 /* Close the interface - either directly or implicitly */
12837 if (remove_netdev) {
12838 unregister_netdev(dev);
12845 bnx2x_iov_remove_one(bp);
12847 /* Power on: we can't let PCI layer write to us while we are in D3 */
12849 bnx2x_set_power_state(bp, PCI_D0);
12851 /* Disable MSI/MSI-X */
12852 bnx2x_disable_msi(bp);
12856 bnx2x_set_power_state(bp, PCI_D3hot);
12858 /* Make sure RESET task is not scheduled before continuing */
12859 cancel_delayed_work_sync(&bp->sp_rtnl_task);
12861 /* send message via vfpf channel to release the resources of this vf */
12863 bnx2x_vfpf_release(bp);
12865 /* Assumes no further PCIe PM changes will occur */
12866 if (system_state == SYSTEM_POWER_OFF) {
12867 pci_wake_from_d3(pdev, bp->wol);
12868 pci_set_power_state(pdev, PCI_D3hot);
12872 iounmap(bp->regview);
12874 /* for vf doorbells are part of the regview and were unmapped along with
12875 * it. FW is only loaded by PF.
12879 iounmap(bp->doorbells);
12881 bnx2x_release_firmware(bp);
12883 bnx2x_free_mem_bp(bp);
12888 if (atomic_read(&pdev->enable_cnt) == 1)
12889 pci_release_regions(pdev);
12891 pci_disable_device(pdev);
12892 pci_set_drvdata(pdev, NULL);
12895 static void bnx2x_remove_one(struct pci_dev *pdev)
12897 struct net_device *dev = pci_get_drvdata(pdev);
12901 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12904 bp = netdev_priv(dev);
12906 __bnx2x_remove(pdev, dev, bp, true);
12909 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12911 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
12913 bp->rx_mode = BNX2X_RX_MODE_NONE;
12915 if (CNIC_LOADED(bp))
12916 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12919 bnx2x_tx_disable(bp);
12920 /* Delete all NAPI objects */
12921 bnx2x_del_all_napi(bp);
12922 if (CNIC_LOADED(bp))
12923 bnx2x_del_all_napi_cnic(bp);
12924 netdev_reset_tc(bp->dev);
12926 del_timer_sync(&bp->timer);
12927 cancel_delayed_work(&bp->sp_task);
12928 cancel_delayed_work(&bp->period_task);
12930 spin_lock_bh(&bp->stats_lock);
12931 bp->stats_state = STATS_STATE_DISABLED;
12932 spin_unlock_bh(&bp->stats_lock);
12934 bnx2x_save_statistics(bp);
12936 netif_carrier_off(bp->dev);
12942 * bnx2x_io_error_detected - called when PCI error is detected
12943 * @pdev: Pointer to PCI device
12944 * @state: The current pci connection state
12946 * This function is called after a PCI bus error affecting
12947 * this device has been detected.
12949 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12950 pci_channel_state_t state)
12952 struct net_device *dev = pci_get_drvdata(pdev);
12953 struct bnx2x *bp = netdev_priv(dev);
12957 BNX2X_ERR("IO error detected\n");
12959 netif_device_detach(dev);
12961 if (state == pci_channel_io_perm_failure) {
12963 return PCI_ERS_RESULT_DISCONNECT;
12966 if (netif_running(dev))
12967 bnx2x_eeh_nic_unload(bp);
12969 bnx2x_prev_path_mark_eeh(bp);
12971 pci_disable_device(pdev);
12975 /* Request a slot reset */
12976 return PCI_ERS_RESULT_NEED_RESET;
12980 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12981 * @pdev: Pointer to PCI device
12983 * Restart the card from scratch, as if from a cold-boot.
12985 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12987 struct net_device *dev = pci_get_drvdata(pdev);
12988 struct bnx2x *bp = netdev_priv(dev);
12992 BNX2X_ERR("IO slot reset initializing...\n");
12993 if (pci_enable_device(pdev)) {
12994 dev_err(&pdev->dev,
12995 "Cannot re-enable PCI device after reset\n");
12997 return PCI_ERS_RESULT_DISCONNECT;
13000 pci_set_master(pdev);
13001 pci_restore_state(pdev);
13002 pci_save_state(pdev);
13004 if (netif_running(dev))
13005 bnx2x_set_power_state(bp, PCI_D0);
13007 if (netif_running(dev)) {
13008 BNX2X_ERR("IO slot reset --> driver unload\n");
13010 /* MCP should have been reset; Need to wait for validity */
13011 bnx2x_init_shmem(bp);
13013 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13017 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13018 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13019 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13021 bnx2x_drain_tx_queues(bp);
13022 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13023 bnx2x_netif_stop(bp, 1);
13024 bnx2x_free_irq(bp);
13026 /* Report UNLOAD_DONE to MCP */
13027 bnx2x_send_unload_done(bp, true);
13032 bnx2x_prev_unload(bp);
13034 /* We should have reseted the engine, so It's fair to
13035 * assume the FW will no longer write to the bnx2x driver.
13037 bnx2x_squeeze_objects(bp);
13038 bnx2x_free_skbs(bp);
13039 for_each_rx_queue(bp, i)
13040 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13041 bnx2x_free_fp_mem(bp);
13042 bnx2x_free_mem(bp);
13044 bp->state = BNX2X_STATE_CLOSED;
13049 return PCI_ERS_RESULT_RECOVERED;
13053 * bnx2x_io_resume - called when traffic can start flowing again
13054 * @pdev: Pointer to PCI device
13056 * This callback is called when the error recovery driver tells us that
13057 * its OK to resume normal operation.
13059 static void bnx2x_io_resume(struct pci_dev *pdev)
13061 struct net_device *dev = pci_get_drvdata(pdev);
13062 struct bnx2x *bp = netdev_priv(dev);
13064 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13065 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13071 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13072 DRV_MSG_SEQ_NUMBER_MASK;
13074 if (netif_running(dev))
13075 bnx2x_nic_load(bp, LOAD_NORMAL);
13077 netif_device_attach(dev);
13082 static const struct pci_error_handlers bnx2x_err_handler = {
13083 .error_detected = bnx2x_io_error_detected,
13084 .slot_reset = bnx2x_io_slot_reset,
13085 .resume = bnx2x_io_resume,
13088 static void bnx2x_shutdown(struct pci_dev *pdev)
13090 struct net_device *dev = pci_get_drvdata(pdev);
13096 bp = netdev_priv(dev);
13101 netif_device_detach(dev);
13104 /* Don't remove the netdevice, as there are scenarios which will cause
13105 * the kernel to hang, e.g., when trying to remove bnx2i while the
13106 * rootfs is mounted from SAN.
13108 __bnx2x_remove(pdev, dev, bp, false);
13111 static struct pci_driver bnx2x_pci_driver = {
13112 .name = DRV_MODULE_NAME,
13113 .id_table = bnx2x_pci_tbl,
13114 .probe = bnx2x_init_one,
13115 .remove = bnx2x_remove_one,
13116 .suspend = bnx2x_suspend,
13117 .resume = bnx2x_resume,
13118 .err_handler = &bnx2x_err_handler,
13119 #ifdef CONFIG_BNX2X_SRIOV
13120 .sriov_configure = bnx2x_sriov_configure,
13122 .shutdown = bnx2x_shutdown,
13125 static int __init bnx2x_init(void)
13129 pr_info("%s", version);
13131 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13132 if (bnx2x_wq == NULL) {
13133 pr_err("Cannot create workqueue\n");
13137 ret = pci_register_driver(&bnx2x_pci_driver);
13139 pr_err("Cannot register driver\n");
13140 destroy_workqueue(bnx2x_wq);
13145 static void __exit bnx2x_cleanup(void)
13147 struct list_head *pos, *q;
13149 pci_unregister_driver(&bnx2x_pci_driver);
13151 destroy_workqueue(bnx2x_wq);
13153 /* Free globally allocated resources */
13154 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13155 struct bnx2x_prev_path_list *tmp =
13156 list_entry(pos, struct bnx2x_prev_path_list, list);
13162 void bnx2x_notify_link_changed(struct bnx2x *bp)
13164 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13167 module_init(bnx2x_init);
13168 module_exit(bnx2x_cleanup);
13171 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13173 * @bp: driver handle
13174 * @set: set or clear the CAM entry
13176 * This function will wait until the ramrod completion returns.
13177 * Return 0 if success, -ENODEV if ramrod doesn't return.
13179 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13181 unsigned long ramrod_flags = 0;
13183 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13184 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13185 &bp->iscsi_l2_mac_obj, true,
13186 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13189 /* count denotes the number of new completions we have seen */
13190 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13192 struct eth_spe *spe;
13193 int cxt_index, cxt_offset;
13195 #ifdef BNX2X_STOP_ON_ERROR
13196 if (unlikely(bp->panic))
13200 spin_lock_bh(&bp->spq_lock);
13201 BUG_ON(bp->cnic_spq_pending < count);
13202 bp->cnic_spq_pending -= count;
13204 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13205 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13206 & SPE_HDR_CONN_TYPE) >>
13207 SPE_HDR_CONN_TYPE_SHIFT;
13208 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13209 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13211 /* Set validation for iSCSI L2 client before sending SETUP
13214 if (type == ETH_CONNECTION_TYPE) {
13215 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13216 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13218 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13219 (cxt_index * ILT_PAGE_CIDS);
13220 bnx2x_set_ctx_validation(bp,
13221 &bp->context[cxt_index].
13222 vcxt[cxt_offset].eth,
13223 BNX2X_ISCSI_ETH_CID(bp));
13228 * There may be not more than 8 L2, not more than 8 L5 SPEs
13229 * and in the air. We also check that number of outstanding
13230 * COMMON ramrods is not more than the EQ and SPQ can
13233 if (type == ETH_CONNECTION_TYPE) {
13234 if (!atomic_read(&bp->cq_spq_left))
13237 atomic_dec(&bp->cq_spq_left);
13238 } else if (type == NONE_CONNECTION_TYPE) {
13239 if (!atomic_read(&bp->eq_spq_left))
13242 atomic_dec(&bp->eq_spq_left);
13243 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13244 (type == FCOE_CONNECTION_TYPE)) {
13245 if (bp->cnic_spq_pending >=
13246 bp->cnic_eth_dev.max_kwqe_pending)
13249 bp->cnic_spq_pending++;
13251 BNX2X_ERR("Unknown SPE type: %d\n", type);
13256 spe = bnx2x_sp_get_next(bp);
13257 *spe = *bp->cnic_kwq_cons;
13259 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13260 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13262 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13263 bp->cnic_kwq_cons = bp->cnic_kwq;
13265 bp->cnic_kwq_cons++;
13267 bnx2x_sp_prod_update(bp);
13268 spin_unlock_bh(&bp->spq_lock);
13271 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13272 struct kwqe_16 *kwqes[], u32 count)
13274 struct bnx2x *bp = netdev_priv(dev);
13277 #ifdef BNX2X_STOP_ON_ERROR
13278 if (unlikely(bp->panic)) {
13279 BNX2X_ERR("Can't post to SP queue while panic\n");
13284 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13285 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13286 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13290 spin_lock_bh(&bp->spq_lock);
13292 for (i = 0; i < count; i++) {
13293 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13295 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13298 *bp->cnic_kwq_prod = *spe;
13300 bp->cnic_kwq_pending++;
13302 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13303 spe->hdr.conn_and_cmd_data, spe->hdr.type,
13304 spe->data.update_data_addr.hi,
13305 spe->data.update_data_addr.lo,
13306 bp->cnic_kwq_pending);
13308 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13309 bp->cnic_kwq_prod = bp->cnic_kwq;
13311 bp->cnic_kwq_prod++;
13314 spin_unlock_bh(&bp->spq_lock);
13316 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13317 bnx2x_cnic_sp_post(bp, 0);
13322 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13324 struct cnic_ops *c_ops;
13327 mutex_lock(&bp->cnic_mutex);
13328 c_ops = rcu_dereference_protected(bp->cnic_ops,
13329 lockdep_is_held(&bp->cnic_mutex));
13331 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13332 mutex_unlock(&bp->cnic_mutex);
13337 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13339 struct cnic_ops *c_ops;
13343 c_ops = rcu_dereference(bp->cnic_ops);
13345 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13352 * for commands that have no data
13354 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13356 struct cnic_ctl_info ctl = {0};
13360 return bnx2x_cnic_ctl_send(bp, &ctl);
13363 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13365 struct cnic_ctl_info ctl = {0};
13367 /* first we tell CNIC and only then we count this as a completion */
13368 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13369 ctl.data.comp.cid = cid;
13370 ctl.data.comp.error = err;
13372 bnx2x_cnic_ctl_send_bh(bp, &ctl);
13373 bnx2x_cnic_sp_post(bp, 0);
13376 /* Called with netif_addr_lock_bh() taken.
13377 * Sets an rx_mode config for an iSCSI ETH client.
13379 * Completion should be checked outside.
13381 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13383 unsigned long accept_flags = 0, ramrod_flags = 0;
13384 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13385 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13388 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13389 * because it's the only way for UIO Queue to accept
13390 * multicasts (in non-promiscuous mode only one Queue per
13391 * function will receive multicast packets (leading in our
13394 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13395 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13396 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13397 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13399 /* Clear STOP_PENDING bit if START is requested */
13400 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13402 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13404 /* Clear START_PENDING bit if STOP is requested */
13405 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13407 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13408 set_bit(sched_state, &bp->sp_state);
13410 __set_bit(RAMROD_RX, &ramrod_flags);
13411 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13416 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13418 struct bnx2x *bp = netdev_priv(dev);
13421 switch (ctl->cmd) {
13422 case DRV_CTL_CTXTBL_WR_CMD: {
13423 u32 index = ctl->data.io.offset;
13424 dma_addr_t addr = ctl->data.io.dma_addr;
13426 bnx2x_ilt_wr(bp, index, addr);
13430 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13431 int count = ctl->data.credit.credit_count;
13433 bnx2x_cnic_sp_post(bp, count);
13437 /* rtnl_lock is held. */
13438 case DRV_CTL_START_L2_CMD: {
13439 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13440 unsigned long sp_bits = 0;
13442 /* Configure the iSCSI classification object */
13443 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13444 cp->iscsi_l2_client_id,
13445 cp->iscsi_l2_cid, BP_FUNC(bp),
13446 bnx2x_sp(bp, mac_rdata),
13447 bnx2x_sp_mapping(bp, mac_rdata),
13448 BNX2X_FILTER_MAC_PENDING,
13449 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13452 /* Set iSCSI MAC address */
13453 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13460 /* Start accepting on iSCSI L2 ring */
13462 netif_addr_lock_bh(dev);
13463 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13464 netif_addr_unlock_bh(dev);
13466 /* bits to wait on */
13467 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13468 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13470 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13471 BNX2X_ERR("rx_mode completion timed out!\n");
13476 /* rtnl_lock is held. */
13477 case DRV_CTL_STOP_L2_CMD: {
13478 unsigned long sp_bits = 0;
13480 /* Stop accepting on iSCSI L2 ring */
13481 netif_addr_lock_bh(dev);
13482 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13483 netif_addr_unlock_bh(dev);
13485 /* bits to wait on */
13486 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13487 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13489 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13490 BNX2X_ERR("rx_mode completion timed out!\n");
13495 /* Unset iSCSI L2 MAC */
13496 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13497 BNX2X_ISCSI_ETH_MAC, true);
13500 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13501 int count = ctl->data.credit.credit_count;
13503 smp_mb__before_atomic_inc();
13504 atomic_add(count, &bp->cq_spq_left);
13505 smp_mb__after_atomic_inc();
13508 case DRV_CTL_ULP_REGISTER_CMD: {
13509 int ulp_type = ctl->data.register_data.ulp_type;
13511 if (CHIP_IS_E3(bp)) {
13512 int idx = BP_FW_MB_IDX(bp);
13513 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13514 int path = BP_PATH(bp);
13515 int port = BP_PORT(bp);
13517 u32 scratch_offset;
13520 /* first write capability to shmem2 */
13521 if (ulp_type == CNIC_ULP_ISCSI)
13522 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13523 else if (ulp_type == CNIC_ULP_FCOE)
13524 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13525 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13527 if ((ulp_type != CNIC_ULP_FCOE) ||
13528 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13529 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13532 /* if reached here - should write fcoe capabilities */
13533 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13534 if (!scratch_offset)
13536 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13537 fcoe_features[path][port]);
13538 host_addr = (u32 *) &(ctl->data.register_data.
13540 for (i = 0; i < sizeof(struct fcoe_capabilities);
13542 REG_WR(bp, scratch_offset + i,
13543 *(host_addr + i/4));
13548 case DRV_CTL_ULP_UNREGISTER_CMD: {
13549 int ulp_type = ctl->data.ulp_type;
13551 if (CHIP_IS_E3(bp)) {
13552 int idx = BP_FW_MB_IDX(bp);
13555 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13556 if (ulp_type == CNIC_ULP_ISCSI)
13557 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13558 else if (ulp_type == CNIC_ULP_FCOE)
13559 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13560 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13566 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13573 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13575 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13577 if (bp->flags & USING_MSIX_FLAG) {
13578 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13579 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13580 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13582 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13583 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13585 if (!CHIP_IS_E1x(bp))
13586 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13588 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13590 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13591 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13592 cp->irq_arr[1].status_blk = bp->def_status_blk;
13593 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13594 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13599 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13601 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13603 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13604 bnx2x_cid_ilt_lines(bp);
13605 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13606 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13607 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13609 if (NO_ISCSI_OOO(bp))
13610 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13613 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13616 struct bnx2x *bp = netdev_priv(dev);
13617 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13620 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13623 BNX2X_ERR("NULL ops received\n");
13627 if (!CNIC_SUPPORT(bp)) {
13628 BNX2X_ERR("Can't register CNIC when not supported\n");
13629 return -EOPNOTSUPP;
13632 if (!CNIC_LOADED(bp)) {
13633 rc = bnx2x_load_cnic(bp);
13635 BNX2X_ERR("CNIC-related load failed\n");
13640 bp->cnic_enabled = true;
13642 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13646 bp->cnic_kwq_cons = bp->cnic_kwq;
13647 bp->cnic_kwq_prod = bp->cnic_kwq;
13648 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13650 bp->cnic_spq_pending = 0;
13651 bp->cnic_kwq_pending = 0;
13653 bp->cnic_data = data;
13656 cp->drv_state |= CNIC_DRV_STATE_REGD;
13657 cp->iro_arr = bp->iro_arr;
13659 bnx2x_setup_cnic_irq_info(bp);
13661 rcu_assign_pointer(bp->cnic_ops, ops);
13666 static int bnx2x_unregister_cnic(struct net_device *dev)
13668 struct bnx2x *bp = netdev_priv(dev);
13669 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13671 mutex_lock(&bp->cnic_mutex);
13673 RCU_INIT_POINTER(bp->cnic_ops, NULL);
13674 mutex_unlock(&bp->cnic_mutex);
13676 bp->cnic_enabled = false;
13677 kfree(bp->cnic_kwq);
13678 bp->cnic_kwq = NULL;
13683 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13685 struct bnx2x *bp = netdev_priv(dev);
13686 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13688 /* If both iSCSI and FCoE are disabled - return NULL in
13689 * order to indicate CNIC that it should not try to work
13690 * with this device.
13692 if (NO_ISCSI(bp) && NO_FCOE(bp))
13695 cp->drv_owner = THIS_MODULE;
13696 cp->chip_id = CHIP_ID(bp);
13697 cp->pdev = bp->pdev;
13698 cp->io_base = bp->regview;
13699 cp->io_base2 = bp->doorbells;
13700 cp->max_kwqe_pending = 8;
13701 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13702 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13703 bnx2x_cid_ilt_lines(bp);
13704 cp->ctx_tbl_len = CNIC_ILT_LINES;
13705 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13706 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13707 cp->drv_ctl = bnx2x_drv_ctl;
13708 cp->drv_register_cnic = bnx2x_register_cnic;
13709 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13710 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13711 cp->iscsi_l2_client_id =
13712 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13713 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13715 if (NO_ISCSI_OOO(bp))
13716 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13719 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13722 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13725 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13727 cp->ctx_tbl_offset,
13733 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13735 struct bnx2x *bp = fp->bp;
13736 u32 offset = BAR_USTRORM_INTMEM;
13739 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13740 else if (!CHIP_IS_E1x(bp))
13741 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13743 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13748 /* called only on E1H or E2.
13749 * When pretending to be PF, the pretend value is the function number 0...7
13750 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13753 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13757 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13760 /* get my own pretend register */
13761 pretend_reg = bnx2x_get_pretend_reg(bp);
13762 REG_WR(bp, pretend_reg, pretend_func_val);
13763 REG_RD(bp, pretend_reg);