1 /* bnx2x_sp.c: Broadcom Everest network driver.
3 * Copyright (c) 2011-2013 Broadcom Corporation
5 * Unless you and Broadcom execute a separate written software license
6 * agreement governing use of this software, this software is licensed to you
7 * under the terms of the GNU General Public License version 2, available
8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
10 * Notwithstanding the above, under no circumstances may you combine this
11 * software in any way with any other Broadcom software provided under a
12 * license other than the GPL, without Broadcom's express prior written
15 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
16 * Written by: Vladislav Zolotarov
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/module.h>
23 #include <linux/crc32.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/crc32c.h>
28 #include "bnx2x_cmn.h"
31 #define BNX2X_MAX_EMUL_MULTI 16
33 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
35 /**** Exe Queue interfaces ****/
38 * bnx2x_exe_queue_init - init the Exe Queue object
40 * @o: poiter to the object
42 * @owner: poiter to the owner
43 * @validate: validate function pointer
44 * @optimize: optimize function pointer
45 * @exec: execute function pointer
46 * @get: get function pointer
48 static inline void bnx2x_exe_queue_init(struct bnx2x *bp,
49 struct bnx2x_exe_queue_obj *o,
51 union bnx2x_qable_obj *owner,
52 exe_q_validate validate,
54 exe_q_optimize optimize,
58 memset(o, 0, sizeof(*o));
60 INIT_LIST_HEAD(&o->exe_queue);
61 INIT_LIST_HEAD(&o->pending_comp);
63 spin_lock_init(&o->lock);
65 o->exe_chunk_len = exe_len;
68 /* Owner specific callbacks */
69 o->validate = validate;
71 o->optimize = optimize;
75 DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n",
79 static inline void bnx2x_exe_queue_free_elem(struct bnx2x *bp,
80 struct bnx2x_exeq_elem *elem)
82 DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n");
86 static inline int bnx2x_exe_queue_length(struct bnx2x_exe_queue_obj *o)
88 struct bnx2x_exeq_elem *elem;
91 spin_lock_bh(&o->lock);
93 list_for_each_entry(elem, &o->exe_queue, link)
96 spin_unlock_bh(&o->lock);
102 * bnx2x_exe_queue_add - add a new element to the execution queue
106 * @cmd: new command to add
107 * @restore: true - do not optimize the command
109 * If the element is optimized or is illegal, frees it.
111 static inline int bnx2x_exe_queue_add(struct bnx2x *bp,
112 struct bnx2x_exe_queue_obj *o,
113 struct bnx2x_exeq_elem *elem,
118 spin_lock_bh(&o->lock);
121 /* Try to cancel this element queue */
122 rc = o->optimize(bp, o->owner, elem);
126 /* Check if this request is ok */
127 rc = o->validate(bp, o->owner, elem);
129 DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc);
134 /* If so, add it to the execution queue */
135 list_add_tail(&elem->link, &o->exe_queue);
137 spin_unlock_bh(&o->lock);
142 bnx2x_exe_queue_free_elem(bp, elem);
144 spin_unlock_bh(&o->lock);
150 static inline void __bnx2x_exe_queue_reset_pending(
152 struct bnx2x_exe_queue_obj *o)
154 struct bnx2x_exeq_elem *elem;
156 while (!list_empty(&o->pending_comp)) {
157 elem = list_first_entry(&o->pending_comp,
158 struct bnx2x_exeq_elem, link);
160 list_del(&elem->link);
161 bnx2x_exe_queue_free_elem(bp, elem);
165 static inline void bnx2x_exe_queue_reset_pending(struct bnx2x *bp,
166 struct bnx2x_exe_queue_obj *o)
169 spin_lock_bh(&o->lock);
171 __bnx2x_exe_queue_reset_pending(bp, o);
173 spin_unlock_bh(&o->lock);
178 * bnx2x_exe_queue_step - execute one execution chunk atomically
182 * @ramrod_flags: flags
184 * (Atomicy is ensured using the exe_queue->lock).
186 static inline int bnx2x_exe_queue_step(struct bnx2x *bp,
187 struct bnx2x_exe_queue_obj *o,
188 unsigned long *ramrod_flags)
190 struct bnx2x_exeq_elem *elem, spacer;
193 memset(&spacer, 0, sizeof(spacer));
195 spin_lock_bh(&o->lock);
198 * Next step should not be performed until the current is finished,
199 * unless a DRV_CLEAR_ONLY bit is set. In this case we just want to
200 * properly clear object internals without sending any command to the FW
201 * which also implies there won't be any completion to clear the
204 if (!list_empty(&o->pending_comp)) {
205 if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {
206 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n");
207 __bnx2x_exe_queue_reset_pending(bp, o);
209 spin_unlock_bh(&o->lock);
215 * Run through the pending commands list and create a next
218 while (!list_empty(&o->exe_queue)) {
219 elem = list_first_entry(&o->exe_queue, struct bnx2x_exeq_elem,
221 WARN_ON(!elem->cmd_len);
223 if (cur_len + elem->cmd_len <= o->exe_chunk_len) {
224 cur_len += elem->cmd_len;
226 * Prevent from both lists being empty when moving an
227 * element. This will allow the call of
228 * bnx2x_exe_queue_empty() without locking.
230 list_add_tail(&spacer.link, &o->pending_comp);
232 list_move_tail(&elem->link, &o->pending_comp);
233 list_del(&spacer.link);
240 spin_unlock_bh(&o->lock);
244 rc = o->execute(bp, o->owner, &o->pending_comp, ramrod_flags);
247 * In case of an error return the commands back to the queue
248 * and reset the pending_comp.
250 list_splice_init(&o->pending_comp, &o->exe_queue);
253 * If zero is returned, means there are no outstanding pending
254 * completions and we may dismiss the pending list.
256 __bnx2x_exe_queue_reset_pending(bp, o);
258 spin_unlock_bh(&o->lock);
262 static inline bool bnx2x_exe_queue_empty(struct bnx2x_exe_queue_obj *o)
264 bool empty = list_empty(&o->exe_queue);
266 /* Don't reorder!!! */
269 return empty && list_empty(&o->pending_comp);
272 static inline struct bnx2x_exeq_elem *bnx2x_exe_queue_alloc_elem(
275 DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n");
276 return kzalloc(sizeof(struct bnx2x_exeq_elem), GFP_ATOMIC);
279 /************************ raw_obj functions ***********************************/
280 static bool bnx2x_raw_check_pending(struct bnx2x_raw_obj *o)
282 return !!test_bit(o->state, o->pstate);
285 static void bnx2x_raw_clear_pending(struct bnx2x_raw_obj *o)
287 smp_mb__before_clear_bit();
288 clear_bit(o->state, o->pstate);
289 smp_mb__after_clear_bit();
292 static void bnx2x_raw_set_pending(struct bnx2x_raw_obj *o)
294 smp_mb__before_clear_bit();
295 set_bit(o->state, o->pstate);
296 smp_mb__after_clear_bit();
300 * bnx2x_state_wait - wait until the given bit(state) is cleared
303 * @state: state which is to be cleared
304 * @state_p: state buffer
307 static inline int bnx2x_state_wait(struct bnx2x *bp, int state,
308 unsigned long *pstate)
310 /* can take a while if any port is running */
314 if (CHIP_REV_IS_EMUL(bp))
317 DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state);
321 if (!test_bit(state, pstate)) {
322 #ifdef BNX2X_STOP_ON_ERROR
323 DP(BNX2X_MSG_SP, "exit (cnt %d)\n", 5000 - cnt);
328 usleep_range(1000, 2000);
335 BNX2X_ERR("timeout waiting for state %d\n", state);
336 #ifdef BNX2X_STOP_ON_ERROR
343 static int bnx2x_raw_wait(struct bnx2x *bp, struct bnx2x_raw_obj *raw)
345 return bnx2x_state_wait(bp, raw->state, raw->pstate);
348 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
349 /* credit handling callbacks */
350 static bool bnx2x_get_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int *offset)
352 struct bnx2x_credit_pool_obj *mp = o->macs_pool;
356 return mp->get_entry(mp, offset);
359 static bool bnx2x_get_credit_mac(struct bnx2x_vlan_mac_obj *o)
361 struct bnx2x_credit_pool_obj *mp = o->macs_pool;
365 return mp->get(mp, 1);
368 static bool bnx2x_get_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int *offset)
370 struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
374 return vp->get_entry(vp, offset);
377 static bool bnx2x_get_credit_vlan(struct bnx2x_vlan_mac_obj *o)
379 struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
383 return vp->get(vp, 1);
386 static bool bnx2x_get_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o)
388 struct bnx2x_credit_pool_obj *mp = o->macs_pool;
389 struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
394 if (!vp->get(vp, 1)) {
402 static bool bnx2x_put_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int offset)
404 struct bnx2x_credit_pool_obj *mp = o->macs_pool;
406 return mp->put_entry(mp, offset);
409 static bool bnx2x_put_credit_mac(struct bnx2x_vlan_mac_obj *o)
411 struct bnx2x_credit_pool_obj *mp = o->macs_pool;
413 return mp->put(mp, 1);
416 static bool bnx2x_put_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int offset)
418 struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
420 return vp->put_entry(vp, offset);
423 static bool bnx2x_put_credit_vlan(struct bnx2x_vlan_mac_obj *o)
425 struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
427 return vp->put(vp, 1);
430 static bool bnx2x_put_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o)
432 struct bnx2x_credit_pool_obj *mp = o->macs_pool;
433 struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
438 if (!vp->put(vp, 1)) {
446 static int bnx2x_get_n_elements(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
449 struct bnx2x_vlan_mac_registry_elem *pos;
454 list_for_each_entry(pos, &o->head, link) {
456 /* place leading zeroes in buffer */
457 memset(next, 0, MAC_LEADING_ZERO_CNT);
459 /* place mac after leading zeroes*/
460 memcpy(next + MAC_LEADING_ZERO_CNT, pos->u.mac.mac,
463 /* calculate address of next element and
467 next = buf + counter * ALIGN(ETH_ALEN, sizeof(u32));
469 DP(BNX2X_MSG_SP, "copied element number %d to address %p element was %pM\n",
470 counter, next, pos->u.mac.mac);
473 return counter * ETH_ALEN;
476 /* check_add() callbacks */
477 static int bnx2x_check_mac_add(struct bnx2x *bp,
478 struct bnx2x_vlan_mac_obj *o,
479 union bnx2x_classification_ramrod_data *data)
481 struct bnx2x_vlan_mac_registry_elem *pos;
483 DP(BNX2X_MSG_SP, "Checking MAC %pM for ADD command\n", data->mac.mac);
485 if (!is_valid_ether_addr(data->mac.mac))
488 /* Check if a requested MAC already exists */
489 list_for_each_entry(pos, &o->head, link)
490 if (!memcmp(data->mac.mac, pos->u.mac.mac, ETH_ALEN))
496 static int bnx2x_check_vlan_add(struct bnx2x *bp,
497 struct bnx2x_vlan_mac_obj *o,
498 union bnx2x_classification_ramrod_data *data)
500 struct bnx2x_vlan_mac_registry_elem *pos;
502 DP(BNX2X_MSG_SP, "Checking VLAN %d for ADD command\n", data->vlan.vlan);
504 list_for_each_entry(pos, &o->head, link)
505 if (data->vlan.vlan == pos->u.vlan.vlan)
511 static int bnx2x_check_vlan_mac_add(struct bnx2x *bp,
512 struct bnx2x_vlan_mac_obj *o,
513 union bnx2x_classification_ramrod_data *data)
515 struct bnx2x_vlan_mac_registry_elem *pos;
517 DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for ADD command\n",
518 data->vlan_mac.mac, data->vlan_mac.vlan);
520 list_for_each_entry(pos, &o->head, link)
521 if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) &&
522 (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac,
530 /* check_del() callbacks */
531 static struct bnx2x_vlan_mac_registry_elem *
532 bnx2x_check_mac_del(struct bnx2x *bp,
533 struct bnx2x_vlan_mac_obj *o,
534 union bnx2x_classification_ramrod_data *data)
536 struct bnx2x_vlan_mac_registry_elem *pos;
538 DP(BNX2X_MSG_SP, "Checking MAC %pM for DEL command\n", data->mac.mac);
540 list_for_each_entry(pos, &o->head, link)
541 if (!memcmp(data->mac.mac, pos->u.mac.mac, ETH_ALEN))
547 static struct bnx2x_vlan_mac_registry_elem *
548 bnx2x_check_vlan_del(struct bnx2x *bp,
549 struct bnx2x_vlan_mac_obj *o,
550 union bnx2x_classification_ramrod_data *data)
552 struct bnx2x_vlan_mac_registry_elem *pos;
554 DP(BNX2X_MSG_SP, "Checking VLAN %d for DEL command\n", data->vlan.vlan);
556 list_for_each_entry(pos, &o->head, link)
557 if (data->vlan.vlan == pos->u.vlan.vlan)
563 static struct bnx2x_vlan_mac_registry_elem *
564 bnx2x_check_vlan_mac_del(struct bnx2x *bp,
565 struct bnx2x_vlan_mac_obj *o,
566 union bnx2x_classification_ramrod_data *data)
568 struct bnx2x_vlan_mac_registry_elem *pos;
570 DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for DEL command\n",
571 data->vlan_mac.mac, data->vlan_mac.vlan);
573 list_for_each_entry(pos, &o->head, link)
574 if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) &&
575 (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac,
582 /* check_move() callback */
583 static bool bnx2x_check_move(struct bnx2x *bp,
584 struct bnx2x_vlan_mac_obj *src_o,
585 struct bnx2x_vlan_mac_obj *dst_o,
586 union bnx2x_classification_ramrod_data *data)
588 struct bnx2x_vlan_mac_registry_elem *pos;
591 /* Check if we can delete the requested configuration from the first
594 pos = src_o->check_del(bp, src_o, data);
596 /* check if configuration can be added */
597 rc = dst_o->check_add(bp, dst_o, data);
599 /* If this classification can not be added (is already set)
600 * or can't be deleted - return an error.
608 static bool bnx2x_check_move_always_err(
610 struct bnx2x_vlan_mac_obj *src_o,
611 struct bnx2x_vlan_mac_obj *dst_o,
612 union bnx2x_classification_ramrod_data *data)
618 static inline u8 bnx2x_vlan_mac_get_rx_tx_flag(struct bnx2x_vlan_mac_obj *o)
620 struct bnx2x_raw_obj *raw = &o->raw;
623 if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) ||
624 (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
625 rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_TX_CMD;
627 if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) ||
628 (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
629 rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_RX_CMD;
635 void bnx2x_set_mac_in_nig(struct bnx2x *bp,
636 bool add, unsigned char *dev_addr, int index)
639 u32 reg_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
640 NIG_REG_LLH0_FUNC_MEM;
642 if (!IS_MF_SI(bp) && !IS_MF_AFEX(bp))
645 if (index > BNX2X_LLH_CAM_MAX_PF_LINE)
648 DP(BNX2X_MSG_SP, "Going to %s LLH configuration at entry %d\n",
649 (add ? "ADD" : "DELETE"), index);
652 /* LLH_FUNC_MEM is a u64 WB register */
653 reg_offset += 8*index;
655 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
656 (dev_addr[4] << 8) | dev_addr[5]);
657 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
659 REG_WR_DMAE(bp, reg_offset, wb_data, 2);
662 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
663 NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4*index, add);
667 * bnx2x_vlan_mac_set_cmd_hdr_e2 - set a header in a single classify ramrod
670 * @o: queue for which we want to configure this rule
671 * @add: if true the command is an ADD command, DEL otherwise
672 * @opcode: CLASSIFY_RULE_OPCODE_XXX
673 * @hdr: pointer to a header to setup
676 static inline void bnx2x_vlan_mac_set_cmd_hdr_e2(struct bnx2x *bp,
677 struct bnx2x_vlan_mac_obj *o, bool add, int opcode,
678 struct eth_classify_cmd_header *hdr)
680 struct bnx2x_raw_obj *raw = &o->raw;
682 hdr->client_id = raw->cl_id;
683 hdr->func_id = raw->func_id;
685 /* Rx or/and Tx (internal switching) configuration ? */
686 hdr->cmd_general_data |=
687 bnx2x_vlan_mac_get_rx_tx_flag(o);
690 hdr->cmd_general_data |= ETH_CLASSIFY_CMD_HEADER_IS_ADD;
692 hdr->cmd_general_data |=
693 (opcode << ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT);
697 * bnx2x_vlan_mac_set_rdata_hdr_e2 - set the classify ramrod data header
699 * @cid: connection id
700 * @type: BNX2X_FILTER_XXX_PENDING
701 * @hdr: poiter to header to setup
704 * currently we always configure one rule and echo field to contain a CID and an
707 static inline void bnx2x_vlan_mac_set_rdata_hdr_e2(u32 cid, int type,
708 struct eth_classify_header *hdr, int rule_cnt)
710 hdr->echo = cpu_to_le32((cid & BNX2X_SWCID_MASK) |
711 (type << BNX2X_SWCID_SHIFT));
712 hdr->rule_cnt = (u8)rule_cnt;
716 /* hw_config() callbacks */
717 static void bnx2x_set_one_mac_e2(struct bnx2x *bp,
718 struct bnx2x_vlan_mac_obj *o,
719 struct bnx2x_exeq_elem *elem, int rule_idx,
722 struct bnx2x_raw_obj *raw = &o->raw;
723 struct eth_classify_rules_ramrod_data *data =
724 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
725 int rule_cnt = rule_idx + 1, cmd = elem->cmd_data.vlan_mac.cmd;
726 union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
727 bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false;
728 unsigned long *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags;
729 u8 *mac = elem->cmd_data.vlan_mac.u.mac.mac;
732 * Set LLH CAM entry: currently only iSCSI and ETH macs are
733 * relevant. In addition, current implementation is tuned for a
736 * When multiple unicast ETH MACs PF configuration in switch
737 * independent mode is required (NetQ, multiple netdev MACs,
738 * etc.), consider better utilisation of 8 per function MAC
739 * entries in the LLH register. There is also
740 * NIG_REG_P[01]_LLH_FUNC_MEM2 registers that complete the
741 * total number of CAM entries to 16.
743 * Currently we won't configure NIG for MACs other than a primary ETH
744 * MAC and iSCSI L2 MAC.
746 * If this MAC is moving from one Queue to another, no need to change
749 if (cmd != BNX2X_VLAN_MAC_MOVE) {
750 if (test_bit(BNX2X_ISCSI_ETH_MAC, vlan_mac_flags))
751 bnx2x_set_mac_in_nig(bp, add, mac,
752 BNX2X_LLH_CAM_ISCSI_ETH_LINE);
753 else if (test_bit(BNX2X_ETH_MAC, vlan_mac_flags))
754 bnx2x_set_mac_in_nig(bp, add, mac,
755 BNX2X_LLH_CAM_ETH_LINE);
758 /* Reset the ramrod data buffer for the first rule */
760 memset(data, 0, sizeof(*data));
762 /* Setup a command header */
763 bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_MAC,
764 &rule_entry->mac.header);
766 DP(BNX2X_MSG_SP, "About to %s MAC %pM for Queue %d\n",
767 (add ? "add" : "delete"), mac, raw->cl_id);
769 /* Set a MAC itself */
770 bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb,
771 &rule_entry->mac.mac_mid,
772 &rule_entry->mac.mac_lsb, mac);
774 /* MOVE: Add a rule that will add this MAC to the target Queue */
775 if (cmd == BNX2X_VLAN_MAC_MOVE) {
779 /* Setup ramrod data */
780 bnx2x_vlan_mac_set_cmd_hdr_e2(bp,
781 elem->cmd_data.vlan_mac.target_obj,
782 true, CLASSIFY_RULE_OPCODE_MAC,
783 &rule_entry->mac.header);
785 /* Set a MAC itself */
786 bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb,
787 &rule_entry->mac.mac_mid,
788 &rule_entry->mac.mac_lsb, mac);
791 /* Set the ramrod data header */
792 /* TODO: take this to the higher level in order to prevent multiple
794 bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
799 * bnx2x_vlan_mac_set_rdata_hdr_e1x - set a header in a single classify ramrod
804 * @cam_offset: offset in cam memory
805 * @hdr: pointer to a header to setup
809 static inline void bnx2x_vlan_mac_set_rdata_hdr_e1x(struct bnx2x *bp,
810 struct bnx2x_vlan_mac_obj *o, int type, int cam_offset,
811 struct mac_configuration_hdr *hdr)
813 struct bnx2x_raw_obj *r = &o->raw;
816 hdr->offset = (u8)cam_offset;
817 hdr->client_id = cpu_to_le16(0xff);
818 hdr->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
819 (type << BNX2X_SWCID_SHIFT));
822 static inline void bnx2x_vlan_mac_set_cfg_entry_e1x(struct bnx2x *bp,
823 struct bnx2x_vlan_mac_obj *o, bool add, int opcode, u8 *mac,
824 u16 vlan_id, struct mac_configuration_entry *cfg_entry)
826 struct bnx2x_raw_obj *r = &o->raw;
827 u32 cl_bit_vec = (1 << r->cl_id);
829 cfg_entry->clients_bit_vector = cpu_to_le32(cl_bit_vec);
830 cfg_entry->pf_id = r->func_id;
831 cfg_entry->vlan_id = cpu_to_le16(vlan_id);
834 SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
835 T_ETH_MAC_COMMAND_SET);
836 SET_FLAG(cfg_entry->flags,
837 MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE, opcode);
839 /* Set a MAC in a ramrod data */
840 bnx2x_set_fw_mac_addr(&cfg_entry->msb_mac_addr,
841 &cfg_entry->middle_mac_addr,
842 &cfg_entry->lsb_mac_addr, mac);
844 SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
845 T_ETH_MAC_COMMAND_INVALIDATE);
848 static inline void bnx2x_vlan_mac_set_rdata_e1x(struct bnx2x *bp,
849 struct bnx2x_vlan_mac_obj *o, int type, int cam_offset, bool add,
850 u8 *mac, u16 vlan_id, int opcode, struct mac_configuration_cmd *config)
852 struct mac_configuration_entry *cfg_entry = &config->config_table[0];
853 struct bnx2x_raw_obj *raw = &o->raw;
855 bnx2x_vlan_mac_set_rdata_hdr_e1x(bp, o, type, cam_offset,
857 bnx2x_vlan_mac_set_cfg_entry_e1x(bp, o, add, opcode, mac, vlan_id,
860 DP(BNX2X_MSG_SP, "%s MAC %pM CLID %d CAM offset %d\n",
861 (add ? "setting" : "clearing"),
862 mac, raw->cl_id, cam_offset);
866 * bnx2x_set_one_mac_e1x - fill a single MAC rule ramrod data
869 * @o: bnx2x_vlan_mac_obj
870 * @elem: bnx2x_exeq_elem
871 * @rule_idx: rule_idx
872 * @cam_offset: cam_offset
874 static void bnx2x_set_one_mac_e1x(struct bnx2x *bp,
875 struct bnx2x_vlan_mac_obj *o,
876 struct bnx2x_exeq_elem *elem, int rule_idx,
879 struct bnx2x_raw_obj *raw = &o->raw;
880 struct mac_configuration_cmd *config =
881 (struct mac_configuration_cmd *)(raw->rdata);
883 * 57710 and 57711 do not support MOVE command,
884 * so it's either ADD or DEL
886 bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ?
889 /* Reset the ramrod data buffer */
890 memset(config, 0, sizeof(*config));
892 bnx2x_vlan_mac_set_rdata_e1x(bp, o, raw->state,
894 elem->cmd_data.vlan_mac.u.mac.mac, 0,
895 ETH_VLAN_FILTER_ANY_VLAN, config);
898 static void bnx2x_set_one_vlan_e2(struct bnx2x *bp,
899 struct bnx2x_vlan_mac_obj *o,
900 struct bnx2x_exeq_elem *elem, int rule_idx,
903 struct bnx2x_raw_obj *raw = &o->raw;
904 struct eth_classify_rules_ramrod_data *data =
905 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
906 int rule_cnt = rule_idx + 1;
907 union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
908 enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
909 bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false;
910 u16 vlan = elem->cmd_data.vlan_mac.u.vlan.vlan;
912 /* Reset the ramrod data buffer for the first rule */
914 memset(data, 0, sizeof(*data));
916 /* Set a rule header */
917 bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_VLAN,
918 &rule_entry->vlan.header);
920 DP(BNX2X_MSG_SP, "About to %s VLAN %d\n", (add ? "add" : "delete"),
923 /* Set a VLAN itself */
924 rule_entry->vlan.vlan = cpu_to_le16(vlan);
926 /* MOVE: Add a rule that will add this MAC to the target Queue */
927 if (cmd == BNX2X_VLAN_MAC_MOVE) {
931 /* Setup ramrod data */
932 bnx2x_vlan_mac_set_cmd_hdr_e2(bp,
933 elem->cmd_data.vlan_mac.target_obj,
934 true, CLASSIFY_RULE_OPCODE_VLAN,
935 &rule_entry->vlan.header);
937 /* Set a VLAN itself */
938 rule_entry->vlan.vlan = cpu_to_le16(vlan);
941 /* Set the ramrod data header */
942 /* TODO: take this to the higher level in order to prevent multiple
944 bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
948 static void bnx2x_set_one_vlan_mac_e2(struct bnx2x *bp,
949 struct bnx2x_vlan_mac_obj *o,
950 struct bnx2x_exeq_elem *elem,
951 int rule_idx, int cam_offset)
953 struct bnx2x_raw_obj *raw = &o->raw;
954 struct eth_classify_rules_ramrod_data *data =
955 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
956 int rule_cnt = rule_idx + 1;
957 union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
958 enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
959 bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false;
960 u16 vlan = elem->cmd_data.vlan_mac.u.vlan_mac.vlan;
961 u8 *mac = elem->cmd_data.vlan_mac.u.vlan_mac.mac;
964 /* Reset the ramrod data buffer for the first rule */
966 memset(data, 0, sizeof(*data));
968 /* Set a rule header */
969 bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_PAIR,
970 &rule_entry->pair.header);
972 /* Set VLAN and MAC themselvs */
973 rule_entry->pair.vlan = cpu_to_le16(vlan);
974 bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb,
975 &rule_entry->pair.mac_mid,
976 &rule_entry->pair.mac_lsb, mac);
978 /* MOVE: Add a rule that will add this MAC to the target Queue */
979 if (cmd == BNX2X_VLAN_MAC_MOVE) {
983 /* Setup ramrod data */
984 bnx2x_vlan_mac_set_cmd_hdr_e2(bp,
985 elem->cmd_data.vlan_mac.target_obj,
986 true, CLASSIFY_RULE_OPCODE_PAIR,
987 &rule_entry->pair.header);
989 /* Set a VLAN itself */
990 rule_entry->pair.vlan = cpu_to_le16(vlan);
991 bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb,
992 &rule_entry->pair.mac_mid,
993 &rule_entry->pair.mac_lsb, mac);
996 /* Set the ramrod data header */
997 /* TODO: take this to the higher level in order to prevent multiple
999 bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
1004 * bnx2x_set_one_vlan_mac_e1h -
1006 * @bp: device handle
1007 * @o: bnx2x_vlan_mac_obj
1008 * @elem: bnx2x_exeq_elem
1009 * @rule_idx: rule_idx
1010 * @cam_offset: cam_offset
1012 static void bnx2x_set_one_vlan_mac_e1h(struct bnx2x *bp,
1013 struct bnx2x_vlan_mac_obj *o,
1014 struct bnx2x_exeq_elem *elem,
1015 int rule_idx, int cam_offset)
1017 struct bnx2x_raw_obj *raw = &o->raw;
1018 struct mac_configuration_cmd *config =
1019 (struct mac_configuration_cmd *)(raw->rdata);
1021 * 57710 and 57711 do not support MOVE command,
1022 * so it's either ADD or DEL
1024 bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ?
1027 /* Reset the ramrod data buffer */
1028 memset(config, 0, sizeof(*config));
1030 bnx2x_vlan_mac_set_rdata_e1x(bp, o, BNX2X_FILTER_VLAN_MAC_PENDING,
1032 elem->cmd_data.vlan_mac.u.vlan_mac.mac,
1033 elem->cmd_data.vlan_mac.u.vlan_mac.vlan,
1034 ETH_VLAN_FILTER_CLASSIFY, config);
1037 #define list_next_entry(pos, member) \
1038 list_entry((pos)->member.next, typeof(*(pos)), member)
1041 * bnx2x_vlan_mac_restore - reconfigure next MAC/VLAN/VLAN-MAC element
1043 * @bp: device handle
1044 * @p: command parameters
1045 * @ppos: pointer to the cooky
1047 * reconfigure next MAC/VLAN/VLAN-MAC element from the
1048 * previously configured elements list.
1050 * from command parameters only RAMROD_COMP_WAIT bit in ramrod_flags is taken
1053 * pointer to the cooky - that should be given back in the next call to make
1054 * function handle the next element. If *ppos is set to NULL it will restart the
1055 * iterator. If returned *ppos == NULL this means that the last element has been
1059 static int bnx2x_vlan_mac_restore(struct bnx2x *bp,
1060 struct bnx2x_vlan_mac_ramrod_params *p,
1061 struct bnx2x_vlan_mac_registry_elem **ppos)
1063 struct bnx2x_vlan_mac_registry_elem *pos;
1064 struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj;
1066 /* If list is empty - there is nothing to do here */
1067 if (list_empty(&o->head)) {
1072 /* make a step... */
1074 *ppos = list_first_entry(&o->head,
1075 struct bnx2x_vlan_mac_registry_elem,
1078 *ppos = list_next_entry(*ppos, link);
1082 /* If it's the last step - return NULL */
1083 if (list_is_last(&pos->link, &o->head))
1086 /* Prepare a 'user_req' */
1087 memcpy(&p->user_req.u, &pos->u, sizeof(pos->u));
1089 /* Set the command */
1090 p->user_req.cmd = BNX2X_VLAN_MAC_ADD;
1092 /* Set vlan_mac_flags */
1093 p->user_req.vlan_mac_flags = pos->vlan_mac_flags;
1095 /* Set a restore bit */
1096 __set_bit(RAMROD_RESTORE, &p->ramrod_flags);
1098 return bnx2x_config_vlan_mac(bp, p);
1102 * bnx2x_exeq_get_mac/bnx2x_exeq_get_vlan/bnx2x_exeq_get_vlan_mac return a
1103 * pointer to an element with a specific criteria and NULL if such an element
1104 * hasn't been found.
1106 static struct bnx2x_exeq_elem *bnx2x_exeq_get_mac(
1107 struct bnx2x_exe_queue_obj *o,
1108 struct bnx2x_exeq_elem *elem)
1110 struct bnx2x_exeq_elem *pos;
1111 struct bnx2x_mac_ramrod_data *data = &elem->cmd_data.vlan_mac.u.mac;
1113 /* Check pending for execution commands */
1114 list_for_each_entry(pos, &o->exe_queue, link)
1115 if (!memcmp(&pos->cmd_data.vlan_mac.u.mac, data,
1117 (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))
1123 static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan(
1124 struct bnx2x_exe_queue_obj *o,
1125 struct bnx2x_exeq_elem *elem)
1127 struct bnx2x_exeq_elem *pos;
1128 struct bnx2x_vlan_ramrod_data *data = &elem->cmd_data.vlan_mac.u.vlan;
1130 /* Check pending for execution commands */
1131 list_for_each_entry(pos, &o->exe_queue, link)
1132 if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan, data,
1134 (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))
1140 static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan_mac(
1141 struct bnx2x_exe_queue_obj *o,
1142 struct bnx2x_exeq_elem *elem)
1144 struct bnx2x_exeq_elem *pos;
1145 struct bnx2x_vlan_mac_ramrod_data *data =
1146 &elem->cmd_data.vlan_mac.u.vlan_mac;
1148 /* Check pending for execution commands */
1149 list_for_each_entry(pos, &o->exe_queue, link)
1150 if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan_mac, data,
1152 (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))
1159 * bnx2x_validate_vlan_mac_add - check if an ADD command can be executed
1161 * @bp: device handle
1162 * @qo: bnx2x_qable_obj
1163 * @elem: bnx2x_exeq_elem
1165 * Checks that the requested configuration can be added. If yes and if
1166 * requested, consume CAM credit.
1168 * The 'validate' is run after the 'optimize'.
1171 static inline int bnx2x_validate_vlan_mac_add(struct bnx2x *bp,
1172 union bnx2x_qable_obj *qo,
1173 struct bnx2x_exeq_elem *elem)
1175 struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac;
1176 struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1179 /* Check the registry */
1180 rc = o->check_add(bp, o, &elem->cmd_data.vlan_mac.u);
1182 DP(BNX2X_MSG_SP, "ADD command is not allowed considering current registry state.\n");
1187 * Check if there is a pending ADD command for this
1188 * MAC/VLAN/VLAN-MAC. Return an error if there is.
1190 if (exeq->get(exeq, elem)) {
1191 DP(BNX2X_MSG_SP, "There is a pending ADD command already\n");
1196 * TODO: Check the pending MOVE from other objects where this
1197 * object is a destination object.
1200 /* Consume the credit if not requested not to */
1201 if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1202 &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1210 * bnx2x_validate_vlan_mac_del - check if the DEL command can be executed
1212 * @bp: device handle
1213 * @qo: quable object to check
1214 * @elem: element that needs to be deleted
1216 * Checks that the requested configuration can be deleted. If yes and if
1217 * requested, returns a CAM credit.
1219 * The 'validate' is run after the 'optimize'.
1221 static inline int bnx2x_validate_vlan_mac_del(struct bnx2x *bp,
1222 union bnx2x_qable_obj *qo,
1223 struct bnx2x_exeq_elem *elem)
1225 struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac;
1226 struct bnx2x_vlan_mac_registry_elem *pos;
1227 struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1228 struct bnx2x_exeq_elem query_elem;
1230 /* If this classification can not be deleted (doesn't exist)
1231 * - return a BNX2X_EXIST.
1233 pos = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u);
1235 DP(BNX2X_MSG_SP, "DEL command is not allowed considering current registry state\n");
1240 * Check if there are pending DEL or MOVE commands for this
1241 * MAC/VLAN/VLAN-MAC. Return an error if so.
1243 memcpy(&query_elem, elem, sizeof(query_elem));
1245 /* Check for MOVE commands */
1246 query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_MOVE;
1247 if (exeq->get(exeq, &query_elem)) {
1248 BNX2X_ERR("There is a pending MOVE command already\n");
1252 /* Check for DEL commands */
1253 if (exeq->get(exeq, elem)) {
1254 DP(BNX2X_MSG_SP, "There is a pending DEL command already\n");
1258 /* Return the credit to the credit pool if not requested not to */
1259 if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1260 &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1261 o->put_credit(o))) {
1262 BNX2X_ERR("Failed to return a credit\n");
1270 * bnx2x_validate_vlan_mac_move - check if the MOVE command can be executed
1272 * @bp: device handle
1273 * @qo: quable object to check (source)
1274 * @elem: element that needs to be moved
1276 * Checks that the requested configuration can be moved. If yes and if
1277 * requested, returns a CAM credit.
1279 * The 'validate' is run after the 'optimize'.
1281 static inline int bnx2x_validate_vlan_mac_move(struct bnx2x *bp,
1282 union bnx2x_qable_obj *qo,
1283 struct bnx2x_exeq_elem *elem)
1285 struct bnx2x_vlan_mac_obj *src_o = &qo->vlan_mac;
1286 struct bnx2x_vlan_mac_obj *dest_o = elem->cmd_data.vlan_mac.target_obj;
1287 struct bnx2x_exeq_elem query_elem;
1288 struct bnx2x_exe_queue_obj *src_exeq = &src_o->exe_queue;
1289 struct bnx2x_exe_queue_obj *dest_exeq = &dest_o->exe_queue;
1292 * Check if we can perform this operation based on the current registry
1295 if (!src_o->check_move(bp, src_o, dest_o,
1296 &elem->cmd_data.vlan_mac.u)) {
1297 DP(BNX2X_MSG_SP, "MOVE command is not allowed considering current registry state\n");
1302 * Check if there is an already pending DEL or MOVE command for the
1303 * source object or ADD command for a destination object. Return an
1306 memcpy(&query_elem, elem, sizeof(query_elem));
1308 /* Check DEL on source */
1309 query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL;
1310 if (src_exeq->get(src_exeq, &query_elem)) {
1311 BNX2X_ERR("There is a pending DEL command on the source queue already\n");
1315 /* Check MOVE on source */
1316 if (src_exeq->get(src_exeq, elem)) {
1317 DP(BNX2X_MSG_SP, "There is a pending MOVE command already\n");
1321 /* Check ADD on destination */
1322 query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD;
1323 if (dest_exeq->get(dest_exeq, &query_elem)) {
1324 BNX2X_ERR("There is a pending ADD command on the destination queue already\n");
1328 /* Consume the credit if not requested not to */
1329 if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
1330 &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1331 dest_o->get_credit(dest_o)))
1334 if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1335 &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1336 src_o->put_credit(src_o))) {
1337 /* return the credit taken from dest... */
1338 dest_o->put_credit(dest_o);
1345 static int bnx2x_validate_vlan_mac(struct bnx2x *bp,
1346 union bnx2x_qable_obj *qo,
1347 struct bnx2x_exeq_elem *elem)
1349 switch (elem->cmd_data.vlan_mac.cmd) {
1350 case BNX2X_VLAN_MAC_ADD:
1351 return bnx2x_validate_vlan_mac_add(bp, qo, elem);
1352 case BNX2X_VLAN_MAC_DEL:
1353 return bnx2x_validate_vlan_mac_del(bp, qo, elem);
1354 case BNX2X_VLAN_MAC_MOVE:
1355 return bnx2x_validate_vlan_mac_move(bp, qo, elem);
1361 static int bnx2x_remove_vlan_mac(struct bnx2x *bp,
1362 union bnx2x_qable_obj *qo,
1363 struct bnx2x_exeq_elem *elem)
1367 /* If consumption wasn't required, nothing to do */
1368 if (test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1369 &elem->cmd_data.vlan_mac.vlan_mac_flags))
1372 switch (elem->cmd_data.vlan_mac.cmd) {
1373 case BNX2X_VLAN_MAC_ADD:
1374 case BNX2X_VLAN_MAC_MOVE:
1375 rc = qo->vlan_mac.put_credit(&qo->vlan_mac);
1377 case BNX2X_VLAN_MAC_DEL:
1378 rc = qo->vlan_mac.get_credit(&qo->vlan_mac);
1391 * bnx2x_wait_vlan_mac - passivly wait for 5 seconds until all work completes.
1393 * @bp: device handle
1394 * @o: bnx2x_vlan_mac_obj
1397 static int bnx2x_wait_vlan_mac(struct bnx2x *bp,
1398 struct bnx2x_vlan_mac_obj *o)
1401 struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1402 struct bnx2x_raw_obj *raw = &o->raw;
1405 /* Wait for the current command to complete */
1406 rc = raw->wait_comp(bp, raw);
1410 /* Wait until there are no pending commands */
1411 if (!bnx2x_exe_queue_empty(exeq))
1412 usleep_range(1000, 2000);
1421 * bnx2x_complete_vlan_mac - complete one VLAN-MAC ramrod
1423 * @bp: device handle
1424 * @o: bnx2x_vlan_mac_obj
1426 * @cont: if true schedule next execution chunk
1429 static int bnx2x_complete_vlan_mac(struct bnx2x *bp,
1430 struct bnx2x_vlan_mac_obj *o,
1431 union event_ring_elem *cqe,
1432 unsigned long *ramrod_flags)
1434 struct bnx2x_raw_obj *r = &o->raw;
1437 /* Reset pending list */
1438 bnx2x_exe_queue_reset_pending(bp, &o->exe_queue);
1441 r->clear_pending(r);
1443 /* If ramrod failed this is most likely a SW bug */
1444 if (cqe->message.error)
1447 /* Run the next bulk of pending commands if requested */
1448 if (test_bit(RAMROD_CONT, ramrod_flags)) {
1449 rc = bnx2x_exe_queue_step(bp, &o->exe_queue, ramrod_flags);
1454 /* If there is more work to do return PENDING */
1455 if (!bnx2x_exe_queue_empty(&o->exe_queue))
1462 * bnx2x_optimize_vlan_mac - optimize ADD and DEL commands.
1464 * @bp: device handle
1465 * @o: bnx2x_qable_obj
1466 * @elem: bnx2x_exeq_elem
1468 static int bnx2x_optimize_vlan_mac(struct bnx2x *bp,
1469 union bnx2x_qable_obj *qo,
1470 struct bnx2x_exeq_elem *elem)
1472 struct bnx2x_exeq_elem query, *pos;
1473 struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac;
1474 struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1476 memcpy(&query, elem, sizeof(query));
1478 switch (elem->cmd_data.vlan_mac.cmd) {
1479 case BNX2X_VLAN_MAC_ADD:
1480 query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL;
1482 case BNX2X_VLAN_MAC_DEL:
1483 query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD;
1486 /* Don't handle anything other than ADD or DEL */
1490 /* If we found the appropriate element - delete it */
1491 pos = exeq->get(exeq, &query);
1494 /* Return the credit of the optimized command */
1495 if (!test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1496 &pos->cmd_data.vlan_mac.vlan_mac_flags)) {
1497 if ((query.cmd_data.vlan_mac.cmd ==
1498 BNX2X_VLAN_MAC_ADD) && !o->put_credit(o)) {
1499 BNX2X_ERR("Failed to return the credit for the optimized ADD command\n");
1501 } else if (!o->get_credit(o)) { /* VLAN_MAC_DEL */
1502 BNX2X_ERR("Failed to recover the credit from the optimized DEL command\n");
1507 DP(BNX2X_MSG_SP, "Optimizing %s command\n",
1508 (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ?
1511 list_del(&pos->link);
1512 bnx2x_exe_queue_free_elem(bp, pos);
1520 * bnx2x_vlan_mac_get_registry_elem - prepare a registry element
1522 * @bp: device handle
1528 * prepare a registry element according to the current command request.
1530 static inline int bnx2x_vlan_mac_get_registry_elem(
1532 struct bnx2x_vlan_mac_obj *o,
1533 struct bnx2x_exeq_elem *elem,
1535 struct bnx2x_vlan_mac_registry_elem **re)
1537 enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
1538 struct bnx2x_vlan_mac_registry_elem *reg_elem;
1540 /* Allocate a new registry element if needed. */
1542 ((cmd == BNX2X_VLAN_MAC_ADD) || (cmd == BNX2X_VLAN_MAC_MOVE))) {
1543 reg_elem = kzalloc(sizeof(*reg_elem), GFP_ATOMIC);
1547 /* Get a new CAM offset */
1548 if (!o->get_cam_offset(o, ®_elem->cam_offset)) {
1550 * This shell never happen, because we have checked the
1551 * CAM availiability in the 'validate'.
1558 DP(BNX2X_MSG_SP, "Got cam offset %d\n", reg_elem->cam_offset);
1560 /* Set a VLAN-MAC data */
1561 memcpy(®_elem->u, &elem->cmd_data.vlan_mac.u,
1562 sizeof(reg_elem->u));
1564 /* Copy the flags (needed for DEL and RESTORE flows) */
1565 reg_elem->vlan_mac_flags =
1566 elem->cmd_data.vlan_mac.vlan_mac_flags;
1567 } else /* DEL, RESTORE */
1568 reg_elem = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u);
1575 * bnx2x_execute_vlan_mac - execute vlan mac command
1577 * @bp: device handle
1582 * go and send a ramrod!
1584 static int bnx2x_execute_vlan_mac(struct bnx2x *bp,
1585 union bnx2x_qable_obj *qo,
1586 struct list_head *exe_chunk,
1587 unsigned long *ramrod_flags)
1589 struct bnx2x_exeq_elem *elem;
1590 struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac, *cam_obj;
1591 struct bnx2x_raw_obj *r = &o->raw;
1593 bool restore = test_bit(RAMROD_RESTORE, ramrod_flags);
1594 bool drv_only = test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags);
1595 struct bnx2x_vlan_mac_registry_elem *reg_elem;
1596 enum bnx2x_vlan_mac_cmd cmd;
1599 * If DRIVER_ONLY execution is requested, cleanup a registry
1600 * and exit. Otherwise send a ramrod to FW.
1603 WARN_ON(r->check_pending(r));
1608 /* Fill tha ramrod data */
1609 list_for_each_entry(elem, exe_chunk, link) {
1610 cmd = elem->cmd_data.vlan_mac.cmd;
1612 * We will add to the target object in MOVE command, so
1613 * change the object for a CAM search.
1615 if (cmd == BNX2X_VLAN_MAC_MOVE)
1616 cam_obj = elem->cmd_data.vlan_mac.target_obj;
1620 rc = bnx2x_vlan_mac_get_registry_elem(bp, cam_obj,
1628 /* Push a new entry into the registry */
1630 ((cmd == BNX2X_VLAN_MAC_ADD) ||
1631 (cmd == BNX2X_VLAN_MAC_MOVE)))
1632 list_add(®_elem->link, &cam_obj->head);
1634 /* Configure a single command in a ramrod data buffer */
1635 o->set_one_rule(bp, o, elem, idx,
1636 reg_elem->cam_offset);
1638 /* MOVE command consumes 2 entries in the ramrod data */
1639 if (cmd == BNX2X_VLAN_MAC_MOVE)
1646 * No need for an explicit memory barrier here as long we would
1647 * need to ensure the ordering of writing to the SPQ element
1648 * and updating of the SPQ producer which involves a memory
1649 * read and we will have to put a full memory barrier there
1650 * (inside bnx2x_sp_post()).
1653 rc = bnx2x_sp_post(bp, o->ramrod_cmd, r->cid,
1654 U64_HI(r->rdata_mapping),
1655 U64_LO(r->rdata_mapping),
1656 ETH_CONNECTION_TYPE);
1661 /* Now, when we are done with the ramrod - clean up the registry */
1662 list_for_each_entry(elem, exe_chunk, link) {
1663 cmd = elem->cmd_data.vlan_mac.cmd;
1664 if ((cmd == BNX2X_VLAN_MAC_DEL) ||
1665 (cmd == BNX2X_VLAN_MAC_MOVE)) {
1666 reg_elem = o->check_del(bp, o,
1667 &elem->cmd_data.vlan_mac.u);
1671 o->put_cam_offset(o, reg_elem->cam_offset);
1672 list_del(®_elem->link);
1683 r->clear_pending(r);
1685 /* Cleanup a registry in case of a failure */
1686 list_for_each_entry(elem, exe_chunk, link) {
1687 cmd = elem->cmd_data.vlan_mac.cmd;
1689 if (cmd == BNX2X_VLAN_MAC_MOVE)
1690 cam_obj = elem->cmd_data.vlan_mac.target_obj;
1694 /* Delete all newly added above entries */
1696 ((cmd == BNX2X_VLAN_MAC_ADD) ||
1697 (cmd == BNX2X_VLAN_MAC_MOVE))) {
1698 reg_elem = o->check_del(bp, cam_obj,
1699 &elem->cmd_data.vlan_mac.u);
1701 list_del(®_elem->link);
1710 static inline int bnx2x_vlan_mac_push_new_cmd(
1712 struct bnx2x_vlan_mac_ramrod_params *p)
1714 struct bnx2x_exeq_elem *elem;
1715 struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj;
1716 bool restore = test_bit(RAMROD_RESTORE, &p->ramrod_flags);
1718 /* Allocate the execution queue element */
1719 elem = bnx2x_exe_queue_alloc_elem(bp);
1723 /* Set the command 'length' */
1724 switch (p->user_req.cmd) {
1725 case BNX2X_VLAN_MAC_MOVE:
1732 /* Fill the object specific info */
1733 memcpy(&elem->cmd_data.vlan_mac, &p->user_req, sizeof(p->user_req));
1735 /* Try to add a new command to the pending list */
1736 return bnx2x_exe_queue_add(bp, &o->exe_queue, elem, restore);
1740 * bnx2x_config_vlan_mac - configure VLAN/MAC/VLAN_MAC filtering rules.
1742 * @bp: device handle
1746 int bnx2x_config_vlan_mac(
1748 struct bnx2x_vlan_mac_ramrod_params *p)
1751 struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj;
1752 unsigned long *ramrod_flags = &p->ramrod_flags;
1753 bool cont = test_bit(RAMROD_CONT, ramrod_flags);
1754 struct bnx2x_raw_obj *raw = &o->raw;
1757 * Add new elements to the execution list for commands that require it.
1760 rc = bnx2x_vlan_mac_push_new_cmd(bp, p);
1766 * If nothing will be executed further in this iteration we want to
1767 * return PENDING if there are pending commands
1769 if (!bnx2x_exe_queue_empty(&o->exe_queue))
1772 if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {
1773 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\n");
1774 raw->clear_pending(raw);
1777 /* Execute commands if required */
1778 if (cont || test_bit(RAMROD_EXEC, ramrod_flags) ||
1779 test_bit(RAMROD_COMP_WAIT, ramrod_flags)) {
1780 rc = bnx2x_exe_queue_step(bp, &o->exe_queue, ramrod_flags);
1786 * RAMROD_COMP_WAIT is a superset of RAMROD_EXEC. If it was set
1787 * then user want to wait until the last command is done.
1789 if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) {
1791 * Wait maximum for the current exe_queue length iterations plus
1792 * one (for the current pending command).
1794 int max_iterations = bnx2x_exe_queue_length(&o->exe_queue) + 1;
1796 while (!bnx2x_exe_queue_empty(&o->exe_queue) &&
1799 /* Wait for the current command to complete */
1800 rc = raw->wait_comp(bp, raw);
1804 /* Make a next step */
1805 rc = bnx2x_exe_queue_step(bp, &o->exe_queue,
1820 * bnx2x_vlan_mac_del_all - delete elements with given vlan_mac_flags spec
1822 * @bp: device handle
1825 * @ramrod_flags: execution flags to be used for this deletion
1827 * if the last operation has completed successfully and there are no
1828 * moreelements left, positive value if the last operation has completed
1829 * successfully and there are more previously configured elements, negative
1830 * value is current operation has failed.
1832 static int bnx2x_vlan_mac_del_all(struct bnx2x *bp,
1833 struct bnx2x_vlan_mac_obj *o,
1834 unsigned long *vlan_mac_flags,
1835 unsigned long *ramrod_flags)
1837 struct bnx2x_vlan_mac_registry_elem *pos = NULL;
1839 struct bnx2x_vlan_mac_ramrod_params p;
1840 struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1841 struct bnx2x_exeq_elem *exeq_pos, *exeq_pos_n;
1843 /* Clear pending commands first */
1845 spin_lock_bh(&exeq->lock);
1847 list_for_each_entry_safe(exeq_pos, exeq_pos_n, &exeq->exe_queue, link) {
1848 if (exeq_pos->cmd_data.vlan_mac.vlan_mac_flags ==
1850 rc = exeq->remove(bp, exeq->owner, exeq_pos);
1852 BNX2X_ERR("Failed to remove command\n");
1853 spin_unlock_bh(&exeq->lock);
1856 list_del(&exeq_pos->link);
1857 bnx2x_exe_queue_free_elem(bp, exeq_pos);
1861 spin_unlock_bh(&exeq->lock);
1863 /* Prepare a command request */
1864 memset(&p, 0, sizeof(p));
1866 p.ramrod_flags = *ramrod_flags;
1867 p.user_req.cmd = BNX2X_VLAN_MAC_DEL;
1870 * Add all but the last VLAN-MAC to the execution queue without actually
1871 * execution anything.
1873 __clear_bit(RAMROD_COMP_WAIT, &p.ramrod_flags);
1874 __clear_bit(RAMROD_EXEC, &p.ramrod_flags);
1875 __clear_bit(RAMROD_CONT, &p.ramrod_flags);
1877 list_for_each_entry(pos, &o->head, link) {
1878 if (pos->vlan_mac_flags == *vlan_mac_flags) {
1879 p.user_req.vlan_mac_flags = pos->vlan_mac_flags;
1880 memcpy(&p.user_req.u, &pos->u, sizeof(pos->u));
1881 rc = bnx2x_config_vlan_mac(bp, &p);
1883 BNX2X_ERR("Failed to add a new DEL command\n");
1889 p.ramrod_flags = *ramrod_flags;
1890 __set_bit(RAMROD_CONT, &p.ramrod_flags);
1892 return bnx2x_config_vlan_mac(bp, &p);
1895 static inline void bnx2x_init_raw_obj(struct bnx2x_raw_obj *raw, u8 cl_id,
1896 u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping, int state,
1897 unsigned long *pstate, bnx2x_obj_type type)
1899 raw->func_id = func_id;
1903 raw->rdata_mapping = rdata_mapping;
1905 raw->pstate = pstate;
1906 raw->obj_type = type;
1907 raw->check_pending = bnx2x_raw_check_pending;
1908 raw->clear_pending = bnx2x_raw_clear_pending;
1909 raw->set_pending = bnx2x_raw_set_pending;
1910 raw->wait_comp = bnx2x_raw_wait;
1913 static inline void bnx2x_init_vlan_mac_common(struct bnx2x_vlan_mac_obj *o,
1914 u8 cl_id, u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping,
1915 int state, unsigned long *pstate, bnx2x_obj_type type,
1916 struct bnx2x_credit_pool_obj *macs_pool,
1917 struct bnx2x_credit_pool_obj *vlans_pool)
1919 INIT_LIST_HEAD(&o->head);
1921 o->macs_pool = macs_pool;
1922 o->vlans_pool = vlans_pool;
1924 o->delete_all = bnx2x_vlan_mac_del_all;
1925 o->restore = bnx2x_vlan_mac_restore;
1926 o->complete = bnx2x_complete_vlan_mac;
1927 o->wait = bnx2x_wait_vlan_mac;
1929 bnx2x_init_raw_obj(&o->raw, cl_id, cid, func_id, rdata, rdata_mapping,
1930 state, pstate, type);
1934 void bnx2x_init_mac_obj(struct bnx2x *bp,
1935 struct bnx2x_vlan_mac_obj *mac_obj,
1936 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1937 dma_addr_t rdata_mapping, int state,
1938 unsigned long *pstate, bnx2x_obj_type type,
1939 struct bnx2x_credit_pool_obj *macs_pool)
1941 union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)mac_obj;
1943 bnx2x_init_vlan_mac_common(mac_obj, cl_id, cid, func_id, rdata,
1944 rdata_mapping, state, pstate, type,
1947 /* CAM credit pool handling */
1948 mac_obj->get_credit = bnx2x_get_credit_mac;
1949 mac_obj->put_credit = bnx2x_put_credit_mac;
1950 mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac;
1951 mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac;
1953 if (CHIP_IS_E1x(bp)) {
1954 mac_obj->set_one_rule = bnx2x_set_one_mac_e1x;
1955 mac_obj->check_del = bnx2x_check_mac_del;
1956 mac_obj->check_add = bnx2x_check_mac_add;
1957 mac_obj->check_move = bnx2x_check_move_always_err;
1958 mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC;
1961 bnx2x_exe_queue_init(bp,
1962 &mac_obj->exe_queue, 1, qable_obj,
1963 bnx2x_validate_vlan_mac,
1964 bnx2x_remove_vlan_mac,
1965 bnx2x_optimize_vlan_mac,
1966 bnx2x_execute_vlan_mac,
1967 bnx2x_exeq_get_mac);
1969 mac_obj->set_one_rule = bnx2x_set_one_mac_e2;
1970 mac_obj->check_del = bnx2x_check_mac_del;
1971 mac_obj->check_add = bnx2x_check_mac_add;
1972 mac_obj->check_move = bnx2x_check_move;
1973 mac_obj->ramrod_cmd =
1974 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
1975 mac_obj->get_n_elements = bnx2x_get_n_elements;
1978 bnx2x_exe_queue_init(bp,
1979 &mac_obj->exe_queue, CLASSIFY_RULES_COUNT,
1980 qable_obj, bnx2x_validate_vlan_mac,
1981 bnx2x_remove_vlan_mac,
1982 bnx2x_optimize_vlan_mac,
1983 bnx2x_execute_vlan_mac,
1984 bnx2x_exeq_get_mac);
1988 void bnx2x_init_vlan_obj(struct bnx2x *bp,
1989 struct bnx2x_vlan_mac_obj *vlan_obj,
1990 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1991 dma_addr_t rdata_mapping, int state,
1992 unsigned long *pstate, bnx2x_obj_type type,
1993 struct bnx2x_credit_pool_obj *vlans_pool)
1995 union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)vlan_obj;
1997 bnx2x_init_vlan_mac_common(vlan_obj, cl_id, cid, func_id, rdata,
1998 rdata_mapping, state, pstate, type, NULL,
2001 vlan_obj->get_credit = bnx2x_get_credit_vlan;
2002 vlan_obj->put_credit = bnx2x_put_credit_vlan;
2003 vlan_obj->get_cam_offset = bnx2x_get_cam_offset_vlan;
2004 vlan_obj->put_cam_offset = bnx2x_put_cam_offset_vlan;
2006 if (CHIP_IS_E1x(bp)) {
2007 BNX2X_ERR("Do not support chips others than E2 and newer\n");
2010 vlan_obj->set_one_rule = bnx2x_set_one_vlan_e2;
2011 vlan_obj->check_del = bnx2x_check_vlan_del;
2012 vlan_obj->check_add = bnx2x_check_vlan_add;
2013 vlan_obj->check_move = bnx2x_check_move;
2014 vlan_obj->ramrod_cmd =
2015 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
2018 bnx2x_exe_queue_init(bp,
2019 &vlan_obj->exe_queue, CLASSIFY_RULES_COUNT,
2020 qable_obj, bnx2x_validate_vlan_mac,
2021 bnx2x_remove_vlan_mac,
2022 bnx2x_optimize_vlan_mac,
2023 bnx2x_execute_vlan_mac,
2024 bnx2x_exeq_get_vlan);
2028 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp,
2029 struct bnx2x_vlan_mac_obj *vlan_mac_obj,
2030 u8 cl_id, u32 cid, u8 func_id, void *rdata,
2031 dma_addr_t rdata_mapping, int state,
2032 unsigned long *pstate, bnx2x_obj_type type,
2033 struct bnx2x_credit_pool_obj *macs_pool,
2034 struct bnx2x_credit_pool_obj *vlans_pool)
2036 union bnx2x_qable_obj *qable_obj =
2037 (union bnx2x_qable_obj *)vlan_mac_obj;
2039 bnx2x_init_vlan_mac_common(vlan_mac_obj, cl_id, cid, func_id, rdata,
2040 rdata_mapping, state, pstate, type,
2041 macs_pool, vlans_pool);
2043 /* CAM pool handling */
2044 vlan_mac_obj->get_credit = bnx2x_get_credit_vlan_mac;
2045 vlan_mac_obj->put_credit = bnx2x_put_credit_vlan_mac;
2047 * CAM offset is relevant for 57710 and 57711 chips only which have a
2048 * single CAM for both MACs and VLAN-MAC pairs. So the offset
2049 * will be taken from MACs' pool object only.
2051 vlan_mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac;
2052 vlan_mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac;
2054 if (CHIP_IS_E1(bp)) {
2055 BNX2X_ERR("Do not support chips others than E2\n");
2057 } else if (CHIP_IS_E1H(bp)) {
2058 vlan_mac_obj->set_one_rule = bnx2x_set_one_vlan_mac_e1h;
2059 vlan_mac_obj->check_del = bnx2x_check_vlan_mac_del;
2060 vlan_mac_obj->check_add = bnx2x_check_vlan_mac_add;
2061 vlan_mac_obj->check_move = bnx2x_check_move_always_err;
2062 vlan_mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC;
2065 bnx2x_exe_queue_init(bp,
2066 &vlan_mac_obj->exe_queue, 1, qable_obj,
2067 bnx2x_validate_vlan_mac,
2068 bnx2x_remove_vlan_mac,
2069 bnx2x_optimize_vlan_mac,
2070 bnx2x_execute_vlan_mac,
2071 bnx2x_exeq_get_vlan_mac);
2073 vlan_mac_obj->set_one_rule = bnx2x_set_one_vlan_mac_e2;
2074 vlan_mac_obj->check_del = bnx2x_check_vlan_mac_del;
2075 vlan_mac_obj->check_add = bnx2x_check_vlan_mac_add;
2076 vlan_mac_obj->check_move = bnx2x_check_move;
2077 vlan_mac_obj->ramrod_cmd =
2078 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
2081 bnx2x_exe_queue_init(bp,
2082 &vlan_mac_obj->exe_queue,
2083 CLASSIFY_RULES_COUNT,
2084 qable_obj, bnx2x_validate_vlan_mac,
2085 bnx2x_remove_vlan_mac,
2086 bnx2x_optimize_vlan_mac,
2087 bnx2x_execute_vlan_mac,
2088 bnx2x_exeq_get_vlan_mac);
2093 /* RX_MODE verbs: DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
2094 static inline void __storm_memset_mac_filters(struct bnx2x *bp,
2095 struct tstorm_eth_mac_filter_config *mac_filters,
2098 size_t size = sizeof(struct tstorm_eth_mac_filter_config);
2100 u32 addr = BAR_TSTRORM_INTMEM +
2101 TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id);
2103 __storm_memset_struct(bp, addr, size, (u32 *)mac_filters);
2106 static int bnx2x_set_rx_mode_e1x(struct bnx2x *bp,
2107 struct bnx2x_rx_mode_ramrod_params *p)
2109 /* update the bp MAC filter structure */
2110 u32 mask = (1 << p->cl_id);
2112 struct tstorm_eth_mac_filter_config *mac_filters =
2113 (struct tstorm_eth_mac_filter_config *)p->rdata;
2115 /* initial seeting is drop-all */
2116 u8 drop_all_ucast = 1, drop_all_mcast = 1;
2117 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2118 u8 unmatched_unicast = 0;
2120 /* In e1x there we only take into account rx acceot flag since tx switching
2122 if (test_bit(BNX2X_ACCEPT_UNICAST, &p->rx_accept_flags))
2123 /* accept matched ucast */
2126 if (test_bit(BNX2X_ACCEPT_MULTICAST, &p->rx_accept_flags))
2127 /* accept matched mcast */
2130 if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, &p->rx_accept_flags)) {
2131 /* accept all mcast */
2135 if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, &p->rx_accept_flags)) {
2136 /* accept all mcast */
2140 if (test_bit(BNX2X_ACCEPT_BROADCAST, &p->rx_accept_flags))
2141 /* accept (all) bcast */
2143 if (test_bit(BNX2X_ACCEPT_UNMATCHED, &p->rx_accept_flags))
2144 /* accept unmatched unicasts */
2145 unmatched_unicast = 1;
2147 mac_filters->ucast_drop_all = drop_all_ucast ?
2148 mac_filters->ucast_drop_all | mask :
2149 mac_filters->ucast_drop_all & ~mask;
2151 mac_filters->mcast_drop_all = drop_all_mcast ?
2152 mac_filters->mcast_drop_all | mask :
2153 mac_filters->mcast_drop_all & ~mask;
2155 mac_filters->ucast_accept_all = accp_all_ucast ?
2156 mac_filters->ucast_accept_all | mask :
2157 mac_filters->ucast_accept_all & ~mask;
2159 mac_filters->mcast_accept_all = accp_all_mcast ?
2160 mac_filters->mcast_accept_all | mask :
2161 mac_filters->mcast_accept_all & ~mask;
2163 mac_filters->bcast_accept_all = accp_all_bcast ?
2164 mac_filters->bcast_accept_all | mask :
2165 mac_filters->bcast_accept_all & ~mask;
2167 mac_filters->unmatched_unicast = unmatched_unicast ?
2168 mac_filters->unmatched_unicast | mask :
2169 mac_filters->unmatched_unicast & ~mask;
2171 DP(BNX2X_MSG_SP, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n"
2172 "accp_mcast 0x%x\naccp_bcast 0x%x\n",
2173 mac_filters->ucast_drop_all, mac_filters->mcast_drop_all,
2174 mac_filters->ucast_accept_all, mac_filters->mcast_accept_all,
2175 mac_filters->bcast_accept_all);
2177 /* write the MAC filter structure*/
2178 __storm_memset_mac_filters(bp, mac_filters, p->func_id);
2180 /* The operation is completed */
2181 clear_bit(p->state, p->pstate);
2182 smp_mb__after_clear_bit();
2187 /* Setup ramrod data */
2188 static inline void bnx2x_rx_mode_set_rdata_hdr_e2(u32 cid,
2189 struct eth_classify_header *hdr,
2192 hdr->echo = cpu_to_le32(cid);
2193 hdr->rule_cnt = rule_cnt;
2196 static inline void bnx2x_rx_mode_set_cmd_state_e2(struct bnx2x *bp,
2197 unsigned long *accept_flags,
2198 struct eth_filter_rules_cmd *cmd,
2199 bool clear_accept_all)
2203 /* start with 'drop-all' */
2204 state = ETH_FILTER_RULES_CMD_UCAST_DROP_ALL |
2205 ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2207 if (test_bit(BNX2X_ACCEPT_UNICAST, accept_flags))
2208 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2210 if (test_bit(BNX2X_ACCEPT_MULTICAST, accept_flags))
2211 state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2213 if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, accept_flags)) {
2214 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2215 state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL;
2218 if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, accept_flags)) {
2219 state |= ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL;
2220 state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2223 if (test_bit(BNX2X_ACCEPT_BROADCAST, accept_flags))
2224 state |= ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL;
2226 if (test_bit(BNX2X_ACCEPT_UNMATCHED, accept_flags)) {
2227 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2228 state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED;
2231 if (test_bit(BNX2X_ACCEPT_ANY_VLAN, accept_flags))
2232 state |= ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN;
2234 /* Clear ACCEPT_ALL_XXX flags for FCoE L2 Queue */
2235 if (clear_accept_all) {
2236 state &= ~ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL;
2237 state &= ~ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL;
2238 state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL;
2239 state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED;
2242 cmd->state = cpu_to_le16(state);
2246 static int bnx2x_set_rx_mode_e2(struct bnx2x *bp,
2247 struct bnx2x_rx_mode_ramrod_params *p)
2249 struct eth_filter_rules_ramrod_data *data = p->rdata;
2253 /* Reset the ramrod data buffer */
2254 memset(data, 0, sizeof(*data));
2256 /* Setup ramrod data */
2258 /* Tx (internal switching) */
2259 if (test_bit(RAMROD_TX, &p->ramrod_flags)) {
2260 data->rules[rule_idx].client_id = p->cl_id;
2261 data->rules[rule_idx].func_id = p->func_id;
2263 data->rules[rule_idx].cmd_general_data =
2264 ETH_FILTER_RULES_CMD_TX_CMD;
2266 bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags,
2267 &(data->rules[rule_idx++]),
2272 if (test_bit(RAMROD_RX, &p->ramrod_flags)) {
2273 data->rules[rule_idx].client_id = p->cl_id;
2274 data->rules[rule_idx].func_id = p->func_id;
2276 data->rules[rule_idx].cmd_general_data =
2277 ETH_FILTER_RULES_CMD_RX_CMD;
2279 bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags,
2280 &(data->rules[rule_idx++]),
2286 * If FCoE Queue configuration has been requested configure the Rx and
2287 * internal switching modes for this queue in separate rules.
2289 * FCoE queue shell never be set to ACCEPT_ALL packets of any sort:
2290 * MCAST_ALL, UCAST_ALL, BCAST_ALL and UNMATCHED.
2292 if (test_bit(BNX2X_RX_MODE_FCOE_ETH, &p->rx_mode_flags)) {
2293 /* Tx (internal switching) */
2294 if (test_bit(RAMROD_TX, &p->ramrod_flags)) {
2295 data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id);
2296 data->rules[rule_idx].func_id = p->func_id;
2298 data->rules[rule_idx].cmd_general_data =
2299 ETH_FILTER_RULES_CMD_TX_CMD;
2301 bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags,
2302 &(data->rules[rule_idx]),
2308 if (test_bit(RAMROD_RX, &p->ramrod_flags)) {
2309 data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id);
2310 data->rules[rule_idx].func_id = p->func_id;
2312 data->rules[rule_idx].cmd_general_data =
2313 ETH_FILTER_RULES_CMD_RX_CMD;
2315 bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags,
2316 &(data->rules[rule_idx]),
2323 * Set the ramrod header (most importantly - number of rules to
2326 bnx2x_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx);
2328 DP(BNX2X_MSG_SP, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\n",
2329 data->header.rule_cnt, p->rx_accept_flags,
2330 p->tx_accept_flags);
2333 * No need for an explicit memory barrier here as long we would
2334 * need to ensure the ordering of writing to the SPQ element
2335 * and updating of the SPQ producer which involves a memory
2336 * read and we will have to put a full memory barrier there
2337 * (inside bnx2x_sp_post()).
2341 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_FILTER_RULES, p->cid,
2342 U64_HI(p->rdata_mapping),
2343 U64_LO(p->rdata_mapping),
2344 ETH_CONNECTION_TYPE);
2348 /* Ramrod completion is pending */
2352 static int bnx2x_wait_rx_mode_comp_e2(struct bnx2x *bp,
2353 struct bnx2x_rx_mode_ramrod_params *p)
2355 return bnx2x_state_wait(bp, p->state, p->pstate);
2358 static int bnx2x_empty_rx_mode_wait(struct bnx2x *bp,
2359 struct bnx2x_rx_mode_ramrod_params *p)
2365 int bnx2x_config_rx_mode(struct bnx2x *bp,
2366 struct bnx2x_rx_mode_ramrod_params *p)
2370 /* Configure the new classification in the chip */
2371 rc = p->rx_mode_obj->config_rx_mode(bp, p);
2375 /* Wait for a ramrod completion if was requested */
2376 if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) {
2377 rc = p->rx_mode_obj->wait_comp(bp, p);
2385 void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
2386 struct bnx2x_rx_mode_obj *o)
2388 if (CHIP_IS_E1x(bp)) {
2389 o->wait_comp = bnx2x_empty_rx_mode_wait;
2390 o->config_rx_mode = bnx2x_set_rx_mode_e1x;
2392 o->wait_comp = bnx2x_wait_rx_mode_comp_e2;
2393 o->config_rx_mode = bnx2x_set_rx_mode_e2;
2397 /********************* Multicast verbs: SET, CLEAR ****************************/
2398 static inline u8 bnx2x_mcast_bin_from_mac(u8 *mac)
2400 return (crc32c_le(0, mac, ETH_ALEN) >> 24) & 0xff;
2403 struct bnx2x_mcast_mac_elem {
2404 struct list_head link;
2406 u8 pad[2]; /* For a natural alignment of the following buffer */
2409 struct bnx2x_pending_mcast_cmd {
2410 struct list_head link;
2411 int type; /* BNX2X_MCAST_CMD_X */
2413 struct list_head macs_head;
2414 u32 macs_num; /* Needed for DEL command */
2415 int next_bin; /* Needed for RESTORE flow with aprox match */
2418 bool done; /* set to true, when the command has been handled,
2419 * practically used in 57712 handling only, where one pending
2420 * command may be handled in a few operations. As long as for
2421 * other chips every operation handling is completed in a
2422 * single ramrod, there is no need to utilize this field.
2426 static int bnx2x_mcast_wait(struct bnx2x *bp,
2427 struct bnx2x_mcast_obj *o)
2429 if (bnx2x_state_wait(bp, o->sched_state, o->raw.pstate) ||
2430 o->raw.wait_comp(bp, &o->raw))
2436 static int bnx2x_mcast_enqueue_cmd(struct bnx2x *bp,
2437 struct bnx2x_mcast_obj *o,
2438 struct bnx2x_mcast_ramrod_params *p,
2439 enum bnx2x_mcast_cmd cmd)
2442 struct bnx2x_pending_mcast_cmd *new_cmd;
2443 struct bnx2x_mcast_mac_elem *cur_mac = NULL;
2444 struct bnx2x_mcast_list_elem *pos;
2445 int macs_list_len = ((cmd == BNX2X_MCAST_CMD_ADD) ?
2446 p->mcast_list_len : 0);
2448 /* If the command is empty ("handle pending commands only"), break */
2449 if (!p->mcast_list_len)
2452 total_sz = sizeof(*new_cmd) +
2453 macs_list_len * sizeof(struct bnx2x_mcast_mac_elem);
2455 /* Add mcast is called under spin_lock, thus calling with GFP_ATOMIC */
2456 new_cmd = kzalloc(total_sz, GFP_ATOMIC);
2461 DP(BNX2X_MSG_SP, "About to enqueue a new %d command. macs_list_len=%d\n",
2462 cmd, macs_list_len);
2464 INIT_LIST_HEAD(&new_cmd->data.macs_head);
2466 new_cmd->type = cmd;
2467 new_cmd->done = false;
2470 case BNX2X_MCAST_CMD_ADD:
2471 cur_mac = (struct bnx2x_mcast_mac_elem *)
2472 ((u8 *)new_cmd + sizeof(*new_cmd));
2474 /* Push the MACs of the current command into the pendig command
2477 list_for_each_entry(pos, &p->mcast_list, link) {
2478 memcpy(cur_mac->mac, pos->mac, ETH_ALEN);
2479 list_add_tail(&cur_mac->link, &new_cmd->data.macs_head);
2485 case BNX2X_MCAST_CMD_DEL:
2486 new_cmd->data.macs_num = p->mcast_list_len;
2489 case BNX2X_MCAST_CMD_RESTORE:
2490 new_cmd->data.next_bin = 0;
2495 BNX2X_ERR("Unknown command: %d\n", cmd);
2499 /* Push the new pending command to the tail of the pending list: FIFO */
2500 list_add_tail(&new_cmd->link, &o->pending_cmds_head);
2508 * bnx2x_mcast_get_next_bin - get the next set bin (index)
2511 * @last: index to start looking from (including)
2513 * returns the next found (set) bin or a negative value if none is found.
2515 static inline int bnx2x_mcast_get_next_bin(struct bnx2x_mcast_obj *o, int last)
2517 int i, j, inner_start = last % BIT_VEC64_ELEM_SZ;
2519 for (i = last / BIT_VEC64_ELEM_SZ; i < BNX2X_MCAST_VEC_SZ; i++) {
2520 if (o->registry.aprox_match.vec[i])
2521 for (j = inner_start; j < BIT_VEC64_ELEM_SZ; j++) {
2522 int cur_bit = j + BIT_VEC64_ELEM_SZ * i;
2523 if (BIT_VEC64_TEST_BIT(o->registry.aprox_match.
2536 * bnx2x_mcast_clear_first_bin - find the first set bin and clear it
2540 * returns the index of the found bin or -1 if none is found
2542 static inline int bnx2x_mcast_clear_first_bin(struct bnx2x_mcast_obj *o)
2544 int cur_bit = bnx2x_mcast_get_next_bin(o, 0);
2547 BIT_VEC64_CLEAR_BIT(o->registry.aprox_match.vec, cur_bit);
2552 static inline u8 bnx2x_mcast_get_rx_tx_flag(struct bnx2x_mcast_obj *o)
2554 struct bnx2x_raw_obj *raw = &o->raw;
2557 if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) ||
2558 (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
2559 rx_tx_flag |= ETH_MULTICAST_RULES_CMD_TX_CMD;
2561 if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) ||
2562 (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
2563 rx_tx_flag |= ETH_MULTICAST_RULES_CMD_RX_CMD;
2568 static void bnx2x_mcast_set_one_rule_e2(struct bnx2x *bp,
2569 struct bnx2x_mcast_obj *o, int idx,
2570 union bnx2x_mcast_config_data *cfg_data,
2571 enum bnx2x_mcast_cmd cmd)
2573 struct bnx2x_raw_obj *r = &o->raw;
2574 struct eth_multicast_rules_ramrod_data *data =
2575 (struct eth_multicast_rules_ramrod_data *)(r->rdata);
2576 u8 func_id = r->func_id;
2577 u8 rx_tx_add_flag = bnx2x_mcast_get_rx_tx_flag(o);
2580 if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE))
2581 rx_tx_add_flag |= ETH_MULTICAST_RULES_CMD_IS_ADD;
2583 data->rules[idx].cmd_general_data |= rx_tx_add_flag;
2585 /* Get a bin and update a bins' vector */
2587 case BNX2X_MCAST_CMD_ADD:
2588 bin = bnx2x_mcast_bin_from_mac(cfg_data->mac);
2589 BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bin);
2592 case BNX2X_MCAST_CMD_DEL:
2593 /* If there were no more bins to clear
2594 * (bnx2x_mcast_clear_first_bin() returns -1) then we would
2595 * clear any (0xff) bin.
2596 * See bnx2x_mcast_validate_e2() for explanation when it may
2599 bin = bnx2x_mcast_clear_first_bin(o);
2602 case BNX2X_MCAST_CMD_RESTORE:
2603 bin = cfg_data->bin;
2607 BNX2X_ERR("Unknown command: %d\n", cmd);
2611 DP(BNX2X_MSG_SP, "%s bin %d\n",
2612 ((rx_tx_add_flag & ETH_MULTICAST_RULES_CMD_IS_ADD) ?
2613 "Setting" : "Clearing"), bin);
2615 data->rules[idx].bin_id = (u8)bin;
2616 data->rules[idx].func_id = func_id;
2617 data->rules[idx].engine_id = o->engine_id;
2621 * bnx2x_mcast_handle_restore_cmd_e2 - restore configuration from the registry
2623 * @bp: device handle
2625 * @start_bin: index in the registry to start from (including)
2626 * @rdata_idx: index in the ramrod data to start from
2628 * returns last handled bin index or -1 if all bins have been handled
2630 static inline int bnx2x_mcast_handle_restore_cmd_e2(
2631 struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_bin,
2634 int cur_bin, cnt = *rdata_idx;
2635 union bnx2x_mcast_config_data cfg_data = {NULL};
2637 /* go through the registry and configure the bins from it */
2638 for (cur_bin = bnx2x_mcast_get_next_bin(o, start_bin); cur_bin >= 0;
2639 cur_bin = bnx2x_mcast_get_next_bin(o, cur_bin + 1)) {
2641 cfg_data.bin = (u8)cur_bin;
2642 o->set_one_rule(bp, o, cnt, &cfg_data,
2643 BNX2X_MCAST_CMD_RESTORE);
2647 DP(BNX2X_MSG_SP, "About to configure a bin %d\n", cur_bin);
2649 /* Break if we reached the maximum number
2652 if (cnt >= o->max_cmd_len)
2661 static inline void bnx2x_mcast_hdl_pending_add_e2(struct bnx2x *bp,
2662 struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos,
2665 struct bnx2x_mcast_mac_elem *pmac_pos, *pmac_pos_n;
2666 int cnt = *line_idx;
2667 union bnx2x_mcast_config_data cfg_data = {NULL};
2669 list_for_each_entry_safe(pmac_pos, pmac_pos_n, &cmd_pos->data.macs_head,
2672 cfg_data.mac = &pmac_pos->mac[0];
2673 o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type);
2677 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
2680 list_del(&pmac_pos->link);
2682 /* Break if we reached the maximum number
2685 if (cnt >= o->max_cmd_len)
2691 /* if no more MACs to configure - we are done */
2692 if (list_empty(&cmd_pos->data.macs_head))
2693 cmd_pos->done = true;
2696 static inline void bnx2x_mcast_hdl_pending_del_e2(struct bnx2x *bp,
2697 struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos,
2700 int cnt = *line_idx;
2702 while (cmd_pos->data.macs_num) {
2703 o->set_one_rule(bp, o, cnt, NULL, cmd_pos->type);
2707 cmd_pos->data.macs_num--;
2709 DP(BNX2X_MSG_SP, "Deleting MAC. %d left,cnt is %d\n",
2710 cmd_pos->data.macs_num, cnt);
2712 /* Break if we reached the maximum
2715 if (cnt >= o->max_cmd_len)
2721 /* If we cleared all bins - we are done */
2722 if (!cmd_pos->data.macs_num)
2723 cmd_pos->done = true;
2726 static inline void bnx2x_mcast_hdl_pending_restore_e2(struct bnx2x *bp,
2727 struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos,
2730 cmd_pos->data.next_bin = o->hdl_restore(bp, o, cmd_pos->data.next_bin,
2733 if (cmd_pos->data.next_bin < 0)
2734 /* If o->set_restore returned -1 we are done */
2735 cmd_pos->done = true;
2737 /* Start from the next bin next time */
2738 cmd_pos->data.next_bin++;
2741 static inline int bnx2x_mcast_handle_pending_cmds_e2(struct bnx2x *bp,
2742 struct bnx2x_mcast_ramrod_params *p)
2744 struct bnx2x_pending_mcast_cmd *cmd_pos, *cmd_pos_n;
2746 struct bnx2x_mcast_obj *o = p->mcast_obj;
2748 list_for_each_entry_safe(cmd_pos, cmd_pos_n, &o->pending_cmds_head,
2750 switch (cmd_pos->type) {
2751 case BNX2X_MCAST_CMD_ADD:
2752 bnx2x_mcast_hdl_pending_add_e2(bp, o, cmd_pos, &cnt);
2755 case BNX2X_MCAST_CMD_DEL:
2756 bnx2x_mcast_hdl_pending_del_e2(bp, o, cmd_pos, &cnt);
2759 case BNX2X_MCAST_CMD_RESTORE:
2760 bnx2x_mcast_hdl_pending_restore_e2(bp, o, cmd_pos,
2765 BNX2X_ERR("Unknown command: %d\n", cmd_pos->type);
2769 /* If the command has been completed - remove it from the list
2770 * and free the memory
2772 if (cmd_pos->done) {
2773 list_del(&cmd_pos->link);
2777 /* Break if we reached the maximum number of rules */
2778 if (cnt >= o->max_cmd_len)
2785 static inline void bnx2x_mcast_hdl_add(struct bnx2x *bp,
2786 struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p,
2789 struct bnx2x_mcast_list_elem *mlist_pos;
2790 union bnx2x_mcast_config_data cfg_data = {NULL};
2791 int cnt = *line_idx;
2793 list_for_each_entry(mlist_pos, &p->mcast_list, link) {
2794 cfg_data.mac = mlist_pos->mac;
2795 o->set_one_rule(bp, o, cnt, &cfg_data, BNX2X_MCAST_CMD_ADD);
2799 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
2806 static inline void bnx2x_mcast_hdl_del(struct bnx2x *bp,
2807 struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p,
2810 int cnt = *line_idx, i;
2812 for (i = 0; i < p->mcast_list_len; i++) {
2813 o->set_one_rule(bp, o, cnt, NULL, BNX2X_MCAST_CMD_DEL);
2817 DP(BNX2X_MSG_SP, "Deleting MAC. %d left\n",
2818 p->mcast_list_len - i - 1);
2825 * bnx2x_mcast_handle_current_cmd -
2827 * @bp: device handle
2830 * @start_cnt: first line in the ramrod data that may be used
2832 * This function is called iff there is enough place for the current command in
2834 * Returns number of lines filled in the ramrod data in total.
2836 static inline int bnx2x_mcast_handle_current_cmd(struct bnx2x *bp,
2837 struct bnx2x_mcast_ramrod_params *p,
2838 enum bnx2x_mcast_cmd cmd,
2841 struct bnx2x_mcast_obj *o = p->mcast_obj;
2842 int cnt = start_cnt;
2844 DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len);
2847 case BNX2X_MCAST_CMD_ADD:
2848 bnx2x_mcast_hdl_add(bp, o, p, &cnt);
2851 case BNX2X_MCAST_CMD_DEL:
2852 bnx2x_mcast_hdl_del(bp, o, p, &cnt);
2855 case BNX2X_MCAST_CMD_RESTORE:
2856 o->hdl_restore(bp, o, 0, &cnt);
2860 BNX2X_ERR("Unknown command: %d\n", cmd);
2864 /* The current command has been handled */
2865 p->mcast_list_len = 0;
2870 static int bnx2x_mcast_validate_e2(struct bnx2x *bp,
2871 struct bnx2x_mcast_ramrod_params *p,
2872 enum bnx2x_mcast_cmd cmd)
2874 struct bnx2x_mcast_obj *o = p->mcast_obj;
2875 int reg_sz = o->get_registry_size(o);
2878 /* DEL command deletes all currently configured MACs */
2879 case BNX2X_MCAST_CMD_DEL:
2880 o->set_registry_size(o, 0);
2883 /* RESTORE command will restore the entire multicast configuration */
2884 case BNX2X_MCAST_CMD_RESTORE:
2885 /* Here we set the approximate amount of work to do, which in
2886 * fact may be only less as some MACs in postponed ADD
2887 * command(s) scheduled before this command may fall into
2888 * the same bin and the actual number of bins set in the
2889 * registry would be less than we estimated here. See
2890 * bnx2x_mcast_set_one_rule_e2() for further details.
2892 p->mcast_list_len = reg_sz;
2895 case BNX2X_MCAST_CMD_ADD:
2896 case BNX2X_MCAST_CMD_CONT:
2897 /* Here we assume that all new MACs will fall into new bins.
2898 * However we will correct the real registry size after we
2899 * handle all pending commands.
2901 o->set_registry_size(o, reg_sz + p->mcast_list_len);
2905 BNX2X_ERR("Unknown command: %d\n", cmd);
2910 /* Increase the total number of MACs pending to be configured */
2911 o->total_pending_num += p->mcast_list_len;
2916 static void bnx2x_mcast_revert_e2(struct bnx2x *bp,
2917 struct bnx2x_mcast_ramrod_params *p,
2920 struct bnx2x_mcast_obj *o = p->mcast_obj;
2922 o->set_registry_size(o, old_num_bins);
2923 o->total_pending_num -= p->mcast_list_len;
2927 * bnx2x_mcast_set_rdata_hdr_e2 - sets a header values
2929 * @bp: device handle
2931 * @len: number of rules to handle
2933 static inline void bnx2x_mcast_set_rdata_hdr_e2(struct bnx2x *bp,
2934 struct bnx2x_mcast_ramrod_params *p,
2937 struct bnx2x_raw_obj *r = &p->mcast_obj->raw;
2938 struct eth_multicast_rules_ramrod_data *data =
2939 (struct eth_multicast_rules_ramrod_data *)(r->rdata);
2941 data->header.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
2942 (BNX2X_FILTER_MCAST_PENDING <<
2943 BNX2X_SWCID_SHIFT));
2944 data->header.rule_cnt = len;
2948 * bnx2x_mcast_refresh_registry_e2 - recalculate the actual number of set bins
2950 * @bp: device handle
2953 * Recalculate the actual number of set bins in the registry using Brian
2954 * Kernighan's algorithm: it's execution complexity is as a number of set bins.
2956 * returns 0 for the compliance with bnx2x_mcast_refresh_registry_e1().
2958 static inline int bnx2x_mcast_refresh_registry_e2(struct bnx2x *bp,
2959 struct bnx2x_mcast_obj *o)
2964 for (i = 0; i < BNX2X_MCAST_VEC_SZ; i++) {
2965 elem = o->registry.aprox_match.vec[i];
2970 o->set_registry_size(o, cnt);
2975 static int bnx2x_mcast_setup_e2(struct bnx2x *bp,
2976 struct bnx2x_mcast_ramrod_params *p,
2977 enum bnx2x_mcast_cmd cmd)
2979 struct bnx2x_raw_obj *raw = &p->mcast_obj->raw;
2980 struct bnx2x_mcast_obj *o = p->mcast_obj;
2981 struct eth_multicast_rules_ramrod_data *data =
2982 (struct eth_multicast_rules_ramrod_data *)(raw->rdata);
2985 /* Reset the ramrod data buffer */
2986 memset(data, 0, sizeof(*data));
2988 cnt = bnx2x_mcast_handle_pending_cmds_e2(bp, p);
2990 /* If there are no more pending commands - clear SCHEDULED state */
2991 if (list_empty(&o->pending_cmds_head))
2994 /* The below may be true iff there was enough room in ramrod
2995 * data for all pending commands and for the current
2996 * command. Otherwise the current command would have been added
2997 * to the pending commands and p->mcast_list_len would have been
3000 if (p->mcast_list_len > 0)
3001 cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, cnt);
3003 /* We've pulled out some MACs - update the total number of
3006 o->total_pending_num -= cnt;
3009 WARN_ON(o->total_pending_num < 0);
3010 WARN_ON(cnt > o->max_cmd_len);
3012 bnx2x_mcast_set_rdata_hdr_e2(bp, p, (u8)cnt);
3014 /* Update a registry size if there are no more pending operations.
3016 * We don't want to change the value of the registry size if there are
3017 * pending operations because we want it to always be equal to the
3018 * exact or the approximate number (see bnx2x_mcast_validate_e2()) of
3019 * set bins after the last requested operation in order to properly
3020 * evaluate the size of the next DEL/RESTORE operation.
3022 * Note that we update the registry itself during command(s) handling
3023 * - see bnx2x_mcast_set_one_rule_e2(). That's because for 57712 we
3024 * aggregate multiple commands (ADD/DEL/RESTORE) into one ramrod but
3025 * with a limited amount of update commands (per MAC/bin) and we don't
3026 * know in this scope what the actual state of bins configuration is
3027 * going to be after this ramrod.
3029 if (!o->total_pending_num)
3030 bnx2x_mcast_refresh_registry_e2(bp, o);
3033 * If CLEAR_ONLY was requested - don't send a ramrod and clear
3034 * RAMROD_PENDING status immediately.
3036 if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3037 raw->clear_pending(raw);
3041 * No need for an explicit memory barrier here as long we would
3042 * need to ensure the ordering of writing to the SPQ element
3043 * and updating of the SPQ producer which involves a memory
3044 * read and we will have to put a full memory barrier there
3045 * (inside bnx2x_sp_post()).
3049 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_MULTICAST_RULES,
3050 raw->cid, U64_HI(raw->rdata_mapping),
3051 U64_LO(raw->rdata_mapping),
3052 ETH_CONNECTION_TYPE);
3056 /* Ramrod completion is pending */
3061 static int bnx2x_mcast_validate_e1h(struct bnx2x *bp,
3062 struct bnx2x_mcast_ramrod_params *p,
3063 enum bnx2x_mcast_cmd cmd)
3065 /* Mark, that there is a work to do */
3066 if ((cmd == BNX2X_MCAST_CMD_DEL) || (cmd == BNX2X_MCAST_CMD_RESTORE))
3067 p->mcast_list_len = 1;
3072 static void bnx2x_mcast_revert_e1h(struct bnx2x *bp,
3073 struct bnx2x_mcast_ramrod_params *p,
3079 #define BNX2X_57711_SET_MC_FILTER(filter, bit) \
3081 (filter)[(bit) >> 5] |= (1 << ((bit) & 0x1f)); \
3084 static inline void bnx2x_mcast_hdl_add_e1h(struct bnx2x *bp,
3085 struct bnx2x_mcast_obj *o,
3086 struct bnx2x_mcast_ramrod_params *p,
3089 struct bnx2x_mcast_list_elem *mlist_pos;
3092 list_for_each_entry(mlist_pos, &p->mcast_list, link) {
3093 bit = bnx2x_mcast_bin_from_mac(mlist_pos->mac);
3094 BNX2X_57711_SET_MC_FILTER(mc_filter, bit);
3096 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC, bin %d\n",
3097 mlist_pos->mac, bit);
3099 /* bookkeeping... */
3100 BIT_VEC64_SET_BIT(o->registry.aprox_match.vec,
3105 static inline void bnx2x_mcast_hdl_restore_e1h(struct bnx2x *bp,
3106 struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p,
3111 for (bit = bnx2x_mcast_get_next_bin(o, 0);
3113 bit = bnx2x_mcast_get_next_bin(o, bit + 1)) {
3114 BNX2X_57711_SET_MC_FILTER(mc_filter, bit);
3115 DP(BNX2X_MSG_SP, "About to set bin %d\n", bit);
3119 /* On 57711 we write the multicast MACs' aproximate match
3120 * table by directly into the TSTORM's internal RAM. So we don't
3121 * really need to handle any tricks to make it work.
3123 static int bnx2x_mcast_setup_e1h(struct bnx2x *bp,
3124 struct bnx2x_mcast_ramrod_params *p,
3125 enum bnx2x_mcast_cmd cmd)
3128 struct bnx2x_mcast_obj *o = p->mcast_obj;
3129 struct bnx2x_raw_obj *r = &o->raw;
3131 /* If CLEAR_ONLY has been requested - clear the registry
3132 * and clear a pending bit.
3134 if (!test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3135 u32 mc_filter[MC_HASH_SIZE] = {0};
3137 /* Set the multicast filter bits before writing it into
3138 * the internal memory.
3141 case BNX2X_MCAST_CMD_ADD:
3142 bnx2x_mcast_hdl_add_e1h(bp, o, p, mc_filter);
3145 case BNX2X_MCAST_CMD_DEL:
3147 "Invalidating multicast MACs configuration\n");
3149 /* clear the registry */
3150 memset(o->registry.aprox_match.vec, 0,
3151 sizeof(o->registry.aprox_match.vec));
3154 case BNX2X_MCAST_CMD_RESTORE:
3155 bnx2x_mcast_hdl_restore_e1h(bp, o, p, mc_filter);
3159 BNX2X_ERR("Unknown command: %d\n", cmd);
3163 /* Set the mcast filter in the internal memory */
3164 for (i = 0; i < MC_HASH_SIZE; i++)
3165 REG_WR(bp, MC_HASH_OFFSET(bp, i), mc_filter[i]);
3167 /* clear the registry */
3168 memset(o->registry.aprox_match.vec, 0,
3169 sizeof(o->registry.aprox_match.vec));
3172 r->clear_pending(r);
3177 static int bnx2x_mcast_validate_e1(struct bnx2x *bp,
3178 struct bnx2x_mcast_ramrod_params *p,
3179 enum bnx2x_mcast_cmd cmd)
3181 struct bnx2x_mcast_obj *o = p->mcast_obj;
3182 int reg_sz = o->get_registry_size(o);
3185 /* DEL command deletes all currently configured MACs */
3186 case BNX2X_MCAST_CMD_DEL:
3187 o->set_registry_size(o, 0);
3190 /* RESTORE command will restore the entire multicast configuration */
3191 case BNX2X_MCAST_CMD_RESTORE:
3192 p->mcast_list_len = reg_sz;
3193 DP(BNX2X_MSG_SP, "Command %d, p->mcast_list_len=%d\n",
3194 cmd, p->mcast_list_len);
3197 case BNX2X_MCAST_CMD_ADD:
3198 case BNX2X_MCAST_CMD_CONT:
3199 /* Multicast MACs on 57710 are configured as unicast MACs and
3200 * there is only a limited number of CAM entries for that
3203 if (p->mcast_list_len > o->max_cmd_len) {
3204 BNX2X_ERR("Can't configure more than %d multicast MACs on 57710\n",
3208 /* Every configured MAC should be cleared if DEL command is
3209 * called. Only the last ADD command is relevant as long as
3210 * every ADD commands overrides the previous configuration.
3212 DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len);
3213 if (p->mcast_list_len > 0)
3214 o->set_registry_size(o, p->mcast_list_len);
3219 BNX2X_ERR("Unknown command: %d\n", cmd);
3224 /* We want to ensure that commands are executed one by one for 57710.
3225 * Therefore each none-empty command will consume o->max_cmd_len.
3227 if (p->mcast_list_len)
3228 o->total_pending_num += o->max_cmd_len;
3233 static void bnx2x_mcast_revert_e1(struct bnx2x *bp,
3234 struct bnx2x_mcast_ramrod_params *p,
3237 struct bnx2x_mcast_obj *o = p->mcast_obj;
3239 o->set_registry_size(o, old_num_macs);
3241 /* If current command hasn't been handled yet and we are
3242 * here means that it's meant to be dropped and we have to
3243 * update the number of outstandling MACs accordingly.
3245 if (p->mcast_list_len)
3246 o->total_pending_num -= o->max_cmd_len;
3249 static void bnx2x_mcast_set_one_rule_e1(struct bnx2x *bp,
3250 struct bnx2x_mcast_obj *o, int idx,
3251 union bnx2x_mcast_config_data *cfg_data,
3252 enum bnx2x_mcast_cmd cmd)
3254 struct bnx2x_raw_obj *r = &o->raw;
3255 struct mac_configuration_cmd *data =
3256 (struct mac_configuration_cmd *)(r->rdata);
3259 if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE)) {
3260 bnx2x_set_fw_mac_addr(&data->config_table[idx].msb_mac_addr,
3261 &data->config_table[idx].middle_mac_addr,
3262 &data->config_table[idx].lsb_mac_addr,
3265 data->config_table[idx].vlan_id = 0;
3266 data->config_table[idx].pf_id = r->func_id;
3267 data->config_table[idx].clients_bit_vector =
3268 cpu_to_le32(1 << r->cl_id);
3270 SET_FLAG(data->config_table[idx].flags,
3271 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
3272 T_ETH_MAC_COMMAND_SET);
3277 * bnx2x_mcast_set_rdata_hdr_e1 - set header values in mac_configuration_cmd
3279 * @bp: device handle
3281 * @len: number of rules to handle
3283 static inline void bnx2x_mcast_set_rdata_hdr_e1(struct bnx2x *bp,
3284 struct bnx2x_mcast_ramrod_params *p,
3287 struct bnx2x_raw_obj *r = &p->mcast_obj->raw;
3288 struct mac_configuration_cmd *data =
3289 (struct mac_configuration_cmd *)(r->rdata);
3291 u8 offset = (CHIP_REV_IS_SLOW(bp) ?
3292 BNX2X_MAX_EMUL_MULTI*(1 + r->func_id) :
3293 BNX2X_MAX_MULTICAST*(1 + r->func_id));
3295 data->hdr.offset = offset;
3296 data->hdr.client_id = cpu_to_le16(0xff);
3297 data->hdr.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
3298 (BNX2X_FILTER_MCAST_PENDING <<
3299 BNX2X_SWCID_SHIFT));
3300 data->hdr.length = len;
3304 * bnx2x_mcast_handle_restore_cmd_e1 - restore command for 57710
3306 * @bp: device handle
3308 * @start_idx: index in the registry to start from
3309 * @rdata_idx: index in the ramrod data to start from
3311 * restore command for 57710 is like all other commands - always a stand alone
3312 * command - start_idx and rdata_idx will always be 0. This function will always
3314 * returns -1 to comply with 57712 variant.
3316 static inline int bnx2x_mcast_handle_restore_cmd_e1(
3317 struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_idx,
3320 struct bnx2x_mcast_mac_elem *elem;
3322 union bnx2x_mcast_config_data cfg_data = {NULL};
3324 /* go through the registry and configure the MACs from it. */
3325 list_for_each_entry(elem, &o->registry.exact_match.macs, link) {
3326 cfg_data.mac = &elem->mac[0];
3327 o->set_one_rule(bp, o, i, &cfg_data, BNX2X_MCAST_CMD_RESTORE);
3331 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
3341 static inline int bnx2x_mcast_handle_pending_cmds_e1(
3342 struct bnx2x *bp, struct bnx2x_mcast_ramrod_params *p)
3344 struct bnx2x_pending_mcast_cmd *cmd_pos;
3345 struct bnx2x_mcast_mac_elem *pmac_pos;
3346 struct bnx2x_mcast_obj *o = p->mcast_obj;
3347 union bnx2x_mcast_config_data cfg_data = {NULL};
3351 /* If nothing to be done - return */
3352 if (list_empty(&o->pending_cmds_head))
3355 /* Handle the first command */
3356 cmd_pos = list_first_entry(&o->pending_cmds_head,
3357 struct bnx2x_pending_mcast_cmd, link);
3359 switch (cmd_pos->type) {
3360 case BNX2X_MCAST_CMD_ADD:
3361 list_for_each_entry(pmac_pos, &cmd_pos->data.macs_head, link) {
3362 cfg_data.mac = &pmac_pos->mac[0];
3363 o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type);
3367 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
3372 case BNX2X_MCAST_CMD_DEL:
3373 cnt = cmd_pos->data.macs_num;
3374 DP(BNX2X_MSG_SP, "About to delete %d multicast MACs\n", cnt);
3377 case BNX2X_MCAST_CMD_RESTORE:
3378 o->hdl_restore(bp, o, 0, &cnt);
3382 BNX2X_ERR("Unknown command: %d\n", cmd_pos->type);
3386 list_del(&cmd_pos->link);
3393 * bnx2x_get_fw_mac_addr - revert the bnx2x_set_fw_mac_addr().
3400 static inline void bnx2x_get_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
3401 __le16 *fw_lo, u8 *mac)
3403 mac[1] = ((u8 *)fw_hi)[0];
3404 mac[0] = ((u8 *)fw_hi)[1];
3405 mac[3] = ((u8 *)fw_mid)[0];
3406 mac[2] = ((u8 *)fw_mid)[1];
3407 mac[5] = ((u8 *)fw_lo)[0];
3408 mac[4] = ((u8 *)fw_lo)[1];
3412 * bnx2x_mcast_refresh_registry_e1 -
3414 * @bp: device handle
3417 * Check the ramrod data first entry flag to see if it's a DELETE or ADD command
3418 * and update the registry correspondingly: if ADD - allocate a memory and add
3419 * the entries to the registry (list), if DELETE - clear the registry and free
3422 static inline int bnx2x_mcast_refresh_registry_e1(struct bnx2x *bp,
3423 struct bnx2x_mcast_obj *o)
3425 struct bnx2x_raw_obj *raw = &o->raw;
3426 struct bnx2x_mcast_mac_elem *elem;
3427 struct mac_configuration_cmd *data =
3428 (struct mac_configuration_cmd *)(raw->rdata);
3430 /* If first entry contains a SET bit - the command was ADD,
3431 * otherwise - DEL_ALL
3433 if (GET_FLAG(data->config_table[0].flags,
3434 MAC_CONFIGURATION_ENTRY_ACTION_TYPE)) {
3435 int i, len = data->hdr.length;
3437 /* Break if it was a RESTORE command */
3438 if (!list_empty(&o->registry.exact_match.macs))
3441 elem = kcalloc(len, sizeof(*elem), GFP_ATOMIC);
3443 BNX2X_ERR("Failed to allocate registry memory\n");
3447 for (i = 0; i < len; i++, elem++) {
3448 bnx2x_get_fw_mac_addr(
3449 &data->config_table[i].msb_mac_addr,
3450 &data->config_table[i].middle_mac_addr,
3451 &data->config_table[i].lsb_mac_addr,
3453 DP(BNX2X_MSG_SP, "Adding registry entry for [%pM]\n",
3455 list_add_tail(&elem->link,
3456 &o->registry.exact_match.macs);
3459 elem = list_first_entry(&o->registry.exact_match.macs,
3460 struct bnx2x_mcast_mac_elem, link);
3461 DP(BNX2X_MSG_SP, "Deleting a registry\n");
3463 INIT_LIST_HEAD(&o->registry.exact_match.macs);
3469 static int bnx2x_mcast_setup_e1(struct bnx2x *bp,
3470 struct bnx2x_mcast_ramrod_params *p,
3471 enum bnx2x_mcast_cmd cmd)
3473 struct bnx2x_mcast_obj *o = p->mcast_obj;
3474 struct bnx2x_raw_obj *raw = &o->raw;
3475 struct mac_configuration_cmd *data =
3476 (struct mac_configuration_cmd *)(raw->rdata);
3479 /* Reset the ramrod data buffer */
3480 memset(data, 0, sizeof(*data));
3482 /* First set all entries as invalid */
3483 for (i = 0; i < o->max_cmd_len ; i++)
3484 SET_FLAG(data->config_table[i].flags,
3485 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
3486 T_ETH_MAC_COMMAND_INVALIDATE);
3488 /* Handle pending commands first */
3489 cnt = bnx2x_mcast_handle_pending_cmds_e1(bp, p);
3491 /* If there are no more pending commands - clear SCHEDULED state */
3492 if (list_empty(&o->pending_cmds_head))
3495 /* The below may be true iff there were no pending commands */
3497 cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, 0);
3499 /* For 57710 every command has o->max_cmd_len length to ensure that
3500 * commands are done one at a time.
3502 o->total_pending_num -= o->max_cmd_len;
3506 WARN_ON(cnt > o->max_cmd_len);
3508 /* Set ramrod header (in particular, a number of entries to update) */
3509 bnx2x_mcast_set_rdata_hdr_e1(bp, p, (u8)cnt);
3511 /* update a registry: we need the registry contents to be always up
3512 * to date in order to be able to execute a RESTORE opcode. Here
3513 * we use the fact that for 57710 we sent one command at a time
3514 * hence we may take the registry update out of the command handling
3515 * and do it in a simpler way here.
3517 rc = bnx2x_mcast_refresh_registry_e1(bp, o);
3522 * If CLEAR_ONLY was requested - don't send a ramrod and clear
3523 * RAMROD_PENDING status immediately.
3525 if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3526 raw->clear_pending(raw);
3530 * No need for an explicit memory barrier here as long we would
3531 * need to ensure the ordering of writing to the SPQ element
3532 * and updating of the SPQ producer which involves a memory
3533 * read and we will have to put a full memory barrier there
3534 * (inside bnx2x_sp_post()).
3538 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, raw->cid,
3539 U64_HI(raw->rdata_mapping),
3540 U64_LO(raw->rdata_mapping),
3541 ETH_CONNECTION_TYPE);
3545 /* Ramrod completion is pending */
3551 static int bnx2x_mcast_get_registry_size_exact(struct bnx2x_mcast_obj *o)
3553 return o->registry.exact_match.num_macs_set;
3556 static int bnx2x_mcast_get_registry_size_aprox(struct bnx2x_mcast_obj *o)
3558 return o->registry.aprox_match.num_bins_set;
3561 static void bnx2x_mcast_set_registry_size_exact(struct bnx2x_mcast_obj *o,
3564 o->registry.exact_match.num_macs_set = n;
3567 static void bnx2x_mcast_set_registry_size_aprox(struct bnx2x_mcast_obj *o,
3570 o->registry.aprox_match.num_bins_set = n;
3573 int bnx2x_config_mcast(struct bnx2x *bp,
3574 struct bnx2x_mcast_ramrod_params *p,
3575 enum bnx2x_mcast_cmd cmd)
3577 struct bnx2x_mcast_obj *o = p->mcast_obj;
3578 struct bnx2x_raw_obj *r = &o->raw;
3579 int rc = 0, old_reg_size;
3581 /* This is needed to recover number of currently configured mcast macs
3582 * in case of failure.
3584 old_reg_size = o->get_registry_size(o);
3586 /* Do some calculations and checks */
3587 rc = o->validate(bp, p, cmd);
3591 /* Return if there is no work to do */
3592 if ((!p->mcast_list_len) && (!o->check_sched(o)))
3595 DP(BNX2X_MSG_SP, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\n",
3596 o->total_pending_num, p->mcast_list_len, o->max_cmd_len);
3598 /* Enqueue the current command to the pending list if we can't complete
3599 * it in the current iteration
3601 if (r->check_pending(r) ||
3602 ((o->max_cmd_len > 0) && (o->total_pending_num > o->max_cmd_len))) {
3603 rc = o->enqueue_cmd(bp, p->mcast_obj, p, cmd);
3607 /* As long as the current command is in a command list we
3608 * don't need to handle it separately.
3610 p->mcast_list_len = 0;
3613 if (!r->check_pending(r)) {
3615 /* Set 'pending' state */
3618 /* Configure the new classification in the chip */
3619 rc = o->config_mcast(bp, p, cmd);
3623 /* Wait for a ramrod completion if was requested */
3624 if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags))
3625 rc = o->wait_comp(bp, o);
3631 r->clear_pending(r);
3634 o->revert(bp, p, old_reg_size);
3639 static void bnx2x_mcast_clear_sched(struct bnx2x_mcast_obj *o)
3641 smp_mb__before_clear_bit();
3642 clear_bit(o->sched_state, o->raw.pstate);
3643 smp_mb__after_clear_bit();
3646 static void bnx2x_mcast_set_sched(struct bnx2x_mcast_obj *o)
3648 smp_mb__before_clear_bit();
3649 set_bit(o->sched_state, o->raw.pstate);
3650 smp_mb__after_clear_bit();
3653 static bool bnx2x_mcast_check_sched(struct bnx2x_mcast_obj *o)
3655 return !!test_bit(o->sched_state, o->raw.pstate);
3658 static bool bnx2x_mcast_check_pending(struct bnx2x_mcast_obj *o)
3660 return o->raw.check_pending(&o->raw) || o->check_sched(o);
3663 void bnx2x_init_mcast_obj(struct bnx2x *bp,
3664 struct bnx2x_mcast_obj *mcast_obj,
3665 u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
3666 u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
3667 int state, unsigned long *pstate, bnx2x_obj_type type)
3669 memset(mcast_obj, 0, sizeof(*mcast_obj));
3671 bnx2x_init_raw_obj(&mcast_obj->raw, mcast_cl_id, mcast_cid, func_id,
3672 rdata, rdata_mapping, state, pstate, type);
3674 mcast_obj->engine_id = engine_id;
3676 INIT_LIST_HEAD(&mcast_obj->pending_cmds_head);
3678 mcast_obj->sched_state = BNX2X_FILTER_MCAST_SCHED;
3679 mcast_obj->check_sched = bnx2x_mcast_check_sched;
3680 mcast_obj->set_sched = bnx2x_mcast_set_sched;
3681 mcast_obj->clear_sched = bnx2x_mcast_clear_sched;
3683 if (CHIP_IS_E1(bp)) {
3684 mcast_obj->config_mcast = bnx2x_mcast_setup_e1;
3685 mcast_obj->enqueue_cmd = bnx2x_mcast_enqueue_cmd;
3686 mcast_obj->hdl_restore =
3687 bnx2x_mcast_handle_restore_cmd_e1;
3688 mcast_obj->check_pending = bnx2x_mcast_check_pending;
3690 if (CHIP_REV_IS_SLOW(bp))
3691 mcast_obj->max_cmd_len = BNX2X_MAX_EMUL_MULTI;
3693 mcast_obj->max_cmd_len = BNX2X_MAX_MULTICAST;
3695 mcast_obj->wait_comp = bnx2x_mcast_wait;
3696 mcast_obj->set_one_rule = bnx2x_mcast_set_one_rule_e1;
3697 mcast_obj->validate = bnx2x_mcast_validate_e1;
3698 mcast_obj->revert = bnx2x_mcast_revert_e1;
3699 mcast_obj->get_registry_size =
3700 bnx2x_mcast_get_registry_size_exact;
3701 mcast_obj->set_registry_size =
3702 bnx2x_mcast_set_registry_size_exact;
3704 /* 57710 is the only chip that uses the exact match for mcast
3707 INIT_LIST_HEAD(&mcast_obj->registry.exact_match.macs);
3709 } else if (CHIP_IS_E1H(bp)) {
3710 mcast_obj->config_mcast = bnx2x_mcast_setup_e1h;
3711 mcast_obj->enqueue_cmd = NULL;
3712 mcast_obj->hdl_restore = NULL;
3713 mcast_obj->check_pending = bnx2x_mcast_check_pending;
3715 /* 57711 doesn't send a ramrod, so it has unlimited credit
3718 mcast_obj->max_cmd_len = -1;
3719 mcast_obj->wait_comp = bnx2x_mcast_wait;
3720 mcast_obj->set_one_rule = NULL;
3721 mcast_obj->validate = bnx2x_mcast_validate_e1h;
3722 mcast_obj->revert = bnx2x_mcast_revert_e1h;
3723 mcast_obj->get_registry_size =
3724 bnx2x_mcast_get_registry_size_aprox;
3725 mcast_obj->set_registry_size =
3726 bnx2x_mcast_set_registry_size_aprox;
3728 mcast_obj->config_mcast = bnx2x_mcast_setup_e2;
3729 mcast_obj->enqueue_cmd = bnx2x_mcast_enqueue_cmd;
3730 mcast_obj->hdl_restore =
3731 bnx2x_mcast_handle_restore_cmd_e2;
3732 mcast_obj->check_pending = bnx2x_mcast_check_pending;
3733 /* TODO: There should be a proper HSI define for this number!!!
3735 mcast_obj->max_cmd_len = 16;
3736 mcast_obj->wait_comp = bnx2x_mcast_wait;
3737 mcast_obj->set_one_rule = bnx2x_mcast_set_one_rule_e2;
3738 mcast_obj->validate = bnx2x_mcast_validate_e2;
3739 mcast_obj->revert = bnx2x_mcast_revert_e2;
3740 mcast_obj->get_registry_size =
3741 bnx2x_mcast_get_registry_size_aprox;
3742 mcast_obj->set_registry_size =
3743 bnx2x_mcast_set_registry_size_aprox;
3747 /*************************** Credit handling **********************************/
3750 * atomic_add_ifless - add if the result is less than a given value.
3752 * @v: pointer of type atomic_t
3753 * @a: the amount to add to v...
3754 * @u: ...if (v + a) is less than u.
3756 * returns true if (v + a) was less than u, and false otherwise.
3759 static inline bool __atomic_add_ifless(atomic_t *v, int a, int u)
3765 if (unlikely(c + a >= u))
3768 old = atomic_cmpxchg((v), c, c + a);
3769 if (likely(old == c))
3778 * atomic_dec_ifmoe - dec if the result is more or equal than a given value.
3780 * @v: pointer of type atomic_t
3781 * @a: the amount to dec from v...
3782 * @u: ...if (v - a) is more or equal than u.
3784 * returns true if (v - a) was more or equal than u, and false
3787 static inline bool __atomic_dec_ifmoe(atomic_t *v, int a, int u)
3793 if (unlikely(c - a < u))
3796 old = atomic_cmpxchg((v), c, c - a);
3797 if (likely(old == c))
3805 static bool bnx2x_credit_pool_get(struct bnx2x_credit_pool_obj *o, int cnt)
3810 rc = __atomic_dec_ifmoe(&o->credit, cnt, 0);
3816 static bool bnx2x_credit_pool_put(struct bnx2x_credit_pool_obj *o, int cnt)
3822 /* Don't let to refill if credit + cnt > pool_sz */
3823 rc = __atomic_add_ifless(&o->credit, cnt, o->pool_sz + 1);
3830 static int bnx2x_credit_pool_check(struct bnx2x_credit_pool_obj *o)
3835 cur_credit = atomic_read(&o->credit);
3840 static bool bnx2x_credit_pool_always_true(struct bnx2x_credit_pool_obj *o,
3847 static bool bnx2x_credit_pool_get_entry(
3848 struct bnx2x_credit_pool_obj *o,
3855 /* Find "internal cam-offset" then add to base for this object... */
3856 for (vec = 0; vec < BNX2X_POOL_VEC_SIZE; vec++) {
3858 /* Skip the current vector if there are no free entries in it */
3859 if (!o->pool_mirror[vec])
3862 /* If we've got here we are going to find a free entry */
3863 for (idx = vec * BIT_VEC64_ELEM_SZ, i = 0;
3864 i < BIT_VEC64_ELEM_SZ; idx++, i++)
3866 if (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) {
3868 BIT_VEC64_CLEAR_BIT(o->pool_mirror, idx);
3869 *offset = o->base_pool_offset + idx;
3877 static bool bnx2x_credit_pool_put_entry(
3878 struct bnx2x_credit_pool_obj *o,
3881 if (offset < o->base_pool_offset)
3884 offset -= o->base_pool_offset;
3886 if (offset >= o->pool_sz)
3889 /* Return the entry to the pool */
3890 BIT_VEC64_SET_BIT(o->pool_mirror, offset);
3895 static bool bnx2x_credit_pool_put_entry_always_true(
3896 struct bnx2x_credit_pool_obj *o,
3902 static bool bnx2x_credit_pool_get_entry_always_true(
3903 struct bnx2x_credit_pool_obj *o,
3910 * bnx2x_init_credit_pool - initialize credit pool internals.
3913 * @base: Base entry in the CAM to use.
3914 * @credit: pool size.
3916 * If base is negative no CAM entries handling will be performed.
3917 * If credit is negative pool operations will always succeed (unlimited pool).
3920 static inline void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p,
3921 int base, int credit)
3923 /* Zero the object first */
3924 memset(p, 0, sizeof(*p));
3926 /* Set the table to all 1s */
3927 memset(&p->pool_mirror, 0xff, sizeof(p->pool_mirror));
3929 /* Init a pool as full */
3930 atomic_set(&p->credit, credit);
3932 /* The total poll size */
3933 p->pool_sz = credit;
3935 p->base_pool_offset = base;
3937 /* Commit the change */
3940 p->check = bnx2x_credit_pool_check;
3942 /* if pool credit is negative - disable the checks */
3944 p->put = bnx2x_credit_pool_put;
3945 p->get = bnx2x_credit_pool_get;
3946 p->put_entry = bnx2x_credit_pool_put_entry;
3947 p->get_entry = bnx2x_credit_pool_get_entry;
3949 p->put = bnx2x_credit_pool_always_true;
3950 p->get = bnx2x_credit_pool_always_true;
3951 p->put_entry = bnx2x_credit_pool_put_entry_always_true;
3952 p->get_entry = bnx2x_credit_pool_get_entry_always_true;
3955 /* If base is negative - disable entries handling */
3957 p->put_entry = bnx2x_credit_pool_put_entry_always_true;
3958 p->get_entry = bnx2x_credit_pool_get_entry_always_true;
3962 void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
3963 struct bnx2x_credit_pool_obj *p, u8 func_id,
3966 /* TODO: this will be defined in consts as well... */
3967 #define BNX2X_CAM_SIZE_EMUL 5
3971 if (CHIP_IS_E1(bp)) {
3972 /* In E1, Multicast is saved in cam... */
3973 if (!CHIP_REV_IS_SLOW(bp))
3974 cam_sz = (MAX_MAC_CREDIT_E1 / 2) - BNX2X_MAX_MULTICAST;
3976 cam_sz = BNX2X_CAM_SIZE_EMUL - BNX2X_MAX_EMUL_MULTI;
3978 bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz);
3980 } else if (CHIP_IS_E1H(bp)) {
3981 /* CAM credit is equaly divided between all active functions
3984 if ((func_num > 0)) {
3985 if (!CHIP_REV_IS_SLOW(bp))
3986 cam_sz = (MAX_MAC_CREDIT_E1H / (2*func_num));
3988 cam_sz = BNX2X_CAM_SIZE_EMUL;
3989 bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz);
3991 /* this should never happen! Block MAC operations. */
3992 bnx2x_init_credit_pool(p, 0, 0);
3998 * CAM credit is equaly divided between all active functions
4001 if ((func_num > 0)) {
4002 if (!CHIP_REV_IS_SLOW(bp))
4003 cam_sz = (MAX_MAC_CREDIT_E2 / func_num);
4005 cam_sz = BNX2X_CAM_SIZE_EMUL;
4008 * No need for CAM entries handling for 57712 and
4011 bnx2x_init_credit_pool(p, -1, cam_sz);
4013 /* this should never happen! Block MAC operations. */
4014 bnx2x_init_credit_pool(p, 0, 0);
4020 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
4021 struct bnx2x_credit_pool_obj *p,
4025 if (CHIP_IS_E1x(bp)) {
4027 * There is no VLAN credit in HW on 57710 and 57711 only
4028 * MAC / MAC-VLAN can be set
4030 bnx2x_init_credit_pool(p, 0, -1);
4033 * CAM credit is equaly divided between all active functions
4037 int credit = MAX_VLAN_CREDIT_E2 / func_num;
4038 bnx2x_init_credit_pool(p, func_id * credit, credit);
4040 /* this should never happen! Block VLAN operations. */
4041 bnx2x_init_credit_pool(p, 0, 0);
4045 /****************** RSS Configuration ******************/
4047 * bnx2x_debug_print_ind_table - prints the indirection table configuration.
4049 * @bp: driver hanlde
4050 * @p: pointer to rss configuration
4052 * Prints it when NETIF_MSG_IFUP debug level is configured.
4054 static inline void bnx2x_debug_print_ind_table(struct bnx2x *bp,
4055 struct bnx2x_config_rss_params *p)
4059 DP(BNX2X_MSG_SP, "Setting indirection table to:\n");
4060 DP(BNX2X_MSG_SP, "0x0000: ");
4061 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
4062 DP_CONT(BNX2X_MSG_SP, "0x%02x ", p->ind_table[i]);
4064 /* Print 4 bytes in a line */
4065 if ((i + 1 < T_ETH_INDIRECTION_TABLE_SIZE) &&
4066 (((i + 1) & 0x3) == 0)) {
4067 DP_CONT(BNX2X_MSG_SP, "\n");
4068 DP(BNX2X_MSG_SP, "0x%04x: ", i + 1);
4072 DP_CONT(BNX2X_MSG_SP, "\n");
4076 * bnx2x_setup_rss - configure RSS
4078 * @bp: device handle
4079 * @p: rss configuration
4081 * sends on UPDATE ramrod for that matter.
4083 static int bnx2x_setup_rss(struct bnx2x *bp,
4084 struct bnx2x_config_rss_params *p)
4086 struct bnx2x_rss_config_obj *o = p->rss_obj;
4087 struct bnx2x_raw_obj *r = &o->raw;
4088 struct eth_rss_update_ramrod_data *data =
4089 (struct eth_rss_update_ramrod_data *)(r->rdata);
4093 memset(data, 0, sizeof(*data));
4095 DP(BNX2X_MSG_SP, "Configuring RSS\n");
4097 /* Set an echo field */
4098 data->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
4099 (r->state << BNX2X_SWCID_SHIFT));
4102 if (test_bit(BNX2X_RSS_MODE_DISABLED, &p->rss_flags))
4103 rss_mode = ETH_RSS_MODE_DISABLED;
4104 else if (test_bit(BNX2X_RSS_MODE_REGULAR, &p->rss_flags))
4105 rss_mode = ETH_RSS_MODE_REGULAR;
4107 data->rss_mode = rss_mode;
4109 DP(BNX2X_MSG_SP, "rss_mode=%d\n", rss_mode);
4111 /* RSS capabilities */
4112 if (test_bit(BNX2X_RSS_IPV4, &p->rss_flags))
4113 data->capabilities |=
4114 ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY;
4116 if (test_bit(BNX2X_RSS_IPV4_TCP, &p->rss_flags))
4117 data->capabilities |=
4118 ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY;
4120 if (test_bit(BNX2X_RSS_IPV4_UDP, &p->rss_flags))
4121 data->capabilities |=
4122 ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY;
4124 if (test_bit(BNX2X_RSS_IPV6, &p->rss_flags))
4125 data->capabilities |=
4126 ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY;
4128 if (test_bit(BNX2X_RSS_IPV6_TCP, &p->rss_flags))
4129 data->capabilities |=
4130 ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY;
4132 if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags))
4133 data->capabilities |=
4134 ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
4137 data->rss_result_mask = p->rss_result_mask;
4140 data->rss_engine_id = o->engine_id;
4142 DP(BNX2X_MSG_SP, "rss_engine_id=%d\n", data->rss_engine_id);
4144 /* Indirection table */
4145 memcpy(data->indirection_table, p->ind_table,
4146 T_ETH_INDIRECTION_TABLE_SIZE);
4148 /* Remember the last configuration */
4149 memcpy(o->ind_table, p->ind_table, T_ETH_INDIRECTION_TABLE_SIZE);
4151 /* Print the indirection table */
4152 if (netif_msg_ifup(bp))
4153 bnx2x_debug_print_ind_table(bp, p);
4156 if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) {
4157 memcpy(&data->rss_key[0], &p->rss_key[0],
4158 sizeof(data->rss_key));
4159 data->capabilities |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY;
4163 * No need for an explicit memory barrier here as long we would
4164 * need to ensure the ordering of writing to the SPQ element
4165 * and updating of the SPQ producer which involves a memory
4166 * read and we will have to put a full memory barrier there
4167 * (inside bnx2x_sp_post()).
4171 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_RSS_UPDATE, r->cid,
4172 U64_HI(r->rdata_mapping),
4173 U64_LO(r->rdata_mapping),
4174 ETH_CONNECTION_TYPE);
4182 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
4185 memcpy(ind_table, rss_obj->ind_table, sizeof(rss_obj->ind_table));
4188 int bnx2x_config_rss(struct bnx2x *bp,
4189 struct bnx2x_config_rss_params *p)
4192 struct bnx2x_rss_config_obj *o = p->rss_obj;
4193 struct bnx2x_raw_obj *r = &o->raw;
4195 /* Do nothing if only driver cleanup was requested */
4196 if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags))
4201 rc = o->config_rss(bp, p);
4203 r->clear_pending(r);
4207 if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags))
4208 rc = r->wait_comp(bp, r);
4214 void bnx2x_init_rss_config_obj(struct bnx2x *bp,
4215 struct bnx2x_rss_config_obj *rss_obj,
4216 u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
4217 void *rdata, dma_addr_t rdata_mapping,
4218 int state, unsigned long *pstate,
4219 bnx2x_obj_type type)
4221 bnx2x_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata,
4222 rdata_mapping, state, pstate, type);
4224 rss_obj->engine_id = engine_id;
4225 rss_obj->config_rss = bnx2x_setup_rss;
4228 /********************** Queue state object ***********************************/
4231 * bnx2x_queue_state_change - perform Queue state change transition
4233 * @bp: device handle
4234 * @params: parameters to perform the transition
4236 * returns 0 in case of successfully completed transition, negative error
4237 * code in case of failure, positive (EBUSY) value if there is a completion
4238 * to that is still pending (possible only if RAMROD_COMP_WAIT is
4239 * not set in params->ramrod_flags for asynchronous commands).
4242 int bnx2x_queue_state_change(struct bnx2x *bp,
4243 struct bnx2x_queue_state_params *params)
4245 struct bnx2x_queue_sp_obj *o = params->q_obj;
4246 int rc, pending_bit;
4247 unsigned long *pending = &o->pending;
4249 /* Check that the requested transition is legal */
4250 rc = o->check_transition(bp, o, params);
4252 BNX2X_ERR("check transition returned an error. rc %d\n", rc);
4256 /* Set "pending" bit */
4257 DP(BNX2X_MSG_SP, "pending bit was=%lx\n", o->pending);
4258 pending_bit = o->set_pending(o, params);
4259 DP(BNX2X_MSG_SP, "pending bit now=%lx\n", o->pending);
4261 /* Don't send a command if only driver cleanup was requested */
4262 if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags))
4263 o->complete_cmd(bp, o, pending_bit);
4266 rc = o->send_cmd(bp, params);
4268 o->next_state = BNX2X_Q_STATE_MAX;
4269 clear_bit(pending_bit, pending);
4270 smp_mb__after_clear_bit();
4274 if (test_bit(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) {
4275 rc = o->wait_comp(bp, o, pending_bit);
4283 return !!test_bit(pending_bit, pending);
4287 static int bnx2x_queue_set_pending(struct bnx2x_queue_sp_obj *obj,
4288 struct bnx2x_queue_state_params *params)
4290 enum bnx2x_queue_cmd cmd = params->cmd, bit;
4292 /* ACTIVATE and DEACTIVATE commands are implemented on top of
4295 if ((cmd == BNX2X_Q_CMD_ACTIVATE) ||
4296 (cmd == BNX2X_Q_CMD_DEACTIVATE))
4297 bit = BNX2X_Q_CMD_UPDATE;
4301 set_bit(bit, &obj->pending);
4305 static int bnx2x_queue_wait_comp(struct bnx2x *bp,
4306 struct bnx2x_queue_sp_obj *o,
4307 enum bnx2x_queue_cmd cmd)
4309 return bnx2x_state_wait(bp, cmd, &o->pending);
4313 * bnx2x_queue_comp_cmd - complete the state change command.
4315 * @bp: device handle
4319 * Checks that the arrived completion is expected.
4321 static int bnx2x_queue_comp_cmd(struct bnx2x *bp,
4322 struct bnx2x_queue_sp_obj *o,
4323 enum bnx2x_queue_cmd cmd)
4325 unsigned long cur_pending = o->pending;
4327 if (!test_and_clear_bit(cmd, &cur_pending)) {
4328 BNX2X_ERR("Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\n",
4329 cmd, o->cids[BNX2X_PRIMARY_CID_INDEX],
4330 o->state, cur_pending, o->next_state);
4334 if (o->next_tx_only >= o->max_cos)
4335 /* >= becuase tx only must always be smaller than cos since the
4336 * primary connection supports COS 0
4338 BNX2X_ERR("illegal value for next tx_only: %d. max cos was %d",
4339 o->next_tx_only, o->max_cos);
4342 "Completing command %d for queue %d, setting state to %d\n",
4343 cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_state);
4345 if (o->next_tx_only) /* print num tx-only if any exist */
4346 DP(BNX2X_MSG_SP, "primary cid %d: num tx-only cons %d\n",
4347 o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_tx_only);
4349 o->state = o->next_state;
4350 o->num_tx_only = o->next_tx_only;
4351 o->next_state = BNX2X_Q_STATE_MAX;
4353 /* It's important that o->state and o->next_state are
4354 * updated before o->pending.
4358 clear_bit(cmd, &o->pending);
4359 smp_mb__after_clear_bit();
4364 static void bnx2x_q_fill_setup_data_e2(struct bnx2x *bp,
4365 struct bnx2x_queue_state_params *cmd_params,
4366 struct client_init_ramrod_data *data)
4368 struct bnx2x_queue_setup_params *params = &cmd_params->params.setup;
4372 /* IPv6 TPA supported for E2 and above only */
4373 data->rx.tpa_en |= test_bit(BNX2X_Q_FLG_TPA_IPV6, ¶ms->flags) *
4374 CLIENT_INIT_RX_DATA_TPA_EN_IPV6;
4377 static void bnx2x_q_fill_init_general_data(struct bnx2x *bp,
4378 struct bnx2x_queue_sp_obj *o,
4379 struct bnx2x_general_setup_params *params,
4380 struct client_init_general_data *gen_data,
4381 unsigned long *flags)
4383 gen_data->client_id = o->cl_id;
4385 if (test_bit(BNX2X_Q_FLG_STATS, flags)) {
4386 gen_data->statistics_counter_id =
4388 gen_data->statistics_en_flg = 1;
4389 gen_data->statistics_zero_flg =
4390 test_bit(BNX2X_Q_FLG_ZERO_STATS, flags);
4392 gen_data->statistics_counter_id =
4393 DISABLE_STATISTIC_COUNTER_ID_VALUE;
4395 gen_data->is_fcoe_flg = test_bit(BNX2X_Q_FLG_FCOE, flags);
4396 gen_data->activate_flg = test_bit(BNX2X_Q_FLG_ACTIVE, flags);
4397 gen_data->sp_client_id = params->spcl_id;
4398 gen_data->mtu = cpu_to_le16(params->mtu);
4399 gen_data->func_id = o->func_id;
4402 gen_data->cos = params->cos;
4404 gen_data->traffic_type =
4405 test_bit(BNX2X_Q_FLG_FCOE, flags) ?
4406 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
4408 DP(BNX2X_MSG_SP, "flags: active %d, cos %d, stats en %d\n",
4409 gen_data->activate_flg, gen_data->cos, gen_data->statistics_en_flg);
4412 static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o,
4413 struct bnx2x_txq_setup_params *params,
4414 struct client_init_tx_data *tx_data,
4415 unsigned long *flags)
4417 tx_data->enforce_security_flg =
4418 test_bit(BNX2X_Q_FLG_TX_SEC, flags);
4419 tx_data->default_vlan =
4420 cpu_to_le16(params->default_vlan);
4421 tx_data->default_vlan_flg =
4422 test_bit(BNX2X_Q_FLG_DEF_VLAN, flags);
4423 tx_data->tx_switching_flg =
4424 test_bit(BNX2X_Q_FLG_TX_SWITCH, flags);
4425 tx_data->anti_spoofing_flg =
4426 test_bit(BNX2X_Q_FLG_ANTI_SPOOF, flags);
4427 tx_data->force_default_pri_flg =
4428 test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags);
4430 tx_data->tx_status_block_id = params->fw_sb_id;
4431 tx_data->tx_sb_index_number = params->sb_cq_index;
4432 tx_data->tss_leading_client_id = params->tss_leading_cl_id;
4434 tx_data->tx_bd_page_base.lo =
4435 cpu_to_le32(U64_LO(params->dscr_map));
4436 tx_data->tx_bd_page_base.hi =
4437 cpu_to_le32(U64_HI(params->dscr_map));
4439 /* Don't configure any Tx switching mode during queue SETUP */
4443 static void bnx2x_q_fill_init_pause_data(struct bnx2x_queue_sp_obj *o,
4444 struct rxq_pause_params *params,
4445 struct client_init_rx_data *rx_data)
4447 /* flow control data */
4448 rx_data->cqe_pause_thr_low = cpu_to_le16(params->rcq_th_lo);
4449 rx_data->cqe_pause_thr_high = cpu_to_le16(params->rcq_th_hi);
4450 rx_data->bd_pause_thr_low = cpu_to_le16(params->bd_th_lo);
4451 rx_data->bd_pause_thr_high = cpu_to_le16(params->bd_th_hi);
4452 rx_data->sge_pause_thr_low = cpu_to_le16(params->sge_th_lo);
4453 rx_data->sge_pause_thr_high = cpu_to_le16(params->sge_th_hi);
4454 rx_data->rx_cos_mask = cpu_to_le16(params->pri_map);
4457 static void bnx2x_q_fill_init_rx_data(struct bnx2x_queue_sp_obj *o,
4458 struct bnx2x_rxq_setup_params *params,
4459 struct client_init_rx_data *rx_data,
4460 unsigned long *flags)
4462 rx_data->tpa_en = test_bit(BNX2X_Q_FLG_TPA, flags) *
4463 CLIENT_INIT_RX_DATA_TPA_EN_IPV4;
4464 rx_data->tpa_en |= test_bit(BNX2X_Q_FLG_TPA_GRO, flags) *
4465 CLIENT_INIT_RX_DATA_TPA_MODE;
4466 rx_data->vmqueue_mode_en_flg = 0;
4468 rx_data->cache_line_alignment_log_size =
4469 params->cache_line_log;
4470 rx_data->enable_dynamic_hc =
4471 test_bit(BNX2X_Q_FLG_DHC, flags);
4472 rx_data->max_sges_for_packet = params->max_sges_pkt;
4473 rx_data->client_qzone_id = params->cl_qzone_id;
4474 rx_data->max_agg_size = cpu_to_le16(params->tpa_agg_sz);
4476 /* Always start in DROP_ALL mode */
4477 rx_data->state = cpu_to_le16(CLIENT_INIT_RX_DATA_UCAST_DROP_ALL |
4478 CLIENT_INIT_RX_DATA_MCAST_DROP_ALL);
4480 /* We don't set drop flags */
4481 rx_data->drop_ip_cs_err_flg = 0;
4482 rx_data->drop_tcp_cs_err_flg = 0;
4483 rx_data->drop_ttl0_flg = 0;
4484 rx_data->drop_udp_cs_err_flg = 0;
4485 rx_data->inner_vlan_removal_enable_flg =
4486 test_bit(BNX2X_Q_FLG_VLAN, flags);
4487 rx_data->outer_vlan_removal_enable_flg =
4488 test_bit(BNX2X_Q_FLG_OV, flags);
4489 rx_data->status_block_id = params->fw_sb_id;
4490 rx_data->rx_sb_index_number = params->sb_cq_index;
4491 rx_data->max_tpa_queues = params->max_tpa_queues;
4492 rx_data->max_bytes_on_bd = cpu_to_le16(params->buf_sz);
4493 rx_data->sge_buff_size = cpu_to_le16(params->sge_buf_sz);
4494 rx_data->bd_page_base.lo =
4495 cpu_to_le32(U64_LO(params->dscr_map));
4496 rx_data->bd_page_base.hi =
4497 cpu_to_le32(U64_HI(params->dscr_map));
4498 rx_data->sge_page_base.lo =
4499 cpu_to_le32(U64_LO(params->sge_map));
4500 rx_data->sge_page_base.hi =
4501 cpu_to_le32(U64_HI(params->sge_map));
4502 rx_data->cqe_page_base.lo =
4503 cpu_to_le32(U64_LO(params->rcq_map));
4504 rx_data->cqe_page_base.hi =
4505 cpu_to_le32(U64_HI(params->rcq_map));
4506 rx_data->is_leading_rss = test_bit(BNX2X_Q_FLG_LEADING_RSS, flags);
4508 if (test_bit(BNX2X_Q_FLG_MCAST, flags)) {
4509 rx_data->approx_mcast_engine_id = params->mcast_engine_id;
4510 rx_data->is_approx_mcast = 1;
4513 rx_data->rss_engine_id = params->rss_engine_id;
4515 /* silent vlan removal */
4516 rx_data->silent_vlan_removal_flg =
4517 test_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, flags);
4518 rx_data->silent_vlan_value =
4519 cpu_to_le16(params->silent_removal_value);
4520 rx_data->silent_vlan_mask =
4521 cpu_to_le16(params->silent_removal_mask);
4525 /* initialize the general, tx and rx parts of a queue object */
4526 static void bnx2x_q_fill_setup_data_cmn(struct bnx2x *bp,
4527 struct bnx2x_queue_state_params *cmd_params,
4528 struct client_init_ramrod_data *data)
4530 bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj,
4531 &cmd_params->params.setup.gen_params,
4533 &cmd_params->params.setup.flags);
4535 bnx2x_q_fill_init_tx_data(cmd_params->q_obj,
4536 &cmd_params->params.setup.txq_params,
4538 &cmd_params->params.setup.flags);
4540 bnx2x_q_fill_init_rx_data(cmd_params->q_obj,
4541 &cmd_params->params.setup.rxq_params,
4543 &cmd_params->params.setup.flags);
4545 bnx2x_q_fill_init_pause_data(cmd_params->q_obj,
4546 &cmd_params->params.setup.pause_params,
4550 /* initialize the general and tx parts of a tx-only queue object */
4551 static void bnx2x_q_fill_setup_tx_only(struct bnx2x *bp,
4552 struct bnx2x_queue_state_params *cmd_params,
4553 struct tx_queue_init_ramrod_data *data)
4555 bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj,
4556 &cmd_params->params.tx_only.gen_params,
4558 &cmd_params->params.tx_only.flags);
4560 bnx2x_q_fill_init_tx_data(cmd_params->q_obj,
4561 &cmd_params->params.tx_only.txq_params,
4563 &cmd_params->params.tx_only.flags);
4565 DP(BNX2X_MSG_SP, "cid %d, tx bd page lo %x hi %x",
4566 cmd_params->q_obj->cids[0],
4567 data->tx.tx_bd_page_base.lo,
4568 data->tx.tx_bd_page_base.hi);
4572 * bnx2x_q_init - init HW/FW queue
4574 * @bp: device handle
4577 * HW/FW initial Queue configuration:
4579 * - CDU context validation
4582 static inline int bnx2x_q_init(struct bnx2x *bp,
4583 struct bnx2x_queue_state_params *params)
4585 struct bnx2x_queue_sp_obj *o = params->q_obj;
4586 struct bnx2x_queue_init_params *init = ¶ms->params.init;
4590 /* Tx HC configuration */
4591 if (test_bit(BNX2X_Q_TYPE_HAS_TX, &o->type) &&
4592 test_bit(BNX2X_Q_FLG_HC, &init->tx.flags)) {
4593 hc_usec = init->tx.hc_rate ? 1000000 / init->tx.hc_rate : 0;
4595 bnx2x_update_coalesce_sb_index(bp, init->tx.fw_sb_id,
4596 init->tx.sb_cq_index,
4597 !test_bit(BNX2X_Q_FLG_HC_EN, &init->tx.flags),
4601 /* Rx HC configuration */
4602 if (test_bit(BNX2X_Q_TYPE_HAS_RX, &o->type) &&
4603 test_bit(BNX2X_Q_FLG_HC, &init->rx.flags)) {
4604 hc_usec = init->rx.hc_rate ? 1000000 / init->rx.hc_rate : 0;
4606 bnx2x_update_coalesce_sb_index(bp, init->rx.fw_sb_id,
4607 init->rx.sb_cq_index,
4608 !test_bit(BNX2X_Q_FLG_HC_EN, &init->rx.flags),
4612 /* Set CDU context validation values */
4613 for (cos = 0; cos < o->max_cos; cos++) {
4614 DP(BNX2X_MSG_SP, "setting context validation. cid %d, cos %d\n",
4616 DP(BNX2X_MSG_SP, "context pointer %p\n", init->cxts[cos]);
4617 bnx2x_set_ctx_validation(bp, init->cxts[cos], o->cids[cos]);
4620 /* As no ramrod is sent, complete the command immediately */
4621 o->complete_cmd(bp, o, BNX2X_Q_CMD_INIT);
4629 static inline int bnx2x_q_send_setup_e1x(struct bnx2x *bp,
4630 struct bnx2x_queue_state_params *params)
4632 struct bnx2x_queue_sp_obj *o = params->q_obj;
4633 struct client_init_ramrod_data *rdata =
4634 (struct client_init_ramrod_data *)o->rdata;
4635 dma_addr_t data_mapping = o->rdata_mapping;
4636 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
4638 /* Clear the ramrod data */
4639 memset(rdata, 0, sizeof(*rdata));
4641 /* Fill the ramrod data */
4642 bnx2x_q_fill_setup_data_cmn(bp, params, rdata);
4645 * No need for an explicit memory barrier here as long we would
4646 * need to ensure the ordering of writing to the SPQ element
4647 * and updating of the SPQ producer which involves a memory
4648 * read and we will have to put a full memory barrier there
4649 * (inside bnx2x_sp_post()).
4652 return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX],
4653 U64_HI(data_mapping),
4654 U64_LO(data_mapping), ETH_CONNECTION_TYPE);
4657 static inline int bnx2x_q_send_setup_e2(struct bnx2x *bp,
4658 struct bnx2x_queue_state_params *params)
4660 struct bnx2x_queue_sp_obj *o = params->q_obj;
4661 struct client_init_ramrod_data *rdata =
4662 (struct client_init_ramrod_data *)o->rdata;
4663 dma_addr_t data_mapping = o->rdata_mapping;
4664 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
4666 /* Clear the ramrod data */
4667 memset(rdata, 0, sizeof(*rdata));
4669 /* Fill the ramrod data */
4670 bnx2x_q_fill_setup_data_cmn(bp, params, rdata);
4671 bnx2x_q_fill_setup_data_e2(bp, params, rdata);
4674 * No need for an explicit memory barrier here as long we would
4675 * need to ensure the ordering of writing to the SPQ element
4676 * and updating of the SPQ producer which involves a memory
4677 * read and we will have to put a full memory barrier there
4678 * (inside bnx2x_sp_post()).
4681 return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX],
4682 U64_HI(data_mapping),
4683 U64_LO(data_mapping), ETH_CONNECTION_TYPE);
4686 static inline int bnx2x_q_send_setup_tx_only(struct bnx2x *bp,
4687 struct bnx2x_queue_state_params *params)
4689 struct bnx2x_queue_sp_obj *o = params->q_obj;
4690 struct tx_queue_init_ramrod_data *rdata =
4691 (struct tx_queue_init_ramrod_data *)o->rdata;
4692 dma_addr_t data_mapping = o->rdata_mapping;
4693 int ramrod = RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP;
4694 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
4695 ¶ms->params.tx_only;
4696 u8 cid_index = tx_only_params->cid_index;
4699 if (cid_index >= o->max_cos) {
4700 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
4701 o->cl_id, cid_index);
4705 DP(BNX2X_MSG_SP, "parameters received: cos: %d sp-id: %d\n",
4706 tx_only_params->gen_params.cos,
4707 tx_only_params->gen_params.spcl_id);
4709 /* Clear the ramrod data */
4710 memset(rdata, 0, sizeof(*rdata));
4712 /* Fill the ramrod data */
4713 bnx2x_q_fill_setup_tx_only(bp, params, rdata);
4715 DP(BNX2X_MSG_SP, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\n",
4716 o->cids[cid_index], rdata->general.client_id,
4717 rdata->general.sp_client_id, rdata->general.cos);
4720 * No need for an explicit memory barrier here as long we would
4721 * need to ensure the ordering of writing to the SPQ element
4722 * and updating of the SPQ producer which involves a memory
4723 * read and we will have to put a full memory barrier there
4724 * (inside bnx2x_sp_post()).
4727 return bnx2x_sp_post(bp, ramrod, o->cids[cid_index],
4728 U64_HI(data_mapping),
4729 U64_LO(data_mapping), ETH_CONNECTION_TYPE);
4732 static void bnx2x_q_fill_update_data(struct bnx2x *bp,
4733 struct bnx2x_queue_sp_obj *obj,
4734 struct bnx2x_queue_update_params *params,
4735 struct client_update_ramrod_data *data)
4737 /* Client ID of the client to update */
4738 data->client_id = obj->cl_id;
4740 /* Function ID of the client to update */
4741 data->func_id = obj->func_id;
4743 /* Default VLAN value */
4744 data->default_vlan = cpu_to_le16(params->def_vlan);
4746 /* Inner VLAN stripping */
4747 data->inner_vlan_removal_enable_flg =
4748 test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM, ¶ms->update_flags);
4749 data->inner_vlan_removal_change_flg =
4750 test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
4751 ¶ms->update_flags);
4753 /* Outer VLAN sripping */
4754 data->outer_vlan_removal_enable_flg =
4755 test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM, ¶ms->update_flags);
4756 data->outer_vlan_removal_change_flg =
4757 test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
4758 ¶ms->update_flags);
4760 /* Drop packets that have source MAC that doesn't belong to this
4763 data->anti_spoofing_enable_flg =
4764 test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF, ¶ms->update_flags);
4765 data->anti_spoofing_change_flg =
4766 test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, ¶ms->update_flags);
4768 /* Activate/Deactivate */
4769 data->activate_flg =
4770 test_bit(BNX2X_Q_UPDATE_ACTIVATE, ¶ms->update_flags);
4771 data->activate_change_flg =
4772 test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, ¶ms->update_flags);
4774 /* Enable default VLAN */
4775 data->default_vlan_enable_flg =
4776 test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, ¶ms->update_flags);
4777 data->default_vlan_change_flg =
4778 test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
4779 ¶ms->update_flags);
4781 /* silent vlan removal */
4782 data->silent_vlan_change_flg =
4783 test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4784 ¶ms->update_flags);
4785 data->silent_vlan_removal_flg =
4786 test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, ¶ms->update_flags);
4787 data->silent_vlan_value = cpu_to_le16(params->silent_removal_value);
4788 data->silent_vlan_mask = cpu_to_le16(params->silent_removal_mask);
4791 static inline int bnx2x_q_send_update(struct bnx2x *bp,
4792 struct bnx2x_queue_state_params *params)
4794 struct bnx2x_queue_sp_obj *o = params->q_obj;
4795 struct client_update_ramrod_data *rdata =
4796 (struct client_update_ramrod_data *)o->rdata;
4797 dma_addr_t data_mapping = o->rdata_mapping;
4798 struct bnx2x_queue_update_params *update_params =
4799 ¶ms->params.update;
4800 u8 cid_index = update_params->cid_index;
4802 if (cid_index >= o->max_cos) {
4803 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
4804 o->cl_id, cid_index);
4809 /* Clear the ramrod data */
4810 memset(rdata, 0, sizeof(*rdata));
4812 /* Fill the ramrod data */
4813 bnx2x_q_fill_update_data(bp, o, update_params, rdata);
4816 * No need for an explicit memory barrier here as long we would
4817 * need to ensure the ordering of writing to the SPQ element
4818 * and updating of the SPQ producer which involves a memory
4819 * read and we will have to put a full memory barrier there
4820 * (inside bnx2x_sp_post()).
4823 return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
4824 o->cids[cid_index], U64_HI(data_mapping),
4825 U64_LO(data_mapping), ETH_CONNECTION_TYPE);
4829 * bnx2x_q_send_deactivate - send DEACTIVATE command
4831 * @bp: device handle
4834 * implemented using the UPDATE command.
4836 static inline int bnx2x_q_send_deactivate(struct bnx2x *bp,
4837 struct bnx2x_queue_state_params *params)
4839 struct bnx2x_queue_update_params *update = ¶ms->params.update;
4841 memset(update, 0, sizeof(*update));
4843 __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags);
4845 return bnx2x_q_send_update(bp, params);
4849 * bnx2x_q_send_activate - send ACTIVATE command
4851 * @bp: device handle
4854 * implemented using the UPDATE command.
4856 static inline int bnx2x_q_send_activate(struct bnx2x *bp,
4857 struct bnx2x_queue_state_params *params)
4859 struct bnx2x_queue_update_params *update = ¶ms->params.update;
4861 memset(update, 0, sizeof(*update));
4863 __set_bit(BNX2X_Q_UPDATE_ACTIVATE, &update->update_flags);
4864 __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags);
4866 return bnx2x_q_send_update(bp, params);
4869 static inline int bnx2x_q_send_update_tpa(struct bnx2x *bp,
4870 struct bnx2x_queue_state_params *params)
4872 /* TODO: Not implemented yet. */
4876 static inline int bnx2x_q_send_halt(struct bnx2x *bp,
4877 struct bnx2x_queue_state_params *params)
4879 struct bnx2x_queue_sp_obj *o = params->q_obj;
4881 return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT,
4882 o->cids[BNX2X_PRIMARY_CID_INDEX], 0, o->cl_id,
4883 ETH_CONNECTION_TYPE);
4886 static inline int bnx2x_q_send_cfc_del(struct bnx2x *bp,
4887 struct bnx2x_queue_state_params *params)
4889 struct bnx2x_queue_sp_obj *o = params->q_obj;
4890 u8 cid_idx = params->params.cfc_del.cid_index;
4892 if (cid_idx >= o->max_cos) {
4893 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
4898 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL,
4899 o->cids[cid_idx], 0, 0, NONE_CONNECTION_TYPE);
4902 static inline int bnx2x_q_send_terminate(struct bnx2x *bp,
4903 struct bnx2x_queue_state_params *params)
4905 struct bnx2x_queue_sp_obj *o = params->q_obj;
4906 u8 cid_index = params->params.terminate.cid_index;
4908 if (cid_index >= o->max_cos) {
4909 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
4910 o->cl_id, cid_index);
4914 return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE,
4915 o->cids[cid_index], 0, 0, ETH_CONNECTION_TYPE);
4918 static inline int bnx2x_q_send_empty(struct bnx2x *bp,
4919 struct bnx2x_queue_state_params *params)
4921 struct bnx2x_queue_sp_obj *o = params->q_obj;
4923 return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_EMPTY,
4924 o->cids[BNX2X_PRIMARY_CID_INDEX], 0, 0,
4925 ETH_CONNECTION_TYPE);
4928 static inline int bnx2x_queue_send_cmd_cmn(struct bnx2x *bp,
4929 struct bnx2x_queue_state_params *params)
4931 switch (params->cmd) {
4932 case BNX2X_Q_CMD_INIT:
4933 return bnx2x_q_init(bp, params);
4934 case BNX2X_Q_CMD_SETUP_TX_ONLY:
4935 return bnx2x_q_send_setup_tx_only(bp, params);
4936 case BNX2X_Q_CMD_DEACTIVATE:
4937 return bnx2x_q_send_deactivate(bp, params);
4938 case BNX2X_Q_CMD_ACTIVATE:
4939 return bnx2x_q_send_activate(bp, params);
4940 case BNX2X_Q_CMD_UPDATE:
4941 return bnx2x_q_send_update(bp, params);
4942 case BNX2X_Q_CMD_UPDATE_TPA:
4943 return bnx2x_q_send_update_tpa(bp, params);
4944 case BNX2X_Q_CMD_HALT:
4945 return bnx2x_q_send_halt(bp, params);
4946 case BNX2X_Q_CMD_CFC_DEL:
4947 return bnx2x_q_send_cfc_del(bp, params);
4948 case BNX2X_Q_CMD_TERMINATE:
4949 return bnx2x_q_send_terminate(bp, params);
4950 case BNX2X_Q_CMD_EMPTY:
4951 return bnx2x_q_send_empty(bp, params);
4953 BNX2X_ERR("Unknown command: %d\n", params->cmd);
4958 static int bnx2x_queue_send_cmd_e1x(struct bnx2x *bp,
4959 struct bnx2x_queue_state_params *params)
4961 switch (params->cmd) {
4962 case BNX2X_Q_CMD_SETUP:
4963 return bnx2x_q_send_setup_e1x(bp, params);
4964 case BNX2X_Q_CMD_INIT:
4965 case BNX2X_Q_CMD_SETUP_TX_ONLY:
4966 case BNX2X_Q_CMD_DEACTIVATE:
4967 case BNX2X_Q_CMD_ACTIVATE:
4968 case BNX2X_Q_CMD_UPDATE:
4969 case BNX2X_Q_CMD_UPDATE_TPA:
4970 case BNX2X_Q_CMD_HALT:
4971 case BNX2X_Q_CMD_CFC_DEL:
4972 case BNX2X_Q_CMD_TERMINATE:
4973 case BNX2X_Q_CMD_EMPTY:
4974 return bnx2x_queue_send_cmd_cmn(bp, params);
4976 BNX2X_ERR("Unknown command: %d\n", params->cmd);
4981 static int bnx2x_queue_send_cmd_e2(struct bnx2x *bp,
4982 struct bnx2x_queue_state_params *params)
4984 switch (params->cmd) {
4985 case BNX2X_Q_CMD_SETUP:
4986 return bnx2x_q_send_setup_e2(bp, params);
4987 case BNX2X_Q_CMD_INIT:
4988 case BNX2X_Q_CMD_SETUP_TX_ONLY:
4989 case BNX2X_Q_CMD_DEACTIVATE:
4990 case BNX2X_Q_CMD_ACTIVATE:
4991 case BNX2X_Q_CMD_UPDATE:
4992 case BNX2X_Q_CMD_UPDATE_TPA:
4993 case BNX2X_Q_CMD_HALT:
4994 case BNX2X_Q_CMD_CFC_DEL:
4995 case BNX2X_Q_CMD_TERMINATE:
4996 case BNX2X_Q_CMD_EMPTY:
4997 return bnx2x_queue_send_cmd_cmn(bp, params);
4999 BNX2X_ERR("Unknown command: %d\n", params->cmd);
5005 * bnx2x_queue_chk_transition - check state machine of a regular Queue
5007 * @bp: device handle
5012 * It both checks if the requested command is legal in a current
5013 * state and, if it's legal, sets a `next_state' in the object
5014 * that will be used in the completion flow to set the `state'
5017 * returns 0 if a requested command is a legal transition,
5018 * -EINVAL otherwise.
5020 static int bnx2x_queue_chk_transition(struct bnx2x *bp,
5021 struct bnx2x_queue_sp_obj *o,
5022 struct bnx2x_queue_state_params *params)
5024 enum bnx2x_q_state state = o->state, next_state = BNX2X_Q_STATE_MAX;
5025 enum bnx2x_queue_cmd cmd = params->cmd;
5026 struct bnx2x_queue_update_params *update_params =
5027 ¶ms->params.update;
5028 u8 next_tx_only = o->num_tx_only;
5031 * Forget all pending for completion commands if a driver only state
5032 * transition has been requested.
5034 if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) {
5036 o->next_state = BNX2X_Q_STATE_MAX;
5040 * Don't allow a next state transition if we are in the middle of
5044 BNX2X_ERR("Blocking transition since pending was %lx\n",
5050 case BNX2X_Q_STATE_RESET:
5051 if (cmd == BNX2X_Q_CMD_INIT)
5052 next_state = BNX2X_Q_STATE_INITIALIZED;
5055 case BNX2X_Q_STATE_INITIALIZED:
5056 if (cmd == BNX2X_Q_CMD_SETUP) {
5057 if (test_bit(BNX2X_Q_FLG_ACTIVE,
5058 ¶ms->params.setup.flags))
5059 next_state = BNX2X_Q_STATE_ACTIVE;
5061 next_state = BNX2X_Q_STATE_INACTIVE;
5065 case BNX2X_Q_STATE_ACTIVE:
5066 if (cmd == BNX2X_Q_CMD_DEACTIVATE)
5067 next_state = BNX2X_Q_STATE_INACTIVE;
5069 else if ((cmd == BNX2X_Q_CMD_EMPTY) ||
5070 (cmd == BNX2X_Q_CMD_UPDATE_TPA))
5071 next_state = BNX2X_Q_STATE_ACTIVE;
5073 else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) {
5074 next_state = BNX2X_Q_STATE_MULTI_COS;
5078 else if (cmd == BNX2X_Q_CMD_HALT)
5079 next_state = BNX2X_Q_STATE_STOPPED;
5081 else if (cmd == BNX2X_Q_CMD_UPDATE) {
5082 /* If "active" state change is requested, update the
5083 * state accordingly.
5085 if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG,
5086 &update_params->update_flags) &&
5087 !test_bit(BNX2X_Q_UPDATE_ACTIVATE,
5088 &update_params->update_flags))
5089 next_state = BNX2X_Q_STATE_INACTIVE;
5091 next_state = BNX2X_Q_STATE_ACTIVE;
5095 case BNX2X_Q_STATE_MULTI_COS:
5096 if (cmd == BNX2X_Q_CMD_TERMINATE)
5097 next_state = BNX2X_Q_STATE_MCOS_TERMINATED;
5099 else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) {
5100 next_state = BNX2X_Q_STATE_MULTI_COS;
5101 next_tx_only = o->num_tx_only + 1;
5104 else if ((cmd == BNX2X_Q_CMD_EMPTY) ||
5105 (cmd == BNX2X_Q_CMD_UPDATE_TPA))
5106 next_state = BNX2X_Q_STATE_MULTI_COS;
5108 else if (cmd == BNX2X_Q_CMD_UPDATE) {
5109 /* If "active" state change is requested, update the
5110 * state accordingly.
5112 if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG,
5113 &update_params->update_flags) &&
5114 !test_bit(BNX2X_Q_UPDATE_ACTIVATE,
5115 &update_params->update_flags))
5116 next_state = BNX2X_Q_STATE_INACTIVE;
5118 next_state = BNX2X_Q_STATE_MULTI_COS;
5122 case BNX2X_Q_STATE_MCOS_TERMINATED:
5123 if (cmd == BNX2X_Q_CMD_CFC_DEL) {
5124 next_tx_only = o->num_tx_only - 1;
5125 if (next_tx_only == 0)
5126 next_state = BNX2X_Q_STATE_ACTIVE;
5128 next_state = BNX2X_Q_STATE_MULTI_COS;
5132 case BNX2X_Q_STATE_INACTIVE:
5133 if (cmd == BNX2X_Q_CMD_ACTIVATE)
5134 next_state = BNX2X_Q_STATE_ACTIVE;
5136 else if ((cmd == BNX2X_Q_CMD_EMPTY) ||
5137 (cmd == BNX2X_Q_CMD_UPDATE_TPA))
5138 next_state = BNX2X_Q_STATE_INACTIVE;
5140 else if (cmd == BNX2X_Q_CMD_HALT)
5141 next_state = BNX2X_Q_STATE_STOPPED;
5143 else if (cmd == BNX2X_Q_CMD_UPDATE) {
5144 /* If "active" state change is requested, update the
5145 * state accordingly.
5147 if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG,
5148 &update_params->update_flags) &&
5149 test_bit(BNX2X_Q_UPDATE_ACTIVATE,
5150 &update_params->update_flags)){
5151 if (o->num_tx_only == 0)
5152 next_state = BNX2X_Q_STATE_ACTIVE;
5153 else /* tx only queues exist for this queue */
5154 next_state = BNX2X_Q_STATE_MULTI_COS;
5156 next_state = BNX2X_Q_STATE_INACTIVE;
5160 case BNX2X_Q_STATE_STOPPED:
5161 if (cmd == BNX2X_Q_CMD_TERMINATE)
5162 next_state = BNX2X_Q_STATE_TERMINATED;
5165 case BNX2X_Q_STATE_TERMINATED:
5166 if (cmd == BNX2X_Q_CMD_CFC_DEL)
5167 next_state = BNX2X_Q_STATE_RESET;
5171 BNX2X_ERR("Illegal state: %d\n", state);
5174 /* Transition is assured */
5175 if (next_state != BNX2X_Q_STATE_MAX) {
5176 DP(BNX2X_MSG_SP, "Good state transition: %d(%d)->%d\n",
5177 state, cmd, next_state);
5178 o->next_state = next_state;
5179 o->next_tx_only = next_tx_only;
5183 DP(BNX2X_MSG_SP, "Bad state transition request: %d %d\n", state, cmd);
5188 void bnx2x_init_queue_obj(struct bnx2x *bp,
5189 struct bnx2x_queue_sp_obj *obj,
5190 u8 cl_id, u32 *cids, u8 cid_cnt, u8 func_id,
5192 dma_addr_t rdata_mapping, unsigned long type)
5194 memset(obj, 0, sizeof(*obj));
5196 /* We support only BNX2X_MULTI_TX_COS Tx CoS at the moment */
5197 BUG_ON(BNX2X_MULTI_TX_COS < cid_cnt);
5199 memcpy(obj->cids, cids, sizeof(obj->cids[0]) * cid_cnt);
5200 obj->max_cos = cid_cnt;
5202 obj->func_id = func_id;
5204 obj->rdata_mapping = rdata_mapping;
5206 obj->next_state = BNX2X_Q_STATE_MAX;
5208 if (CHIP_IS_E1x(bp))
5209 obj->send_cmd = bnx2x_queue_send_cmd_e1x;
5211 obj->send_cmd = bnx2x_queue_send_cmd_e2;
5213 obj->check_transition = bnx2x_queue_chk_transition;
5215 obj->complete_cmd = bnx2x_queue_comp_cmd;
5216 obj->wait_comp = bnx2x_queue_wait_comp;
5217 obj->set_pending = bnx2x_queue_set_pending;
5220 /* return a queue object's logical state*/
5221 int bnx2x_get_q_logical_state(struct bnx2x *bp,
5222 struct bnx2x_queue_sp_obj *obj)
5224 switch (obj->state) {
5225 case BNX2X_Q_STATE_ACTIVE:
5226 case BNX2X_Q_STATE_MULTI_COS:
5227 return BNX2X_Q_LOGICAL_STATE_ACTIVE;
5228 case BNX2X_Q_STATE_RESET:
5229 case BNX2X_Q_STATE_INITIALIZED:
5230 case BNX2X_Q_STATE_MCOS_TERMINATED:
5231 case BNX2X_Q_STATE_INACTIVE:
5232 case BNX2X_Q_STATE_STOPPED:
5233 case BNX2X_Q_STATE_TERMINATED:
5234 case BNX2X_Q_STATE_FLRED:
5235 return BNX2X_Q_LOGICAL_STATE_STOPPED;
5241 /********************** Function state object *********************************/
5242 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
5243 struct bnx2x_func_sp_obj *o)
5245 /* in the middle of transaction - return INVALID state */
5247 return BNX2X_F_STATE_MAX;
5250 * unsure the order of reading of o->pending and o->state
5251 * o->pending should be read first
5258 static int bnx2x_func_wait_comp(struct bnx2x *bp,
5259 struct bnx2x_func_sp_obj *o,
5260 enum bnx2x_func_cmd cmd)
5262 return bnx2x_state_wait(bp, cmd, &o->pending);
5266 * bnx2x_func_state_change_comp - complete the state machine transition
5268 * @bp: device handle
5272 * Called on state change transition. Completes the state
5273 * machine transition only - no HW interaction.
5275 static inline int bnx2x_func_state_change_comp(struct bnx2x *bp,
5276 struct bnx2x_func_sp_obj *o,
5277 enum bnx2x_func_cmd cmd)
5279 unsigned long cur_pending = o->pending;
5281 if (!test_and_clear_bit(cmd, &cur_pending)) {
5282 BNX2X_ERR("Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\n",
5283 cmd, BP_FUNC(bp), o->state,
5284 cur_pending, o->next_state);
5289 "Completing command %d for func %d, setting state to %d\n",
5290 cmd, BP_FUNC(bp), o->next_state);
5292 o->state = o->next_state;
5293 o->next_state = BNX2X_F_STATE_MAX;
5295 /* It's important that o->state and o->next_state are
5296 * updated before o->pending.
5300 clear_bit(cmd, &o->pending);
5301 smp_mb__after_clear_bit();
5307 * bnx2x_func_comp_cmd - complete the state change command
5309 * @bp: device handle
5313 * Checks that the arrived completion is expected.
5315 static int bnx2x_func_comp_cmd(struct bnx2x *bp,
5316 struct bnx2x_func_sp_obj *o,
5317 enum bnx2x_func_cmd cmd)
5319 /* Complete the state machine part first, check if it's a
5322 int rc = bnx2x_func_state_change_comp(bp, o, cmd);
5327 * bnx2x_func_chk_transition - perform function state machine transition
5329 * @bp: device handle
5333 * It both checks if the requested command is legal in a current
5334 * state and, if it's legal, sets a `next_state' in the object
5335 * that will be used in the completion flow to set the `state'
5338 * returns 0 if a requested command is a legal transition,
5339 * -EINVAL otherwise.
5341 static int bnx2x_func_chk_transition(struct bnx2x *bp,
5342 struct bnx2x_func_sp_obj *o,
5343 struct bnx2x_func_state_params *params)
5345 enum bnx2x_func_state state = o->state, next_state = BNX2X_F_STATE_MAX;
5346 enum bnx2x_func_cmd cmd = params->cmd;
5349 * Forget all pending for completion commands if a driver only state
5350 * transition has been requested.
5352 if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) {
5354 o->next_state = BNX2X_F_STATE_MAX;
5358 * Don't allow a next state transition if we are in the middle of
5365 case BNX2X_F_STATE_RESET:
5366 if (cmd == BNX2X_F_CMD_HW_INIT)
5367 next_state = BNX2X_F_STATE_INITIALIZED;
5370 case BNX2X_F_STATE_INITIALIZED:
5371 if (cmd == BNX2X_F_CMD_START)
5372 next_state = BNX2X_F_STATE_STARTED;
5374 else if (cmd == BNX2X_F_CMD_HW_RESET)
5375 next_state = BNX2X_F_STATE_RESET;
5378 case BNX2X_F_STATE_STARTED:
5379 if (cmd == BNX2X_F_CMD_STOP)
5380 next_state = BNX2X_F_STATE_INITIALIZED;
5381 /* afex ramrods can be sent only in started mode, and only
5382 * if not pending for function_stop ramrod completion
5383 * for these events - next state remained STARTED.
5385 else if ((cmd == BNX2X_F_CMD_AFEX_UPDATE) &&
5386 (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5387 next_state = BNX2X_F_STATE_STARTED;
5389 else if ((cmd == BNX2X_F_CMD_AFEX_VIFLISTS) &&
5390 (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5391 next_state = BNX2X_F_STATE_STARTED;
5393 /* Switch_update ramrod can be sent in either started or
5394 * tx_stopped state, and it doesn't change the state.
5396 else if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) &&
5397 (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5398 next_state = BNX2X_F_STATE_STARTED;
5400 else if (cmd == BNX2X_F_CMD_TX_STOP)
5401 next_state = BNX2X_F_STATE_TX_STOPPED;
5404 case BNX2X_F_STATE_TX_STOPPED:
5405 if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) &&
5406 (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5407 next_state = BNX2X_F_STATE_TX_STOPPED;
5409 else if (cmd == BNX2X_F_CMD_TX_START)
5410 next_state = BNX2X_F_STATE_STARTED;
5414 BNX2X_ERR("Unknown state: %d\n", state);
5417 /* Transition is assured */
5418 if (next_state != BNX2X_F_STATE_MAX) {
5419 DP(BNX2X_MSG_SP, "Good function state transition: %d(%d)->%d\n",
5420 state, cmd, next_state);
5421 o->next_state = next_state;
5425 DP(BNX2X_MSG_SP, "Bad function state transition request: %d %d\n",
5432 * bnx2x_func_init_func - performs HW init at function stage
5434 * @bp: device handle
5437 * Init HW when the current phase is
5438 * FW_MSG_CODE_DRV_LOAD_FUNCTION: initialize only FUNCTION-only
5441 static inline int bnx2x_func_init_func(struct bnx2x *bp,
5442 const struct bnx2x_func_sp_drv_ops *drv)
5444 return drv->init_hw_func(bp);
5448 * bnx2x_func_init_port - performs HW init at port stage
5450 * @bp: device handle
5453 * Init HW when the current phase is
5454 * FW_MSG_CODE_DRV_LOAD_PORT: initialize PORT-only and
5455 * FUNCTION-only HW blocks.
5458 static inline int bnx2x_func_init_port(struct bnx2x *bp,
5459 const struct bnx2x_func_sp_drv_ops *drv)
5461 int rc = drv->init_hw_port(bp);
5465 return bnx2x_func_init_func(bp, drv);
5469 * bnx2x_func_init_cmn_chip - performs HW init at chip-common stage
5471 * @bp: device handle
5474 * Init HW when the current phase is
5475 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON_CHIP,
5476 * PORT-only and FUNCTION-only HW blocks.
5478 static inline int bnx2x_func_init_cmn_chip(struct bnx2x *bp,
5479 const struct bnx2x_func_sp_drv_ops *drv)
5481 int rc = drv->init_hw_cmn_chip(bp);
5485 return bnx2x_func_init_port(bp, drv);
5489 * bnx2x_func_init_cmn - performs HW init at common stage
5491 * @bp: device handle
5494 * Init HW when the current phase is
5495 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON,
5496 * PORT-only and FUNCTION-only HW blocks.
5498 static inline int bnx2x_func_init_cmn(struct bnx2x *bp,
5499 const struct bnx2x_func_sp_drv_ops *drv)
5501 int rc = drv->init_hw_cmn(bp);
5505 return bnx2x_func_init_port(bp, drv);
5508 static int bnx2x_func_hw_init(struct bnx2x *bp,
5509 struct bnx2x_func_state_params *params)
5511 u32 load_code = params->params.hw_init.load_phase;
5512 struct bnx2x_func_sp_obj *o = params->f_obj;
5513 const struct bnx2x_func_sp_drv_ops *drv = o->drv;
5516 DP(BNX2X_MSG_SP, "function %d load_code %x\n",
5517 BP_ABS_FUNC(bp), load_code);
5519 /* Prepare buffers for unzipping the FW */
5520 rc = drv->gunzip_init(bp);
5525 rc = drv->init_fw(bp);
5527 BNX2X_ERR("Error loading firmware\n");
5531 /* Handle the beginning of COMMON_XXX pases separatelly... */
5532 switch (load_code) {
5533 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5534 rc = bnx2x_func_init_cmn_chip(bp, drv);
5539 case FW_MSG_CODE_DRV_LOAD_COMMON:
5540 rc = bnx2x_func_init_cmn(bp, drv);
5545 case FW_MSG_CODE_DRV_LOAD_PORT:
5546 rc = bnx2x_func_init_port(bp, drv);
5551 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5552 rc = bnx2x_func_init_func(bp, drv);
5558 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5563 drv->gunzip_end(bp);
5565 /* In case of success, complete the comand immediatelly: no ramrods
5569 o->complete_cmd(bp, o, BNX2X_F_CMD_HW_INIT);
5575 * bnx2x_func_reset_func - reset HW at function stage
5577 * @bp: device handle
5580 * Reset HW at FW_MSG_CODE_DRV_UNLOAD_FUNCTION stage: reset only
5581 * FUNCTION-only HW blocks.
5583 static inline void bnx2x_func_reset_func(struct bnx2x *bp,
5584 const struct bnx2x_func_sp_drv_ops *drv)
5586 drv->reset_hw_func(bp);
5590 * bnx2x_func_reset_port - reser HW at port stage
5592 * @bp: device handle
5595 * Reset HW at FW_MSG_CODE_DRV_UNLOAD_PORT stage: reset
5596 * FUNCTION-only and PORT-only HW blocks.
5600 * It's important to call reset_port before reset_func() as the last thing
5601 * reset_func does is pf_disable() thus disabling PGLUE_B, which
5602 * makes impossible any DMAE transactions.
5604 static inline void bnx2x_func_reset_port(struct bnx2x *bp,
5605 const struct bnx2x_func_sp_drv_ops *drv)
5607 drv->reset_hw_port(bp);
5608 bnx2x_func_reset_func(bp, drv);
5612 * bnx2x_func_reset_cmn - reser HW at common stage
5614 * @bp: device handle
5617 * Reset HW at FW_MSG_CODE_DRV_UNLOAD_COMMON and
5618 * FW_MSG_CODE_DRV_UNLOAD_COMMON_CHIP stages: reset COMMON,
5619 * COMMON_CHIP, FUNCTION-only and PORT-only HW blocks.
5621 static inline void bnx2x_func_reset_cmn(struct bnx2x *bp,
5622 const struct bnx2x_func_sp_drv_ops *drv)
5624 bnx2x_func_reset_port(bp, drv);
5625 drv->reset_hw_cmn(bp);
5629 static inline int bnx2x_func_hw_reset(struct bnx2x *bp,
5630 struct bnx2x_func_state_params *params)
5632 u32 reset_phase = params->params.hw_reset.reset_phase;
5633 struct bnx2x_func_sp_obj *o = params->f_obj;
5634 const struct bnx2x_func_sp_drv_ops *drv = o->drv;
5636 DP(BNX2X_MSG_SP, "function %d reset_phase %x\n", BP_ABS_FUNC(bp),
5639 switch (reset_phase) {
5640 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
5641 bnx2x_func_reset_cmn(bp, drv);
5643 case FW_MSG_CODE_DRV_UNLOAD_PORT:
5644 bnx2x_func_reset_port(bp, drv);
5646 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
5647 bnx2x_func_reset_func(bp, drv);
5650 BNX2X_ERR("Unknown reset_phase (0x%x) from MCP\n",
5655 /* Complete the comand immediatelly: no ramrods have been sent. */
5656 o->complete_cmd(bp, o, BNX2X_F_CMD_HW_RESET);
5661 static inline int bnx2x_func_send_start(struct bnx2x *bp,
5662 struct bnx2x_func_state_params *params)
5664 struct bnx2x_func_sp_obj *o = params->f_obj;
5665 struct function_start_data *rdata =
5666 (struct function_start_data *)o->rdata;
5667 dma_addr_t data_mapping = o->rdata_mapping;
5668 struct bnx2x_func_start_params *start_params = ¶ms->params.start;
5670 memset(rdata, 0, sizeof(*rdata));
5672 /* Fill the ramrod data with provided parameters */
5673 rdata->function_mode = (u8)start_params->mf_mode;
5674 rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag);
5675 rdata->path_id = BP_PATH(bp);
5676 rdata->network_cos_mode = start_params->network_cos_mode;
5679 * No need for an explicit memory barrier here as long we would
5680 * need to ensure the ordering of writing to the SPQ element
5681 * and updating of the SPQ producer which involves a memory
5682 * read and we will have to put a full memory barrier there
5683 * (inside bnx2x_sp_post()).
5686 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0,
5687 U64_HI(data_mapping),
5688 U64_LO(data_mapping), NONE_CONNECTION_TYPE);
5691 static inline int bnx2x_func_send_switch_update(struct bnx2x *bp,
5692 struct bnx2x_func_state_params *params)
5694 struct bnx2x_func_sp_obj *o = params->f_obj;
5695 struct function_update_data *rdata =
5696 (struct function_update_data *)o->rdata;
5697 dma_addr_t data_mapping = o->rdata_mapping;
5698 struct bnx2x_func_switch_update_params *switch_update_params =
5699 ¶ms->params.switch_update;
5701 memset(rdata, 0, sizeof(*rdata));
5703 /* Fill the ramrod data with provided parameters */
5704 rdata->tx_switch_suspend_change_flg = 1;
5705 rdata->tx_switch_suspend = switch_update_params->suspend;
5706 rdata->echo = SWITCH_UPDATE;
5708 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
5709 U64_HI(data_mapping),
5710 U64_LO(data_mapping), NONE_CONNECTION_TYPE);
5713 static inline int bnx2x_func_send_afex_update(struct bnx2x *bp,
5714 struct bnx2x_func_state_params *params)
5716 struct bnx2x_func_sp_obj *o = params->f_obj;
5717 struct function_update_data *rdata =
5718 (struct function_update_data *)o->afex_rdata;
5719 dma_addr_t data_mapping = o->afex_rdata_mapping;
5720 struct bnx2x_func_afex_update_params *afex_update_params =
5721 ¶ms->params.afex_update;
5723 memset(rdata, 0, sizeof(*rdata));
5725 /* Fill the ramrod data with provided parameters */
5726 rdata->vif_id_change_flg = 1;
5727 rdata->vif_id = cpu_to_le16(afex_update_params->vif_id);
5728 rdata->afex_default_vlan_change_flg = 1;
5729 rdata->afex_default_vlan =
5730 cpu_to_le16(afex_update_params->afex_default_vlan);
5731 rdata->allowed_priorities_change_flg = 1;
5732 rdata->allowed_priorities = afex_update_params->allowed_priorities;
5733 rdata->echo = AFEX_UPDATE;
5735 /* No need for an explicit memory barrier here as long we would
5736 * need to ensure the ordering of writing to the SPQ element
5737 * and updating of the SPQ producer which involves a memory
5738 * read and we will have to put a full memory barrier there
5739 * (inside bnx2x_sp_post()).
5742 "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x\n",
5744 rdata->afex_default_vlan, rdata->allowed_priorities);
5746 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
5747 U64_HI(data_mapping),
5748 U64_LO(data_mapping), NONE_CONNECTION_TYPE);
5752 inline int bnx2x_func_send_afex_viflists(struct bnx2x *bp,
5753 struct bnx2x_func_state_params *params)
5755 struct bnx2x_func_sp_obj *o = params->f_obj;
5756 struct afex_vif_list_ramrod_data *rdata =
5757 (struct afex_vif_list_ramrod_data *)o->afex_rdata;
5758 struct bnx2x_func_afex_viflists_params *afex_vif_params =
5759 ¶ms->params.afex_viflists;
5760 u64 *p_rdata = (u64 *)rdata;
5762 memset(rdata, 0, sizeof(*rdata));
5764 /* Fill the ramrod data with provided parameters */
5765 rdata->vif_list_index = cpu_to_le16(afex_vif_params->vif_list_index);
5766 rdata->func_bit_map = afex_vif_params->func_bit_map;
5767 rdata->afex_vif_list_command = afex_vif_params->afex_vif_list_command;
5768 rdata->func_to_clear = afex_vif_params->func_to_clear;
5770 /* send in echo type of sub command */
5771 rdata->echo = afex_vif_params->afex_vif_list_command;
5773 /* No need for an explicit memory barrier here as long we would
5774 * need to ensure the ordering of writing to the SPQ element
5775 * and updating of the SPQ producer which involves a memory
5776 * read and we will have to put a full memory barrier there
5777 * (inside bnx2x_sp_post()).
5780 DP(BNX2X_MSG_SP, "afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x\n",
5781 rdata->afex_vif_list_command, rdata->vif_list_index,
5782 rdata->func_bit_map, rdata->func_to_clear);
5784 /* this ramrod sends data directly and not through DMA mapping */
5785 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 0,
5786 U64_HI(*p_rdata), U64_LO(*p_rdata),
5787 NONE_CONNECTION_TYPE);
5790 static inline int bnx2x_func_send_stop(struct bnx2x *bp,
5791 struct bnx2x_func_state_params *params)
5793 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0,
5794 NONE_CONNECTION_TYPE);
5797 static inline int bnx2x_func_send_tx_stop(struct bnx2x *bp,
5798 struct bnx2x_func_state_params *params)
5800 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 0, 0, 0,
5801 NONE_CONNECTION_TYPE);
5803 static inline int bnx2x_func_send_tx_start(struct bnx2x *bp,
5804 struct bnx2x_func_state_params *params)
5806 struct bnx2x_func_sp_obj *o = params->f_obj;
5807 struct flow_control_configuration *rdata =
5808 (struct flow_control_configuration *)o->rdata;
5809 dma_addr_t data_mapping = o->rdata_mapping;
5810 struct bnx2x_func_tx_start_params *tx_start_params =
5811 ¶ms->params.tx_start;
5814 memset(rdata, 0, sizeof(*rdata));
5816 rdata->dcb_enabled = tx_start_params->dcb_enabled;
5817 rdata->dcb_version = tx_start_params->dcb_version;
5818 rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0_en;
5820 for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)
5821 rdata->traffic_type_to_priority_cos[i] =
5822 tx_start_params->traffic_type_to_priority_cos[i];
5824 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_START_TRAFFIC, 0,
5825 U64_HI(data_mapping),
5826 U64_LO(data_mapping), NONE_CONNECTION_TYPE);
5829 static int bnx2x_func_send_cmd(struct bnx2x *bp,
5830 struct bnx2x_func_state_params *params)
5832 switch (params->cmd) {
5833 case BNX2X_F_CMD_HW_INIT:
5834 return bnx2x_func_hw_init(bp, params);
5835 case BNX2X_F_CMD_START:
5836 return bnx2x_func_send_start(bp, params);
5837 case BNX2X_F_CMD_STOP:
5838 return bnx2x_func_send_stop(bp, params);
5839 case BNX2X_F_CMD_HW_RESET:
5840 return bnx2x_func_hw_reset(bp, params);
5841 case BNX2X_F_CMD_AFEX_UPDATE:
5842 return bnx2x_func_send_afex_update(bp, params);
5843 case BNX2X_F_CMD_AFEX_VIFLISTS:
5844 return bnx2x_func_send_afex_viflists(bp, params);
5845 case BNX2X_F_CMD_TX_STOP:
5846 return bnx2x_func_send_tx_stop(bp, params);
5847 case BNX2X_F_CMD_TX_START:
5848 return bnx2x_func_send_tx_start(bp, params);
5849 case BNX2X_F_CMD_SWITCH_UPDATE:
5850 return bnx2x_func_send_switch_update(bp, params);
5852 BNX2X_ERR("Unknown command: %d\n", params->cmd);
5857 void bnx2x_init_func_obj(struct bnx2x *bp,
5858 struct bnx2x_func_sp_obj *obj,
5859 void *rdata, dma_addr_t rdata_mapping,
5860 void *afex_rdata, dma_addr_t afex_rdata_mapping,
5861 struct bnx2x_func_sp_drv_ops *drv_iface)
5863 memset(obj, 0, sizeof(*obj));
5865 mutex_init(&obj->one_pending_mutex);
5868 obj->rdata_mapping = rdata_mapping;
5869 obj->afex_rdata = afex_rdata;
5870 obj->afex_rdata_mapping = afex_rdata_mapping;
5871 obj->send_cmd = bnx2x_func_send_cmd;
5872 obj->check_transition = bnx2x_func_chk_transition;
5873 obj->complete_cmd = bnx2x_func_comp_cmd;
5874 obj->wait_comp = bnx2x_func_wait_comp;
5876 obj->drv = drv_iface;
5880 * bnx2x_func_state_change - perform Function state change transition
5882 * @bp: device handle
5883 * @params: parameters to perform the transaction
5885 * returns 0 in case of successfully completed transition,
5886 * negative error code in case of failure, positive
5887 * (EBUSY) value if there is a completion to that is
5888 * still pending (possible only if RAMROD_COMP_WAIT is
5889 * not set in params->ramrod_flags for asynchronous
5892 int bnx2x_func_state_change(struct bnx2x *bp,
5893 struct bnx2x_func_state_params *params)
5895 struct bnx2x_func_sp_obj *o = params->f_obj;
5897 enum bnx2x_func_cmd cmd = params->cmd;
5898 unsigned long *pending = &o->pending;
5900 mutex_lock(&o->one_pending_mutex);
5902 /* Check that the requested transition is legal */
5903 rc = o->check_transition(bp, o, params);
5904 if ((rc == -EBUSY) &&
5905 (test_bit(RAMROD_RETRY, ¶ms->ramrod_flags))) {
5906 while ((rc == -EBUSY) && (--cnt > 0)) {
5907 mutex_unlock(&o->one_pending_mutex);
5909 mutex_lock(&o->one_pending_mutex);
5910 rc = o->check_transition(bp, o, params);
5913 mutex_unlock(&o->one_pending_mutex);
5914 BNX2X_ERR("timeout waiting for previous ramrod completion\n");
5918 mutex_unlock(&o->one_pending_mutex);
5922 /* Set "pending" bit */
5923 set_bit(cmd, pending);
5925 /* Don't send a command if only driver cleanup was requested */
5926 if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) {
5927 bnx2x_func_state_change_comp(bp, o, cmd);
5928 mutex_unlock(&o->one_pending_mutex);
5931 rc = o->send_cmd(bp, params);
5933 mutex_unlock(&o->one_pending_mutex);
5936 o->next_state = BNX2X_F_STATE_MAX;
5937 clear_bit(cmd, pending);
5938 smp_mb__after_clear_bit();
5942 if (test_bit(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) {
5943 rc = o->wait_comp(bp, o, cmd);
5951 return !!test_bit(cmd, pending);