drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/types.h>
  17 #include <linux/fcntl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/string.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_platform.h>
  33 #include <net/arp.h>
  34
  35 #include <linux/mii.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/in.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/phy.h>
  45
  46 #include <asm/unaligned.h>
  47
  48 #include "bcmgenet.h"
  49
  50 /* Maximum number of hardware queues, downsized if needed */
  51 #define GENET_MAX_MQ_CNT        4
  52
  53 /* Default highest priority queue for multi queue support */
  54 #define GENET_Q0_PRIORITY       0
  55
  56 #define GENET_DEFAULT_BD_CNT    \
  57         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
  58
  59 #define RX_BUF_LENGTH           2048
  60 #define SKB_ALIGNMENT           32
  61
  62 /* Tx/Rx DMA register offset, skip 256 descriptors */
  63 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  64 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  65
  66 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  67                                 TOTAL_DESC * DMA_DESC_SIZE)
  68
  69 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  70                                 TOTAL_DESC * DMA_DESC_SIZE)
  71
  72 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  73                                              void __iomem *d, u32 value)
  74 {
  75         __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
  76 }
  77
  78 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
  79                                             void __iomem *d)
  80 {
  81         return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
  82 }
  83
  84 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
  85                                     void __iomem *d,
  86                                     dma_addr_t addr)
  87 {
  88         __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
  89
  90         /* Register writes to GISB bus can take couple hundred nanoseconds
  91          * and are done for each packet, save these expensive writes unless
  92          * the platform is explicitly configured for 64-bits/LPAE.
  93          */
  94 #ifdef CONFIG_PHYS_ADDR_T_64BIT
  95         if (priv->hw_params->flags & GENET_HAS_40BITS)
  96                 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
  97 #endif
  98 }
  99
 100 /* Combined address + length/status setter */
 101 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 102                                void __iomem *d, dma_addr_t addr, u32 val)
 103 {
 104         dmadesc_set_length_status(priv, d, val);
 105         dmadesc_set_addr(priv, d, addr);
 106 }
 107
 108 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 109                                           void __iomem *d)
 110 {
 111         dma_addr_t addr;
 112
 113         addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
 114
 115         /* Register writes to GISB bus can take couple hundred nanoseconds
 116          * and are done for each packet, save these expensive writes unless
 117          * the platform is explicitly configured for 64-bits/LPAE.
 118          */
 119 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 120         if (priv->hw_params->flags & GENET_HAS_40BITS)
 121                 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 122 #endif
 123         return addr;
 124 }
 125
 126 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 127
 128 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 129                                 NETIF_MSG_LINK)
 130
 131 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 132 {
 133         if (GENET_IS_V1(priv))
 134                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 135         else
 136                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 137 }
 138
 139 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 140 {
 141         if (GENET_IS_V1(priv))
 142                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 143         else
 144                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 145 }
 146
 147 /* These macros are defined to deal with register map change
 148  * between GENET1.1 and GENET2. Only those currently being used
 149  * by driver are defined.
 150  */
 151 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 152 {
 153         if (GENET_IS_V1(priv))
 154                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 155         else
 156                 return __raw_readl(priv->base +
 157                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 158 }
 159
 160 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 161 {
 162         if (GENET_IS_V1(priv))
 163                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 164         else
 165                 __raw_writel(val, priv->base +
 166                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 167 }
 168
 169 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 170 {
 171         if (GENET_IS_V1(priv))
 172                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 173         else
 174                 return __raw_readl(priv->base +
 175                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 176 }
 177
 178 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 179 {
 180         if (GENET_IS_V1(priv))
 181                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 182         else
 183                 __raw_writel(val, priv->base +
 184                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 185 }
 186
 187 /* RX/TX DMA register accessors */
 188 enum dma_reg {
 189         DMA_RING_CFG = 0,
 190         DMA_CTRL,
 191         DMA_STATUS,
 192         DMA_SCB_BURST_SIZE,
 193         DMA_ARB_CTRL,
 194         DMA_PRIORITY_0,
 195         DMA_PRIORITY_1,
 196         DMA_PRIORITY_2,
 197 };
 198
 199 static const u8 bcmgenet_dma_regs_v3plus[] = {
 200         [DMA_RING_CFG]          = 0x00,
 201         [DMA_CTRL]              = 0x04,
 202         [DMA_STATUS]            = 0x08,
 203         [DMA_SCB_BURST_SIZE]    = 0x0C,
 204         [DMA_ARB_CTRL]          = 0x2C,
 205         [DMA_PRIORITY_0]        = 0x30,
 206         [DMA_PRIORITY_1]        = 0x34,
 207         [DMA_PRIORITY_2]        = 0x38,
 208 };
 209
 210 static const u8 bcmgenet_dma_regs_v2[] = {
 211         [DMA_RING_CFG]          = 0x00,
 212         [DMA_CTRL]              = 0x04,
 213         [DMA_STATUS]            = 0x08,
 214         [DMA_SCB_BURST_SIZE]    = 0x0C,
 215         [DMA_ARB_CTRL]          = 0x30,
 216         [DMA_PRIORITY_0]        = 0x34,
 217         [DMA_PRIORITY_1]        = 0x38,
 218         [DMA_PRIORITY_2]        = 0x3C,
 219 };
 220
 221 static const u8 bcmgenet_dma_regs_v1[] = {
 222         [DMA_CTRL]              = 0x00,
 223         [DMA_STATUS]            = 0x04,
 224         [DMA_SCB_BURST_SIZE]    = 0x0C,
 225         [DMA_ARB_CTRL]          = 0x30,
 226         [DMA_PRIORITY_0]        = 0x34,
 227         [DMA_PRIORITY_1]        = 0x38,
 228         [DMA_PRIORITY_2]        = 0x3C,
 229 };
 230
 231 /* Set at runtime once bcmgenet version is known */
 232 static const u8 *bcmgenet_dma_regs;
 233
 234 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 235 {
 236         return netdev_priv(dev_get_drvdata(dev));
 237 }
 238
 239 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 240                                       enum dma_reg r)
 241 {
 242         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 243                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 244 }
 245
 246 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 247                                         u32 val, enum dma_reg r)
 248 {
 249         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 250                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 251 }
 252
 253 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 254                                       enum dma_reg r)
 255 {
 256         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 257                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 258 }
 259
 260 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 261                                         u32 val, enum dma_reg r)
 262 {
 263         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 264                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 265 }
 266
 267 /* RDMA/TDMA ring registers and accessors
 268  * we merge the common fields and just prefix with T/D the registers
 269  * having different meaning depending on the direction
 270  */
 271 enum dma_ring_reg {
 272         TDMA_READ_PTR = 0,
 273         RDMA_WRITE_PTR = TDMA_READ_PTR,
 274         TDMA_READ_PTR_HI,
 275         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 276         TDMA_CONS_INDEX,
 277         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 278         TDMA_PROD_INDEX,
 279         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 280         DMA_RING_BUF_SIZE,
 281         DMA_START_ADDR,
 282         DMA_START_ADDR_HI,
 283         DMA_END_ADDR,
 284         DMA_END_ADDR_HI,
 285         DMA_MBUF_DONE_THRESH,
 286         TDMA_FLOW_PERIOD,
 287         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 288         TDMA_WRITE_PTR,
 289         RDMA_READ_PTR = TDMA_WRITE_PTR,
 290         TDMA_WRITE_PTR_HI,
 291         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 292 };
 293
 294 /* GENET v4 supports 40-bits pointer addressing
 295  * for obvious reasons the LO and HI word parts
 296  * are contiguous, but this offsets the other
 297  * registers.
 298  */
 299 static const u8 genet_dma_ring_regs_v4[] = {
 300         [TDMA_READ_PTR]                 = 0x00,
 301         [TDMA_READ_PTR_HI]              = 0x04,
 302         [TDMA_CONS_INDEX]               = 0x08,
 303         [TDMA_PROD_INDEX]               = 0x0C,
 304         [DMA_RING_BUF_SIZE]             = 0x10,
 305         [DMA_START_ADDR]                = 0x14,
 306         [DMA_START_ADDR_HI]             = 0x18,
 307         [DMA_END_ADDR]                  = 0x1C,
 308         [DMA_END_ADDR_HI]               = 0x20,
 309         [DMA_MBUF_DONE_THRESH]          = 0x24,
 310         [TDMA_FLOW_PERIOD]              = 0x28,
 311         [TDMA_WRITE_PTR]                = 0x2C,
 312         [TDMA_WRITE_PTR_HI]             = 0x30,
 313 };
 314
 315 static const u8 genet_dma_ring_regs_v123[] = {
 316         [TDMA_READ_PTR]                 = 0x00,
 317         [TDMA_CONS_INDEX]               = 0x04,
 318         [TDMA_PROD_INDEX]               = 0x08,
 319         [DMA_RING_BUF_SIZE]             = 0x0C,
 320         [DMA_START_ADDR]                = 0x10,
 321         [DMA_END_ADDR]                  = 0x14,
 322         [DMA_MBUF_DONE_THRESH]          = 0x18,
 323         [TDMA_FLOW_PERIOD]              = 0x1C,
 324         [TDMA_WRITE_PTR]                = 0x20,
 325 };
 326
 327 /* Set at runtime once GENET version is known */
 328 static const u8 *genet_dma_ring_regs;
 329
 330 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 331                                            unsigned int ring,
 332                                            enum dma_ring_reg r)
 333 {
 334         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 335                         (DMA_RING_SIZE * ring) +
 336                         genet_dma_ring_regs[r]);
 337 }
 338
 339 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 340                                              unsigned int ring, u32 val,
 341                                              enum dma_ring_reg r)
 342 {
 343         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 344                         (DMA_RING_SIZE * ring) +
 345                         genet_dma_ring_regs[r]);
 346 }
 347
 348 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 349                                            unsigned int ring,
 350                                            enum dma_ring_reg r)
 351 {
 352         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 353                         (DMA_RING_SIZE * ring) +
 354                         genet_dma_ring_regs[r]);
 355 }
 356
 357 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 358                                              unsigned int ring, u32 val,
 359                                              enum dma_ring_reg r)
 360 {
 361         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 362                         (DMA_RING_SIZE * ring) +
 363                         genet_dma_ring_regs[r]);
 364 }
 365
 366 static int bcmgenet_get_settings(struct net_device *dev,
 367                                  struct ethtool_cmd *cmd)
 368 {
 369         struct bcmgenet_priv *priv = netdev_priv(dev);
 370
 371         if (!netif_running(dev))
 372                 return -EINVAL;
 373
 374         if (!priv->phydev)
 375                 return -ENODEV;
 376
 377         return phy_ethtool_gset(priv->phydev, cmd);
 378 }
 379
 380 static int bcmgenet_set_settings(struct net_device *dev,
 381                                  struct ethtool_cmd *cmd)
 382 {
 383         struct bcmgenet_priv *priv = netdev_priv(dev);
 384
 385         if (!netif_running(dev))
 386                 return -EINVAL;
 387
 388         if (!priv->phydev)
 389                 return -ENODEV;
 390
 391         return phy_ethtool_sset(priv->phydev, cmd);
 392 }
 393
 394 static int bcmgenet_set_rx_csum(struct net_device *dev,
 395                                 netdev_features_t wanted)
 396 {
 397         struct bcmgenet_priv *priv = netdev_priv(dev);
 398         u32 rbuf_chk_ctrl;
 399         bool rx_csum_en;
 400
 401         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 402
 403         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 404
 405         /* enable rx checksumming */
 406         if (rx_csum_en)
 407                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 408         else
 409                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 410         priv->desc_rxchk_en = rx_csum_en;
 411
 412         /* If UniMAC forwards CRC, we need to skip over it to get
 413          * a valid CHK bit to be set in the per-packet status word
 414         */
 415         if (rx_csum_en && priv->crc_fwd_en)
 416                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 417         else
 418                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 419
 420         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 421
 422         return 0;
 423 }
 424
 425 static int bcmgenet_set_tx_csum(struct net_device *dev,
 426                                 netdev_features_t wanted)
 427 {
 428         struct bcmgenet_priv *priv = netdev_priv(dev);
 429         bool desc_64b_en;
 430         u32 tbuf_ctrl, rbuf_ctrl;
 431
 432         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 433         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 434
 435         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 436
 437         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 438         if (desc_64b_en) {
 439                 tbuf_ctrl |= RBUF_64B_EN;
 440                 rbuf_ctrl |= RBUF_64B_EN;
 441         } else {
 442                 tbuf_ctrl &= ~RBUF_64B_EN;
 443                 rbuf_ctrl &= ~RBUF_64B_EN;
 444         }
 445         priv->desc_64b_en = desc_64b_en;
 446
 447         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 448         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 449
 450         return 0;
 451 }
 452
 453 static int bcmgenet_set_features(struct net_device *dev,
 454                                  netdev_features_t features)
 455 {
 456         netdev_features_t changed = features ^ dev->features;
 457         netdev_features_t wanted = dev->wanted_features;
 458         int ret = 0;
 459
 460         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 461                 ret = bcmgenet_set_tx_csum(dev, wanted);
 462         if (changed & (NETIF_F_RXCSUM))
 463                 ret = bcmgenet_set_rx_csum(dev, wanted);
 464
 465         return ret;
 466 }
 467
 468 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 469 {
 470         struct bcmgenet_priv *priv = netdev_priv(dev);
 471
 472         return priv->msg_enable;
 473 }
 474
 475 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 476 {
 477         struct bcmgenet_priv *priv = netdev_priv(dev);
 478
 479         priv->msg_enable = level;
 480 }
 481
 482 /* standard ethtool support functions. */
 483 enum bcmgenet_stat_type {
 484         BCMGENET_STAT_NETDEV = -1,
 485         BCMGENET_STAT_MIB_RX,
 486         BCMGENET_STAT_MIB_TX,
 487         BCMGENET_STAT_RUNT,
 488         BCMGENET_STAT_MISC,
 489 };
 490
 491 struct bcmgenet_stats {
 492         char stat_string[ETH_GSTRING_LEN];
 493         int stat_sizeof;
 494         int stat_offset;
 495         enum bcmgenet_stat_type type;
 496         /* reg offset from UMAC base for misc counters */
 497         u16 reg_offset;
 498 };
 499
 500 #define STAT_NETDEV(m) { \
 501         .stat_string = __stringify(m), \
 502         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 503         .stat_offset = offsetof(struct net_device_stats, m), \
 504         .type = BCMGENET_STAT_NETDEV, \
 505 }
 506
 507 #define STAT_GENET_MIB(str, m, _type) { \
 508         .stat_string = str, \
 509         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 510         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 511         .type = _type, \
 512 }
 513
 514 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 515 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 516 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 517
 518 #define STAT_GENET_MISC(str, m, offset) { \
 519         .stat_string = str, \
 520         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 521         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 522         .type = BCMGENET_STAT_MISC, \
 523         .reg_offset = offset, \
 524 }
 525
 526
 527 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 528  * between the end of TX stats and the beginning of the RX RUNT
 529  */
 530 #define BCMGENET_STAT_OFFSET    0xc
 531
 532 /* Hardware counters must be kept in sync because the order/offset
 533  * is important here (order in structure declaration = order in hardware)
 534  */
 535 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 536         /* general stats */
 537         STAT_NETDEV(rx_packets),
 538         STAT_NETDEV(tx_packets),
 539         STAT_NETDEV(rx_bytes),
 540         STAT_NETDEV(tx_bytes),
 541         STAT_NETDEV(rx_errors),
 542         STAT_NETDEV(tx_errors),
 543         STAT_NETDEV(rx_dropped),
 544         STAT_NETDEV(tx_dropped),
 545         STAT_NETDEV(multicast),
 546         /* UniMAC RSV counters */
 547         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 548         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 549         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 550         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 551         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 552         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 553         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 554         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 555         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 556         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 557         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 558         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 559         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 560         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 561         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 562         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 563         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 564         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 565         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 566         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 567         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 568         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 569         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 570         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 571         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 572         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 573         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 574         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 575         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 576         /* UniMAC TSV counters */
 577         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 578         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 579         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 580         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 581         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 582         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 583         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 584         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 585         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 586         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 587         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 588         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 589         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 590         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 591         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 592         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 593         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 594         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 595         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 596         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 597         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 598         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 599         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 600         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 601         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 602         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 603         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 604         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 605         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 606         /* UniMAC RUNT counters */
 607         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 608         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 609         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 610         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 611         /* Misc UniMAC counters */
 612         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 613                         UMAC_RBUF_OVFL_CNT),
 614         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
 615         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 616         STAT_GENET_MIB_RX("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 617         STAT_GENET_MIB_RX("rx_dma_failed", mib.rx_dma_failed),
 618         STAT_GENET_MIB_TX("tx_dma_failed", mib.tx_dma_failed),
 619 };
 620
 621 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 622
 623 static void bcmgenet_get_drvinfo(struct net_device *dev,
 624                                  struct ethtool_drvinfo *info)
 625 {
 626         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 627         strlcpy(info->version, "v2.0", sizeof(info->version));
 628         info->n_stats = BCMGENET_STATS_LEN;
 629 }
 630
 631 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 632 {
 633         switch (string_set) {
 634         case ETH_SS_STATS:
 635                 return BCMGENET_STATS_LEN;
 636         default:
 637                 return -EOPNOTSUPP;
 638         }
 639 }
 640
 641 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 642                                  u8 *data)
 643 {
 644         int i;
 645
 646         switch (stringset) {
 647         case ETH_SS_STATS:
 648                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 649                         memcpy(data + i * ETH_GSTRING_LEN,
 650                                bcmgenet_gstrings_stats[i].stat_string,
 651                                ETH_GSTRING_LEN);
 652                 }
 653                 break;
 654         }
 655 }
 656
 657 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 658 {
 659         int i, j = 0;
 660
 661         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 662                 const struct bcmgenet_stats *s;
 663                 u8 offset = 0;
 664                 u32 val = 0;
 665                 char *p;
 666
 667                 s = &bcmgenet_gstrings_stats[i];
 668                 switch (s->type) {
 669                 case BCMGENET_STAT_NETDEV:
 670                         continue;
 671                 case BCMGENET_STAT_MIB_RX:
 672                 case BCMGENET_STAT_MIB_TX:
 673                 case BCMGENET_STAT_RUNT:
 674                         if (s->type != BCMGENET_STAT_MIB_RX)
 675                                 offset = BCMGENET_STAT_OFFSET;
 676                         val = bcmgenet_umac_readl(priv,
 677                                                   UMAC_MIB_START + j + offset);
 678                         break;
 679                 case BCMGENET_STAT_MISC:
 680                         val = bcmgenet_umac_readl(priv, s->reg_offset);
 681                         /* clear if overflowed */
 682                         if (val == ~0)
 683                                 bcmgenet_umac_writel(priv, 0, s->reg_offset);
 684                         break;
 685                 }
 686
 687                 j += s->stat_sizeof;
 688                 p = (char *)priv + s->stat_offset;
 689                 *(u32 *)p = val;
 690         }
 691 }
 692
 693 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 694                                        struct ethtool_stats *stats,
 695                                        u64 *data)
 696 {
 697         struct bcmgenet_priv *priv = netdev_priv(dev);
 698         int i;
 699
 700         if (netif_running(dev))
 701                 bcmgenet_update_mib_counters(priv);
 702
 703         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 704                 const struct bcmgenet_stats *s;
 705                 char *p;
 706
 707                 s = &bcmgenet_gstrings_stats[i];
 708                 if (s->type == BCMGENET_STAT_NETDEV)
 709                         p = (char *)&dev->stats;
 710                 else
 711                         p = (char *)priv;
 712                 p += s->stat_offset;
 713                 data[i] = *(u32 *)p;
 714         }
 715 }
 716
 717 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
 718 {
 719         struct bcmgenet_priv *priv = netdev_priv(dev);
 720         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
 721         u32 reg;
 722
 723         if (enable && !priv->clk_eee_enabled) {
 724                 clk_prepare_enable(priv->clk_eee);
 725                 priv->clk_eee_enabled = true;
 726         }
 727
 728         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
 729         if (enable)
 730                 reg |= EEE_EN;
 731         else
 732                 reg &= ~EEE_EN;
 733         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
 734
 735         /* Enable EEE and switch to a 27Mhz clock automatically */
 736         reg = __raw_readl(priv->base + off);
 737         if (enable)
 738                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
 739         else
 740                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
 741         __raw_writel(reg, priv->base + off);
 742
 743         /* Do the same for thing for RBUF */
 744         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
 745         if (enable)
 746                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
 747         else
 748                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
 749         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
 750
 751         if (!enable && priv->clk_eee_enabled) {
 752                 clk_disable_unprepare(priv->clk_eee);
 753                 priv->clk_eee_enabled = false;
 754         }
 755
 756         priv->eee.eee_enabled = enable;
 757         priv->eee.eee_active = enable;
 758 }
 759
 760 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
 761 {
 762         struct bcmgenet_priv *priv = netdev_priv(dev);
 763         struct ethtool_eee *p = &priv->eee;
 764
 765         if (GENET_IS_V1(priv))
 766                 return -EOPNOTSUPP;
 767
 768         e->eee_enabled = p->eee_enabled;
 769         e->eee_active = p->eee_active;
 770         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
 771
 772         return phy_ethtool_get_eee(priv->phydev, e);
 773 }
 774
 775 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
 776 {
 777         struct bcmgenet_priv *priv = netdev_priv(dev);
 778         struct ethtool_eee *p = &priv->eee;
 779         int ret = 0;
 780
 781         if (GENET_IS_V1(priv))
 782                 return -EOPNOTSUPP;
 783
 784         p->eee_enabled = e->eee_enabled;
 785
 786         if (!p->eee_enabled) {
 787                 bcmgenet_eee_enable_set(dev, false);
 788         } else {
 789                 ret = phy_init_eee(priv->phydev, 0);
 790                 if (ret) {
 791                         netif_err(priv, hw, dev, "EEE initialization failed\n");
 792                         return ret;
 793                 }
 794
 795                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
 796                 bcmgenet_eee_enable_set(dev, true);
 797         }
 798
 799         return phy_ethtool_set_eee(priv->phydev, e);
 800 }
 801
 802 /* standard ethtool support functions. */
 803 static struct ethtool_ops bcmgenet_ethtool_ops = {
 804         .get_strings            = bcmgenet_get_strings,
 805         .get_sset_count         = bcmgenet_get_sset_count,
 806         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
 807         .get_settings           = bcmgenet_get_settings,
 808         .set_settings           = bcmgenet_set_settings,
 809         .get_drvinfo            = bcmgenet_get_drvinfo,
 810         .get_link               = ethtool_op_get_link,
 811         .get_msglevel           = bcmgenet_get_msglevel,
 812         .set_msglevel           = bcmgenet_set_msglevel,
 813         .get_wol                = bcmgenet_get_wol,
 814         .set_wol                = bcmgenet_set_wol,
 815         .get_eee                = bcmgenet_get_eee,
 816         .set_eee                = bcmgenet_set_eee,
 817 };
 818
 819 /* Power down the unimac, based on mode. */
 820 static void bcmgenet_power_down(struct bcmgenet_priv *priv,
 821                                 enum bcmgenet_power_mode mode)
 822 {
 823         u32 reg;
 824
 825         switch (mode) {
 826         case GENET_POWER_CABLE_SENSE:
 827                 phy_detach(priv->phydev);
 828                 break;
 829
 830         case GENET_POWER_WOL_MAGIC:
 831                 bcmgenet_wol_power_down_cfg(priv, mode);
 832                 break;
 833
 834         case GENET_POWER_PASSIVE:
 835                 /* Power down LED */
 836                 if (priv->hw_params->flags & GENET_HAS_EXT) {
 837                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 838                         reg |= (EXT_PWR_DOWN_PHY |
 839                                 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
 840                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 841                 }
 842                 break;
 843         default:
 844                 break;
 845         }
 846 }
 847
 848 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
 849                               enum bcmgenet_power_mode mode)
 850 {
 851         u32 reg;
 852
 853         if (!(priv->hw_params->flags & GENET_HAS_EXT))
 854                 return;
 855
 856         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 857
 858         switch (mode) {
 859         case GENET_POWER_PASSIVE:
 860                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
 861                                 EXT_PWR_DOWN_BIAS);
 862                 /* fallthrough */
 863         case GENET_POWER_CABLE_SENSE:
 864                 /* enable APD */
 865                 reg |= EXT_PWR_DN_EN_LD;
 866                 break;
 867         case GENET_POWER_WOL_MAGIC:
 868                 bcmgenet_wol_power_up_cfg(priv, mode);
 869                 return;
 870         default:
 871                 break;
 872         }
 873
 874         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 875
 876         if (mode == GENET_POWER_PASSIVE)
 877                 bcmgenet_mii_reset(priv->dev);
 878 }
 879
 880 /* ioctl handle special commands that are not present in ethtool. */
 881 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 882 {
 883         struct bcmgenet_priv *priv = netdev_priv(dev);
 884         int val = 0;
 885
 886         if (!netif_running(dev))
 887                 return -EINVAL;
 888
 889         switch (cmd) {
 890         case SIOCGMIIPHY:
 891         case SIOCGMIIREG:
 892         case SIOCSMIIREG:
 893                 if (!priv->phydev)
 894                         val = -ENODEV;
 895                 else
 896                         val = phy_mii_ioctl(priv->phydev, rq, cmd);
 897                 break;
 898
 899         default:
 900                 val = -EINVAL;
 901                 break;
 902         }
 903
 904         return val;
 905 }
 906
 907 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
 908                                          struct bcmgenet_tx_ring *ring)
 909 {
 910         struct enet_cb *tx_cb_ptr;
 911
 912         tx_cb_ptr = ring->cbs;
 913         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
 914         tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
 915         /* Advancing local write pointer */
 916         if (ring->write_ptr == ring->end_ptr)
 917                 ring->write_ptr = ring->cb_ptr;
 918         else
 919                 ring->write_ptr++;
 920
 921         return tx_cb_ptr;
 922 }
 923
 924 /* Simple helper to free a control block's resources */
 925 static void bcmgenet_free_cb(struct enet_cb *cb)
 926 {
 927         dev_kfree_skb_any(cb->skb);
 928         cb->skb = NULL;
 929         dma_unmap_addr_set(cb, dma_addr, 0);
 930 }
 931
 932 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
 933                                                   struct bcmgenet_tx_ring *ring)
 934 {
 935         bcmgenet_intrl2_0_writel(priv,
 936                                  UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
 937                                  INTRL2_CPU_MASK_SET);
 938 }
 939
 940 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
 941                                                  struct bcmgenet_tx_ring *ring)
 942 {
 943         bcmgenet_intrl2_0_writel(priv,
 944                                  UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
 945                                  INTRL2_CPU_MASK_CLEAR);
 946 }
 947
 948 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
 949                                                struct bcmgenet_tx_ring *ring)
 950 {
 951         bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
 952                                  INTRL2_CPU_MASK_CLEAR);
 953         priv->int1_mask &= ~(1 << ring->index);
 954 }
 955
 956 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
 957                                                 struct bcmgenet_tx_ring *ring)
 958 {
 959         bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
 960                                  INTRL2_CPU_MASK_SET);
 961         priv->int1_mask |= (1 << ring->index);
 962 }
 963
 964 /* Unlocked version of the reclaim routine */
 965 static void __bcmgenet_tx_reclaim(struct net_device *dev,
 966                                   struct bcmgenet_tx_ring *ring)
 967 {
 968         struct bcmgenet_priv *priv = netdev_priv(dev);
 969         int last_tx_cn, last_c_index, num_tx_bds;
 970         struct enet_cb *tx_cb_ptr;
 971         struct netdev_queue *txq;
 972         unsigned int bds_compl;
 973         unsigned int c_index;
 974
 975         /* Compute how many buffers are transmitted since last xmit call */
 976         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
 977         txq = netdev_get_tx_queue(dev, ring->queue);
 978
 979         last_c_index = ring->c_index;
 980         num_tx_bds = ring->size;
 981
 982         c_index &= (num_tx_bds - 1);
 983
 984         if (c_index >= last_c_index)
 985                 last_tx_cn = c_index - last_c_index;
 986         else
 987                 last_tx_cn = num_tx_bds - last_c_index + c_index;
 988
 989         netif_dbg(priv, tx_done, dev,
 990                   "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
 991                   __func__, ring->index,
 992                   c_index, last_tx_cn, last_c_index);
 993
 994         /* Reclaim transmitted buffers */
 995         while (last_tx_cn-- > 0) {
 996                 tx_cb_ptr = ring->cbs + last_c_index;
 997                 bds_compl = 0;
 998                 if (tx_cb_ptr->skb) {
 999                         bds_compl = skb_shinfo(tx_cb_ptr->skb)->nr_frags + 1;
1000                         dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1001                         dma_unmap_single(&dev->dev,
1002                                          dma_unmap_addr(tx_cb_ptr, dma_addr),
1003                                          tx_cb_ptr->skb->len,
1004                                          DMA_TO_DEVICE);
1005                         bcmgenet_free_cb(tx_cb_ptr);
1006                 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1007                         dev->stats.tx_bytes +=
1008                                 dma_unmap_len(tx_cb_ptr, dma_len);
1009                         dma_unmap_page(&dev->dev,
1010                                        dma_unmap_addr(tx_cb_ptr, dma_addr),
1011                                        dma_unmap_len(tx_cb_ptr, dma_len),
1012                                        DMA_TO_DEVICE);
1013                         dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1014                 }
1015                 dev->stats.tx_packets++;
1016                 ring->free_bds += bds_compl;
1017
1018                 last_c_index++;
1019                 last_c_index &= (num_tx_bds - 1);
1020         }
1021
1022         if (ring->free_bds > (MAX_SKB_FRAGS + 1))
1023                 ring->int_disable(priv, ring);
1024
1025         if (netif_tx_queue_stopped(txq))
1026                 netif_tx_wake_queue(txq);
1027
1028         ring->c_index = c_index;
1029 }
1030
1031 static void bcmgenet_tx_reclaim(struct net_device *dev,
1032                                 struct bcmgenet_tx_ring *ring)
1033 {
1034         unsigned long flags;
1035
1036         spin_lock_irqsave(&ring->lock, flags);
1037         __bcmgenet_tx_reclaim(dev, ring);
1038         spin_unlock_irqrestore(&ring->lock, flags);
1039 }
1040
1041 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1042 {
1043         struct bcmgenet_priv *priv = netdev_priv(dev);
1044         int i;
1045
1046         if (netif_is_multiqueue(dev)) {
1047                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1048                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1049         }
1050
1051         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1052 }
1053
1054 /* Transmits a single SKB (either head of a fragment or a single SKB)
1055  * caller must hold priv->lock
1056  */
1057 static int bcmgenet_xmit_single(struct net_device *dev,
1058                                 struct sk_buff *skb,
1059                                 u16 dma_desc_flags,
1060                                 struct bcmgenet_tx_ring *ring)
1061 {
1062         struct bcmgenet_priv *priv = netdev_priv(dev);
1063         struct device *kdev = &priv->pdev->dev;
1064         struct enet_cb *tx_cb_ptr;
1065         unsigned int skb_len;
1066         dma_addr_t mapping;
1067         u32 length_status;
1068         int ret;
1069
1070         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1071
1072         if (unlikely(!tx_cb_ptr))
1073                 BUG();
1074
1075         tx_cb_ptr->skb = skb;
1076
1077         skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1078
1079         mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1080         ret = dma_mapping_error(kdev, mapping);
1081         if (ret) {
1082                 priv->mib.tx_dma_failed++;
1083                 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1084                 dev_kfree_skb(skb);
1085                 return ret;
1086         }
1087
1088         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1089         dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1090         length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1091                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1092                         DMA_TX_APPEND_CRC;
1093
1094         if (skb->ip_summed == CHECKSUM_PARTIAL)
1095                 length_status |= DMA_TX_DO_CSUM;
1096
1097         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1098
1099         /* Decrement total BD count and advance our write pointer */
1100         ring->free_bds -= 1;
1101         ring->prod_index += 1;
1102         ring->prod_index &= DMA_P_INDEX_MASK;
1103
1104         return 0;
1105 }
1106
1107 /* Transmit a SKB fragment */
1108 static int bcmgenet_xmit_frag(struct net_device *dev,
1109                               skb_frag_t *frag,
1110                               u16 dma_desc_flags,
1111                               struct bcmgenet_tx_ring *ring)
1112 {
1113         struct bcmgenet_priv *priv = netdev_priv(dev);
1114         struct device *kdev = &priv->pdev->dev;
1115         struct enet_cb *tx_cb_ptr;
1116         dma_addr_t mapping;
1117         int ret;
1118
1119         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1120
1121         if (unlikely(!tx_cb_ptr))
1122                 BUG();
1123         tx_cb_ptr->skb = NULL;
1124
1125         mapping = skb_frag_dma_map(kdev, frag, 0,
1126                                    skb_frag_size(frag), DMA_TO_DEVICE);
1127         ret = dma_mapping_error(kdev, mapping);
1128         if (ret) {
1129                 priv->mib.tx_dma_failed++;
1130                 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1131                           __func__);
1132                 return ret;
1133         }
1134
1135         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1136         dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1137
1138         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1139                     (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1140                     (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1141
1142
1143         ring->free_bds -= 1;
1144         ring->prod_index += 1;
1145         ring->prod_index &= DMA_P_INDEX_MASK;
1146
1147         return 0;
1148 }
1149
1150 /* Reallocate the SKB to put enough headroom in front of it and insert
1151  * the transmit checksum offsets in the descriptors
1152  */
1153 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1154                                             struct sk_buff *skb)
1155 {
1156         struct status_64 *status = NULL;
1157         struct sk_buff *new_skb;
1158         u16 offset;
1159         u8 ip_proto;
1160         u16 ip_ver;
1161         u32 tx_csum_info;
1162
1163         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1164                 /* If 64 byte status block enabled, must make sure skb has
1165                  * enough headroom for us to insert 64B status block.
1166                  */
1167                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1168                 dev_kfree_skb(skb);
1169                 if (!new_skb) {
1170                         dev->stats.tx_errors++;
1171                         dev->stats.tx_dropped++;
1172                         return NULL;
1173                 }
1174                 skb = new_skb;
1175         }
1176
1177         skb_push(skb, sizeof(*status));
1178         status = (struct status_64 *)skb->data;
1179
1180         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1181                 ip_ver = htons(skb->protocol);
1182                 switch (ip_ver) {
1183                 case ETH_P_IP:
1184                         ip_proto = ip_hdr(skb)->protocol;
1185                         break;
1186                 case ETH_P_IPV6:
1187                         ip_proto = ipv6_hdr(skb)->nexthdr;
1188                         break;
1189                 default:
1190                         return skb;
1191                 }
1192
1193                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1194                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1195                                 (offset + skb->csum_offset);
1196
1197                 /* Set the length valid bit for TCP and UDP and just set
1198                  * the special UDP flag for IPv4, else just set to 0.
1199                  */
1200                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1201                         tx_csum_info |= STATUS_TX_CSUM_LV;
1202                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1203                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1204                 } else {
1205                         tx_csum_info = 0;
1206                 }
1207
1208                 status->tx_csum_info = tx_csum_info;
1209         }
1210
1211         return skb;
1212 }
1213
1214 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1215 {
1216         struct bcmgenet_priv *priv = netdev_priv(dev);
1217         struct bcmgenet_tx_ring *ring = NULL;
1218         struct netdev_queue *txq;
1219         unsigned long flags = 0;
1220         int nr_frags, index;
1221         u16 dma_desc_flags;
1222         int ret;
1223         int i;
1224
1225         index = skb_get_queue_mapping(skb);
1226         /* Mapping strategy:
1227          * queue_mapping = 0, unclassified, packet xmited through ring16
1228          * queue_mapping = 1, goes to ring 0. (highest priority queue
1229          * queue_mapping = 2, goes to ring 1.
1230          * queue_mapping = 3, goes to ring 2.
1231          * queue_mapping = 4, goes to ring 3.
1232          */
1233         if (index == 0)
1234                 index = DESC_INDEX;
1235         else
1236                 index -= 1;
1237
1238         nr_frags = skb_shinfo(skb)->nr_frags;
1239         ring = &priv->tx_rings[index];
1240         txq = netdev_get_tx_queue(dev, ring->queue);
1241
1242         spin_lock_irqsave(&ring->lock, flags);
1243         if (ring->free_bds <= nr_frags + 1) {
1244                 netif_tx_stop_queue(txq);
1245                 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1246                            __func__, index, ring->queue);
1247                 ret = NETDEV_TX_BUSY;
1248                 goto out;
1249         }
1250
1251         if (skb_padto(skb, ETH_ZLEN)) {
1252                 ret = NETDEV_TX_OK;
1253                 goto out;
1254         }
1255
1256         /* set the SKB transmit checksum */
1257         if (priv->desc_64b_en) {
1258                 skb = bcmgenet_put_tx_csum(dev, skb);
1259                 if (!skb) {
1260                         ret = NETDEV_TX_OK;
1261                         goto out;
1262                 }
1263         }
1264
1265         dma_desc_flags = DMA_SOP;
1266         if (nr_frags == 0)
1267                 dma_desc_flags |= DMA_EOP;
1268
1269         /* Transmit single SKB or head of fragment list */
1270         ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1271         if (ret) {
1272                 ret = NETDEV_TX_OK;
1273                 goto out;
1274         }
1275
1276         /* xmit fragment */
1277         for (i = 0; i < nr_frags; i++) {
1278                 ret = bcmgenet_xmit_frag(dev,
1279                                          &skb_shinfo(skb)->frags[i],
1280                                          (i == nr_frags - 1) ? DMA_EOP : 0,
1281                                          ring);
1282                 if (ret) {
1283                         ret = NETDEV_TX_OK;
1284                         goto out;
1285                 }
1286         }
1287
1288         skb_tx_timestamp(skb);
1289
1290         /* we kept a software copy of how much we should advance the TDMA
1291          * producer index, now write it down to the hardware
1292          */
1293         bcmgenet_tdma_ring_writel(priv, ring->index,
1294                                   ring->prod_index, TDMA_PROD_INDEX);
1295
1296         if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
1297                 netif_tx_stop_queue(txq);
1298                 ring->int_enable(priv, ring);
1299         }
1300
1301 out:
1302         spin_unlock_irqrestore(&ring->lock, flags);
1303
1304         return ret;
1305 }
1306
1307
1308 static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb)
1309 {
1310         struct device *kdev = &priv->pdev->dev;
1311         struct sk_buff *skb;
1312         dma_addr_t mapping;
1313         int ret;
1314
1315         skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1316         if (!skb)
1317                 return -ENOMEM;
1318
1319         /* a caller did not release this control block */
1320         WARN_ON(cb->skb != NULL);
1321         cb->skb = skb;
1322         mapping = dma_map_single(kdev, skb->data,
1323                                  priv->rx_buf_len, DMA_FROM_DEVICE);
1324         ret = dma_mapping_error(kdev, mapping);
1325         if (ret) {
1326                 priv->mib.rx_dma_failed++;
1327                 bcmgenet_free_cb(cb);
1328                 netif_err(priv, rx_err, priv->dev,
1329                           "%s DMA map failed\n", __func__);
1330                 return ret;
1331         }
1332
1333         dma_unmap_addr_set(cb, dma_addr, mapping);
1334         /* assign packet, prepare descriptor, and advance pointer */
1335
1336         dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1337
1338         /* turn on the newly assigned BD for DMA to use */
1339         priv->rx_bd_assign_index++;
1340         priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1341
1342         priv->rx_bd_assign_ptr = priv->rx_bds +
1343                 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1344
1345         return 0;
1346 }
1347
1348 /* bcmgenet_desc_rx - descriptor based rx process.
1349  * this could be called from bottom half, or from NAPI polling method.
1350  */
1351 static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1352                                      unsigned int budget)
1353 {
1354         struct net_device *dev = priv->dev;
1355         struct enet_cb *cb;
1356         struct sk_buff *skb;
1357         u32 dma_length_status;
1358         unsigned long dma_flag;
1359         int len, err;
1360         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1361         unsigned int p_index;
1362         unsigned int chksum_ok = 0;
1363
1364         p_index = bcmgenet_rdma_ring_readl(priv, DESC_INDEX, RDMA_PROD_INDEX);
1365         p_index &= DMA_P_INDEX_MASK;
1366
1367         if (p_index < priv->rx_c_index)
1368                 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1369                         priv->rx_c_index + p_index;
1370         else
1371                 rxpkttoprocess = p_index - priv->rx_c_index;
1372
1373         netif_dbg(priv, rx_status, dev,
1374                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1375
1376         while ((rxpktprocessed < rxpkttoprocess) &&
1377                (rxpktprocessed < budget)) {
1378                 cb = &priv->rx_cbs[priv->rx_read_ptr];
1379                 skb = cb->skb;
1380
1381                 /* We do not have a backing SKB, so we do not have a
1382                  * corresponding DMA mapping for this incoming packet since
1383                  * bcmgenet_rx_refill always either has both skb and mapping or
1384                  * none.
1385                  */
1386                 if (unlikely(!skb)) {
1387                         dev->stats.rx_dropped++;
1388                         dev->stats.rx_errors++;
1389                         goto refill;
1390                 }
1391
1392                 /* Unmap the packet contents such that we can use the
1393                  * RSV from the 64 bytes descriptor when enabled and save
1394                  * a 32-bits register read
1395                  */
1396                 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
1397                                  priv->rx_buf_len, DMA_FROM_DEVICE);
1398
1399                 if (!priv->desc_64b_en) {
1400                         dma_length_status =
1401                                 dmadesc_get_length_status(priv,
1402                                                           priv->rx_bds +
1403                                                           (priv->rx_read_ptr *
1404                                                            DMA_DESC_SIZE));
1405                 } else {
1406                         struct status_64 *status;
1407
1408                         status = (struct status_64 *)skb->data;
1409                         dma_length_status = status->length_status;
1410                 }
1411
1412                 /* DMA flags and length are still valid no matter how
1413                  * we got the Receive Status Vector (64B RSB or register)
1414                  */
1415                 dma_flag = dma_length_status & 0xffff;
1416                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1417
1418                 netif_dbg(priv, rx_status, dev,
1419                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1420                           __func__, p_index, priv->rx_c_index,
1421                           priv->rx_read_ptr, dma_length_status);
1422
1423                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1424                         netif_err(priv, rx_status, dev,
1425                                   "dropping fragmented packet!\n");
1426                         dev->stats.rx_dropped++;
1427                         dev->stats.rx_errors++;
1428                         dev_kfree_skb_any(cb->skb);
1429                         cb->skb = NULL;
1430                         goto refill;
1431                 }
1432                 /* report errors */
1433                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1434                                                 DMA_RX_OV |
1435                                                 DMA_RX_NO |
1436                                                 DMA_RX_LG |
1437                                                 DMA_RX_RXER))) {
1438                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1439                                   (unsigned int)dma_flag);
1440                         if (dma_flag & DMA_RX_CRC_ERROR)
1441                                 dev->stats.rx_crc_errors++;
1442                         if (dma_flag & DMA_RX_OV)
1443                                 dev->stats.rx_over_errors++;
1444                         if (dma_flag & DMA_RX_NO)
1445                                 dev->stats.rx_frame_errors++;
1446                         if (dma_flag & DMA_RX_LG)
1447                                 dev->stats.rx_length_errors++;
1448                         dev->stats.rx_dropped++;
1449                         dev->stats.rx_errors++;
1450
1451                         /* discard the packet and advance consumer index.*/
1452                         dev_kfree_skb_any(cb->skb);
1453                         cb->skb = NULL;
1454                         goto refill;
1455                 } /* error packet */
1456
1457                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1458                              priv->desc_rxchk_en;
1459
1460                 skb_put(skb, len);
1461                 if (priv->desc_64b_en) {
1462                         skb_pull(skb, 64);
1463                         len -= 64;
1464                 }
1465
1466                 if (likely(chksum_ok))
1467                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1468
1469                 /* remove hardware 2bytes added for IP alignment */
1470                 skb_pull(skb, 2);
1471                 len -= 2;
1472
1473                 if (priv->crc_fwd_en) {
1474                         skb_trim(skb, len - ETH_FCS_LEN);
1475                         len -= ETH_FCS_LEN;
1476                 }
1477
1478                 /*Finish setting up the received SKB and send it to the kernel*/
1479                 skb->protocol = eth_type_trans(skb, priv->dev);
1480                 dev->stats.rx_packets++;
1481                 dev->stats.rx_bytes += len;
1482                 if (dma_flag & DMA_RX_MULT)
1483                         dev->stats.multicast++;
1484
1485                 /* Notify kernel */
1486                 napi_gro_receive(&priv->napi, skb);
1487                 cb->skb = NULL;
1488                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1489
1490                 /* refill RX path on the current control block */
1491 refill:
1492                 err = bcmgenet_rx_refill(priv, cb);
1493                 if (err) {
1494                         priv->mib.alloc_rx_buff_failed++;
1495                         netif_err(priv, rx_err, dev, "Rx refill failed\n");
1496                 }
1497
1498                 rxpktprocessed++;
1499                 priv->rx_read_ptr++;
1500                 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1501         }
1502
1503         return rxpktprocessed;
1504 }
1505
1506 /* Assign skb to RX DMA descriptor. */
1507 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1508 {
1509         struct enet_cb *cb;
1510         int ret = 0;
1511         int i;
1512
1513         netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1514
1515         /* loop here for each buffer needing assign */
1516         for (i = 0; i < priv->num_rx_bds; i++) {
1517                 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1518                 if (cb->skb)
1519                         continue;
1520
1521                 ret = bcmgenet_rx_refill(priv, cb);
1522                 if (ret)
1523                         break;
1524         }
1525
1526         return ret;
1527 }
1528
1529 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1530 {
1531         struct enet_cb *cb;
1532         int i;
1533
1534         for (i = 0; i < priv->num_rx_bds; i++) {
1535                 cb = &priv->rx_cbs[i];
1536
1537                 if (dma_unmap_addr(cb, dma_addr)) {
1538                         dma_unmap_single(&priv->dev->dev,
1539                                          dma_unmap_addr(cb, dma_addr),
1540                                          priv->rx_buf_len, DMA_FROM_DEVICE);
1541                         dma_unmap_addr_set(cb, dma_addr, 0);
1542                 }
1543
1544                 if (cb->skb)
1545                         bcmgenet_free_cb(cb);
1546         }
1547 }
1548
1549 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1550 {
1551         u32 reg;
1552
1553         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1554         if (enable)
1555                 reg |= mask;
1556         else
1557                 reg &= ~mask;
1558         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1559
1560         /* UniMAC stops on a packet boundary, wait for a full-size packet
1561          * to be processed
1562          */
1563         if (enable == 0)
1564                 usleep_range(1000, 2000);
1565 }
1566
1567 static int reset_umac(struct bcmgenet_priv *priv)
1568 {
1569         struct device *kdev = &priv->pdev->dev;
1570         unsigned int timeout = 0;
1571         u32 reg;
1572
1573         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1574         bcmgenet_rbuf_ctrl_set(priv, 0);
1575         udelay(10);
1576
1577         /* disable MAC while updating its registers */
1578         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1579
1580         /* issue soft reset, wait for it to complete */
1581         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1582         while (timeout++ < 1000) {
1583                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1584                 if (!(reg & CMD_SW_RESET))
1585                         return 0;
1586
1587                 udelay(1);
1588         }
1589
1590         if (timeout == 1000) {
1591                 dev_err(kdev,
1592                         "timeout waiting for MAC to come out of reset\n");
1593                 return -ETIMEDOUT;
1594         }
1595
1596         return 0;
1597 }
1598
1599 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1600 {
1601         /* Mask all interrupts.*/
1602         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1603         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1604         bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1605         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1606         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1607         bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1608 }
1609
1610 static int init_umac(struct bcmgenet_priv *priv)
1611 {
1612         struct device *kdev = &priv->pdev->dev;
1613         int ret;
1614         u32 reg, cpu_mask_clear;
1615
1616         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1617
1618         ret = reset_umac(priv);
1619         if (ret)
1620                 return ret;
1621
1622         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1623         /* clear tx/rx counter */
1624         bcmgenet_umac_writel(priv,
1625                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1626                              UMAC_MIB_CTRL);
1627         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1628
1629         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1630
1631         /* init rx registers, enable ip header optimization */
1632         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1633         reg |= RBUF_ALIGN_2B;
1634         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1635
1636         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1637                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1638
1639         bcmgenet_intr_disable(priv);
1640
1641         cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1642
1643         dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1644
1645         /* Monitor cable plug/unplugged event for internal PHY */
1646         if (phy_is_internal(priv->phydev)) {
1647                 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1648         } else if (priv->ext_phy) {
1649                 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1650         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1651                 reg = bcmgenet_bp_mc_get(priv);
1652                 reg |= BIT(priv->hw_params->bp_in_en_shift);
1653
1654                 /* bp_mask: back pressure mask */
1655                 if (netif_is_multiqueue(priv->dev))
1656                         reg |= priv->hw_params->bp_in_mask;
1657                 else
1658                         reg &= ~priv->hw_params->bp_in_mask;
1659                 bcmgenet_bp_mc_set(priv, reg);
1660         }
1661
1662         /* Enable MDIO interrupts on GENET v3+ */
1663         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1664                 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1665
1666         bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
1667
1668         /* Enable rx/tx engine.*/
1669         dev_dbg(kdev, "done init umac\n");
1670
1671         return 0;
1672 }
1673
1674 /* Initialize all house-keeping variables for a TX ring, along
1675  * with corresponding hardware registers
1676  */
1677 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1678                                   unsigned int index, unsigned int size,
1679                                   unsigned int write_ptr, unsigned int end_ptr)
1680 {
1681         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1682         u32 words_per_bd = WORDS_PER_BD(priv);
1683         u32 flow_period_val = 0;
1684         unsigned int first_bd;
1685
1686         spin_lock_init(&ring->lock);
1687         ring->index = index;
1688         if (index == DESC_INDEX) {
1689                 ring->queue = 0;
1690                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1691                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1692         } else {
1693                 ring->queue = index + 1;
1694                 ring->int_enable = bcmgenet_tx_ring_int_enable;
1695                 ring->int_disable = bcmgenet_tx_ring_int_disable;
1696         }
1697         ring->cbs = priv->tx_cbs + write_ptr;
1698         ring->size = size;
1699         ring->c_index = 0;
1700         ring->free_bds = size;
1701         ring->write_ptr = write_ptr;
1702         ring->cb_ptr = write_ptr;
1703         ring->end_ptr = end_ptr - 1;
1704         ring->prod_index = 0;
1705
1706         /* Set flow period for ring != 16 */
1707         if (index != DESC_INDEX)
1708                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1709
1710         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1711         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1712         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1713         /* Disable rate control for now */
1714         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1715                                   TDMA_FLOW_PERIOD);
1716         /* Unclassified traffic goes to ring 16 */
1717         bcmgenet_tdma_ring_writel(priv, index,
1718                                   ((size << DMA_RING_SIZE_SHIFT) |
1719                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1720
1721         first_bd = write_ptr;
1722
1723         /* Set start and end address, read and write pointers */
1724         bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1725                                   DMA_START_ADDR);
1726         bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1727                                   TDMA_READ_PTR);
1728         bcmgenet_tdma_ring_writel(priv, index, first_bd,
1729                                   TDMA_WRITE_PTR);
1730         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1731                                   DMA_END_ADDR);
1732 }
1733
1734 /* Initialize a RDMA ring */
1735 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1736                                  unsigned int index, unsigned int size)
1737 {
1738         u32 words_per_bd = WORDS_PER_BD(priv);
1739         int ret;
1740
1741         priv->num_rx_bds = TOTAL_DESC;
1742         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1743         priv->rx_bd_assign_ptr = priv->rx_bds;
1744         priv->rx_bd_assign_index = 0;
1745         priv->rx_c_index = 0;
1746         priv->rx_read_ptr = 0;
1747         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
1748                                GFP_KERNEL);
1749         if (!priv->rx_cbs)
1750                 return -ENOMEM;
1751
1752         ret = bcmgenet_alloc_rx_buffers(priv);
1753         if (ret) {
1754                 kfree(priv->rx_cbs);
1755                 return ret;
1756         }
1757
1758         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1759         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1760         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1761         bcmgenet_rdma_ring_writel(priv, index,
1762                                   ((size << DMA_RING_SIZE_SHIFT) |
1763                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1764         bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1765         bcmgenet_rdma_ring_writel(priv, index,
1766                                   words_per_bd * size - 1, DMA_END_ADDR);
1767         bcmgenet_rdma_ring_writel(priv, index,
1768                                   (DMA_FC_THRESH_LO <<
1769                                    DMA_XOFF_THRESHOLD_SHIFT) |
1770                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1771         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1772
1773         return ret;
1774 }
1775
1776 /* init multi xmit queues, only available for GENET2+
1777  * the queue is partitioned as follows:
1778  *
1779  * queue 0 - 3 is priority based, each one has 32 descriptors,
1780  * with queue 0 being the highest priority queue.
1781  *
1782  * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1783  * descriptors: 256 - (number of tx queues * bds per queues) = 128
1784  * descriptors.
1785  *
1786  * The transmit control block pool is then partitioned as following:
1787  * - tx_cbs[0...127] are for queue 16
1788  * - tx_ring_cbs[0] points to tx_cbs[128..159]
1789  * - tx_ring_cbs[1] points to tx_cbs[160..191]
1790  * - tx_ring_cbs[2] points to tx_cbs[192..223]
1791  * - tx_ring_cbs[3] points to tx_cbs[224..255]
1792  */
1793 static void bcmgenet_init_multiq(struct net_device *dev)
1794 {
1795         struct bcmgenet_priv *priv = netdev_priv(dev);
1796         unsigned int i, dma_enable;
1797         u32 reg, dma_ctrl, ring_cfg = 0;
1798         u32 dma_priority[3] = {0, 0, 0};
1799
1800         if (!netif_is_multiqueue(dev)) {
1801                 netdev_warn(dev, "called with non multi queue aware HW\n");
1802                 return;
1803         }
1804
1805         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1806         dma_enable = dma_ctrl & DMA_EN;
1807         dma_ctrl &= ~DMA_EN;
1808         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1809
1810         /* Enable strict priority arbiter mode */
1811         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1812
1813         for (i = 0; i < priv->hw_params->tx_queues; i++) {
1814                 /* first 64 tx_cbs are reserved for default tx queue
1815                  * (ring 16)
1816                  */
1817                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
1818                                       i * priv->hw_params->bds_cnt,
1819                                       (i + 1) * priv->hw_params->bds_cnt);
1820
1821                 /* Configure ring as descriptor ring and setup priority */
1822                 ring_cfg |= 1 << i;
1823                 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1824
1825                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1826                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1827         }
1828
1829         /* Set ring 16 priority and program the hardware registers */
1830         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1831                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1832                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
1833         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1834         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1835         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1836
1837         /* Enable rings */
1838         reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1839         reg |= ring_cfg;
1840         bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1841
1842         /* Configure ring as descriptor ring and re-enable DMA if enabled */
1843         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1844         reg |= dma_ctrl;
1845         if (dma_enable)
1846                 reg |= DMA_EN;
1847         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1848 }
1849
1850 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
1851 {
1852         int ret = 0;
1853         int timeout = 0;
1854         u32 reg;
1855
1856         /* Disable TDMA to stop add more frames in TX DMA */
1857         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1858         reg &= ~DMA_EN;
1859         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1860
1861         /* Check TDMA status register to confirm TDMA is disabled */
1862         while (timeout++ < DMA_TIMEOUT_VAL) {
1863                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
1864                 if (reg & DMA_DISABLED)
1865                         break;
1866
1867                 udelay(1);
1868         }
1869
1870         if (timeout == DMA_TIMEOUT_VAL) {
1871                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
1872                 ret = -ETIMEDOUT;
1873         }
1874
1875         /* Wait 10ms for packet drain in both tx and rx dma */
1876         usleep_range(10000, 20000);
1877
1878         /* Disable RDMA */
1879         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1880         reg &= ~DMA_EN;
1881         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1882
1883         timeout = 0;
1884         /* Check RDMA status register to confirm RDMA is disabled */
1885         while (timeout++ < DMA_TIMEOUT_VAL) {
1886                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
1887                 if (reg & DMA_DISABLED)
1888                         break;
1889
1890                 udelay(1);
1891         }
1892
1893         if (timeout == DMA_TIMEOUT_VAL) {
1894                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
1895                 ret = -ETIMEDOUT;
1896         }
1897
1898         return ret;
1899 }
1900
1901 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1902 {
1903         int i;
1904
1905         /* disable DMA */
1906         bcmgenet_dma_teardown(priv);
1907
1908         for (i = 0; i < priv->num_tx_bds; i++) {
1909                 if (priv->tx_cbs[i].skb != NULL) {
1910                         dev_kfree_skb(priv->tx_cbs[i].skb);
1911                         priv->tx_cbs[i].skb = NULL;
1912                 }
1913         }
1914
1915         bcmgenet_free_rx_buffers(priv);
1916         kfree(priv->rx_cbs);
1917         kfree(priv->tx_cbs);
1918 }
1919
1920 /* init_edma: Initialize DMA control register */
1921 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1922 {
1923         int ret;
1924
1925         netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1926
1927         /* by default, enable ring 16 (descriptor based) */
1928         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1929         if (ret) {
1930                 netdev_err(priv->dev, "failed to initialize RX ring\n");
1931                 return ret;
1932         }
1933
1934         /* init rDma */
1935         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1936
1937         /* Init tDma */
1938         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1939
1940         /* Initialize common TX ring structures */
1941         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1942         priv->num_tx_bds = TOTAL_DESC;
1943         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
1944                                GFP_KERNEL);
1945         if (!priv->tx_cbs) {
1946                 bcmgenet_fini_dma(priv);
1947                 return -ENOMEM;
1948         }
1949
1950         /* initialize multi xmit queue */
1951         bcmgenet_init_multiq(priv->dev);
1952
1953         /* initialize special ring 16 */
1954         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
1955                               priv->hw_params->tx_queues *
1956                               priv->hw_params->bds_cnt,
1957                               TOTAL_DESC);
1958
1959         return 0;
1960 }
1961
1962 /* NAPI polling method*/
1963 static int bcmgenet_poll(struct napi_struct *napi, int budget)
1964 {
1965         struct bcmgenet_priv *priv = container_of(napi,
1966                         struct bcmgenet_priv, napi);
1967         unsigned int work_done;
1968
1969         /* tx reclaim */
1970         bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1971
1972         work_done = bcmgenet_desc_rx(priv, budget);
1973
1974         /* Advancing our consumer index*/
1975         priv->rx_c_index += work_done;
1976         priv->rx_c_index &= DMA_C_INDEX_MASK;
1977         bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
1978                                   priv->rx_c_index, RDMA_CONS_INDEX);
1979         if (work_done < budget) {
1980                 napi_complete(napi);
1981                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
1982                                          INTRL2_CPU_MASK_CLEAR);
1983         }
1984
1985         return work_done;
1986 }
1987
1988 /* Interrupt bottom half */
1989 static void bcmgenet_irq_task(struct work_struct *work)
1990 {
1991         struct bcmgenet_priv *priv = container_of(
1992                         work, struct bcmgenet_priv, bcmgenet_irq_work);
1993
1994         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
1995
1996         if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
1997                 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
1998                 netif_dbg(priv, wol, priv->dev,
1999                           "magic packet detected, waking up\n");
2000                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2001         }
2002
2003         /* Link UP/DOWN event */
2004         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2005             (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
2006                 phy_mac_interrupt(priv->phydev,
2007                                   priv->irq0_stat & UMAC_IRQ_LINK_UP);
2008                 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
2009         }
2010 }
2011
2012 /* bcmgenet_isr1: interrupt handler for ring buffer. */
2013 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2014 {
2015         struct bcmgenet_priv *priv = dev_id;
2016         unsigned int index;
2017
2018         /* Save irq status for bottom-half processing. */
2019         priv->irq1_stat =
2020                 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2021                 ~priv->int1_mask;
2022         /* clear interrupts */
2023         bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2024
2025         netif_dbg(priv, intr, priv->dev,
2026                   "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
2027         /* Check the MBDONE interrupts.
2028          * packet is done, reclaim descriptors
2029          */
2030         if (priv->irq1_stat & 0x0000ffff) {
2031                 index = 0;
2032                 for (index = 0; index < 16; index++) {
2033                         if (priv->irq1_stat & (1 << index))
2034                                 bcmgenet_tx_reclaim(priv->dev,
2035                                                     &priv->tx_rings[index]);
2036                 }
2037         }
2038         return IRQ_HANDLED;
2039 }
2040
2041 /* bcmgenet_isr0: Handle various interrupts. */
2042 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2043 {
2044         struct bcmgenet_priv *priv = dev_id;
2045
2046         /* Save irq status for bottom-half processing. */
2047         priv->irq0_stat =
2048                 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2049                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2050         /* clear interrupts */
2051         bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2052
2053         netif_dbg(priv, intr, priv->dev,
2054                   "IRQ=0x%x\n", priv->irq0_stat);
2055
2056         if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
2057                 /* We use NAPI(software interrupt throttling, if
2058                  * Rx Descriptor throttling is not used.
2059                  * Disable interrupt, will be enabled in the poll method.
2060                  */
2061                 if (likely(napi_schedule_prep(&priv->napi))) {
2062                         bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2063                                                  INTRL2_CPU_MASK_SET);
2064                         __napi_schedule(&priv->napi);
2065                 }
2066         }
2067         if (priv->irq0_stat &
2068                         (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
2069                 /* Tx reclaim */
2070                 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
2071         }
2072         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2073                                 UMAC_IRQ_PHY_DET_F |
2074                                 UMAC_IRQ_LINK_UP |
2075                                 UMAC_IRQ_LINK_DOWN |
2076                                 UMAC_IRQ_HFB_SM |
2077                                 UMAC_IRQ_HFB_MM |
2078                                 UMAC_IRQ_MPD_R)) {
2079                 /* all other interested interrupts handled in bottom half */
2080                 schedule_work(&priv->bcmgenet_irq_work);
2081         }
2082
2083         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2084             priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2085                 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2086                 wake_up(&priv->wq);
2087         }
2088
2089         return IRQ_HANDLED;
2090 }
2091
2092 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2093 {
2094         struct bcmgenet_priv *priv = dev_id;
2095
2096         pm_wakeup_event(&priv->pdev->dev, 0);
2097
2098         return IRQ_HANDLED;
2099 }
2100
2101 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2102 {
2103         u32 reg;
2104
2105         reg = bcmgenet_rbuf_ctrl_get(priv);
2106         reg |= BIT(1);
2107         bcmgenet_rbuf_ctrl_set(priv, reg);
2108         udelay(10);
2109
2110         reg &= ~BIT(1);
2111         bcmgenet_rbuf_ctrl_set(priv, reg);
2112         udelay(10);
2113 }
2114
2115 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2116                                  unsigned char *addr)
2117 {
2118         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2119                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2120         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2121 }
2122
2123 /* Returns a reusable dma control register value */
2124 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2125 {
2126         u32 reg;
2127         u32 dma_ctrl;
2128
2129         /* disable DMA */
2130         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2131         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2132         reg &= ~dma_ctrl;
2133         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2134
2135         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2136         reg &= ~dma_ctrl;
2137         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2138
2139         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2140         udelay(10);
2141         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2142
2143         return dma_ctrl;
2144 }
2145
2146 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2147 {
2148         u32 reg;
2149
2150         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2151         reg |= dma_ctrl;
2152         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2153
2154         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2155         reg |= dma_ctrl;
2156         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2157 }
2158
2159 static void bcmgenet_netif_start(struct net_device *dev)
2160 {
2161         struct bcmgenet_priv *priv = netdev_priv(dev);
2162
2163         /* Start the network engine */
2164         napi_enable(&priv->napi);
2165
2166         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2167
2168         if (phy_is_internal(priv->phydev))
2169                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2170
2171         netif_tx_start_all_queues(dev);
2172
2173         phy_start(priv->phydev);
2174 }
2175
2176 static int bcmgenet_open(struct net_device *dev)
2177 {
2178         struct bcmgenet_priv *priv = netdev_priv(dev);
2179         unsigned long dma_ctrl;
2180         u32 reg;
2181         int ret;
2182
2183         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2184
2185         /* Turn on the clock */
2186         if (!IS_ERR(priv->clk))
2187                 clk_prepare_enable(priv->clk);
2188
2189         /* take MAC out of reset */
2190         bcmgenet_umac_reset(priv);
2191
2192         ret = init_umac(priv);
2193         if (ret)
2194                 goto err_clk_disable;
2195
2196         /* disable ethernet MAC while updating its registers */
2197         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2198
2199         /* Make sure we reflect the value of CRC_CMD_FWD */
2200         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2201         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2202
2203         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2204
2205         if (phy_is_internal(priv->phydev)) {
2206                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2207                 reg |= EXT_ENERGY_DET_MASK;
2208                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2209         }
2210
2211         /* Disable RX/TX DMA and flush TX queues */
2212         dma_ctrl = bcmgenet_dma_disable(priv);
2213
2214         /* Reinitialize TDMA and RDMA and SW housekeeping */
2215         ret = bcmgenet_init_dma(priv);
2216         if (ret) {
2217                 netdev_err(dev, "failed to initialize DMA\n");
2218                 goto err_fini_dma;
2219         }
2220
2221         /* Always enable ring 16 - descriptor ring */
2222         bcmgenet_enable_dma(priv, dma_ctrl);
2223
2224         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2225                           dev->name, priv);
2226         if (ret < 0) {
2227                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2228                 goto err_fini_dma;
2229         }
2230
2231         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2232                           dev->name, priv);
2233         if (ret < 0) {
2234                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2235                 goto err_irq0;
2236         }
2237
2238         /* Re-configure the port multiplexer towards the PHY device */
2239         bcmgenet_mii_config(priv->dev, false);
2240
2241         phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2242                            priv->phy_interface);
2243
2244         bcmgenet_netif_start(dev);
2245
2246         return 0;
2247
2248 err_irq0:
2249         free_irq(priv->irq0, dev);
2250 err_fini_dma:
2251         bcmgenet_fini_dma(priv);
2252 err_clk_disable:
2253         if (!IS_ERR(priv->clk))
2254                 clk_disable_unprepare(priv->clk);
2255         return ret;
2256 }
2257
2258 static void bcmgenet_netif_stop(struct net_device *dev)
2259 {
2260         struct bcmgenet_priv *priv = netdev_priv(dev);
2261
2262         netif_tx_stop_all_queues(dev);
2263         napi_disable(&priv->napi);
2264         phy_stop(priv->phydev);
2265
2266         bcmgenet_intr_disable(priv);
2267
2268         /* Wait for pending work items to complete. Since interrupts are
2269          * disabled no new work will be scheduled.
2270          */
2271         cancel_work_sync(&priv->bcmgenet_irq_work);
2272
2273         priv->old_link = -1;
2274         priv->old_speed = -1;
2275         priv->old_duplex = -1;
2276         priv->old_pause = -1;
2277 }
2278
2279 static int bcmgenet_close(struct net_device *dev)
2280 {
2281         struct bcmgenet_priv *priv = netdev_priv(dev);
2282         int ret;
2283
2284         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2285
2286         bcmgenet_netif_stop(dev);
2287
2288         /* Really kill the PHY state machine and disconnect from it */
2289         phy_disconnect(priv->phydev);
2290
2291         /* Disable MAC receive */
2292         umac_enable_set(priv, CMD_RX_EN, false);
2293
2294         ret = bcmgenet_dma_teardown(priv);
2295         if (ret)
2296                 return ret;
2297
2298         /* Disable MAC transmit. TX DMA disabled have to done before this */
2299         umac_enable_set(priv, CMD_TX_EN, false);
2300
2301         /* tx reclaim */
2302         bcmgenet_tx_reclaim_all(dev);
2303         bcmgenet_fini_dma(priv);
2304
2305         free_irq(priv->irq0, priv);
2306         free_irq(priv->irq1, priv);
2307
2308         if (phy_is_internal(priv->phydev))
2309                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2310
2311         if (!IS_ERR(priv->clk))
2312                 clk_disable_unprepare(priv->clk);
2313
2314         return 0;
2315 }
2316
2317 static void bcmgenet_timeout(struct net_device *dev)
2318 {
2319         struct bcmgenet_priv *priv = netdev_priv(dev);
2320
2321         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2322
2323         dev->trans_start = jiffies;
2324
2325         dev->stats.tx_errors++;
2326
2327         netif_tx_wake_all_queues(dev);
2328 }
2329
2330 #define MAX_MC_COUNT    16
2331
2332 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2333                                          unsigned char *addr,
2334                                          int *i,
2335                                          int *mc)
2336 {
2337         u32 reg;
2338
2339         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2340                              UMAC_MDF_ADDR + (*i * 4));
2341         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2342                              addr[4] << 8 | addr[5],
2343                              UMAC_MDF_ADDR + ((*i + 1) * 4));
2344         reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2345         reg |= (1 << (MAX_MC_COUNT - *mc));
2346         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2347         *i += 2;
2348         (*mc)++;
2349 }
2350
2351 static void bcmgenet_set_rx_mode(struct net_device *dev)
2352 {
2353         struct bcmgenet_priv *priv = netdev_priv(dev);
2354         struct netdev_hw_addr *ha;
2355         int i, mc;
2356         u32 reg;
2357
2358         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2359
2360         /* Promiscuous mode */
2361         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2362         if (dev->flags & IFF_PROMISC) {
2363                 reg |= CMD_PROMISC;
2364                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2365                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2366                 return;
2367         } else {
2368                 reg &= ~CMD_PROMISC;
2369                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2370         }
2371
2372         /* UniMac doesn't support ALLMULTI */
2373         if (dev->flags & IFF_ALLMULTI) {
2374                 netdev_warn(dev, "ALLMULTI is not supported\n");
2375                 return;
2376         }
2377
2378         /* update MDF filter */
2379         i = 0;
2380         mc = 0;
2381         /* Broadcast */
2382         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2383         /* my own address.*/
2384         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2385         /* Unicast list*/
2386         if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2387                 return;
2388
2389         if (!netdev_uc_empty(dev))
2390                 netdev_for_each_uc_addr(ha, dev)
2391                         bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2392         /* Multicast */
2393         if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2394                 return;
2395
2396         netdev_for_each_mc_addr(ha, dev)
2397                 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2398 }
2399
2400 /* Set the hardware MAC address. */
2401 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2402 {
2403         struct sockaddr *addr = p;
2404
2405         /* Setting the MAC address at the hardware level is not possible
2406          * without disabling the UniMAC RX/TX enable bits.
2407          */
2408         if (netif_running(dev))
2409                 return -EBUSY;
2410
2411         ether_addr_copy(dev->dev_addr, addr->sa_data);
2412
2413         return 0;
2414 }
2415
2416 static const struct net_device_ops bcmgenet_netdev_ops = {
2417         .ndo_open               = bcmgenet_open,
2418         .ndo_stop               = bcmgenet_close,
2419         .ndo_start_xmit         = bcmgenet_xmit,
2420         .ndo_tx_timeout         = bcmgenet_timeout,
2421         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
2422         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
2423         .ndo_do_ioctl           = bcmgenet_ioctl,
2424         .ndo_set_features       = bcmgenet_set_features,
2425 };
2426
2427 /* Array of GENET hardware parameters/characteristics */
2428 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2429         [GENET_V1] = {
2430                 .tx_queues = 0,
2431                 .rx_queues = 0,
2432                 .bds_cnt = 0,
2433                 .bp_in_en_shift = 16,
2434                 .bp_in_mask = 0xffff,
2435                 .hfb_filter_cnt = 16,
2436                 .qtag_mask = 0x1F,
2437                 .hfb_offset = 0x1000,
2438                 .rdma_offset = 0x2000,
2439                 .tdma_offset = 0x3000,
2440                 .words_per_bd = 2,
2441         },
2442         [GENET_V2] = {
2443                 .tx_queues = 4,
2444                 .rx_queues = 4,
2445                 .bds_cnt = 32,
2446                 .bp_in_en_shift = 16,
2447                 .bp_in_mask = 0xffff,
2448                 .hfb_filter_cnt = 16,
2449                 .qtag_mask = 0x1F,
2450                 .tbuf_offset = 0x0600,
2451                 .hfb_offset = 0x1000,
2452                 .hfb_reg_offset = 0x2000,
2453                 .rdma_offset = 0x3000,
2454                 .tdma_offset = 0x4000,
2455                 .words_per_bd = 2,
2456                 .flags = GENET_HAS_EXT,
2457         },
2458         [GENET_V3] = {
2459                 .tx_queues = 4,
2460                 .rx_queues = 4,
2461                 .bds_cnt = 32,
2462                 .bp_in_en_shift = 17,
2463                 .bp_in_mask = 0x1ffff,
2464                 .hfb_filter_cnt = 48,
2465                 .qtag_mask = 0x3F,
2466                 .tbuf_offset = 0x0600,
2467                 .hfb_offset = 0x8000,
2468                 .hfb_reg_offset = 0xfc00,
2469                 .rdma_offset = 0x10000,
2470                 .tdma_offset = 0x11000,
2471                 .words_per_bd = 2,
2472                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2473         },
2474         [GENET_V4] = {
2475                 .tx_queues = 4,
2476                 .rx_queues = 4,
2477                 .bds_cnt = 32,
2478                 .bp_in_en_shift = 17,
2479                 .bp_in_mask = 0x1ffff,
2480                 .hfb_filter_cnt = 48,
2481                 .qtag_mask = 0x3F,
2482                 .tbuf_offset = 0x0600,
2483                 .hfb_offset = 0x8000,
2484                 .hfb_reg_offset = 0xfc00,
2485                 .rdma_offset = 0x2000,
2486                 .tdma_offset = 0x4000,
2487                 .words_per_bd = 3,
2488                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2489         },
2490 };
2491
2492 /* Infer hardware parameters from the detected GENET version */
2493 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2494 {
2495         struct bcmgenet_hw_params *params;
2496         u32 reg;
2497         u8 major;
2498
2499         if (GENET_IS_V4(priv)) {
2500                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2501                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2502                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2503                 priv->version = GENET_V4;
2504         } else if (GENET_IS_V3(priv)) {
2505                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2506                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2507                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2508                 priv->version = GENET_V3;
2509         } else if (GENET_IS_V2(priv)) {
2510                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2511                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2512                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2513                 priv->version = GENET_V2;
2514         } else if (GENET_IS_V1(priv)) {
2515                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2516                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2517                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2518                 priv->version = GENET_V1;
2519         }
2520
2521         /* enum genet_version starts at 1 */
2522         priv->hw_params = &bcmgenet_hw_params[priv->version];
2523         params = priv->hw_params;
2524
2525         /* Read GENET HW version */
2526         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2527         major = (reg >> 24 & 0x0f);
2528         if (major == 5)
2529                 major = 4;
2530         else if (major == 0)
2531                 major = 1;
2532         if (major != priv->version) {
2533                 dev_err(&priv->pdev->dev,
2534                         "GENET version mismatch, got: %d, configured for: %d\n",
2535                         major, priv->version);
2536         }
2537
2538         /* Print the GENET core version */
2539         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
2540                  major, (reg >> 16) & 0x0f, reg & 0xffff);
2541
2542         /* Store the integrated PHY revision for the MDIO probing function
2543          * to pass this information to the PHY driver. The PHY driver expects
2544          * to find the PHY major revision in bits 15:8 while the GENET register
2545          * stores that information in bits 7:0, account for that.
2546          */
2547         priv->gphy_rev = (reg & 0xffff) << 8;
2548
2549 #ifdef CONFIG_PHYS_ADDR_T_64BIT
2550         if (!(params->flags & GENET_HAS_40BITS))
2551                 pr_warn("GENET does not support 40-bits PA\n");
2552 #endif
2553
2554         pr_debug("Configuration for version: %d\n"
2555                 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2556                 "BP << en: %2d, BP msk: 0x%05x\n"
2557                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2558                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2559                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2560                 "Words/BD: %d\n",
2561                 priv->version,
2562                 params->tx_queues, params->rx_queues, params->bds_cnt,
2563                 params->bp_in_en_shift, params->bp_in_mask,
2564                 params->hfb_filter_cnt, params->qtag_mask,
2565                 params->tbuf_offset, params->hfb_offset,
2566                 params->hfb_reg_offset,
2567                 params->rdma_offset, params->tdma_offset,
2568                 params->words_per_bd);
2569 }
2570
2571 static const struct of_device_id bcmgenet_match[] = {
2572         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2573         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2574         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2575         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2576         { },
2577 };
2578
2579 static int bcmgenet_probe(struct platform_device *pdev)
2580 {
2581         struct device_node *dn = pdev->dev.of_node;
2582         const struct of_device_id *of_id;
2583         struct bcmgenet_priv *priv;
2584         struct net_device *dev;
2585         const void *macaddr;
2586         struct resource *r;
2587         int err = -EIO;
2588
2589         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2590         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2591         if (!dev) {
2592                 dev_err(&pdev->dev, "can't allocate net device\n");
2593                 return -ENOMEM;
2594         }
2595
2596         of_id = of_match_node(bcmgenet_match, dn);
2597         if (!of_id)
2598                 return -EINVAL;
2599
2600         priv = netdev_priv(dev);
2601         priv->irq0 = platform_get_irq(pdev, 0);
2602         priv->irq1 = platform_get_irq(pdev, 1);
2603         priv->wol_irq = platform_get_irq(pdev, 2);
2604         if (!priv->irq0 || !priv->irq1) {
2605                 dev_err(&pdev->dev, "can't find IRQs\n");
2606                 err = -EINVAL;
2607                 goto err;
2608         }
2609
2610         macaddr = of_get_mac_address(dn);
2611         if (!macaddr) {
2612                 dev_err(&pdev->dev, "can't find MAC address\n");
2613                 err = -EINVAL;
2614                 goto err;
2615         }
2616
2617         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2618         priv->base = devm_ioremap_resource(&pdev->dev, r);
2619         if (IS_ERR(priv->base)) {
2620                 err = PTR_ERR(priv->base);
2621                 goto err;
2622         }
2623
2624         SET_NETDEV_DEV(dev, &pdev->dev);
2625         dev_set_drvdata(&pdev->dev, dev);
2626         ether_addr_copy(dev->dev_addr, macaddr);
2627         dev->watchdog_timeo = 2 * HZ;
2628         dev->ethtool_ops = &bcmgenet_ethtool_ops;
2629         dev->netdev_ops = &bcmgenet_netdev_ops;
2630         netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2631
2632         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2633
2634         /* Set hardware features */
2635         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2636                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2637
2638         /* Request the WOL interrupt and advertise suspend if available */
2639         priv->wol_irq_disabled = true;
2640         err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2641                                dev->name, priv);
2642         if (!err)
2643                 device_set_wakeup_capable(&pdev->dev, 1);
2644
2645         /* Set the needed headroom to account for any possible
2646          * features enabling/disabling at runtime
2647          */
2648         dev->needed_headroom += 64;
2649
2650         netdev_boot_setup_check(dev);
2651
2652         priv->dev = dev;
2653         priv->pdev = pdev;
2654         priv->version = (enum bcmgenet_version)of_id->data;
2655
2656         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2657         if (IS_ERR(priv->clk))
2658                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2659
2660         if (!IS_ERR(priv->clk))
2661                 clk_prepare_enable(priv->clk);
2662
2663         bcmgenet_set_hw_params(priv);
2664
2665         /* Mii wait queue */
2666         init_waitqueue_head(&priv->wq);
2667         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2668         priv->rx_buf_len = RX_BUF_LENGTH;
2669         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2670
2671         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2672         if (IS_ERR(priv->clk_wol))
2673                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2674
2675         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
2676         if (IS_ERR(priv->clk_eee)) {
2677                 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
2678                 priv->clk_eee = NULL;
2679         }
2680
2681         err = reset_umac(priv);
2682         if (err)
2683                 goto err_clk_disable;
2684
2685         err = bcmgenet_mii_init(dev);
2686         if (err)
2687                 goto err_clk_disable;
2688
2689         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
2690          * just the ring 16 descriptor based TX
2691          */
2692         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2693         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2694
2695         /* libphy will determine the link state */
2696         netif_carrier_off(dev);
2697
2698         /* Turn off the main clock, WOL clock is handled separately */
2699         if (!IS_ERR(priv->clk))
2700                 clk_disable_unprepare(priv->clk);
2701
2702         err = register_netdev(dev);
2703         if (err)
2704                 goto err;
2705
2706         return err;
2707
2708 err_clk_disable:
2709         if (!IS_ERR(priv->clk))
2710                 clk_disable_unprepare(priv->clk);
2711 err:
2712         free_netdev(dev);
2713         return err;
2714 }
2715
2716 static int bcmgenet_remove(struct platform_device *pdev)
2717 {
2718         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2719
2720         dev_set_drvdata(&pdev->dev, NULL);
2721         unregister_netdev(priv->dev);
2722         bcmgenet_mii_exit(priv->dev);
2723         free_netdev(priv->dev);
2724
2725         return 0;
2726 }
2727
2728 #ifdef CONFIG_PM_SLEEP
2729 static int bcmgenet_suspend(struct device *d)
2730 {
2731         struct net_device *dev = dev_get_drvdata(d);
2732         struct bcmgenet_priv *priv = netdev_priv(dev);
2733         int ret;
2734
2735         if (!netif_running(dev))
2736                 return 0;
2737
2738         bcmgenet_netif_stop(dev);
2739
2740         phy_suspend(priv->phydev);
2741
2742         netif_device_detach(dev);
2743
2744         /* Disable MAC receive */
2745         umac_enable_set(priv, CMD_RX_EN, false);
2746
2747         ret = bcmgenet_dma_teardown(priv);
2748         if (ret)
2749                 return ret;
2750
2751         /* Disable MAC transmit. TX DMA disabled have to done before this */
2752         umac_enable_set(priv, CMD_TX_EN, false);
2753
2754         /* tx reclaim */
2755         bcmgenet_tx_reclaim_all(dev);
2756         bcmgenet_fini_dma(priv);
2757
2758         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2759         if (device_may_wakeup(d) && priv->wolopts) {
2760                 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2761                 clk_prepare_enable(priv->clk_wol);
2762         }
2763
2764         /* Turn off the clocks */
2765         clk_disable_unprepare(priv->clk);
2766
2767         return 0;
2768 }
2769
2770 static int bcmgenet_resume(struct device *d)
2771 {
2772         struct net_device *dev = dev_get_drvdata(d);
2773         struct bcmgenet_priv *priv = netdev_priv(dev);
2774         unsigned long dma_ctrl;
2775         int ret;
2776         u32 reg;
2777
2778         if (!netif_running(dev))
2779                 return 0;
2780
2781         /* Turn on the clock */
2782         ret = clk_prepare_enable(priv->clk);
2783         if (ret)
2784                 return ret;
2785
2786         bcmgenet_umac_reset(priv);
2787
2788         ret = init_umac(priv);
2789         if (ret)
2790                 goto out_clk_disable;
2791
2792         /* From WOL-enabled suspend, switch to regular clock */
2793         if (priv->wolopts)
2794                 clk_disable_unprepare(priv->clk_wol);
2795
2796         phy_init_hw(priv->phydev);
2797         /* Speed settings must be restored */
2798         bcmgenet_mii_config(priv->dev, false);
2799
2800         /* disable ethernet MAC while updating its registers */
2801         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2802
2803         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2804
2805         if (phy_is_internal(priv->phydev)) {
2806                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2807                 reg |= EXT_ENERGY_DET_MASK;
2808                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2809         }
2810
2811         if (priv->wolopts)
2812                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2813
2814         /* Disable RX/TX DMA and flush TX queues */
2815         dma_ctrl = bcmgenet_dma_disable(priv);
2816
2817         /* Reinitialize TDMA and RDMA and SW housekeeping */
2818         ret = bcmgenet_init_dma(priv);
2819         if (ret) {
2820                 netdev_err(dev, "failed to initialize DMA\n");
2821                 goto out_clk_disable;
2822         }
2823
2824         /* Always enable ring 16 - descriptor ring */
2825         bcmgenet_enable_dma(priv, dma_ctrl);
2826
2827         netif_device_attach(dev);
2828
2829         phy_resume(priv->phydev);
2830
2831         if (priv->eee.eee_enabled)
2832                 bcmgenet_eee_enable_set(dev, true);
2833
2834         bcmgenet_netif_start(dev);
2835
2836         return 0;
2837
2838 out_clk_disable:
2839         clk_disable_unprepare(priv->clk);
2840         return ret;
2841 }
2842 #endif /* CONFIG_PM_SLEEP */
2843
2844 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
2845
2846 static struct platform_driver bcmgenet_driver = {
2847         .probe  = bcmgenet_probe,
2848         .remove = bcmgenet_remove,
2849         .driver = {
2850                 .name   = "bcmgenet",
2851                 .owner  = THIS_MODULE,
2852                 .of_match_table = bcmgenet_match,
2853                 .pm     = &bcmgenet_pm_ops,
2854         },
2855 };
2856 module_platform_driver(bcmgenet_driver);
2857
2858 MODULE_AUTHOR("Broadcom Corporation");
2859 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2860 MODULE_ALIAS("platform:bcmgenet");
2861 MODULE_LICENSE("GPL");