drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/types.h>
  17 #include <linux/fcntl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/string.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_platform.h>
  33 #include <net/arp.h>
  34
  35 #include <linux/mii.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/in.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/phy.h>
  45
  46 #include <asm/unaligned.h>
  47
  48 #include "bcmgenet.h"
  49
  50 /* Maximum number of hardware queues, downsized if needed */
  51 #define GENET_MAX_MQ_CNT        4
  52
  53 /* Default highest priority queue for multi queue support */
  54 #define GENET_Q0_PRIORITY       0
  55
  56 #define GENET_DEFAULT_BD_CNT    \
  57         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
  58
  59 #define RX_BUF_LENGTH           2048
  60 #define SKB_ALIGNMENT           32
  61
  62 /* Tx/Rx DMA register offset, skip 256 descriptors */
  63 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  64 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  65
  66 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  67                                 TOTAL_DESC * DMA_DESC_SIZE)
  68
  69 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  70                                 TOTAL_DESC * DMA_DESC_SIZE)
  71
  72 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  73                                              void __iomem *d, u32 value)
  74 {
  75         __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
  76 }
  77
  78 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
  79                                             void __iomem *d)
  80 {
  81         return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
  82 }
  83
  84 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
  85                                     void __iomem *d,
  86                                     dma_addr_t addr)
  87 {
  88         __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
  89
  90         /* Register writes to GISB bus can take couple hundred nanoseconds
  91          * and are done for each packet, save these expensive writes unless
  92          * the platform is explicitly configured for 64-bits/LPAE.
  93          */
  94 #ifdef CONFIG_PHYS_ADDR_T_64BIT
  95         if (priv->hw_params->flags & GENET_HAS_40BITS)
  96                 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
  97 #endif
  98 }
  99
 100 /* Combined address + length/status setter */
 101 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 102                                void __iomem *d, dma_addr_t addr, u32 val)
 103 {
 104         dmadesc_set_length_status(priv, d, val);
 105         dmadesc_set_addr(priv, d, addr);
 106 }
 107
 108 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 109                                           void __iomem *d)
 110 {
 111         dma_addr_t addr;
 112
 113         addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
 114
 115         /* Register writes to GISB bus can take couple hundred nanoseconds
 116          * and are done for each packet, save these expensive writes unless
 117          * the platform is explicitly configured for 64-bits/LPAE.
 118          */
 119 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 120         if (priv->hw_params->flags & GENET_HAS_40BITS)
 121                 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 122 #endif
 123         return addr;
 124 }
 125
 126 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 127
 128 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 129                                 NETIF_MSG_LINK)
 130
 131 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 132 {
 133         if (GENET_IS_V1(priv))
 134                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 135         else
 136                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 137 }
 138
 139 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 140 {
 141         if (GENET_IS_V1(priv))
 142                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 143         else
 144                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 145 }
 146
 147 /* These macros are defined to deal with register map change
 148  * between GENET1.1 and GENET2. Only those currently being used
 149  * by driver are defined.
 150  */
 151 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 152 {
 153         if (GENET_IS_V1(priv))
 154                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 155         else
 156                 return __raw_readl(priv->base +
 157                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 158 }
 159
 160 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 161 {
 162         if (GENET_IS_V1(priv))
 163                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 164         else
 165                 __raw_writel(val, priv->base +
 166                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 167 }
 168
 169 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 170 {
 171         if (GENET_IS_V1(priv))
 172                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 173         else
 174                 return __raw_readl(priv->base +
 175                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 176 }
 177
 178 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 179 {
 180         if (GENET_IS_V1(priv))
 181                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 182         else
 183                 __raw_writel(val, priv->base +
 184                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 185 }
 186
 187 /* RX/TX DMA register accessors */
 188 enum dma_reg {
 189         DMA_RING_CFG = 0,
 190         DMA_CTRL,
 191         DMA_STATUS,
 192         DMA_SCB_BURST_SIZE,
 193         DMA_ARB_CTRL,
 194         DMA_PRIORITY_0,
 195         DMA_PRIORITY_1,
 196         DMA_PRIORITY_2,
 197 };
 198
 199 static const u8 bcmgenet_dma_regs_v3plus[] = {
 200         [DMA_RING_CFG]          = 0x00,
 201         [DMA_CTRL]              = 0x04,
 202         [DMA_STATUS]            = 0x08,
 203         [DMA_SCB_BURST_SIZE]    = 0x0C,
 204         [DMA_ARB_CTRL]          = 0x2C,
 205         [DMA_PRIORITY_0]        = 0x30,
 206         [DMA_PRIORITY_1]        = 0x34,
 207         [DMA_PRIORITY_2]        = 0x38,
 208 };
 209
 210 static const u8 bcmgenet_dma_regs_v2[] = {
 211         [DMA_RING_CFG]          = 0x00,
 212         [DMA_CTRL]              = 0x04,
 213         [DMA_STATUS]            = 0x08,
 214         [DMA_SCB_BURST_SIZE]    = 0x0C,
 215         [DMA_ARB_CTRL]          = 0x30,
 216         [DMA_PRIORITY_0]        = 0x34,
 217         [DMA_PRIORITY_1]        = 0x38,
 218         [DMA_PRIORITY_2]        = 0x3C,
 219 };
 220
 221 static const u8 bcmgenet_dma_regs_v1[] = {
 222         [DMA_CTRL]              = 0x00,
 223         [DMA_STATUS]            = 0x04,
 224         [DMA_SCB_BURST_SIZE]    = 0x0C,
 225         [DMA_ARB_CTRL]          = 0x30,
 226         [DMA_PRIORITY_0]        = 0x34,
 227         [DMA_PRIORITY_1]        = 0x38,
 228         [DMA_PRIORITY_2]        = 0x3C,
 229 };
 230
 231 /* Set at runtime once bcmgenet version is known */
 232 static const u8 *bcmgenet_dma_regs;
 233
 234 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 235 {
 236         return netdev_priv(dev_get_drvdata(dev));
 237 }
 238
 239 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 240                                       enum dma_reg r)
 241 {
 242         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 243                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 244 }
 245
 246 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 247                                         u32 val, enum dma_reg r)
 248 {
 249         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 250                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 251 }
 252
 253 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 254                                       enum dma_reg r)
 255 {
 256         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 257                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 258 }
 259
 260 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 261                                         u32 val, enum dma_reg r)
 262 {
 263         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 264                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 265 }
 266
 267 /* RDMA/TDMA ring registers and accessors
 268  * we merge the common fields and just prefix with T/D the registers
 269  * having different meaning depending on the direction
 270  */
 271 enum dma_ring_reg {
 272         TDMA_READ_PTR = 0,
 273         RDMA_WRITE_PTR = TDMA_READ_PTR,
 274         TDMA_READ_PTR_HI,
 275         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 276         TDMA_CONS_INDEX,
 277         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 278         TDMA_PROD_INDEX,
 279         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 280         DMA_RING_BUF_SIZE,
 281         DMA_START_ADDR,
 282         DMA_START_ADDR_HI,
 283         DMA_END_ADDR,
 284         DMA_END_ADDR_HI,
 285         DMA_MBUF_DONE_THRESH,
 286         TDMA_FLOW_PERIOD,
 287         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 288         TDMA_WRITE_PTR,
 289         RDMA_READ_PTR = TDMA_WRITE_PTR,
 290         TDMA_WRITE_PTR_HI,
 291         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 292 };
 293
 294 /* GENET v4 supports 40-bits pointer addressing
 295  * for obvious reasons the LO and HI word parts
 296  * are contiguous, but this offsets the other
 297  * registers.
 298  */
 299 static const u8 genet_dma_ring_regs_v4[] = {
 300         [TDMA_READ_PTR]                 = 0x00,
 301         [TDMA_READ_PTR_HI]              = 0x04,
 302         [TDMA_CONS_INDEX]               = 0x08,
 303         [TDMA_PROD_INDEX]               = 0x0C,
 304         [DMA_RING_BUF_SIZE]             = 0x10,
 305         [DMA_START_ADDR]                = 0x14,
 306         [DMA_START_ADDR_HI]             = 0x18,
 307         [DMA_END_ADDR]                  = 0x1C,
 308         [DMA_END_ADDR_HI]               = 0x20,
 309         [DMA_MBUF_DONE_THRESH]          = 0x24,
 310         [TDMA_FLOW_PERIOD]              = 0x28,
 311         [TDMA_WRITE_PTR]                = 0x2C,
 312         [TDMA_WRITE_PTR_HI]             = 0x30,
 313 };
 314
 315 static const u8 genet_dma_ring_regs_v123[] = {
 316         [TDMA_READ_PTR]                 = 0x00,
 317         [TDMA_CONS_INDEX]               = 0x04,
 318         [TDMA_PROD_INDEX]               = 0x08,
 319         [DMA_RING_BUF_SIZE]             = 0x0C,
 320         [DMA_START_ADDR]                = 0x10,
 321         [DMA_END_ADDR]                  = 0x14,
 322         [DMA_MBUF_DONE_THRESH]          = 0x18,
 323         [TDMA_FLOW_PERIOD]              = 0x1C,
 324         [TDMA_WRITE_PTR]                = 0x20,
 325 };
 326
 327 /* Set at runtime once GENET version is known */
 328 static const u8 *genet_dma_ring_regs;
 329
 330 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 331                                            unsigned int ring,
 332                                            enum dma_ring_reg r)
 333 {
 334         return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 335                         (DMA_RING_SIZE * ring) +
 336                         genet_dma_ring_regs[r]);
 337 }
 338
 339 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 340                                              unsigned int ring, u32 val,
 341                                              enum dma_ring_reg r)
 342 {
 343         __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 344                         (DMA_RING_SIZE * ring) +
 345                         genet_dma_ring_regs[r]);
 346 }
 347
 348 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 349                                            unsigned int ring,
 350                                            enum dma_ring_reg r)
 351 {
 352         return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 353                         (DMA_RING_SIZE * ring) +
 354                         genet_dma_ring_regs[r]);
 355 }
 356
 357 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 358                                              unsigned int ring, u32 val,
 359                                              enum dma_ring_reg r)
 360 {
 361         __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 362                         (DMA_RING_SIZE * ring) +
 363                         genet_dma_ring_regs[r]);
 364 }
 365
 366 static int bcmgenet_get_settings(struct net_device *dev,
 367                                  struct ethtool_cmd *cmd)
 368 {
 369         struct bcmgenet_priv *priv = netdev_priv(dev);
 370
 371         if (!netif_running(dev))
 372                 return -EINVAL;
 373
 374         if (!priv->phydev)
 375                 return -ENODEV;
 376
 377         return phy_ethtool_gset(priv->phydev, cmd);
 378 }
 379
 380 static int bcmgenet_set_settings(struct net_device *dev,
 381                                  struct ethtool_cmd *cmd)
 382 {
 383         struct bcmgenet_priv *priv = netdev_priv(dev);
 384
 385         if (!netif_running(dev))
 386                 return -EINVAL;
 387
 388         if (!priv->phydev)
 389                 return -ENODEV;
 390
 391         return phy_ethtool_sset(priv->phydev, cmd);
 392 }
 393
 394 static int bcmgenet_set_rx_csum(struct net_device *dev,
 395                                 netdev_features_t wanted)
 396 {
 397         struct bcmgenet_priv *priv = netdev_priv(dev);
 398         u32 rbuf_chk_ctrl;
 399         bool rx_csum_en;
 400
 401         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 402
 403         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 404
 405         /* enable rx checksumming */
 406         if (rx_csum_en)
 407                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 408         else
 409                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 410         priv->desc_rxchk_en = rx_csum_en;
 411
 412         /* If UniMAC forwards CRC, we need to skip over it to get
 413          * a valid CHK bit to be set in the per-packet status word
 414         */
 415         if (rx_csum_en && priv->crc_fwd_en)
 416                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 417         else
 418                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 419
 420         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 421
 422         return 0;
 423 }
 424
 425 static int bcmgenet_set_tx_csum(struct net_device *dev,
 426                                 netdev_features_t wanted)
 427 {
 428         struct bcmgenet_priv *priv = netdev_priv(dev);
 429         bool desc_64b_en;
 430         u32 tbuf_ctrl, rbuf_ctrl;
 431
 432         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 433         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 434
 435         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 436
 437         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 438         if (desc_64b_en) {
 439                 tbuf_ctrl |= RBUF_64B_EN;
 440                 rbuf_ctrl |= RBUF_64B_EN;
 441         } else {
 442                 tbuf_ctrl &= ~RBUF_64B_EN;
 443                 rbuf_ctrl &= ~RBUF_64B_EN;
 444         }
 445         priv->desc_64b_en = desc_64b_en;
 446
 447         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 448         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 449
 450         return 0;
 451 }
 452
 453 static int bcmgenet_set_features(struct net_device *dev,
 454                                  netdev_features_t features)
 455 {
 456         netdev_features_t changed = features ^ dev->features;
 457         netdev_features_t wanted = dev->wanted_features;
 458         int ret = 0;
 459
 460         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 461                 ret = bcmgenet_set_tx_csum(dev, wanted);
 462         if (changed & (NETIF_F_RXCSUM))
 463                 ret = bcmgenet_set_rx_csum(dev, wanted);
 464
 465         return ret;
 466 }
 467
 468 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 469 {
 470         struct bcmgenet_priv *priv = netdev_priv(dev);
 471
 472         return priv->msg_enable;
 473 }
 474
 475 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 476 {
 477         struct bcmgenet_priv *priv = netdev_priv(dev);
 478
 479         priv->msg_enable = level;
 480 }
 481
 482 /* standard ethtool support functions. */
 483 enum bcmgenet_stat_type {
 484         BCMGENET_STAT_NETDEV = -1,
 485         BCMGENET_STAT_MIB_RX,
 486         BCMGENET_STAT_MIB_TX,
 487         BCMGENET_STAT_RUNT,
 488         BCMGENET_STAT_MISC,
 489 };
 490
 491 struct bcmgenet_stats {
 492         char stat_string[ETH_GSTRING_LEN];
 493         int stat_sizeof;
 494         int stat_offset;
 495         enum bcmgenet_stat_type type;
 496         /* reg offset from UMAC base for misc counters */
 497         u16 reg_offset;
 498 };
 499
 500 #define STAT_NETDEV(m) { \
 501         .stat_string = __stringify(m), \
 502         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 503         .stat_offset = offsetof(struct net_device_stats, m), \
 504         .type = BCMGENET_STAT_NETDEV, \
 505 }
 506
 507 #define STAT_GENET_MIB(str, m, _type) { \
 508         .stat_string = str, \
 509         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 510         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 511         .type = _type, \
 512 }
 513
 514 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 515 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 516 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 517
 518 #define STAT_GENET_MISC(str, m, offset) { \
 519         .stat_string = str, \
 520         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 521         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 522         .type = BCMGENET_STAT_MISC, \
 523         .reg_offset = offset, \
 524 }
 525
 526
 527 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 528  * between the end of TX stats and the beginning of the RX RUNT
 529  */
 530 #define BCMGENET_STAT_OFFSET    0xc
 531
 532 /* Hardware counters must be kept in sync because the order/offset
 533  * is important here (order in structure declaration = order in hardware)
 534  */
 535 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 536         /* general stats */
 537         STAT_NETDEV(rx_packets),
 538         STAT_NETDEV(tx_packets),
 539         STAT_NETDEV(rx_bytes),
 540         STAT_NETDEV(tx_bytes),
 541         STAT_NETDEV(rx_errors),
 542         STAT_NETDEV(tx_errors),
 543         STAT_NETDEV(rx_dropped),
 544         STAT_NETDEV(tx_dropped),
 545         STAT_NETDEV(multicast),
 546         /* UniMAC RSV counters */
 547         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 548         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 549         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 550         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 551         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 552         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 553         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 554         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 555         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 556         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 557         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 558         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 559         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 560         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 561         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 562         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 563         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 564         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 565         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 566         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 567         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 568         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 569         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 570         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 571         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 572         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 573         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 574         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 575         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 576         /* UniMAC TSV counters */
 577         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 578         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 579         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 580         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 581         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 582         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 583         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 584         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 585         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 586         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 587         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 588         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 589         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 590         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 591         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 592         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 593         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 594         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 595         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 596         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 597         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 598         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 599         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 600         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 601         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 602         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 603         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 604         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 605         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 606         /* UniMAC RUNT counters */
 607         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 608         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 609         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 610         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 611         /* Misc UniMAC counters */
 612         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 613                         UMAC_RBUF_OVFL_CNT),
 614         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
 615         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 616         STAT_GENET_MIB_RX("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 617         STAT_GENET_MIB_RX("rx_dma_failed", mib.rx_dma_failed),
 618         STAT_GENET_MIB_TX("tx_dma_failed", mib.tx_dma_failed),
 619 };
 620
 621 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 622
 623 static void bcmgenet_get_drvinfo(struct net_device *dev,
 624                                  struct ethtool_drvinfo *info)
 625 {
 626         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 627         strlcpy(info->version, "v2.0", sizeof(info->version));
 628         info->n_stats = BCMGENET_STATS_LEN;
 629 }
 630
 631 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 632 {
 633         switch (string_set) {
 634         case ETH_SS_STATS:
 635                 return BCMGENET_STATS_LEN;
 636         default:
 637                 return -EOPNOTSUPP;
 638         }
 639 }
 640
 641 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 642                                  u8 *data)
 643 {
 644         int i;
 645
 646         switch (stringset) {
 647         case ETH_SS_STATS:
 648                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 649                         memcpy(data + i * ETH_GSTRING_LEN,
 650                                bcmgenet_gstrings_stats[i].stat_string,
 651                                ETH_GSTRING_LEN);
 652                 }
 653                 break;
 654         }
 655 }
 656
 657 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 658 {
 659         int i, j = 0;
 660
 661         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 662                 const struct bcmgenet_stats *s;
 663                 u8 offset = 0;
 664                 u32 val = 0;
 665                 char *p;
 666
 667                 s = &bcmgenet_gstrings_stats[i];
 668                 switch (s->type) {
 669                 case BCMGENET_STAT_NETDEV:
 670                         continue;
 671                 case BCMGENET_STAT_MIB_RX:
 672                 case BCMGENET_STAT_MIB_TX:
 673                 case BCMGENET_STAT_RUNT:
 674                         if (s->type != BCMGENET_STAT_MIB_RX)
 675                                 offset = BCMGENET_STAT_OFFSET;
 676                         val = bcmgenet_umac_readl(priv,
 677                                                   UMAC_MIB_START + j + offset);
 678                         break;
 679                 case BCMGENET_STAT_MISC:
 680                         val = bcmgenet_umac_readl(priv, s->reg_offset);
 681                         /* clear if overflowed */
 682                         if (val == ~0)
 683                                 bcmgenet_umac_writel(priv, 0, s->reg_offset);
 684                         break;
 685                 }
 686
 687                 j += s->stat_sizeof;
 688                 p = (char *)priv + s->stat_offset;
 689                 *(u32 *)p = val;
 690         }
 691 }
 692
 693 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 694                                        struct ethtool_stats *stats,
 695                                        u64 *data)
 696 {
 697         struct bcmgenet_priv *priv = netdev_priv(dev);
 698         int i;
 699
 700         if (netif_running(dev))
 701                 bcmgenet_update_mib_counters(priv);
 702
 703         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 704                 const struct bcmgenet_stats *s;
 705                 char *p;
 706
 707                 s = &bcmgenet_gstrings_stats[i];
 708                 if (s->type == BCMGENET_STAT_NETDEV)
 709                         p = (char *)&dev->stats;
 710                 else
 711                         p = (char *)priv;
 712                 p += s->stat_offset;
 713                 data[i] = *(u32 *)p;
 714         }
 715 }
 716
 717 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
 718 {
 719         struct bcmgenet_priv *priv = netdev_priv(dev);
 720         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
 721         u32 reg;
 722
 723         if (enable && !priv->clk_eee_enabled) {
 724                 clk_prepare_enable(priv->clk_eee);
 725                 priv->clk_eee_enabled = true;
 726         }
 727
 728         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
 729         if (enable)
 730                 reg |= EEE_EN;
 731         else
 732                 reg &= ~EEE_EN;
 733         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
 734
 735         /* Enable EEE and switch to a 27Mhz clock automatically */
 736         reg = __raw_readl(priv->base + off);
 737         if (enable)
 738                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
 739         else
 740                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
 741         __raw_writel(reg, priv->base + off);
 742
 743         /* Do the same for thing for RBUF */
 744         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
 745         if (enable)
 746                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
 747         else
 748                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
 749         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
 750
 751         if (!enable && priv->clk_eee_enabled) {
 752                 clk_disable_unprepare(priv->clk_eee);
 753                 priv->clk_eee_enabled = false;
 754         }
 755
 756         priv->eee.eee_enabled = enable;
 757         priv->eee.eee_active = enable;
 758 }
 759
 760 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
 761 {
 762         struct bcmgenet_priv *priv = netdev_priv(dev);
 763         struct ethtool_eee *p = &priv->eee;
 764
 765         if (GENET_IS_V1(priv))
 766                 return -EOPNOTSUPP;
 767
 768         e->eee_enabled = p->eee_enabled;
 769         e->eee_active = p->eee_active;
 770         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
 771
 772         return phy_ethtool_get_eee(priv->phydev, e);
 773 }
 774
 775 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
 776 {
 777         struct bcmgenet_priv *priv = netdev_priv(dev);
 778         struct ethtool_eee *p = &priv->eee;
 779         int ret = 0;
 780
 781         if (GENET_IS_V1(priv))
 782                 return -EOPNOTSUPP;
 783
 784         p->eee_enabled = e->eee_enabled;
 785
 786         if (!p->eee_enabled) {
 787                 bcmgenet_eee_enable_set(dev, false);
 788         } else {
 789                 ret = phy_init_eee(priv->phydev, 0);
 790                 if (ret) {
 791                         netif_err(priv, hw, dev, "EEE initialization failed\n");
 792                         return ret;
 793                 }
 794
 795                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
 796                 bcmgenet_eee_enable_set(dev, true);
 797         }
 798
 799         return phy_ethtool_set_eee(priv->phydev, e);
 800 }
 801
 802 static int bcmgenet_nway_reset(struct net_device *dev)
 803 {
 804         struct bcmgenet_priv *priv = netdev_priv(dev);
 805
 806         return genphy_restart_aneg(priv->phydev);
 807 }
 808
 809 /* standard ethtool support functions. */
 810 static struct ethtool_ops bcmgenet_ethtool_ops = {
 811         .get_strings            = bcmgenet_get_strings,
 812         .get_sset_count         = bcmgenet_get_sset_count,
 813         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
 814         .get_settings           = bcmgenet_get_settings,
 815         .set_settings           = bcmgenet_set_settings,
 816         .get_drvinfo            = bcmgenet_get_drvinfo,
 817         .get_link               = ethtool_op_get_link,
 818         .get_msglevel           = bcmgenet_get_msglevel,
 819         .set_msglevel           = bcmgenet_set_msglevel,
 820         .get_wol                = bcmgenet_get_wol,
 821         .set_wol                = bcmgenet_set_wol,
 822         .get_eee                = bcmgenet_get_eee,
 823         .set_eee                = bcmgenet_set_eee,
 824         .nway_reset             = bcmgenet_nway_reset,
 825 };
 826
 827 /* Power down the unimac, based on mode. */
 828 static void bcmgenet_power_down(struct bcmgenet_priv *priv,
 829                                 enum bcmgenet_power_mode mode)
 830 {
 831         u32 reg;
 832
 833         switch (mode) {
 834         case GENET_POWER_CABLE_SENSE:
 835                 phy_detach(priv->phydev);
 836                 break;
 837
 838         case GENET_POWER_WOL_MAGIC:
 839                 bcmgenet_wol_power_down_cfg(priv, mode);
 840                 break;
 841
 842         case GENET_POWER_PASSIVE:
 843                 /* Power down LED */
 844                 if (priv->hw_params->flags & GENET_HAS_EXT) {
 845                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 846                         reg |= (EXT_PWR_DOWN_PHY |
 847                                 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
 848                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 849                 }
 850                 break;
 851         default:
 852                 break;
 853         }
 854 }
 855
 856 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
 857                               enum bcmgenet_power_mode mode)
 858 {
 859         u32 reg;
 860
 861         if (!(priv->hw_params->flags & GENET_HAS_EXT))
 862                 return;
 863
 864         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 865
 866         switch (mode) {
 867         case GENET_POWER_PASSIVE:
 868                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
 869                                 EXT_PWR_DOWN_BIAS);
 870                 /* fallthrough */
 871         case GENET_POWER_CABLE_SENSE:
 872                 /* enable APD */
 873                 reg |= EXT_PWR_DN_EN_LD;
 874                 break;
 875         case GENET_POWER_WOL_MAGIC:
 876                 bcmgenet_wol_power_up_cfg(priv, mode);
 877                 return;
 878         default:
 879                 break;
 880         }
 881
 882         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 883
 884         if (mode == GENET_POWER_PASSIVE)
 885                 bcmgenet_mii_reset(priv->dev);
 886 }
 887
 888 /* ioctl handle special commands that are not present in ethtool. */
 889 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 890 {
 891         struct bcmgenet_priv *priv = netdev_priv(dev);
 892         int val = 0;
 893
 894         if (!netif_running(dev))
 895                 return -EINVAL;
 896
 897         switch (cmd) {
 898         case SIOCGMIIPHY:
 899         case SIOCGMIIREG:
 900         case SIOCSMIIREG:
 901                 if (!priv->phydev)
 902                         val = -ENODEV;
 903                 else
 904                         val = phy_mii_ioctl(priv->phydev, rq, cmd);
 905                 break;
 906
 907         default:
 908                 val = -EINVAL;
 909                 break;
 910         }
 911
 912         return val;
 913 }
 914
 915 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
 916                                          struct bcmgenet_tx_ring *ring)
 917 {
 918         struct enet_cb *tx_cb_ptr;
 919
 920         tx_cb_ptr = ring->cbs;
 921         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
 922         tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
 923         /* Advancing local write pointer */
 924         if (ring->write_ptr == ring->end_ptr)
 925                 ring->write_ptr = ring->cb_ptr;
 926         else
 927                 ring->write_ptr++;
 928
 929         return tx_cb_ptr;
 930 }
 931
 932 /* Simple helper to free a control block's resources */
 933 static void bcmgenet_free_cb(struct enet_cb *cb)
 934 {
 935         dev_kfree_skb_any(cb->skb);
 936         cb->skb = NULL;
 937         dma_unmap_addr_set(cb, dma_addr, 0);
 938 }
 939
 940 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
 941                                                   struct bcmgenet_tx_ring *ring)
 942 {
 943         bcmgenet_intrl2_0_writel(priv,
 944                                  UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
 945                                  INTRL2_CPU_MASK_SET);
 946 }
 947
 948 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
 949                                                  struct bcmgenet_tx_ring *ring)
 950 {
 951         bcmgenet_intrl2_0_writel(priv,
 952                                  UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
 953                                  INTRL2_CPU_MASK_CLEAR);
 954 }
 955
 956 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
 957                                                struct bcmgenet_tx_ring *ring)
 958 {
 959         bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
 960                                  INTRL2_CPU_MASK_CLEAR);
 961         priv->int1_mask &= ~(1 << ring->index);
 962 }
 963
 964 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
 965                                                 struct bcmgenet_tx_ring *ring)
 966 {
 967         bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
 968                                  INTRL2_CPU_MASK_SET);
 969         priv->int1_mask |= (1 << ring->index);
 970 }
 971
 972 /* Unlocked version of the reclaim routine */
 973 static void __bcmgenet_tx_reclaim(struct net_device *dev,
 974                                   struct bcmgenet_tx_ring *ring)
 975 {
 976         struct bcmgenet_priv *priv = netdev_priv(dev);
 977         int last_tx_cn, last_c_index, num_tx_bds;
 978         struct enet_cb *tx_cb_ptr;
 979         struct netdev_queue *txq;
 980         unsigned int bds_compl;
 981         unsigned int c_index;
 982
 983         /* Compute how many buffers are transmitted since last xmit call */
 984         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
 985         txq = netdev_get_tx_queue(dev, ring->queue);
 986
 987         last_c_index = ring->c_index;
 988         num_tx_bds = ring->size;
 989
 990         c_index &= (num_tx_bds - 1);
 991
 992         if (c_index >= last_c_index)
 993                 last_tx_cn = c_index - last_c_index;
 994         else
 995                 last_tx_cn = num_tx_bds - last_c_index + c_index;
 996
 997         netif_dbg(priv, tx_done, dev,
 998                   "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
 999                   __func__, ring->index,
1000                   c_index, last_tx_cn, last_c_index);
1001
1002         /* Reclaim transmitted buffers */
1003         while (last_tx_cn-- > 0) {
1004                 tx_cb_ptr = ring->cbs + last_c_index;
1005                 bds_compl = 0;
1006                 if (tx_cb_ptr->skb) {
1007                         bds_compl = skb_shinfo(tx_cb_ptr->skb)->nr_frags + 1;
1008                         dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1009                         dma_unmap_single(&dev->dev,
1010                                          dma_unmap_addr(tx_cb_ptr, dma_addr),
1011                                          tx_cb_ptr->skb->len,
1012                                          DMA_TO_DEVICE);
1013                         bcmgenet_free_cb(tx_cb_ptr);
1014                 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1015                         dev->stats.tx_bytes +=
1016                                 dma_unmap_len(tx_cb_ptr, dma_len);
1017                         dma_unmap_page(&dev->dev,
1018                                        dma_unmap_addr(tx_cb_ptr, dma_addr),
1019                                        dma_unmap_len(tx_cb_ptr, dma_len),
1020                                        DMA_TO_DEVICE);
1021                         dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1022                 }
1023                 dev->stats.tx_packets++;
1024                 ring->free_bds += bds_compl;
1025
1026                 last_c_index++;
1027                 last_c_index &= (num_tx_bds - 1);
1028         }
1029
1030         if (ring->free_bds > (MAX_SKB_FRAGS + 1))
1031                 ring->int_disable(priv, ring);
1032
1033         if (netif_tx_queue_stopped(txq))
1034                 netif_tx_wake_queue(txq);
1035
1036         ring->c_index = c_index;
1037 }
1038
1039 static void bcmgenet_tx_reclaim(struct net_device *dev,
1040                                 struct bcmgenet_tx_ring *ring)
1041 {
1042         unsigned long flags;
1043
1044         spin_lock_irqsave(&ring->lock, flags);
1045         __bcmgenet_tx_reclaim(dev, ring);
1046         spin_unlock_irqrestore(&ring->lock, flags);
1047 }
1048
1049 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1050 {
1051         struct bcmgenet_priv *priv = netdev_priv(dev);
1052         int i;
1053
1054         if (netif_is_multiqueue(dev)) {
1055                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1056                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1057         }
1058
1059         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1060 }
1061
1062 /* Transmits a single SKB (either head of a fragment or a single SKB)
1063  * caller must hold priv->lock
1064  */
1065 static int bcmgenet_xmit_single(struct net_device *dev,
1066                                 struct sk_buff *skb,
1067                                 u16 dma_desc_flags,
1068                                 struct bcmgenet_tx_ring *ring)
1069 {
1070         struct bcmgenet_priv *priv = netdev_priv(dev);
1071         struct device *kdev = &priv->pdev->dev;
1072         struct enet_cb *tx_cb_ptr;
1073         unsigned int skb_len;
1074         dma_addr_t mapping;
1075         u32 length_status;
1076         int ret;
1077
1078         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1079
1080         if (unlikely(!tx_cb_ptr))
1081                 BUG();
1082
1083         tx_cb_ptr->skb = skb;
1084
1085         skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1086
1087         mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1088         ret = dma_mapping_error(kdev, mapping);
1089         if (ret) {
1090                 priv->mib.tx_dma_failed++;
1091                 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1092                 dev_kfree_skb(skb);
1093                 return ret;
1094         }
1095
1096         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1097         dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1098         length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1099                         (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1100                         DMA_TX_APPEND_CRC;
1101
1102         if (skb->ip_summed == CHECKSUM_PARTIAL)
1103                 length_status |= DMA_TX_DO_CSUM;
1104
1105         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1106
1107         /* Decrement total BD count and advance our write pointer */
1108         ring->free_bds -= 1;
1109         ring->prod_index += 1;
1110         ring->prod_index &= DMA_P_INDEX_MASK;
1111
1112         return 0;
1113 }
1114
1115 /* Transmit a SKB fragment */
1116 static int bcmgenet_xmit_frag(struct net_device *dev,
1117                               skb_frag_t *frag,
1118                               u16 dma_desc_flags,
1119                               struct bcmgenet_tx_ring *ring)
1120 {
1121         struct bcmgenet_priv *priv = netdev_priv(dev);
1122         struct device *kdev = &priv->pdev->dev;
1123         struct enet_cb *tx_cb_ptr;
1124         dma_addr_t mapping;
1125         int ret;
1126
1127         tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1128
1129         if (unlikely(!tx_cb_ptr))
1130                 BUG();
1131         tx_cb_ptr->skb = NULL;
1132
1133         mapping = skb_frag_dma_map(kdev, frag, 0,
1134                                    skb_frag_size(frag), DMA_TO_DEVICE);
1135         ret = dma_mapping_error(kdev, mapping);
1136         if (ret) {
1137                 priv->mib.tx_dma_failed++;
1138                 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1139                           __func__);
1140                 return ret;
1141         }
1142
1143         dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1144         dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1145
1146         dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1147                     (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1148                     (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1149
1150
1151         ring->free_bds -= 1;
1152         ring->prod_index += 1;
1153         ring->prod_index &= DMA_P_INDEX_MASK;
1154
1155         return 0;
1156 }
1157
1158 /* Reallocate the SKB to put enough headroom in front of it and insert
1159  * the transmit checksum offsets in the descriptors
1160  */
1161 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1162                                             struct sk_buff *skb)
1163 {
1164         struct status_64 *status = NULL;
1165         struct sk_buff *new_skb;
1166         u16 offset;
1167         u8 ip_proto;
1168         u16 ip_ver;
1169         u32 tx_csum_info;
1170
1171         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1172                 /* If 64 byte status block enabled, must make sure skb has
1173                  * enough headroom for us to insert 64B status block.
1174                  */
1175                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1176                 dev_kfree_skb(skb);
1177                 if (!new_skb) {
1178                         dev->stats.tx_errors++;
1179                         dev->stats.tx_dropped++;
1180                         return NULL;
1181                 }
1182                 skb = new_skb;
1183         }
1184
1185         skb_push(skb, sizeof(*status));
1186         status = (struct status_64 *)skb->data;
1187
1188         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1189                 ip_ver = htons(skb->protocol);
1190                 switch (ip_ver) {
1191                 case ETH_P_IP:
1192                         ip_proto = ip_hdr(skb)->protocol;
1193                         break;
1194                 case ETH_P_IPV6:
1195                         ip_proto = ipv6_hdr(skb)->nexthdr;
1196                         break;
1197                 default:
1198                         return skb;
1199                 }
1200
1201                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1202                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1203                                 (offset + skb->csum_offset);
1204
1205                 /* Set the length valid bit for TCP and UDP and just set
1206                  * the special UDP flag for IPv4, else just set to 0.
1207                  */
1208                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1209                         tx_csum_info |= STATUS_TX_CSUM_LV;
1210                         if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1211                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1212                 } else {
1213                         tx_csum_info = 0;
1214                 }
1215
1216                 status->tx_csum_info = tx_csum_info;
1217         }
1218
1219         return skb;
1220 }
1221
1222 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1223 {
1224         struct bcmgenet_priv *priv = netdev_priv(dev);
1225         struct bcmgenet_tx_ring *ring = NULL;
1226         struct netdev_queue *txq;
1227         unsigned long flags = 0;
1228         int nr_frags, index;
1229         u16 dma_desc_flags;
1230         int ret;
1231         int i;
1232
1233         index = skb_get_queue_mapping(skb);
1234         /* Mapping strategy:
1235          * queue_mapping = 0, unclassified, packet xmited through ring16
1236          * queue_mapping = 1, goes to ring 0. (highest priority queue
1237          * queue_mapping = 2, goes to ring 1.
1238          * queue_mapping = 3, goes to ring 2.
1239          * queue_mapping = 4, goes to ring 3.
1240          */
1241         if (index == 0)
1242                 index = DESC_INDEX;
1243         else
1244                 index -= 1;
1245
1246         nr_frags = skb_shinfo(skb)->nr_frags;
1247         ring = &priv->tx_rings[index];
1248         txq = netdev_get_tx_queue(dev, ring->queue);
1249
1250         spin_lock_irqsave(&ring->lock, flags);
1251         if (ring->free_bds <= nr_frags + 1) {
1252                 netif_tx_stop_queue(txq);
1253                 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1254                            __func__, index, ring->queue);
1255                 ret = NETDEV_TX_BUSY;
1256                 goto out;
1257         }
1258
1259         if (skb_padto(skb, ETH_ZLEN)) {
1260                 ret = NETDEV_TX_OK;
1261                 goto out;
1262         }
1263
1264         /* set the SKB transmit checksum */
1265         if (priv->desc_64b_en) {
1266                 skb = bcmgenet_put_tx_csum(dev, skb);
1267                 if (!skb) {
1268                         ret = NETDEV_TX_OK;
1269                         goto out;
1270                 }
1271         }
1272
1273         dma_desc_flags = DMA_SOP;
1274         if (nr_frags == 0)
1275                 dma_desc_flags |= DMA_EOP;
1276
1277         /* Transmit single SKB or head of fragment list */
1278         ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1279         if (ret) {
1280                 ret = NETDEV_TX_OK;
1281                 goto out;
1282         }
1283
1284         /* xmit fragment */
1285         for (i = 0; i < nr_frags; i++) {
1286                 ret = bcmgenet_xmit_frag(dev,
1287                                          &skb_shinfo(skb)->frags[i],
1288                                          (i == nr_frags - 1) ? DMA_EOP : 0,
1289                                          ring);
1290                 if (ret) {
1291                         ret = NETDEV_TX_OK;
1292                         goto out;
1293                 }
1294         }
1295
1296         skb_tx_timestamp(skb);
1297
1298         /* we kept a software copy of how much we should advance the TDMA
1299          * producer index, now write it down to the hardware
1300          */
1301         bcmgenet_tdma_ring_writel(priv, ring->index,
1302                                   ring->prod_index, TDMA_PROD_INDEX);
1303
1304         if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
1305                 netif_tx_stop_queue(txq);
1306                 ring->int_enable(priv, ring);
1307         }
1308
1309 out:
1310         spin_unlock_irqrestore(&ring->lock, flags);
1311
1312         return ret;
1313 }
1314
1315
1316 static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb)
1317 {
1318         struct device *kdev = &priv->pdev->dev;
1319         struct sk_buff *skb;
1320         dma_addr_t mapping;
1321         int ret;
1322
1323         skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1324         if (!skb)
1325                 return -ENOMEM;
1326
1327         /* a caller did not release this control block */
1328         WARN_ON(cb->skb != NULL);
1329         cb->skb = skb;
1330         mapping = dma_map_single(kdev, skb->data,
1331                                  priv->rx_buf_len, DMA_FROM_DEVICE);
1332         ret = dma_mapping_error(kdev, mapping);
1333         if (ret) {
1334                 priv->mib.rx_dma_failed++;
1335                 bcmgenet_free_cb(cb);
1336                 netif_err(priv, rx_err, priv->dev,
1337                           "%s DMA map failed\n", __func__);
1338                 return ret;
1339         }
1340
1341         dma_unmap_addr_set(cb, dma_addr, mapping);
1342         /* assign packet, prepare descriptor, and advance pointer */
1343
1344         dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1345
1346         /* turn on the newly assigned BD for DMA to use */
1347         priv->rx_bd_assign_index++;
1348         priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1349
1350         priv->rx_bd_assign_ptr = priv->rx_bds +
1351                 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1352
1353         return 0;
1354 }
1355
1356 /* bcmgenet_desc_rx - descriptor based rx process.
1357  * this could be called from bottom half, or from NAPI polling method.
1358  */
1359 static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1360                                      unsigned int budget)
1361 {
1362         struct net_device *dev = priv->dev;
1363         struct enet_cb *cb;
1364         struct sk_buff *skb;
1365         u32 dma_length_status;
1366         unsigned long dma_flag;
1367         int len, err;
1368         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1369         unsigned int p_index;
1370         unsigned int chksum_ok = 0;
1371
1372         p_index = bcmgenet_rdma_ring_readl(priv, DESC_INDEX, RDMA_PROD_INDEX);
1373         p_index &= DMA_P_INDEX_MASK;
1374
1375         if (p_index < priv->rx_c_index)
1376                 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1377                         priv->rx_c_index + p_index;
1378         else
1379                 rxpkttoprocess = p_index - priv->rx_c_index;
1380
1381         netif_dbg(priv, rx_status, dev,
1382                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1383
1384         while ((rxpktprocessed < rxpkttoprocess) &&
1385                (rxpktprocessed < budget)) {
1386                 cb = &priv->rx_cbs[priv->rx_read_ptr];
1387                 skb = cb->skb;
1388
1389                 /* We do not have a backing SKB, so we do not have a
1390                  * corresponding DMA mapping for this incoming packet since
1391                  * bcmgenet_rx_refill always either has both skb and mapping or
1392                  * none.
1393                  */
1394                 if (unlikely(!skb)) {
1395                         dev->stats.rx_dropped++;
1396                         dev->stats.rx_errors++;
1397                         goto refill;
1398                 }
1399
1400                 /* Unmap the packet contents such that we can use the
1401                  * RSV from the 64 bytes descriptor when enabled and save
1402                  * a 32-bits register read
1403                  */
1404                 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
1405                                  priv->rx_buf_len, DMA_FROM_DEVICE);
1406
1407                 if (!priv->desc_64b_en) {
1408                         dma_length_status =
1409                                 dmadesc_get_length_status(priv,
1410                                                           priv->rx_bds +
1411                                                           (priv->rx_read_ptr *
1412                                                            DMA_DESC_SIZE));
1413                 } else {
1414                         struct status_64 *status;
1415
1416                         status = (struct status_64 *)skb->data;
1417                         dma_length_status = status->length_status;
1418                 }
1419
1420                 /* DMA flags and length are still valid no matter how
1421                  * we got the Receive Status Vector (64B RSB or register)
1422                  */
1423                 dma_flag = dma_length_status & 0xffff;
1424                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1425
1426                 netif_dbg(priv, rx_status, dev,
1427                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1428                           __func__, p_index, priv->rx_c_index,
1429                           priv->rx_read_ptr, dma_length_status);
1430
1431                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1432                         netif_err(priv, rx_status, dev,
1433                                   "dropping fragmented packet!\n");
1434                         dev->stats.rx_dropped++;
1435                         dev->stats.rx_errors++;
1436                         dev_kfree_skb_any(cb->skb);
1437                         cb->skb = NULL;
1438                         goto refill;
1439                 }
1440                 /* report errors */
1441                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1442                                                 DMA_RX_OV |
1443                                                 DMA_RX_NO |
1444                                                 DMA_RX_LG |
1445                                                 DMA_RX_RXER))) {
1446                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1447                                   (unsigned int)dma_flag);
1448                         if (dma_flag & DMA_RX_CRC_ERROR)
1449                                 dev->stats.rx_crc_errors++;
1450                         if (dma_flag & DMA_RX_OV)
1451                                 dev->stats.rx_over_errors++;
1452                         if (dma_flag & DMA_RX_NO)
1453                                 dev->stats.rx_frame_errors++;
1454                         if (dma_flag & DMA_RX_LG)
1455                                 dev->stats.rx_length_errors++;
1456                         dev->stats.rx_dropped++;
1457                         dev->stats.rx_errors++;
1458
1459                         /* discard the packet and advance consumer index.*/
1460                         dev_kfree_skb_any(cb->skb);
1461                         cb->skb = NULL;
1462                         goto refill;
1463                 } /* error packet */
1464
1465                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1466                              priv->desc_rxchk_en;
1467
1468                 skb_put(skb, len);
1469                 if (priv->desc_64b_en) {
1470                         skb_pull(skb, 64);
1471                         len -= 64;
1472                 }
1473
1474                 if (likely(chksum_ok))
1475                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1476
1477                 /* remove hardware 2bytes added for IP alignment */
1478                 skb_pull(skb, 2);
1479                 len -= 2;
1480
1481                 if (priv->crc_fwd_en) {
1482                         skb_trim(skb, len - ETH_FCS_LEN);
1483                         len -= ETH_FCS_LEN;
1484                 }
1485
1486                 /*Finish setting up the received SKB and send it to the kernel*/
1487                 skb->protocol = eth_type_trans(skb, priv->dev);
1488                 dev->stats.rx_packets++;
1489                 dev->stats.rx_bytes += len;
1490                 if (dma_flag & DMA_RX_MULT)
1491                         dev->stats.multicast++;
1492
1493                 /* Notify kernel */
1494                 napi_gro_receive(&priv->napi, skb);
1495                 cb->skb = NULL;
1496                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1497
1498                 /* refill RX path on the current control block */
1499 refill:
1500                 err = bcmgenet_rx_refill(priv, cb);
1501                 if (err) {
1502                         priv->mib.alloc_rx_buff_failed++;
1503                         netif_err(priv, rx_err, dev, "Rx refill failed\n");
1504                 }
1505
1506                 rxpktprocessed++;
1507                 priv->rx_read_ptr++;
1508                 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1509         }
1510
1511         return rxpktprocessed;
1512 }
1513
1514 /* Assign skb to RX DMA descriptor. */
1515 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1516 {
1517         struct enet_cb *cb;
1518         int ret = 0;
1519         int i;
1520
1521         netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1522
1523         /* loop here for each buffer needing assign */
1524         for (i = 0; i < priv->num_rx_bds; i++) {
1525                 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1526                 if (cb->skb)
1527                         continue;
1528
1529                 ret = bcmgenet_rx_refill(priv, cb);
1530                 if (ret)
1531                         break;
1532         }
1533
1534         return ret;
1535 }
1536
1537 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1538 {
1539         struct enet_cb *cb;
1540         int i;
1541
1542         for (i = 0; i < priv->num_rx_bds; i++) {
1543                 cb = &priv->rx_cbs[i];
1544
1545                 if (dma_unmap_addr(cb, dma_addr)) {
1546                         dma_unmap_single(&priv->dev->dev,
1547                                          dma_unmap_addr(cb, dma_addr),
1548                                          priv->rx_buf_len, DMA_FROM_DEVICE);
1549                         dma_unmap_addr_set(cb, dma_addr, 0);
1550                 }
1551
1552                 if (cb->skb)
1553                         bcmgenet_free_cb(cb);
1554         }
1555 }
1556
1557 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1558 {
1559         u32 reg;
1560
1561         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1562         if (enable)
1563                 reg |= mask;
1564         else
1565                 reg &= ~mask;
1566         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1567
1568         /* UniMAC stops on a packet boundary, wait for a full-size packet
1569          * to be processed
1570          */
1571         if (enable == 0)
1572                 usleep_range(1000, 2000);
1573 }
1574
1575 static int reset_umac(struct bcmgenet_priv *priv)
1576 {
1577         struct device *kdev = &priv->pdev->dev;
1578         unsigned int timeout = 0;
1579         u32 reg;
1580
1581         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1582         bcmgenet_rbuf_ctrl_set(priv, 0);
1583         udelay(10);
1584
1585         /* disable MAC while updating its registers */
1586         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1587
1588         /* issue soft reset, wait for it to complete */
1589         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1590         while (timeout++ < 1000) {
1591                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1592                 if (!(reg & CMD_SW_RESET))
1593                         return 0;
1594
1595                 udelay(1);
1596         }
1597
1598         if (timeout == 1000) {
1599                 dev_err(kdev,
1600                         "timeout waiting for MAC to come out of reset\n");
1601                 return -ETIMEDOUT;
1602         }
1603
1604         return 0;
1605 }
1606
1607 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1608 {
1609         /* Mask all interrupts.*/
1610         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1611         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1612         bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1613         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1614         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1615         bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1616 }
1617
1618 static int init_umac(struct bcmgenet_priv *priv)
1619 {
1620         struct device *kdev = &priv->pdev->dev;
1621         int ret;
1622         u32 reg, cpu_mask_clear;
1623
1624         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1625
1626         ret = reset_umac(priv);
1627         if (ret)
1628                 return ret;
1629
1630         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1631         /* clear tx/rx counter */
1632         bcmgenet_umac_writel(priv,
1633                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1634                              UMAC_MIB_CTRL);
1635         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1636
1637         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1638
1639         /* init rx registers, enable ip header optimization */
1640         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1641         reg |= RBUF_ALIGN_2B;
1642         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1643
1644         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1645                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1646
1647         bcmgenet_intr_disable(priv);
1648
1649         cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1650
1651         dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1652
1653         /* Monitor cable plug/unplugged event for internal PHY */
1654         if (phy_is_internal(priv->phydev)) {
1655                 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1656         } else if (priv->ext_phy) {
1657                 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1658         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1659                 reg = bcmgenet_bp_mc_get(priv);
1660                 reg |= BIT(priv->hw_params->bp_in_en_shift);
1661
1662                 /* bp_mask: back pressure mask */
1663                 if (netif_is_multiqueue(priv->dev))
1664                         reg |= priv->hw_params->bp_in_mask;
1665                 else
1666                         reg &= ~priv->hw_params->bp_in_mask;
1667                 bcmgenet_bp_mc_set(priv, reg);
1668         }
1669
1670         /* Enable MDIO interrupts on GENET v3+ */
1671         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1672                 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1673
1674         bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
1675
1676         /* Enable rx/tx engine.*/
1677         dev_dbg(kdev, "done init umac\n");
1678
1679         return 0;
1680 }
1681
1682 /* Initialize all house-keeping variables for a TX ring, along
1683  * with corresponding hardware registers
1684  */
1685 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1686                                   unsigned int index, unsigned int size,
1687                                   unsigned int write_ptr, unsigned int end_ptr)
1688 {
1689         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1690         u32 words_per_bd = WORDS_PER_BD(priv);
1691         u32 flow_period_val = 0;
1692         unsigned int first_bd;
1693
1694         spin_lock_init(&ring->lock);
1695         ring->index = index;
1696         if (index == DESC_INDEX) {
1697                 ring->queue = 0;
1698                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1699                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1700         } else {
1701                 ring->queue = index + 1;
1702                 ring->int_enable = bcmgenet_tx_ring_int_enable;
1703                 ring->int_disable = bcmgenet_tx_ring_int_disable;
1704         }
1705         ring->cbs = priv->tx_cbs + write_ptr;
1706         ring->size = size;
1707         ring->c_index = 0;
1708         ring->free_bds = size;
1709         ring->write_ptr = write_ptr;
1710         ring->cb_ptr = write_ptr;
1711         ring->end_ptr = end_ptr - 1;
1712         ring->prod_index = 0;
1713
1714         /* Set flow period for ring != 16 */
1715         if (index != DESC_INDEX)
1716                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1717
1718         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1719         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1720         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1721         /* Disable rate control for now */
1722         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1723                                   TDMA_FLOW_PERIOD);
1724         /* Unclassified traffic goes to ring 16 */
1725         bcmgenet_tdma_ring_writel(priv, index,
1726                                   ((size << DMA_RING_SIZE_SHIFT) |
1727                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1728
1729         first_bd = write_ptr;
1730
1731         /* Set start and end address, read and write pointers */
1732         bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1733                                   DMA_START_ADDR);
1734         bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1735                                   TDMA_READ_PTR);
1736         bcmgenet_tdma_ring_writel(priv, index, first_bd,
1737                                   TDMA_WRITE_PTR);
1738         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1739                                   DMA_END_ADDR);
1740 }
1741
1742 /* Initialize a RDMA ring */
1743 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1744                                  unsigned int index, unsigned int size)
1745 {
1746         u32 words_per_bd = WORDS_PER_BD(priv);
1747         int ret;
1748
1749         priv->num_rx_bds = TOTAL_DESC;
1750         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1751         priv->rx_bd_assign_ptr = priv->rx_bds;
1752         priv->rx_bd_assign_index = 0;
1753         priv->rx_c_index = 0;
1754         priv->rx_read_ptr = 0;
1755         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
1756                                GFP_KERNEL);
1757         if (!priv->rx_cbs)
1758                 return -ENOMEM;
1759
1760         ret = bcmgenet_alloc_rx_buffers(priv);
1761         if (ret) {
1762                 kfree(priv->rx_cbs);
1763                 return ret;
1764         }
1765
1766         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1767         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1768         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1769         bcmgenet_rdma_ring_writel(priv, index,
1770                                   ((size << DMA_RING_SIZE_SHIFT) |
1771                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1772         bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1773         bcmgenet_rdma_ring_writel(priv, index,
1774                                   words_per_bd * size - 1, DMA_END_ADDR);
1775         bcmgenet_rdma_ring_writel(priv, index,
1776                                   (DMA_FC_THRESH_LO <<
1777                                    DMA_XOFF_THRESHOLD_SHIFT) |
1778                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1779         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1780
1781         return ret;
1782 }
1783
1784 /* init multi xmit queues, only available for GENET2+
1785  * the queue is partitioned as follows:
1786  *
1787  * queue 0 - 3 is priority based, each one has 32 descriptors,
1788  * with queue 0 being the highest priority queue.
1789  *
1790  * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1791  * descriptors: 256 - (number of tx queues * bds per queues) = 128
1792  * descriptors.
1793  *
1794  * The transmit control block pool is then partitioned as following:
1795  * - tx_cbs[0...127] are for queue 16
1796  * - tx_ring_cbs[0] points to tx_cbs[128..159]
1797  * - tx_ring_cbs[1] points to tx_cbs[160..191]
1798  * - tx_ring_cbs[2] points to tx_cbs[192..223]
1799  * - tx_ring_cbs[3] points to tx_cbs[224..255]
1800  */
1801 static void bcmgenet_init_multiq(struct net_device *dev)
1802 {
1803         struct bcmgenet_priv *priv = netdev_priv(dev);
1804         unsigned int i, dma_enable;
1805         u32 reg, dma_ctrl, ring_cfg = 0;
1806         u32 dma_priority[3] = {0, 0, 0};
1807
1808         if (!netif_is_multiqueue(dev)) {
1809                 netdev_warn(dev, "called with non multi queue aware HW\n");
1810                 return;
1811         }
1812
1813         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1814         dma_enable = dma_ctrl & DMA_EN;
1815         dma_ctrl &= ~DMA_EN;
1816         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1817
1818         /* Enable strict priority arbiter mode */
1819         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1820
1821         for (i = 0; i < priv->hw_params->tx_queues; i++) {
1822                 /* first 64 tx_cbs are reserved for default tx queue
1823                  * (ring 16)
1824                  */
1825                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
1826                                       i * priv->hw_params->bds_cnt,
1827                                       (i + 1) * priv->hw_params->bds_cnt);
1828
1829                 /* Configure ring as descriptor ring and setup priority */
1830                 ring_cfg |= 1 << i;
1831                 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1832
1833                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1834                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1835         }
1836
1837         /* Set ring 16 priority and program the hardware registers */
1838         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1839                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1840                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
1841         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1842         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1843         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1844
1845         /* Enable rings */
1846         reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1847         reg |= ring_cfg;
1848         bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1849
1850         /* Configure ring as descriptor ring and re-enable DMA if enabled */
1851         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1852         reg |= dma_ctrl;
1853         if (dma_enable)
1854                 reg |= DMA_EN;
1855         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1856 }
1857
1858 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
1859 {
1860         int ret = 0;
1861         int timeout = 0;
1862         u32 reg;
1863
1864         /* Disable TDMA to stop add more frames in TX DMA */
1865         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1866         reg &= ~DMA_EN;
1867         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1868
1869         /* Check TDMA status register to confirm TDMA is disabled */
1870         while (timeout++ < DMA_TIMEOUT_VAL) {
1871                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
1872                 if (reg & DMA_DISABLED)
1873                         break;
1874
1875                 udelay(1);
1876         }
1877
1878         if (timeout == DMA_TIMEOUT_VAL) {
1879                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
1880                 ret = -ETIMEDOUT;
1881         }
1882
1883         /* Wait 10ms for packet drain in both tx and rx dma */
1884         usleep_range(10000, 20000);
1885
1886         /* Disable RDMA */
1887         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1888         reg &= ~DMA_EN;
1889         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1890
1891         timeout = 0;
1892         /* Check RDMA status register to confirm RDMA is disabled */
1893         while (timeout++ < DMA_TIMEOUT_VAL) {
1894                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
1895                 if (reg & DMA_DISABLED)
1896                         break;
1897
1898                 udelay(1);
1899         }
1900
1901         if (timeout == DMA_TIMEOUT_VAL) {
1902                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
1903                 ret = -ETIMEDOUT;
1904         }
1905
1906         return ret;
1907 }
1908
1909 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1910 {
1911         int i;
1912
1913         /* disable DMA */
1914         bcmgenet_dma_teardown(priv);
1915
1916         for (i = 0; i < priv->num_tx_bds; i++) {
1917                 if (priv->tx_cbs[i].skb != NULL) {
1918                         dev_kfree_skb(priv->tx_cbs[i].skb);
1919                         priv->tx_cbs[i].skb = NULL;
1920                 }
1921         }
1922
1923         bcmgenet_free_rx_buffers(priv);
1924         kfree(priv->rx_cbs);
1925         kfree(priv->tx_cbs);
1926 }
1927
1928 /* init_edma: Initialize DMA control register */
1929 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1930 {
1931         int ret;
1932
1933         netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1934
1935         /* by default, enable ring 16 (descriptor based) */
1936         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1937         if (ret) {
1938                 netdev_err(priv->dev, "failed to initialize RX ring\n");
1939                 return ret;
1940         }
1941
1942         /* init rDma */
1943         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1944
1945         /* Init tDma */
1946         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1947
1948         /* Initialize common TX ring structures */
1949         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1950         priv->num_tx_bds = TOTAL_DESC;
1951         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
1952                                GFP_KERNEL);
1953         if (!priv->tx_cbs) {
1954                 bcmgenet_fini_dma(priv);
1955                 return -ENOMEM;
1956         }
1957
1958         /* initialize multi xmit queue */
1959         bcmgenet_init_multiq(priv->dev);
1960
1961         /* initialize special ring 16 */
1962         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
1963                               priv->hw_params->tx_queues *
1964                               priv->hw_params->bds_cnt,
1965                               TOTAL_DESC);
1966
1967         return 0;
1968 }
1969
1970 /* NAPI polling method*/
1971 static int bcmgenet_poll(struct napi_struct *napi, int budget)
1972 {
1973         struct bcmgenet_priv *priv = container_of(napi,
1974                         struct bcmgenet_priv, napi);
1975         unsigned int work_done;
1976
1977         /* tx reclaim */
1978         bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1979
1980         work_done = bcmgenet_desc_rx(priv, budget);
1981
1982         /* Advancing our consumer index*/
1983         priv->rx_c_index += work_done;
1984         priv->rx_c_index &= DMA_C_INDEX_MASK;
1985         bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
1986                                   priv->rx_c_index, RDMA_CONS_INDEX);
1987         if (work_done < budget) {
1988                 napi_complete(napi);
1989                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
1990                                          INTRL2_CPU_MASK_CLEAR);
1991         }
1992
1993         return work_done;
1994 }
1995
1996 /* Interrupt bottom half */
1997 static void bcmgenet_irq_task(struct work_struct *work)
1998 {
1999         struct bcmgenet_priv *priv = container_of(
2000                         work, struct bcmgenet_priv, bcmgenet_irq_work);
2001
2002         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2003
2004         if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2005                 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2006                 netif_dbg(priv, wol, priv->dev,
2007                           "magic packet detected, waking up\n");
2008                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2009         }
2010
2011         /* Link UP/DOWN event */
2012         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2013             (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
2014                 phy_mac_interrupt(priv->phydev,
2015                                   priv->irq0_stat & UMAC_IRQ_LINK_UP);
2016                 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
2017         }
2018 }
2019
2020 /* bcmgenet_isr1: interrupt handler for ring buffer. */
2021 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2022 {
2023         struct bcmgenet_priv *priv = dev_id;
2024         unsigned int index;
2025
2026         /* Save irq status for bottom-half processing. */
2027         priv->irq1_stat =
2028                 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2029                 ~priv->int1_mask;
2030         /* clear interrupts */
2031         bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2032
2033         netif_dbg(priv, intr, priv->dev,
2034                   "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
2035         /* Check the MBDONE interrupts.
2036          * packet is done, reclaim descriptors
2037          */
2038         if (priv->irq1_stat & 0x0000ffff) {
2039                 index = 0;
2040                 for (index = 0; index < 16; index++) {
2041                         if (priv->irq1_stat & (1 << index))
2042                                 bcmgenet_tx_reclaim(priv->dev,
2043                                                     &priv->tx_rings[index]);
2044                 }
2045         }
2046         return IRQ_HANDLED;
2047 }
2048
2049 /* bcmgenet_isr0: Handle various interrupts. */
2050 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2051 {
2052         struct bcmgenet_priv *priv = dev_id;
2053
2054         /* Save irq status for bottom-half processing. */
2055         priv->irq0_stat =
2056                 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2057                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2058         /* clear interrupts */
2059         bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2060
2061         netif_dbg(priv, intr, priv->dev,
2062                   "IRQ=0x%x\n", priv->irq0_stat);
2063
2064         if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
2065                 /* We use NAPI(software interrupt throttling, if
2066                  * Rx Descriptor throttling is not used.
2067                  * Disable interrupt, will be enabled in the poll method.
2068                  */
2069                 if (likely(napi_schedule_prep(&priv->napi))) {
2070                         bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2071                                                  INTRL2_CPU_MASK_SET);
2072                         __napi_schedule(&priv->napi);
2073                 }
2074         }
2075         if (priv->irq0_stat &
2076                         (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
2077                 /* Tx reclaim */
2078                 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
2079         }
2080         if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2081                                 UMAC_IRQ_PHY_DET_F |
2082                                 UMAC_IRQ_LINK_UP |
2083                                 UMAC_IRQ_LINK_DOWN |
2084                                 UMAC_IRQ_HFB_SM |
2085                                 UMAC_IRQ_HFB_MM |
2086                                 UMAC_IRQ_MPD_R)) {
2087                 /* all other interested interrupts handled in bottom half */
2088                 schedule_work(&priv->bcmgenet_irq_work);
2089         }
2090
2091         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2092             priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2093                 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2094                 wake_up(&priv->wq);
2095         }
2096
2097         return IRQ_HANDLED;
2098 }
2099
2100 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2101 {
2102         struct bcmgenet_priv *priv = dev_id;
2103
2104         pm_wakeup_event(&priv->pdev->dev, 0);
2105
2106         return IRQ_HANDLED;
2107 }
2108
2109 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2110 {
2111         u32 reg;
2112
2113         reg = bcmgenet_rbuf_ctrl_get(priv);
2114         reg |= BIT(1);
2115         bcmgenet_rbuf_ctrl_set(priv, reg);
2116         udelay(10);
2117
2118         reg &= ~BIT(1);
2119         bcmgenet_rbuf_ctrl_set(priv, reg);
2120         udelay(10);
2121 }
2122
2123 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2124                                  unsigned char *addr)
2125 {
2126         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2127                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2128         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2129 }
2130
2131 /* Returns a reusable dma control register value */
2132 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2133 {
2134         u32 reg;
2135         u32 dma_ctrl;
2136
2137         /* disable DMA */
2138         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2139         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2140         reg &= ~dma_ctrl;
2141         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2142
2143         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2144         reg &= ~dma_ctrl;
2145         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2146
2147         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2148         udelay(10);
2149         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2150
2151         return dma_ctrl;
2152 }
2153
2154 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2155 {
2156         u32 reg;
2157
2158         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2159         reg |= dma_ctrl;
2160         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2161
2162         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2163         reg |= dma_ctrl;
2164         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2165 }
2166
2167 static void bcmgenet_netif_start(struct net_device *dev)
2168 {
2169         struct bcmgenet_priv *priv = netdev_priv(dev);
2170
2171         /* Start the network engine */
2172         napi_enable(&priv->napi);
2173
2174         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2175
2176         if (phy_is_internal(priv->phydev))
2177                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2178
2179         netif_tx_start_all_queues(dev);
2180
2181         phy_start(priv->phydev);
2182 }
2183
2184 static int bcmgenet_open(struct net_device *dev)
2185 {
2186         struct bcmgenet_priv *priv = netdev_priv(dev);
2187         unsigned long dma_ctrl;
2188         u32 reg;
2189         int ret;
2190
2191         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2192
2193         /* Turn on the clock */
2194         if (!IS_ERR(priv->clk))
2195                 clk_prepare_enable(priv->clk);
2196
2197         /* take MAC out of reset */
2198         bcmgenet_umac_reset(priv);
2199
2200         ret = init_umac(priv);
2201         if (ret)
2202                 goto err_clk_disable;
2203
2204         /* disable ethernet MAC while updating its registers */
2205         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2206
2207         /* Make sure we reflect the value of CRC_CMD_FWD */
2208         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2209         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2210
2211         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2212
2213         if (phy_is_internal(priv->phydev)) {
2214                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2215                 reg |= EXT_ENERGY_DET_MASK;
2216                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2217         }
2218
2219         /* Disable RX/TX DMA and flush TX queues */
2220         dma_ctrl = bcmgenet_dma_disable(priv);
2221
2222         /* Reinitialize TDMA and RDMA and SW housekeeping */
2223         ret = bcmgenet_init_dma(priv);
2224         if (ret) {
2225                 netdev_err(dev, "failed to initialize DMA\n");
2226                 goto err_fini_dma;
2227         }
2228
2229         /* Always enable ring 16 - descriptor ring */
2230         bcmgenet_enable_dma(priv, dma_ctrl);
2231
2232         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2233                           dev->name, priv);
2234         if (ret < 0) {
2235                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2236                 goto err_fini_dma;
2237         }
2238
2239         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2240                           dev->name, priv);
2241         if (ret < 0) {
2242                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2243                 goto err_irq0;
2244         }
2245
2246         /* Re-configure the port multiplexer towards the PHY device */
2247         bcmgenet_mii_config(priv->dev, false);
2248
2249         phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2250                            priv->phy_interface);
2251
2252         bcmgenet_netif_start(dev);
2253
2254         return 0;
2255
2256 err_irq0:
2257         free_irq(priv->irq0, dev);
2258 err_fini_dma:
2259         bcmgenet_fini_dma(priv);
2260 err_clk_disable:
2261         if (!IS_ERR(priv->clk))
2262                 clk_disable_unprepare(priv->clk);
2263         return ret;
2264 }
2265
2266 static void bcmgenet_netif_stop(struct net_device *dev)
2267 {
2268         struct bcmgenet_priv *priv = netdev_priv(dev);
2269
2270         netif_tx_stop_all_queues(dev);
2271         napi_disable(&priv->napi);
2272         phy_stop(priv->phydev);
2273
2274         bcmgenet_intr_disable(priv);
2275
2276         /* Wait for pending work items to complete. Since interrupts are
2277          * disabled no new work will be scheduled.
2278          */
2279         cancel_work_sync(&priv->bcmgenet_irq_work);
2280
2281         priv->old_link = -1;
2282         priv->old_speed = -1;
2283         priv->old_duplex = -1;
2284         priv->old_pause = -1;
2285 }
2286
2287 static int bcmgenet_close(struct net_device *dev)
2288 {
2289         struct bcmgenet_priv *priv = netdev_priv(dev);
2290         int ret;
2291
2292         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2293
2294         bcmgenet_netif_stop(dev);
2295
2296         /* Really kill the PHY state machine and disconnect from it */
2297         phy_disconnect(priv->phydev);
2298
2299         /* Disable MAC receive */
2300         umac_enable_set(priv, CMD_RX_EN, false);
2301
2302         ret = bcmgenet_dma_teardown(priv);
2303         if (ret)
2304                 return ret;
2305
2306         /* Disable MAC transmit. TX DMA disabled have to done before this */
2307         umac_enable_set(priv, CMD_TX_EN, false);
2308
2309         /* tx reclaim */
2310         bcmgenet_tx_reclaim_all(dev);
2311         bcmgenet_fini_dma(priv);
2312
2313         free_irq(priv->irq0, priv);
2314         free_irq(priv->irq1, priv);
2315
2316         if (phy_is_internal(priv->phydev))
2317                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2318
2319         if (!IS_ERR(priv->clk))
2320                 clk_disable_unprepare(priv->clk);
2321
2322         return 0;
2323 }
2324
2325 static void bcmgenet_timeout(struct net_device *dev)
2326 {
2327         struct bcmgenet_priv *priv = netdev_priv(dev);
2328
2329         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2330
2331         dev->trans_start = jiffies;
2332
2333         dev->stats.tx_errors++;
2334
2335         netif_tx_wake_all_queues(dev);
2336 }
2337
2338 #define MAX_MC_COUNT    16
2339
2340 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2341                                          unsigned char *addr,
2342                                          int *i,
2343                                          int *mc)
2344 {
2345         u32 reg;
2346
2347         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2348                              UMAC_MDF_ADDR + (*i * 4));
2349         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2350                              addr[4] << 8 | addr[5],
2351                              UMAC_MDF_ADDR + ((*i + 1) * 4));
2352         reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2353         reg |= (1 << (MAX_MC_COUNT - *mc));
2354         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2355         *i += 2;
2356         (*mc)++;
2357 }
2358
2359 static void bcmgenet_set_rx_mode(struct net_device *dev)
2360 {
2361         struct bcmgenet_priv *priv = netdev_priv(dev);
2362         struct netdev_hw_addr *ha;
2363         int i, mc;
2364         u32 reg;
2365
2366         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2367
2368         /* Promiscuous mode */
2369         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2370         if (dev->flags & IFF_PROMISC) {
2371                 reg |= CMD_PROMISC;
2372                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2373                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2374                 return;
2375         } else {
2376                 reg &= ~CMD_PROMISC;
2377                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2378         }
2379
2380         /* UniMac doesn't support ALLMULTI */
2381         if (dev->flags & IFF_ALLMULTI) {
2382                 netdev_warn(dev, "ALLMULTI is not supported\n");
2383                 return;
2384         }
2385
2386         /* update MDF filter */
2387         i = 0;
2388         mc = 0;
2389         /* Broadcast */
2390         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2391         /* my own address.*/
2392         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2393         /* Unicast list*/
2394         if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2395                 return;
2396
2397         if (!netdev_uc_empty(dev))
2398                 netdev_for_each_uc_addr(ha, dev)
2399                         bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2400         /* Multicast */
2401         if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2402                 return;
2403
2404         netdev_for_each_mc_addr(ha, dev)
2405                 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2406 }
2407
2408 /* Set the hardware MAC address. */
2409 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2410 {
2411         struct sockaddr *addr = p;
2412
2413         /* Setting the MAC address at the hardware level is not possible
2414          * without disabling the UniMAC RX/TX enable bits.
2415          */
2416         if (netif_running(dev))
2417                 return -EBUSY;
2418
2419         ether_addr_copy(dev->dev_addr, addr->sa_data);
2420
2421         return 0;
2422 }
2423
2424 static const struct net_device_ops bcmgenet_netdev_ops = {
2425         .ndo_open               = bcmgenet_open,
2426         .ndo_stop               = bcmgenet_close,
2427         .ndo_start_xmit         = bcmgenet_xmit,
2428         .ndo_tx_timeout         = bcmgenet_timeout,
2429         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
2430         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
2431         .ndo_do_ioctl           = bcmgenet_ioctl,
2432         .ndo_set_features       = bcmgenet_set_features,
2433 };
2434
2435 /* Array of GENET hardware parameters/characteristics */
2436 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2437         [GENET_V1] = {
2438                 .tx_queues = 0,
2439                 .rx_queues = 0,
2440                 .bds_cnt = 0,
2441                 .bp_in_en_shift = 16,
2442                 .bp_in_mask = 0xffff,
2443                 .hfb_filter_cnt = 16,
2444                 .qtag_mask = 0x1F,
2445                 .hfb_offset = 0x1000,
2446                 .rdma_offset = 0x2000,
2447                 .tdma_offset = 0x3000,
2448                 .words_per_bd = 2,
2449         },
2450         [GENET_V2] = {
2451                 .tx_queues = 4,
2452                 .rx_queues = 4,
2453                 .bds_cnt = 32,
2454                 .bp_in_en_shift = 16,
2455                 .bp_in_mask = 0xffff,
2456                 .hfb_filter_cnt = 16,
2457                 .qtag_mask = 0x1F,
2458                 .tbuf_offset = 0x0600,
2459                 .hfb_offset = 0x1000,
2460                 .hfb_reg_offset = 0x2000,
2461                 .rdma_offset = 0x3000,
2462                 .tdma_offset = 0x4000,
2463                 .words_per_bd = 2,
2464                 .flags = GENET_HAS_EXT,
2465         },
2466         [GENET_V3] = {
2467                 .tx_queues = 4,
2468                 .rx_queues = 4,
2469                 .bds_cnt = 32,
2470                 .bp_in_en_shift = 17,
2471                 .bp_in_mask = 0x1ffff,
2472                 .hfb_filter_cnt = 48,
2473                 .qtag_mask = 0x3F,
2474                 .tbuf_offset = 0x0600,
2475                 .hfb_offset = 0x8000,
2476                 .hfb_reg_offset = 0xfc00,
2477                 .rdma_offset = 0x10000,
2478                 .tdma_offset = 0x11000,
2479                 .words_per_bd = 2,
2480                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2481         },
2482         [GENET_V4] = {
2483                 .tx_queues = 4,
2484                 .rx_queues = 4,
2485                 .bds_cnt = 32,
2486                 .bp_in_en_shift = 17,
2487                 .bp_in_mask = 0x1ffff,
2488                 .hfb_filter_cnt = 48,
2489                 .qtag_mask = 0x3F,
2490                 .tbuf_offset = 0x0600,
2491                 .hfb_offset = 0x8000,
2492                 .hfb_reg_offset = 0xfc00,
2493                 .rdma_offset = 0x2000,
2494                 .tdma_offset = 0x4000,
2495                 .words_per_bd = 3,
2496                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2497         },
2498 };
2499
2500 /* Infer hardware parameters from the detected GENET version */
2501 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2502 {
2503         struct bcmgenet_hw_params *params;
2504         u32 reg;
2505         u8 major;
2506
2507         if (GENET_IS_V4(priv)) {
2508                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2509                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2510                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2511                 priv->version = GENET_V4;
2512         } else if (GENET_IS_V3(priv)) {
2513                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2514                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2515                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2516                 priv->version = GENET_V3;
2517         } else if (GENET_IS_V2(priv)) {
2518                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2519                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2520                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2521                 priv->version = GENET_V2;
2522         } else if (GENET_IS_V1(priv)) {
2523                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2524                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2525                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2526                 priv->version = GENET_V1;
2527         }
2528
2529         /* enum genet_version starts at 1 */
2530         priv->hw_params = &bcmgenet_hw_params[priv->version];
2531         params = priv->hw_params;
2532
2533         /* Read GENET HW version */
2534         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2535         major = (reg >> 24 & 0x0f);
2536         if (major == 5)
2537                 major = 4;
2538         else if (major == 0)
2539                 major = 1;
2540         if (major != priv->version) {
2541                 dev_err(&priv->pdev->dev,
2542                         "GENET version mismatch, got: %d, configured for: %d\n",
2543                         major, priv->version);
2544         }
2545
2546         /* Print the GENET core version */
2547         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
2548                  major, (reg >> 16) & 0x0f, reg & 0xffff);
2549
2550         /* Store the integrated PHY revision for the MDIO probing function
2551          * to pass this information to the PHY driver. The PHY driver expects
2552          * to find the PHY major revision in bits 15:8 while the GENET register
2553          * stores that information in bits 7:0, account for that.
2554          */
2555         priv->gphy_rev = (reg & 0xffff) << 8;
2556
2557 #ifdef CONFIG_PHYS_ADDR_T_64BIT
2558         if (!(params->flags & GENET_HAS_40BITS))
2559                 pr_warn("GENET does not support 40-bits PA\n");
2560 #endif
2561
2562         pr_debug("Configuration for version: %d\n"
2563                 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2564                 "BP << en: %2d, BP msk: 0x%05x\n"
2565                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2566                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2567                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2568                 "Words/BD: %d\n",
2569                 priv->version,
2570                 params->tx_queues, params->rx_queues, params->bds_cnt,
2571                 params->bp_in_en_shift, params->bp_in_mask,
2572                 params->hfb_filter_cnt, params->qtag_mask,
2573                 params->tbuf_offset, params->hfb_offset,
2574                 params->hfb_reg_offset,
2575                 params->rdma_offset, params->tdma_offset,
2576                 params->words_per_bd);
2577 }
2578
2579 static const struct of_device_id bcmgenet_match[] = {
2580         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2581         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2582         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2583         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2584         { },
2585 };
2586
2587 static int bcmgenet_probe(struct platform_device *pdev)
2588 {
2589         struct device_node *dn = pdev->dev.of_node;
2590         const struct of_device_id *of_id;
2591         struct bcmgenet_priv *priv;
2592         struct net_device *dev;
2593         const void *macaddr;
2594         struct resource *r;
2595         int err = -EIO;
2596
2597         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2598         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2599         if (!dev) {
2600                 dev_err(&pdev->dev, "can't allocate net device\n");
2601                 return -ENOMEM;
2602         }
2603
2604         of_id = of_match_node(bcmgenet_match, dn);
2605         if (!of_id)
2606                 return -EINVAL;
2607
2608         priv = netdev_priv(dev);
2609         priv->irq0 = platform_get_irq(pdev, 0);
2610         priv->irq1 = platform_get_irq(pdev, 1);
2611         priv->wol_irq = platform_get_irq(pdev, 2);
2612         if (!priv->irq0 || !priv->irq1) {
2613                 dev_err(&pdev->dev, "can't find IRQs\n");
2614                 err = -EINVAL;
2615                 goto err;
2616         }
2617
2618         macaddr = of_get_mac_address(dn);
2619         if (!macaddr) {
2620                 dev_err(&pdev->dev, "can't find MAC address\n");
2621                 err = -EINVAL;
2622                 goto err;
2623         }
2624
2625         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2626         priv->base = devm_ioremap_resource(&pdev->dev, r);
2627         if (IS_ERR(priv->base)) {
2628                 err = PTR_ERR(priv->base);
2629                 goto err;
2630         }
2631
2632         SET_NETDEV_DEV(dev, &pdev->dev);
2633         dev_set_drvdata(&pdev->dev, dev);
2634         ether_addr_copy(dev->dev_addr, macaddr);
2635         dev->watchdog_timeo = 2 * HZ;
2636         dev->ethtool_ops = &bcmgenet_ethtool_ops;
2637         dev->netdev_ops = &bcmgenet_netdev_ops;
2638         netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2639
2640         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2641
2642         /* Set hardware features */
2643         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2644                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2645
2646         /* Request the WOL interrupt and advertise suspend if available */
2647         priv->wol_irq_disabled = true;
2648         err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2649                                dev->name, priv);
2650         if (!err)
2651                 device_set_wakeup_capable(&pdev->dev, 1);
2652
2653         /* Set the needed headroom to account for any possible
2654          * features enabling/disabling at runtime
2655          */
2656         dev->needed_headroom += 64;
2657
2658         netdev_boot_setup_check(dev);
2659
2660         priv->dev = dev;
2661         priv->pdev = pdev;
2662         priv->version = (enum bcmgenet_version)of_id->data;
2663
2664         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2665         if (IS_ERR(priv->clk))
2666                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2667
2668         if (!IS_ERR(priv->clk))
2669                 clk_prepare_enable(priv->clk);
2670
2671         bcmgenet_set_hw_params(priv);
2672
2673         /* Mii wait queue */
2674         init_waitqueue_head(&priv->wq);
2675         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2676         priv->rx_buf_len = RX_BUF_LENGTH;
2677         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2678
2679         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2680         if (IS_ERR(priv->clk_wol))
2681                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2682
2683         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
2684         if (IS_ERR(priv->clk_eee)) {
2685                 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
2686                 priv->clk_eee = NULL;
2687         }
2688
2689         err = reset_umac(priv);
2690         if (err)
2691                 goto err_clk_disable;
2692
2693         err = bcmgenet_mii_init(dev);
2694         if (err)
2695                 goto err_clk_disable;
2696
2697         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
2698          * just the ring 16 descriptor based TX
2699          */
2700         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2701         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2702
2703         /* libphy will determine the link state */
2704         netif_carrier_off(dev);
2705
2706         /* Turn off the main clock, WOL clock is handled separately */
2707         if (!IS_ERR(priv->clk))
2708                 clk_disable_unprepare(priv->clk);
2709
2710         err = register_netdev(dev);
2711         if (err)
2712                 goto err;
2713
2714         return err;
2715
2716 err_clk_disable:
2717         if (!IS_ERR(priv->clk))
2718                 clk_disable_unprepare(priv->clk);
2719 err:
2720         free_netdev(dev);
2721         return err;
2722 }
2723
2724 static int bcmgenet_remove(struct platform_device *pdev)
2725 {
2726         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2727
2728         dev_set_drvdata(&pdev->dev, NULL);
2729         unregister_netdev(priv->dev);
2730         bcmgenet_mii_exit(priv->dev);
2731         free_netdev(priv->dev);
2732
2733         return 0;
2734 }
2735
2736 #ifdef CONFIG_PM_SLEEP
2737 static int bcmgenet_suspend(struct device *d)
2738 {
2739         struct net_device *dev = dev_get_drvdata(d);
2740         struct bcmgenet_priv *priv = netdev_priv(dev);
2741         int ret;
2742
2743         if (!netif_running(dev))
2744                 return 0;
2745
2746         bcmgenet_netif_stop(dev);
2747
2748         phy_suspend(priv->phydev);
2749
2750         netif_device_detach(dev);
2751
2752         /* Disable MAC receive */
2753         umac_enable_set(priv, CMD_RX_EN, false);
2754
2755         ret = bcmgenet_dma_teardown(priv);
2756         if (ret)
2757                 return ret;
2758
2759         /* Disable MAC transmit. TX DMA disabled have to done before this */
2760         umac_enable_set(priv, CMD_TX_EN, false);
2761
2762         /* tx reclaim */
2763         bcmgenet_tx_reclaim_all(dev);
2764         bcmgenet_fini_dma(priv);
2765
2766         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2767         if (device_may_wakeup(d) && priv->wolopts) {
2768                 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2769                 clk_prepare_enable(priv->clk_wol);
2770         }
2771
2772         /* Turn off the clocks */
2773         clk_disable_unprepare(priv->clk);
2774
2775         return 0;
2776 }
2777
2778 static int bcmgenet_resume(struct device *d)
2779 {
2780         struct net_device *dev = dev_get_drvdata(d);
2781         struct bcmgenet_priv *priv = netdev_priv(dev);
2782         unsigned long dma_ctrl;
2783         int ret;
2784         u32 reg;
2785
2786         if (!netif_running(dev))
2787                 return 0;
2788
2789         /* Turn on the clock */
2790         ret = clk_prepare_enable(priv->clk);
2791         if (ret)
2792                 return ret;
2793
2794         bcmgenet_umac_reset(priv);
2795
2796         ret = init_umac(priv);
2797         if (ret)
2798                 goto out_clk_disable;
2799
2800         /* From WOL-enabled suspend, switch to regular clock */
2801         if (priv->wolopts)
2802                 clk_disable_unprepare(priv->clk_wol);
2803
2804         phy_init_hw(priv->phydev);
2805         /* Speed settings must be restored */
2806         bcmgenet_mii_config(priv->dev, false);
2807
2808         /* disable ethernet MAC while updating its registers */
2809         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2810
2811         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2812
2813         if (phy_is_internal(priv->phydev)) {
2814                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2815                 reg |= EXT_ENERGY_DET_MASK;
2816                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2817         }
2818
2819         if (priv->wolopts)
2820                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2821
2822         /* Disable RX/TX DMA and flush TX queues */
2823         dma_ctrl = bcmgenet_dma_disable(priv);
2824
2825         /* Reinitialize TDMA and RDMA and SW housekeeping */
2826         ret = bcmgenet_init_dma(priv);
2827         if (ret) {
2828                 netdev_err(dev, "failed to initialize DMA\n");
2829                 goto out_clk_disable;
2830         }
2831
2832         /* Always enable ring 16 - descriptor ring */
2833         bcmgenet_enable_dma(priv, dma_ctrl);
2834
2835         netif_device_attach(dev);
2836
2837         phy_resume(priv->phydev);
2838
2839         if (priv->eee.eee_enabled)
2840                 bcmgenet_eee_enable_set(dev, true);
2841
2842         bcmgenet_netif_start(dev);
2843
2844         return 0;
2845
2846 out_clk_disable:
2847         clk_disable_unprepare(priv->clk);
2848         return ret;
2849 }
2850 #endif /* CONFIG_PM_SLEEP */
2851
2852 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
2853
2854 static struct platform_driver bcmgenet_driver = {
2855         .probe  = bcmgenet_probe,
2856         .remove = bcmgenet_remove,
2857         .driver = {
2858                 .name   = "bcmgenet",
2859                 .owner  = THIS_MODULE,
2860                 .of_match_table = bcmgenet_match,
2861                 .pm     = &bcmgenet_pm_ops,
2862         },
2863 };
2864 module_platform_driver(bcmgenet_driver);
2865
2866 MODULE_AUTHOR("Broadcom Corporation");
2867 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2868 MODULE_ALIAS("platform:bcmgenet");
2869 MODULE_LICENSE("GPL");